WO2019184321A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2019184321A1
WO2019184321A1 PCT/CN2018/111631 CN2018111631W WO2019184321A1 WO 2019184321 A1 WO2019184321 A1 WO 2019184321A1 CN 2018111631 W CN2018111631 W CN 2018111631W WO 2019184321 A1 WO2019184321 A1 WO 2019184321A1
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Prior art keywords
electrode plate
tft
electrode
array substrate
layer
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PCT/CN2018/111631
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English (en)
French (fr)
Inventor
程鸿飞
张玉欣
郝学光
马永达
卢永春
李会
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to US16/475,335 priority Critical patent/US11094766B2/en
Priority to KR1020197015432A priority patent/KR102201052B1/ko
Priority to JP2019528880A priority patent/JP7024937B2/ja
Priority to EP18893327.9A priority patent/EP3780107B1/en
Publication of WO2019184321A1 publication Critical patent/WO2019184321A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/805—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/302—Details of OLEDs of OLED structures

Definitions

  • the present disclosure relates to the field of display technologies, for example, to an array substrate, a display panel, and a display device.
  • OLED Organic Light Emitting Diodes
  • QLED Quantum dots Light-emitting Diodes
  • OLED Organic Light Emitting Diodes
  • QLED Quantum dots Light-emitting Diodes
  • An array substrate comprising a plurality of pixel units, wherein each pixel unit comprises a storage capacitor, the storage capacitor comprises at least three mutually parallel electrode plates, and the at least three mutually parallel electrode plates comprise a first electrode plate, a second electrode plate and a third electrode plate, the first electrode plate is electrically connected to the second electrode plate, and the third electrode plate is disposed between the first electrode plate and the second electrode plate, And the first electrode plate and the second electrode plate respectively have opposite portions with the third electrode plate.
  • At least one of the first electrode plate and the second electrode plate is bent in a direction opposite to the third electrode plate.
  • the at least three mutually parallel electrode plates further include a fourth electrode plate, the fourth electrode plate is electrically connected to the first electrode plate, and the fourth electrode plate is disposed on the first electrode plate Between an electrode plate and the third electrode plate, the fourth electrode plate and the third electrode plate have opposite portions.
  • each of the pixel units includes an active layer sequentially disposed on the substrate, a gate insulating layer, a gate of the first thin film transistor TFT, an interlayer insulating layer, and a source of the first TFT disposed in the same layer. a drain and a drain of the first TFT, a passivation layer, and a pixel electrode;
  • a drain of the first TFT is electrically connected to the pixel electrode through a first via hole penetrating the passivation layer; the active layer is integrated with the first electrode plate; and the pixel electrode is
  • the second electrode plate is a unitary structure.
  • the array substrate, wherein the third electrode plate is disposed in the same layer as the drain of the first TFT.
  • the array substrate further includes a second TFT, a data line, and a gate line, a source of the second TFT is connected to the data line, a gate of the second TFT, and the gate a line connection, and a source of the second TFT, a drain of the second TFT, a source of the first TFT, and a drain of the first TFT are disposed in the same layer, and a gate of the second TFT The pole is disposed in the same layer as the gate of the first TFT; wherein a drain of the second TFT and a gate of the first TFT are electrically connected by a third via extending through the interlayer insulating layer.
  • the at least three mutually parallel electrode plates further comprise a fourth electrode plate electrically connected to the first electrode plate
  • the fourth electrode plate and the third electrode plate are opposite each other
  • the fourth electrode plate is disposed in the same layer as the gate of the first TFT.
  • the fourth electrode plate and the first electrode plate are electrically connected by a fourth via hole penetrating the gate insulating layer.
  • a flat layer is disposed between the passivation layer and the pixel electrode, and a portion of the flat layer facing the third electrode plate is provided with a groove, and the second electrode plate is deposited. On the flat layer, the second electrode plate forms a bend at the groove; and/or,
  • a portion of the substrate opposite to the third electrode plate is provided with a protrusion, and the first electrode plate is deposited on the substrate, and the first electrode plate is bent at the protrusion.
  • the array substrate further includes an anode, a cathode, and a light emitting layer disposed between the anode and the cathode, wherein the pixel electrode is the anode, and each pixel unit is disposed on one side There is the light emitting layer, and the light emitting layer is an organic light emitting layer or a quantum dot light emitting layer.
  • a display panel includes the array substrate of any of the above.
  • a display device includes the display panel as described above.
  • FIG. 1 is a schematic structural view of a driving circuit of a pixel unit in an OLED display
  • FIG. 2 is a schematic plan view showing the structure of an array substrate provided by some embodiments.
  • 3A is a cross-sectional view of the array substrate taken along line AA' of FIG. 2, provided by some embodiments;
  • 3B is a cross-sectional view of the array substrate taken along line BB' of FIG. 2, provided by some embodiments;
  • 3C is a cross-sectional view of the array substrate taken along line CC' of FIG. 2, provided by some embodiments;
  • FIG. 4 is a cross-sectional view of the array substrate taken along line AA' of FIG. 2 provided by other embodiments;
  • FIG. 5 is a schematic diagram showing the planar structure of an array substrate provided by other embodiments.
  • Figure 6 is a cross-sectional view of the array substrate taken along line DD' of Figure 5, provided by some embodiments.
  • FIG. 1 is a schematic structural diagram of a driving circuit of a pixel unit in an OLED display.
  • the driving circuit includes a Thin Film Transistor (TFT) T1 for driving an OLED, a thin film transistor T2 provided as a switch-controlled OLED, and a storage capacitor C.
  • TFT Thin Film Transistor
  • the gate of the thin film transistor T2 (also referred to as a switching TFT) is connected to a gate line G1
  • the source of the thin film transistor T2 is connected to a data line D1
  • the drain of the thin film transistor T2 is connected to a thin film transistor T1 (also known as the gate of the driving TFT).
  • the source of the thin film transistor T1 is connected to the power supply line V dd
  • the drain of the thin film transistor T1 is connected to the pixel electrode (the anode of the organic light emitting diode (OLED) OL1).
  • the first electrode C1 of the storage capacitor C is connected to the drain of the thin film transistor T2 and the gate of the thin film transistor T1, and the second electrode C2 of the storage capacitor C is connected to the drain of the thin film transistor T1 and the anode of the OL1.
  • the capacitance value of the capacitor C becomes a method for improving the stability of the display screen.
  • the capacitance value of the storage capacitor C increases, and it is usually required to increase the facing area of the two electrodes of the storage capacitor, but the method increases the capacitance value under the condition that the display area (the area of the display area of the display panel) is limited. The effect is limited.
  • Some embodiments provide an array substrate, the array substrate includes a plurality of pixel units, wherein each of the pixel units is respectively provided with a storage capacitor, and the storage capacitor includes at least three electrode plates parallel to each other, the at least three The mutually parallel electrode plates comprise a first electrode plate, a second electrode plate and a third electrode plate, wherein the first electrode plate is electrically connected to the second electrode plate, and the third electrode plate is disposed on the Between the first electrode plate and the second electrode plate, and the first electrode plate and the third electrode plate have opposite portions, and the second electrode plate and the third electrode plate have The right part.
  • the storage capacitor of the pixel circuit includes at least three mutually parallel electrode plates, and the third electrode plate disposed between the first electrode plate and the second electrode plate and the first electrode plate respectively Facing the second electrode plate, it is configured as a storage capacitor.
  • the number of electrode plates of the storage capacitor is increased without increasing the occupied area of the storage capacitor. The distance increases the overall capacitance of the storage capacitor.
  • FIG. 2 is a schematic diagram showing the planar structure of an array substrate provided by some embodiments.
  • 3A is a cross-sectional view of the array substrate taken along line AA' of FIG. 2, provided by some embodiments.
  • the array substrate includes a plurality of pixel units 100, each of which includes a first TFT 110, a second TFT 120, a pixel electrode 130, and a storage capacitor.
  • the pixel electrode 130 is the anode of the OLED.
  • the array substrate further includes a gate line 101, a data line 102, and a power line (V dd ) 103.
  • the gate of the second TFT 120 is connected to the gate line 101, the source of the second TFT 120 is connected to the data line 102, and the drain of the second TFT 120 is connected to the gate of the first TFT 110.
  • the source of the first TFT 110 is connected to V dd 103, and the drain of the first TFT 110 is connected to the pixel electrode (that is, the anode of the OLED) 130.
  • each pixel unit 100 including the above-mentioned members in the array substrate is disposed on the substrate 1 as an example of a cross section of the portion at the array substrate AA', and each of the pixel units 100 includes an active layer sequentially disposed on the substrate 1.
  • the gate insulating layer 3, the gate 111 of the first TFT 110, the interlayer insulating layer 4, and the source 112 of the first TFT 110 (the source 112 of the first TFT 110 is disposed in the same layer as the drain 113 of the first TFT 110)
  • the passivation layer 5 and the pixel electrode 130 is disposed on the substrate 1 as an example of a cross section of the portion at the array substrate AA', and each of the pixel units 100 includes an active layer sequentially disposed on the substrate 1. 2.
  • the substrate 1 is a glass substrate.
  • each pixel unit 100 further includes a storage capacitor, which includes a first electrode plate 210, a second electrode plate 220, and a third electrode plate 230, in conjunction with FIGS. 2 and 3A.
  • the first electrode plate 210 is electrically connected to the second electrode plate 220
  • the third electrode plate 230 is disposed between the first electrode plate 210 and the second electrode plate 220
  • the first electrode plate 210 and the second electrode plate 220 are respectively
  • the three electrode plates 230 have opposite portions.
  • the array substrate provided in the embodiment of FIG. 2 and FIG. 3A increases the number of electrode plates and reduces the number of electrode plates without increasing the occupied area of the storage capacitors. The distance between them increases the overall capacitance of the storage capacitor.
  • the active layer 2 and the first electrode plate 210 are integrated, and the pixel electrode 130 and the second electrode plate 220 are integrated.
  • the drain 113 of the first TFT 110 is connected to the pixel electrode 130 through the first via 51 penetrating the passivation layer 5, and the drain 113 of the first TFT 110 is also connected to the active layer 2.
  • the first electrode plate 210 is connected to the drain 113 of the first TFT 110
  • the second electrode plate 220 is also connected to the drain 113 of the first TFT 110, so the first electrode plate 210 and the second electrode plate 220 electrical connection.
  • the third electrode plate 230 is disposed between the first electrode plate 210 and the second electrode plate 220 and is opposite to the first electrode plate 210 and the second electrode plate 220, respectively.
  • the capacitance formed by the third electrode plate 230 and the first electrode plate 210, and the capacitance formed by the third electrode plate 230 and the second electrode plate 220 form two parallel capacitors, and the capacitances of the two capacitors connected in parallel are greater than The capacitance value of a storage capacitor composed only of two electrode plates.
  • the third electrode plate 230 is disposed in the same layer as the drain 113 of the first TFT 110.
  • the source 122 of the second TFT 120, the drain 123 of the second TFT 120, the source 112 of the first TFT 110, and the first The drain 113 of the TFT 110 is disposed in the same layer, and the gate 121 of the second TFT 120 is disposed in the same layer as the gate 111 of the first TFT 110.
  • the storage capacitor when the storage capacitor includes the first electrode plate 210, the second electrode plate 220, and the third electrode plate 230, the third electrode plate 230 and the gate 111 of the first TFT 110
  • the drain electrode 123 of the second TFT 120 and the gate electrode 111 of the first TFT 110 are electrically connected through the third via hole 42 penetrating the interlayer insulating layer 4 by being electrically connected through the second via hole 41 of the interlayer insulating layer 4.
  • the third electrode plate 230 is connected to the gate 111 of the first TFT 110, and is configured as an electrode plate C1 of the storage capacitor; and the first electrode plate 210 and the first electrode plate are electrically connected.
  • the two electrode plates 220 are connected to the pixel electrodes 130 and configured as the other electrode plates C2 of the storage capacitors. Therefore, the capacitance including the three electrode plates is connected to other components in the pixel unit.
  • the first electrode plate of the storage capacitor is integrated with the active layer.
  • the preparation of the active layer is completed by using the semiconductor, ionization processing is performed on a part of the active layer. That is, the preparation of the first electrode plate is completed; the second electrode plate of the storage capacitor is integrated with the pixel electrode, and is prepared by the pixel electrode, and the preparation of the second electrode plate is completed at the same time.
  • the preparation of the third electrode plate is completed while the drain of the first TFT is formed.
  • the manufacturing process of the three electrode plates of the storage capacitor is simple and convenient, and does not increase the complicated manufacturing process.
  • the pixel electrode 130 is formed on the flat layer 6, and the first via 51 also penetrates the flat layer 6.
  • the gate of the first TFT 110, the source of the first TFT 110, the drain of the first TFT 110, the gate of the second TFT 120, the source of the second TFT 120, and the second TFT 120 is prepared using one of Cu, Al, Mo, Ti, Cr, and W, or an alloy of at least two of these materials.
  • the gate of the first TFT 110, the source of the first TFT 110, the drain of the first TFT 110, the gate of the second TFT 120, the source of the second TFT 120, and the second TFT 120 are respectively a single layer structure.
  • the gate of the first TFT 110, the source of the first TFT 110, the drain of the first TFT 110, the gate of the second TFT 120, the source of the second TFT 120, and the second TFT 120 are respectively a multilayer structure including at least two layers.
  • the gate insulating layer 3 is made of silicon nitride or silicon oxide.
  • the gate insulating layer 3 has a single layer structure.
  • the gate insulating layer 3 is a multilayer structure including at least two layers.
  • the gate insulating layer includes a silicon oxide layer and a silicon nitride layer.
  • the passivation layer 5 is made of silicon nitride or silicon oxide.
  • the passivation layer 5 is a single layer structure.
  • the passivation layer 5 is a multilayer structure including at least two layers.
  • the passivation layer 5 includes a silicon oxide layer and a silicon nitride layer.
  • the array substrate in the OLED display is further provided with an anode of the OLED, a cathode 140, and a light emitting layer 150 between the anode and the cathode 140.
  • the anode of the OLED is the above pixel. Electrode 130.
  • a light emitting layer 150 is disposed on one side of each pixel unit on the array substrate of the OLED display panel, and the light emitting layer 150 is an organic light emitting layer.
  • the anode of the OLED is prepared using indium tin oxide ITO.
  • ITO and Ag were used as the anode of the OLED as an ITO/Ag/ITO structure.
  • the cathode of the OLED is prepared using Al or Ag.
  • the storage capacitor when the storage capacitor includes three electrode plates of the first electrode plate 210, the second electrode plate 220, and the third electrode plate 230, at least one of the first electrode plate 210 and the second electrode plate 220, and The portion facing the third electrode plate is bent toward the direction of the third electrode plate 230.
  • the distance between the third electrode plate and the bent electrode plate is reduced, and the storage is increased.
  • the capacitance value of the capacitor is increased.
  • each of the pixel units 100 includes an active layer 2, a gate insulating layer 3, and a gate of the first TFT 110 which are sequentially disposed on the substrate 1.
  • Each of the pixel units 100 further includes a storage capacitor, which includes a first electrode plate 210, a second electrode plate 220, and a third electrode plate 230, in conjunction with FIGS. 2 and 4.
  • the first electrode plate 210 is electrically connected to the second electrode plate 220
  • the third electrode plate 230 is disposed between the first electrode plate 210 and the second electrode plate 220
  • the first electrode plate 210 and the second electrode plate 220 are respectively
  • the three electrode plates 230 have opposite portions.
  • the array substrate in FIG. 4 is the same as the array substrate shown in FIG. 3A.
  • the active layer 2 and the first electrode plate 210 are integrated, and the pixel electrode 130 and the second electrode plate 220 are integrated, and the third electrode plate is formed.
  • 230 is disposed in the same layer as the drain 113 of the first TFT 110.
  • a flat layer 6 is further disposed between the passivation layer 5 and the pixel electrode 130, and a portion of the flat layer 6 opposite to the third electrode plate 230 is provided with a recess 61.
  • the second electrode plate 220 is deposited on the flat layer 6, and the second electrode plate 220 is bent at the groove 61.
  • the structure of the array substrate in FIG. 4 is reduced between the portion of the second electrode plate 220 opposite to the third electrode plate 230 and the third electrode plate 230 compared to the structure of the array substrate shown in FIG. 3A.
  • the distance increases the capacitance of the storage capacitor.
  • a protrusion is provided on a portion of the substrate 1 opposite to the third electrode plate 230 such that when the first electrode plate 210 is deposited on the substrate 1, the first electrode plate 210 is bent at the protrusion, as compared with The structure of the array substrate shown in FIG. 3A reduces the distance between the portion of the first electrode plate 210 facing the third electrode plate 230 and the third electrode plate 230, and increases the capacitance value of the storage capacitor.
  • the connection between the plurality of members in the array substrate shown in 3A is the same.
  • the array substrate provided in the above embodiment is described by taking a storage capacitor including three electrode plates as an example.
  • the storage capacitor includes more than three electrode plates.
  • the storage capacitor includes a first electrode plate 210, a second electrode plate 220, and a third electrode plate 230.
  • the storage capacitor further includes a fourth electrode plate, and the fourth electrode plate and the first electrode plate
  • the electrode plates 210 are electrically connected, and the fourth electrode plates are disposed between the first electrode plates 210 and the third electrode plates 230, and the fourth electrode plates and the third electrode plates 230 have opposite portions.
  • the distance between the two opposite electrode plates is reduced. Increases the capacitance of the storage capacitor.
  • the storage capacitor further includes a fifth electrode plate, and the fifth electrode plate is disposed between the second electrode plate 220 and the third electrode plate 230, and is fifth.
  • the electrode plate is electrically connected to the second electrode plate 220, which reduces the distance between the two opposite electrode plates and increases the capacitance value of the storage capacitor.
  • the structure of the array substrate shown in FIG. 5 and FIG. 6 is the same as that of the array substrate in the above embodiment.
  • the array substrate includes a plurality of pixel units 100, and each pixel unit 100 includes a first TFT 110.
  • the array substrate further includes a gate line 101, a data line 102, and a power line (V dd ) 103.
  • the gate of the second TFT 120 is connected to the gate line 101, the source of the second TFT 120 is connected to the data line 102, and the drain of the second TFT 120 is connected to the gate of the first TFT 110.
  • the source of the first TFT 110 is connected to V dd 103, and the drain of the first TFT 110 is connected to the pixel electrode 130.
  • each pixel unit 100 including the above-mentioned components in the array substrate is disposed on the substrate 1 , taking a cross-sectional view taken along the line DD′ of the array substrate as an example.
  • an active layer is sequentially disposed on the substrate 1 .
  • each pixel unit 100 further includes a storage capacitor.
  • the storage capacitor includes a first electrode plate 210 , a second electrode plate 220 , a third electrode plate 230 , and a fourth electrode plate 240 .
  • the first electrode plate 210, the second electrode plate 220, and the fourth electrode plate 240 are electrically connected, and the third electrode plate 230 is disposed between the fourth electrode plate 240 and the second electrode plate 220, and the first electrode plate 210,
  • the second electrode plate 220 and the fourth electrode plate 240 have portions opposite to the third electrode plate 230, respectively.
  • the active layer 2 and the first electrode plate 210 are integrated, the pixel electrode 130 and the second electrode plate 220 are integrated, and the third electrode plate 230 is disposed in the same layer as the drain 113 of the first TFT 110.
  • the fourth electrode plate 240 is disposed in the same layer as the gate 111 of the first TFT 110.
  • a flat layer 6 is further disposed between the passivation layer 5 and the pixel electrode 130, and a portion of the flat layer 6 opposite to the third electrode plate 230 is provided with a recess 61, wherein The two electrode plates 220 are deposited on the flat layer 6, and the second electrode plates 220 are bent at the grooves 61.
  • the drain 113 of the first TFT 110 is connected to the pixel electrode 130 through the first via 51 penetrating the passivation layer 5, and the drain 113 of the first TFT 110 is also associated with
  • the active layer 2 is connected to each other, and the first electrode plate 210 is electrically connected to the second electrode plate 220. Further, the fourth electrode plate 240 and the first electrode plate 210 are electrically connected through the fourth via hole 31 penetrating the gate insulating layer 3.
  • the first electrode plate 210, the second electrode plate 220, and the fourth electrode plate 240 are electrically connected.
  • the source 122 of the second TFT 120, the drain 123 of the second TFT 120, the source 112 of the first TFT 110, and the drain 113 of the first TFT 110 are disposed in the same layer.
  • the gate electrode 121 of the second TFT 120 is disposed in the same layer as the gate electrode 111 of the first TFT 110.
  • the third electrode plate 230 is electrically connected to the gate 111 of the first TFT 110 through the second via hole 41 penetrating the interlayer insulating layer 4, and the drain electrode 123 of the second TFT 120 and the gate electrode 111 of the first TFT 110 pass through the through layer.
  • the third vias 42 of the interlayer insulating layer 4 are electrically connected.
  • the third electrode plate 230 is connected to the gate 111 of the first TFT 110, and is configured as an electrode plate C1 of the storage capacitor;
  • the first electrode plate 210, the second electrode plate 220, and the fourth electrode plate 240 are connected to the pixel electrode 130, and are configured as an electrode plate C2 of the storage capacitor. Therefore, the capacitance including the four electrode plates is connected to the pixel unit. Other parts.
  • the portion facing the third electrode plate 220 and the third electrode plate 230 is bent toward the third electrode plate, and the third electrode plate 230 and the first electrode plate are bent.
  • a fourth electrode plate is disposed between the 210s. Compared with the array substrate in the embodiment of FIG. 2 to FIG. 4, the distance between the plurality of electrode plates is reduced, and the capacitance value of the storage capacitor is increased.
  • the array substrate in the above OLED display panel is applied in a QLED display panel.
  • the array substrate of the QLED display panel includes an anode, a cathode, and a light emitting layer disposed between the cathode and the anode.
  • the light emitting layer is disposed on one side of each pixel unit, the light emitting layer is a quantum dot light emitting layer, and the pixel electrode is the anode.
  • Some embodiments provide a display panel comprising the array substrate of any of the above embodiments.
  • Some embodiments provide a display device comprising a display panel as described above.
  • the array substrate, the display panel, and the display device improve the stability of the display screen compared to the facing area of the two electrodes including the storage capacitors including the two electrodes, without increasing the storage capacitor.
  • the distance between the electrode plates is reduced, and the overall capacitance value of the storage capacitor is increased.

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Abstract

提供了一种阵列基板、显示面板及显示装置。该阵列基板包括多个像素单元，其中每一像素单元包括存储电容，所述存储电容包括至少三个相互平行的电极板，其中，所述至少三个相互平行的电极板包括第一电极板、第二电极板和第三电极板，所述第一电极板与所述第二电极板电连接，所述第三电极板设置于所述第一电极板与所述第二电极板之间，且所述第一电极板和所述第二电极板分别与所述第三电极板具有相正对的部分。

Description

阵列基板、显示面板及显示装置
相关申请的交叉引用
本申请主张在2018年3月28日在中国提交的中国专利申请号No.201820433213.7的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，例如，涉及一种阵列基板、显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diodes，OLED)显示器件和量子点电致发光二极管(Quantum dots Light-emitting Diodes，QLED)显示器件均为自发光型显示设备，这些自发光型显示设备包括作为阳极的像素电极、作为阴极的公共电极以及设在像素电极与公共电极之间的发光层。在阳极和阴极被施加适当的电压时，发光层能够发光。
发明内容
一种阵列基板，包括多个像素单元，其中每一像素单元包括存储电容，所述存储电容包括至少三个相互平行的电极板，所述至少三个相互平行的电极板包括第一电极板、第二电极板和第三电极板，所述第一电极板与所述第二电极板电连接，所述第三电极板设置于所述第一电极板与所述第二电极板之间，且所述第一电极板和所述第二电极板分别与所述第三电极板具有相正对的部分。
一些实施例中，所述第一电极板和所述第二电极板中至少之一，与所述第三电极板相正对的部分朝所述第三电极板的方向弯折。
一些实施例中，所述至少三个相互平行的电极板还包括第四电极板，所述第四电极板与所述第一电极板电连接，且所述第四电极板设置于所述第一电极板与所述第三电极板之间，所述第四电极板与所述第三电极板具有相正 对的部分。
一些实施例中，所述每一像素单元包括依次设置于基板上的有源层、栅极绝缘层、第一薄膜晶体管TFT的栅极、层间绝缘层、同层设置的第一TFT的源极和第一TFT的漏极、钝化层和像素电极；
所述第一TFT的漏极与所述像素电极通过贯穿所述钝化层的第一过孔电连接；所述有源层与所述第一电极板为一体结构；以及所述像素电极与所述第二电极板为一体结构。
一些实施例中，所述的阵列基板，其中，所述第三电极板与所述第一TFT的漏极为同层设置。
一些实施例中，所述的阵列基板，其中，所述第三电极板与所述第一TFT的栅极通过贯穿所述层间绝缘层的第二过孔电连接。
一些实施例中，所述的阵列基板，还包括第二TFT、数据线以及栅线，所述第二TFT的源极与所述数据线连接，所述第二TFT的栅极与所述栅线连接，且所述第二TFT的源极、所述第二TFT的漏极、所述第一TFT的源极以及所述第一TFT的漏极同层设置，所述第二TFT的栅极与所述第一TFT的栅极同层设置；其中所述第二TFT的漏极与所述第一TFT的栅极通过贯穿所述层间绝缘层的第三过孔电连接。
一些实施例中，当所述至少三个相互平行的电极板还包括与所述第一电极板电连接的第四电极板，所述第四电极板与所述第三电极板具有相正对的部分时，所述第四电极板与所述第一TFT的栅极同层设置。
一些实施例中，所述第四电极板与所述第一电极板通过贯穿所述栅极绝缘层的第四过孔电连接。
一些实施例中，所述钝化层和所述像素电极之间设置有平坦层，所述平坦层与所述第三电极板相正对的部分设置有凹槽，所述第二电极板沉积在所述平坦层上，所述第二电极板在所述凹槽处形成弯折；和/或，
所述基板与所述第三电极板相正对的部分设置有突起，所述第一电极板沉积在所述基板上，所述第一电极板在所述突起处形成弯折。
一些实施例中，所述阵列基板还包括阳极、阴极以及设置在所述阳极和所述阴极之间的发光层，其中，所述像素电极为所述阳极，所述每一像素单 元一侧设置有所述发光层，以及所述发光层为有机发光层或者量子点发光层。
一种显示面板包括如上任一项所述的阵列基板。
一种显示装置包括如上所述的显示面板。
附图说明
图1为OLED显示器中像素单元的驱动电路的结构示意图；
图2为一些实施例提供的阵列基板的平面结构示意图；
图3A为一些实施例提供的沿图2中线AA’截取的阵列基板的剖面图；
图3B为一些实施例提供的沿图2中线BB’截取的阵列基板的剖面图；
图3C为一些实施例提供的沿图2中线CC’截取的阵列基板的剖面图；
图4为另一些实施例提供的沿图2中线AA’截取的阵列基板的剖面图；
图5为另一些实施例提供的阵列基板的平面结构示意图；以及
图6为一些实施例提供的沿图5中线DD’截取的阵列基板的剖面图。
具体实施方式
图1为一种OLED显示器中，像素单元的驱动电路的结构示意图。如图1所示，该驱动电路包括设置为驱动OLED的薄膜晶体管(Thin Film Transistor，TFT)T1、设置为开关控制OLED的薄膜晶体管T2、以及存储电容C。
其中，薄膜晶体管T2(又称，开关TFT)的栅极连接栅线(Gate Line)G1，薄膜晶体管T2的源极连接数据线(Data Line)D1，薄膜晶体管T2的漏极连接薄膜晶体管T1(又称，驱动TFT)的栅极。薄膜晶体管T1的源极连接电源线V dd，薄膜晶体管T1的漏极连接像素电极(有机发光二极管(OLED)OL1的阳极)。存储电容C的第一电极C1连接至薄膜晶体管T2的漏极和薄膜晶体管T1的栅极，存储电容C的第二电极C2连接至薄膜晶体管T1的漏极和OL1的阳极。
图1所示的OLED显示器的驱动电路中，存储电容C的电容值越大，OLED显示器的显示画面受薄膜晶体管T1的漏电流影响越大，显示画面的画面质量越稳定，因此，增大存储电容C的电容值成为提高显示画面稳定性的一种方法。
存储电容C的电容值增大，通常需要加大存储电容的两个电极的正对面积，但在显示面积(显示面板的显示区域的面积)有限的条件下，该方式对于电容值的增大效果有限。
一些实施例提供了一种阵列基板，所述阵列基板包括多个像素单元，其中每一像素单元上分别设置有存储电容，所述存储电容包括至少三个相互平行的电极板，所述至少三个相互平行的电极板包括第一电极板、第二电极板和第三电极板，其中，所述第一电极板与所述第二电极板电连接，所述第三电极板设置于所述第一电极板与所述第二电极板之间，且所述第一电极板与所述第三电极板具有相正对的部分，以及所述第二电极板与所述第三电极板具有相正对的部分。
上述实施例提供的所述阵列基板中，像素电路的存储电容包括至少三个相互平行的电极板，设置于第一电极板与第二电极板之间的第三电极板分别与第一电极板与第二电极板相正对，构成为存储电容，相较于相关技术，在不增加存储电容的占用面积的情况下，通过增加存储电容的电极板的数量，减小了电极板之间的距离，增大了存储电容的整体电容值。
如图2为一些实施例提供的阵列基板的平面结构示意图。图3A为一些实施例提供的沿图2中线AA’截取的阵列基板的剖面图。参阅图2和图3A，阵列基板包括多个像素单元100，每一像素单元100包括第一TFT 110、第二TFT 120、像素电极130和存储电容。
以下对应用于OLED显示器中的阵列基板进行说明。结合图1所示，OLED显示器的阵列基板中，像素电极130为OLED的阳极。
一些实施例中，参阅图2和图3A，并结合图1，阵列基板还包括栅线(Gate Line)101、数据线(Data Line)102以及电源线(V dd)103。第二TFT 120的栅极连接栅线101，第二TFT 120的源极连接数据线102，以及第二TFT 120的漏极连接第一TFT 110的栅极。第一TFT 110的源极连接V dd103，以及第一TFT 110的漏极连接像素电极(也即为OLED的阳极)130。
参阅图3A，阵列基板中包括上述构件的每个像素单元100设置于基板1上，以阵列基板AA’处部分的剖面为例，每个像素单元100包括在基板1上依次设置的有源层2、栅极绝缘层3、第一TFT 110的栅极111、层间绝缘 层4、第一TFT110的源极112(第一TFT110的源极112与第一TFT110的漏极113同层设置)、钝化层5和像素电极130。
一些实施例中，基板1为玻璃基板。
一些实施例中，每个像素单元100还包括存储电容，结合图2和图3A，该存储电容包括第一电极板210、第二电极板220和第三电极板230。第一电极板210与第二电极板220电连接，第三电极板230设置于第一电极板210与第二电极板220之间，且第一电极板210和第二电极板220分别与第三电极板230具有相正对的部分。
相较于设置两个电极板的存储电容，图2和图3A所在实施例提供的阵列基板，在不增加存储电容的占用面积的情况下，增加了电极板的数量，减小了电极板之间的距离，增大了存储电容的整体电容值。
一些实施例中，结合图3A所示，有源层2与第一电极板210为一体结构，像素电极130与第二电极板220为一体结构。
一些实施例中，第一TFT 110的漏极113与像素电极130通过贯穿钝化层5的第一过孔51相连接，而第一TFT 110的漏极113还与有源层2相连接，基于该结构，第一电极板210与第一TFT 110的漏极113相连接，第二电极板220也与第一TFT 110的漏极113相连接，因此第一电极板210与第二电极板220电连接。第三电极板230设置于第一电极板210与第二电极板220之间，并分别与第一电极板210和第二电极板220相正对。因此，第三电极板230与第一电极板210形成的电容，与第三电极板230和第二电极板220形成的电容，形成两个并联的电容，相并联的两个电容的电容值大于仅由两层电极板构成的存储电容的电容值。
一些实施例中，如图3A所示，第三电极板230与第一TFT 110的漏极113为同层设置。
一些实施例中，结合图2、图3B所示，在一个像素单元100中，第二TFT 120的源极122、第二TFT 120的漏极123、第一TFT 110的源极112以及第一TFT 110的漏极113同层设置，第二TFT 120的栅极121与第一TFT 110的栅极111同层设置。
一些实施例中，如图2和图3C所示，当存储电容包括第一电极板210、 第二电极板220和第三电极板230时，第三电极板230与第一TFT110的栅极111通过贯穿层间绝缘层4的第二过孔41电连接，第二TFT 120的漏极123与第一TFT 110的栅极111通过贯穿层间绝缘层4的第三过孔42电连接。
结合图1、图2和图3A所示，第三电极板230与第一TFT 110的栅极111相连接，构成为存储电容的一个电极板C1；而电连接的第一电极板210和第二电极板220，与像素电极130相连接，构成为存储电容的另一个电极板C2，因此，包括三个电极板的电容连接至像素单元中的其他部件。
一些实施例中，存储电容的第一电极板与有源层为一体结构，在进行阵列基板制作时，在利用半导体完成有源层的制备后，对有源层的其中一部分执行离子化处理，即完成第一电极板的制备；存储电容的第二电极板与像素电极为一体结构，通过像素电极制备，同时完成第二电极板的制备。
一些实施例中，由于第三电极板与第一TFT的漏极为同层设置，在制作第一TFT的漏极的同时完成第三电极板的制备。
因此，上述实施例中，存储电容的三个电极板的制作过程简单、方便，不会增加复杂的制作工序。
一些实施例中，如图3A所示，像素电极130制作于平坦层6上，第一过孔51还贯穿平坦层6。
一些实施例中，第一TFT 110的栅极、第一TFT 110的源极、第一TFT 110的漏极、第二TFT 120的栅极、第二TFT 120的源极以及第二TFT 120的漏极采用Cu、Al、Mo、Ti、Cr和W中的一种金属材料制备，或者采用这些材料中至少两种材料的合金制备。
一些实施例中，第一TFT 110的栅极、第一TFT 110的源极、第一TFT 110的漏极、第二TFT 120的栅极、第二TFT 120的源极以及第二TFT 120的漏极分别为单层结构。
一些实施例中，第一TFT 110的栅极、第一TFT 110的源极、第一TFT 110的漏极、第二TFT 120的栅极、第二TFT 120的源极以及第二TFT 120的漏极分别为包括至少两层的多层结构。
一些实施例中，栅极绝缘层3采用氮化硅或氧化硅制成。
一些实施例中，栅极绝缘层3为单层结构。
一些实施例中，栅极绝缘层3为包括至少两层的多层结构。例如，栅极绝缘层包括氧化硅层和氮化硅层。
一些实施例中，钝化层5采用氮化硅或氧化硅制成。
一些实施例中，钝化层5为单层结构。
一些实施例中，钝化层5为包括至少两层的多层结构。例如，钝化层5包括氧化硅层和氮化硅层。
一些实施例中，参见图3A所示，OLED显示器中的阵列基板上还设置有OLED的阳极、阴极140和位于阳极和阴极140之间的发光层150，根据以上，OLED的阳极为上述的像素电极130。
一些实施例中，参见图3A，OLED显示面板的阵列基板上每一像素单元一侧设置有发光层150，以及发光层150为有机发光层。
一些实施例中，采用氧化铟锡ITO制备OLED的阳极。
一些实施例中，采用ITO和Ag制备为ITO/Ag/ITO结构作为OLED的阳极。
一些实施例中，OLED的阴极采用Al或Ag制备。
一些实施例中，当存储电容包括第一电极板210、第二电极板220和第三电极板230这三个电极板时，第一电极板210和第二电极板220中至少之一，与第三电极板相正对的部分朝第三电极板230的方向弯折。
通过使第一电极板和第二电极板中至少之一正对的部分朝第三电极板的方向弯折，减小了第三电极板与弯折的电极板之间的距离，增加了存储电容的电容值。
图4为另一些实施例提供的沿图2中线AA’截取的阵列基板的剖面图。图4所示的阵列基板的结构中，与图3A所示的结构相同，每个像素单元100包括在基板1上依次设置的有源层2、栅极绝缘层3、第一TFT 110的栅极111、层间绝缘层4、第一TFT110的源极112(第一TFT110的源极112与第一TFT110的漏极113同层设置)、钝化层5和像素电极130。每个像素单元100还包括存储电容，结合图2和图4，该存储电容包括第一电极板210、第二电极板220和第三电极板230。第一电极板210与第二电极板220电连接，第三电极板230设置于第一电极板210与第二电极板220之间，且第一电极板 210和第二电极板220分别与第三电极板230具有相正对的部分。
图4中的阵列基板与图3A所示的阵列基板的实施结构相同，有源层2与第一电极板210为一体结构，像素电极130与第二电极板220为一体结构，第三电极板230与第一TFT 110的漏极113为同层设置。
在上述结构的基础上，参阅图4所示，钝化层5和像素电极130之间还设置有平坦层6，平坦层6与第三电极板230相正对的部分设置有凹槽61，其中第二电极板220沉积在平坦层6上，第二电极板220在凹槽61处形成弯折。
图4中的阵列基板的结构，相较于图3A所示的阵列基板的结构，减小了第二电极板220与第三电极板230相正对的部分和第三电极板230之间的距离，提高了存储电容的电容值。
一些实施例中，在基板1上与第三电极板230相正对的部分设置突起，使得第一电极板210沉积在基板1时，使第一电极板210在突起处弯折，相较于图3A所示的阵列基板的结构，减小了第一电极板210与第三电极板230相正对的部分和第三电极板230之间的距离，提高了存储电容的电容值。
图4所示的阵列基板的结构中，第一TFT 110、第二TFT 120、像素电极130、第一电极板210、第二电极板220、第三电极板230之间的连接方式，与图3A所示阵列基板中上述多个构件之间的连接方式相同。
上述实施例提供的所述阵列基板，以存储电容包括三个电极板为例进行说明。
一些实施例中，存储电容包括的电极板的数量大于3。
一些实施例中，在上述实施例中存储电容包括第一电极板210、第二电极板220和第三电极板230的基础上，存储电容还包括第四电极板，第四电极板与第一电极板210电连接，且第四电极板设置于第一电极板210与第三电极板230之间，第四电极板与第三电极板230具有相正对的部分。
在上述实施例中，通过在第一电极板210与第三电极板230之间增加一个与第一电极板210电连接的第四电极板，减小了两个相对的电极板之间的距离，提高了存储电容的电容值。
在上述实施例中阵列基板的结构的基础上，一些实施例中，存储电容还 包括第五电极板，第五电极板设置在第二电极板220与第三电极板230之间，且第五电极板与第二电极板220电连接，减小了两个相对的电极板之间的距离，提高了存储电容的电容值。
一些实施例中，参阅图5和图6所示的阵列基板的结构与上述实施例中的阵列基板结构相同，阵列基板包括多个像素单元100，每一像素单元100包括第一TFT 110、第二TFT 120、像素电极130和存储电容。
阵列基板还包括栅线(Gate Line)101、数据线(Data Line)102和电源线(V dd)103。第二TFT 120的栅极连接栅线101，第二TFT 120的源极连接数据线102，第二TFT 120的漏极连接第一TFT 110的栅极。第一TFT 110的源极连接V dd 103，第一TFT 110的漏极连接像素电极130。
参阅图6，阵列基板中包括上述构件的每个像素单元100设置于基板1，以阵列基板沿线DD’截取的剖面图为例，每个像素单元100中，在基板1上依次设置有源层2、栅极绝缘层3、第一TFT 110的栅极111、层间绝缘层4、第一TFT110的源极112(第一TFT110的漏极113同层设置与第一TFT110的源极112同层设置)、钝化层5和像素电极130。
参阅图6，每个像素单元100中还包括存储电容，结合图5和图6，该存储电容包括第一电极板210、第二电极板220、第三电极板230和第四电极板240。其中，第一电极板210、第二电极板220和第四电极板240电连接，第三电极板230设置于第四电极板240与第二电极板220之间，且第一电极板210、第二电极板220和第四电极板240分别与第三电极板230具有相正对的部分。
一些实施例中，有源层2与第一电极板210为一体结构，像素电极130与第二电极板220为一体结构，第三电极板230与第一TFT 110的漏极113为同层设置，第四电极板240与第一TFT 110的栅极111同层设置。
一些实施例中，参阅图6所示，钝化层5和像素电极130之间还设置有平坦层6，平坦层6与第三电极板230相正对的部分设置有凹槽61，其中第二电极板220沉积在平坦层6上，第二电极板220在凹槽61处形成弯折。
一些实施例中，结合图5和图6，第一TFT 110的漏极113与像素电极130通过贯穿钝化层5的第一过孔51相连接，而第一TFT 110的漏极113还 与有源层2相连接，第一电极板210与第二电极板220电连接，此外，第四电极板240与第一电极板210通过贯穿栅极绝缘层3的第四过孔31电连接，第一电极板210、第二电极板220和第四电极板240电连接。
一些实施例中，在一个像素单元100中，第二TFT 120的源极122、第二TFT 120的漏极123、第一TFT 110的源极112和第一TFT 110的漏极113同层设置，第二TFT 120的栅极121与第一TFT 110的栅极111同层设置。第三电极板230与第一TFT 110的栅极111通过贯穿层间绝缘层4的第二过孔41电连接，第二TFT 120的漏极123与第一TFT 110的栅极111通过贯穿层间绝缘层4的第三过孔42电连接。
在上述阵列基板的结构中，结合图1、图5和图6所示，第三电极板230与第一TFT 110的栅极111相连接，构成为存储电容的一个电极板C1；而电连接的第一电极板210、第二电极板220和第四电极板240，与像素电极130相连接，构成为存储电容的一个电极板C2，因此，包括四个电极板的电容连接至像素单元中的其他部件。
图5和图6所在实施例中，通过使第二电极板220与第三电极板230相正对的部分朝第三电极板的方向弯折，以及在第三电极板230与第一电极板210之间设置第四电极板，相较于图2至图4所在实施例中的阵列基板，减小了多个电极板之间的距离，提高了存储电容的电容值。
以上实施例以OLED显示面板中的阵列基板为例进行了说明。
一些实施例中，上述OLED显示面板中的所述阵列基板应用在QLED显示面板中。
一些实施例中，QLED显示面板的阵列基板包括阳极、阴极以及设置在阴极和阳极之间的发光层。当将OLED显示面板中的阵列基板应用于QLED显示面板时，每一像素单元一侧设置有所述发光层，所述发光层为量子点发光层，以及，像素电极为所述阳极。
一些实施例提供一种显示面板，包括如上任一实施例中的阵列基板。
一些实施例提供了一种显示装置，包括如上所述的显示面板。
上述实施例中的所述阵列基板、显示面板和显示装置，相较于加大包括两个电极的存储电容的两个电极的正对面积提高显示画面稳定性的方法，在 不增加存储电容的占用面积的情况下，通过增加电容的电极板的数量，减小电极板之间的距离，增大了存储电容的整体电容值。

Claims (13)

  1. 一种阵列基板，包括多个像素单元，其中每一像素单元包括存储电容，所述存储电容包括至少三个相互平行的电极板，所述至少三个相互平行的电极板包括第一电极板、第二电极板和第三电极板，所述第一电极板与所述第二电极板电连接，所述第三电极板设置于所述第一电极板与所述第二电极板之间，且所述第一电极板和所述第二电极板分别与所述第三电极板具有相正对的部分。
  2. 根据权利要求1所述的阵列基板，其中，所述第一电极板和所述第二电极板中至少之一，与所述第三电极板相正对的部分朝所述第三电极板的方向弯折。
  3. 根据权利要求1所述的阵列基板，其中，所述至少三个相互平行的电极板还包括第四电极板，所述第四电极板与所述第一电极板电连接，且所述第四电极板设置于所述第一电极板与所述第三电极板之间，所述第四电极板与所述第三电极板具有相正对的部分。
  4. 根据权利要求1至3任一项所述的阵列基板，其中，所述每一像素单元包括依次设置于基板上的有源层、栅极绝缘层、第一薄膜晶体管TFT的栅极、层间绝缘层、同层设置的第一TFT的源极和第一TFT的漏极、钝化层和像素电极；
    所述第一TFT的漏极与所述像素电极通过贯穿所述钝化层的第一过孔电连接；所述有源层与所述第一电极板为一体结构；以及所述像素电极与所述第二电极板为一体结构。
  5. 根据权利要求4所述的阵列基板，其中，所述第三电极板与所述第一TFT的漏极为同层设置。
  6. 根据权利要求4所述的阵列基板，其中，所述第三电极板与所述第一TFT的栅极通过贯穿所述层间绝缘层的第二过孔电连接。
  7. 根据权利要求4所述的阵列基板，还包括第二TFT、数据线以及栅线，其中，所述第二TFT的源极与所述数据线连接，所述第二TFT的栅极与所述栅线连接，且所述第二TFT的源极、所述第二TFT的漏极、所述第一TFT 的源极以及所述第一TFT的漏极同层设置，所述第二TFT的栅极与所述第一TFT的栅极同层设置；其中所述第二TFT的漏极与所述第一TFT的栅极通过贯穿所述层间绝缘层的第三过孔电连接。
  8. 根据权利要求4所述的阵列基板，其中，当所述至少三个相互平行的电极板还包括与所述第一电极板电连接的第四电极板，所述第四电极板与所述第三电极板具有相正对的部分时，所述第四电极板与所述第一TFT的栅极同层设置。
  9. 根据权利要求8所述的阵列基板，其中，所述第四电极板与所述第一电极板通过贯穿所述栅极绝缘层的第四过孔电连接。
  10. 根据权利要求4所述的阵列基板，其中，所述钝化层和所述像素电极之间设置有平坦层，所述平坦层与所述第三电极板相正对的部分设置有凹槽，所述第二电极板沉积在所述平坦层上，所述第二电极板在所述凹槽处形成弯折；和/或，
    所述基板与所述第三电极板相正对的部分设置有突起，所述第一电极板沉积在所述基板上，所述第一电极板在所述突起处形成弯折。
  11. 根据权利要求4所述的阵列基板，还包括阳极、阴极以及设置在所述阳极和所述阴极之间的发光层，其中，所述像素电极为所述阳极，所述每一像素单元一侧设置有所述发光层，以及所述发光层为有机发光层或者量子点发光层。
  12. 一种显示面板，包括权利要求1至11任一项所述的阵列基板。
  13. 一种显示装置，包括权利要求12所述的显示面板。
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JP7024937B2 (ja) 2022-02-24
CN207909879U (zh) 2018-09-25
EP3780107A4 (en) 2021-12-22
US11094766B2 (en) 2021-08-17
KR102201052B1 (ko) 2021-01-11
KR20190113757A (ko) 2019-10-08

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