WO2019185031A1 - 光模块 - Google Patents

光模块 Download PDF

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Publication number
WO2019185031A1
WO2019185031A1 PCT/CN2019/080464 CN2019080464W WO2019185031A1 WO 2019185031 A1 WO2019185031 A1 WO 2019185031A1 CN 2019080464 W CN2019080464 W CN 2019080464W WO 2019185031 A1 WO2019185031 A1 WO 2019185031A1
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WO
WIPO (PCT)
Prior art keywords
voltage
optical module
pin
output
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/080464
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English (en)
French (fr)
Inventor
郑龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hisense Broadband Multimedia Technology Co Ltd
Original Assignee
Hisense Broadband Multimedia Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201810631480.XA external-priority patent/CN108736977B/zh
Priority claimed from CN201810637538.1A external-priority patent/CN108880685B/zh
Application filed by Hisense Broadband Multimedia Technology Co Ltd filed Critical Hisense Broadband Multimedia Technology Co Ltd
Priority to EP19774767.8A priority Critical patent/EP3694119B1/en
Priority to US16/503,274 priority patent/US10637577B2/en
Publication of WO2019185031A1 publication Critical patent/WO2019185031A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/40—Transceivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/50—Transmitters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/0001—Selecting arrangements for multiplex systems using optical switching
    • H04Q11/0005—Switch and router aspects
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4274—Electrical aspects

Definitions

  • the present application relates to the field of optical communication technologies, and in particular, to an optical module.
  • the number of transmission channels increases. Therefore, the number of gold fingers used to implement signal transmission between the optical module and the upper computer is correspondingly increased.
  • the size of the optical modules cannot be too large, which limits the size of the optical modules on the optical modules.
  • the number of different control levels transmitted on the gold finger is limited, so that the working mode and the function of the optical module are limited. Therefore, the number of the gold finger pins in the optical module is limited, and different control voltages cannot be output.
  • Driving the optical module enables technical problems with different operating modes.
  • the present application provides an optical module to solve the technical problem that the existing optical module has a limited number of gold finger pins and cannot output different control voltages to drive the optical module to enable different working modes.
  • the application provides an optical module including a gold finger, a comparison unit and a voltage dividing unit.
  • the gold finger includes a plurality of pins, and one of the plurality of pins is a first pin.
  • the comparison unit includes a first input, a second input, and a first output. The first input terminal is connected to the first pin, the second input terminal is configured to determine a reference voltage, and the first output terminal is configured as an output voltage.
  • the voltage dividing unit includes a third input end and a second output end. The third input is configured to receive a voltage input.
  • the second output is coupled to the first pin and configured to adjust a voltage at the first pin to obtain an input voltage of a first input of the comparison unit. An output voltage having a different level is obtained according to a comparison between an input voltage of the first input terminal of the comparison unit and a decision reference voltage of the second input terminal.
  • FIG. 1 is a structural diagram of an optical module according to an embodiment of the present application.
  • FIG. 2A is a schematic circuit diagram of an embodiment of the present application.
  • 2B is a schematic circuit diagram of an embodiment of the present application.
  • 2C is a schematic circuit diagram of an embodiment of the present application.
  • 3A is a level diagram of a circuit provided by an embodiment of the present application.
  • FIG. 3B is a schematic diagram of levels of a circuit provided by an embodiment of the present application.
  • the optical module When the optical module is used, it needs to be inserted into the equipment machine (host computer).
  • the optical module establishes an electrical connection with the host computer through the gold finger on the circuit board to perform power supply, data transmission and other electrical interaction.
  • the optical module is manufactured by the optical module manufacturer, and the upper computer is manufactured by the upper computer manufacturer.
  • the part connecting the optical module and the upper computer needs to be manufactured according to a unified standard. Specifically, the optical module is connected with the gold finger.
  • the number and definition of the feet should be consistent with the host computer interface.
  • the embodiment of the present application needs to increase the number of the golden finger pins to transmit more control levels to enable different working modes, but is limited by the standard requirements of the upper computer.
  • the number of gold finger pins is physically increased. Therefore, in the present application, a technical solution for realizing function multiplexing of pins on the gold finger is proposed.
  • FIG. 1 is a structural diagram of an optical module according to an embodiment of the present application.
  • the optical module provided by the embodiment of the present application includes an upper casing 11 , a lower casing 12 , and a circuit board 10 .
  • a resistor, a comparator, a power source, and the like are provided on the surface of the circuit board 10.
  • the first end of the circuit board 10 is provided with an optical sub-module such as a light-emitting sub-module 13 and a light-receiving sub-module 14.
  • the second end of the circuit board 10 is provided with a gold finger 15 and the gold finger 15 is composed of a plurality of pins.
  • the golden finger of the optical module is inserted into the upper computer, and the pin in the golden finger is in electrical contact with the pin of the upper computer.
  • the plurality of pins of the golden finger 15 have a multiplexing pin, and the multiplexed pin realizes that at least two signals/functions are transmitted through the multiplexed pin.
  • the upper computer also has a multiplexing reference. The pin is set corresponding to the multiplexed pin of the optical module, so that the multiplexed pin in the optical module communicates with the multiplexed pin in the upper computer.
  • an optical module that communicates with a host includes a multiplexing pin 16, a comparison unit 201, and a voltage dividing unit 202.
  • the comparison unit 201 includes two input ends and one output end, which are a first input end, a second input end, and a first output end, respectively.
  • the first input of the comparison unit 201 is connected to the multiplexed pin 16, and the second input of the comparison unit 201 is configured to determine the reference voltage.
  • the first output of the comparison unit 201 is configured as an output voltage.
  • the voltage dividing unit 202 includes an input terminal and an output terminal, which may be referred to as a third input terminal and a second output terminal.
  • the second output of the voltage dividing unit 202 is connected to the multiplexed pin 16 and configured to adjust the voltage at the multiplexed pin 16 so that the first input of the comparing unit 201 obtains the voltage adjusted by the voltage dividing unit.
  • An output voltage having a different level is obtained based on a comparison between the input voltage of the first input terminal and the decision reference voltage at the second input terminal.
  • the multiplexed pin outputs enable control voltages for different operating modes.
  • the voltage transmitted by the pins on the gold finger is multiplexed to meet the requirements of the optical module in different working modes, and the function mode of the optical module is enriched to improve the performance of the optical module.
  • the multiplexing pin 16 is configured to implement at least one of the following functional multiplexing: determining a high and low power consumption function and determining whether the function multiplexing of the in-position function, and resetting the reset function and the function multiplexing of the abnormal fault function.
  • the host computer issues an indication signal to control the optical module to enter the Reset mode, so that the optical module is reset in the Reset mode, thereby implementing the reset function.
  • the control pin for controlling the Reset mode in the upper computer is connected with the controlled pin of the golden finger of the optical module, and the upper computer can change the voltage of the controlled pin of the gold finger of the optical module, and when the upper computer inputs the high level
  • the controlled pin on the optical finger of the optical module receives the Reset control level of the high level, and the optical module enters the Reset mode to perform reset.
  • the optical module communicates with the host computer, if an abnormality is detected inside the optical module, such as an abnormal state in which the laser does not emit light, emits abnormal light, the normal light cannot be turned off, the MCU is abnormal, and the other abnormality of the chip does not work, the optical module is in an abnormal state.
  • the Fault control level is output to the host computer, and the corresponding processing mode is determined by the host computer to solve the abnormality.
  • the processing mode is as follows: disconnecting the power supply of the optical module, outputting a Disable signal to the optical module, or accessing the optical module through the IIC for processing.
  • the Reset function and the Fault function of the optical module are implemented by the same physical pin, which is a multiplexed pin.
  • the pins When multiplexing the pins, different signals are multiplexed by time division. The foot is transmitted.
  • the optical module has the function of a low power LOWPOWER (LP) mode.
  • the upper computer indicates that the optical module enters the low power mode from the normal working state (ie, the high power consumption mode) to achieve energy saving.
  • the optical module needs to be instructed by the host computer to enter the low power mode and exit the low power mode.
  • the LP mode control pin of the upper computer is connected with the golden finger controlled pin of the optical module, and the upper computer can change the voltage of the gold finger controlled pin of the optical module through the connection relationship, and the voltage output of the upper computer increases.
  • the voltage comparison unit in the optical module determines whether to enter or exit the low power mode by judging the voltage level of the controlled pin.
  • the host computer needs to check whether the optical module is connected, that is, whether the optical module is in place.
  • the in-position detection pin of the upper computer maintains a high state by default, that is, a high state is maintained when the optical module is not connected.
  • the upper computer detects a high level, it determines that the optical module is not in the position;
  • the pin of the optical module is connected with the in-position detection pin of the upper computer, which lowers the voltage of the in-position detection pin of the upper computer.
  • the upper computer detects the low voltage, it judges that the optical module is in place. .
  • a voltage comparison unit is used in the upper computer to determine the voltage of the in-position detection pin.
  • the in-position detection and low-power mode judgment of the optical module are performed by detecting the voltage state of the pin, and the decision threshold voltage of the upper computer is higher than the decision reference voltage of the optical module.
  • the physical pin is a multiplexed pin.
  • multiplexed pins different signals are time-divided.
  • the mode is transmitted through the multiplexed pins.
  • an optical module is provided, as shown in FIG. 2B, which includes a comparison unit 10 and a voltage dividing unit 20.
  • the first input of the comparison unit 10 is coupled to a multiplexed pin 16', the first input receiving a first control voltage output by the host via the multiplexed pin 16'.
  • the second input of the comparison unit 10 is configured to determine the reference voltage.
  • the output of the comparison unit 10 controls the output of the first multiplexing voltage, and the first multiplexing voltage is used to enable the first multiplexing mode.
  • the first multiplexing mode is a Reset mode
  • the second multiplexing mode is a Fault mode.
  • the configured threshold voltage is greater than the decision reference voltage, so as to divide the working voltage of the multiplexed pin in the optical module into three voltage intervals, and respectively implement switching control of different multiplexing modes of the optical module in each voltage interval, wherein the division is performed.
  • the specific voltage interval please refer to FIG. 3A.
  • the working mode and switching process in each voltage interval will be described in detail below.
  • the first input end of the comparison unit 10 is connected to the multiplexed pin 16', receives the first control voltage output by the upper computer via the multiplexed pin 16', and the comparison unit 10 according to the first control voltage and the decision reference
  • the magnitude relationship of the voltage controls the first multiplexed voltage of the output.
  • the positive terminal of the comparison unit 10 is a first input terminal, and the negative terminal thereof is a second input terminal.
  • the output terminal of the comparison unit 10 outputs a first multiplex voltage.
  • the outputted first multiplexed voltage is at a low level, and the first multiplexed voltage is enabled by the first multiplexed voltage, that is, the Reset mode of the optical module is implemented.
  • the optical module includes a comparing unit 10 and a voltage dividing unit 20, and the comparing unit 10 is a comparator IC-1, and the first input end (ie, the positive end) of the comparator IC-1 passes the light.
  • the multiplexed pin 16' on the module is connected to the host (Host), and the second input (ie, the negative terminal) of the comparator IC-1 is configured to determine the reference voltage of 1.25V.
  • the host includes a second buffer (buffer IC-4), a comparator IC-3, and a third resistor (resistor R3, wherein the resistance R3 has a resistance of 68K).
  • the upper control unit When the host computer controls the optical module to enter the reset mode, the upper control unit outputs a first control voltage low level via the buffer IC-4 and the multiplexed pin 16', and the comparator IC-1
  • the first input terminal receives the first control voltage via the multiplexed pin, the first control voltage is less than the configured decision reference voltage, and the output of the comparator IC-1 controls the output of the first multiplexed voltage, wherein the first complex
  • the first multiplexing mode is enabled by the first multiplexing voltage, that is, the Reset mode of the optical module is implemented.
  • the upper control unit When the host computer (Host) does not need to control the optical module (Module) to enter the Reset mode, the upper control unit outputs a first control voltage of a high level via the buffer IC-4 and the multiplexed pin 16', and is multiplexed. 16' is transmitted to the first input terminal of the comparator IC-1, at which time the first control voltage is greater than the configured decision reference voltage, and the output of the comparator IC-1 controls the first multiplexed voltage of the output. Wherein, the first multiplexing voltage is at a high level to disable the first multiplexing mode.
  • the optical module receives the first control voltage output by the host computer via the multiplexed pin, and the comparison unit in the optical module controls the output to enable the first multiplexing according to the relationship between the first control voltage and the decision reference voltage.
  • the first multiplexed voltage of the mode to control the enabled or disabled state of the first multiplexed mode.
  • the input end of the voltage dividing unit 20 is for receiving the second control voltage, and the output end of the voltage dividing unit 20 is connected to the multiplexing pin 16'.
  • the output end of the voltage dividing unit 20 outputs a second multiplexing voltage
  • the output end of the voltage dividing unit 20 outputs a third multiplexing voltage for disabling, wherein the second multiplexing voltage is greater than a decision threshold configured in the upper computer
  • the voltage, the second multiplexed voltage is used to enable the second multiplexing mode, the third multiplexed voltage is less than the decision threshold voltage, and the threshold voltage is determined to be greater than the decision reference voltage.
  • the voltage dividing unit 20 includes a first buffer (buffer IC-2) and a second resistor (resistor R2).
  • the input end of the first buffer (buffer IC-2) receives the second control voltage, and the second control voltage is a control signal that needs to be reported to the upper computer when the optical module is faulty.
  • the second control voltage is at a high level, and when the optical module does not have a fault, the second control voltage is at a low level.
  • the first output of the first buffer (buffer IC-2) is connected to a second resistor (resistor R2), and the second output of the first buffer (buffer IC-2) is grounded.
  • the resistance of the second resistor (resistor R2) can be 8K.
  • the second resistor (resistor R2) has one end connected to the first output of the first buffer (buffer IC-2) and the other end connected to the multiplexed pin 16'.
  • the optical module further includes a first resistor (resistor R1), the first end of the first resistor is connected to the power supply VCC (the power supply VCC is 3.3V), and the second end is connected to the multiplexed pin 16' Connected.
  • the resistance of the first resistor (resistor R1) can be 5K.
  • the first buffer (buffer IC-2) receives the second control voltage and the second control voltage is at the second level.
  • the second level is a low level.
  • the voltage output by the voltage dividing unit 20 is a parallel resistance of the power supply VCC via the first resistor (resistor R1) and the second resistor (resistor R2) and the third resistor (resistor R3) (the resistance of the parallel connection of R2 and R3)
  • the voltage divider value of the shunt resistor is corresponding, that is, when the second control voltage is the second level, the third of the multiplexed pin 16' is disabled.
  • the third multiplex voltage is smaller than the decision threshold voltage of the positive terminal of the comparator IC-3 disposed in the upper computer, wherein the threshold voltage is 2.5. V
  • the output of the comparator IC-3 outputs a high level, so that the upper computer determines that the optical module has no abnormality according to the high level outputted at the output of the comparator IC-3, that is, does not enter the Fault mode.
  • the first buffer (buffer IC-2) receives the second control voltage and the second control voltage is the first One level, for example, the first level is a high level, and the first buffer (buffer IC-2) receives the second control voltage of the high level, the first buffer (buffer IC-2) In the high resistance state, the first output terminal is in a floating state, and accordingly, one end of the second resistor (resistor R2) connected to the first output terminal of the first buffer (buffer IC-2) is also suspended.
  • the voltage transmitted by the multiplexed pin 16' is a partial voltage of the first resistor (resistor R1) and the third resistor (resistor R3), that is, when the optical module does not operate abnormally, that is, the second control voltage is the second
  • the upper computer determines that the optical module abnormality occurs according to the low level outputted at the output of the comparator IC-3, that is, enters the Fault mode.
  • the second multiplexing voltage (3.07V) is greater than the decision reference voltage, and the optical module does not enter the first multiplexing mode.
  • the voltage dividing unit 20 receives the second control voltage at a different level at its receiving end, the voltage transmitted to the upper computer via the multiplexed pin is controlled.
  • the voltage is increased by the voltage dividing unit 20 to be greater than the threshold voltage of the upper end of the optical module to enable the second multiplexing mode of the optical module, that is, the fault mode.
  • the optical module provided by the above specific embodiment of the present application can implement control of the voltage outputted by the multiplexed pin.
  • the multiplexed pin outputs respectively enable the control voltages of different working modes.
  • the control level of the pin on the gold finger is multiplexed to meet the requirements of the optical module in different working modes, and the function mode of the optical module is enriched to improve the performance of the optical module.
  • an optical module in another embodiment, is provided. As shown in FIG. 2C, the optical module includes a comparison unit 110 and a voltage dividing unit 130.
  • the first input of the comparison unit 110 is connected to the multiplexed pin 16", and the multiplexed pin 16" receives the first voltage and the second voltage from the upper computer in a time-sharing manner.
  • the voltage dividing unit 130 is connected to the multiplexing pin 16" to reduce the voltage of the upper computer, so that the upper computer outputs the first voltage, and the first voltage is lower than the threshold voltage of the upper computer.
  • the second input of the comparing unit 110 is connected. Determining the reference voltage, the output of the comparison unit 110 outputs a control voltage, wherein the reference voltage is determined to be greater than the second voltage and less than the first voltage.
  • the upper computer needs to judge whether the optical module is in place (whether or not it is inserted into the upper computer), and the judgment of the upper computer is performed by the voltage decision of the specific pin.
  • the pin of the upper computer socket is connected with the multiplexed pin of the optical module gold finger, and the pin of the upper computer socket is at a high voltage state by default.
  • the multiplexed pin of the optical module gold finger is connected to the voltage dividing unit inside the optical module to reduce the pin voltage of the upper computer socket.
  • the pin of the upper computer outputs a first voltage to the multiplexed pin of the optical module, that is, the pin of the upper computer changes from a high voltage to a reduced first voltage.
  • the decision threshold voltage of the upper computer for determining whether the optical module is in position is 2.5V, and the voltage of the upper computer is higher than 2.5V by default.
  • the upper computer determines that the optical module is not in position; when the optical module is inserted into the upper computer, the optical module The voltage dividing unit in the unit pulls the voltage of the multiplexed pin down to 2.5V or less to obtain the first voltage.
  • the optical module is inserted into the upper computer, and the multiplexed pin is electrically connected with the corresponding pin of the upper computer.
  • the voltage dividing unit of the optical module lowers the voltage of the pin corresponding to the upper computer and the multiplexed pin, so that the upper computer determines that the optical module is in place. , the in-situ judgment of the transmission of this signal is realized.
  • an indication signal is sent to the optical module, and the other indication signal can also be transmitted through the multiplexed pin.
  • an indication signal is sent to the optical module, and the other indication signal can also be transmitted through the multiplexed pin.
  • the multiplexed pin can transmit multiple signals, mainly because of the in-position judgment of the upper computer and the low power state judgment of the optical module. The decision voltages of the two are different, and the low power state is after the optical module is in position. Further status. Specifically, the in-position judgment of the upper computer determines that the threshold voltage is 2.5V, and the low power state of the optical module determines that the reference voltage is 1.25V.
  • the default output of the host computer is higher than 2.5V, until the optical module is inserted into the host computer, the voltage is pulled down, but the first voltage after the pull-down is still greater than the decision voltage of the low-power consumption of the optical module, which is in place and high-power.
  • the host computer further changes the voltage, and the changed second voltage is lower than the low-power decision reference voltage of the optical module, so that the optical module enters the in-position and low power consumption state.
  • the optical module pulls the voltage low and enters the in-position state and the high power consumption state; the upper computer further pulls down the voltage to enter the in-position and low power consumption state.
  • the comparison unit 110 in the optical module is a comparator
  • the voltage dividing unit 130 is a resistor R3
  • one end of the resistor R3 is connected to the multiplexed pin
  • the other end of the resistor R3 is grounded.
  • the optical module provided by the embodiment of the present application includes a comparison unit 110 (comparator IC-1), a voltage dividing unit 130 (resistor R3), and a first input/positive input terminal of the comparator IC-1 and a multiplexing guide.
  • the pins are connected, and thus can be connected to the host through a multiplexed pin on the optical module.
  • the multiplexed pin of the optical module is connected to the pin of the upper computer to form an electrical path 16 .
  • the upper computer connected to the optical module includes a buffer IC-2, a comparator IC-3, a resistor R1, and a resistor R2.
  • the positive input of IC-3 can be connected to the first input/positive input of comparator IC-1 of the optical module through a multiplexed pin on the optical module.
  • the negative input of IC-3 is connected to the decision threshold voltage, and the negative input of IC-1 is connected to the decision reference voltage.
  • the decision threshold voltage is used to determine whether the optical module is inserted into the upper computer, and the reference voltage is used to determine whether the optical module enters the low power mode.
  • one end of the resistor R3 is connected to the multiplexed pin, and the other end is grounded.
  • one end of the resistor R1 is connected to the positive input terminal of the comparator IC-3, and the other end is connected to the output end of the buffer IC-2.
  • One end of the resistor R2 is connected to the power supply, and the other end is connected to the positive input of the IC-3.
  • the first voltage is indicated as Presence and the second voltage is indicated as LPMode.
  • the host computer Under the control of the signal Host_LPMode received by the buffer IC-2, the host computer transmits a second voltage indication LPMode to the optical module, and the optical module outputs a control voltage Module_LPMode under the control of the LPMode.
  • the positive input voltage of the comparator IC-3 is higher than the threshold voltage, so that the output signal Host_Presence of the IC-3 is high, indicating that the optical module is not in position.
  • the positive input terminal of the comparator IC-3 receives the first voltage indication Presence, and the IC-3 positive input terminal voltage is lower than the threshold voltage, so that the IC-3 output signal Host_Presence is low, upward
  • the bit machine indicates that the optical module is in place.
  • the positive input voltage of the comparator IC-1 is lower than the decision reference voltage, so that the output signal (Module_LPMode) of the IC-1 is low, and the optical module is controlled to operate with low power consumption.
  • the comparator IC-3 positive input terminal voltage is lower than the decision threshold voltage, so that the IC-3 output signal Host_Presence is low, indicating that the optical module is in place.
  • IC-2 When Host_LPMode is high, IC-2 outputs a high level.
  • the positive input voltage of IC-1 is higher than the decision reference voltage, making Module_LPMode high, controlling the high power consumption of the optical module.
  • the IC-3 positive input voltage can be lower than the decision threshold voltage, making Host_Presence low, indicating that the optical module is in place.
  • FIG. 3B is a level diagram of the application scenario of FIG. 2C. As shown in FIG. 3B, in the interval 1, the voltage of the multiplexed pin is located at 0V to 1.25V, that is, under the decision reference voltage (1.25V), Module_LPMode is low, and Host_Presence is low, indicating that the optical module is Bit and low power operation.
  • the voltage of the multiplexed pin is located at 1.25V to 2.5V, Module_LPMode is high, and Host_Presence is low, indicating that the optical module is in place and operates with low power consumption.
  • interval 3 the voltage of the multiplexed pin is above the decision threshold voltage (2.5V), and Host_Presence is high, indicating that the optical module is not in position.
  • the voltage lower than 2.5V can be theoretically considered to be in place, it is actually significantly lower than 2.5V, so the interval 2 shown in the figure is located at 1.25V and 2.5.
  • the resistor R1 is 15 K ⁇
  • R2 is 25 K ⁇
  • R3 is 10 K ⁇ .
  • the optical module part of Figure 2C does not exist.
  • the voltage of the signal multiplexing pin is pulled up to the power supply (3.3V) through R2, so the positive input terminal of the comparator IC-3 is 3.3V.
  • the negative input terminal is the decision threshold voltage (2.5V), so the signal Host_Presence is high.
  • the signal Host_LPMode is low level, and the IC-2 input low level.
  • the positive input of comparator IC-1 is 0.94V
  • the negative input is the decision reference voltage (1.25V), so the signal Module_LPMode is low.
  • the signal Host_LPMode is high level, and the high level is input to IC-2.
  • the positive input of comparator IC-1 is 1.7V
  • the negative input is 1.25V of the decision reference voltage, so the signal Module_LPMode is high.
  • the optical module provided by the above specific embodiment of the present application can implement control of the voltage outputted by the multiplexed pin.
  • the voltage dividing unit reduces the voltage on the multiplexed pin, and the obtained first voltage is lower than the threshold voltage of the upper computer, thereby realizing a signal transmitted between the optical module and the upper computer; the optical module receives the second voltage from the upper computer,
  • the decision reference voltage of the comparison unit is greater than the second voltage and less than the first voltage, so that another signal is transmitted between the upper computer and the optical module.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Electromagnetism (AREA)
  • Signal Processing (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Optical Communication System (AREA)

Abstract

本申请提供一种光模块，包括金手指、比较单元和分压单元。金手指包括多个引脚，所述多个引脚中的第一引脚能够被复用。比较单元包括第一输入端、第二输入端和第一输出端。第一输入端与所述第一引脚连接，第二输入端配置判决参考电压，第一输出端配置为输出电压。分压单元包括第三输入端和第二输出端，第三输入端配置为接收电压输入，第二输出端与所述第一引脚连接，配置为对第一引脚处的电压进行调整，以使比较单元的第一输入端获得输入电压。根据比较单元的第一输入端的输入电压与第二输入端的判决参考电压之间的比较结果获得具有不同电平的输出电压。

Description

光模块
相关申请的交叉引用
本专利申请要求于2018年3月29日提交的、申请号为2018102685355、发明名称为“一种光模块”，于2018年5月9日提交的、申请号为2018104390601、发明名称为“一种光模块”，于2018年6月19日提交的、申请号为201810631480X、发明名称为“一种光模块”，于2018年6月20日提交的、申请号为2018106375381、发明名称为“一种光模块”的中国专利申请的优先权，这些申请的全文以引用的方式并入本文中。
技术领域
本申请涉及光通信技术领域，尤其涉及一种光模块。
背景技术
随着光模块速率越来越高，传输通道随之增多，因此，用于实现光模块与上位机之间信号传输的金手指的数量也相应要求增加。为了在标准机框内插入更多的光模块，受限于标准机框和上位机的尺寸要求，光模块的尺寸无法过大，进而限制了光模块上金手指的引脚布设数量，也相应限制了金手指上所传输的不同控制电平的数量，使得光模块的工作模式和使用功能所受限，因此，光模块中存在因金手指引脚数量受限而无法输出不同的控制电压以驱动光模块使能不同工作模式的技术问题。
发明内容
本申请提供了一种光模块，以解决现有光模块中存在因金手指引脚数量受限而无法输出不同的控制电压以驱动光模块使能不同工作模式的技术问题。
本申请提供一种光模块，包括金手指、比较单元和分压单元。所述金手指包括多个引脚，所述多个引脚中的一个引脚为第一引脚。所述比较单元包括第一输入端、第二输入端和第一输出端。所述第一输入端与所述第一引脚连接，所述第二输入端配置判决参考电压，所述第一输出端配置为输出电压。分压单元包括第三输入端和第二输出端。所述第三输入端配置为接收电压输入。所述第二输出端与所述第一引脚连接，配置为对所述第一引脚处的电压进行调整，以使所述比较单元的第一输入端获得输入电压。根据所述比较单元的所述第一输入端的输入电压与所述第二输入端的判决参考电压之间的比 较结果获得具有不同电平的输出电压。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本申请。
附图说明
为了更清楚地说明本申请的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，对于本领域普通技术人员而言，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的光模块结构图；
图2A是本申请实施例提供的电路示意图；
图2B是本申请实施例提供的电路示意图；
图2C是本申请实施例提供的电路示意图；
图3A是本申请实施例提供的电路的电平示意图；
图3B是本申请实施例提供的电路的电平示意图。
具体实施方式
这里将详细地对示例性实施例执行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
光模块在使用时需要插入设备机(上位机)中，光模块通过电路板上的金手指与上位机建立电连接，以进行供电、数据传递等电交互。从产业分工来看，光模块由光模块厂商生产制造，上位机由上位机厂商生产制造，在光模块与上位机衔接的部分需要按照统一的标准制造，具体地，光模块金手指上连接引脚的数量以及定义要与上位机接口一致。这种标准虽然便于光模块与上位机建立电连接，但是限制了金手指引脚的数量及功能，进而限制了光模块厂商对光模块功能的研发。
本申请实施例为了扩展光模块的功能及工作模式，需要增加金手指引脚的数量以传输更多的控制电平以使能不同工作模式，但是受限于与上位机的标准要求，无法从物理 上增加金手指引脚的数量，故在本申请中提出一种对金手指上的引脚实现功能复用的技术方案。
图1是本申请实施例提供的光模块结构图。如图1所示，本申请实施例提供的光模块包括上壳体11、下壳体12及电路板10。在电路板10的表面设置有电阻、比较器、电源等电器件。电路板10的第一端设置有光发射次模块13、光接收次模块14等光学次模块，其第二端设置有金手指15，金手指15由多个引脚所组成。为实现光模块与上位机之间的通信传输，将光模块的金手指插入上位机中，金手指中的引脚与上位机的引脚实现电接触。其中金手指15的多个引脚中具有一复用引脚，复用引脚实现了至少两种信号/功能通过该复用引脚进行传输，与此对应的，上位机同样有一复用引脚与光模块的复用引脚相对应设置，以实现光模块内的复用引脚与上位机中的复用引脚进行通信传输。
在一个实施例中，如图2A所示，与上位机(Host)通信的光模块(Module)包括复用引脚16、比较单元201和分压单元202。比较单元201包括两个输入端和一个输出端，分别为第一输入端、第二输入端和第一输出端。比较单元201的第一输入端与复用引脚16连接，比较单元201的第二输入端配置判决参考电压。比较单元201的第一输出端配置为输出电压。分压单元202包括一个输入端和一个输出端，可以称为第三输入端和第二输出端。分压单元202的第二输出端与复用引脚16连接，配置为对复用引脚16处的电压进行调整，使比较单元201的第一输入端获得分压单元调整后的电压。根据该第一输入端的输入电压与第二输入端处的判决参考电压之间的比较结果获得具有不同电平的输出电压。
在该实施例中，通过在光模块设置判决参考电压并由分压单元调整使得最终输出电压位于不同电压区间内，以实现经复用引脚输出分别使能不同工作模式的控制电压。在无需增加金手指引脚数量的前提下，复用金手指上引脚所传输的电压以满足光模块在不同工作模式下的需求，丰富光模块的功能模式，提高光模块整机性能。
可选地，复用引脚16用于实现以下至少一种功能复用：判断高低功耗功能和判断是否在位功能的功能复用，以及复位Reset功能和异常Fault功能的功能复用。
在一个示例中，光模块在与上位机进行通信时，上位机发出指示信号以控制光模块进入Reset模式，以使得光模块在Reset模式下进行复位，从而实现复位功能。具体地，上位机中控制Reset模式的控制引脚与光模块的金手指的被控引脚相连接，上位机可改变光模块金手指的被控引脚的电压，当上位机输入高电平有效的Reset控制电平时，光 模块金手指上的被控引脚接收到该高电平的Reset控制电平，光模块进而进入Reset模式以进行复位。
此外，光模块在与上位机进行通信时，若光模块内部检测到异常，如激光器异常不发光、发异常光、常发光无法关断、MCU异常其他芯片异常不工作等异常状态，光模块就会输出Fault控制电平给上位机，由上位机确定相应处理方式以解决该异常。其中，处理方式如断开光模块的供电电源，输出Disable信号给光模块或通过IIC访问光模块进行处理等。
在上述示例中，将光模块的Reset功能与Fault功能采用同一个物理引脚实现，该物理引脚即复用引脚，在复用引脚时，不同的信号采用时分的方式通过复用引脚进行传输。
在另一示例中，光模块中具有低功耗LOWPOWER(LP)模式的功能。在上位机不需要光模块进行光电转换以传递信息时，由上位机指示光模块由正常的工作状态(即高功耗模式)进入低功耗模式，以实现节能。光模块进入低功耗模式以及退出低功耗模式均需要上位机的指示。具体地，上位机的LP模式控制引脚与光模块的金手指被控引脚连接，上位机可以通过这种连接关系改变光模块金手指被控引脚的电压，当上位机增加其电压输出时，光模块金手指被控引脚的电压随之升高，光模块内的电压比较单元通过判断被控引脚的电压高低来判断进入或退出低功耗模式。
此外，上位机需要检查光模块是否接入，即光模块是否在位。上位机对光模块是否在位的判断，只有两种状态，即在位和不在位。具体地，上位机的在位检测引脚默认保持高电平状态，即在光模块未接入时保持高电平状态，此时上位机检测到高电平后，判断光模块不在位；当光模块接入时，光模块的引脚与上位机的在位检测引脚连接，拉低了上位机在位检测引脚的电压，此时上位机检测到低电压后，判断光模块在位。具体地，上位机中采用电压比较单元来判断在位检测引脚的电压。光模块的在位检测与低功耗模式判断都是通过检测引脚的电压状态进行的，而且上位机的判决门限电压比光模块的判决参考电压高。
在上述示例中，将光模块是否处低功耗与光模块是否在位采用同一个物理引脚实现，该物理引脚即复用引脚，在复用引脚时，不同的信号采用时分的方式通过复用引脚进行传输。
在一个具体实施方式中，提供了一种光模块，如图2B所示，其包括比较单元10和分压单元20。比较单元10的第一输入端与复用引脚16’连接，第一输入端接收由上位 机经复用引脚16’所输出的第一控制电压。比较单元10的第二输入端配置判决参考电压。比较单元10的输出端控制输出第一复用电压，第一复用电压用于使能第一复用模式。其中，第一复用模式为Reset模式，第二复用模式为Fault模式。所配置判决门限电压大于判决参考电压，以将光模块内复用引脚的工作电压分为三个电压区间，各电压区间内分别实现对光模块不同复用模式的切换控制，其中，所划分的电压区间具体请参见图3A所示，各电压区间下的工作模式及切换过程将在下文进行详细说明。
具体的，比较单元10的第一输入端与复用引脚16’相连，接收由上位机经复用引脚16’所输出的第一控制电压，比较单元10根据第一控制电压与判决参考电压的大小关系控制输出的第一复用电压。比较单元10的正端为第一输入端，其负端为第二输入端，所接收到的第一控制电压小于判决参考电压时，比较单元10的输出端输出第一复用电压，其中，所输出的第一复用电压为低电平，由第一复用电压使能第一复用模式，即，实现光模块的Reset模式。
具体的，请参考图2B，光模块(Module)包括比较单元10和分压单元20，比较单元10为比较器IC-1，比较器IC-1的第一输入端(即正端)通过光模块上的复用引脚16’与上位机(Host)相连接，比较器IC-1的第二输入端(即负端)配置判决参考电压1.25V。
上位机(Host)包括第二缓冲器(缓冲器IC-4)、比较器IC-3和第三电阻(电阻R3，其中，电阻R3阻值为68K)。当上位机(Host)控制光模块(Module)进入Reset模式时，由上位机经缓冲器IC-4和复用引脚16’输出为低电平的第一控制电压，比较器IC-1的第一输入端经复用引脚接收第一控制电压，第一控制电压小于所配置的判决参考电压，由比较器IC-1的输出端控制输出的第一复用电压，其中，第一复用电压为低电平，由第一复用电压使能第一复用模式，即，实现光模块的Reset模式。当上位机(Host)无需控制光模块(Module)进入Reset模式时，由上位机经缓冲器IC-4和复用引脚16’输出为高电平的第一控制电压，经复用引脚16’传输至比较器IC-1的第一输入端，此时第一控制电压大于所配置的判决参考电压，由比较器IC-1的输出端控制输出的第一复用电压。其中，第一复用电压为高电平，以禁用第一复用模式。由此，光模块经复用引脚接收由上位机所输出的第一控制电压，光模块内的比较单元根据第一控制电压与判决参考电压大小关系以控制输出用于使能第一复用模式的第一复用电压，以控制第一复用模式的使能或禁用状态。
分压单元20的输入端用于接收第二控制电压，分压单元20的输出端与复用引脚16’相连，当第二控制电压为第一电平时，分压单元20的输出端输出第二复用电压，当第 二控制电压为第二电平时，分压单元20的输出端输出用于禁用的第三复用电压，其中，第二复用电压大于配置于上位机的判决门限电压，第二复用电压用于使能第二复用模式，第三复用电压小于判决门限电压，判决门限电压大于判决参考电压。
请参考图2B，分压单元20包括第一缓冲器(缓冲器IC-2)和第二电阻(电阻R2)。第一缓冲器(缓冲器IC-2)的输入端接收第二控制电压，第二控制电压为光模块发生Fault时需要向上位机报错的控制信号。当光模块发生Fault时，第二控制电压为高电平，当光模块未发生Fault时，第二控制电压为低电平。第一缓冲器(缓冲器IC-2)的第一输出端与第二电阻(电阻R2)相连，第一缓冲器(缓冲器IC-2)的第二输出端接地。第二电阻(电阻R2)阻值可为8K。第二电阻(电阻R2)的一端与第一缓冲器(缓冲器IC-2)的第一输出端相连，其另一端与复用引脚16’相连。参照图2B所示，光模块还包括第一电阻(电阻R1)，第一电阻的第一端与供电电源VCC(供电电源VCC为3.3V)相连，其第二端与复用引脚16’相连。第一电阻(电阻R1)阻值可为5K。
具体地，当光模块未发生工作异常时，第一缓冲器(缓冲器IC-2)接收第二控制电压且第二控制电压为第二电平，示例的，第二电平为低电平，分压单元20所输出的电压为，供电电源VCC经第一电阻(电阻R1)与，第二电阻(电阻R2)和第三电阻(电阻R3)的并联电阻(R2与R3并联的阻值为68K*8K/(68K+8K)＝7.16KΩ)后对应该并联电阻的分压值，即在第二控制电压为第二电平时，复用引脚16’处的用于禁用的第三复用电压为7.16K*3.3V/(7.16K+5k)＝1.94V，该第三复用电压小于配置于上位机中比较器IC-3正端的判决门限电压，其中，判决门限电压为2.5V，由比较器IC-3输出端输出高电平，以此上位机根据在比较器IC-3输出端所输出的高电平确定光模块无异常发生，即不进入Fault模式。
当光模块发生工作异常时，其需要向上位机报错以告知上位机当前光模块的工作状态发生错误，第一缓冲器(缓冲器IC-2)接收第二控制电压且第二控制电压为第一电平，示例的，第一电平为高电平，第一缓冲器(缓冲器IC-2)在接收到高电平的第二控制电压时，第一缓冲器(缓冲器IC-2)为高阻状态，其第一输出端为悬空状态，相应地，与第一缓冲器(缓冲器IC-2)的第一输出端相连的第二电阻(电阻R2)的一端也为悬空。由此，经复用引脚16’所传输的电压为第一电阻(电阻R1)和第三电阻(电阻R3)的分压，即光模块未发生工作异常时，即第二控制电压为第二电平(低电平)时，分压单元20拉高复用引脚16’的电压得到第二复用电压，该第二复用电压例如为68K*3.3V/(68K+5K)＝3.07V，其大于配置于上位机中比较器IC-3正端的判决门限电压 2.5V，由第二复用电压使能第二复用模式(Fault模式)，由比较器IC-3输出端输出低电平，以此上位机根据在比较器IC-3输出端所输出的低电平确定光模块异常发生，即进入Fault模式。同时，第二复用电压(3.07V)大于判决参考电压，光模块不会进入第一复用模式。由此，通过分压单元20在其接收端接收到位于不同电平的第二控制电压时，对经由复用引脚向上位机所传输的电压进行控制。当光模块发生工作异常时，由分压单元20拉高电压使其大于配置于上位机端的判决门限电压，以使能光模块的第二复用模式，即Fault模式。
综上所述，本申请上述具体实施方式提供的光模块能够实现对复用引脚所输出电压的控制。通过设置判决门限电压、判决参考电压并由比较单元和分压单元调整由复用引脚所传输电压位于不同电压区间内，以实现经复用引脚输出分别使能不同工作模式的控制电压，在无需增加金手指引脚数量的前提下，复用金手指上引脚所传输的控制电平以满足光模块在不同工作模式下的需求，丰富光模块的功能模式，提高光模块整机性能。
在另一个具体实施方式中，提供了一种光模块，如图2C所示，光模块包括比较单元110和分压单元130。比较单元110的第一输入端与复用引脚16”连接，复用引脚16”分时地接收来自上位机的第一电压及第二电压。分压单元130与复用引脚16”连接，以降低上位机的电压，使得上位机输出第一电压，第一电压低于上位机的判决门限电压。比较单元110的第二输入端接入判决参考电压，比较单元110的输出端输出控制电压。其中判决参考电压大于第二电压、小于第一电压。
上位机需要对光模块是否在位(是否插入上位机)进行判断，上位机的这种判决是通过特定引脚的电压判决进行的。上位机插座的引脚与光模块金手指的复用引脚连接，上位机插座的引脚默认处于高电压状态。当光模块插入后，光模块金手指的复用引脚连接光模块内部的分压单元，以降低上位机插座的引脚电压。拉低电压之后，上位机的引脚向光模块的复用引脚输出第一电压，即在上位机的引脚由高电压转变为降低后的第一电压。具体地，上位机对光模块是否在位判断的判决门限电压为2.5V，上位机的电压默认高于2.5V，此时上位机判定光模块不在位；当光模块插入上位机后，光模块中的分压单元将复用引脚的电压拉低至2.5V以下，即得到第一电压。光模块插入上位机，复用引脚与上位机对应引脚电连接，光模块的分压单元拉低了上位机与复用引脚对应的引脚的电压，使得上位机判定光模块在位，实现了在位判断这一路信号的传输。上位机指示光模块进入低功耗模式时，会向光模块发出指示信号，这另外的一路指示信号也可以通过复用引脚进行传输。
上位机指示光模块进入低功耗模式时，会向光模块发出指示信号，这另外的一路指示信号也可以通过复用引脚进行传输。复用引脚可以进行多路信号的传输，主要因为上位机的在位判断以及光模块的低功耗状态判断，这两者的判决电压不同，而且低功耗状态是光模块在位之后的进一步状态。具体地，上位机的在位判断，其判决门限电压为2.5V，而光模块的低功耗状态判断，其判决参考电压为1.25V。上位机默认输出高于2.5V的电压，直到光模块插入上位机后拉低了该电压，但是拉低后的第一电压仍然大于光模块低功耗的判决参考电压，处于在位且高功耗的状态，上位机进一步改变该电压，改变后的第二电压低于光模块低功耗判决参考电压，使得光模块进入在位且低功耗状态。这样，在同一个引脚上，由光模块拉低电压，进入在位状态且高功耗状态；由上位机进一步拉低电压，进入在位且低功耗状态。
参照图2C，光模块内的比较单元110是比较器，分压单元130是电阻R3，电阻R3的一端与复用引脚连接，电阻R3的另一端接地。本申请实施例提供的光模块(Module)包括比较单元110(比较器IC-1)、分压单元130(电阻R3)，比较器IC-1的第一输入端/正输入端与复用引脚连接，进而能够通过光模块上的复用引脚与上位机(Host)连接。图2C中由光模块的复用引脚与上位机的引脚连接成一路电通路16。
与光模块连接的上位机包括缓冲器IC-2、比较器IC-3、电阻R1、电阻R2。IC-3的正输入端能够通过光模块上的复用引脚与光模块的比较器IC-1的第一输入端/正输入端连接。IC-3的负输入端连接判决门限电压，IC-1的负输入端连接判决参考电压。判决门限电压用于判断光模块是否插入上位机中，判决参考电压用于判断光模块是否进入低功耗模式。
光模块中，电阻R3一端与复用引脚连接，另一端接地。
上位机中，电阻R1一端与比较器IC-3的正输入端连接，另一端连接缓冲器IC-2的输出端。电阻R2一端与供电电源连接，另一端与IC-3的正输入端连接。
第一电压指示为Presence，第二电压指示为LPMode。在缓冲器IC-2所接收信号Host_LPMode的控制下，上位机向光模块传输第二电压指示LPMode，光模块在LPMode的控制下输出控制电压Module_LPMode。
光模块不与上位机连接时，比较器IC-3正输入端电压高于判决门限电压，使得IC-3的输出信号Host_Presence为高电平，指示光模块不在位。
光模块与上位机连接时，比较器IC-3正输入端接收第一电压指示Presence，IC-3正 输入端电压低于判决门限电压，使得IC-3的输出信号Host_Presence为低电平，向上位机指示光模块在位。
Host_LPMode为低电平时，一方面，比较器IC-1正输入端电压低于判决参考电压，使得IC-1的输出信号(Module_LPMode)为低电平，控制光模块低功耗工作。另一方面，比较器IC-3正输入端电压低于判决门限电压，使得IC-3的输出信号Host_Presence为低电平，指示光模块在位。
Host_LPMode为高电平时，IC-2输出高电平，一方面，IC-1正输入端电压高于判决参考电压，使得Module_LPMode为高电平，控制光模块高功耗工作。另一方面，IC-3正输入端电压可低于判决门限电压，使得Host_Presence为低电平，指示光模块在位。
图3B是图2C应用场景的电平示意图。如图3B所示，区间1中，复用引脚的电压位于0V至1.25V，即位于判决参考电压(1.25V)之下，Module_LPMode为低电平，Host_Presence为低电平，指示光模块在位并低功耗工作。
区间2中，复用引脚的电压位于1.25V至2.5V，Module_LPMode为高电平，Host_Presence为低电平，指示光模块在位并低功耗工作。
区间3中，复用引脚的电压位于判决门限电压(2.5V)之上，Host_Presence为高电平，指示光模块不在位。实际应用中，为了保持对电压的高灵敏度判断，虽然低于2.5V的电压就可以理论上认为是在位，但实际还是会明显低于2.5V，所以图示的区间2位于1.25V与2.5V之间的中间区域。
其中，具体地，电阻R1为15KΩ，R2为25KΩ，R3为10KΩ。
当光模块不在位时，图2C中光模块部分不存在，此时信号复用引脚的电压通过R2上拉至供电电源(3.3V)，因此比较器IC-3的正输入端为3.3V，负输入端为判决门限电压(2.5V)，因此信号Host_Presence为高电平。
当光模块低功耗工作时，信号Host_LPMode为低电平，向IC-2输入低电平，此时复用引脚的电压通过R3和R2分压后，10K*3.3V/(10K+25K)＝0.94V，因此IC-3的正输入端为0.94V，负输入端为判决门限电压(2.5V)，因此信号Host_Presence为低电平。同时，比较器IC-1的正输入端为0.94V，负输入端为判决参考电压(1.25V)，因此信号Module_LPMode为低电平。
当光模块高功耗工作时，信号Host_LPMode为高电平，向IC-2输入高电平，此时电阻R1与电阻R2并联的阻值为25K*15K/(25K+15K)＝9.375KΩ，复用引脚的电压为 10K*3.3V/(10K+9.375K)＝1.7V，因此比较器IC-3的正输入端为1.7V，负输入端为判决门限电压(2.5V)，因此信号Host_Presence为低电平。同时，比较器IC-1的正输入端为1.7V，负输入端为判决参考电压1.25V，因此信号Module_LPMode为高电平。
综上所述，本申请上述具体实施方式提供的光模块能够实现对复用引脚所输出电压的控制。分压单元降低复用引脚上的电压，得到的第一电压低于上位机的判决门限电压，实现了光模块与上位机之间传递一路信号；光模块接收来自上位机的第二电压，比较单元的判决参考电压大于第二电压、小于第一电压，实现了上位机与光模块之间传递另一路信号。
本领域技术人员在考虑说明书及实践这里申请的公开后，将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本申请的真正范围和精神由下面的权利要求指出。
应当理解的是，诸如“第一”和“第二”等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。本申请并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求来限制。

Claims (12)

  1. 一种光模块，包括：
    金手指，包括多个引脚，所述多个引脚中的第一引脚能够被复用；
    比较单元，包括第一输入端、第二输入端和第一输出端，所述第一输入端与所述第一引脚连接，所述第二输入端配置判决参考电压，所述第一输出端配置为输出电压；和
    分压单元，包括第三输入端和第二输出端，所述第三输入端配置为接收电压输入，所述第二输出端与所述第一引脚连接，配置为对所述第一引脚处的电压进行调整，以使所述比较单元的第一输入端获得调整后的电压，根据所述比较单元的第一输入端的输入电压与所述第二输入端的判决参考电压之间的比较结果获得具有不同电平的输出电压。
  2. 根据权利要求1所述的光模块，所述第一引脚用于实现以下至少一种功能复用：
    判断高低功耗功能和判断是否在位功能的功能复用；
    复位Reset功能和异常Fault功能的功能复用。
  3. 根据权利要求1所述的光模块，
    所述比较单元的第一输入端配置为接收由上位机经所述第一引脚所输出的第一控制电压，
    所述比较单元的第一输出端配置为输出第一复用电压，所述第一复用电压用于使能第一复用模式；
    所述分压单元的第三输入端配置为接收第二控制电压；
    其中，所述分压单元的第二输出端配置为：当所述第三输入端输入的第二控制电压为第一电平时，输出第二复用电压，当所述第三输入端输入的第二控制电压为第二电平时，输出用于禁用的第三复用电压；
    所述第二复用电压用于使能第二复用模式，大于配置于所述上位机的判决门限电压，所述第三复用电压小于所述判决门限电压，所述判决门限电压大于所述判决参考电压。
  4. 根据权利要求1所述的光模块，
    所述比较单元的第一输入端，配置为接收由上位机经所述第一引脚所输出的第一控制电压，所述比较单元的第二输入端配置判决参考电压，其中，所述比较单元的第一输出端，配置为：在所述第一输入端接收的第一控制电压小于所述判决参考电压时，输出第一复用电压以使能第一复用模式；
    所述分压单元的第三输入端，配置为接收第二控制电压，所述分压单元第二输出端，配置为：当所述分压单元的第三输入端接收到所述第二控制电压时，将所述第一引脚处 的电压拉高以输出所述第二复用电压以使能第二复用模式，所述第二复用电压大于配置于所述上位机的判决门限电压，所述判决门限电压大于所述判决参考电压。
  5. 根据权利要求1所述的光模块，
    所述第一引脚还配置为分时地接收来自上位机的第一电压及第二电压，所述第一电压是通过经由所述分压单元降低所述上位机的电压获得，所述第一电压低于所述上位机的判决门限电压；所述判决参考电压大于所述第二电压并且小于所述第一电压。
  6. 根据权利要求3所述的光模块，所述比较单元为比较器，所述比较单元的第一输入端为正端，所述比较单元的第二输入端为负端。
  7. 根据权利要求6所述的光模块，所述比较单元的输出端进一步配置为：在所述正端的所述第一控制电压小于所述负端的判决参考电压时，输出所述第一复用电压以使能第一复用模式。
  8. 根据权利要求3所述的光模块，所述光模块还包括第一电阻，所述第一电阻的第一端与所述第一引脚相连，第二端与供电电源相连。
  9. 根据权利要求3或4所述的光模块，所述分压单元包括第二电阻和第一缓冲器，所述第二电阻的第一端连接第一缓冲器，第二端连接所述第一引脚，所述第一缓冲器的一端接地，所述第一缓冲器配置为：在所述第二控制电压为第二电平时，呈现高阻状态。
  10. 根据权利要求3所述的光模块，所述第一复用模式为Reset模式，所述第二复用模式为Fault模式。
  11. 根据权利要求5所述的光模块，所述判决门限电压用于判断所述光模块是否插入所述上位机中。
  12. 根据权利要求5所述的光模块，所述判决参考电压用于判断所述光模块是否进入低功耗模式。
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