WO2019196447A1 - 栅极驱动模组、栅极驱动控制方法和显示装置 - Google Patents

栅极驱动模组、栅极驱动控制方法和显示装置 Download PDF

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Publication number
WO2019196447A1
WO2019196447A1 PCT/CN2018/119772 CN2018119772W WO2019196447A1 WO 2019196447 A1 WO2019196447 A1 WO 2019196447A1 CN 2018119772 W CN2018119772 W CN 2018119772W WO 2019196447 A1 WO2019196447 A1 WO 2019196447A1
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Prior art keywords
shift register
gate
sub
circuit
register unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/119772
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English (en)
French (fr)
Inventor
黄炜赟
高永益
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to EP18889953.8A priority Critical patent/EP3779943A4/en
Priority to US16/475,301 priority patent/US11232732B2/en
Publication of WO2019196447A1 publication Critical patent/WO2019196447A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/03—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays
    • G09G3/035—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes specially adapted for displays having non-planar surfaces, e.g. curved displays for flexible display surfaces
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/04—Partial updating of the display screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2380/00—Specific applications
    • G09G2380/02—Flexible displays

Definitions

  • the present disclosure relates to the field of display driving technologies, and in particular, to a gate driving module, a gate driving control method, and a display device.
  • the flexible display panel can be folded and can be applied to a folding terminal.
  • the folding terminal may be, for example, a folding mobile phone, a folding flat plate or the like.
  • the folding terminal faces a problem, which needs to be displayed on both sides before and after the expansion, and only one of the sides is required for folding.
  • it is necessary to turn off the signal output of the shift register unit corresponding to the display area.
  • the existing solution is to use at least two gate driving circuits according to at least two sub-display areas of the display panel when folded, so that each gate driving circuit can respectively control one sub-display area.
  • this method requires a driver IC (Integrated Circuit) to support more clock signals and start signals, and at the same time, there is no cascading relationship between the at least two gate drive circuits, which is easy to occur when the gate drive scans.
  • the clock is misaligned, and the Gate Loading between the at least two gate drive circuits is also different, so that at least two sub-display areas have a split screen when the full screen display is caused.
  • an embodiment of the present disclosure provides a gate driving module, which is applied to a display panel, the display panel has a display area, and when the display panel is in a non-planar state, the display area is formed.
  • the gate driving module includes a gate driving circuit, wherein the gate driving circuit includes a plurality of shift register sub-circuits that are cascaded with each other; and the plurality of shift register sub-circuits
  • the first shift register sub-circuit includes at least one stage first shift register unit, and the second one of the plurality of shift register sub-circuits includes at least one stage second shift register unit;
  • the pole drive module also includes a control circuit.
  • Each of the at least one first shift register unit is connected to a gate line provided in a first sub-display area of the plurality of sub-display areas; the at least one level Each of the second shift register units is respectively connected to a clock signal line and a gate line disposed in a second sub-display area of the plurality of sub-display areas, for being used according to the clock signal a voltage signal on the line generates a gate drive signal output to the gate line; and the control circuit is configured to when the display panel is in a non-planar state and in the at least one stage of the second shift register unit When a second shift register unit performs gate drive scanning, controlling to supply a first voltage signal to the clock signal line, so that the second shift register unit control gate line is emitted such that a transistor corresponding to the gate line is turned off ( OFF) signal.
  • the display panel when the display panel is in the non-planar state, the display panel is folded, and the display area forms a plurality of sub-display areas by one or more folding axes; or
  • the display panel is curled when the display panel is in the non-planar state.
  • the number of the folding axes is one, the number of the first shift register sub-circuits is one, and the number of the second shift register sub-circuits is one;
  • the first shift register sub-circuit includes a gate drive signal output end of the last stage first shift register unit and an input of the first stage second shift register unit included in the second shift register sub-circuit End connection;
  • the second shift register sub-circuit includes a gate drive signal output end of the first stage second shift register unit and a reset of the last stage first shift register unit included in the first shift register sub-circuit End connection.
  • the number of the folding axes is two, the number of the first shift register sub-circuits and the number of the first sub-display areas are two, the first The shift register sub-circuit is in one-to-one correspondence with the first sub-display area; the number of the second shift register sub-circuit and the number of the second sub-display area is one;
  • a first stage of the first shift register sub-circuit comprising: a gate drive signal output end of the first stage first shift register unit and a first stage second shift register included in the second shift register sub-circuit The input of the unit is connected;
  • the second shift register sub-circuit includes a gate drive signal output end of the first stage second shift register unit and a last stage first shift register included in the first one of the first shift register sub-circuits The reset end of the unit is connected;
  • the second shift register sub-circuit includes a gate drive signal output end of the last stage second shift register unit and a first stage first shift register included in the second first shift register sub-circuit The input of the unit is connected;
  • a second first shift register sub-circuit comprising a gate drive signal output of the first stage first shift register unit and a last stage second shift register included in the second shift register sub-circuit The reset end of the unit is connected.
  • the first shift register unit is further connected to the clock signal line for generating an output according to a voltage signal on the clock signal line to be connected to the first shift register unit. a gate drive signal of the gate line;
  • the control circuit is further configured to: when the display panel is in a non-planar state, and when the first shift register unit performs a gate drive scan, control to provide a clock signal to the clock signal line, so that the The first shift register unit controls the gate line to emit a signal that causes the transistor corresponding to the gate line to be turned ON.
  • control circuit is further configured to control providing a clock signal to the clock signal line when the display panel is in a planar state, such that when the first shift register unit performs a gate When the scan is driven, the first shift register unit controls the gate line to emit a signal that causes the transistor corresponding to the gate line to be turned ON, and when the second shift register unit performs gate drive scan, the first The two shift register unit control gate lines emit signals that cause the transistors corresponding to the gate lines to be turned "ON".
  • the display panel when the display panel is in the planar state, the display panel is restored from a collapsed state to an expanded state;
  • the display panel When the display panel is in the planar state, the display panel is restored from the curled state to the expanded state.
  • the gate driving module further includes a detecting circuit, configured to detect that the display panel is in a non-planar state or a planar state, generate a corresponding state indication signal, and An indication signal is transmitted to the control circuit.
  • control circuit is further configured to control the direction and the second sub-frame during a black screen display period immediately before the non-planar time and immediately adjacent to the non-planar time a sub-pixel connected data line in the display area provides a predetermined data voltage such that the sub-pixel displays a black picture;
  • the non-planar time is a time at which the control circuit starts controlling to supply a first voltage signal to the clock signal line.
  • the clock signal line includes a first clock signal line and a second clock signal line
  • the first shift register sub-circuit includes an odd-numbered first shift register unit coupled to the first clock signal input, the first shift register sub-circuit including an even-numbered first shift register unit and The second clock signal input is connected;
  • the first shift register sub-circuit includes a first shift register unit having an even number of stages, the second shift register sub-circuit including an odd-numbered second shift register unit and the first clock signal input End connection, the second shift register sub-circuit comprising an even-numbered second shift register unit is coupled to the second clock signal input.
  • the clock signal line includes a first clock signal line and a second clock signal line
  • the first shift register sub-circuit includes an odd-numbered first shift register unit coupled to the first clock signal input, the first shift register sub-circuit including an even-numbered first shift register unit and The second clock signal input is connected;
  • the first shift register sub-circuit includes an odd number of stages of the first shift register unit
  • the second shift register sub-circuit includes an odd-numbered second shift register unit and the second clock signal input End connection, the second shift register sub-circuit comprising an even-numbered second shift register unit connected to the first clock signal input.
  • an embodiment of the present disclosure provides a gate driving control method applied to a gate driving module as described in the first aspect, the gate Drive control methods include:
  • the control circuit controls to provide a first voltage signal to the clock signal line such that the second shift register unit controls the gate line A signal is issued that causes the transistor corresponding to the gate line to be turned OFF.
  • the first shift register unit is further connected to the clock signal line; the gate drive control method further includes:
  • the control circuit controls to provide a clock signal to the clock signal line to cause the first shift
  • the bit register unit controls the gate line to emit a signal that causes the corresponding transistor of the gate line to be turned ON.
  • the gate driving control method further includes:
  • the control circuit controls to provide a clock signal to the clock signal line when the display panel is in a planar state, such that the first shift register unit when the first shift register unit performs gate drive scanning
  • the control gate line emits a signal that causes the corresponding transistor of the gate line to be turned ON
  • the second shift register unit controls the gate line to emit The signal corresponding to the transistor of the gate line is turned ON.
  • the gate driving module further includes a detecting circuit; the gate driving control method further includes:
  • the detecting circuit detects that the display panel is in a non-planar state or a planar state, generates a corresponding status indication signal, and transmits the status indication signal to the control circuit.
  • the gate driving control method further includes:
  • the control circuit controls providing to a data line connected to a sub-pixel provided in the second sub-display area during a black picture display period immediately before the non-planar time and immediately adjacent to the non-planar time Predetermining a data voltage such that the sub-pixel displays a black picture;
  • the non-planar time is a time at which the control circuit starts controlling to supply a first voltage signal to the clock signal line.
  • an embodiment of the present disclosure further provides a display device comprising the gate drive module as described in the first aspect.
  • the display device further includes a driving integrated circuit and a plurality of gate lines extending in the first direction; the folding axis extending in the first direction; the gate driving The control circuit included in the module is disposed in the driving integrated circuit.
  • the gate driving module includes a gate driving circuit disposed in a peripheral region of the display panel to which the plurality of gate lines extend.
  • the plurality of gate lines are disposed longitudinally
  • the gate driving module includes a gate driving circuit disposed on an upper side of the display panel or a lower side of the display panel, wherein The longitudinal direction is substantially identical to the first direction.
  • the plurality of gate lines are longitudinally disposed, the gate driving module includes two gate driving circuits; and the first gate driving circuit of the two gate driving circuits is disposed at An upper side of the display panel, the shift register unit included in the gate driving circuit is connected to an upper end of the corresponding gate line; and a second gate driving circuit of the two gate driving circuits is disposed on the display panel The lower side, the gate drive circuit includes a shift register unit coupled to a lower end of the corresponding gate line, wherein the longitudinal direction substantially coincides with the first direction.
  • the first gate driving circuit and the second gate driving circuit are both gate driving circuits (GOAs) disposed on the array substrate.
  • GAAs gate driving circuits
  • FIG. 1 is a schematic diagram of a display panel to which a gate driving module according to an embodiment of the present disclosure is applied in an unfolded state (ie, a planar state);
  • FIG. 2 is a schematic diagram of a display panel applied to a gate driving module according to an embodiment of the present disclosure when folded (ie, in a non-planar state);
  • FIG. 3 is a structural diagram of a specific embodiment of a gate driving module according to the present disclosure.
  • FIG. 4 is an operation timing diagram of the specific embodiment of the gate driving module of the present disclosure when the display panel is in a folded state
  • FIG 5 is an operational timing diagram of the specific embodiment of the gate driving module of the present disclosure when the display panel is in an unfolded state
  • FIG. 6 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics.
  • one of the poles is referred to as a first pole, and the other pole is referred to as a second pole.
  • the first pole may be a drain
  • the second pole may be a source
  • the first pole may be a source
  • the second pole may be a drain.
  • the gate driving module of the embodiment of the present disclosure is applied to a display panel, the display panel has a display area, and when the display panel is in a folded state, the display area forms a plurality of sub-folds through one or more folding axes.
  • the gate driving module includes a gate driving circuit;
  • the gate driving circuit includes a plurality of shift register sub-circuits that are cascaded with each other;
  • the first shift register sub-circuit of the plurality of shift register sub-circuits includes at least one stage first shift register unit
  • the second shift register sub-circuit of the plurality of shift register sub-circuits includes at least one stage second shift register unit
  • the gate driving module further includes a control circuit
  • Each of the at least one first shift register unit is connected to a gate line in a first sub display region of the plurality of sub display regions;
  • Each of the at least one second shift register unit is respectively connected to a clock signal line and a gate line disposed in a second sub-display area of the plurality of sub-display areas, for Generating a gate drive signal output to the gate line according to a voltage signal on the clock signal line;
  • the control circuit is configured to control the clock when the display panel is in a folded state and when a second one of the at least one second shift register unit performs a gate drive scan
  • the signal line provides a first voltage signal such that the second shift register unit controls the gate line to emit a signal that causes the corresponding transistor of the gate line to be turned OFF.
  • the gate driving module of the embodiment of the present disclosure does not physically divide the gate driving circuit.
  • the first shift register sub-circuit and the second The shift register sub-circuits are cascaded with each other, but when the display panel is in a folded state, the second shift register unit is controlled by the control circuit (eg, the second shift register unit corresponds to the second sub-display) a region, the second sub-display region is a sub-display region that is not displayed when the display panel is in a folded state, and when the gate driving scan is performed, the control provides a first voltage signal to the clock signal line, so that the second shift The bit register unit controls the gate line to emit a signal that causes the transistor corresponding to the gate line to be turned off, so that the second sub-display area does not display a picture, and the split screen display when the display panel is in the folded state can be realized by adjusting the timing, and Saves power consumption of the gate drive.
  • the display panel may be, for example, a flexible display panel, for example, can be folded, or can be bent, so as to be in a non-planar state, but not limited thereto.
  • the first voltage signal is a high voltage signal, so that the transistor is turned off.
  • the transistor connected to the gate line included in the sub-pixel of the AA area of the display panel is an n-type transistor
  • the first voltage signal is a low voltage signal to turn the transistor off.
  • the display panel 10 when the display panel 10 is in an unfolded state (ie, a planar state), the display panel 10 includes a display area 11, and in FIG. 1, a broken line is shown by a broken line.
  • the display area when the display panel 10 is in a folded state, the display area forms a first sub-display area 20 through the folding axis (when the display panel 10 is in a folded state)
  • the first sub-display area 20 is a front display area of a normal display screen) and a second sub-display area (when the display panel 10 is in a folded state (ie, a non-planar state)
  • the second sub-display area is folded to the back side, the second sub-display area is not shown in FIG. 2, and in FIG. 2, the broken line is shown by a broken line.
  • the number of the folding shafts may be not only one, and the gate driving module in the embodiment of the present disclosure may also include at least two folding axes, when the display panel 10 is in a folded state, The display area 11 can form at least three sub-display areas by the at least two folding axes.
  • the gate driving module according to the embodiment of the present disclosure includes two folding axes, when the display panel is in a folded state, two first sub-display regions for normal display when folding may be formed, and A second sub-display area that is not used for display when folded, but is not limited to this.
  • the number of the folding axes is one
  • the number of the first shift register sub-circuits is one
  • the number of the second shift register sub-circuits is one.
  • the first shift register sub-circuit includes a gate drive signal output end of the last stage first shift register unit and an input of the first stage second shift register unit included in the second shift register sub-circuit End connection.
  • the second shift register sub-circuit includes a gate drive signal output end of the first stage second shift register unit and a reset of the last stage first shift register unit included in the first shift register sub-circuit End connection.
  • the first shift register sub-circuit includes the first stage of the first shift register unit and the second shift register sub-circuit including the first level
  • the two shift register units are connected to each other such that the first shift register sub-circuit and the second shift register sub-circuit are cascaded with each other.
  • the number of the folding axes is two
  • the number of the first shift register sub-circuits and the number of the first sub-display areas are two
  • the number A shift register sub-circuit is in one-to-one correspondence with the first sub-display area.
  • the number of the second shift register sub-circuits and the number of the second sub-display areas are both one.
  • the first one of the first shift register sub-circuits includes a gate drive signal output end of the first stage first shift register unit and a first stage second of the second shift register sub-circuit The input terminals of the shift register unit are connected.
  • the second shift register sub-circuit includes a gate drive signal output end of the first stage second shift register unit and a first stage first shift included in the first one of the first shift register sub-circuits The reset terminal of the bit register unit is connected.
  • the second shift register sub-circuit includes a gate drive signal output end of the last stage second shift register unit and a first stage first shift included in the second first shift register sub-circuit The input of the bit register unit is connected.
  • the second first shift register sub-circuit includes a gate drive signal output end of the first stage first shift register unit and a second stage shift included in the second shift register sub-circuit The reset terminal of the bit register unit is connected.
  • the gate driving module of the embodiment of the present disclosure includes two first shift register sub-circuits and one second shift register sub-circuit, and the first first shift register sub-circuit and the second shift The bit register sub-circuits are cascaded with each other, and the second shift register sub-circuit is cascaded with the second first shift register sub-circuit.
  • the first shift register unit is further connected to the clock signal line, and configured to generate, according to a voltage signal on the clock signal line, an output to a gate of a gate line connected to the first shift register unit. Drive signal.
  • the control circuit is further configured to: when the display panel is in a folded state, and when the first shift register unit performs a gate drive scan, control to provide a clock signal to the clock signal line, so that the A shift register unit controls the gate lines to signal that the transistors corresponding to the gate lines are turned "ON".
  • the control circuit When the display panel is in a folded state (ie, a non-planar state), when the first shift register unit corresponding to the first sub-display area of the normal display screen performs gate drive scanning, the control circuit normally supplies a clock to the clock signal line. And a signal, so that the first shift register unit control gate line emits a signal that causes a transistor corresponding to the gate line to be turned ON, and the first sub display area normally displays a picture.
  • control circuit is further configured to: when the display panel is in an unfolded state (ie, a planar state), control to provide a clock signal to the clock signal line, so that when the first shift register unit performs a gate
  • the first shift register unit controls the gate line to emit a signal that causes the transistor corresponding to the gate line to be turned ON
  • the second shift register unit performs gate drive scan
  • the first The two shift register unit control gate lines emit signals that cause the transistors corresponding to the gate lines to be turned "ON".
  • control circuit 30 controls the clock signal to be normally supplied to the clock signal line, so that the display area of the display panel normally displays the screen.
  • control circuit 30 can be implemented, for example, by an IC chip, including a memory storing an associated computer program and a processor for retrieving the computer program and performing related processing to cause the control circuit 30 by executing a computer program.
  • the control is normally provided to provide a clock signal to the clock signal line, so that the display area of the display panel displays the picture normally.
  • the gate driving module of the present disclosure may further include a detecting circuit 40 .
  • the detecting circuit 40 is configured to detect that the display panel is in a folded state or an expanded state, generate a corresponding status indication signal, and transmit the status indication signal to the control circuit 30.
  • the gate driving module of the embodiment of the present disclosure may further include a detecting circuit 40 to detect a state in which the display panel is located.
  • the detecting circuit 40 may be, for example, an electronic camera, a video camera, an image sensor or the like having a device that captures a real-time image or real-time status of the display panel.
  • control circuit 30 is further configured to control, in a black screen display period immediately before the folding time, and in a black screen display period immediately adjacent to the folding time,
  • the pixel-connected data lines provide a predetermined data voltage such that the sub-pixel displays a black picture.
  • the folding timing is a timing at which the control circuit starts controlling to supply a first voltage signal to the clock signal line.
  • the duration of the black screen display time period may be selected according to actual conditions.
  • the black screen display period can be a frame display time
  • the control circuit can display the time of one frame before the first voltage signal is supplied to the clock signal line, and control the sub-pixels in the second sub-display area. A black screen is displayed to prepare for entering the collapsed state.
  • the clock signal line may include a first clock signal line and a second clock signal line.
  • the first shift register sub-circuit includes an odd-numbered first shift register unit coupled to the first clock signal input, the first shift register sub-circuit including an even-numbered first shift register unit and The second clock signal input terminal is connected.
  • the first shift register sub-circuit includes a first shift register unit having an even number of stages, the second shift register sub-circuit including an odd-numbered second shift register unit and the first clock signal input End connection, the second shift register sub-circuit comprising an even-numbered second shift register unit is coupled to the second clock signal input.
  • the gate driving circuit in the gate driving module in the embodiment of the present disclosure includes an odd-numbered shift register.
  • the unit is connected to the first clock signal line, and the even-numbered shift register unit included in the gate driving circuit is connected to the second clock signal line.
  • the first shift register sub-circuit includes an even-numbered first shift register unit
  • the odd-numbered second shift register unit in the second shift register sub-circuit is an odd-numbered stage included in the gate drive circuit
  • the shift register unit, the even-numbered second shift register unit in the second shift register sub-circuit is an even-numbered shift register unit included in the gate drive circuit.
  • the clock signal line may include a first clock signal line and a second clock signal line.
  • the first shift register sub-circuit includes an odd-numbered first shift register unit coupled to the first clock signal input, the first shift register sub-circuit including an even-numbered first shift register unit and The second clock signal input terminal is connected.
  • the first shift register sub-circuit includes an odd number of stages of the first shift register unit
  • the second shift register sub-circuit includes an odd-numbered second shift register unit and the second clock signal input End connection, the second shift register sub-circuit comprising an even-numbered second shift register unit connected to the first clock signal input.
  • the gate driving circuit in the gate driving module in the embodiment of the present disclosure includes an odd-numbered shift register.
  • the unit is connected to the first clock signal line, and the even-numbered shift register unit included in the gate driving circuit is connected to the second clock signal line.
  • the gate driving circuit in the gate driving module in the embodiment of the present disclosure includes an odd-numbered shift register.
  • the unit is connected to the first clock signal line, and the even-numbered shift register unit included in the gate driving circuit is connected to the second clock signal line.
  • the first shift register sub-circuit includes an odd-numbered first shift register unit
  • the even-numbered second shift register unit in the second shift register sub-circuit is an odd-numbered stage included in the gate drive circuit
  • the shift register unit, the odd-numbered second shift register unit in the second shift register sub-circuit is an even-numbered shift register unit included in the gate drive circuit.
  • the number of clock signal lines used in the embodiments of the present disclosure may not be limited to two, but 2A clock signal lines may be used, and A is a positive integer.
  • the embodiment of the present disclosure adopts four clock signal lines, and the gate drive circuit includes a 4a-3th stage shift register unit connected to the first clock signal line, and the gate drive The circuit includes a 4a-2th stage shift register unit connected to the second clock signal line, and the gate drive circuit includes a 4a-1th stage shift register unit connected to the third clock signal line, the gate The pole drive circuit includes a 4th stage shift register unit connected to the fourth clock signal line, a being a positive integer, and 4a being less than or equal to the number of stages of the shift register unit included in the gate drive circuit.
  • the gate driving module of the present disclosure will be described below by way of a specific embodiment.
  • a specific embodiment of the gate driving module of the present disclosure is applied to a display panel, the display panel has a display area, and when the display panel is in a folded state, the display area forms a first sub-display through a folding axis a region and a second sub-display region, the gate driving module including a gate driving circuit.
  • the gate driving circuit includes a first shift register sub-circuit S1 and a second shift register sub-circuit S2 that are cascaded with each other;
  • the first shift register sub-circuit S1 includes an N-stage shift register unit
  • the first shift register unit of the first stage is denoted by S11
  • the first shift register unit of the second stage is denoted by S12
  • the first shift register unit S13 of the third stage is denoted by S13.
  • labeled S1N is the Nth stage first shift register unit; N is an odd number greater than 3;
  • the second shift register sub-circuit S2 includes a first stage second shift register unit S21, a second stage second shift register unit S22, a third stage second shift register unit S23, and a fourth level The second shift register unit S24 and the fifth stage second shift register unit S25.
  • the gate driving module further includes a control circuit 30;
  • S11 is correspondingly connected to a first gate line (not shown in FIG. 3) provided in the first sub-display area; S12 and a second gate line disposed in the first sub-display area (FIG. 3) Corresponding to the connection; S13 is correspondingly connected with a third gate line (not shown in FIG. 3) provided in the first sub-display area; S1N is disposed in the first sub-display area The Nth gate line (not shown in FIG. 3) is correspondingly connected;
  • S21 is correspondingly connected to a first gate line (not shown in FIG. 3) provided in the second sub-display area; S22 and a second gate line disposed in the second sub-display area (FIG. 3) Corresponding connection; S23 is correspondingly connected with a third gate line (not shown in FIG. 3) provided in the second sub-display area; S24 is disposed in the second sub-display area The fourth gate line (not shown in FIG. 3) is correspondingly connected; S25 is correspondingly connected to a fifth gate line (not shown in FIG. 3) provided in the second sub-display area.
  • S11 is connected to the first clock signal line CKB
  • S12 is connected to the second clock signal line CK
  • S13 is connected to the first clock signal line CKB
  • S1N is connected to the first clock signal line CKB
  • S21 is connected to the second clock signal line CK.
  • S22 is connected to the first clock signal line CKB
  • S23 is connected to the second clock signal line CK
  • S24 is connected to the first clock signal line CKB
  • S25 is connected to the second clock signal line CK.
  • the input terminal INPUT11 of S11 is connected to the start signal STV, the reset terminal RESET11 of S11 is connected to the gate drive signal output terminal OUT12 of S12, the input terminal INPUT12 of S12 is connected to the gate drive signal output terminal OUT11 of S11, and the reset end of S12 is connected.
  • RESET12 is connected to the gate drive signal output terminal OUT13 of S13, the input end of S13 is connected to the gate drive signal output terminal OUT12 of S12, the reset terminal RESET13 of S13 and the gate drive signal output of the fourth stage first shift register unit are output.
  • the terminal connection (the fourth stage first shift register unit is not shown in FIG.
  • the input terminal INPUT1N of the S1N is connected to the gate drive signal output end of the N-1th first shift register unit (FIG. 3)
  • the fourth stage first shift register unit is not shown, the reset terminal RESET1N of S1N is connected to the gate drive signal output terminal OUT21 of S21, and the input terminal INPUT21 of S21 is connected to the gate drive signal output terminal OUT1N of S1N, S21
  • the reset terminal RESET21 is connected to the gate drive signal output terminal OUT22 of S22, the input terminal INPUT22 of S22 is connected to the gate drive signal output terminal OUT21 of S21, and the reset terminal RESET22 of S22 is connected to the gate drive signal output terminal OUT23 of S23.
  • the input terminal INPUT23 of S23 is connected to the gate drive signal output terminal OUT22 of S22, the reset terminal RESET22 of S23 is connected to the gate drive signal output terminal OUT24 of S24, and the input terminal INPUT24 of S24 is connected to the gate drive signal output terminal OUT23 of S23.
  • the reset terminal RESET24 of S24 is connected to the gate drive signal output terminal OUT25 of S25, and the input terminal INPUT25 of S25 is connected to the gate drive signal output terminal OUT24 of S24.
  • the reset terminal RESET25 of S25 can be connected to an external reset signal (not shown in FIG. 3);
  • the control circuit 30 is connected to the first clock signal line CKB and the second clock signal line CK, respectively.
  • the control circuit 30 outputs a first clock signal to the CKB, and outputs a second clock signal to the CK, so that the gate of the S11 output through the OUT11 is output.
  • the pole drive signal, the gate drive signal output by S12 through OUT12, the gate drive signal output by S13 through OUT13, and the gate drive signal output by S1N through OUT1N sequentially control the gate line to be emitted so that the transistor corresponding to the gate line is turned on (ON) Signal that causes the first sub-display area to be displayed normally when the display panel is folded;
  • the control circuit 30 controls to supply high voltage signals to both CKB and CK (at this time, the gate and gate in the sub-pixel)
  • the line-connected transistor is a p-type transistor), and the gate lines of S21, S22, S23, S24, and S25 are controlled to emit signals for turning off the transistors corresponding to the gate lines, so that when the display panel is folded, the second sub-display area is not performed. display.
  • control circuit is connected to CK and CKB, respectively.
  • the control circuit 30 In the first display period t21, when S11, S12, S13, S1N perform gate drive scanning, the control circuit 30 outputs a first clock signal to CKB, and outputs a second clock signal to CK, so that S11 is output through OUT11.
  • the gate drive signal, the gate drive signal output by S12 through OUT12, the gate drive signal output by S13 through OUT13, and the gate drive signal output by S1N through OUT1N sequentially control the gate line to be emitted such that the transistor corresponding to the gate line is turned on ( ON) signal, such that the first sub-display area is normally displayed when the display panel is expanded;
  • the control circuit 30 In the second display period t22, when S21, S22, S23, S24, S25 perform gate drive scanning, the control circuit 30 outputs a first clock signal to CKB and a second clock signal to CK, so that S21 passes
  • the gate drive signal output from OUT21, the gate drive signal output from S22 through OUT22, the gate drive signal output from S23 through OUT23, the gate drive signal output from S24 through OUT24, and the gate drive signal output from S25 through OUT25 sequentially control the gate.
  • the line emits a signal that causes the corresponding transistor of the gate line to be turned ON, so that the second sub-display area performs normal display when the display panel is expanded.
  • the black state voltage may be written to the second sub display area, so as to be the second sub display for the folded state.
  • the area does not display the screen to prepare.
  • the gate driving module of the present disclosure when the display panel is in a folded state and needs to be displayed in a half screen, only the stop display period included in the frame display time Tz is required. T12, the high voltage signal can be output to the CKB and CK through the control circuit 30. Since the CK and CKB no longer output pulse signals, the power consumption of the gate drive can be saved.
  • the embodiment of the present disclosure adjusts from the timing to realize the half screen display, and can realize the position of freely adjusting the half screen display, for example, adjusting the position where the folding axis is located from the Nth row gate line in the display area to the display area In the Mth row of the gate line (M is a positive integer), it is only necessary to adjust the timing of the signal on the CK and the timing of the signal on the CKB to improve the compatibility of the display panel.
  • the gate driving control method according to the embodiment of the present disclosure is applied to the above-described gate driving module, and the gate driving control method includes:
  • the control circuit controls to supply the first voltage signal to the clock signal line, so that the second shift register unit controls the gate line to be emitted.
  • the gate driving control method does not physically divide the gate driving circuit, but controls the second shift register unit to be gated by the control circuit when the display panel is in a folded state.
  • the pole drive scans, the first voltage signal is supplied to the clock signal line, so that the second shift register unit control gate line emits a signal that causes the transistor corresponding to the gate line to be turned OFF, so that the second sub display area
  • the screen is not displayed, and the split screen display when the display panel is in the folded state can be realized by adjusting the timing, and the power consumption of the gate drive can be saved.
  • the first shift register unit is further connected to the clock signal line; the gate drive control method further includes:
  • the control circuit controls to provide a clock signal to the clock signal line to cause the first shift
  • the register unit control gate line emits a signal that causes a transistor corresponding to the gate line to be turned ON.
  • the control circuit When the display panel is in the folded state, when the first shift register unit corresponding to the first sub display area of the normal display screen performs the gate drive scan, the control circuit normally supplies a clock signal to the clock signal line, so that the The first shift register unit controls the gate line to emit a signal that causes the transistor corresponding to the gate line to be turned ON, and the first sub-display area normally displays a picture.
  • the gate driving control method in the embodiment of the present disclosure may further include:
  • the control circuit controls to provide a clock signal to the clock signal line when the display panel is in an unfolded state, such that the first shift register unit when the first shift register unit performs gate drive scanning
  • the control gate line emits a signal that causes the corresponding transistor of the gate line to be turned ON, and when the second shift register unit performs gate drive scanning, the second shift register unit controls the gate line to emit The signal corresponding to the transistor of the gate line is turned ON.
  • control circuit controls to normally provide a clock signal to the clock signal line, so that the display area of the display panel normally displays the screen.
  • the gate driving module may further include a detecting circuit; the gate driving control method further includes:
  • the detecting circuit detects that the display panel is in a folded state or an expanded state, generates a corresponding status indication signal, and transmits the status indication signal to the control circuit.
  • the detection circuit may be, for example, an electronic camera, a video camera, an image sensor or the like having a device that captures a real-time image or real-time status of the display panel.
  • the gate driving control method in the embodiment of the present disclosure may further include:
  • the control circuit controls to supply a predetermined data voltage to the data line connected to the sub-pixels disposed in the second sub-display area before being set at the folding time and in a black picture display period immediately adjacent to the folding time Making the sub-pixel display a black picture;
  • the folding timing is a timing at which the control circuit starts controlling to supply a first voltage signal to the clock signal line.
  • the duration of the black screen display period may be selected according to actual conditions.
  • the black screen display period may be a frame display time
  • the control circuit may be before the first voltage signal is supplied to the clock signal line.
  • the display time of one frame is controlled, and the sub-pixels in the second sub-display area are controlled to display a black picture in order to prepare for entering the folded state.
  • the display device includes the above-described gate driving module.
  • the display device of the embodiment of the present disclosure may further include a driving integrated circuit and a plurality of gate lines extending in the first direction; the folding axis extending along the first direction; the gate A control circuit included in the driving module is disposed in the driving integrated circuit.
  • control circuit may be disposed in a driving IC (Integrated Circuit), and the folding axis and the plurality of gate lines may extend in the first direction.
  • driving IC Integrated Circuit
  • the gate driving circuit includes a gate driving circuit disposed in a peripheral region of the display panel pointed by the plurality of gate lines extending direction.
  • the plurality of gate lines are disposed longitudinally, and the gate driving module includes a gate driving circuit disposed on an upper side of the display panel or a lower side of the display panel, wherein the The longitudinal direction is substantially identical to the first direction.
  • the gate driving module may include only one gate driving circuit, and when the plurality of gate lines and the folding axis are longitudinally disposed, the gate driving circuit may be set The upper side of the display panel or the lower side of the display panel, wherein the longitudinal direction substantially coincides with the first direction.
  • the plurality of gate lines are longitudinally disposed, and the gate driving module includes two gate driving circuits, that is, a first gate driving circuit and a second gate driving circuit; a gate driving circuit is disposed on an upper side of the display panel, the first gate driving circuit includes a shift register unit connected to an upper end of the corresponding gate line; and the second gate driving circuit is disposed on the display panel
  • the lower side of the second gate driving circuit includes a shift register unit connected to a lower end of the corresponding gate line.
  • the gate driving module of the embodiment of the present disclosure may include two gate driving circuits: a first gate driving circuit disposed on an upper side of the display panel, and setting The second gate driving circuit on the lower side of the display panel, the first gate driving circuit and the second gate driving circuit simultaneously perform gate driving scanning on the gate lines.
  • the display panel 10 includes a display area 11 when the display panel 10 is in an unfolded state.
  • the broken line is shown by a broken line.
  • the sub display area on the left side of the folding axis is a first sub display area, and the sub display area on the right side of the folding axis is a second sub display area.
  • reference numeral 61 is a first gate driving circuit
  • 62 is a second gate driving circuit
  • DIC is a driving integrated circuit
  • the control circuit is, for example, disposed on the driving integrated circuit.
  • the first gate driving circuit 61 includes a multi-stage shift register unit (not shown in FIG. 6) that are cascaded with each other, and the second gate driving circuit 62 includes a multi-stage shift register unit that is cascaded with each other ( Not shown in Figure 6).
  • both the first gate driving circuit and the second gate driving circuit may be a GOA (Gate On Array).
  • the display device may be, for example, an electronic paper, an OLED (Organic Light-Emitting Diode) display device, an LCD (Liquid Crystal Display) device, a mobile phone, a tablet computer, a television, a display, a notebook computer, Any product or component with display function such as digital photo frame and navigator

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Abstract

一种栅极驱动模组，包括栅极驱动电路，栅极驱动电路包括相互级联的第一移位寄存器子电路（S1）和第二移位寄存器子电路（S2）；栅极驱动模组还包括控制电路（30）；第一移位寄存器单元（S11~S1N）与设于第一子显示区域中的栅线对应连接；第二移位寄存器单元（S21~S25）分别与时钟信号线（CK,CKB）和设于第二子显示区域中的栅线对应连接，用于根据时钟信号线（CK,CKB）上的电压信号生成输出至栅线的栅极驱动信号；控制电路（30）用于当显示面板（10）处于非平面状态时，并当第二移位寄存器单元（S21~S25）进行栅极驱动扫描时，控制向时钟信号线（CK,CKB）提供第一电压信号，以使得第二移位寄存器单元（S21~S25）控制栅线发出使得栅线对应的晶体管关闭的信号。

Description

栅极驱动模组、栅极驱动控制方法和显示装置
相关申请的交叉引用
本申请主张在2018年4月13日在中国提交的中国专利申请号No.201810329788.9的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示驱动技术领域，尤其涉及一种栅极驱动模组、栅极驱动控制方法和显示装置。
背景技术
柔性显示面板可以进行折叠，可以应用于折叠终端中。所述折叠终端例如可以为折叠手机，折叠平板等。通常，折叠终端会面临一个问题，展开时需要前后两面显示，折叠时只需要其中一面显示。为了降低功耗，需要将不显示区域对应的移位寄存器单元的信号输出关掉。现有的解决方法是根据折叠时的显示面板的至少两个子显示区域，采用相应的至少两个栅极驱动电路，这样每一个栅极驱动电路可以分别控制一个子显示区域。但是此方法需要驱动IC(Integrated Circuit，集成电路)支持更多的时钟信号和起始信号，并且同时该至少两个栅极驱动电路之间并无级联关系，在栅极驱动扫描时容易发生时钟错位，且至少两个栅极驱动电路之间的Gate Loading(栅线负载)也会存在差异，从而引起全屏显示时，至少两个子显示区域存在分屏的现象。
发明内容
在第一个方面中，本公开实施例提供了一种栅极驱动模组，应用于显示面板，所述显示面板具有显示区域，当所述显示面板处于非平面状态时，所述显示区域形成多个子显示区域，所述栅极驱动模组包括栅极驱动电路，其中，所述栅极驱动电路包括相互级联的多个移位寄存器子电路；所述多个移位寄存器子电路中的第一移位寄存器子电路包括至少一级第一移位寄存器单元，所述多个移位寄存器子电路中的第二移位寄存器子电路包括至少一级第 二移位寄存器单元；所述栅极驱动模组还包括控制电路。所述至少一级第一移位寄存器单元中的每一个第一移位寄存器单元与设于所述多个子显示区域中的第一子显示区域中的栅线对应连接；所述至少一级第二移位寄存器单元中的每一个第二移位寄存器单元分别与时钟信号线和设于所述多个子显示区域中的第二子显示区域中的栅线对应连接，用于根据所述时钟信号线上的电压信号生成输出至该栅线的栅极驱动信号；并且所述控制电路用于当所述显示面板处于非平面状态时，并当所述至少一级第二移位寄存器单元中的一个第二移位寄存器单元进行栅极驱动扫描时，控制向所述时钟信号线提供第一电压信号，以使得该第二移位寄存器单元控制栅线发出使得所述栅线对应的晶体管关闭(OFF)的信号。
根据本公开的一些实施例，当所述显示面板处于所述非平面状态时，所述显示面板被折叠，并且所述显示区域通过一个或多个折叠轴形成多个子显示区域；或者
当所述显示面板处于所述非平面状态时，所述显示面板被卷曲。
根据本公开的一些实施例，所述折叠轴的个数为一个，所述第一移位寄存器子电路的个数为一个，所述第二移位寄存器子电路的个数为一个；
所述第一移位寄存器子电路包括的最后一级第一移位寄存器单元的栅极驱动信号输出端与所述第二移位寄存器子电路包括的第一级第二移位寄存器单元的输入端连接；并且
所述第二移位寄存器子电路包括的第一级第二移位寄存器单元的栅极驱动信号输出端与所述第一移位寄存器子电路包括的最后一级第一移位寄存器单元的复位端连接。
根据本公开的一些实施例，所述折叠轴的个数为两个，所述第一移位寄存器子电路的个数和所述第一子显示区域的个数为两个，所述第一移位寄存器子电路与所述第一子显示区域一一对应；所述第二移位寄存器子电路的个数和所述第二子显示区域的个数为一个；
第一个所述第一移位寄存器子电路包括的最后一级第一移位寄存器单元的栅极驱动信号输出端与所述第二移位寄存器子电路包括的第一级第二移位寄存器单元的输入端连接；
所述第二移位寄存器子电路包括的第一级第二移位寄存器单元的栅极驱动信号输出端与第一个所述第一移位寄存器子电路包括的最后一级第一移位寄存器单元的复位端连接；
所述第二移位寄存器子电路包括的最后一级第二移位寄存器单元的栅极驱动信号输出端与第二个所述第一移位寄存器子电路包括的第一级第一移位寄存器单元的输入端连接；并且
第二个所述第一移位寄存器子电路包括的第一级第一移位寄存器单元的栅极驱动信号输出端与所述第二移位寄存器子电路包括的最后一级第二移位寄存器单元的复位端连接。
根据本公开的一些实施例，所述第一移位寄存器单元还与所述时钟信号线连接，用于根据所述时钟信号线上的电压信号生成输出至与该第一移位寄存器单元连接的栅线的栅极驱动信号；并且
所述控制电路还用于当所述显示面板处于非平面状态时，并当所述第一移位寄存器单元进行栅极驱动扫描时，控制向所述时钟信号线提供时钟信号，以使得所述第一移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号。
根据本公开的一些实施例，所述控制电路还用于当所述显示面板处于平面状态时，控制向所述时钟信号线提供时钟信号，以使得当所述第一移位寄存器单元进行栅极驱动扫描时，该第一移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号，并使得当所述第二移位寄存器单元进行栅极驱动扫描时，该第二移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号。
根据本公开的一些实施例，当所述显示面板处于所述平面状态时，所述显示面板从被折叠的状态恢复为展开状态；或者
当所述显示面板处于所述平面状态时，所述显示面板从被卷曲的状态恢复为展开状态。
根据本公开的一些实施例，所述栅极驱动模组还包括检测电路，所述检测电路用于检测所述显示面板处于非平面状态或平面状态，生成相应的状态指示信号，并将该状态指示信号传送至所述控制电路。
根据本公开的一些实施例，所述控制电路还用于在设置于非平面时刻之前，并与所述非平面时刻紧邻的一黑画面显示时间段内，控制向与设于所述第二子显示区域中的亚像素连接的数据线提供预定数据电压，以使得该亚像素显示黑画面；并且
所述非平面时刻为所述控制电路开始控制向所述时钟信号线提供第一电压信号的时刻。
根据本公开的一些实施例，所述时钟信号线包括第一时钟信号线和第二时钟信号线；
所述第一移位寄存器子电路包括的奇数级第一移位寄存器单元与所述第一时钟信号输入端连接，所述第一移位寄存器子电路包括的偶数级第一移位寄存器单元与所述第二时钟信号输入端连接；并且
所述第一移位寄存器子电路包括的第一移位寄存器单元的级数为偶数，所述第二移位寄存器子电路包括的奇数级第二移位寄存器单元与所述第一时钟信号输入端连接，所述第二移位寄存器子电路包括的偶数级第二移位寄存器单元与所述第二时钟信号输入端连接。
根据本公开的一些实施例，所述时钟信号线包括第一时钟信号线和第二时钟信号线；
所述第一移位寄存器子电路包括的奇数级第一移位寄存器单元与所述第一时钟信号输入端连接，所述第一移位寄存器子电路包括的偶数级第一移位寄存器单元与所述第二时钟信号输入端连接；并且
所述第一移位寄存器子电路包括的第一移位寄存器单元的级数为奇数，所述第二移位寄存器子电路包括的奇数级第二移位寄存器单元与所述第二时钟信号输入端连接，所述第二移位寄存器子电路包括的偶数级第二移位寄存器单元与所述第一时钟信号输入端连接。
在第二个方面中，本公开实施例提供了一种栅极驱动控制方法，所述栅极驱动控制方法应用于如在第一个方面中所述的栅极驱动模组，所述栅极驱动控制方法包括：
当显示面板处于非平面状态时，并当第二移位寄存器单元进行栅极驱动扫描时，控制电路控制向时钟信号线提供第一电压信号，以使得所述第二移 位寄存器单元控制栅线发出使得所述栅线对应的晶体管关闭(OFF)的信号。
根据本公开的一些实施例，第一移位寄存器单元还与所述时钟信号线连接；所述栅极驱动控制方法还包括：
当所述显示面板处于非平面状态时，并当所述第一移位寄存器单元进行栅极驱动扫描时，所述控制电路控制向所述时钟信号线提供时钟信号，以使得所述第一移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号。
根据本公开的一些实施例，所述栅极驱动控制方法还包括：
当所述显示面板处于平面状态时，所述控制电路控制向所述时钟信号线提供时钟信号，以使得当所述第一移位寄存器单元进行栅极驱动扫描时，该第一移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号，并使得当所述第二移位寄存器单元进行栅极驱动扫描时，该第二移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号。
根据本公开的一些实施例，所述栅极驱动模组还包括检测电路；所述栅极驱动控制方法还包括：
所述检测电路检测所述显示面板处于非平面状态或平面状态，生成相应的状态指示信号，并将该状态指示信号传送至所述控制电路。
根据本公开的一些实施例，所述栅极驱动控制方法还包括：
在设置于非平面时刻之前，并与所述非平面时刻紧邻的一黑画面显示时间段内，所述控制电路控制向与设于所述第二子显示区域中的亚像素连接的数据线提供预定数据电压，以使得该亚像素显示黑画面；并且
所述非平面时刻为所述控制电路开始控制向所述时钟信号线提供第一电压信号的时刻。
在第三个方面中，本公开实施例还提供了一种显示装置，包括如在第一个方面中所述的栅极驱动模组。
根据本公开的一些实施例，所述显示装置还包括驱动集成电路和多条栅线，所述多条栅线沿第一方向延伸；折叠轴沿所述第一方向延伸；所述栅极驱动模组包括的控制电路设置于所述驱动集成电路中。
根据本公开的一些实施例，所述栅极驱动模组包括的栅极驱动电路设置 于所述多条栅线延伸方向所指向的显示面板的周边区域内。
根据本公开的一些实施例，所述多条栅线纵向设置，所述栅极驱动模组包括的栅极驱动电路设置于显示面板的上侧边或所述显示面板的下侧边，其中所述纵向与所述第一方向实质上一致。
根据本公开的一些实施例，所述多条栅线纵向设置，所述栅极驱动模组包括两个栅极驱动电路；所述两个栅极驱动电路当中的第一栅极驱动电路设置于显示面板的上侧边，该栅极驱动电路包括的移位寄存器单元与对应的栅线的上端连接；所述两个栅极驱动电路当中的第二栅极驱动电路设置于所述显示面板的下侧边，该栅极驱动电路包括的移位寄存器单元与对应的栅线的下端连接，其中所述纵向与所述第一方向实质上一致。
根据本公开的一些实施例，所述第一栅极驱动电路和所述第二栅极驱动电路都是设置于阵列基板上的栅极驱动电路(GOA)。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例的描述中所需要使用的附图作简单地介绍，清楚地是，下面具体实施方式中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例所述的栅极驱动模组应用于的显示面板在展开(即平面状态)时的示意图；
图2是本公开实施例所述的栅极驱动模组应用于的显示面板在折叠(即非平面状态)时的示意图；
图3是本公开所述的栅极驱动模组的一具体实施例的结构图；
图4是本公开所述的栅极驱动模组的该具体实施例，在显示面板处于折叠状态时的工作时序图；
图5是本公开所述的栅极驱动模组的该具体实施例，在显示面板处于展开状态时的工作时序图；以及
图6是本公开实施例所述的显示装置的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。在实际操作时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第二极可以为漏极。
本公开实施例所述的栅极驱动模组，应用于显示面板，所述显示面板具有显示区域，当所述显示面板处于折叠状态时，所述显示区域通过一个或多个折叠轴形成多个子显示区域，所述栅极驱动模组包括栅极驱动电路；
所述栅极驱动电路包括相互级联的多个移位寄存器子电路；
所述多个移位寄存器子电路中的第一移位寄存器子电路包括至少一级第一移位寄存器单元；
所述多个移位寄存器子电路中的第二移位寄存器子电路包括至少一级第二移位寄存器单元；
所述栅极驱动模组还包括控制电路；
所述至少一级第一移位寄存器单元中的每一个第一移位寄存器单元与设于所述多个子显示区域中的第一子显示区域中的栅线对应连接；
所述至少一级第二移位寄存器单元中的每一个第二移位寄存器单元分别与时钟信号线和设于所述多个子显示区域中的第二子显示区域中的栅线对应连接，用于根据所述时钟信号线上的电压信号生成输出至该栅线的栅极驱动信号；并且
所述控制电路用于当所述显示面板处于折叠状态时，并当所述至少一级第二移位寄存器单元中的一个第二移位寄存器单元进行栅极驱动扫描时，控制向所述时钟信号线提供第一电压信号，以使得该第二移位寄存器单元控制栅线发出使得所述栅线对应的晶体管关闭(OFF)的信号。
本公开实施例所述的栅极驱动模组不在物理上对所述栅极驱动电路进行分割(在本公开实施例所述的栅极驱动模组中，第一移位寄存器子电路和第二移位寄存器子电路相互级联)，而是当所述显示面板处于折叠状态时，通过控制电路控制当第二移位寄存器单元(例如，所述第二移位寄存器单元对应于第二子显示区域，该第二子显示区域为所述显示面板处于折叠状态时不进行显示的子显示区域)进行栅极驱动扫描时，控制向时钟信号线提供第一电压信号，以使得所述第二移位寄存器单元控制栅线发出使得所述栅线对应的晶体管关闭的信号，使得第二子显示区域不显示画面，通过时序上的调整即可实现显示面板处于折叠状态时的分屏显示，并能够节省栅极驱动的功耗。
在具体实施时，所述显示面板可以例如为柔性显示面板，例如能够被折叠，或者能够被弯曲，从而处于非平面状态，但不以此为限。
在实际操作时，当显示面板的AA(Active Area，有效显示)区中亚像素包括的与栅线连接的晶体管为p型晶体管时，第一电压信号为高电压信号，以使得该晶体管断开。当显示面板的AA区中亚像素包括的与栅线连接的晶体管为n型晶体管时，第一电压信号为低电压信号，以使得该晶体管断开。由此可以看出，本公开各个实施例对于显示面板的AA区中亚像素包括的与栅线连接的晶体管的类型没有任何限制。
如图1所示，在显示面板10处于展开状态(即平面状态)时，所述显示面板10包括显示区域11，在图1中，虚线所示的为折叠轴。
如图2所示，根据一种具体实施方式，当所述显示面板10处于折叠状态时，所述显示区域通过所述折叠轴形成第一子显示区域20(当所述显示面板10处于折叠状态时，在图2所示的实施例中，所述第一子显示区域20为正常显示画面的正面显示区域)和第二子显示区域(当所述显示面板10处于折叠状态(即非平面状态)时，所述第二子显示区域被折叠至背面，因此图2中未示出所述第二子显示区域)，在图2中，虚线所示的为所述折叠轴。
在实际操作时，所述折叠轴的个数可以不仅为一个，本公开实施例所述的栅极驱动模组也可以包括至少两个折叠轴，当所述显示面板10处于折叠状态时，所述显示区域11通过所述至少两个折叠轴可以形成至少三个子显示区域。例如，当本公开实施例所述的栅极驱动模组包括两个折叠轴时，当所述 显示面板处于折叠状态时，可以形成两个折叠时用于正常显示的第一子显示区域，以及一个折叠时不用于显示的第二子显示区域，但不以此为限。
根据一种具体实施方式，所述折叠轴的个数为一个，所述第一移位寄存器子电路的个数为一个，所述第二移位寄存器子电路的个数为一个。
所述第一移位寄存器子电路包括的最后一级第一移位寄存器单元的栅极驱动信号输出端与所述第二移位寄存器子电路包括的第一级第二移位寄存器单元的输入端连接。
所述第二移位寄存器子电路包括的第一级第二移位寄存器单元的栅极驱动信号输出端与所述第一移位寄存器子电路包括的最后一级第一移位寄存器单元的复位端连接。
在显示面板处于折叠状态时仅分为两个半屏的情况下，第一移位寄存器子电路包括的最后一级第一移位寄存器单元与第二移位寄存器子电路包括的第一级第二移位寄存器单元相互连接，以使得所述第一移位寄存器子电路和所述第二移位寄存器子电路相互级联。
根据另一种具体实施方式，所述折叠轴的个数为两个，所述第一移位寄存器子电路的个数和所述第一子显示区域的个数为两个，并且所述第一移位寄存器子电路与所述第一子显示区域一一对应。此外，所述第二移位寄存器子电路的个数和所述第二子显示区域的个数均为一个。
具体的，第一个所述第一移位寄存器子电路包括的最后一级第一移位寄存器单元的栅极驱动信号输出端与所述第二移位寄存器子电路包括的第一级第二移位寄存器单元的输入端连接。
另外，所述第二移位寄存器子电路包括的第一级第二移位寄存器单元的栅极驱动信号输出端与第一个所述第一移位寄存器子电路包括的最后一级第一移位寄存器单元的复位端连接。
另外，所述第二移位寄存器子电路包括的最后一级第二移位寄存器单元的栅极驱动信号输出端与第二个所述第一移位寄存器子电路包括的第一级第一移位寄存器单元的输入端连接。
另外，第二个所述第一移位寄存器子电路包括的第一级第一移位寄存器单元的栅极驱动信号输出端与所述第二移位寄存器子电路包括的最后一级第 二移位寄存器单元的复位端连接。
作为本公开的另外一种可行实施方式，所述显示面板处于折叠状态时可以例如分为三个分屏，其中两个分屏用于正常显示，另外一个分屏不用于显示。也即本公开实施例所述的栅极驱动模组包括两个第一移位寄存器子电路和一个第二移位寄存器子电路，第一个第一移位寄存器子电路与所述第二移位寄存器子电路相互级联，所述第二移位寄存器子电路与第二个第一移位寄存器子电路相互级联。
具体的，所述第一移位寄存器单元还与所述时钟信号线连接，用于根据所述时钟信号线上的电压信号生成输出至与该第一移位寄存器单元连接的栅线的栅极驱动信号。
所述控制电路还用于当所述显示面板处于折叠状态时，并当所述第一移位寄存器单元进行栅极驱动扫描时，控制向所述时钟信号线提供时钟信号，以使得所述第一移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号。
当显示面板处于折叠状态(即非平面状态)时，当对应于正常显示画面的第一子显示区域的第一移位寄存器单元在进行栅极驱动扫描时，控制电路正常向时钟信号线提供时钟信号，以使得所述第一移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号，第一子显示区域正常显示画面。
具体的，所述控制电路还用于当所述显示面板处于展开状态(即平面状态)时，控制向所述时钟信号线提供时钟信号，以使得当所述第一移位寄存器单元进行栅极驱动扫描时，该第一移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号，并使得当所述第二移位寄存器单元进行栅极驱动扫描时，该第二移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号。
相应的，当显示面板处于展开状态时，如图3所示，控制电路30控制正常向时钟信号线提供时钟信号，使得显示面板的显示区域正常显示画面。
具体的，所述控制电路30可以例如由IC芯片来实现，其中包括存储有相关计算机程序的存储器和用于调取该计算机程序并执行相关处理的处理器， 以便通过执行计算机程序使得控制电路30实现控制正常向时钟信号线提供时钟信号，使得显示面板的显示区域正常显示画面。
在具体实施时，如图3所示，本公开所述的栅极驱动模组还可以包括检测电路40。所述检测电路40用于检测所述显示面板处于折叠状态或展开状态，生成相应的状态指示信号，并将该状态指示信号传送至所述控制电路30。
相应的，本公开实施例所述的栅极驱动模组还可以包括检测电路40，以检测显示面板处于的状态。
具体的，所述检测电路40可以例如是电子照相机、摄像机、图像传感器等具有捕获所述显示面板的实时图像或实时状态的设备。
在具体实施时，所述控制电路30还用于在设置于折叠时刻之前，并与该折叠时刻紧邻的一黑画面显示时间段内，控制向与设于所述第二子显示区域中的亚像素连接的数据线提供预定数据电压，以使得该亚像素显示黑画面。
例如，所述折叠时刻为所述控制电路开始控制向所述时钟信号线提供第一电压信号的时刻。
所述黑画面显示时间段持续的时间可以根据实际情况选定。例如，该黑画面显示时间段可以为一帧画面显示时间，所述控制电路可以在向时钟信号线提供第一电压信号之前的一帧画面显示时间，控制第二子显示区域中的亚像素都显示黑画面，以便为进入折叠状态做好准备。
根据一种具体实施方式，所述时钟信号线可以包括第一时钟信号线和第二时钟信号线。
所述第一移位寄存器子电路包括的奇数级第一移位寄存器单元与所述第一时钟信号输入端连接，所述第一移位寄存器子电路包括的偶数级第一移位寄存器单元与所述第二时钟信号输入端连接。
所述第一移位寄存器子电路包括的第一移位寄存器单元的级数为偶数，所述第二移位寄存器子电路包括的奇数级第二移位寄存器单元与所述第一时钟信号输入端连接，所述第二移位寄存器子电路包括的偶数级第二移位寄存器单元与所述第二时钟信号输入端连接。
在具体实施时，当所述时钟信号线包括第一时钟信号线和第二时钟信号线时，本公开实施例所述的栅极驱动模组中的栅极驱动电路包括的奇数级移 位寄存器单元与第一时钟信号线连接，该栅极驱动电路包括的偶数级移位寄存器单元与第二时钟信号线连接。当所述第一移位寄存器子电路包括偶数级第一移位寄存器单元时，则第二移位寄存器子电路中的奇数级第二移位寄存器单元为所述栅极驱动电路包括的奇数级移位寄存器单元，第二移位寄存器子电路中的偶数级第二移位寄存器单元为所述栅极驱动电路包括的偶数级移位寄存器单元。
根据另一种具体实施方式，所述时钟信号线可以包括第一时钟信号线和第二时钟信号线。
所述第一移位寄存器子电路包括的奇数级第一移位寄存器单元与所述第一时钟信号输入端连接，所述第一移位寄存器子电路包括的偶数级第一移位寄存器单元与所述第二时钟信号输入端连接。
所述第一移位寄存器子电路包括的第一移位寄存器单元的级数为奇数，所述第二移位寄存器子电路包括的奇数级第二移位寄存器单元与所述第二时钟信号输入端连接，所述第二移位寄存器子电路包括的偶数级第二移位寄存器单元与所述第一时钟信号输入端连接。
在具体实施时，当所述时钟信号线包括第一时钟信号线和第二时钟信号线时，本公开实施例所述的栅极驱动模组中的栅极驱动电路包括的奇数级移位寄存器单元与第一时钟信号线连接，该栅极驱动电路包括的偶数级移位寄存器单元与第二时钟信号线连接。
在具体实施时，当所述时钟信号线包括第一时钟信号线和第二时钟信号线时，本公开实施例所述的栅极驱动模组中的栅极驱动电路包括的奇数级移位寄存器单元与第一时钟信号线连接，该栅极驱动电路包括的偶数级移位寄存器单元与第二时钟信号线连接。当所述第一移位寄存器子电路包括奇数级第一移位寄存器单元时，则第二移位寄存器子电路中的偶数级第二移位寄存器单元为所述栅极驱动电路包括的奇数级移位寄存器单元，第二移位寄存器子电路中的奇数级第二移位寄存器单元为所述栅极驱动电路包括的偶数级移位寄存器单元。
在实际操作时，本公开实施例采用的时钟信号线的条数可以不限于两条，而是可以采用2A条时钟信号线，A为正整数。例如，当A等于2时，本公 开实施例采用四条时钟信号线，则所述栅极驱动电路包括的第4a-3级移位寄存器单元与第一条时钟信号线连接，所述栅极驱动电路包括的第4a-2级移位寄存器单元与第二条时钟信号线连接，所述栅极驱动电路包括的第4a-1级移位寄存器单元与第三条时钟信号线连接，所述栅极驱动电路包括的第4a级移位寄存器单元与第四条时钟信号线连接，a为正整数，4a小于或等于所述栅极驱动电路包括的移位寄存器单元的级数。
下面通过一具体实施例来说明本公开所述的栅极驱动模组。
本公开所述的栅极驱动模组的一具体实施例应用于显示面板，所述显示面板具有显示区域，当所述显示面板处于折叠状态时，所述显示区域通过折叠轴形成第一子显示区域和第二子显示区域，所述栅极驱动模组包括栅极驱动电路。
如图3所示，所述栅极驱动电路包括相互级联的第一移位寄存器子电路S1和第二移位寄存器子电路S2；
所述第一移位寄存器子电路S1包括N级移位寄存器单元；
在图3中，标号为S11的为第一级第一移位寄存器单元、标号为S12的为第二级第一移位寄存器单元，标号为S13的为第三级第一移位寄存器单元S13，标号为S1N的为第N级第一移位寄存器单元；N为大于3的奇数；
同样，所述第二移位寄存器子电路S2包括第一级第二移位寄存器单元S21、第二级第二移位寄存器单元S22、第三级第二移位寄存器单元S23、第四级第二移位寄存器单元S24、第五级第二移位寄存器单元S25。
如图3所示，所述栅极驱动模组还包括控制电路30；
S11与设于所述第一子显示区域中的第一条栅线(图3中未示出)对应连接；S12与设于所述第一子显示区域中的第二条栅线(图3中未示出)对应连接；S13与设于所述第一子显示区域中的第三条栅线(图3中未示出)对应连接；S1N与设于所述第一子显示区域中的第N条栅线(图3中未示出)对应连接；
S21与设于所述第二子显示区域中的第一条栅线(图3中未示出)对应连接；S22与设于所述第二子显示区域中的第二条栅线(图3中未示出)对应连接；S23与设于所述第二子显示区域中的第三条栅线(图3中未示出) 对应连接；S24与设于所述第二子显示区域中的第四条栅线(图3中未示出)对应连接；S25与设于所述第二子显示区域中的第五条栅线(图3中未示出)对应连接。
S11与第一时钟信号线CKB连接，S12与第二时钟信号线CK连接，S13与第一时钟信号线CKB连接，S1N与第一时钟信号线CKB连接，S21与第二时钟信号线CK连接，S22与第一时钟信号线CKB连接，S23与第二时钟信号线CK连接，S24与第一时钟信号线CKB连接，S25与第二时钟信号线CK连接。
S11的输入端INPUT11接入起始信号STV，S11的复位端RESET11与S12的栅极驱动信号输出端OUT12连接，S12的输入端INPUT12与S11的栅极驱动信号输出端OUT11连接，S12的复位端RESET12与S13的栅极驱动信号输出端OUT13连接，S13的输入端与S12的栅极驱动信号输出端OUT12连接，S13的复位端RESET13与第四级第一移位寄存器单元的栅极驱动信号输出端连接(图3中未示出该第四级第一移位寄存器单元)，S1N的输入端INPUT1N与第N-1级第一移位寄存器单元的栅极驱动信号输出端连接(图3中未示出该第四级第一移位寄存器单元)，S1N的复位端RESET1N与S21的栅极驱动信号输出端OUT21连接，S21的输入端INPUT21与S1N的栅极驱动信号输出端OUT1N连接，S21的复位端RESET21与S22的栅极驱动信号输出端OUT22连接，S22的输入端INPUT22与S21的栅极驱动信号输出端OUT21连接，S22的复位端RESET22与S23的栅极驱动信号输出端OUT23连接，S23的输入端INPUT23与S22的栅极驱动信号输出端OUT22连接，S23的复位端RESET22与S24的栅极驱动信号输出端OUT24连接，S24的输入端INPUT24与S23的栅极驱动信号输出端OUT23连接，S24的复位端RESET24与S25的栅极驱动信号输出端OUT25连接，S25的输入端INPUT25与S24的栅极驱动信号输出端OUT24连接。
另外，S25的复位端RESET25可以接入外部复位信号(图3中未示出)；
所述控制电路30分别与第一时钟信号线CKB和第二时钟信号线CK连接。
如图4所示，当所述显示面板处于折叠状态时，在一帧画面显示时间Tz 内，
在显示时间段t11，当S11、S12、S13、S1N进行栅极驱动扫描时，所述控制电路30向CKB输出第一时钟信号，向CK输出第二时钟信号，以使得S11通过OUT11输出的栅极驱动信号、S12通过OUT12输出的栅极驱动信号、S13通过OUT13输出的栅极驱动信号、S1N通过OUT1N输出的栅极驱动信号依次控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号，使得在显示面板折叠时第一子显示区域进行正常显示；以及
在停止显示时间段t12，当S21、S22、S23、S24、S25进行栅极驱动扫描时，所述控制电路30控制向CKB和CK都提供高电压信号(此时亚像素中的栅极与栅线连接的晶体管为p型晶体管)，以S21、S22、S23、S24、S25控制栅线发出使得所述栅线对应的晶体管关闭的信号，使得在显示面板折叠时，第二子显示区域不进行显示。
在具体实施时，所述控制电路分别与CK与CKB连接。
如图5所示，当所述显示面板处于展开状态时，在一帧画面显示时间Tz内，
在第一显示时间段t21，当S11、S12、S13、S1N进行栅极驱动扫描时，所述控制电路30向CKB输出第一时钟信号，向CK输出第二时钟信号，以使得S11通过OUT11输出的栅极驱动信号、S12通过OUT12输出的栅极驱动信号、S13通过OUT13输出的栅极驱动信号、S1N通过OUT1N输出的栅极驱动信号依次控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号，使得在显示面板展开时第一子显示区域进行正常显示；以及
在第二显示时间段t22，当S21、S22、S23、S24、S25进行栅极驱动扫描时，所述控制电路30向CKB输出第一时钟信号，向CK输出第二时钟信号，以使得S21通过OUT21输出的栅极驱动信号、S22通过OUT22输出的栅极驱动信号、S23通过OUT23输出的栅极驱动信号、S24通过OUT24输出的栅极驱动信号、S25通过OUT25输出的栅极驱动信号依次控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号，使得在显示面板展开时第二子显示区域进行正常显示。
在具体实施时，在所述控制电路30向CK和CKB提供高电压信号的前 一帧画面显示时间，可以对第二子显示区域写入黑态电压，以便为进行折叠状态时第二子显示区域不显示画面做准备。
本公开所述的栅极驱动模组的该具体实施例在工作时，当所述显示面板处于折叠状态，需要进行半屏显示时，只需要在一帧画面显示时间Tz包括的停止显示时间段t12，通过控制电路30向CKB和CK输出高电压信号即可。由于CK和CKB不再输出脉冲信号，因此可以节省栅极驱动的功耗。本公开实施例是从时序上调整以实现半屏显示，可以实现自由调节半屏显示的位置，譬如将折叠轴所在的位置从所述显示区域中的第N行栅线调整至所述显示区域中的第M行栅线(M为正整数)，只需要调整CK上的信号的时序和CKB上的信号的时序即可，提升显示面板的兼容性。
本公开实施例所述的栅极驱动控制方法应用于上述的栅极驱动模组，所述栅极驱动控制方法包括：
当显示面板处于折叠状态时，并当第二移位寄存器单元进行栅极驱动扫描时，控制电路控制向时钟信号线提供第一电压信号，以使得所述第二移位寄存器单元控制栅线发出使得所述栅线对应的晶体管关闭(OFF)的信号。
本公开实施例所述的栅极驱动控制方法不在物理上对所述栅极驱动电路进行分割，而是当所述显示面板处于折叠状态时，通过控制电路控制当第二移位寄存器单元进行栅极驱动扫描时，向时钟信号线提供第一电压信号，以使得所述第二移位寄存器单元控制栅线发出使得所述栅线对应的晶体管关闭(OFF)的信号，使得第二子显示区域不显示画面，通过时序上的调整即可实现显示面板处于折叠状态时的分屏显示，并能够节省栅极驱动的功耗。
在实际操作时，第一移位寄存器单元还与所述时钟信号线连接；所述栅极驱动控制方法还包括：
当所述显示面板处于折叠状态时，并当所述第一移位寄存器单元进行栅极驱动扫描时，所述控制电路控制向所述时钟信号线提供时钟信号，以使得所述第一移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号。
当显示面板处于折叠状态时，当对应于正常显示画面的第一子显示区域的第一移位寄存器单元在进行栅极驱动扫描时，控制电路正常向时钟信号线 提供时钟信号，以使得所述第一移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号，第一子显示区域正常显示画面。
具体的，本公开实施例所述的栅极驱动控制方法还可以包括：
当所述显示面板处于展开状态时，所述控制电路控制向所述时钟信号线提供时钟信号，以使得当所述第一移位寄存器单元进行栅极驱动扫描时，该第一移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号，并使得当所述第二移位寄存器单元进行栅极驱动扫描时，该第二移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号。
当显示面板处于展开状态时，控制电路控制正常向时钟信号线提供时钟信号，使得显示面板的显示区域正常显示画面。
具体的，所述栅极驱动模组还可以包括检测电路；所述栅极驱动控制方法还包括：
所述检测电路检测所述显示面板处于折叠状态或展开状态，生成相应的状态指示信号，并将该状态指示信号传送至所述控制电路。
具体的，所述检测电路可以例如是电子照相机、摄像机、图像传感器等具有捕获所述显示面板的实时图像或实时状态的设备。
在具体实施时，本公开实施例所述的栅极驱动控制方法还可以包括：
在设置于折叠时刻之前，并与该折叠时刻紧邻的一黑画面显示时间段内，控制电路控制向与设于所述第二子显示区域中的亚像素连接的数据线提供预定数据电压，以使得该亚像素显示黑画面；
所述折叠时刻为所述控制电路开始控制向所述时钟信号线提供第一电压信号的时刻。
所述黑画面显示时间段持续的时间可以根据实际情况选定，例如，该黑画面显示时间段可以为一帧画面显示时间，所述控制电路可以在向时钟信号线提供第一电压信号之前的一帧画面显示时间，控制第二子显示区域中的亚像素都显示黑画面，以便为进入折叠状态做准备。
本公开实施例所述的显示装置包括上述的栅极驱动模组。
具体的，本公开实施例所述的显示装置还可以包括驱动集成电路和多条栅线，所述多条栅线沿第一方向延伸；折叠轴沿所述第一方向延伸；所述栅 极驱动模组包括的控制电路设置于所述驱动集成电路中。
在具体实施时，所述控制电路可以设置于驱动IC(Integrated Circuit，集成电路)中，所述折叠轴和所述多条栅线可以一样沿第一方向延伸。
在具体实施时，所述栅极驱动模组包括的栅极驱动电路可以设置于所述多条栅线延伸方向指向的显示面板的周边区域内。
根据一种具体实施方式，所述多条栅线纵向设置，所述栅极驱动模组包括的栅极驱动电路设置于显示面板的上侧边或所述显示面板的下侧边，其中所述纵向与所述第一方向实质上一致。
当所述显示面板的尺寸较小时，所述栅极驱动模组可以仅包括一个栅极驱动电路，当所述多条栅线和所述折叠轴都纵向设置时，该栅极驱动电路可以设置于显示面板的上侧边或所述显示面板的下侧边，其中所述纵向与所述第一方向实质上一致。
根据另一种具体实施方式，所述多条栅线纵向设置，所述栅极驱动模组包括两个栅极驱动电路，即第一栅极驱动电路和第二栅极驱动电路；所述第一栅极驱动电路设置于显示面板的上侧边，该第一栅极驱动电路包括的移位寄存器单元与对应的栅线的上端连接；所述第二栅极驱动电路设置于所述显示面板的下侧边，该第二栅极驱动电路包括的移位寄存器单元与对应的栅线的下端连接。
当所述显示面板的尺寸较大时，本公开实施例所述的栅极驱动模组可以包括两个栅极驱动电路：设置于显示面板的上侧边的第一栅极驱动电路，以及设置于显示面板的下侧边的第二栅极驱动电路，第一栅极驱动电路和第二栅极驱动电路同时对栅线进行栅极驱动扫描。
如图6所示，在显示面板10处于展开状态时，所述显示面板10包括显示区域11。在图6中，虚线所示的为折叠轴。所述折叠轴左侧的子显示区域为第一子显示区域，所述折叠轴右侧的子显示区域为第二子显示区域。
在图6中，标号为61的为第一栅极驱动电路，标号为62的为第二栅极驱动电路，标号为DIC的为驱动集成电路，所述控制电路例如设置于所述驱动集成电路DIC中。
所述第一栅极驱动电路61包括相互级联的多级移位寄存器单元(图6中 未示出)，所述第二栅极驱动电路62包括相互级联的多级移位寄存器单元(图6中未示出)。
在实际操作时，所述第一栅极驱动电路和所述第二栅极驱动电路都可以为GOA(Gate On Array，设置于阵列基板上的栅极驱动电路)。
所述显示装置例如可以为：电子纸、OLED(Organic Light-Emitting Diode，有机发光二极管)显示装置、LCD(Liquid Crystal Display，液晶显示)装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件
以上所述是本公开的一些可选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (22)

  1. 一种栅极驱动模组，应用于显示面板，所述显示面板具有显示区域，当所述显示面板处于非平面状态时，所述显示区域形成多个子显示区域，所述栅极驱动模组包括栅极驱动电路，其中，所述栅极驱动电路包括相互级联的多个移位寄存器子电路；所述多个移位寄存器子电路中的第一移位寄存器子电路包括至少一级第一移位寄存器单元，所述多个移位寄存器子电路中的第二移位寄存器子电路包括至少一级第二移位寄存器单元；所述栅极驱动模组还包括控制电路；
    所述至少一级第一移位寄存器单元中的每一个第一移位寄存器单元与设于所述多个子显示区域中的第一子显示区域中的栅线对应连接；
    所述至少一级第二移位寄存器单元中的每一个第二移位寄存器单元分别与时钟信号线和设于所述多个子显示区域中的第二子显示区域中的栅线对应连接，用于根据所述时钟信号线上的电压信号生成输出至该栅线的栅极驱动信号；并且
    所述控制电路用于当所述显示面板处于非平面状态时，并当所述至少一级第二移位寄存器单元中的一个第二移位寄存器单元进行栅极驱动扫描时，控制向所述时钟信号线提供第一电压信号，以使得该第二移位寄存器单元控制栅线发出使得所述栅线对应的晶体管关闭(OFF)的信号。
  2. 如权利要求1所述的栅极驱动模组，其中，当所述显示面板处于所述非平面状态时，所述显示面板被折叠，并且所述显示区域通过一个或多个折叠轴形成多个子显示区域；或者
    当所述显示面板处于所述非平面状态时，所述显示面板被卷曲。
  3. 如权利要求2所述的栅极驱动模组，其中，所述折叠轴的个数为一个，所述第一移位寄存器子电路的个数为一个，所述第二移位寄存器子电路的个数为一个；
    所述第一移位寄存器子电路包括的最后一级第一移位寄存器单元的栅极驱动信号输出端与所述第二移位寄存器子电路包括的第一级第二移位寄存器单元的输入端连接；并且
    所述第二移位寄存器子电路包括的第一级第二移位寄存器单元的栅极驱动信号输出端与所述第一移位寄存器子电路包括的最后一级第一移位寄存器单元的复位端连接。
  4. 如权利要求2所述的栅极驱动模组，其中，所述折叠轴的个数为两个，所述第一移位寄存器子电路的个数和所述第一子显示区域的个数为两个，所述第一移位寄存器子电路与所述第一子显示区域一一对应；所述第二移位寄存器子电路的个数和所述第二子显示区域的个数为一个；
    第一个所述第一移位寄存器子电路包括的最后一级第一移位寄存器单元的栅极驱动信号输出端与所述第二移位寄存器子电路包括的第一级第二移位寄存器单元的输入端连接；
    所述第二移位寄存器子电路包括的第一级第二移位寄存器单元的栅极驱动信号输出端与第一个所述第一移位寄存器子电路包括的最后一级第一移位寄存器单元的复位端连接；
    所述第二移位寄存器子电路包括的最后一级第二移位寄存器单元的栅极驱动信号输出端与第二个所述第一移位寄存器子电路包括的第一级第一移位寄存器单元的输入端连接；并且
    第二个所述第一移位寄存器子电路包括的第一级第一移位寄存器单元的栅极驱动信号输出端与所述第二移位寄存器子电路包括的最后一级第二移位寄存器单元的复位端连接。
  5. 如权利要求1至4中任一项权利要求所述的栅极驱动模组，其中，所述第一移位寄存器单元还与所述时钟信号线连接，用于根据所述时钟信号线上的电压信号生成输出至与该第一移位寄存器单元连接的栅线的栅极驱动信号；并且
    所述控制电路还用于当所述显示面板处于非平面状态时，并当所述第一移位寄存器单元进行栅极驱动扫描时，控制向所述时钟信号线提供时钟信号，以使得所述第一移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号。
  6. 如权利要求1至5中任一项权利要求所述的栅极驱动模组，其中，所述控制电路还用于当所述显示面板处于平面状态时，控制向所述时钟信号线 提供时钟信号，以使得当所述第一移位寄存器单元进行栅极驱动扫描时，该第一移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号，并使得当所述第二移位寄存器单元进行栅极驱动扫描时，该第二移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号。
  7. 如权利要求6所述的栅极驱动模组，其中，当所述显示面板处于所述平面状态时，所述显示面板从被折叠的状态恢复为展开状态；或者
    当所述显示面板处于所述平面状态时，所述显示面板从被卷曲的状态恢复为展开状态。
  8. 如权利要求1至7中任一项权利要求所述的栅极驱动模组，其中，所述栅极驱动模组还包括检测电路，所述检测电路用于检测所述显示面板处于非平面状态或平面状态，生成相应的状态指示信号，并将该状态指示信号传送至所述控制电路。
  9. 如权利要求1至8中任一项权利要求所述的栅极驱动模组，其中，所述控制电路还用于在设置于非平面时刻之前，并与所述非平面时刻紧邻的一黑画面显示时间段内，控制向与设于所述第二子显示区域中的亚像素连接的数据线提供预定数据电压，以使得该亚像素显示黑画面；并且
    所述非平面时刻为所述控制电路开始控制向所述时钟信号线提供第一电压信号的时刻。
  10. 如权利要求1至9中任一项权利要求所述的栅极驱动模组，其中，所述时钟信号线包括第一时钟信号线和第二时钟信号线；
    所述第一移位寄存器子电路包括的奇数级第一移位寄存器单元与所述第一时钟信号输入端连接，所述第一移位寄存器子电路包括的偶数级第一移位寄存器单元与所述第二时钟信号输入端连接；并且
    所述第一移位寄存器子电路包括的第一移位寄存器单元的级数为偶数，所述第二移位寄存器子电路包括的奇数级第二移位寄存器单元与所述第一时钟信号输入端连接，所述第二移位寄存器子电路包括的偶数级第二移位寄存器单元与所述第二时钟信号输入端连接。
  11. 如权利要求1至9中任一项权利要求所述的栅极驱动模组，其中，所述时钟信号线包括第一时钟信号线和第二时钟信号线；
    所述第一移位寄存器子电路包括的奇数级第一移位寄存器单元与所述第一时钟信号输入端连接，所述第一移位寄存器子电路包括的偶数级第一移位寄存器单元与所述第二时钟信号输入端连接；并且
    所述第一移位寄存器子电路包括的第一移位寄存器单元的级数为奇数，所述第二移位寄存器子电路包括的奇数级第二移位寄存器单元与所述第二时钟信号输入端连接，所述第二移位寄存器子电路包括的偶数级第二移位寄存器单元与所述第一时钟信号输入端连接。
  12. 一种栅极驱动控制方法，所述栅极驱动控制方法应用于如权利要求1至11中任一项权利要求所述的栅极驱动模组，所述栅极驱动控制方法包括：
    当显示面板处于非平面状态时，并当第二移位寄存器单元进行栅极驱动扫描时，控制电路控制向时钟信号线提供第一电压信号，以使得所述第二移位寄存器单元控制栅线发出使得所述栅线对应的晶体管关闭(OFF)的信号。
  13. 如权利要求12所述的栅极驱动控制方法，其中，第一移位寄存器单元还与所述时钟信号线连接；所述栅极驱动控制方法还包括：
    当所述显示面板处于非平面状态时，并当所述第一移位寄存器单元进行栅极驱动扫描时，所述控制电路控制向所述时钟信号线提供时钟信号，以使得所述第一移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号。
  14. 如权利要求12或13所述的栅极驱动控制方法，其中，所述栅极驱动控制方法还包括：
    当所述显示面板处于平面状态时，所述控制电路控制向所述时钟信号线提供时钟信号，以使得当所述第一移位寄存器单元进行栅极驱动扫描时，该第一移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号，并使得当所述第二移位寄存器单元进行栅极驱动扫描时，该第二移位寄存器单元控制栅线发出使得所述栅线对应的晶体管打开(ON)的信号。
  15. 如权利要求12至14中任一项所述的栅极驱动控制方法，其中，所述栅极驱动模组还包括检测电路；所述栅极驱动控制方法还包括：
    所述检测电路检测所述显示面板处于非平面状态或平面状态，生成相应的状态指示信号，并将该状态指示信号传送至所述控制电路。
  16. 如权利要求12至15中任一项所述的栅极驱动控制方法，其中，所述栅极驱动控制方法还包括：
    在设置于非平面时刻之前，并与所述非平面时刻紧邻的一黑画面显示时间段内，所述控制电路控制向与设于所述第二子显示区域中的亚像素连接的数据线提供预定数据电压，以使得该亚像素显示黑画面；并且
    所述非平面时刻为所述控制电路开始控制向所述时钟信号线提供第一电压信号的时刻。
  17. 一种显示装置，包括如权利要求1至11中任一项权利要求所述的栅极驱动模组。
  18. 如权利要求17所述的显示装置，其中，所述显示装置还包括驱动集成电路和多条栅线，所述多条栅线沿第一方向延伸；折叠轴沿所述第一方向延伸；所述栅极驱动模组包括的控制电路设置于所述驱动集成电路中。
  19. 如权利要求18所述的显示装置，其中，所述栅极驱动模组包括的栅极驱动电路设置于所述多条栅线延伸方向所指向的显示面板的周边区域内。
  20. 如权利要求19所述的显示装置，其中，所述多条栅线纵向设置，所述栅极驱动模组包括的栅极驱动电路设置于显示面板的上侧边或所述显示面板的下侧边，其中所述纵向与所述第一方向实质上一致。
  21. 如权利要求19所述的显示装置，其中，所述多条栅线纵向设置，所述栅极驱动模组包括两个栅极驱动电路；所述两个栅极驱动电路当中的第一栅极驱动电路设置于显示面板的上侧边，该栅极驱动电路包括的移位寄存器单元与对应的栅线的上端连接；所述两个栅极驱动电路当中的第二栅极驱动电路设置于所述显示面板的下侧边，该栅极驱动电路包括的移位寄存器单元与对应的栅线的下端连接，其中所述纵向与所述第一方向实质上一致。
  22. 如权利要求21所述的显示装置，其中，所述第一栅极驱动电路和所述第二栅极驱动电路都是设置于阵列基板上的栅极驱动电路(GOA)。
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109859694B (zh) * 2019-03-19 2021-04-20 京东方科技集团股份有限公司 显示面板及其驱动控制方法、驱动控制电路、显示装置
CN111210754B (zh) * 2020-02-19 2022-08-19 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路
CN111292664B (zh) * 2020-02-20 2022-08-09 合肥京东方卓印科技有限公司 栅极驱动电路、显示面板及其显示方法
CN111402806B (zh) * 2020-04-26 2021-08-27 京东方科技集团股份有限公司 一种驱动电路及其驱动方法、显示面板
CN113823207A (zh) 2020-06-18 2021-12-21 华为技术有限公司 驱动控制方法及相关设备
US11244646B1 (en) * 2020-09-16 2022-02-08 Himax Technologies Limited Display device and display control method
CN113380311B (zh) * 2021-06-30 2024-02-09 上海中航光电子有限公司 一种显示面板及显示装置
CN114783360B (zh) * 2022-04-20 2024-09-03 京东方科技集团股份有限公司 栅极驱动控制方法及其系统、显示驱动系统、显示装置
CN117116163A (zh) * 2023-01-31 2023-11-24 荣耀终端有限公司 一种折叠屏的显示方法及电子设备
CN116597759B (zh) * 2023-05-06 2026-03-27 合肥维信诺科技有限公司 显示驱动电路及其控制方法、显示面板
CN118471086B (zh) * 2023-12-13 2025-02-28 荣耀终端股份有限公司 柔性显示面板及其显示方法、电子设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101025906A (zh) * 2006-02-20 2007-08-29 三星电子株式会社 显示装置及其驱动方法
CN104537970A (zh) * 2014-11-27 2015-04-22 上海天马微电子有限公司 栅极驱动单元、栅极驱动电路及驱动方法、显示装置
CN104658466A (zh) * 2015-01-27 2015-05-27 京东方科技集团股份有限公司 一种goa电路及其驱动方法、显示面板及显示装置
CN104851369A (zh) * 2015-06-12 2015-08-19 京东方科技集团股份有限公司 一种柔性显示面板及其驱动方法、显示装置
CN106328081A (zh) * 2016-10-09 2017-01-11 武汉华星光电技术有限公司 柔性显示器及其驱动方法
US20170033126A1 (en) * 2009-07-07 2017-02-02 Semiconductor Energy Laboratory Co., Ltd. Display device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4885865B2 (ja) * 2005-09-21 2012-02-29 パナソニック株式会社 画像投射装置
CN101377595B (zh) * 2007-08-31 2010-06-09 北京京东方光电科技有限公司 液晶显示器栅极驱动装置
KR101509116B1 (ko) 2007-11-13 2015-04-06 삼성디스플레이 주식회사 표시 장치와 그 구동 장치 및 구동 방법
KR102432511B1 (ko) * 2013-08-02 2022-08-12 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치
KR102174323B1 (ko) 2014-05-27 2020-11-05 삼성디스플레이 주식회사 게이트 구동 회로 및 이를 포함하는 표시 장치
US10482822B2 (en) * 2016-09-09 2019-11-19 Apple Inc. Displays with multiple scanning modes
TWI619103B (zh) * 2016-09-23 2018-03-21 友達光電股份有限公司 可撓式顯示器
KR102603440B1 (ko) * 2016-10-10 2023-11-20 삼성디스플레이 주식회사 폴더블 표시 장치
CN106504714B (zh) * 2016-12-12 2019-05-03 武汉华星光电技术有限公司 一种显示装置及其分屏显示方法
CN107610636B (zh) * 2017-10-30 2021-02-02 武汉天马微电子有限公司 一种显示面板及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101025906A (zh) * 2006-02-20 2007-08-29 三星电子株式会社 显示装置及其驱动方法
US20170033126A1 (en) * 2009-07-07 2017-02-02 Semiconductor Energy Laboratory Co., Ltd. Display device
CN104537970A (zh) * 2014-11-27 2015-04-22 上海天马微电子有限公司 栅极驱动单元、栅极驱动电路及驱动方法、显示装置
CN104658466A (zh) * 2015-01-27 2015-05-27 京东方科技集团股份有限公司 一种goa电路及其驱动方法、显示面板及显示装置
CN104851369A (zh) * 2015-06-12 2015-08-19 京东方科技集团股份有限公司 一种柔性显示面板及其驱动方法、显示装置
CN106328081A (zh) * 2016-10-09 2017-01-11 武汉华星光电技术有限公司 柔性显示器及其驱动方法

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