WO2020001200A1 - 移位寄存器及驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器及驱动方法、栅极驱动电路和显示装置 Download PDF

Info

Publication number
WO2020001200A1
WO2020001200A1 PCT/CN2019/087835 CN2019087835W WO2020001200A1 WO 2020001200 A1 WO2020001200 A1 WO 2020001200A1 CN 2019087835 W CN2019087835 W CN 2019087835W WO 2020001200 A1 WO2020001200 A1 WO 2020001200A1
Authority
WO
WIPO (PCT)
Prior art keywords
terminal
transistor
signal
electrically connected
clock signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/087835
Other languages
English (en)
French (fr)
Inventor
郑灿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to JP2019564138A priority Critical patent/JP7267935B2/ja
Priority to US16/613,125 priority patent/US11581051B2/en
Priority to KR1020197035458A priority patent/KR102275425B1/ko
Priority to EP19824634.0A priority patent/EP3816984B1/en
Publication of WO2020001200A1 publication Critical patent/WO2020001200A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/007—Use of pixel shift techniques, e.g. by mechanical shift of the physical pixels or by optical shift of the perceived pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation

Definitions

  • Embodiments of the present disclosure relate to a shift register and a driving method, a gate driving circuit, and a display device.
  • the Gate-Driven Array (GOA) technology integrates the gate-drive circuit directly on the array substrate of the display device through a photolithography process.
  • the GOA circuit usually includes multiple cascaded shift registers.
  • the shift registers each correspond to a gate line corresponding to a row of pixels (for example, each shift register provides a scan driving signal to a gate line connected to a row of pixels) to realize scan driving of a display panel.
  • GOA technology can save the space of the bonding area and fan-out area of the gate integrated circuit (IC), so as to achieve a narrow bezel of the display panel, and at the same time can reduce product costs and improve product Yield.
  • At least one embodiment of the present disclosure provides a shift register including an input circuit, a control circuit, an intermediate circuit, and an output circuit.
  • the input circuits are electrically connected to an input voltage terminal and a first clock signal terminal, respectively, and are configured to The input voltage provided by the input voltage terminal is input to the intermediate circuit under the control of the first clock signal provided by the first clock signal terminal; the intermediate circuit is respectively connected with the intermediate output terminal, the first power source terminal, The second power supply terminal, the first clock signal terminal, and the second clock signal terminal are electrically connected, and are configured to, under the control of the input voltage and the control circuit, output a first voltage output from the second clock signal terminal.
  • Two clock signals or a first power signal output from the first power terminal is written into the intermediate output terminal as an intermediate output signal; the output circuit is respectively connected to the first power terminal, the second power terminal, and the first
  • the three power terminals, the third clock signal terminal, the intermediate output terminal, and the output terminal are electrically connected, and are configured to output an output signal at the output terminal that is opposite to the intermediate output signal.
  • the output circuit includes a first output sub-circuit, a second output sub-circuit, and a first storage circuit, and the first output sub-circuit is respectively connected to the first output sub-circuit.
  • the power supply terminal, the intermediate output terminal, the output terminal and the first node are electrically connected, and are configured to write the first power supply signal into the output node under the control of the intermediate output signal.
  • the second output sub-circuit is electrically connected to the second power supply terminal, the third power supply terminal, the third clock signal terminal, the first node, and the output terminal, and is configured To write the second power signal provided by the second power terminal to the output terminal under the control of the third clock signal output from the third clock signal terminal in the input phase, the buffer phase and the stabilization phase;
  • the first storage circuit is electrically connected to the first node and the output terminal, respectively.
  • the first output sub-circuit includes a first transistor and a second transistor, and a first pole of the first transistor is electrically connected to the first power terminal, The second pole of the first transistor is electrically connected to the first node, the gate of the first transistor is electrically connected to the intermediate output terminal, and the first pole of the second transistor is connected to the first power source.
  • Terminals are electrically connected, a second pole of the second transistor is electrically connected to the output terminal, a gate of the second transistor is electrically connected to the intermediate output terminal, and the second output sub-circuit includes a third transistor and A fourth transistor, a first pole of the third transistor is electrically connected to the first node, a second pole of the third transistor is electrically connected to the third power terminal, and a gate of the third transistor is connected to The third clock signal terminal is electrically connected, a first pole of the fourth transistor is electrically connected to the output terminal, a second pole of the fourth transistor is electrically connected to the second power source terminal, and the fourth The gate of the transistor is electrically connected to the first node
  • Said first memory circuit includes a first capacitor, the first terminal of the first capacitor is electrically connected to the first node, a second terminal of the first capacitor is connected to said output terminal.
  • the third power terminal is configured to provide a third power signal, and the second power signal is greater than the third power signal.
  • a relationship between the second power signal and the third power signal is expressed as:
  • VL indicates the second power signal
  • VL1 indicates the third power signal
  • Vth10 indicates a threshold voltage of the third transistor
  • Vth12 indicates a threshold voltage of the fourth transistor.
  • the intermediate circuit is configured to write the second clock signal to the intermediate output under the input voltage control in the input stage. Terminal as the intermediate output signal; in the output phase and the buffer phase, writing the second clock signal to the intermediate output terminal as the intermediate output signal; and in the stabilization phase, in the stabilization phase, Under the control of the control circuit, the first power signal is written into the intermediate output terminal as the intermediate output signal.
  • the intermediate circuit includes: a first control sub-circuit, which is respectively connected to a second node, a third node, a fourth node, the first power terminal, and the The second power supply terminal is electrically connected to the second clock signal terminal, and is configured to: write the input voltage to the second node in the input phase; and write the first voltage to the first node in the stabilization phase.
  • a power signal is written into the second node;
  • a second control sub-circuit is electrically connected to the third node, the fourth node, and the first clock signal terminal, respectively, and is configured to connect the first clock signal Write to the third node;
  • the intermediate output sub-circuit is electrically connected to the second node, the intermediate output terminal, and the second clock signal terminal, respectively, and is configured to: in the input stage, the output Phase and the buffering phase, writing the second clock signal into the intermediate output terminal as the intermediate output signal.
  • the first control sub-circuit includes a fifth transistor, a sixth transistor, and a seventh transistor, and a first pole of the fifth transistor and the first power source Terminals are electrically connected, the second pole of the fifth transistor is electrically connected to the first pole of the sixth transistor, and the gate of the fifth transistor is electrically connected to the third node; A second pole is electrically connected to the fourth node, a gate of the sixth transistor is electrically connected to the second clock signal terminal, and a first pole of the seventh transistor is electrically connected to the fourth node. A second pole of a seventh transistor is electrically connected to the second node, and a gate of the seventh transistor is electrically connected to the second power terminal.
  • the second control sub-circuit includes an eighth transistor, a first pole of the eighth transistor is electrically connected to the third node, and the eighth transistor The second electrode of is electrically connected to the first clock signal terminal, and the gate of the eighth transistor is electrically connected to the fourth node.
  • the intermediate output sub-circuit includes a ninth transistor, a first pole of the ninth transistor is electrically connected to the second clock signal terminal, and the ninth A second electrode of the transistor is electrically connected to the intermediate output terminal, and a gate of the ninth transistor is electrically connected to the second node.
  • the intermediate circuit further includes: a second storage sub-circuit, the second storage sub-circuit includes a second capacitor, and a first end of the second capacitor and The second node is electrically connected, and the second terminal of the second capacitor is electrically connected to the intermediate output terminal.
  • the intermediate circuit further includes: an intermediate output control sub-circuit, which is electrically connected to the third node, the intermediate output terminal, and the first power source terminal, respectively. Is configured to: in the stabilization phase, under the control of the control circuit, write the first power supply signal to the intermediate output terminal; and a third storage sub-circuit, which is respectively connected to the third node and The first power terminal is electrically connected.
  • the intermediate output control sub-circuit includes a tenth transistor
  • the third storage sub-circuit includes a third capacitor
  • the first pole of the tenth transistor and the The first power terminal is electrically connected
  • the second pole of the tenth transistor is electrically connected to the intermediate output terminal
  • the gate of the tenth transistor is electrically connected to the third node
  • the third capacitor of the third capacitor is electrically connected.
  • One end is electrically connected to the third node
  • the second end of the third capacitor is electrically connected to the first power supply terminal.
  • the high level of the second clock signal is the same as the level of the first power signal, and the low level of the second clock signal is the same as the The level of the second power signal is the same.
  • the control circuit includes an eleventh transistor, a first pole of the eleventh transistor is electrically connected to the second power source terminal, and the eleventh A second pole of the transistor is electrically connected to the third node, and a gate of the eleventh transistor is electrically connected to the first clock signal terminal.
  • the high level of the clock signal output from the third clock signal terminal is the same as the level of the first power signal
  • the third clock signal terminal outputs The low level of the clock signal is the same as the level of the third power signal.
  • the input circuit includes a twelfth transistor, a first pole of the twelfth transistor is electrically connected to the input voltage terminal, and the twelfth transistor The second electrode of is electrically connected to the fourth node, and the gate of the twelfth transistor is electrically connected to the first clock signal terminal.
  • At least one embodiment of the present disclosure further provides a gate driving circuit including the shift register according to any one of the above.
  • the gate driving circuit provided by an embodiment of the present disclosure includes a plurality of cascaded shift registers according to any one of the above.
  • the input of the current stage shift register The voltage terminal is electrically connected to the intermediate output terminal of the upper-stage shift register.
  • a gate driving circuit provided by an embodiment of the present disclosure further includes a signal generating circuit configured to generate a first control signal, a second control signal, a third control signal, and a fourth control signal.
  • a first control signal is applied to the first clock signal terminal of the 2N-1 stage shift register and the second clock signal terminal of the 2N stage shift register;
  • the second control signal is applied to the The second clock signal terminal of the 2N-1 stage shift register and the first clock signal terminal of the 2N stage shift register;
  • the third control signal is applied to the 2N-1 stage The third clock signal terminal of the shift register;
  • the fourth control signal is applied to the third clock signal terminal of the 2N-stage shift register; wherein N is a positive integer and N is greater than or equal to 1 .
  • At least one embodiment of the present disclosure also provides a display device including a gate driving circuit provided by any one of the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure also provides a method for driving a shift register, including: under the control of the input voltage and the control circuit, outputting the second clock signal or The first power signal output from the first power terminal is written into the intermediate output terminal as the intermediate output signal; the third clock signal output at the intermediate output signal and the third clock signal terminal Under the control of, the output terminal outputs an output signal that is inverse to the intermediate output signal.
  • FIG. 1 is a schematic block diagram of a shift register according to some embodiments of the present disclosure
  • FIG. 2 is a schematic circuit structure diagram of a specific implementation example of a shift register provided by some embodiments of the present disclosure
  • FIG. 3 is a driving timing diagram of a shift register provided by some embodiments of the present disclosure.
  • FIG. 4 is a schematic block diagram of a gate driving circuit provided by some embodiments of the present disclosure.
  • FIG. 5 is a schematic structural diagram of a gate driving circuit provided by some embodiments of the present disclosure.
  • FIG. 6 is a driving timing diagram of a gate driving circuit provided by some embodiments of the present disclosure.
  • FIG. 7 is a schematic diagram of a display panel provided by some embodiments of the present disclosure.
  • FIG. 8 is a flowchart of a driving method provided by some embodiments of the present disclosure.
  • a transistor in a shift register of a gate driving circuit is a P-type thin film transistor, and a gate driving circuit (for example, a GOA circuit) requires When a high-pulse signal is output, the low-level signal output by the P-type thin-film transistor has a threshold loss, which makes the high-pulse signal output by the GOA circuit inaccurate, which affects the display effect and reduces the display quality. Therefore, how to design a GOA circuit with a simple structure and a P-type thin film transistor outputting a low-level signal without threshold loss has become an urgent problem.
  • At least one embodiment of the present disclosure provides a shift register and a gate driving circuit.
  • the shift register can increase the DC power signal output from the third power terminal, so that the P-type thin film transistor can output a low-level signal without a threshold loss.
  • the structure of the shift register is simple and the production cost is low.
  • FIG. 1 is a schematic block diagram of a shift register provided by some embodiments of the present disclosure
  • FIG. 2 is a schematic circuit structure diagram of a specific implementation example of a shift register provided by some embodiments of the present disclosure.
  • Embodiments of the present disclosure provide a shift register.
  • the shift register includes an input circuit 100, an intermediate circuit 200, a control circuit 300, and an output circuit 400.
  • the input circuit 100 is electrically connected to the input voltage terminal STV and the first clock signal terminal CK, respectively, and the input circuit 100 is also electrically connected to the intermediate circuit 200.
  • the input voltage terminal STV is configured to provide an input voltage V in
  • the first clock signal terminal CK is configured to provide a first clock signal V c1 .
  • Input circuit 100 is configured under control of a first clock signal V C1 of the first clock signal terminal CK supplied, the input voltage V in supplied voltage terminal STV is input to the intermediate circuit 200. That is, when the input circuit 100 is turned on under the control of the first clock signal V c1 , the input voltage terminal STV is connected to the intermediate circuit 200, and the input voltage V in can be transmitted to the intermediate circuit 200.
  • the intermediate circuit 200 is electrically connected to the intermediate output terminal GOUT, the first power terminal VGH, the second power terminal VGL, the first clock signal terminal CK, and the second clock signal terminal CB, respectively.
  • the first power terminal VGH is configured to provide a first power signal VH
  • the second power terminal VGL is configured to provide a second power signal VL
  • the second clock signal terminal CB is configured to output a second clock signal V c2 .
  • Intermediate circuit 200 is configured under control of the input voltage V in and the control circuit 300, a second clock signal of the first power supply terminal of the second clock signal CB outputted from V c2 VGH or the first power supply terminal VH written to the intermediate output signal
  • the output terminal GOUT is used as an intermediate output signal V GOUT .
  • a second clock signal V c2 may be written to the intermediate output terminal GOUT is used as the intermediate output signal V GOUT ; or when the intermediate circuit 200 turns on the first power terminal VGH and the intermediate output terminal GOUT, the first power signal VH can be written into the intermediate output terminal GOUT as the intermediate output signal V GOUT .
  • the control circuit 300 is electrically connected to the second power supply terminal VGL, the first clock signal terminal CK, and the intermediate circuit 200, respectively.
  • the control circuit 300 is configured to output the second power signal VL output from the second power terminal VGL to the intermediate circuit 200 under the control of the first clock signal V c1 provided by the first clock signal terminal CK. That is, when the control circuit 300 is turned on under the control of the first clock signal V c1 , the second power terminal VGL is connected to the intermediate circuit 200, so that the second power signal VL can be transmitted to the intermediate circuit 200.
  • the output circuit 400 is electrically connected to the first power terminal VGH, the second power terminal VGL, the third power terminal VGL1, the third clock signal terminal CK1, the intermediate output terminal GOUT, and the output terminal EOUT, respectively.
  • the third power terminal VGL1 is configured to provide a third power signal VL1
  • the third clock signal terminal CK1 is configured to provide a third clock signal Vc3 .
  • the output circuit 400 is configured to output an output signal V EOUT that is inverted from the intermediate output signal V GOUT .
  • the output circuit 400 turns the first The power signal VH is transmitted to the output terminal EOUT as a high-level signal of the output signal V EOUT .
  • the output circuit 400 will The second power signal VL is transmitted to the output terminal EOUT as a low-level signal of the output signal V EOUT .
  • the second power supply signal VL is larger than the third power supply signal VL1, so that the threshold loss of the second power supply signal VL output to the output terminal EOUT via the output transistor (for example, the fourth transistor T4 shown in FIG. 2) can be reduced.
  • the first power signal VH, the second power signal VL, and the third power signal VL1 are all DC signals.
  • the first power signal VH is a high-level signal (such as 5V, 10V, or other voltages);
  • the second power signal VL is a low-level signal (such as 0V, -1V, or other voltages); Flat signal (eg -2V, -1V or other voltage). It should be noted that the low-level signal and the high-level signal are relative, and the low-level signal is smaller than the high-level signal.
  • the value of the high-level signal may be different, and the value of the low-level signal may also be different, as long as the second power signal VL is greater than the third power signal VL1, which is not limited in the embodiments of the present disclosure. .
  • all the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the source and drain of the transistor used here can be symmetrical in structure, so there can be no difference in structure of the source and drain of the transistor.
  • one pole is directly described as the first pole and the other pole is the second pole. Therefore, all or part of the first poles of the transistors in the embodiments of the present disclosure are described. It is interchangeable with the second pole as required.
  • the first electrode of the transistor according to the embodiment of the present disclosure may be a source and the second electrode may be a drain; or, the first electrode of the transistor is a drain and the second electrode is a source.
  • the transistors can be divided into N-type and P-type transistors according to the characteristics of the transistors.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, or other values), and the turn-off voltage is a high-level voltage (for example, 5V, 10V, or other values); when the transistor is N-type
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V, or other values)
  • the turn-off voltage is a low-level voltage (for example, 0V, -5V, or other values).
  • all transistors are P-type transistors.
  • the output circuit 400 may include a first output sub-circuit 401, a second output sub-circuit 402, and a first storage circuit 403.
  • the first output sub-circuit 401 is electrically connected to the first power supply terminal VGH, the intermediate output terminal GOUT, the output terminal EOUT, and the first node N1, respectively, and the first output sub-circuit 401 is configured to output a signal in the middle during the output stage. Under the control of V GOUT , the first power signal VH is written into the output terminal EOUT as a high-level signal of the output signal V EOUT .
  • the second output sub-circuit 402 is electrically connected to the second power supply terminal VGL, the third power supply terminal VGL1, the third clock signal terminal CK1, the first node N1, and the output terminal EOUT, respectively, and the second output sub-circuit 402 is configured to In the input phase, the buffer phase, and the stabilization phase, the second power supply signal VL provided by the second power supply terminal VGL is written into the output terminal EOUT as an output signal under the control of the third clock signal V c3 output from the third clock signal terminal CK1. V EOUT low signal.
  • the first storage circuit 403 is electrically connected to the first node N1 and the output terminal EOUT, respectively.
  • the first output sub-circuit 401 includes a first transistor T1 and a second transistor T2.
  • the first pole of the first transistor T1 is electrically connected to the first power terminal VGH to receive the first power signal VH
  • the second pole of the first transistor T1 is electrically connected to the first node N1, and the gate of the first transistor T1 and the intermediate output
  • the terminal GOUT is electrically connected
  • the first pole of the second transistor T2 is electrically connected to the first power terminal VGH to receive the first power signal VH
  • the second pole of the second transistor T2 is electrically connected to the output terminal EOUT
  • the second transistor T2 The gate is electrically connected to the intermediate output terminal GOUT.
  • the second output sub-circuit 402 includes a third transistor T3 and a fourth transistor T4.
  • the first pole of the third transistor T3 is electrically connected to the first node N1, and the second pole of the third transistor T3 is electrically connected to the third power terminal VGL1.
  • the gate of the third transistor T3 is electrically connected to the third clock signal terminal CK1 to receive the third clock signal Vc3 ;
  • the first electrode of the fourth transistor T4 is electrically connected to the output terminal EOUT,
  • the second pole of the four transistor T4 is electrically connected to the second power terminal VGL to receive the second power signal VL, and the gate of the fourth transistor T4 is electrically connected to the first node N1.
  • the third power supply voltage VL1 can control the conduction degree of the fourth transistor T4 (for example, the When the fourth transistor T4 outputs the second low-level power supply signal VL to the output terminal EOUT, the second power supply signal VL has no threshold loss, that is, the output signal V EOUT has no threshold loss.
  • the threshold loss outputs a low-level signal to improve the display quality of the display panel.
  • output circuit 400 shown in FIG. 2 is only an exemplary implementation, and the output circuit 400 provided by the embodiment of the present disclosure includes but is not limited to the output circuit 400 shown in FIG. 2.
  • the relationship between the second power signal VL and the third power signal VL1 can be expressed as:
  • Vth10 represents the threshold voltage of the third transistor T3
  • Vth12 represents the threshold voltage of the fourth transistor T4.
  • the low level of the third clock signal V c3 is , for example, equal to the level of the third power supply signal VL1, that is, the voltage of the gate of the third transistor T3 is the third power supply signal.
  • VL1 when the voltage of the source of the third transistor T3 is lower than VL1-Vth10, the third transistor T3 is turned off, that is, the voltage of the source of the third transistor T3 can reach at least VL1-Vth10.
  • the third power source signal VL1 is transmitted to the first node N1 (that is, the gate of the fourth transistor T4), due to the transmission threshold loss of the third transistor T3, and the third power source is lost.
  • the signal VL1 is a low-level signal.
  • the third transistor T3 is turned off and cannot continue to transmit a low-level signal. Therefore, the voltage transmitted from the third transistor T3 to the gate of the fourth transistor T4 is VL1-Vth10.
  • the gate-source voltage Vgs12 of the fourth transistor T4 is VL1-Vth10-VL, because VL-VL1>
  • the threshold voltage Vth10 of the third transistor T3 is -0.5V
  • the threshold voltage Vth12 of the fourth transistor T4 is -0.5V
  • the second power signal VL is -4V
  • the third power signal VL1 is -6V.
  • the fourth transistor T4 is turned on, and the second power signal VL is transmitted to the output terminal EOUT through the fourth transistor T4. Because the source voltage of the fourth transistor T4 can be at least -5V, that is, when the output signal V EOUT is- At 4V (that is, the second power signal VL), the fourth transistor T4 is still on, that is, the second power signal VL can be transmitted to the output terminal EOUT without loss.
  • the shift register provided in the present disclosure can output the second low-level power supply signal VL to the output terminal EOUT without threshold loss.
  • the first storage circuit 403 includes a first capacitor C1, a first terminal of the first capacitor C1 is electrically connected to the first node N1, and a second terminal of the first capacitor C1 is electrically connected to the output terminal EOUT.
  • the intermediate circuit 200 is configured to: in the input phase, under the control of the input voltage Vin, write the second clock signal V c2 into the intermediate output terminal GOUT as the intermediate output signal V GOUT ; in the output phase and the buffer phase, write the second clock signal V GOUT ;
  • the clock signal V c2 is written into the intermediate output terminal GOUT as the intermediate output signal V GOUT ; and in the stable phase, under the control of the control circuit 300, the first power signal VH is written into the intermediate output terminal GOUT as the intermediate output signal V GOUT .
  • the intermediate output signal V GOUT may be used to control, for example, the first output sub-circuit 401 in the output circuit 400 to be turned on or off.
  • the intermediate circuit 200 may include a first control sub-circuit 201, a second control sub-circuit 202, an intermediate output sub-circuit 203, a second storage sub-circuit 204, an intermediate output control sub-circuit 205, and a third storage Sub-circuit 206.
  • the pull-down control sub-circuit is an example of the first control sub-circuit 201
  • the pull-up control sub-circuit is an example of the second control sub-circuit 202
  • the intermediate output pull-up sub-circuit is intermediate output control
  • An example of the sub-circuit 205 is described below by taking the first control sub-circuit 201 as a pull-down control sub-circuit, the second control sub-circuit 202 as a pull-up control sub-circuit, and the intermediate output control sub-circuit as an intermediate output pull-up sub-circuit.
  • the embodiments of the present disclosure are not limited thereto, and the following embodiments are the same, and will not be described again.
  • the pull-down control sub-circuit 201 is electrically connected to the second node N2, the third node N3, the fourth node N4, the first power terminal VGH, the second power terminal VGL, and the second clock signal terminal CB, respectively. .
  • the pull-down control sub-circuit 201 is used to control the voltage of the second node N2.
  • the intermediate output sub-circuit 203 can write the second clock signal V c2 to the intermediate output
  • the terminal GOUT serves as the intermediate output signal V GOUT .
  • the pull-down control sub-circuit 201 is configured to write the input voltage Vin to the second node N2 during the input phase; and write the first power supply signal VH to the second node N2 during the stabilization phase.
  • the pull-up control sub-circuit 202 is electrically connected to the third node N3, the fourth node N4, and the first clock signal terminal CK, respectively.
  • the pull-up control sub-circuit 202 is used to control the voltage of the third node N3.
  • the intermediate output pull-up sub-circuit 205 can switch the first power supply signal VH
  • the intermediate output terminal GOUT is written so as to control (eg, pull up) the potential of the intermediate output terminal GOUT.
  • the pull-up control sub-circuit 202 is configured to write the first clock signal V c1 to the third node N3.
  • the intermediate output sub-circuit 203 is electrically connected to the second node N2, the intermediate output terminal GOUT, and the second clock signal terminal CB, respectively.
  • the intermediate output sub-circuit 203 is configured to write the second clock signal V c2 into the intermediate output terminal GOUT as the intermediate output signal V GOUT in the input phase, the output phase, and the buffer phase.
  • the second storage sub-circuit 204 is electrically connected to the second node N2 and the intermediate output terminal GOUT, respectively.
  • the second storage sub-circuit 204 is used to maintain the voltage at the second node N2.
  • the intermediate output pull-up sub-circuit 205 is electrically connected to the third node N3, the intermediate output terminal GOUT, and the first power supply terminal VGH, respectively.
  • the intermediate output pull-up sub-circuit 205 is configured to write the first power supply signal VH to the intermediate output terminal GOUT under the control of the control circuit 300 in a stable phase.
  • the third storage sub-circuit 206 is electrically connected to the third node N3 and the first power supply terminal VGH, respectively.
  • the intermediate output pull-up sub-circuit 205 is used to control the potential of the intermediate output terminal GOUT, for example, to pull up the potential of the intermediate output terminal GOUT; the third storage sub-circuit 206 is used to maintain the voltage at the third node N3.
  • the pull-down control sub-circuit 201 includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.
  • the first pole of the fifth transistor T5 is electrically connected to the first power terminal VGH to receive the first power signal VH
  • the second pole of the fifth transistor T5 is electrically connected to the first pole of the sixth transistor T6, and the gate of the fifth transistor T5
  • the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4, and the gate of the sixth transistor T6 is electrically connected to the second clock signal terminal CB to receive the second clock signal V c2 ;
  • the first pole of the seventh transistor T7 is electrically connected to the fourth node N4, the second pole of the seventh transistor T7 is electrically connected to the second node N2, and the gate of the seventh transistor T7 is electrically connected to the second power terminal VGL to receive the first Two power supply signals VL.
  • the pull-up control sub-circuit 202 includes an eighth transistor T8.
  • the first pole of the eighth transistor T8 is electrically connected to the third node N3, the second pole of the eighth transistor T8 is electrically connected to the first clock signal terminal CK to receive the first clock signal V c1 , and the gate of the eighth transistor T8 is connected to The fourth node N4 is electrically connected.
  • the intermediate output sub-circuit 203 includes a ninth transistor T9
  • the second storage sub-circuit 204 includes a second capacitor C2.
  • the first pole of the ninth transistor T9 is electrically connected to the second clock signal terminal CB to receive the second clock signal V c2
  • the second pole of the ninth transistor T9 is electrically connected to the intermediate output terminal GOUT
  • the gate of the ninth transistor T9 is connected to
  • the second node N2 is electrically connected.
  • a first terminal of the second capacitor C2 is electrically connected to the second node N2, and a second terminal of the second capacitor C2 is electrically connected to the intermediate output terminal GOUT.
  • the intermediate output pull-up sub-circuit 205 includes a tenth transistor T10
  • the third storage sub-circuit 206 includes a third capacitor C3.
  • the first pole of the tenth transistor T10 is electrically connected to the first power supply terminal VGH
  • the second pole of the tenth transistor T10 is electrically connected to the intermediate output terminal GOUT
  • the gate of the tenth transistor T10 is electrically connected to the third node N3
  • the first terminal of the capacitor C3 is electrically connected to the third node N3, and the second terminal of the third capacitor C3 is electrically connected to the first power terminal VGH to receive the first power signal VH.
  • the control circuit 300 is used to control the intermediate output pull-up sub-circuit 205 to stabilize the voltage of the intermediate output terminal GOUT to the first power supply voltage VH in the stabilization stage.
  • the control circuit 300 includes an eleventh transistor T11.
  • the first pole of the eleventh transistor T11 is electrically connected to the second power terminal VGL to receive the second power signal VL
  • the second pole of the eleventh transistor T11 is electrically connected to the third node N3, and the gate of the eleventh transistor T11
  • the first clock signal terminal CK is electrically connected to receive the first clock signal V c1 .
  • the input circuit 100 is used to transmit the input voltage Vin to the intermediate circuit 200 to trigger the shift register to work.
  • the input circuit 100 includes a twelfth transistor T12.
  • the first pole of the twelfth transistor T12 is electrically connected to the input voltage terminal STV
  • the second pole of the twelfth transistor T12 is electrically connected to the fourth node N4
  • the gate of the twelfth transistor T12 is electrically connected to the first clock signal terminal CK. Connected to receive the first clock signal V c1 .
  • the input circuit 100, the intermediate circuit 200, and the control circuit 300 shown in FIG. 2 are only examples of the embodiments of the present disclosure, and the embodiments of the present disclosure include but are not limited to the situation shown in FIG. 2.
  • the high level of the first clock signal V c1 is the same as the level of the first power signal VH, and the low level of the first clock signal V c1 is the same as the level of the second power signal VL.
  • the high-level signals of the first power signal VH and the second clock signal V c2 are simultaneously transmitted to the intermediate output terminal GOUT, so that the high level of the second clock signal V c2 and the first power signal VH The same level is used to prevent the voltage signal of the output terminal GOUT from colliding at the same time.
  • the low level of the second clock signal V c2 is the same as the level of the second power signal VL.
  • the high level of the third clock signal V c3 output from the third clock signal terminal CK1 is the same as the level of the first power signal VH.
  • the low level of the third clock signal V c3 output from the third clock signal terminal CK1 is the same as the level of the third power signal VL1 to ensure that the fourth transistor T4 can be fully turned on, thereby outputting the second power signal VL without a threshold loss. .
  • the high level of the first clock signal V c1 and the high level of the third clock signal V c3 may be different from the level of the first power signal VH, and the low level of the first clock signal V c1 may also be different. It may be different from the level of the second power signal VL, and the low level of the third clock signal V c3 may be different from the level of the third power signal VL1 as long as the first clock signal V c1 and the third clock signal V It is sufficient for c3 to be able to perform its own function, which is not limited in this disclosure.
  • the low level of the second clock signal V c2 may be different from the level of the second power signal VL.
  • the high level of the first clock signal V c1 and the high level of the third clock signal V c3 are the same as the level of the first power signal VH, and the low level of the first clock signal V c1 is equal to
  • the level of the second power signal VL is the same
  • the low level of the third clock signal V c3 is the same as the level of the third power signal VL1
  • the low level of the second clock signal V c2 is the same as the level of the second power signal VL
  • the same is used as an example to describe the shift register provided by the present disclosure.
  • FIG. 3 is a driving timing diagram of a shift register provided by some embodiments of the present disclosure.
  • the shift register shown in FIG. 2 and the driving timing shown in FIG. 3 are taken as examples to introduce the working principle of the shift register provided by the embodiment of the present disclosure.
  • the working process of the shift register includes an input phase t1, an output phase t2, a buffer phase t3, and a stabilization phase t4.
  • the first clock signal V c1 output by the first clock signal terminal CK is a low-level signal
  • the second clock signal V c2 output by the second clock signal terminal CB is a high-level signal
  • the third clock signal V c3 output from the third clock signal terminal CK1 is a low-level signal
  • the input voltage Vin output from the input voltage terminal STV is a low-level voltage, such as the input voltage Vin and the second power signal VL is equal.
  • the first clock signal V c1 is a low-level voltage
  • the twelfth transistor T12 is turned on, and the input voltage Vin is transmitted to the fourth node N4 through the twelfth transistor T12.
  • the twelfth transistor T12 transmits a low-level signal with a threshold value Loss, so that the voltage of the fourth node N4 is Vin-Vth1, that is, VL-Vth1, where Vth1 represents the threshold voltage of the twelfth transistor T12. Since the gate of the seventh transistor T7 receives the second power supply voltage VL, the seventh transistor T7 is in an on state. Therefore, the voltage VL-Vth1 is transmitted to the second node N2 via the seventh transistor T7. For example, the voltage of the seventh transistor T7 is The threshold voltage is expressed as Vth8.
  • the voltage of the second node N2 is VL-VthN2, where VthN2 is the smaller of Vth1 and Vth8.
  • the voltage of the second node N2 can control the ninth transistor T9 to be turned on, and the second clock signal V c2 is written into the intermediate output terminal GOUT as the intermediate output signal V GOUT via the ninth transistor T9, that is, in the input stage t1, the intermediate output signal
  • the third clock signal V c3 is a low-level voltage, so that the third transistor T3 is turned on, and the third power supply signal VL1 is transmitted to the first node N1 (that is, the gate of the fourth transistor T4).
  • the low-level signal has a threshold loss.
  • the voltage on the first node N1 is VL1-Vth10.
  • the voltage VL1-Vth10 can control the fourth transistor T4 to be turned on.
  • the second power signal VL is transmitted to the output terminal EOUT through the fourth transistor T4.
  • the fourth transistor T4 When the output signal V EOUT of the output EOUT is VL1 +
  • the eleventh transistor T11 is turned on, and the second power signal VL is transmitted to the third node N3 via the eleventh transistor T11.
  • the voltage of N4 is VL-Vth1
  • the eighth transistor T8 is turned on, and the low-level first clock signal V c1 is transmitted to the third node N3 through the eighth transistor T8.
  • the threshold voltage of the eighth transistor T8 is represented as Vth2
  • the threshold voltage of the eleventh transistor T11 is represented as Vth3.
  • the first clock signal V c1 output by the first clock signal terminal CK and the third clock signal V c3 output by the third clock signal terminal CK1 are both at a high level.
  • the second clock signal V c2 output from the second clock signal terminal CB is a low-level signal
  • the input voltage Vin output from the input voltage terminal STV is a high-level voltage.
  • the ninth transistor T9 is turned on, and the second clock signal V c2 is written into the intermediate output terminal GOUT as the intermediate output signal V EOUT via the ninth transistor T9.
  • the voltage of the end of the second capacitor C2 connected to the intermediate output terminal GOUT is the first power signal VH
  • the voltage of the end of the second capacitor C2 connected to the second node N2 is VL-VthN2
  • the output stage t2 The voltage of the end of the second capacitor C2 connected to the intermediate output terminal GOUT becomes VL, that is, the change is VL-VH. Due to the bootstrapping effect of the second capacitor C2, the end of the second capacitor C2 connected to the second node N2 , The voltage of the second node N2 becomes 2VL-VthN2-VH, that is, the voltage of the second node N2 becomes 2VL-VthN2-VH.
  • the seventh transistor T7 is turned off and the ninth transistor T9 can be better turned on.
  • the output signal V EOUT is the first Two power supply signals VL.
  • the third clock signal V c3 is a high-level signal, so that the third transistor T3 is turned off. Since the second clock signal V c2 is a low-level signal, both the first transistor T1 and the second transistor T2 are turned on.
  • the first power signal VH can be transmitted to the first node N1 through the first transistor T1, so that the fourth transistor T4 is turned off.
  • the first power signal VH can also be transmitted to the output terminal EOUT as the output signal V EOUT through the second transistor T2.
  • the output signal V EOUT is the first power signal VH.
  • the first clock signal V c1 is a high-level signal, so that the twelfth transistor T12 and the eleventh transistor T11 are both turned off.
  • the voltage of the fourth node N4 is still VL-VthN2, the eighth transistor T8 is turned on, and the high-level first clock signal V c1 is transmitted to the third node N3 through the eighth transistor T8, that is, the voltage of the third node N3 is the first
  • the power signal VH is thereby turned off for both the tenth transistor T10 and the fifth transistor T5. Since the second clock signal V c2 is a low-level signal, the sixth transistor T6 is turned on.
  • the first clock signal V c1 output by the first clock signal terminal CK and the second clock signal V c2 output by the second clock signal terminal CB are both at a high level.
  • the third clock signal V c3 output from the third clock signal terminal CK1 is a low-level signal
  • the input voltage Vin output from the input voltage terminal STV is a high-level voltage.
  • the ninth transistor T9 is turned on, and the second clock signal V c2 is written into the intermediate output terminal GOUT as the intermediate output signal V EOUT via the ninth transistor T9.
  • the intermediate output signal V EOUT is a high-level second clock signal V c2 , that is, the first power signal VH, due to the bootstrapping effect of the second capacitor C2, the voltage of the second node N2 becomes VL-VthN2.
  • the intermediate output signal V EOUT is the first power signal VH, and both the first transistor T1 and the second transistor T2 are turned off.
  • the third clock signal V c3 is a low-level voltage, so that the third transistor T3 is turned on, and the third power signal VL1 is transmitted to the first node N1.
  • the voltage on the first node N1 is VL1-Vth10, and the voltage VL1-Vth10
  • the fourth transistor T4 can be controlled to be turned on, the second power signal VL can be transmitted to the output terminal EOUT without loss, and the output signal V EOUT is the second power signal VL.
  • the first clock signal V c1 is a high-level signal, so that the twelfth transistor T12 and the eleventh transistor T11 are both turned off.
  • the voltage of the second node N2 becomes VL-VthN2.
  • the seventh transistor T7 is turned on
  • the voltage of the fourth node N4 is also VL-VthN2
  • the eighth transistor T8 is turned on
  • the high-level first clock signal V c1 is turned on.
  • the voltage transmitted to the third node N3 through the eighth transistor T8 is the first power signal VH, and thus the tenth transistor T10 and the fifth transistor T5 are both turned off. Since the second clock signal V c2 is a high-level signal, the sixth transistor T6 is turned off.
  • the first clock signal V c1 output by the first clock signal terminal CK is a low-level signal
  • the second clock signal terminal CB outputs
  • the second clock signal V c2 is a high-level signal
  • the third clock signal V c3 output from the third clock signal terminal CK1 is a low-level signal
  • the input voltage Vin output from the input voltage terminal STV is a high-level voltage, for example, the input The voltage Vin is equal to the first power signal VH.
  • the twelfth transistor T12 is turned on, and the input voltage Vin is transmitted to the fourth node N4 through the twelfth transistor T12. Since the twelfth transistor T12 transmits a high-level signal, there is no threshold Loss, the voltage of the fourth node N4 is the input voltage Vin (that is, the first power signal VH), and the eighth transistor T8 is turned off. Because the seventh transistor T7 is in an on state, the voltage of the second node N2 is the same as the voltage of the fourth node N4, that is, the voltage of the second node N2 is the first power signal VH, and the ninth transistor T9 is turned off.
  • the eleventh transistor T11 is turned on, the voltage of the third node N3 is VL-Vth3, the tenth transistor T10 and the fifth transistor T5 are both turned on, and the first power signal VH
  • the tenth transistor T10 is transmitted to the intermediate output terminal GOUT, that is, the intermediate output signal V GOUT is the first power signal VH.
  • both the first transistor T1 and the second transistor T2 are turned off.
  • the third transistor T3 is turned on, and the third power supply signal VL1 is transmitted to the first node N1 via the third transistor T3.
  • the voltage of the first node N1 is VL1-Vth10, and the VL1-Vth10
  • the fourth transistor T4 can be controlled to be turned on, and the second power signal VL is transmitted to the output terminal EOUT through the fourth transistor T4, so that the output signal V EOUT remains at the low level of the second power signal VL.
  • the first clock signal V c1 output by the first clock signal terminal CK and the third clock signal output by the third clock signal terminal CK1 V c3 is a high-level signal
  • the second clock signal V c2 output from the second clock signal terminal CB is a low-level signal
  • the input voltage Vin output from the input voltage terminal STV is a high-level voltage.
  • the voltages of the second node N2 and the fourth node N4 are the input voltage Vin (that is, the first power signal VH)
  • the ninth transistor T9 and the eighth transistor T8 are both turned off.
  • the first clock signal V c1 is a high-level signal, so that the twelfth transistor T12 and the eleventh transistor T11 are both turned off. Due to the holding effect of the third capacitor C3, the voltage of the third node N3 is still (VL-Vth3), The tenth transistor T10 and the fifth transistor T5 are both turned on, the first power signal VH is transmitted to the intermediate output terminal GOUT through the tenth transistor T10, and the intermediate output signal V GOUT is the first power signal VH. Under the control of the intermediate output signal V GOUT , both the first transistor T1 and the second transistor T2 are turned off.
  • the third clock signal V c3 is a high-level signal and the third transistor T3 is turned off, the voltage of the first node N1 is still maintained at VL1-Vth10 due to the holding effect of the first capacitor C1, so that the second power supply signal VL can still be
  • the fourth transistor T4 is transmitted to the output terminal EOUT to ensure that the output signal V EOUT remains at the low-level second power signal VL.
  • the sixth transistor T6 is turned on, so that the first power signal VH passes through the fifth transistor T5.
  • the and sixth transistors T6 are transmitted to the fourth node N4 and the second node N2 to keep the voltage of the second node N2 and the voltage of the fourth node N4 at a high level.
  • the first clock signal V c1 output by the first clock signal terminal CK and the second clock signal output by the second clock signal terminal CB V c2 is a high-level signal
  • the third clock signal V c3 output from the third clock signal terminal CK1 is a low-level signal
  • the input voltage Vin output from the input voltage terminal STV is a high-level voltage.
  • the voltages of the second node N2 and the fourth node N4 are the first power signal VH
  • the ninth transistor T9 and the eighth transistor T8 are turned off.
  • the first clock signal V c1 is a high-level signal, so that the twelfth transistor T12 and the eleventh transistor T11 are both turned off, the voltage at the third node N3 is still VL-Vth3, and the tenth transistor T10 and the fifth transistor T5 are both turned on. through.
  • the first power signal VH is transmitted to the intermediate output terminal GOUT through the tenth transistor T10, and the intermediate output signal V GOUT is the first power signal VH.
  • both the first transistor T1 and the second transistor T2 are turned off.
  • the third clock signal V c3 Under the control of the third clock signal V c3 , the third transistor T3 is turned on, and the voltage of the first node N1 is VL1-Vth10, so that the output signal V EOUT is maintained at the low-level second power signal VL.
  • the voltage of the first node N1 is periodically pulled down, thereby ensuring that the output signal V EOUT remains at the low level of the second power signal. VL.
  • FIG. 4 is a schematic block diagram of a gate driving circuit provided by some embodiments of the present disclosure
  • FIG. 5 is a schematic structural diagram of a gate driving circuit provided by some embodiments of the present disclosure
  • FIG. 6 is provided by some embodiments of the present disclosure.
  • At least one embodiment of the present disclosure further provides a gate driving circuit.
  • the gate driving circuit 1 includes a shift register 10 according to any one of the above embodiments of the present disclosure.
  • the gate driving circuit provided by the present disclosure can output a low-level signal with no threshold loss through the shift register 10, thereby improving the accuracy of the output scanning signal.
  • the gate driving circuit 1 includes a plurality of cascaded shift registers SR1, SR2, SR3,... SRn (n is an integer greater than 3).
  • SR1 represents the first-stage shift register
  • SR2 represents the second-stage shift register
  • SR3 represents the third-stage shift register
  • SRn represents the n-stage shift register.
  • These shift registers SR1, SR2, SR3,... SRn may all be shift registers described in any one of the above embodiments of the present disclosure.
  • the output terminals EOUT of the shift registers SR1, SR2, SR3 ... SRn are respectively connected to the gate lines G1, G2, G3 ... Gn in a one-to-one correspondence.
  • EOUT1 indicates the output terminal of the first stage shift register
  • EOUT2 indicates the output terminal of the second stage shift register
  • EOUT3 indicates the output terminal of the third stage shift register
  • EOUTn indicates the output terminal of the n stage shift register.
  • the input voltage terminal STV of the current-stage shift register is electrically connected to the intermediate output terminal GOUT of the upper-stage shift register, so as to be controlled by the intermediate output signal of the upper-stage shift register.
  • the working status of the next-stage shift register to output pulse scan signals in sequence.
  • the input voltage terminal STV of the first-stage shift register SR1 is connected to the trigger signal terminal STV0 (which is configured to provide a trigger signal to control the gate driving circuit to start working) to receive the trigger signal as the input voltage V in .
  • the gate driving circuit 1 further includes a signal generating circuit 20.
  • the signal generating circuit 20 is configured to generate a first control signal CK0, a second control signal CB0, a third control signal CK10, and a fourth control signal CK20.
  • the first control signal CK0 is the first clock signal of the shift register in the above embodiment
  • the second control signal CB0 is The second clock signal and the third control signal CK10 of the shift register in the above embodiment are the third clock signal of the shift register in the above embodiment.
  • the first control signal CK0 is the second clock signal of the shift register in the above embodiment
  • the second control signal CB0 is the first clock signal of the shift register in the above embodiment
  • the fourth The control signal CK20 is the third clock signal of the shift register in the above embodiment.
  • the first control signal CK0, the second control signal CB0, the third control signal CK10, and the fourth control signal CK20 alternately control the shift registers of the odd and even stages, thereby reducing the number of signals and reducing production costs.
  • the first control signal CK0 is applied to the first clock signal terminal CK of the 2N-1 stage shift register and the second clock signal terminal CB of the 2N stage shift register;
  • the second control signal CB0 is applied to the second clock signal terminal CB of the 2N-1 stage shift register and the first clock signal terminal CK of the 2N stage shift register;
  • the third control signal CK10 is applied to the 2N-1 stage shift register
  • the third clock signal terminal CK1 of the second clock signal is applied to the third clock signal terminal CK1 of the 2N-stage shift register.
  • N is a positive integer
  • N is greater than or equal to 1, and less than n / 2.
  • n may be an even number or an odd number, which is not limited in the present disclosure. In the example shown in FIG. 5, n is an even number.
  • the gate driving circuit 1 further includes a first power supply line VGH0, a second power supply line VGL0, and a third power supply line VGL10, so that the first power supply terminal VGH, the second power supply terminal VGL, and the The three power terminals VGL1 provide a first power signal VH, a second power signal VL, and a third power signal VL1.
  • upper level and lower level do not refer to the upper and lower levels in the scanning sequence, but refer to the upper and lower levels on the physical connection.
  • the trigger signal terminal STV0 provides the first-stage shift register SR1 with a trigger signal as an input voltage, thereby controlling the first stage
  • the stage shift register SR1 starts to work.
  • the first stage shift register SR1 outputs a first output signal V EOUT1 to the gate line G1 as a scan. signal.
  • the intermediate output signal V GOUT1 output from the first-stage shift register SR1 is transmitted to the second-stage shift register SR2 as the input voltage of the second-stage shift register SR2, so as to control the second-stage shift register SR2 to start working.
  • the second-stage shift register SR2 Under the control of the first control signal CK0, the second control signal CB0, and the fourth control signal CK20, the second-stage shift register SR2 outputs a second output signal V EOUT2 to the gate line G2 as a scanning signal.
  • the intermediate output signal V GOUT2 output from the second-stage shift register SR2 is transmitted to its next-stage shift register as the input voltage of its next-stage shift register, and so on, and finally the gate drive circuit finishes scanning one frame. jobs. For example, for a specific working process of the gate driving circuit, reference may be made to a working process of the shift register shown in FIG. 3.
  • FIG. 7 is a schematic diagram of a display panel according to an embodiment of the present disclosure.
  • Some embodiments of the present disclosure also provide a display device including a display panel 50 as shown in FIG. 7. As shown in FIG. 7, the display panel 50 of the display device includes a gate driving circuit 1 provided by any embodiment of the present disclosure.
  • the display panel 50 provided by the embodiment of the present disclosure further includes gate lines 2, data lines 3, and a plurality of pixel units 4 defined by the intersection of the gate lines 2 and the data lines 3.
  • the gate driving circuit 1 is It is configured to provide a gate driving signal to the gate line 2.
  • the display panel 50 may further include a data driving circuit (not shown in the figure) configured to provide a data signal to the data line 3.
  • the data signals provided by the data driving circuit are written line by line into a plurality of pixel units 4 defined in a crosswise manner to realize the progressive scanning of the display panel.
  • the gate line 2 may include gate lines G1, G2, G3, ..., Gn shown in FIG. 5, and each stage of the shift register SR1, SR2, SR3, ..., SRn is used to provide a corresponding gate line.
  • G1, G2, G3 ... Gn outputs a row of gate driving signals.
  • the display panel 50 may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • FIG. 8 is a flowchart of a driving method provided by some embodiments of the present disclosure.
  • Some embodiments of the present disclosure also provide a driving method for a shift register provided by any embodiment of the present disclosure. As shown in FIG. 8, the driving method includes the following steps:
  • Step S10 write the second clock signal output from the second clock signal terminal or the first power signal output from the first power terminal to the intermediate output terminal as the intermediate output signal under the control of the input voltage and the control circuit;
  • Step S20 Under the control of the intermediate output signal and the third clock signal output from the third clock signal terminal, output an output signal that is opposite to the intermediate output signal.
  • the driving method of the shift register provided by the embodiment of the present disclosure can realize the P-type thin film transistor to output a low-level signal without threshold loss, and improve the display quality of the display panel.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Shift Register Type Memory (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种移位寄存器及驱动方法、栅极驱动电路和显示装置。该移位寄存器包括：输入电路(100)，分别与输入电压端(STV)和第一时钟信号端(CK)电连接，被配置为在第一时钟信号端(CK)提供的第一时钟信号的控制下，将输入电压端(STV)提供的输入电压输入到中间电路(200)；中间电路(200)，分别与中间输出端(GOUT)、第一电源端(VGH)、第二电源端(VGL)、第一时钟信号端(CK)和第二时钟信号端(CB)电连接，且被配置为在输入电压和控制电路(300)的控制下，将第二时钟信号端(CB)输出的第二时钟信号或第一电源端(VGH)输出的第一电源信号写入中间输出端(GOUT)作为中间输出信号；输出电路(400)，分别与第一电源端(VGH)、第二电源端(VGL)、第三电源端(VGL1)、第三时钟信号端(CK1)、中间输出端(GOUT)和输出端(EOUT)电连接，且被配置为输出与中间输出信号反相的输出信号。该移位寄存器可以提升显示面板的显示质量。

Description

移位寄存器及驱动方法、栅极驱动电路和显示装置
本申请要求于2018年6月28日递交的中国专利申请第201810691092.0号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器及驱动方法、栅极驱动电路和显示装置。
背景技术
随着显示技术的飞速发展，显示面板越来越向着高集成度和低成本的方向发展。栅极驱动电路基板(Gate-driver on Array，GOA)技术是通过光刻工艺将栅极驱动电路直接集成在显示装置的阵列基板上，GOA电路通常包括多个级联的移位寄存器，每个移位寄存器均对应于一行像素所对应的栅线(例如，每个移位寄存器给与一行像素均连接的栅线提供扫描驱动信号)，以实现对显示面板的扫描驱动。GOA技术可以节省栅极集成电路(Integrated Circuit，IC)的绑定(Bonding)区域以及扇出(Fan-out)区域的空间，从而实现显示面板的窄边框，同时可以降低产品成本、提高产品的良率。
发明内容
本公开至少一实施例提供一种移位寄存器，包括：输入电路、控制电路、中间电路和输出电路，所述输入电路，分别与输入电压端和第一时钟信号端电连接，被配置为在所述第一时钟信号端提供的第一时钟信号的控制下，将所述输入电压端提供的输入电压输入到所述中间电路；所述中间电路，分别与中间输出端、第一电源端、第二电源端、所述第一时钟信号端和第二时钟信号端电连接，且被配置为在所述输入电压和所述控制电路的控制下，将所述第二时钟信号端输出的第二时钟信号或所述第一电源端输出的第一电源信号写入所述中间输出端作为中间输出信号；所述输出电路，分别与所述第一 电源端、所述第二电源端、第三电源端、第三时钟信号端、所述中间输出端和输出端电连接，且被配置为在所述输出端输出与所述中间输出信号反相的输出信号。
例如，在本公开一实施例提供的移位寄存器中，所述输出电路包括第一输出子电路、第二输出子电路和第一存储电路，所述第一输出子电路分别与所述第一电源端、所述中间输出端、所述输出端和第一节点电连接，且被配置为：在输出阶段，在所述中间输出信号的控制下，将所述第一电源信号写入所述输出端；所述第二输出子电路分别与所述第二电源端、所述第三电源端、所述第三时钟信号端、所述第一节点和所述输出端电连接，且被配置为：在输入阶段、缓冲阶段和稳定阶段，在所述第三时钟信号端输出的第三时钟信号的控制下将所述第二电源端提供的第二电源信号写入所述输出端；所述第一存储电路分别与所述第一节点和所述输出端电连接。
例如，在本公开一实施例提供的移位寄存器中，所述第一输出子电路包括第一晶体管和第二晶体管，所述第一晶体管的第一极与所述第一电源端电连接，所述第一晶体管的第二极与所述第一节点电连接，所述第一晶体管的栅极与所述中间输出端电连接，所述第二晶体管的第一极与所述第一电源端电连接，所述第二晶体管的第二极与所述输出端电连接，所述第二晶体管的栅极与所述中间输出端电连接；所述第二输出子电路包括第三晶体管和第四晶体管，所述第三晶体管的第一极与所述第一节点电连接，所述第三晶体管的第二极与所述第三电源端电连接，所述第三晶体管的栅极与所述第三时钟信号端电连接，所述第四晶体管的第一极与所述输出端电连接，所述第四晶体管的第二极与所述第二电源端电连接，所述第四晶体管的栅极与所述第一节点电连接；所述第一存储电路包括第一电容，所述第一电容的第一端与所述第一节点电连接，所述第一电容的第二端与所述输出端电连接。
例如，在本公开一实施例提供的移位寄存器中，所述第三电源端被配置为提供第三电源信号，所述第二电源信号大于所述第三电源信号。
例如，在本公开一实施例提供的移位寄存器中，所述第二电源信号和所述第三电源信号之间的关系表示为：
VL-VL1>|Vth10+Vth12|
其中，VL表示所述第二电源信号，VL1表示所述第三电源信号，Vth10 表示所述第三晶体管的阈值电压，Vth12表示所述第四晶体管的阈值电压。
例如，在本公开一实施例提供的移位寄存器中，所述中间电路被配置为：在所述输入阶段，在所述输入电压控制下，将所述第二时钟信号写入所述中间输出端作为所述中间输出信号；在所述输出阶段和所述缓冲阶段，将所述第二时钟信号写入所述中间输出端作为所述中间输出信号；以及在所述稳定阶段，在所述控制电路的控制下，将所述第一电源信号写入所述中间输出端作为所述中间输出信号。
例如，在本公开一实施例提供的移位寄存器中，所述中间电路包括：第一控制子电路，分别与第二节点、第三节点、第四节点、所述第一电源端、所述第二电源端和所述第二时钟信号端电连接，被配置为：在所述输入阶段，将所述输入电压写入所述第二节点；以及在所述稳定阶段，将所述第一电源信号写入所述第二节点；第二控制子电路，分别与所述第三节点、所述第四节点和所述第一时钟信号端电连接，被配置为将所述第一时钟信号写入所述第三节点；中间输出子电路，分别与所述第二节点、所述中间输出端和所述第二时钟信号端电连接，被配置为：在所述输入阶段、所述输出阶段和所述缓冲阶段，将所述第二时钟信号写入所述中间输出端作为所述中间输出信号。
例如，在本公开一实施例提供的移位寄存器中，所述第一控制子电路包括第五晶体管、第六晶体管和第七晶体管，所述第五晶体管的第一极与所述第一电源端电连接，所述第五晶体管的第二极与所述第六晶体管的第一极电连接，所述第五晶体管的栅极与所述第三节点电连接；所述第六晶体管的第二极与所述第四节点电连接，所述第六晶体管的栅极与所述第二时钟信号端电连接；所述第七晶体管的第一极与所述第四节点电连接，所述第七晶体管的第二极与所述第二节点电连接，所述第七晶体管的栅极与所述第二电源端电连接。
例如，在本公开一实施例提供的移位寄存器中，所述第二控制子电路包括第八晶体管，所述第八晶体管的第一极与所述第三节点电连接，所述第八晶体管的第二极与所述第一时钟信号端电连接，所述第八晶体管的栅极与所述第四节点电连接。
例如，在本公开一实施例提供的移位寄存器中，所述中间输出子电路包括第九晶体管，所述第九晶体管的第一极与所述第二时钟信号端电连接，所 述第九晶体管的第二极与所述中间输出端电连接，所述第九晶体管的栅极与所述第二节点电连接。
例如，在本公开一实施例提供的移位寄存器中，所述中间电路还包括：第二存储子电路，所述第二存储子电路包括第二电容，所述第二电容的第一端与所述第二节点电连接，所述第二电容的第二端与所述中间输出端电连接。
例如，在本公开一实施例提供的移位寄存器中，所述中间电路还包括：中间输出控制子电路，分别与所述第三节点、所述中间输出端和所述第一电源端电连接，被配置为：在所述稳定阶段，在所述控制电路的控制下，将所述第一电源信号写入所述中间输出端；以及第三存储子电路，分别与所述第三节点和所述第一电源端电连接。
例如，在本公开一实施例提供的移位寄存器中，所述中间输出控制子电路包括第十晶体管，所述第三存储子电路包括第三电容，所述第十晶体管的第一极与所述第一电源端电连接，所述第十晶体管的第二极与所述中间输出端电连接，所述第十晶体管的栅极与所述第三节点电连接；所述第三电容的第一端与所述第三节点电连接，所述第三电容的第二端与所述第一电源端电连接。
例如，在本公开一实施例提供的移位寄存器中，所述第二时钟信号的高电平与所述第一电源信号的电平相同，所述第二时钟信号的低电平与所述第二电源信号的电平相同。
例如，在本公开一实施例提供的移位寄存器中，所述控制电路包括第十一晶体管，所述第十一晶体管的第一极与所述第二电源端电连接，所述第十一晶体管的第二极与所述第三节点电连接，所述第十一晶体管的栅极与所述第一时钟信号端电连接。
例如，在本公开一实施例提供的移位寄存器中，所述第三时钟信号端输出的时钟信号的高电平与所述第一电源信号的电平相同，所述第三时钟信号端输出的时钟信号的低电平与所述第三电源信号的电平相同。
例如，在本公开一实施例提供的移位寄存器中，所述输入电路包括第十二晶体管，所述第十二晶体管的第一极与所述输入电压端电连接，所述第十二晶体管的第二极与所述第四节点电连接，所述第十二晶体管的栅极与所述第一时钟信号端电连接。
本公开至少一实施例还提供一种栅极驱动电路，包括如上述任一项所述的移位寄存器。
例如，在本公开一实施例提供的栅极驱动电路中，包括级联的多个上述任一项所述的移位寄存器，除第一级移位寄存器之外，本级移位寄存器的输入电压端与上一级移位寄存器的中间输出端电连接。
例如，本公开一实施例提供的栅极驱动电路还包括信号生成电路，所述信号生成电路被配置为生成第一控制信号、第二控制信号、第三控制信号和第四控制信号，所述第一控制信号被施加至第2N-1级移位寄存器的所述第一时钟信号端和第2N级移位寄存器的所述第二时钟信号端；所述第二控制信号被施加至所述第2N-1级移位寄存器的所述第二时钟信号端和所述第2N级移位寄存器的所述第一时钟信号端；所述第三控制信号被施加至所述第2N-1级移位寄存器的所述第三时钟信号端；所述第四控制信号被施加至所述第2N级移位寄存器的所述第三时钟信号端；其中，N为正整数，且N大于等于1。
本公开至少一实施例还提供一种显示装置，包括本公开任一实施例提供的栅极驱动电路。
本公开至少一实施例还提供一种移位寄存器的驱动方法，包括：在所述输入电压和所述控制电路的控制下，将所述第二时钟信号端输出的所述第二时钟信号或所述第一电源端输出的所述第一电源信号写入所述中间输出端作为所述中间输出信号；在所述中间输出信号和所述第三时钟信号端输出的所述第三时钟信号的控制下，在所述输出端输出与所述中间输出信号反相的输出信号。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开一些实施例提供的一种移位寄存器的示意性框图；
图2为本公开一些实施例提供的一种移位寄存器的一种具体实现示例的电路结构示意图；
图3为本公开一些实施例提供的一种移位寄存器的驱动时序图；
图4为本公开一些实施例提供的一种栅极驱动电路的示意性框图；
图5本公开一些实施例提供的一种栅极驱动电路的结构示意；
图6为本公开一些实施例提供的一种栅极驱动电路的驱动时序图；
图7本公开一些实施例提供的一种显示面板的示意图；
图8本公开一些实施例提供的一种驱动方法的流程图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
为了保持本公开实施例的以下说明清楚且简明，本公开省略了已知功能和已知部件的详细说明。
目前，在有机发光二极管显示面板(OLED)和液晶显示面板(LCD)中，在栅极驱动电路的移位寄存器中的晶体管为P型薄膜晶体管，且栅极驱动电路(例如，GOA电路)需要输出高脉冲信号的情况下，由于P型薄膜晶体管输出的低电平信号存在阈值损失，使得该GOA电路输出的高脉冲信号不准确，从而影响显示效果、降低显示质量。因此，如何设计结构简单且P型薄膜晶体管输出无阈值损失的低电平信号的GOA电路成为亟待解决的问 题。
本公开至少一实施例提供一种移位寄存器及栅极驱动电路，该移位寄存器通过增加第三电源端输出的直流电源信号，从而可以实现P型薄膜晶体管输出无阈值损失的低电平信号，提升显示面板的显示质量；另一方面，该移位寄存器的结构简单，生产成本较低。
下面结合附图对本公开的一些实施例进行详细说明，但是本公开并不限于这些具体的实施例。
图1为本公开一些实施例提供的一种移位寄存器的示意性框图，图2为本公开一些实施例提供的一种移位寄存器的一种具体实现示例的电路结构示意图。
本公开的实施例提供一种移位寄存器。例如，如图1所示，该移位寄存器包括输入电路100、中间电路200、控制电路300和输出电路400。
例如，如图1所示，输入电路100分别与输入电压端STV和第一时钟信号端CK电连接，输入电路100还与中间电路200电连接。输入电压端STV被配置为提供输入电压V in，第一时钟信号端CK被配置为提供第一时钟信号V c1。输入电路100被配置为在第一时钟信号端CK提供的第一时钟信号V c1的控制下，将输入电压端STV提供的输入电压V in输入到中间电路200。也就是说，当输入电路100在第一时钟信号V c1的控制下导通时，使得输入电压端STV与中间电路200连接，输入电压V in可以被传输至中间电路200。
例如，如图1所示，中间电路200分别与中间输出端GOUT、第一电源端VGH、第二电源端VGL、第一时钟信号端CK和第二时钟信号端CB电连接。第一电源端VGH被配置为提供第一电源信号VH，第二电源端VGL被配置为提供第二电源信号VL，第二时钟信号端CB被配置为输出第二时钟信号V c2。中间电路200被配置为在输入电压V in和控制电路300的控制下，将第二时钟信号端CB输出的第二时钟信号V c2或第一电源端VGH输出的第一电源信号VH写入中间输出端GOUT作为中间输出信号V GOUT。也就是说，在输入电压V in和控制电路300的控制下，当中间电路200将第二时钟信号端CB和中间输出端GOUT导通时，第二时钟信号V c2可以被写入中间输出端GOUT作为中间输出信号V GOUT；或者，当中间电路200将第一电源端VGH和中间输出端GOUT导通，第一电源信号VH可以被写入中间输出端 GOUT作为中间输出信号V GOUT。
例如，如图1所示，控制电路300分别与第二电源端VGL、第一时钟信号端CK和中间电路200电连接。控制电路300被配置为在第一时钟信号端CK提供的第一时钟信号V c1的控制下，将第二电源端VGL输出的第二电源信号VL输出至中间电路200。也就是说，当控制电路300在第一时钟信号V c1的控制下导通时，使得第二电源端VGL和中间电路200连接，从而第二电源信号VL可以被传输至中间电路200。
例如，如图1所示，输出电路400分别与第一电源端VGH、第二电源端VGL、第三电源端VGL1、第三时钟信号端CK1、中间输出端GOUT和输出端EOUT电连接。第三电源端VGL1被配置为提供第三电源信号VL1，第三时钟信号端CK1被配置为提供第三时钟信号V c3。输出电路400被配置为输出与中间输出信号V GOUT反相的输出信号V EOUT。例如，在中间输出信号V GOUT和第三时钟信号V c3的控制下，当输出电路400的连接第一电源端VGH的一端和连接输出端EOUT的一端相互导通时，输出电路400将第一电源信号VH传输至输出端EOUT以作为输出信号V EOUT的高电平信号；而当输出电路400的连接第二电源端VGL的一端和连接输出端EOUT的一端相互导通时，输出电路400将第二电源信号VL传输至输出端EOUT以作为输出信号V EOUT的低电平信号。
例如，第二电源信号VL大于第三电源信号VL1，从而可以减少经由输出晶体管(例如，图2中所示的第四晶体管T4)输出至输出端EOUT的第二电源信号VL的阈值损失。
例如，第一电源信号VH、第二电源信号VL和第三电源信号VL1均为直流信号。第一电源信号VH为高电平信号(例如5V、10V或其他电压)；第二电源信号VL为低电平信号(例如0V、-1V或其他电压)，第三电源信号VL1也为低电平信号(例如-2V、-1V或其他电压)。需要说明的是，低电平信号和高电平信号是相对而言的，低电平信号小于高电平信号。在不同的实施方式中，高电平信号的数值可能不同，低电平信号的数值也可能不同，只要第二电源信号VL大于第三电源信号VL1即可，本公开的实施例对此不作限制。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或 场效应晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，所以本公开实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。例如，本公开实施例所述的晶体管的第一极可以为源极，第二极可以为漏极；或者，晶体管的第一极为漏极，第二极为源极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V或其他数值)，关闭电压为高电平电压(例如，5V、10V或其他数值)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他数值)，关闭电压为低电平电压(例如，0V、-5V或其他数值)。
例如，在本公开的一些实施例中，所有晶体管为P型晶体管。
例如，如图1所示，输出电路400可以包括第一输出子电路401、第二输出子电路402和第一存储电路403。
例如，第一输出子电路401分别与第一电源端VGH、中间输出端GOUT、输出端EOUT和第一节点N1电连接，且第一输出子电路401被配置为在输出阶段，在中间输出信号V GOUT的控制下，将第一电源信号VH写入输出端EOUT以作为输出信号V EOUT的高电平信号。
例如，第二输出子电路402分别与第二电源端VGL、第三电源端VGL1、第三时钟信号端CK1、第一节点N1和输出端EOUT电连接，且第二输出子电路402被配置为在输入阶段、缓冲阶段和稳定阶段，在第三时钟信号端CK1输出的第三时钟信号V c3的控制下将第二电源端VGL提供的第二电源信号VL写入输出端EOUT以作为输出信号V EOUT的低电平信号。
例如，第一存储电路403分别与第一节点N1和输出端EOUT电连接。
例如，如图2所示，第一输出子电路401包括第一晶体管T1和第二晶体管T2。第一晶体管T1的第一极与第一电源端VGH电连接以接收第一电源信号VH，第一晶体管T1的第二极与第一节点N1电连接，第一晶体管T1的栅极与中间输出端GOUT电连接；第二晶体管T2的第一极与第一电源端VGH电连接以接收第一电源信号VH，第二晶体管T2的第二极与所输出端EOUT电连接，第二晶体管T2的栅极与中间输出端GOUT电连接。
例如，第二输出子电路402包括第三晶体管T3和第四晶体管T4，第三晶体管T3的第一极与第一节点N1电连接，第三晶体管T3的第二极与第三电源端VGL1电连接以接收第三电源信号VL1，第三晶体管T3的栅极与第三时钟信号端CK1电连接以接收第三时钟信号V c3；第四晶体管T4的第一极与输出端EOUT电连接，第四晶体管T4的第二极与第二电源端VGL电连接以接收第二电源信号VL，第四晶体管T4的栅极与第一节点N1电连接。
例如，在该输出电路400中，由于第三电源端VGL1提供的第三电源电压VL1比第二电源电压VL小，该第三电源电压VL1可以控制第四晶体管T4的导通程度(例如，可以完全导通)，当第四晶体管T4输出低电平的第二电源信号VL至输出端EOUT时，第二电源信号VL无阈值损失，即输出信号V EOUT无阈值损失，从而实现P型晶体管无阈值损失输出低电平信号，提升显示面板的显示质量。
需要说明的是，图2中所示的输出电路400仅为示例性的实施方式，本公开实施例提供的输出电路400包括但不局限于图2中所示的输出电路400。
例如，第二电源信号VL和第三电源信号VL1之间的关系可以表示为：
VL-VL1>|Vth10+Vth12|
其中，Vth10表示第三晶体管T3的阈值电压，Vth12表示第四晶体管T4的阈值电压。例如，当第三时钟信号CK1为低电平时，第三时钟信号V c3的低电平例如与第三电源信号VL1的电平相等，即第三晶体管T3的栅极的电压为第三电源信号VL1，则当第三晶体管T3的源极的电压低于VL1-Vth10时，第三晶体管T3截止，即第三晶体管T3的源极的电压最低可达到VL1-Vth10。也就是说，当第三晶体管T3导通，第三电源信号VL1被传输至第一节点N1(即，第四晶体管T4的栅极)，由于第三晶体管T3的传输阈值损失，且第三电源信号VL1为低电平信号，当第一节点N1的电压为VL1-Vth10时(此时，第三晶体管T3的栅源电压为Vth10)，第三晶体管T3截止，无法继续传输低电平信号。由此，第三晶体管T3传输至第四晶体管T4的栅极的电压为VL1-Vth10。该电压(VL1-Vth10)可以控制第四晶体管T4导通，从而第二电源信号VL经由第四晶体管T4被传输至输出端EOUT。由于第四晶体管T4的栅极的电压为VL1-Vth10，则当第四晶体管T4的源极的电压低于VL1-Vth10-Vth12时，第四晶体管T4截止，从而第四 晶体管T4的源极的电压最低可以为VL1-Vth10-Vth12，也就是说，当输出端EOUT的输出信号V EOUT为VL1-Vth10-Vth12(由于Vth10和Vth12均小于零，即VL1-Vth10-Vth12＝VL1+|Vth10+Vth12|)时，第四晶体管T4截止。当第二电源信号VL被完全传输至输出端EOUT，即输出信号V EOUT为第二电源信号VL时，第四晶体管T4的栅源电压Vgs12为VL1-Vth10-VL，由于VL-VL1>|Vth10+Vth12|，即VL1-Vth10-VL<Vth12，也就是说，该栅源电压Vgs12小于第四晶体管T4的阈值电压Vth12，因此，当输出信号V EOUT为第二电源信号VL时，第四晶体管T4仍然处于开启状态，从而第二电源信号VL可以无损失地被传输至输出端EOUT。
例如，在一个具体示例中，若第三晶体管T3的阈值电压Vth10为-0.5V，第四晶体管T4的阈值电压Vth12为-0.5V，第二电源信号VL为-4V，第三电源信号VL1为-6V。第三晶体管T3导通，第三电源信号VL1被传输至第一节点N1，由于第三晶体管T3的传输阈值损失，第一节点N1的电压最低可以为-5.5V(即，-6V-(-0.5)＝-5.5V)，即当第一节点N1的电压为-5.5V时，第三晶体管T3截止，第三电源信号VL1无法完全被传输至第一节点N1。第四晶体管T4的栅极的电压为-5.5V，由此，第四晶体管T4的源极的电压最低可以为-5V(即，-5.5V-(-0.5)＝-5V)。此时，第四晶体管T4开启，第二电源信号VL经由第四晶体管T4被传输至输出端EOUT，由于第四晶体管T4的源极的电压最低可以为-5V，即当输出信号V EOUT为-4V(即第二电源信号VL)时，第四晶体管T4仍然处于开启状态，也就是说，第二电源信号VL可以无损失地被传输至输出端EOUT。
综上，在本公开提供的移位寄存器可以无阈值损失地输出低电平的第二电源信号VL至输出端EOUT。
例如，如图2所示，第一存储电路403包括第一电容C1，第一电容C1的第一端与第一节点N1电连接，第一电容C1的第二端与输出端EOUT电连接。
例如，中间电路200被配置为：在输入阶段，在输入电压Vin控制下，将第二时钟信号V c2写入中间输出端GOUT作为中间输出信号V GOUT；在输出阶段和缓冲阶段，将第二时钟信号V c2写入中间输出端GOUT作为中间输出信号V GOUT；以及在稳定阶段，在控制电路300的控制下，将第一电源信 号VH写入中间输出端GOUT作为中间输出信号V GOUT。例如，中间输出信号V GOUT可以用于控制输出电路400中的例如第一输出子电路401导通或断开。
例如，如图1所示，中间电路200可以包括第一控制子电路201、第二控制子电路202、中间输出子电路203、第二存储子电路204、中间输出控制子电路205和第三存储子电路206。例如，在本公开实施例中，下拉控制子电路为第一控制子电路201的一个示例，上拉控制子电路为第二控制子电路202的一个示例，中间输出上拉子电路为中间输出控制子电路205的一个示例，下面以第一控制子电路201为下拉控制子电路，第二控制子电路202为上拉控制子电路，中间输出控制子电路为中间输出上拉子电路为例进行说明，但是本公开的实施例不限于此，以下实施例与此相同，不再赘述。
例如，如图1所示，下拉控制子电路201分别与第二节点N2、第三节点N3、第四节点N4、第一电源端VGH、第二电源端VGL和第二时钟信号端CB电连接。下拉控制子电路201用于控制第二节点N2的电压，当第二节点N2的电压可以控制中间输出子电路203导通时，中间输出子电路203可以将第二时钟信号V c2写入中间输出端GOUT以作为中间输出信号V GOUT。例如，下拉控制子电路201被配置为：在输入阶段，将输入电压Vin写入第二节点N2；以及在稳定阶段，将第一电源信号VH写入第二节点N2。
例如，如图1所示，上拉控制子电路202分别与第三节点N3、第四节点N4和第一时钟信号端CK电连接。上拉控制子电路202用于控制第三节点N3的电压，当第三节点N3的电压可以控制中间输出上拉子电路205导通时，中间输出上拉子电路205可以将第一电源信号VH写入中间输出端GOUT，从而控制(例如，拉高)中间输出端GOUT的电位。例如，上拉控制子电路202被配置为将第一时钟信号V c1写入第三节点N3。
例如，如图1所示，中间输出子电路203分别与第二节点N2、中间输出端GOUT和第二时钟信号端CB电连接。中间输出子电路203被配置为：在输入阶段、输出阶段和缓冲阶段，将第二时钟信号V c2写入中间输出端GOUT作为中间输出信号V GOUT。
例如，如图1所示，第二存储子电路204分别与第二节点N2和中间输出端GOUT电连接。第二存储子电路204用于维持第二节点N2处的电压。
例如，如图1所示，中间输出上拉子电路205分别与第三节点N3、中间输出端GOUT和第一电源端VGH电连接。中间输出上拉子电路205被配置为：在稳定阶段，在控制电路300的控制下，将第一电源信号VH写入中间输出端GOUT。第三存储子电路206分别与第三节点N3和第一电源端VGH电连接。中间输出上拉子电路205用于控制中间输出端GOUT的电位，例如，将中间输出端GOUT的电位拉高；第三存储子电路206用于维持第三节点N3处的电压。
例如，如图2所示，下拉控制子电路201包括第五晶体管T5、第六晶体管T6和第七晶体管T7。第五晶体管T5的第一极与第一电源端VGH电连接以接收第一电源信号VH，第五晶体管T5的第二极与第六晶体管T6的第一极电连接，第五晶体管T5的栅极与第三节点N3电连接；第六晶体管T6的第二极与第四节点N4电连接，第六晶体管T6的栅极与第二时钟信号端CB电连接以接收第二时钟信号V c2；第七晶体管T7的第一极与第四节点N4电连接，第七晶体管T7的第二极与第二节点N2电连接，第七晶体管T7的栅极与第二电源端VGL电连接以接收第二电源信号VL。
例如，如图2所示，上拉控制子电路202包括第八晶体管T8。第八晶体管T8的第一极与第三节点N3电连接，第八晶体管T8的第二极与第一时钟信号端CK电连接以接收第一时钟信号V c1，第八晶体管T8的栅极与第四节点N4电连接。
例如，如图2所示，中间输出子电路203包括第九晶体管T9,第二存储子电路204包括第二电容C2。第九晶体管T9的第一极与第二时钟信号端CB电连接以接收第二时钟信号V c2，第九晶体管T9的第二极与中间输出端GOUT电连接，第九晶体管T9的栅极与第二节点N2电连接。第二电容C2的第一端与第二节点N2电连接，第二电容C2的第二端与中间输出端GOUT电连接。
例如，如图2所示，中间输出上拉子电路205包括第十晶体管T10，第三存储子电路206包括第三电容C3。第十晶体管T10的第一极与第一电源端VGH电连接，第十晶体管T10的第二极与中间输出端GOUT电连接，第十晶体管T10的栅极与第三节点N3电连接；第三电容C3的第一端与第三节点N3电连接，第三电容C3的第二端与第一电源端VGH电连接以接收第 一电源信号VH。
例如，控制电路300用于在稳定阶段控制中间输出上拉子电路205将中间输出端GOUT的电压稳定在第一电源电压VH。如图2所示，控制电路300包括第十一晶体管T11。第十一晶体管T11的第一极与第二电源端VGL电连接以接收第二电源信号VL，第十一晶体管T11的第二极与第三节点N3电连接，第十一晶体管T11的栅极与第一时钟信号端CK电连接以接收第一时钟信号V c1。
例如，输入电路100用于向中间电路200传输输入电压Vin，以触发移位寄存器进行工作。如图2所示，输入电路100包括第十二晶体管T12。第十二晶体管T12的第一极与输入电压端STV电连接，第十二晶体管T12的第二极与第四节点N4电连接，第十二晶体管T12的栅极与第一时钟信号端CK电连接以接收第一时钟信号V c1。
需要说明的是，图2所示的输入电路100、中间电路200和控制电路300仅为本公开实施例的一个示例，本公开的实施例包括但不局限于图2所示的情形。
例如，第一时钟信号V c1的高电平与第一电源信号VH的电平相同，第一时钟信号V c1的低电平与第二电源信号VL的电平相同。
例如，由于在输入阶段，第一电源信号VH和第二时钟信号V c2的高电平信号同时被传输至中间输出端GOUT，从而第二时钟信号V c2的高电平与第一电源信号VH的电平相同，以防止在同一时刻中间输出端GOUT的电压信号出现冲突的现象。第二时钟信号V c2的低电平与第二电源信号VL的电平相同。
例如，第三时钟信号端CK1输出的第三时钟信号V c3的高电平与第一电源信号VH的电平相同。第三时钟信号端CK1输出的第三时钟信号V c3的低电平与第三电源信号VL1的电平相同，以保证第四晶体管T4能够完全打开，从而输出无阈值损失的第二电源信号VL。
需要说明的是，第一时钟信号V c1的高电平和第三时钟信号V c3的高电平也可以与第一电源信号VH的电平不相同，第一时钟信号V c1的低电平也可以与第二电源信号VL的电平不相同，第三时钟信号V c3的低电平也可以与第三电源信号VL1的电平不相同，只要第一时钟信号V c1和第三时钟信号 V c3能够执行其自身的功能即可，本公开对此不作限制。另外，第二时钟信号V c2的低电平也可以与第二电源信号VL的电平不相同。在本公开实施例中，以第一时钟信号V c1的高电平和第三时钟信号V c3的高电平与第一电源信号VH的电平相同，第一时钟信号V c1的低电平与第二电源信号VL的电平相同，第三时钟信号V c3的低电平与第三电源信号VL1的电平相同，第二时钟信号V c2的低电平与第二电源信号VL的电平相同为例描述本公开提供的移位寄存器。
图3是本公开一些实施例提供的一种移位寄存器的驱动时序图。接下来以图2所示的移位寄存器和图3所示的驱动时序为例介绍本公开实施例提供的移位寄存器的工作原理。
例如，如图3所示，本公开实施例提供的移位寄存器的工作过程包括输入阶段t1、输出阶段t2、缓冲阶段t3和稳定阶段t4。
例如，如图2和图3所示，在输入阶段t1，第一时钟信号端CK输出的第一时钟信号V c1为低电平信号，第二时钟信号端CB输出的第二时钟信号V c2为高电平信号，第三时钟信号端CK1输出的第三时钟信号V c3为低电平信号，输入电压端STV输出的输入电压Vin为低电平电压，例如输入电压Vin与第二电源信号VL相等。由于第一时钟信号V c1为低电平电压，第十二晶体管T12导通，输入电压Vin经由第十二晶体管T12传输至第四节点N4，由于第十二晶体管T12传递低电平信号具有阈值损失，从而第四节点N4的电压为Vin-Vth1，即VL-Vth1，其中，Vth1表示第十二晶体管T12的阈值电压。由于第七晶体管T7的栅极接收第二电源电压VL，从而第七晶体管T7处于开启状态，由此，电压VL-Vth1经由第七晶体管T7传输至第二节点N2，例如，第七晶体管T7的阈值电压表示为Vth8，同理，由于第七晶体管T7传递低电平信号具有阈值损失，第二节点N2的电压为VL-VthN2，其中，VthN2为Vth1和Vth8中较小的一个。第二节点N2的电压可以控制第九晶体管T9导通，第二时钟信号V c2经由第九晶体管T9被写入中间输出端GOUT以作为中间输出信号V GOUT，即在输入阶段t1，中间输出信号V GOUT为高电平的第二时钟信号V c2，即第一电源信号VH，从而第一晶体管T1和第二晶体管T2均断开。第三时钟信号V c3为低电平电压，从而第三晶体管T3导通，第三电源信号VL1被传输至第一节点N1(即，第四晶体管T4的栅极)，由 于第三晶体管T3传递低电平信号具有阈值损失，第一节点N1上的电压为VL1-Vth10，该电压VL1-Vth10可以控制第四晶体管T4导通，第二电源信号VL经由第四晶体管T4被传输至输出端EOUT，当输出端EOUT的输出信号V EOUT为VL1+|Vth10+Vth12|时，第四晶体管T4截止，由于VL-VL1>|Vth10+Vth12|，也就是说，当输出信号V EOUT为第二电源信号VL时，第四晶体管T4仍然处于开启状态，从而第二电源信号VL可以无损失地传输至输出端EOUT，也就是说，在输入阶段t1，输出信号V EOUT为第二电源信号VL。
例如，在输入阶段t1，由于第一时钟信号V c1为低电平电压，第十一晶体管T11导通，第二电源信号VL经由第十一晶体管T11传输至第三节点N3，由于第四节点N4的电压为VL-Vth1，第八晶体管T8导通，低电平第一时钟信号V c1经由第八晶体管T8传输至第三节点N3。例如，第八晶体管T8的阈值电压表示为Vth2，第十一晶体管T11的阈值电压表示为Vth3，当Vth3<Vth2+Vth1，则第三节点N3的电压为VL-Vth2-Vth1；而当Vth3>Vth2+Vth1，则第三节点N3的电压为VL-Vth3。此时，第十晶体管T10和第五晶体管T5均导通。由于第二时钟信号V c2为高电平信号，第六晶体管T6截止。
例如，如图2和图3所示，在输出阶段t2，第一时钟信号端CK输出的第一时钟信号V c1和第三时钟信号端CK1输出的第三时钟信号V c3均为高电平信号，第二时钟信号端CB输出的第二时钟信号V c2为低电平信号，输入电压端STV输出的输入电压Vin为高电平电压。第九晶体管T9导通，第二时钟信号V c2经由第九晶体管T9被写入中间输出端GOUT以作为中间输出信号V EOUT。在输入阶段t1，第二电容C2的连接中间输出端GOUT的一端的电压为第一电源信号VH，第二电容C2的连接第二节点N2的一端的电压为VL-VthN2，而在输出阶段t2，第二电容C2的连接中间输出端GOUT的一端的电压变为VL，即，变化量为VL-VH，由于第二电容C2的自举作用，第二电容C2的连接第二节点N2的一端的电压变为2VL-VthN2-VH，即第二节点N2的电压变为2VL-VthN2-VH，此时，第七晶体管T7截止，第九晶体管T9可以更好地打开，输出信号V EOUT为第二电源信号VL。第三时钟信号V c3为高电平信号，从而第三晶体管T3截止。由于第二时钟信号V c2为低电 平信号，从而第一晶体管T1和第二晶体管T2均导通。第一电源信号VH可以经由第一晶体管T1传输至第一节点N1，从而第四晶体管T4截止；同时，第一电源信号VH还可以经由第二晶体管T2传输至输出端EOUT以作为输出信号V EOUT，此时，输出信号V EOUT为第一电源信号VH。
例如，在输出阶段t2，第一时钟信号V c1为高电平信号，从而第十二晶体管T12和第十一晶体管T11均截止。第四节点N4的电压仍为VL-VthN2，第八晶体管T8导通，高电平第一时钟信号V c1经由第八晶体管T8传输至第三节点N3，即第三节点N3的电压为第一电源信号VH，由此，第十晶体管T10和第五晶体管T5均截止。由于第二时钟信号V c2为低电平信号，第六晶体管T6导通。
例如，如图2和图3所示，在缓冲阶段t3，第一时钟信号端CK输出的第一时钟信号V c1和第二时钟信号端CB输出的第二时钟信号V c2均为高电平信号，第三时钟信号端CK1输出的第三时钟信号V c3为低电平信号，输入电压端STV输出的输入电压Vin为高电平电压。第九晶体管T9导通，第二时钟信号V c2经由第九晶体管T9被写入中间输出端GOUT以作为中间输出信号V EOUT，此时，中间输出信号V EOUT为高电平的第二时钟信号V c2，即第一电源信号VH，由于第二电容C2的自举作用，第二节点N2的电压变为VL-VthN2。中间输出信号V EOUT为第一电源信号VH，第一晶体管T1和第二晶体管T2均断开。第三时钟信号V c3为低电平电压，从而第三晶体管T3导通，第三电源信号VL1被传输至第一节点N1，第一节点N1上的电压为VL1-Vth10，该电压VL1-Vth10可以控制第四晶体管T4导通，第二电源信号VL可以无损失地传输至输出端EOUT，输出信号V EOUT为第二电源信号VL。
例如，在缓冲阶段t3，第一时钟信号V c1为高电平信号，从而第十二晶体管T12和第十一晶体管T11均截止。第二节点N2的电压变为VL-VthN2，此时，第七晶体管T7导通，第四节点N4的电压也为VL-VthN2，第八晶体管T8导通，高电平第一时钟信号V c1经由第八晶体管T8传输至第三节点N3，即第三节点N3的电压为第一电源信号VH，由此，第十晶体管T10和第五晶体管T5均截止。由于第二时钟信号V c2为高电平信号，第六晶体管T6截止。
例如，如图2和图3所示，在稳定阶段t4的第一子阶段t41中，第一时 钟信号端CK输出的第一时钟信号V c1为低电平信号，第二时钟信号端CB输出的第二时钟信号V c2为高电平信号，第三时钟信号端CK1输出的第三时钟信号V c3为低电平信号，输入电压端STV输出的输入电压Vin为高电平电压，例如输入电压Vin与第一电源信号VH相等。由于第一时钟信号V c1为低电平信号，第十二晶体管T12导通，输入电压Vin经由第十二晶体管T12传输至第四节点N4，由于第十二晶体管T12传递高电平信号无阈值损失，第四节点N4的电压为输入电压Vin(即，第一电源信号VH)，第八晶体管T8截止。由于第七晶体管T7处于开启状态，第二节点N2的电压与第四节点N4相同，也就是说，第二节点N2的电压为第一电源信号VH，第九晶体管T9截止。由于第一时钟信号V c1为低电平信号，第十一晶体管T11导通，第三节点N3的电压为VL-Vth3，第十晶体管T10和第五晶体管T5均导通，第一电源信号VH经由第十晶体管T10传输至中间输出端GOUT，即中间输出信号V GOUT为第一电源信号VH。在中间输出信号V GOUT的控制下，第一晶体管T1和第二晶体管T2均断开。在第三时钟信号V c3的控制下第三晶体管T3导通，第三电源信号VL1经由第三晶体管T3被传输至第一节点N1，第一节点N1的电压为VL1-Vth10，该VL1-Vth10可以控制第四晶体管T4导通，第二电源信号VL经由第四晶体管T4被传输至输出端EOUT，从而输出信号V EOUT保持为低电平的第二电源信号VL。
例如，如图2和图3所示，在稳定阶段t4的第二子阶段t42中，第一时钟信号端CK输出的第一时钟信号V c1和第三时钟信号端CK1输出的第三时钟信号V c3均为高电平信号，第二时钟信号端CB输出的第二时钟信号V c2为低电平信号，输入电压端STV输出的输入电压Vin为高电平电压。第二节点N2和第四节点N4的电压为输入电压Vin(即，第一电源信号VH)，第九晶体管T9和第八晶体管T8均截止。第一时钟信号V c1为高电平信号，从而第十二晶体管T12和第十一晶体管T11均截止，由于第三电容C3的保持作用，第三节点N3的电压仍为(VL-Vth3)，第十晶体管T10和第五晶体管T5均导通，第一电源信号VH经由第十晶体管T10传输至中间输出端GOUT，中间输出信号V GOUT为第一电源信号VH。在中间输出信号V GOUT的控制下，第一晶体管T1和第二晶体管T2均断开。由于第三时钟信号V c3均为高电平信号，第三晶体管T3截止，由于第一电容C1的保持作用，第一 节点N1的电压仍然保持为VL1-Vth10，从而第二电源信号VL仍然可以经由第四晶体管T4被传输至输出端EOUT，以保证输出信号V EOUT仍然保持为低电平的第二电源信号VL。
例如，如图2和图3所示，在第二子阶段t42中，由于第二时钟信号V c2为低电平信号，第六晶体管T6导通，从而第一电源信号VH经由第五晶体管T5和第六晶体管T6被传输至第四节点N4和第二节点N2，以使第二节点N2的电压和第四节点N4的电压保持为高电平。
例如，如图2和图3所示，在稳定阶段t4的第三子阶段t43中，第一时钟信号端CK输出的第一时钟信号V c1和第二时钟信号端CB输出的第二时钟信号V c2均为高电平信号，第三时钟信号端CK1输出的第三时钟信号V c3为低电平信号，输入电压端STV输出的输入电压Vin为高电平电压。第二节点N2和第四节点N4的电压为第一电源信号VH，第九晶体管T9和第八晶体管T8截止。第一时钟信号V c1为高电平信号，从而第十二晶体管T12和第十一晶体管T11均截止，第三节点N3的电压仍为VL-Vth3，第十晶体管T10和第五晶体管T5均导通。第一电源信号VH经由第十晶体管T10传输至中间输出端GOUT，中间输出信号V GOUT为第一电源信号VH。在中间输出信号V GOUT的控制下，第一晶体管T1和第二晶体管T2均断开。在第三时钟信号V c3的控制下第三晶体管T3导通，第一节点N1的电压为VL1-Vth10，从而输出信号V EOUT保持为低电平的第二电源信号VL。
综上所述，在稳定阶段t4，在第三时钟信号V c3的控制下，第一节点N1的电压周期性地被拉低，从而保证输出信号V EOUT保持为低电平的第二电源信号VL。
图4为本公开一些实施例提供的一种栅极驱动电路的示意性框图，图5本公开一些实施例提供的一种栅极驱动电路的结构示意，图6为本公开一些实施例提供的一种栅极驱动电路的驱动时序图。
本公开至少一实施例还提供一种栅极驱动电路，如图4所示，该栅极驱动电路1包括本公开上述实施例中任一项所述的移位寄存器10。本公开提供的栅极驱动电路可以通过移位寄存器10输出无阈值损失的低电平信号，提高输出的扫描信号的精确度。
例如，如图5所示，栅极驱动电路1包括级联的多个移位寄存器SR1、 SR2、SR3……SRn(n为大于3的整数)。例如，SR1表示第1级移位寄存器，SR2表示第2级移位寄存器，SR3表示第3级移位寄存器，SRn表示第n级移位寄存器。这些移位寄存器SR1、SR2、SR3……SRn均可以是本公开上述实施例中任一项所述的移位寄存器。这些移位寄存器SR1、SR2、SR3……SRn的输出端EOUT分别与多条栅线G1、G2、G3……Gn一一对应连接。
相应地，EOUT1表示第1级移位寄存器的输出端，EOUT2表示第2级移位寄存器的输出端，EOUT3表示第3级移位寄存器的输出端，EOUTn表示第n级移位寄存器的输出端。
例如，除第一级移位寄存器之外，本级移位寄存器的输入电压端STV与上一级移位寄存器的中间输出端GOUT电连接，从而通过上一级移位寄存器的中间输出信号控制下一级移位寄存器的工作状态，以实现依次输出脉冲扫描信号。
例如，第一级移位寄存器SR1的输入电压端STV与触发信号端STV0(其被配置为提供触发信号，以控制栅极驱动电路开始工作)连接，以接收触发信号作为输入电压V in。
例如，如图4所示，栅极驱动电路1还包括信号生成电路20。如图5所示，信号生成电路20被配置为生成第一控制信号CK0、第二控制信号CB0、第三控制信号CK10和第四控制信号CK20。例如，对于第2N-1级(N为正整数，且N大于等于1)移位寄存器，第一控制信号CK0为上述实施例中的移位寄存器的第一时钟信号，第二控制信号CB0为上述实施例中的移位寄存器的第二时钟信号，第三控制信号CK10为上述实施例中的移位寄存器的第三时钟信号。对于第2N级移位寄存器，第一控制信号CK0为上述实施例中的移位寄存器的第二时钟信号，第二控制信号CB0为上述实施例中的移位寄存器的第一时钟信号，第四控制信号CK20为上述实施例中的移位寄存器的第三时钟信号。第一控制信号CK0、第二控制信号CB0、第三控制信号CK10和第四控制信号CK20交替控制奇数级和偶数级的移位寄存器，从而减少信号数量，降低生产成本。
例如，如图5所示，第一控制信号CK0被施加至第2N-1级移位寄存器的第一时钟信号端CK和第2N级移位寄存器的第二时钟信号端CB；第二控制信号CB0被施加至第2N-1级移位寄存器的第二时钟信号端CB和第2N级 移位寄存器的第一时钟信号端CK；第三控制信号CK10被施加至第2N-1级移位寄存器的第三时钟信号端CK1；第四控制信号CK20被施加至第2N级移位寄存器的第三时钟信号端CK1。例如，N为正整数，且N大于等于1，且小于n/2。需要说明的是，n可以为偶数，也可以为奇数，本公开对此不作限制，在图5所示的示例中，n为偶数。
例如，该栅极驱动电路1还包括第一电源线VGH0、第二电源线VGL0以及第三电源线VGL10，以分别向各级移位寄存器的第一电源端VGH、第二电源端VGL以及第三电源端VGL1提供第一电源信号VH、第二电源信号VL以及第三电源信号VL1。
需要说明的是，上述的“上一级”和“下一级”并不是指扫描时序上的上一级和下一级，而是指物理连接上的上一级和下一级。
例如，如图6所示，以第一级移位寄存器SR1和第二级移位寄存器SR2为例，触发信号端STV0向第一级移位寄存器SR1提供触发信号作为输入电压，从而控制第一级移位寄存器SR1开始工作，在第一控制信号CK0、第二控制信号CB0和第三控制信号CK10的控制下，第一级移位寄存器SR1向栅线G1输出第一输出信号V EOUT1作为扫描信号。第一级移位寄存器SR1输出的中间输出信号V GOUT1被传输至第二级移位寄存器SR2以作为第二级移位寄存器SR2的输入电压，从而控制第二级移位寄存器SR2开始工作，在第一控制信号CK0、第二控制信号CB0和第四控制信号CK20的控制下，第二级移位寄存器SR2向栅线G2输出第二输出信号V EOUT2作为扫描信号。第二级移位寄存器SR2输出的中间输出信号V GOUT2被传输至其下一级移位寄存器以作为其下一级移位寄存器的输入电压，依次类推，最终栅极驱动电路完成一帧的扫描工作。例如，该栅极驱动电路的具体工作过程可参考图3中所示的移位寄存器的工作过程。
图7本公开一实施例提供的一种显示面板的示意图。
本公开的一些实施例还提供一种显示装置，包括如图7所示的显示面板50。如图7所示，显示装置的显示面板50包括本公开任一实施例提供的栅极驱动电路1。
例如，如图7所示，本公开实施例提供的显示面板50还包括栅线2、数据线3以及由栅线2和数据线3交叉限定的多个像素单元4，栅极驱动电路1 被配置为向栅线2提供栅极驱动信号。例如，该显示面板50还可以包括数据驱动电路(图中未示出)，数据驱动电路被配置为向数据线3提供数据信号。例如，在栅极驱动电路1输出的栅极驱动信号的控制下，将数据驱动电路提供的数据信号逐行写入交叉限定的多个像素单元4中，以实现显示面板的逐行扫描。
例如，栅线2可以包括图5中所示的栅线G1、G2、G3……Gn，移位寄存器SR1、SR2、SR3……SRn中的每一级移位寄存器用于向对应的栅线G1、G2、G3……Gn输出一行栅极驱动信号。
例如，显示面板50可以为应用于手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
图8本公开一些实施例提供的一种驱动方法的流程图。
本公开一些实施例还提供一种本公开任一实施例提供的移位寄存器的驱动方法，如图8所示，该驱动方法包括如下步骤：
步骤S10：在输入电压和控制电路的控制下，将第二时钟信号端输出的第二时钟信号或第一电源端输出的第一电源信号写入中间输出端作为中间输出信号；以及
步骤S20：在中间输出信号和第三时钟信号端输出的第三时钟信号的控制下，输出与中间输出信号反相的输出信号。
本公开的实施例提供的移位寄存器的驱动方法可以实现P型薄膜晶体管输出无阈值损失的低电平信号，提升显示面板的显示质量。
需要说明的是，本公开实施例提供的驱动方法的具体操作过程可以参考上述移位寄存器的实施例中对输入阶段t1、输出阶段t2、缓冲阶段t3和稳定阶段t4的相关描述，重复之处在此不再赘述。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (22)

  1. 一种移位寄存器，包括：输入电路、控制电路、中间电路和输出电路，其中，
    所述输入电路，分别与输入电压端和第一时钟信号端电连接，被配置为在所述第一时钟信号端提供的第一时钟信号的控制下，将所述输入电压端提供的输入电压输入到所述中间电路；
    所述中间电路，分别与中间输出端、第一电源端、第二电源端、所述第一时钟信号端和第二时钟信号端电连接，且被配置为在所述输入电压和所述控制电路的控制下，将所述第二时钟信号端输出的第二时钟信号或所述第一电源端输出的第一电源信号写入所述中间输出端作为中间输出信号；
    所述输出电路，分别与所述第一电源端、所述第二电源端、第三电源端、第三时钟信号端、所述中间输出端和输出端电连接，且被配置为在所述输出端输出与所述中间输出信号反相的输出信号。
  2. 根据权利要求1所述的移位寄存器，其中，所述输出电路包括第一输出子电路、第二输出子电路和第一存储电路，
    所述第一输出子电路分别与所述第一电源端、所述中间输出端、所述输出端和第一节点电连接，且被配置为：
    在输出阶段，在所述中间输出信号的控制下，将所述第一电源信号写入所述输出端；
    所述第二输出子电路分别与所述第二电源端、所述第三电源端、所述第三时钟信号端、所述第一节点和所述输出端电连接，且被配置为：
    在输入阶段、缓冲阶段和稳定阶段，在所述第三时钟信号端输出的第三时钟信号的控制下将所述第二电源端提供的第二电源信号写入所述输出端；
    所述第一存储电路分别与所述第一节点和所述输出端电连接。
  3. 根据权利要求2所述的移位寄存器，其中，
    所述第一输出子电路包括第一晶体管和第二晶体管，所述第一晶体管的第一极与所述第一电源端电连接，所述第一晶体管的第二极与所述第一节点电连接，所述第一晶体管的栅极与所述中间输出端电连接，所述第二晶体管 的第一极与所述第一电源端电连接，所述第二晶体管的第二极与所述输出端电连接，所述第二晶体管的栅极与所述中间输出端电连接；
    所述第二输出子电路包括第三晶体管和第四晶体管，所述第三晶体管的第一极与所述第一节点电连接，所述第三晶体管的第二极与所述第三电源端电连接，所述第三晶体管的栅极与所述第三时钟信号端电连接，所述第四晶体管的第一极与所述输出端电连接，所述第四晶体管的第二极与所述第二电源端电连接，所述第四晶体管的栅极与所述第一节点电连接；
    所述第一存储电路包括第一电容，所述第一电容的第一端与所述第一节点电连接，所述第一电容的第二端与所述输出端电连接。
  4. 根据权利要求3所述的移位寄存器，其中，所述第三电源端被配置为提供第三电源信号，所述第二电源信号大于所述第三电源信号。
  5. 根据权利要求4所述的移位寄存器，其中，所述第二电源信号和所述第三电源信号之间的关系表示为：
    VL-VL1>|Vth10+Vth12|
    其中，VL表示所述第二电源信号，VL1表示所述第三电源信号，Vth10表示所述第三晶体管的阈值电压，Vth12表示所述第四晶体管的阈值电压。
  6. 根据权利要求2所述的移位寄存器，其中，所述中间电路被配置为：
    在所述输入阶段，在所述输入电压控制下，将所述第二时钟信号写入所述中间输出端作为所述中间输出信号；
    在所述输出阶段和所述缓冲阶段，将所述第二时钟信号写入所述中间输出端作为所述中间输出信号；以及
    在所述稳定阶段，在所述控制电路的控制下，将所述第一电源信号写入所述中间输出端作为所述中间输出信号。
  7. 根据权利要求6所述的移位寄存器，其中，所述中间电路包括：
    第一控制子电路，分别与第二节点、第三节点、第四节点、所述第一电源端、所述第二电源端和所述第二时钟信号端电连接，被配置为：
    在所述输入阶段，将所述输入电压写入所述第二节点；以及
    在所述稳定阶段，将所述第一电源信号写入所述第二节点；
    第二控制子电路，分别与所述第三节点、所述第四节点和所述第一时钟信号端电连接，被配置为将所述第一时钟信号写入所述第三节点；
    中间输出子电路，分别与所述第二节点、所述中间输出端和所述第二时钟信号端电连接，被配置为：
    在所述输入阶段、所述输出阶段和所述缓冲阶段，将所述第二时钟信号写入所述中间输出端作为所述中间输出信号。
  8. 根据权利要求7所述的移位寄存器，其中，所述第一控制子电路包括第五晶体管、第六晶体管和第七晶体管，
    所述第五晶体管的第一极与所述第一电源端电连接，所述第五晶体管的第二极与所述第六晶体管的第一极电连接，所述第五晶体管的栅极与所述第三节点电连接；
    所述第六晶体管的第二极与所述第四节点电连接，所述第六晶体管的栅极与所述第二时钟信号端电连接；
    所述第七晶体管的第一极与所述第四节点电连接，所述第七晶体管的第二极与所述第二节点电连接，所述第七晶体管的栅极与所述第二电源端电连接。
  9. 根据权利要求7所述的移位寄存器，其中，所述第二控制子电路包括第八晶体管，
    所述第八晶体管的第一极与所述第三节点电连接，所述第八晶体管的第二极与所述第一时钟信号端电连接，所述第八晶体管的栅极与所述第四节点电连接。
  10. 根据权利要求7所述的移位寄存器，其中，所述中间输出子电路包括第九晶体管，
    所述第九晶体管的第一极与所述第二时钟信号端电连接，所述第九晶体管的第二极与所述中间输出端电连接，所述第九晶体管的栅极与所述第二节点电连接。
  11. 根据权利要求7所述的移位寄存器，其中，所述中间电路还包括：第二存储子电路，
    所述第二存储子电路包括第二电容，所述第二电容的第一端与所述第二节点电连接，所述第二电容的第二端与所述中间输出端电连接。
  12. 根据权利要求7所述的移位寄存器，其中，所述中间电路还包括：
    中间输出控制子电路，分别与所述第三节点、所述中间输出端和所述第 一电源端电连接，被配置为：在所述稳定阶段，在所述控制电路的控制下，将所述第一电源信号写入所述中间输出端；以及
    第三存储子电路，分别与所述第三节点和所述第一电源端电连接。
  13. 根据权利要求12所述的移位寄存器，其中，所述中间输出控制子电路包括第十晶体管，所述第三存储子电路包括第三电容，
    所述第十晶体管的第一极与所述第一电源端电连接，所述第十晶体管的第二极与所述中间输出端电连接，所述第十晶体管的栅极与所述第三节点电连接；
    所述第三电容的第一端与所述第三节点电连接，所述第三电容的第二端与所述第一电源端电连接。
  14. 根据权利要求12所述的移位寄存器，其中，所述第二时钟信号的高电平与所述第一电源信号的电平相同，所述第二时钟信号的低电平与所述第二电源信号的电平相同。
  15. 根据权利要求7所述的移位寄存器，其中，所述控制电路包括第十一晶体管，
    所述第十一晶体管的第一极与所述第二电源端电连接，所述第十一晶体管的第二极与所述第三节点电连接，所述第十一晶体管的栅极与所述第一时钟信号端电连接。
  16. 根据权利要求1所述的移位寄存器，其中，所述第三时钟信号端输出的时钟信号的高电平与所述第一电源信号的电平相同，所述第三时钟信号端输出的时钟信号的低电平与所述第三电源信号的电平相同。
  17. 根据权利要求1所述的移位寄存器，其中，所述输入电路包括第十二晶体管，所述第十二晶体管的第一极与所述输入电压端电连接，所述第十二晶体管的第二极与所述第四节点电连接，所述第十二晶体管的栅极与所述第一时钟信号端电连接。
  18. 一种栅极驱动电路，包括如权利要求1-17任一项所述的移位寄存器。
  19. 根据权利要求18所述的栅极驱动电路，包括级联的多个如权利要求1-17任一项所述的移位寄存器，
    其中，除第一级移位寄存器之外，本级移位寄存器的输入电压端与上一级移位寄存器的中间输出端电连接。
  20. 根据权利要求19所述的栅极驱动电路，还包括信号生成电路，
    其中，所述信号生成电路被配置为生成第一控制信号、第二控制信号、第三控制信号和第四控制信号，
    所述第一控制信号被施加至第2N-1级移位寄存器的所述第一时钟信号端和第2N级移位寄存器的所述第二时钟信号端；
    所述第二控制信号被施加至所述第2N-1级移位寄存器的所述第二时钟信号端和所述第2N级移位寄存器的所述第一时钟信号端；
    所述第三控制信号被施加至所述第2N-1级移位寄存器的所述第三时钟信号端；
    所述第四控制信号被施加至所述第2N级移位寄存器的所述第三时钟信号端；
    其中，N为正整数，且N大于等于1。
  21. 一种显示装置，包括如权利要求18-20任一所述的栅极驱动电路。
  22. 一种如权利要求1-17任一所述的移位寄存器的驱动方法，包括：
    在所述输入电压和所述控制电路的控制下，将所述第二时钟信号端输出的所述第二时钟信号或所述第一电源端输出的所述第一电源信号写入所述中间输出端作为所述中间输出信号；
    在所述中间输出信号和所述第三时钟信号端输出的所述第三时钟信号的控制下，在所述输出端输出与所述中间输出信号反相的输出信号。
PCT/CN2019/087835 2018-06-28 2019-05-21 移位寄存器及驱动方法、栅极驱动电路和显示装置 Ceased WO2020001200A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2019564138A JP7267935B2 (ja) 2018-06-28 2019-05-21 シフトレジスターおよび駆動方法、ゲート駆動回路および表示装置
US16/613,125 US11581051B2 (en) 2018-06-28 2019-05-21 Shift register and driving method thereof, gate drive circuit, and display device
KR1020197035458A KR102275425B1 (ko) 2018-06-28 2019-05-21 시프트 레지스터 및 그 구동 방법, 게이트 구동 회로, 및 디스플레이 디바이스
EP19824634.0A EP3816984B1 (en) 2018-06-28 2019-05-21 Shift register and driving method, gate driving circuit and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810691092.0A CN110660362B (zh) 2018-06-28 2018-06-28 移位寄存器及栅极驱动电路
CN201810691092.0 2018-06-28

Publications (1)

Publication Number Publication Date
WO2020001200A1 true WO2020001200A1 (zh) 2020-01-02

Family

ID=68985477

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/087835 Ceased WO2020001200A1 (zh) 2018-06-28 2019-05-21 移位寄存器及驱动方法、栅极驱动电路和显示装置

Country Status (6)

Country Link
US (1) US11581051B2 (zh)
EP (1) EP3816984B1 (zh)
JP (1) JP7267935B2 (zh)
KR (1) KR102275425B1 (zh)
CN (1) CN110660362B (zh)
WO (1) WO2020001200A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4120229A4 (en) * 2021-03-09 2023-06-28 BOE Technology Group Co., Ltd. Shift register, drive circuit and display substrate

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111312177B (zh) * 2020-03-03 2021-04-02 武汉华星光电技术有限公司 Goa驱动电路、显示面板及显示装置
US11875749B2 (en) * 2020-04-10 2024-01-16 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate and manufacturing method thereof, display device
CN116564231B (zh) 2020-04-10 2025-07-25 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN113785352B (zh) 2020-04-10 2023-04-11 京东方科技集团股份有限公司 显示基板及其制作方法、显示装置
CN111415624B (zh) * 2020-04-29 2021-05-14 京东方科技集团股份有限公司 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置
JP7648544B2 (ja) * 2020-04-30 2025-03-18 京東方科技集團股▲ふん▼有限公司 表示基板及びその製造方法、表示装置
CN111739473B (zh) * 2020-07-24 2021-12-03 京东方科技集团股份有限公司 Goa单元及其驱动方法、goa驱动电路、显示装置
WO2022133800A1 (zh) * 2020-12-23 2022-06-30 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动器、显示装置
CN112687230B (zh) * 2021-01-29 2022-06-10 云谷（固安）科技有限公司 移位寄存器、栅极驱动电路和显示面板
CN113284457A (zh) * 2021-05-19 2021-08-20 厦门天马微电子有限公司 移位寄存器及其驱动方法、显示面板
CN115812231B (zh) * 2021-05-24 2025-04-11 京东方科技集团股份有限公司 移位寄存器及其驱动方法、扫描驱动电路、显示装置
CN113380172B (zh) * 2021-06-07 2022-12-06 中国科学院微电子研究所 一种栅极驱动电路、驱动方法及goa电路
CN113362768B (zh) * 2021-06-29 2023-02-28 京东方科技集团股份有限公司 显示装置、栅极驱动电路、移位寄存单元及其驱动方法
CN115602124B (zh) * 2021-07-08 2025-08-15 乐金显示有限公司 选通驱动器及包括其的显示面板
WO2023019561A1 (zh) * 2021-08-20 2023-02-23 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN117501368A (zh) * 2022-05-27 2024-02-02 京东方科技集团股份有限公司 移位寄存器及其驱动方法、显示基板和显示装置
CN118899012B (zh) * 2023-04-28 2025-09-19 长鑫存储技术有限公司 一种控制电路和存储器
CN116994516B (zh) * 2023-07-28 2024-01-30 上海和辉光电股份有限公司 栅极驱动电路以及显示面板
KR20250099422A (ko) * 2023-10-08 2025-07-01 우한 차이나 스타 옵토일렉트로닉스 세미컨덕터 디스플레이 테크놀로지 컴퍼니 리미티드 게이트 구동 회로 및 이를 포함하는 디스플레이 패널
WO2025260347A1 (zh) * 2024-06-21 2025-12-26 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
WO2026065271A1 (zh) * 2024-09-29 2026-04-02 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN119495248A (zh) * 2024-12-18 2025-02-21 广州华星光电半导体显示技术有限公司 栅极驱动电路及显示面板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202434192U (zh) * 2012-01-06 2012-09-12 京东方科技集团股份有限公司 移位寄存器和阵列基板栅极驱动电路
CN104064158A (zh) * 2014-07-17 2014-09-24 深圳市华星光电技术有限公司 具有自我补偿功能的栅极驱动电路
US20150179128A1 (en) * 2013-04-28 2015-06-25 Hefei Boe Optoelectronics Technology Co., Ltd. Gate driver and display apparatus
US20160358569A1 (en) * 2015-06-02 2016-12-08 Boe Technology Group Co., Ltd. Voltage output device, gate driving circuit and display apparatus
CN107464539A (zh) * 2017-09-21 2017-12-12 京东方科技集团股份有限公司 移位寄存器单元、驱动装置、显示装置以及驱动方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101778701B1 (ko) * 2010-08-11 2017-09-15 삼성디스플레이 주식회사 구동 장치 및 이를 포함하는 표시 장치
TWI621243B (zh) * 2011-08-29 2018-04-11 半導體能源研究所股份有限公司 半導體裝置
US9443608B2 (en) * 2012-04-25 2016-09-13 Joled Inc. Shift register having multiple output units connected in cascade as display device scan line driving circuit
JP6521794B2 (ja) * 2014-09-03 2019-05-29 株式会社半導体エネルギー研究所 半導体装置、及び電子機器
CN104318904B (zh) * 2014-11-20 2017-08-01 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、移位寄存器、显示装置
CN204257215U (zh) * 2014-12-18 2015-04-08 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示装置
CN104883181B (zh) * 2015-06-10 2018-03-16 京东方科技集团股份有限公司 或非门电路、移位寄存器、阵列基板及显示装置
CN104900192B (zh) * 2015-07-01 2017-10-10 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路、显示装置
CN105243984B (zh) * 2015-11-25 2018-03-27 上海天马有机发光显示技术有限公司 移位寄存单元、移位寄存器及移位寄存器的驱动方法
CN107103870A (zh) * 2017-06-27 2017-08-29 上海天马有机发光显示技术有限公司 移位寄存单元、其驱动方法及显示面板
CN107301834B (zh) * 2017-08-25 2020-11-03 京东方科技集团股份有限公司 一种逻辑单元电路和像素驱动电路
CN107863057B (zh) * 2017-10-31 2020-12-18 上海天马微电子有限公司 一种移位寄存器、其驱动方法、驱动控制电路及相关装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN202434192U (zh) * 2012-01-06 2012-09-12 京东方科技集团股份有限公司 移位寄存器和阵列基板栅极驱动电路
US20150179128A1 (en) * 2013-04-28 2015-06-25 Hefei Boe Optoelectronics Technology Co., Ltd. Gate driver and display apparatus
CN104064158A (zh) * 2014-07-17 2014-09-24 深圳市华星光电技术有限公司 具有自我补偿功能的栅极驱动电路
US20160358569A1 (en) * 2015-06-02 2016-12-08 Boe Technology Group Co., Ltd. Voltage output device, gate driving circuit and display apparatus
CN107464539A (zh) * 2017-09-21 2017-12-12 京东方科技集团股份有限公司 移位寄存器单元、驱动装置、显示装置以及驱动方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3816984A4

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4120229A4 (en) * 2021-03-09 2023-06-28 BOE Technology Group Co., Ltd. Shift register, drive circuit and display substrate
US11967278B2 (en) 2021-03-09 2024-04-23 Chengdu Boe Optoelectronics Technology Co., Ltd. Shift register, driving circuit and display substrate
US12293719B2 (en) 2021-03-09 2025-05-06 Chengdu Boe Optoelectronics Technology Co., Ltd. Shift register, driving circuit and display substrate

Also Published As

Publication number Publication date
EP3816984A4 (en) 2022-03-16
EP3816984B1 (en) 2024-10-02
US11581051B2 (en) 2023-02-14
JP7267935B2 (ja) 2023-05-02
EP3816984A1 (en) 2021-05-05
CN110660362A (zh) 2020-01-07
KR20200003125A (ko) 2020-01-08
CN110660362B (zh) 2021-01-22
JP2021529410A (ja) 2021-10-28
KR102275425B1 (ko) 2021-07-09
US20210358367A1 (en) 2021-11-18

Similar Documents

Publication Publication Date Title
CN110660362B (zh) 移位寄存器及栅极驱动电路
CN110176217B (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN110264948B (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN113299223B (zh) 一种显示面板和显示装置
WO2018205543A1 (zh) 移位寄存器、其驱动方法、栅极集成驱动电路及显示装置
WO2018161528A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
WO2018161611A1 (zh) 移位寄存器电路及其驱动方法、栅极驱动电路、显示装置
CN115997249B (zh) 移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN107516505B (zh) 移位寄存器单元及其驱动方法、栅极驱动电路和显示面板
US11393402B2 (en) OR logic operation circuit and driving method, shift register unit, gate drive circuit, and display device
CN106228927A (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN109166542B (zh) 移位寄存器单元及驱动方法、栅极驱动电路、显示装置
CN108320708A (zh) 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2020052343A1 (zh) 移位寄存器单元及其驱动方法、栅极驱动电路和显示设备
CN107452351A (zh) 一种移位寄存器、其驱动方法、驱动控制电路及显示装置
US10403210B2 (en) Shift register and driving method, driving circuit, array substrate and display device
CN105243984A (zh) 移位寄存单元、移位寄存器及移位寄存器的驱动方法
CN107093414A (zh) 一种移位寄存器、其驱动方法、栅极驱动电路及显示装置
CN108288451A (zh) 移位寄存器单元、驱动方法、栅极驱动电路及显示装置
CN109584780B (zh) 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2017185822A1 (zh) 移位寄存器、栅极驱动电路、阵列基板
CN106683617A (zh) 移位寄存器单元、阵列基板和显示装置
CN106991958B (zh) 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN109377948B (zh) 移位寄存器及其驱动方法、栅极驱动电路和显示装置
CN105913826B (zh) 移位寄存器单元及驱动方法、移位寄存器电路及显示装置

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2019564138

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 201947047344

Country of ref document: IN

ENP Entry into the national phase

Ref document number: 20197035458

Country of ref document: KR

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19824634

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2019824634

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2019824634

Country of ref document: EP

Effective date: 20210128

WWG Wipo information: grant in national office

Ref document number: 201947047344

Country of ref document: IN