WO2020001635A1 - 驱动电路及其驱动方法、显示装置 - Google Patents

驱动电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2020001635A1
WO2020001635A1 PCT/CN2019/093785 CN2019093785W WO2020001635A1 WO 2020001635 A1 WO2020001635 A1 WO 2020001635A1 CN 2019093785 W CN2019093785 W CN 2019093785W WO 2020001635 A1 WO2020001635 A1 WO 2020001635A1
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Prior art keywords
circuit
driving
transistor
sub
signal terminal
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/093785
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English (en)
French (fr)
Inventor
玄明花
陈小川
岳晗
丛宁
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to KR1020207013570A priority Critical patent/KR20200057785A/ko
Priority to JP2020528056A priority patent/JP7672820B2/ja
Priority to EP19826767.6A priority patent/EP3816978A4/en
Priority to US16/620,683 priority patent/US11270630B2/en
Priority to KR1020217035455A priority patent/KR20210134833A/ko
Publication of WO2020001635A1 publication Critical patent/WO2020001635A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0626—Adjustment of display parameters for control of overall brightness

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a driving circuit, a driving method thereof, and a display device.
  • micro light-emitting diode display devices Compared with OLED (Organic Light Emitting Diode) display devices, micro light-emitting diode display devices (for example, MicroLED display devices or ⁇ LED display devices) have the advantages of low driving voltage, long life, wide temperature resistance, etc., and Gradually applied to the field of mobile terminals.
  • OLED Organic Light Emitting Diode
  • the present disclosure provides a driving circuit including a driving device for driving an element to be driven to work;
  • the driving device and the element to be driven are connected in series between a first working voltage terminal and a second working voltage terminal; the driving device is configured to provide a driving signal to the element to be driven and control the first working voltage The conducting time of the signal path between the terminal and the second working voltage terminal;
  • the driving device includes a driving sub-circuit, a writing sub-circuit, and a gray-level control sub-circuit;
  • the writing sub-circuit is connected to a first scanning signal terminal, a first data signal terminal, and the driving sub-circuit; the writing sub-circuit is configured to control the first data under the control of the first scanning signal terminal. Writing a first data voltage provided by a signal terminal into the driving sub-circuit;
  • the gray-scale control sub-circuit is connected to a driving control signal terminal, a second scanning signal terminal, a second data signal terminal, and the driving sub-circuit;
  • the gray-scale control sub-circuit is configured to transmit a first working voltage provided by the first working voltage terminal to the driving sub-circuit under the control of the driving control signal terminal;
  • the driving sub-circuit is configured to generate the driving signal according to the first data voltage and the first operating voltage
  • the gray-scale control sub-circuit is further configured to control the on-time of the current path under the control of the driving control signal terminal, the second scanning signal terminal, and the second data signal terminal.
  • the gray-scale control sub-circuit includes a first control sub-circuit and a second control sub-circuit;
  • the first control sub-circuit is connected to the driving control signal terminal, the driving sub-circuit, and the second control sub-circuit; the first control sub-circuit is used to control all the signals under the control of the driving control signal terminal.
  • the first working voltage provided by the first working voltage terminal is transmitted to the driving sub-circuit;
  • the first control sub-circuit is further configured to transmit the driving current generated by the driving sub-circuit to the second control sub-circuit under the control of the driving control signal terminal, and control the on-time of the current path. ;
  • the second control sub-circuit is further connected to the second scan signal terminal and the second data signal terminal; the second control sub-circuit is configured to connect the second scan signal terminal and the second data signal terminal. Under control, the on-time of the current path is controlled.
  • the driving circuit further includes a compensation sub-circuit
  • the compensation sub-circuit is connected to the first scanning signal terminal and the driving sub-circuit; the compensation sub-circuit is configured to compensate the threshold voltage of the driving sub-circuit under the control of the first scanning signal terminal.
  • the driving circuit further includes a reset sub-circuit
  • the reset sub-circuit is connected to a reset voltage terminal, a reset control signal terminal, and the driving sub-circuit; the reset sub-circuit is used to transmit the reset voltage provided by the reset voltage terminal to the reset voltage terminal under the control of the reset control signal terminal.
  • the driving sub-circuit is connected to a reset voltage terminal, a reset control signal terminal, and the driving sub-circuit; the reset sub-circuit is used to transmit the reset voltage provided by the reset voltage terminal to the reset voltage terminal under the control of the reset control signal terminal.
  • the first control sub-circuit includes a first transistor and a second transistor
  • An anode of the element to be driven is connected to the second control sub-circuit, a cathode of the element to be driven is connected to the second operating voltage terminal; a gate of the first transistor is connected to the driving control signal terminal, Pole connected to the first working voltage terminal, and a second pole connected to the driving sub-circuit;
  • a gate of the second transistor is connected to the driving control signal terminal, a first pole is connected to the driving sub-circuit, and a second pole is connected to the second control sub-circuit.
  • the first control sub-circuit includes a first transistor and a second transistor
  • An anode of the element to be driven is connected to the first operating voltage terminal; a gate of the first transistor is connected to the driving control signal terminal, a first pole is connected to a cathode of the element to be driven, and a second pole is connected to the Driving sub-circuit
  • a gate of the second transistor is connected to the driving control signal terminal, a first pole is connected to the driving sub-circuit, and a second pole is connected to the second control sub-circuit.
  • the second control sub-circuit is further connected to a first voltage terminal;
  • the second control sub-circuit includes a third transistor, a fourth transistor, and a first capacitor;
  • a gate of the third transistor is connected to the second scan signal terminal, a first electrode is connected to the second data signal terminal, and a second electrode is connected to the gate of the fourth transistor;
  • One end of the first capacitor is connected to a second pole of the third transistor, and the other end of the first capacitor is connected to the first voltage terminal;
  • the cathode of the element to be driven is connected to the second working voltage terminal; the first pole of the fourth transistor is connected to the first control sub-circuit, and the second pole is connected to the anode of the element to be driven.
  • the second control sub-circuit is further connected to a first voltage terminal;
  • the second control sub-circuit includes a third transistor, a fourth transistor, and a first capacitor;
  • a gate of the third transistor is connected to the second scan signal terminal, a first electrode is connected to the second data signal terminal, and a second electrode is connected to the gate of the fourth transistor;
  • One end of the first capacitor is connected to a second pole of the third transistor, and the other end of the first capacitor is connected to the first voltage terminal;
  • An anode of the element to be driven is connected to the first operating voltage terminal, a cathode of the element to be driven is connected to the first control sub-circuit; a first pole of the fourth transistor is connected to the first control sub-circuit, The second electrode is connected to the second working voltage terminal.
  • the driving sub-circuit is further connected to a second voltage terminal, and the driving sub-circuit includes a driving transistor;
  • a gate of the driving transistor is connected to the second voltage terminal, a first electrode is connected to the writing sub-circuit, and a second electrode is connected to the gray-scale control sub-circuit.
  • the driving sub-circuit is further connected to a second voltage terminal, and the driving sub-circuit includes a driving transistor and a second capacitor;
  • a gate of the driving transistor is connected to one end of the second capacitor, a first electrode is connected to the writing sub-circuit, and a second electrode is connected to the gray-scale control sub-circuit;
  • the other end of the second capacitor is connected to the second voltage terminal.
  • the writing sub-circuit includes a fifth transistor
  • a gate of the fifth transistor is connected to the first scan signal terminal, a first pole is connected to the first data signal terminal, and a second pole is connected to the driving sub-circuit.
  • the compensation sub-circuit includes a sixth transistor
  • a gate of the sixth transistor is connected to the first scan signal terminal, and a first electrode and a second electrode are connected to the driving sub-circuit.
  • the reset sub-circuit includes a seventh transistor
  • a gate of the seventh transistor is connected to the reset control signal terminal, a first pole is connected to the reset voltage terminal, and a second pole is connected to the driving sub-circuit.
  • the element to be driven is a micro light emitting diode.
  • the present disclosure provides a driving circuit for driving an element to be driven.
  • the driving circuit includes first to seventh transistors, a first capacitor, a second capacitor, a driving transistor, a reset control signal terminal, and a driving circuit.
  • the drive control signal terminal is connected to a gate of the first transistor and a gate of the second transistor,
  • the first data signal terminal is connected to a first pole of the fifth transistor
  • the second data signal terminal is connected to a first pole of the third transistor
  • the first scan signal terminal is connected to the gate of the fifth transistor and the gate of the sixth transistor,
  • the second scan signal terminal is connected to the gate of the third transistor
  • the first working voltage terminal is connected to a first pole of the first transistor
  • the first voltage terminal is connected to one end of the first capacitor
  • the second voltage terminal is connected to one end of the second capacitor
  • the reset control signal terminal is connected to the gate of the seventh transistor
  • the reset voltage terminal is connected to a first electrode of the seventh transistor
  • the second pole of the first transistor and the second pole of the fifth transistor are connected to the first pole of the driving transistor
  • the other end of the second capacitor, the second pole of the sixth transistor, and the second pole of the seventh transistor are connected to the gate of the driving transistor
  • a first pole of the second transistor and a first pole of the sixth transistor are connected to a second pole of the driving transistor
  • a second pole of the second transistor is connected to a first pole of the fourth transistor
  • the other end of the first capacitor and the second electrode of the third transistor are connected to the gate of the fourth transistor
  • the second pole of the fourth transistor is connected to the element to be driven.
  • the present disclosure provides a driving circuit for driving an element to be driven.
  • the driving circuit includes first to seventh transistors, a first capacitor, a second capacitor, a driving transistor, a reset control signal terminal, and a driving circuit.
  • the drive control signal terminal is connected to a gate of the first transistor and a gate of the second transistor,
  • the first data signal terminal is connected to a first pole of the fifth transistor
  • the second data signal terminal is connected to a first pole of the third transistor
  • the first scan signal terminal is connected to the gate of the fifth transistor and the gate of the sixth transistor,
  • the second scan signal terminal is connected to the gate of the third transistor
  • the power voltage terminal is connected to the second electrode of the fourth transistor
  • the first voltage terminal is connected to one end of the first capacitor
  • the second voltage terminal is connected to one end of the second capacitor
  • the reset control signal terminal is connected to the gate of the seventh transistor
  • the reset voltage terminal is connected to a first electrode of the seventh transistor
  • the second pole of the first transistor and the second pole of the fifth transistor are connected to the first pole of the driving transistor
  • the other end of the second capacitor, the second pole of the sixth transistor, and the second pole of the seventh transistor are connected to the gate of the driving transistor
  • a first pole of the second transistor and a first pole of the sixth transistor are connected to a second pole of the driving transistor
  • a second pole of the second transistor is connected to a first pole of the fourth transistor
  • the other end of the first capacitor and the second electrode of the third transistor are connected to the gate of the fourth transistor
  • a first pole of the first transistor is connected to the element to be driven.
  • the present disclosure provides a display device including a substrate.
  • a display area of the display substrate has a plurality of sub-pixels, and at least one of the sub-pixels is provided with a driving circuit and an element to be driven according to an embodiment of the present disclosure.
  • the driving circuit is configured to provide a driving signal to the element to be driven.
  • the present disclosure provides a driving method for a driving circuit according to an embodiment of the present disclosure, wherein, within an image frame, the driving circuit has a plurality of scanning cycles; the grayscale control sub-circuit includes a first A control sub-circuit and a second control sub-circuit; in one of the scan periods, the method for driving the driving circuit includes:
  • a driving control signal is provided to the driving control signal terminal, and a first operating voltage is provided to the first operating voltage terminal, and the first operating voltage is transmitted to the driving subcircuit through the first control subcircuit, so that the element to be driven is in the
  • the driving control signal, the first scan signal, the second scan signal, and the second data voltage are controlled to operate based on the first data voltage and the first operating voltage.
  • the method further includes:
  • the time when the second scanning signal terminal outputs a valid signal is later than the time when the first scanning signal terminal outputs a valid signal.
  • the driving circuit further includes a reset sub-circuit, the first scanning signal is provided to the first scanning signal terminal, and the first data voltage is provided to the first data signal terminal, and the first data voltage passes Before the writing sub-circuit is written to the driving sub-circuit, the method for driving the driving circuit further includes:
  • a reset control signal is provided to a reset control signal terminal, and a reset voltage is provided to a reset voltage terminal, and the reset voltage is transmitted to the driving subcircuit through the reset subcircuit.
  • the driving sub-circuit includes a driving transistor and a second capacitor; a gate of the driving transistor is connected to one end of the second capacitor, and the other end of the second capacitor is connected to a second voltage terminal, The voltage input from the second voltage terminal is the same as the voltage input from the first working voltage terminal.
  • FIG. 1 is a schematic structural diagram of a driving circuit provided by some embodiments of the present disclosure
  • FIG. 2 is a schematic structural diagram of another driving circuit provided by some embodiments of the present disclosure.
  • FIG. 3 is a schematic diagram of a specific structure of the driving circuit shown in FIG. 1;
  • FIG. 4 is a schematic diagram of a specific structure of the driving circuit shown in FIG. 2;
  • FIG. 5 is a detailed structural diagram of each sub-circuit in the driving circuit shown in FIG. 3;
  • FIG. 5 is a detailed structural diagram of each sub-circuit in the driving circuit shown in FIG. 3;
  • FIG. 6 is a specific structural diagram of each sub-circuit in the driving circuit shown in FIG. 4; FIG.
  • FIG. 7 is a schematic structural diagram of another driving circuit provided by some embodiments of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another driving circuit provided by some embodiments of the present disclosure.
  • FIG. 9 is a timing signal diagram provided by some embodiments of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a display panel provided by some embodiments of the present disclosure.
  • FIG. 11 is a flowchart of a driving method of a driving circuit provided by some embodiments of the present disclosure.
  • FIG. 12 is another timing signal diagram provided by some embodiments of the present disclosure.
  • FIG. 13 is a detailed structural diagram of each sub-circuit in a driving circuit according to another embodiment.
  • FIG. 14 is a detailed structural diagram of each sub-circuit in a driving circuit according to another embodiment.
  • the driving circuit 01 includes a driving device 100 and an element L to be driven.
  • the driving device 100 and the element to be driven L are connected in series between the first working voltage terminal VL1 and the second working voltage terminal VL2.
  • the driving device 100 is connected between the first operating voltage terminal VL1 and the anode of the element to be driven L, and the cathode of the to-be-driven element L is connected to the second operating voltage terminal VL2.
  • the driving device 100 is connected between the second operating voltage terminal VL2 and the cathode of the element to be driven L, and the anode of the to-be-driven element L is connected to the first operating voltage terminal VL1.
  • the element to be driven L may be a light emitting device, such as a micro light emitting diode, such as a ⁇ LED or a MicroLED.
  • the size level of a ⁇ LED or MicroLED is a micrometer ( ⁇ m) level.
  • the embodiment of the present disclosure is described using the element to be driven L as a light emitting device and the driving circuit 01 as a driving circuit as an example. It can be understood that the element to be driven L may be other flow-control electronic components.
  • the driving device 100 is configured to provide a driving current I and control a conduction time of a current path between the first working voltage terminal VL1 and the second working voltage terminal VL2.
  • the first working voltage VDD output from the first working voltage terminal VL1 and the second working voltage VSS output from the second working voltage terminal VL2 can provide a potential difference to the current path, so that the driving current I can be transmitted along the current path.
  • the driving current I can be transmitted along the current path.
  • first operating voltage VDD may be a constant high level
  • second operating voltage VSS may be a constant low level
  • the light emitting device L is used to receive a driving current I in a current path and emit light.
  • the driving device 100 includes a driving sub-circuit 10, a writing sub-circuit 20, and a gray-level control sub-circuit 30.
  • the writing sub-circuit 20 is connected to the first scanning signal terminal G_A, the first data signal terminal D_A, and the driving sub-circuit 10.
  • the writing sub-circuit 20 is used to write the first data voltage Vdata_A provided by the first data signal terminal D_A to the driving sub-circuit 10 under the control of the first scanning signal terminal G_A.
  • the gray-scale control sub-circuit 30 is connected to the light-emitting control signal terminal EM (as a driving control signal terminal), the second scanning signal terminal G_B, the second data signal terminal D_B, and the driving sub-circuit 10.
  • the gray-scale control sub-circuit 30 in the driving circuit 01 may be directly connected to the first working voltage terminal VL1, and connected to the Two working voltage terminals VL2 are connected.
  • the grayscale control sub-circuit 30 in the driving circuit 01 may be connected to the first working voltage terminal VL1 through the light emitting device L. And directly connected to the second working voltage terminal VL2.
  • the gray-scale control sub-circuit 30 is configured to transmit the first operating voltage VDD provided by the first operating voltage terminal VL1 to the driver under the control of the light-emitting control signal terminal EM. Circuit 10.
  • the driving sub-circuit 10 is configured to generate a driving current I according to the first data voltage Vdata_A and the first operating voltage VDD.
  • the gray-level control sub-circuit 30 is further configured to control the on-time of the current path under the control of the light-emitting control signal terminal EM, the second scan signal terminal G_B, and the second data signal terminal D_B.
  • the writing sub-circuit 20 can output the first data voltage Vdata_A related to the display gray scale to the driving sub-circuit 10 so that the driving sub-circuit 10 can generate a driving current I for driving the light-emitting device L to emit light.
  • the gray-scale control sub-circuit 30 can control the conduction time of the current path formed during the driving current I flows into the light-emitting device L, thereby controlling the light-emitting time of the light-emitting device L.
  • the effective light emission of the light-emitting device L can be controlled by the size of the first data voltage Vdata_A and the gray-scale control sub-circuit 30 in one scanning cycle Brightness, to achieve the purpose of adjusting the display gray scale.
  • each of the driving circuits 01 is provided with a grayscale control sub-circuit 30, and for each driving circuit corresponding to a sub-pixel in the same row, each grayscale control sub-circuit 30 included is connected To different data signal lines (that is, controlled by the second data voltage Vdata_B which is independent from each other), therefore, the driving circuit 01 provided in the embodiment of the present application can directly respond to the light emitting device L (such as ⁇ LED) in the driving circuit 01. Brightness is controlled individually. Also.
  • the driving circuit 01 provided in the embodiment of the present application may be fabricated on a glass substrate or a transparent resin substrate in a display panel of a display device through a patterning process. When the light emitting device is a ⁇ LED, an implementation manner of a ⁇ LED display device with low cost, simple manufacturing process, and mass production can be provided.
  • the gray-scale control sub-circuit 30, as shown in FIG. 5, may include a first control sub-circuit 301 and a second control sub-circuit 302.
  • a first control sub-circuit 301 is connected to a light-emitting control signal terminal EM, a driving sub-circuit 10 and a second control sub-circuit 302.
  • the first control sub-circuit 301 is used to transmit the first working voltage VDD provided by the first working voltage terminal VL1 to the driving sub-circuit 10 under the control of the light-emitting control signal terminal EM.
  • the first control sub-circuit 301 is further configured to transmit the driving current I generated by the driving sub-circuit 10 to the second control sub-circuit 302 under the control of the light-emitting control signal terminal EM, and control the on-time of the current path.
  • the second control sub-circuit 302 is also connected to a second scan signal terminal G_B and a second data signal terminal D_B.
  • the second control sub-circuit 302 is used for controlling whether the current path is conducted in one scanning period and controlling the total of the current path in multiple scanning periods under the control of the second scanning signal end G_B and the second data signal end D_B. On time.
  • the current path can be conducted only when the first control sub-circuit 301 and the second control sub-circuit 302 are both on, and the driving current I generated by the driving sub-circuit 10 can be output to the light-emitting device through the current path. L.
  • the effective light-emitting brightness of the light-emitting device L can be controlled by the cooperative control of the driving current I, the first control sub-circuit 301, and the second control sub-circuit 302, and the factors affecting the effective light-emitting brightness of the light-emitting device L are increased, so that the The grayscale values that the sub-pixels of the driving circuit 01 can display are more diverse.
  • the first control sub-circuit 301 may include a first transistor T1 and a second transistor T2.
  • FIG. 5 uses the structure shown in FIG. 3 as an example to describe the structure of each sub-circuit in FIG. 3.
  • the cathode of the light emitting device L is connected to the second operating voltage terminal VL2.
  • the gate of the first transistor T1 is connected to the light emission control signal terminal EM, the first pole is connected to the first operating voltage terminal VL1, and the second pole is connected to the driving sub-circuit 10.
  • the gate of the second transistor T2 is connected to the light emission control signal terminal EM, the first pole is connected to the driving sub-circuit 10, and the second pole is connected to the second control sub-circuit 302.
  • the second control sub-circuit 302 is also connected to the first voltage terminal V1.
  • the first voltage terminal V1 may be a ground terminal GND.
  • the second control sub-circuit 302 includes a third transistor T3, a fourth transistor T4, and a first capacitor C1.
  • the gate of the third transistor T3 is connected to the second scan signal terminal G_B, the first electrode is connected to the second data signal terminal D_B, and the second electrode is connected to the gate of the fourth transistor T4.
  • One end of the first capacitor C1 is connected to the second electrode of the third transistor T3, and the other end of the first capacitor C1 is connected to the first voltage terminal V1.
  • the first electrode of the fourth transistor T4 is connected to the first control sub-circuit. 301.
  • the second electrode is connected to the anode of the light emitting device L.
  • the first pole of the fourth transistor T4 is connected to the second pole of the second transistor T2.
  • the structure shown in FIG. 4 is taken as an example to describe the structure of each sub-circuit in FIG. 4.
  • FIG. 6 is a schematic structural diagram of each sub-circuit in FIG. 4. Referring to FIG. 6, it is similar to the structure of each sub-circuit in FIG. . Specifically, referring to FIG. 4 and FIG. 6, the anode of the light emitting device L is connected to the first working voltage terminal VL1; the cathode of the light emitting device L is connected to the first electrode of the first transistor T1. A first pole of the fourth transistor T4 is connected to the first control sub-circuit 301, and a second pole is connected to the second working voltage terminal VL2.
  • the driving sub-circuit 10 includes a driving transistor Td and a second capacitor C2.
  • the gate of the driving transistor Td is connected to one end of the second capacitor C2 and the other end of the second capacitor C2 is connected.
  • the second voltage terminal V2 may be the same as the first voltage terminal V1 and both are ground terminals GND.
  • the second voltage terminal V2 since the second voltage terminal V2 is closer to the first working voltage terminal VL1, in order to make the circuit layout design easier, the second voltage terminal V2 may be connected to the first working voltage terminal VL1 to receive the first A first operating voltage VDD output from an operating voltage terminal VL1.
  • the gate of the driving transistor Td is connected to one end of the second capacitor C2, the first electrode is connected to the write sub-circuit 20, and the second electrode is connected to the gray-scale control sub-circuit 30.
  • the second pole of the driving transistor Td is connected to the first pole of the second transistor T2.
  • the write sub-circuit 20 includes a fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the first scan signal terminal G_A, the first electrode is connected to the first data signal terminal D_A, and the second electrode is connected to the driving sub-circuit 10.
  • the second pole of the fifth transistor T5 is connected to the first pole of the driving transistor Td.
  • the threshold voltage Vth of the driving transistor Td will drift during the working process, and the threshold voltage Vth of the driving transistor Td located in different sub-pixels may not necessarily be the same. In this way, when displaying the same grayscale data, different The driving current I generated by the driving transistor Td in the sub-pixel will be different, so that the brightness of the light-emitting devices L of different sub-pixels is uneven, which affects the display effect.
  • the driving circuit 01 provided in the embodiment of the present application as shown in FIG. 7, further includes a compensation sub-circuit 40.
  • the compensation sub-circuit 40 is connected to the first scanning signal terminal G_A and the driving sub-circuit 10.
  • the compensation sub-circuit 40 is configured to compensate the threshold voltage of the driving sub-circuit 10 under the control of the first scan signal terminal G_A.
  • the compensation sub-circuit 40 can compensate the threshold voltage Vth of the driving transistor Td. A specific process of compensating the threshold voltage Vth will be described later.
  • the compensation sub-circuit 40 may include a sixth transistor T6.
  • the gate of the sixth transistor T6 is connected to the first scanning signal terminal G_A, and the first and second electrodes are both connected to the driving sub-circuit 10.
  • the first pole of the sixth transistor T6 is connected to the second pole of the driving transistor Td
  • the second pole of the sixth transistor T6 is connected to the gate of the driving transistor Td.
  • the driving circuit 01 provided in the embodiment of the present application further includes a reset sub-circuit 50.
  • the reset sub-circuit 50 is connected to a reset voltage terminal VINT, a reset control signal terminal RS, and the driving sub-circuit 10.
  • the reset sub-circuit 50 is used for transmitting the reset voltage provided by the reset voltage terminal VINT to the driving sub-circuit 10 under the control of the reset control signal terminal RS.
  • the reset sub-circuit 50 includes a seventh transistor T7.
  • the gate of the seventh transistor T7 is connected to the reset control signal terminal RS, the first electrode is connected to the reset voltage terminal VINT, and the second electrode is connected to the driving sub-circuit 10.
  • the first electrode of the seventh transistor T7 is connected to the gate of the driving transistor Td.
  • FIG. 7 is described by using the driving method of the driving device 100 and the light emitting device L as shown in FIG. 1.
  • the driving device 100 and the light emitting device L are connected as shown in FIG. 2, the specific structures and connection methods of the compensation sub-circuit 40 and the reset sub-circuit 50 are the same as those described above, and the driving sub-circuit 10, the writing sub-circuit 20, The structure of the drive circuit 01 of the step control sub-circuit 30, the compensation sub-circuit 40, and the reset sub-circuit 50 is shown in FIG.
  • each transistor as a P-type transistor as an example.
  • the transistors in each sub-circuit may also be N-type transistors.
  • the first electrode of the transistor may be a source electrode and the second electrode is a drain electrode; alternatively, the first electrode is a drain electrode and the second electrode is a source electrode.
  • the following uses the structure of the driving circuit 01 shown in FIG. 7 as an example to describe the working process of the driving circuit 01 in an image frame in detail.
  • the driving circuit 01 may have multiple scanning periods S in one image frame. For example, as shown in FIG. 9, description is made by taking an image frame having three scanning periods S1, S2, and S3 as an example.
  • Each scanning cycle can be divided into three phases: a first phase t1, a second phase t2, and a third phase t3.
  • the reset control signal terminal RS inputs a low level
  • the seventh transistor T7 is turned on, and the reset voltage provided by the reset voltage terminal VINT is transmitted to the driving transistor Td through the seventh transistor T7.
  • the gate of the driving transistor Td is reset to prevent the voltage remaining in the driving transistor Td from the previous image frame from affecting the display of the image frame.
  • the voltage of the node N1 is the reset voltage provided by the reset voltage terminal VINT.
  • the reset voltage may be a low level, so that the driving transistor is in a state close to being turned on and the driving transistor Td is not turned on, so that the gate of the driving transistor Td is performed during the subsequent data writing phase.
  • Preparation for charging enables the first data voltage Vdata_A to charge the gate of the driving transistor Td more quickly. Therefore, in the subsequent data writing period, when different data voltages are written to the driving transistor, the data voltage writing time can be reduced, so that for all the driving circuits of the entire display panel, all of the driving transistors Td The response time is almost the same, and the writing time of the data voltage is approximately the same. For the entire display panel, this setting method makes the display effect more uniform.
  • the first phase t1 may be referred to as a reset phase.
  • the first scanning signal terminal G_A and the second scanning signal terminal G_B are input with a low level.
  • the fifth transistor T5 and the sixth transistor T6 are turned on.
  • the first data voltage Vdata_A provided by the first data signal terminal D_A is transmitted to the first electrode of the driving transistor Td through the fifth transistor T5.
  • the gate of the driving transistor Td and the second electrode are electrically connected, so that the driving transistor Td functions as a diode.
  • the first data voltage Vdata_A charges the gate of the driving transistor Td until the driving transistor Td is turned off.
  • the first data voltage Vdata_A is written to the gate of the driving transistor Td.
  • the third transistor T3 is turned on, and the second data voltage Vdata_B provided by the second data signal terminal D_B is transmitted to the gate of the fourth transistor T4 through the third transistor T3.
  • the voltage of the node N2 is Vdata_B.
  • the second phase t2 may be a data writing phase.
  • the light emission control signal terminal EM provides a low level, and the first transistor T1 and the second transistor T2 are turned on.
  • the second data voltage Vdata_B output from the second data signal terminal D_B has two modes of high level (VGH) and low level (VGL). It can be set that when the gate of the fourth transistor T4 receives a high level, the fourth transistor T4 is turned off, and when the gate of the fourth transistor T4 receives a low level, the fourth transistor T4 is turned on.
  • the second data voltage Vdata_B is at a low level.
  • the second scanning signal terminal G_B is changed from a low level to a high level, and the third transistor T3 is turned off.
  • the potential of the node N2 is still maintained at the high level in the second stage t2, so the fourth transistor T4 is turned off, and the light-emitting device L does not emit light at this time. Therefore, by controlling the light emitting device L not to emit light during the scanning period, the light emitting time of the light emitting device in one image frame can be reduced as a whole.
  • Vdata_B may be set to a low level at the second period t2, so that the fourth transistor T4 is turned on in the third period t3.
  • the first The current path between the working voltage terminal VL1 and the second working voltage terminal VL2 is turned on.
  • the driving current I generated by the driving transistor Td operating in the saturation region is transmitted to the light emitting device L through the current path, so that the light emitting device L emits light.
  • K 1/2 Cox ( ⁇ W / L); Cox, ⁇ , W, and L are the channel capacitance, channel mobility, channel width, and channel length of the driving transistor Td, respectively. K is therefore constant.
  • the driving current I is independent of the threshold voltage Vth of the driving transistor Td. Therefore, the magnitude of the driving current I does not change due to a shift in the threshold voltage Vth of the driving transistor Td.
  • the third stage t3 may be a light emitting stage.
  • Vdata_B may be set to a low level at a second period t2 of the second scanning period S2, so that the fourth transistor T4 is turned on in the second scanning period S1, and thus the light emitting device L is in the second scanning
  • the period S2 emits light to change the effective light-emitting brightness of the light-emitting device L in one image frame.
  • Vdata_B can decide when to transmit the driving current I to the light emitting device L.
  • the effective light emission luminance of the light-emitting device L in the driving circuit 01 in an image frame can be determined by the number of scanning periods in an image frame, the duration of each scanning period, the first data voltage Vdata_A, and the second data voltage.
  • Vdata_B, the light emission control signal provided by the light emission control signal terminal EM are determined by multiple factors, so that the sub-pixel display with the driving circuit 01 can have more grayscale values, and the picture displayed on the display panel is richer and more delicate.
  • FIG. 7 the gates of the fifth transistor T5 and the sixth transistor T6 are connected to the first scan signal terminal G_A, and the gates of the third transistor T3 are connected to the second scan signal terminal G_B.
  • FIG. 9 is an example in which the signals input from the first scan signal terminal G_A and the second scan signal terminal G_B are the same.
  • the valid signal input from the second scanning signal terminal G_B may be delayed, for example, at the second stage t2, the second scanning signal The valid signal input from the terminal G_B is later than the valid signal input from the first scan signal terminal G_A.
  • the valid signal refers to a level signal, such as a low level, that can make the sub-circuit that receives the valid signal in an on state.
  • the turn-on time of the grayscale control sub-circuit 30 receiving the valid signal input from the second scan signal terminal G_B is later than the turn-on time of the writing sub-circuit 20 receiving the valid signal input from the first scan signal terminal G_A.
  • the effective signal refers to a level signal that enables the transistor controlled by the effective signal to be in an on state.
  • the gray-scale control sub-circuit 30 includes a third transistor T3
  • the write sub-circuit 20 includes a fifth transistor T5
  • the compensation sub-circuit 40 includes a sixth transistor T6, the fifth transistor T5 and The on-time of the sixth transistor T6 is prior to the on-time of the third transistor T3 controlled by the second scan signal terminal G_B.
  • the transistor is a P-type transistor, the effective signal is low.
  • the on-time of the fourth transistor T4 can be delayed, thereby preventing a leakage current generated by the second transistor T2 from flowing through the light-emitting device L through the fourth transistor T4 and causing a false light emission phenomenon. That is, according to the embodiment of the present disclosure, after the state in which the first data voltage Vdata_A provided by the first data signal terminal D_A is written into the driving transistor Td is stable, and the driving current I generated by the driving transistor Td is stable, the third The transistor T3 is turned on again, and the fourth transistor T4 is controlled to be turned on to transmit a stable driving current I to the light emitting device L, so that the light emitting brightness of the light emitting device L is stable.
  • Some embodiments of the present application provide a display device including a display panel.
  • a display area of the display panel has a plurality of sub-pixels 02 as shown in FIG. 10, and at least one of the sub-pixels 02 is provided with any one of the foregoing.
  • the sub-pixel 02 may be defined by the first scanning signal line G_A and the first data signal line D_A crossing horizontally and vertically.
  • the second scan signal line G_B may be disposed in parallel with the first scan signal line G_A
  • the second data signal line D_B may be disposed in parallel with the first data signal line D_A.
  • the first transistors T1 in the driving circuit 01 of the sub-pixels located in the same row are connected to the same light emission control signal terminal EM.
  • the light-emitting control signal terminal EM provides an effective signal, such as a low level as shown in FIG. 9, each of the first and second transistors T1 and T2 in the same row is turned on.
  • the third transistor T3 can be turned on by inputting an effective signal through the second scan signal terminal G_B. Then, after the third transistor T3 is turned on, When the second data voltage Vdata_B provided by the two data signal terminals D_B is an effective signal, the fourth transistor T4 is controlled to be turned on, so that the current path between the first working voltage terminal VL1 and the second working voltage terminal VL2 is turned on.
  • the driving current I generated by the driving transistor Td can be transmitted to the light emitting device L through a current path.
  • the magnitude of the driving current I can also be adjusted by adjusting the magnitude of the first data voltage Vdata_A provided by the first data signal terminal D_A. The larger the driving current I is, the higher the effective light-emitting brightness of the light-emitting device L in one scanning period S is.
  • the third stage t3 in these three scanning periods is different from each other. Therefore, the corresponding one or more scanning periods can be selected according to the desired light emitting time of the light emitting device, so that the light emitting device at the third stage t3 in the one or more scanning periods emits light, so that 8 different gray levels can be obtained.
  • the third stage in a plurality of scanning cycles of one image frame may be the same as each other.
  • one or more scanning periods may also be selected according to the desired light emitting time of the light emitting device, so that the light emitting device emits light at the third stage t3 in the one or more scanning periods, so as to change the light emitting device light emitting time, 4 Different gray scales.
  • the adjustable range of the light emitting time and effective brightness of the light emitting device can be enlarged, and the gray of the display panel can be displayed. Order number.
  • the display device may be any product or component having a display function such as a display, a television, a digital photo frame, a mobile phone, or a tablet computer.
  • the display device has the same technical effects as the driving circuit 01 provided in the foregoing embodiment, and details are not described herein again.
  • Some embodiments of the present application provide a method for driving the driving circuit 01 as described above.
  • the driving circuit In an image frame, the driving circuit has multiple scanning cycles.
  • the gray-scale control sub-circuit 30 in the driving circuit 01 includes a first control sub-circuit 301 and a second control sub-circuit 302.
  • a scanning period S (for example, the first scanning period S1)
  • the method for driving the driving circuit includes steps S100 to S103.
  • Step S101 includes providing a first scan signal to the first scan signal terminal G_A, and providing a first data voltage Vdata_A to the first data signal terminal D_A.
  • the first data voltage Vdata_A is written to the driving subcircuit 10 through the writing subcircuit 20.
  • the signal provided by the first scanning signal terminal G_A has two states of high level and low level.
  • a low level Can be used as an effective signal for turning on the writing sub-circuit 20.
  • the writing sub-circuit 20 is turned off.
  • Step S102 includes providing a second scan signal to the second scan signal terminal G_B, and providing a second data voltage Vdata_B to the second data signal terminal D_B, so that the second control sub-circuit 302 performs the second scan signal and the second data voltage Vdata_B. Turn on or off under control.
  • the second scan signal terminal G_B and the second data voltage terminal D_B have two states of high level and low level.
  • the low level when the low level is input to the second scan signal terminal G_B and the first
  • the two data voltage terminals D_B input a low level, they can be used as an effective signal for turning on the second control sub-circuit 302.
  • the second control sub-circuit 302 is turned off.
  • step S101 and step S102 may be performed in a second stage t2 in a scanning cycle shown in FIG. 9.
  • the driving circuit 01 further includes a compensation sub-circuit 40
  • the compensation sub-circuit 40 when the first scanning signal is provided to the first scanning signal terminal G_A at the second stage t2, the compensation sub-circuit 40 is turned on, thereby driving the driving sub-circuit 10
  • the threshold voltage Vth of the middle driving transistor Td is compensated.
  • Step S103 includes providing a light-emitting control signal to the light-emitting control signal terminal EM, and the first operating voltage VDD provided by the first operating voltage terminal VL1 is transmitted to the driving sub-circuit 10 through the first control sub-circuit 301 so that the light-emitting device L is in the light-emitting control signal
  • the first scan signal, the second scan signal, and the second data voltage Vdata_B are controlled to emit light based on the first operating voltage VDD and the first data voltage Vdata_A.
  • the light emission control signal terminal EM has two states of high level and low level. In the embodiment of the present application, when the light emission control signal terminal EM provides a low level, it can be used to turn on the first control element. Active signal from circuit 301. When the light-emitting control signal terminal EM provides a high level, the first control sub-circuit 301 is turned off.
  • the driving sub-circuit 10 generates a driving current I according to the first data voltage Vdata_A and the first operating voltage VDD.
  • the driving current I is transmitted to the second control sub-circuit 302 through the first control sub-circuit 301. Since both the first control sub-circuit 301 and the second control sub-circuit 302 are turned on, the current path between the first working voltage terminal VL1 and the second working voltage terminal VL2 is turned on, and the driving current I is transmitted to the light-emitting device through the current path. L.
  • the light emitting device L receives the driving current I in the current path and emits light.
  • step S103 may be performed in a third stage t3 in a scanning cycle shown in FIG. 9.
  • the driving method of the driving circuit as shown in FIG. 11, further includes:
  • step S100 a reset control signal is provided to the reset control signal terminal RS, and a reset voltage is provided to the reset voltage terminal VINT.
  • the reset voltage is transmitted to the driving sub-circuit 10 through the reset sub-circuit 50.
  • the reset control signal terminal RS has two states of high level and low level.
  • the reset control signal terminal RS when the reset control signal terminal RS inputs a low level, it can be used to enable the reset sub-circuit 50. Effective signal.
  • the reset control signal terminal RS inputs a high level, the reset sub-circuit 50 is turned off.
  • the step S100 can be used to reset the gate of the driving transistor Td in the driving sub-circuit 10.
  • Step S100 may be performed in a first stage t1 in a scanning cycle shown in FIG. 9.
  • each sub-circuit in the driving circuit 10 is shown in FIG. 7 or FIG. 8, the driving method of the driving circuit 10 has been detailed in the working process of the driving circuit 10 in the foregoing embodiment. The description is not repeated here.
  • the driving method of the driving circuit has the same technical effects as those of the driving circuit provided in the foregoing embodiment, and details are not described herein again.
  • the second control sub-circuit 302 is turned on again, optionally, as shown in FIG. 12, in a scanning period S In the second phase t2, the time when the second scanning signal terminal G_A outputs a valid signal is later than the time when the first scanning signal terminal G_B outputs a valid signal. Therefore, after the driving current I generated by the driving sub-circuit 10 is stabilized, the second control sub-circuit 302 is turned on again to turn on the current path.
  • the description of the valid signals is the same as above, and is not repeated here.
  • the driving sub-circuit 10 includes a driving transistor Td and a second capacitor C2, the gate of the driving transistor Td is connected to one end of the second capacitor C2, and the other end of the second capacitor C2 is connected to the second voltage terminal V2.
  • the second voltage terminal V2 is near the first working voltage terminal VL1. Therefore, in order to make the circuit layout design easier, the second voltage terminal V2 and the first working voltage terminal VL1 have the same voltage input. In this way, the first working voltage terminal VL1 and the second voltage terminal V2 can be electrically connected.
  • the driving sub-circuit 10 operates, the first working voltage VDD provided by the first working voltage terminal VL1 can be transmitted to the second voltage terminal V2.
  • the driving device 100 may include only the second grayscale control sub-circuit 302 and the driving transistor Td and the second transistor T2. It can be understood that the driving sub-circuit Td can generate a driving current for driving the light emitting device L according to a source signal provided by the third voltage terminal V3 and a gate signal provided by the fourth voltage terminal V4. The driving time of the light emitting device L may be controlled by the second transistor T2 and the second control sub-circuit 302.
  • the driving sub-circuit 10 may include only the driving transistor Td, a gate of the driving transistor is connected to the fourth voltage terminal V4, a first pole is connected to the writing sub-circuit, and a second pole is connected to the The gray-scale control sub-circuit is described.
  • the fourth voltage terminal V4 is used to provide a suitable voltage signal to the gate of the driving transistor Td, so that the driving transistor Td is turned on.

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Abstract

一种驱动电路（01）及其驱动方法、显示装置，涉及显示技术领域。驱动电路（01）用于驱动待驱动元件（L），驱动电路（01）包括驱动器件（100）。驱动器件（100）和待驱动元件（L）串联于第一工作电压端（VL1）和第二工作电压端（VL2）之间。驱动器件（100）包括驱动子电路（10）、写入子电路（20）以及灰阶控制子电路（30）。写入子电路（20）将第一数据信号端（DA）提供的第一数据电压（Vdata-A）写入至驱动子电路（10）。灰阶控制子电路（30）将第一工作电压端（VL1）提供的第一工作电压传输至驱动子电路（10）。驱动子电路（10）生成驱动电流。灰阶控制子电路（30）还控制电流通路的导通时长。

Description

驱动电路及其驱动方法、显示装置
相关申请的交叉引用
本申请要求于2018年6月29日提交的中国专利申请No.201810696655.5的优先权，该中国专利申请所公开的内容以引用的方式全文并入本文中。
技术领域
本公开涉及显示技术领域，尤其涉及驱动电路及其驱动方法、显示装置。
背景技术
相对于OLED(Organic Light Emitting Diode，有机发光二极管)显示装置而言，微型发光二极管显示装置(例如，Micro LED显示装置或μLED显示装置)具有驱动电压低、寿命长、耐宽温等优势，并逐渐应用至移动终端领域。
发明内容
一方面，本公开提供一种驱动电路，包括驱动器件，用于驱动待驱动元件工作；
所述驱动器件和所述待驱动元件串联于第一工作电压端和第二工作电压端之间；所述驱动器件用于向所述待驱动元件提供驱动信号，并控制所述第一工作电压端和所述第二工作电压端之间信号通路的导通时长；
所述驱动器件包括驱动子电路、写入子电路以及灰阶控制子电路；
所述写入子电路连接第一扫描信号端、第一数据信号端以及所 述驱动子电路；所述写入子电路用于在所述第一扫描信号端的控制下，将所述第一数据信号端提供的第一数据电压写入至所述驱动子电路；
所述灰阶控制子电路连接驱动控制信号端、第二扫描信号端、第二数据信号端、所述驱动子电路；
所述灰阶控制子电路用于在所述驱动控制信号端的控制下，将所述第一工作电压端提供的第一工作电压传输至所述驱动子电路；
所述驱动子电路用于根据所述第一数据电压和所述第一工作电压，生成所述驱动信号；
所述灰阶控制子电路还用于在所述驱动控制信号端、所述第二扫描信号端以及所述第二数据信号端的控制下，控制所述电流通路的导通时长。
根据本公开的实施例，所述灰阶控制子电路包括第一控制子电路和第二控制子电路；
所述第一控制子电路连接所述驱动控制信号端、所述驱动子电路以及所述第二控制子电路；所述第一控制子电路用于在所述驱动控制信号端的控制下，将所述第一工作电压端提供的第一工作电压传输至所述驱动子电路；
所述第一控制子电路还用于在所述驱动控制信号端的控制下，将所述驱动子电路产生的驱动电流传输至所述第二控制子电路，并控制所述电流通路的导通时长；
所述第二控制子电路还连接所述第二扫描信号端、所述第二数据信号端；所述第二控制子电路用于在所述第二扫描信号端和所述第二数据信号端的控制下，控制所述电流通路的导通时长。
根据本公开的实施例，所述驱动电路还包括补偿子电路；
所述补偿子电路连接所述第一扫描信号端以及所述驱动子电路；所述补偿子电路用于在所述第一扫描信号端的控制下，对所述驱动子电路的阈值电压进行补偿。
根据本公开的实施例，所述驱动电路还包括复位子电路；
所述复位子电路连接复位电压端、复位控制信号端以及所述驱 动子电路；所述复位子电路用于在所述复位控制信号端的控制下，将所述复位电压端提供的复位电压传输至所述驱动子电路。
根据本公开的实施例，所述第一控制子电路包括第一晶体管和第二晶体管；
所述待驱动元件的阳极连接所述第二控制子电路，所述待驱动元件的阴极连接所述第二工作电压端；所述第一晶体管的栅极连接所述驱动控制信号端，第一极连接所述第一工作电压端，第二极连接所述驱动子电路；
所述第二晶体管的栅极连接所述驱动控制信号端，第一极连接所述驱动子电路，第二极连接所述第二控制子电路。
根据本公开的实施例，所述第一控制子电路包括第一晶体管和第二晶体管；
所述待驱动元件的阳极连接所述第一工作电压端；所述第一晶体管的栅极连接所述驱动控制信号端，第一极连接所述待驱动元件的阴极，第二极连接所述驱动子电路；
所述第二晶体管的栅极连接所述驱动控制信号端，第一极连接所述驱动子电路，第二极连接所述第二控制子电路。
根据本公开的实施例，所述第二控制子电路还连接第一电压端；所述第二控制子电路包括第三晶体管、第四晶体管以及第一电容；
所述第三晶体管的栅极连接所述第二扫描信号端，第一极连接所述第二数据信号端，第二极连接所述第四晶体管的栅极；
所述第一电容的一端与所述第三晶体管的第二极相连接，所述第一电容的另一端连接所述第一电压端；
所述待驱动元件的阴极连接所述第二工作电压端；所述第四晶体管的第一极连接所述第一控制子电路，第二极与所述待驱动元件的阳极相连接。
根据本公开的实施例，所述第二控制子电路还连接第一电压端；所述第二控制子电路包括第三晶体管、第四晶体管以及第一电容；
所述第三晶体管的栅极连接所述第二扫描信号端，第一极连接所述第二数据信号端，第二极连接所述第四晶体管的栅极；
所述第一电容的一端与所述第三晶体管的第二极相连接，所述第一电容的另一端连接所述第一电压端；
所述待驱动元件的阳极连接所述第一工作电压端，所述待驱动元件的阴极连接所述第一控制子电路；所述第四晶体管的第一极连接所述第一控制子电路，第二极与所述第二工作电压端相连接。
根据本公开的实施例，所述驱动子电路还连接第二电压端，所述驱动子电路包括驱动晶体管；
所述驱动晶体管的栅极连接所述第二电压端，第一极连接所述写入子电路，第二极连接所述灰阶控制子电路。
根据本公开的实施例，所述驱动子电路还连接第二电压端，所述驱动子电路包括驱动晶体管和第二电容；
所述驱动晶体管的栅极连接所述第二电容的一端，第一极连接所述写入子电路，第二极连接所述灰阶控制子电路；
所述第二电容的另一端连接所述第二电压端。
根据本公开的实施例，所述写入子电路包括第五晶体管；
所述第五晶体管的栅极连接所述第一扫描信号端，第一极连接所述第一数据信号端，第二极与所述驱动子电路相连接。
根据本公开的实施例，所述补偿子电路包括第六晶体管；
所述第六晶体管的栅极连接所述第一扫描信号端，第一极和第二极均连接所述驱动子电路。
根据本公开的实施例，所述复位子电路包括第七晶体管；
所述第七晶体管的栅极连接所述复位控制信号端，第一极连接所述复位电压端，第二极与所述驱动子电路相连接。
根据本公开的实施例，所述待驱动元件为微型发光二极管。
另一方面，本公开提供一种驱动电路，用于驱动待驱动元件工作，所述驱动电路包括第一晶体管至第七晶体管、第一电容、第二电容、驱动晶体管、复位控制信号端、驱动控制信号端、第一数据信号端、第二数据信号端、第一扫描信号端、第二扫描信号端、第一工作电压端、第一电压端和第二电压端，其中，
所述驱动控制信号端连接至所述第一晶体管的栅极和所述第二 晶体管的栅极，
所述第一数据信号端连接至所述第五晶体管的第一极，
所述第二数据信号端连接至所述第三晶体管的第一极，
所述第一扫描信号端连接至第五晶体管的栅极和第六晶体管的栅极，
所述第二扫描信号端连接至所述第三晶体管的栅极，
所述第一工作电压端连接至所述第一晶体管的第一极，
所述第一电压端连接至所述第一电容的一端，
所述第二电压端连接至所述第二电容的一端，
所述复位控制信号端连接至所述第七晶体管的栅极，
所述复位电压端连接至所述第七晶体管的第一极，
所述第一晶体管的第二极、所述第五晶体管的第二极连接至所述驱动晶体管的第一极，
所述第二电容的另一端、所述第六晶体管的第二极、所述第七晶体管的第二极连接至所述驱动晶体管的栅极，
所述第二晶体管的第一极、所述第六晶体管的第一极连接至所述驱动晶体管的第二极，
所述第二晶体管的第二极连接至所述第四晶体管的第一极，
所述第一电容的另一端、所述第三晶体管的第二极连接至所述第四晶体管的栅极，
所述第四晶体管的第二极连接至待驱动元件。
另一方面，本公开提供一种驱动电路，用于驱动待驱动元件工作，所述驱动电路包括第一晶体管至第七晶体管、第一电容、第二电容、驱动晶体管、复位控制信号端、驱动控制信号端、第一数据信号端、第二数据信号端、第一扫描信号端、第二扫描信号端、电源电压端、第一电压端和第二电压端，其中，
所述驱动控制信号端连接至所述第一晶体管的栅极和所述第二晶体管的栅极，
所述第一数据信号端连接至所述第五晶体管的第一极，
所述第二数据信号端连接至所述第三晶体管的第一极，
所述第一扫描信号端连接至第五晶体管的栅极和第六晶体管的栅极，
所述第二扫描信号端连接至所述第三晶体管的栅极，
所述电源电压端连接至所述第四晶体管的第二极，
所述第一电压端连接至所述第一电容的一端，
所述第二电压端连接至所述第二电容的一端，
所述复位控制信号端连接至所述第七晶体管的栅极，
所述复位电压端连接至所述第七晶体管的第一极，
所述第一晶体管的第二极、所述第五晶体管的第二极连接至所述驱动晶体管的第一极，
所述第二电容的另一端、所述第六晶体管的第二极、所述第七晶体管的第二极连接至所述驱动晶体管的栅极，
所述第二晶体管的第一极、所述第六晶体管的第一极连接至所述驱动晶体管的第二极，
所述第二晶体管的第二极连接至所述第四晶体管的第一极，
所述第一电容的另一端、所述第三晶体管的第二极连接至所述第四晶体管的栅极，
所述第一晶体管的第一极连接至所述待驱动元件。
另一方面，本公开提供一种显示装置，包括基板，所述显示基板的显示区域具有多个亚像素，至少一个亚像素内设置有根据本公开实施例所述的驱动电路和待驱动元件，所述驱动电路用于向所述待驱动元件提供驱动信号。
另一方面，本公开提供一种用于对根据本公开实施例的驱动电路的驱动方法，其中，在一图像帧内，驱动电路具有多个扫描周期；所述灰阶控制子电路包括第一控制子电路和第二控制子电路；在一个所述扫描周期内，所述驱动电路驱动的方法包括：
向第一扫描信号端提供第一扫描信号，向第一数据信号端提供第一数据电压，所述第一数据电压通过写入子电路写入至驱动子电路；
向第二扫描信号端提供第二扫描信号，向第二数据信号端提供 第二数据电压，以使得第二控制子电路在所述第二扫描信号和所述第二数据电压的控制下开启或关闭；
向驱动控制信号端提供驱动控制信号，向所述第一工作电压端提供第一工作电压，所述第一工作电压通过第一控制子电路传输至驱动子电路，以使得待驱动元件在所述驱动控制信号、所述第一扫描信号、所述第二扫描信号以及所述第二数据电压的控制下基于所述第一数据电压和所述第一工作电压工作。
根据本公开的实施例，所述方法还包括：
在一个所述扫描周期内，所述第二扫描信号端输出有效信号的时间晚于所述第一扫描信号端输出有效信号的时间。
根据本公开的实施例，所述驱动电路还包括复位子电路，所述向第一扫描信号端提供第一扫描信号，向第一数据信号端提供第一数据电压，所述第一数据电压通过写入子电路写入至驱动子电路之前，所述驱动电路驱动的方法还包括：
向复位控制信号端提供复位控制信号，向复位电压端提供复位电压，所述复位电压通过所述复位子电路传输至所述驱动子电路。
根据本公开的实施例，所述驱动子电路包括驱动晶体管和第二电容；所述驱动晶体管的栅极连接所述第二电容的一端，所述第二电容的另一端连接第二电压端，所述第二电压端与所述第一工作电压端输入的电压相同。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开的一些实施例提供的一种驱动电路的结构示意图；
图2为本公开的一些实施例提供的另一种驱动电路的结构示意图；
图3为图1所示的驱动电路的一种具体结构示意图；
图4为图2所示的驱动电路的一种具体结构示意图；
图5为图3所示的驱动电路中各个子电路的具体结构示意图；
图6为图4所示的驱动电路中各个子电路的具体结构示意图；
图7为本公开的一些实施例提供的另一种驱动电路的结构示意图；
图8为本公开的一些实施例提供的另一种驱动电路的结构示意图；
图9为本公开的一些实施例提供的一种时序信号图；
图10为本公开的一些实施例提供的一种显示面板的结构示意图；
图11为本公开的一些实施例提供的一种驱动电路的驱动方法流程图；
图12为本公开的一些实施例提供的另一种时序信号图；
图13为另一实施例的驱动电路中各个子电路的具体结构示意图。
图14为另一实施例的驱动电路中各个子电路的具体结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本申请的一些实施例提供一种驱动电路01，如图1或图2所示，所述驱动电路01包括驱动器件100和待驱动元件L。
驱动器件100和待驱动元件L串联于第一工作电压端VL1和第二工作电压端VL2之间。
例如，如图1所示，驱动器件100连接在第一工作电压端VL1 和待驱动元件L的阳极之间，该待驱动元件L的阴极连接第二工作电压端VL2。
可替代地，又例如，如图2所示，驱动器件100连接在第二工作电压端VL2和待驱动元件L的阴极之间，该待驱动元件L的阳极连接第一工作电压端VL1。
待驱动元件L可以为发光器件，例如微型发光二极管，例如μLED或者Micro LED。μLED或者Micro LED的尺寸级别为微米(μm)级别。本公开的实施例是以待驱动元件L为发光器件、驱动电路01为驱动电路作为示例进行描述。可以理解，待驱动元件L可以为其他流控型电子元器件。
本公开的实施例中，驱动器件100用于提供驱动电流I，并控制第一工作电压端VL1和第二工作电压端VL2之间电流通路的导通时长。
在电流通路导通时，第一工作电压端VL1输出的第一工作电压VDD与第二工作电压端VL2输出的第二工作电压VSS可以向电流通路提供电势差，使得驱动电流I能够沿电流通路传输至发光器件L。
需要说明的是，第一工作电压VDD可以为恒定的高电平，第二工作电压VSS可以为恒定的低电平。
发光器件L用于在电流通路中接收驱动电流I，并发光。
如图3或图4所示，驱动器件100包括驱动子电路10、写入子电路20以及灰阶控制子电路30。
写入子电路20连接第一扫描信号端G_A、第一数据信号端D_A以及驱动子电路10。该写入子电路20用于在第一扫描信号端G_A的控制下，将第一数据信号端D_A提供的第一数据电压Vdata_A写入至驱动子电路10。
灰阶控制子电路30连接发光控制信号端EM(作为驱动控制信号端)、第二扫描信号端G_B、第二数据信号端D_B、驱动子电路10。
当驱动电路01采用如图1所示的结构时，如图3所示，该驱动电路01中的灰阶控制子电路30可以与第一工作电压端VL1直接连接，并且通过发光器件L与第二工作电压端VL2连接。可替代地，当 驱动电路01采用如图2所示的结构时，如图4所示，该驱动电路01中的灰阶控制子电路30可以通过发光器件L与第一工作电压端VL1相连接，并且直接与第二工作电压端VL2连接。在如图3所示的驱动电路01的情况下，灰阶控制子电路30用于在发光控制信号端EM的控制下，将第一工作电压端VL1提供的第一工作电压VDD传输至驱动子电路10。
驱动子电路10用于根据第一数据电压Vdata_A和第一工作电压VDD，生成驱动电流I。
灰阶控制子电路30还用于在发光控制信号端EM、第二扫描信号端G_B以及第二数据信号端D_B的控制下，控制电流通路的导通时长。
综上所述，写入子电路20能够将与显示灰阶有关的第一数据电压Vdata_A输出至驱动子电路10，以使得驱动子电路10能够产生用于驱动发光器件L发光的驱动电流I。此外，灰阶控制子电路30可以控制驱动电流I在流入发光器件L的过程中，所形成的电流通路的导通时长，从而控制发光器件L的发光时长。由于驱动电流I的大小和发光时长影响发光器件的L的有效亮度，这样一来，在一个扫描周期内，通过第一数据电压Vdata_A的大小以及灰阶控制子电路30可以控制发光器件L有效发光亮度，达到调节显示灰阶的目的。根据本公开的实施例，由于每个驱动电路01中均设置有灰阶控制子电路30，并且对于同一行的亚像素对应的各个驱动电路而言，所包括的各个灰阶控制子电路30连接至不同的数据信号线(即，受到彼此独立的第二数据电压Vdata_B的控制)，因此，本申请实施例提供的驱动电路01可以直接对该驱动电路01中的发光器件L(例如μLED)的亮度单独进行控制。此外。本申请实施例提供的驱动电路01可以通过构图工艺制作于显示装置的显示面板中的玻璃衬底或透明树脂衬底上。在发光器件为μLED时，能够提供一种成本较低、制作工艺简单，可量产的μLED显示装置的实现方式。
以下对驱动电路01中各个子电路的结构进行详细的说明。
以图3所示的结构为例，灰阶控制子电路30，如图5所示，可以包括第一控制子电路301和第二控制子电路302。
参照图5，第一控制子电路301连接发光控制信号端EM、驱动子电路10以及第二控制子电路302。该第一控制子电路301用于在发光控制信号端EM的控制下，将第一工作电压端VL1提供的第一工作电压VDD传输至驱动子电路10。
第一控制子电路301还用于在发光控制信号端EM的控制下，将驱动子电路10产生的驱动电流I传输至第二控制子电路302，并控制电流通路的导通时长。
第二控制子电路302还连接第二扫描信号端G_B、第二数据信号端D_B。第二控制子电路302用于在第二扫描信号端G_B、和第二数据信号端D_B的控制下，控制电流通路在一个扫描周期内是否导通以及控制电流通路在多个扫描周期内的总的导通时长。
由上述可知，只有当第一控制子电路301和第二控制子电路302均处于开启状态时，电流通路才能够导通，驱动子电路10产生的驱动电流I才能够通过电流通路输出至发光器件L。这样一来，发光器件L的有效发光亮度可以受到驱动电流I、第一控制子电路301以及第二控制子电路302的协同控制，增加了影响发光器件L的有效发光亮度的因素，使得具有该驱动电路01的亚像素能够显示的灰阶值更加多样化。
根据本公开的实施例，如图5所示，第一控制子电路301可以包括第一晶体管T1和第二晶体管T2。
图5是以图3所示的结构为例，对图3中各个子电路的结构进行的说明。在此情况下，如图5所示，发光器件L的阴极连接第二工作电压端VL2。
第一晶体管T1的栅极连接发光控制信号端EM，第一极连接第一工作电压端VL1，第二极连接驱动子电路10。
第二晶体管T2的栅极连接发光控制信号端EM，第一极连接驱动子电路10，第二极连接第二控制子电路302。
此外，第二控制子电路302还连接第一电压端V1。该第一电压端V1可以为接地端GND。
第二控制子电路302包括第三晶体管T3、第四晶体管T4以及第 一电容C1。
第三晶体管T3的栅极连接第二扫描信号端G_B，第一极连接第二数据信号端D_B，第二极连接第四晶体管T4的栅极。
第一电容C1的一端与第三晶体管T3的第二极相连接，第一电容C1的另一端连接第一电压端V1。
如图5所示，在发光器件L的阳极连接第二控制子电路302，发光器件L的阴极连接第二工作电压端VL2的情况下，第四晶体管T4的第一极连接第一控制子电路301，第二极与发光器件L的阳极相连接。
在第一控制子电路301的结构如上所述时，第四晶体管T4的第一极连接第二晶体管T2的第二极。
根据本公开的另一实施例，以图4所示的结构为例，对图4中各个子电路的结构进行的说明。
图6是图4中各个子电路的结构示意图，参照图6，其与图5的各个子电路的结构类似，区别在于发光器件L、第一控制子电路、第二控制子电路的连接方式不同。具体地，参照图4和图6，发光器件L的阳极连接第一工作电压端VL1；发光器件L的阴极连接第一晶体管T1的第一极。第四晶体管T4的第一极连接第一控制子电路301，第二极与第二工作电压端VL2相连接。
根据本公开的实施例，如图7所示，驱动子电路10包括驱动晶体管Td和第二电容C2，该驱动晶体管Td的栅极连接第二电容C2的一端，第二电容C2的另一端连接第二电压端V2。该第二电压端V2可以与第一电压端V1相同，均为接地端GND。可替代地，由于第二电压端V2与第一工作电压端VL1的位置较近，因此为了使得电路版图设计更加简便，第二电压端V2可以与第一工作电压端VL1相连接，以接收第一工作电压端VL1输出的第一工作电压VDD。
驱动晶体管Td的栅极连接第二电容C2的一端，第一极连接写入子电路20，第二极连接灰阶控制子电路30。在灰阶控制子电路30的结构如上所述时，驱动晶体管Td的第二极连接第二晶体管T2的第一极。
根据本公开的实施例，写入子电路20包括第五晶体管T5。
第五晶体管T5的栅极连接第一扫描信号端G_A，第一极连接第一数据信号端D_A，第二极与驱动子电路10相连接。在驱动子电路10的结构如上所述时，第五晶体管T5的第二极连接驱动晶体管Td的第一极。
当驱动子电路10中的驱动晶体管Td在饱和区工作时，该驱动晶体管Td可以根据其栅极电压和源极电压生成驱动电流I。根据驱动电流公式I＝K(Vgs-Vth) 2可以得出，驱动电流I受到驱动晶体管Td的阈值电压Vth的影响。由于驱动晶体管Td在工作过程中，其阈值电压Vth会发生漂移，且位于不同亚像素的驱动晶体管Td的阈值电压Vth的漂移量不一定相同，这样一来，在显示同一灰阶数据时，不同亚像素中的驱动晶体管Td产生的驱动电流I会不同，从而使得不同亚像素的发光器件L的亮度不均，影响显示效果。
为了解决上述问题，本申请实施例提供的驱动电路01，如图7所示，还包括补偿子电路40。
该补偿子电路40连接第一扫描信号端G_A以及驱动子电路10。补偿子电路40用于在第一扫描信号端G_A的控制下，对驱动子电路10的阈值电压进行补偿。在驱动子电路10的结构如上所述时，该补偿子电路40可以对驱动晶体管Td的阈值电压Vth进行补偿。稍后将描述补偿阈值电压Vth的具体过程。
示例性的，补偿子电路40可以包括第六晶体管T6。
该第六晶体管T6的栅极连接第一扫描信号端G_A，第一极和第二极均连接驱动子电路10。在驱动子电路10的结构如上所述时，该第六晶体管T6的第一极连接驱动晶体管Td的第二极，该第六晶体管T6的第二极连接驱动晶体管Td的栅极。
此外，上一图像帧残留于驱动子电路10的信号对下一图像帧的显示画面造成影响，本申请实施例提供的驱动电路01，如图7所示，还包括复位子电路50。
该复位子电路50连接复位电压端VINT、复位控制信号端RS以及驱动子电路10。该复位子电路50用于在复位控制信号端RS的控 制下，将复位电压端VINT提供的复位电压传输至驱动子电路10。
复位子电路50包括第七晶体管T7。
该第七晶体管T7的栅极连接复位控制信号端RS，第一极连接复位电压端VINT，第二极与驱动子电路10相连接。在驱动子电路10的结构如上所述时，第七晶体管T7的第一极连接驱动晶体管Td的栅极。
需要说明的是，图7是以驱动器件100与发光器件L采用如图1的连接方式进行的说明。当驱动器件100与发光器件L采用如图2的连接方式时，补偿子电路40和复位子电路50的具体结构以及连接方式同上所述，且具有驱动子电路10、写入子电路20、灰阶控制子电路30、补偿子电路40以及复位子电路50的驱动电路01的结构如图8所示。
此外，图5至图8中，是以各个晶体管均为P型晶体管为例进行的说明。在本申请的一些实施例中，各个子电路中的晶体管还可以均为N型晶体管。晶体管的第一极可以为源极，第二极为漏极；可替代地，第一极为漏极，第二极为源极。
以下以图7所示的驱动电路01的结构为例，对该驱动电路01在一图像帧内的工作过程进行详细的说明。
在本申请的一些实施例中，为了使得具有驱动电路01的亚像素能够显示的灰阶值更多，显示效果更好，在一图像帧内，该驱动电路01可以具有多个扫描周期S。例如，如图9所述，是以图像帧具有三个扫描周期S1、S2以及S3为例进行的说明。
以每个扫描周期可以划分为三个阶段：第一阶段t1、第二阶段t2以及第三阶段t3。
以第一扫描周期S1为例，在第一阶段t1，复位控制信号端RS输入低电平，第七晶体管T7导通，复位电压端VINT提供的复位电压通过第七晶体管T7传输至驱动晶体管Td的栅极，从而对驱动晶体管Td的栅极进行复位，避免上一图像帧残留于驱动晶体管Td的电压对本图像帧的显示造成影响。此时，节点N1的电压为复位电压端VINT提供的复位电压。
根据本公开的实施例，复位电压可以为低电平，使驱动晶体管处于接近导通而驱动晶体管Td未能开启的状态，从而为接下来的数据写入阶段期间对驱动晶体管Td的栅极进行充电做准备，使得第一数据电压Vdata_A能够更快速地为驱动晶体管Td的栅极进行充电。因此，在后续的数据写入期间中，当不同的数据电压写入到驱动晶体管时，可以减少数据电压写入的时间，从而使得对于整个显示面板的所有驱动电路而言，所有驱动晶体管Td的响应时间几乎相同，数据电压的写入时间大致相同，对整个显示面板而言，这种设置方式使得显示效果均一性更高。
第一阶段t1可以称为复位阶段。
在第二阶段t2，第一扫描信号端G_A和第二扫描信号端G_B输入低电平。在第一扫描信号端G_A的控制下，第五晶体管T5和第六晶体管T6导通。第一数据信号端D_A提供的第一数据电压Vdata_A通过第五晶体管T5传输至驱动晶体管Td的第一极。
第六晶体管T6导通后，驱动晶体管Td的栅极和第二极电连接，从而使得驱动晶体管Td用作二极管。此时，第一数据电压Vdata_A向驱动晶体管Td的栅极进行充电，直至驱动晶体管Td截止为止。当驱动晶体管Td截止时，驱动晶体管Td的栅源电压Vgs＝Vth，即Vg-Vs＝Vth。此时，驱动晶体管Td的栅源电压(N1节点的电压)Vg＝Vs+Vth＝Vdata_A+Vth。在此情况下，第一数据电压Vdata_A写入至驱动晶体管Td的栅极。
此外，在第二扫描信号端G_B的控制下，第三晶体管T3导通，第二数据信号端D_B提供的第二数据电压Vdata_B通过第三晶体管T3传输至第四晶体管T4的栅极。节点N2的电压为Vdata_B。
在第一电容C1和第二电容C2的作用下，在第一扫描信号端G_A和第二扫描信号端G_B再次输出低电平之前，节点N1和节点N2的电位保持不变。
第二阶段t2可以为数据写入阶段。
在第三阶段t3，如图9所示，发光控制信号端EM提供低电平，第一晶体管T1和第二晶体管T2导通。
此外，第二数据信号端D_B输出的第二数据电压Vdata_B为高电平(VGH)和低电平(VGL)两种模式。可以设置当第四晶体管T4的栅极接收到高电平时，该第四晶体管T4截止，而当第四晶体管T4的栅极接收到低电平时，该第四晶体管T4导通。
图9中，在第三阶段t3，第二数据电压Vdata_B为低电平，此时，第二扫描信号端G_B由低电平变为高电平，第三晶体管T3截止。但是，由于第一电容C1的存在，使得节点N2的电位还保持为第二阶段t2时的高电平，因此第四晶体管T4截止，此时发光器件L不发光。从而可以通过控制在该扫描周期中发光器件L不发光来整体上减小一个图像帧中发光器件的发光时长。
可替代地，与图9所示的时序图相比，可以在第二时段t2处将Vdata_B设置为低电平，从而使得第三阶段t3中第四晶体管T4导通，该情况下，第一工作电压端VL1和第二工作电压端VL2之间的电流通路导通。此时，工作在饱和区的驱动晶体管Td产生的驱动电流I通过电流通路传输至发光器件L，使得该发光器件L发光。
驱动电流I＝K(Vgs-Vth) 2＝K(Vg-Vs-Vth) 2＝K(Vdata_A+Vth-VDD-Vth) 2＝K(Vdata_A-VDD) 2。
其中，K＝1/2Cox(μW/L)；Cox、μ、W、L分别为驱动晶体管Td的单位面积沟道电容、沟道迁移率、沟道宽度和沟道长度。因此K为常数。
由驱动电流I的公式可知，驱动电流I与驱动晶体管Td的阈值电压Vth无关。因此驱动电流I的大小不会由于驱动晶体管Td的阈值电压Vth发生漂移而改变。
第三阶段t3可以为发光阶段。
需要说明的是，是对第一扫描周期S1中驱动电路01的工作过程进行的说明。其余扫描周期中驱动电路01的工作过程同上所述，此处不再赘述。
不同之处在于，一方面、可以改变第一数据信号端D_A提供的第一数据电压Vdata_A的大小，以改变流过发光器件L的驱动电流I的大小。另一方面，还可以改变第二数据信号端D_B提供的第二数据 电压Vdata_B的大小。例如，参照图9，可以在第二扫描周期S2的第二时段t2处将Vdata_B设置为低电平，从而使得第四晶体管T4在第二扫描周期S1导通，因此发光器件L在第二扫描周期S2发光，以改变发光器件L在一个图像帧的有效发光亮度。因此，Vdata_B可以决定何时将驱动电流I传输至发光器件L。又一方面，还可以控制发光控制信号端EM提供低电平的时长，如控制发光控制信号端EM提供信号的占空比，以控制第一晶体管T1和第二晶体管T2的导通时长，从而控制驱动电流I流经的电流通路的导通时长。
综上所述，驱动电路01中发光器件L在一图像帧内的有效发光亮度可以由一图像帧内扫描周期的个数、每个扫描周期的时长、第一数据电压Vdata_A、第二数据电压Vdata_B、发光控制信号端EM提供的发光控制信号多个因素决定，从而可以使得具有驱动电路01的亚像素显示的灰阶值更多，显示面板显示的画面更加的丰富、细腻。
此外，如图7所示，第五晶体管T5和第六晶体管T6的栅极连接第一扫描信号端G_A，第三晶体管T3的栅极连接第二扫描信号端G_B。图9是以第一扫描信号端G_A和第二扫描信号端G_B输入的信号相同为例进行的说明。
本申请的一些实施例中，如图12所示，在一个扫描周期S内，可以使得第二扫描信号端G_B输入的有效信号有所延时，例如，在第二阶段t2，第二扫描信号端G_B输入的有效信号晚于第一扫描信号端G_A输入的有效信号。
有效信号是指，可以使得接收到该有效信号的子电路处于开启状态的电平信号，例如低电平。在此情况下，接收该第二扫描信号端G_B输入有效信号的灰阶控制子电路30的开启时间，晚于接收第一扫描信号端G_A输入有效信号的写入子电路20的开启时间。
此外，当子电路包括晶体管时，有效信号是指能够使得该有效信号控制的晶体管处于导通状态的电平信号。例如，在灰阶控制子电路30包括第三晶体管T3，写入子电路20包括第五晶体管T5和补偿子电路40包括第六晶体管T6时，第一扫描信号端G_A控制的第五晶体管T5和第六晶体管T6的导通时间，优先于第二扫描信号端G_B 控制的第三晶体管T3的导通时间。在晶体管为P型晶体管时，有效信号为低电平。
这样一来，可以使第四晶体管T4的导通时间延迟，从而避免第二晶体管T2产生的漏电流通过第四晶体管T4流过发光器件L造成误发光的现象。也就是说，根据本公开的实施例，在第一数据信号端D_A提供的第一数据电压Vdata_A写入驱动晶体管Td的状态稳定后，且该驱动晶体管Td产生的驱动电流I稳定后，第三晶体管T3再导通，并控制第四晶体管T4导通，以将稳定的驱动电流I传输至发光器件L，使得发光器件L的发光亮度稳定。
以上是以图7所示的结构为例进行的说明，图8所示的驱动电路01的工作过程同上所述，此处不再赘述。
本申请的一些实施例，提供一种显示装置，包括显示面板，该显示面板的显示区域具有多个如图10所示的亚像素02，至少一个亚像素02内设置有如上所述的任意一种驱动电路01。
亚像素02可以由横纵交叉的第一扫描信号线G_A与第一数据信号线D_A交叉界定。此外，第二扫描信号线G_B可以与第一扫描信号线G_A平行设置，第二数据信号线D_B可以与第一数据信号线D_A平行设置。
由图10可以看出，位于同一行的亚像素，其驱动电路01中的第一晶体管T1连接同一条发光控制信号端EM。在此情况下，当该发光控制信号端EM提供有效信号，例如如图9所示的低电平时，位于同一行的各个第一晶体管T1和第二晶体管T2均导通。
基于此，为了使得同一行中不同亚像素的发光亮度可以单独控制，可以通过第二扫描信号端G_B输入有效信号控制第三晶体管T3导通，然后，在第三晶体管T3导通后，通过第二数据信号端D_B提供的第二数据电压Vdata_B为有效信号时，控制第四晶体管T4的导通，从而使得第一工作电压端VL1与第二工作电压端VL2之间的电流通路导通。
驱动晶体管Td产生的驱动电流I能够通过电流通路传输至发光器件L。该电流通路导通的时间越长，发光器件L在一个扫描周期S 内的有效发光亮度越高。此外，还可以通过调整第一数据信号端D_A提供的第一数据电压Vdata_A的大小，达到调整驱动电流I的大小。该驱动电流I越大，发光器件L在一个扫描周期S内的有效发光亮度越高。
根据本公开的实施例，如图9所示，在一个图像帧内存在三个扫描周期S1、S2和S3。这三个扫描周期中的第三阶段t3彼此不同。因此，可以根据发光器件的期望的发光时长来选择相应的一个或多个扫描周期，使得在该一个或多个扫描周期内的第三阶段t3发光器件发光，从而能够得到8种不同的灰阶亮度。根据本公开的另一实施例，一个图像帧的多个扫描周期中的第三阶段可以彼此相同。因此也可以根据发光器件的期望的发光时长来选择一个或多个扫描周期，使得在该一个或多个扫描周期内的第三阶段t3发光器件发光，以改变发光器件的发光时长，可以得到4种不同的灰阶。
可以看出，在一个图像帧内存在多个扫描周期且每个扫描周期的长度都不同的情况下，能够扩大发光器件的发光时长和有效亮度的可调节范围，丰富显示面板的能够显示的灰阶数量。
综上所述，在相关技术中，在发光控制信号端EM提供的发光控制信号的控制下，可以实现一行驱动电路01中的所有亚像素同时发光，但是无法单独控制各亚像素的发光亮度和发光时长。然而，根据本申请提供的驱动电路，可以在发光控制信号端EM、第一扫描信号端G_A、第二扫描信号端G_B、第一数据信号端D_A以及第二数据信号端D_B的共同协作下，实现单个亚像素发光亮度的调节。
需要说明的是，显示装置可以为显示器、电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。其中，该显示装置具有与前述实施例提供的驱动电路01相同的技术效果，此处不再赘述。
本申请的一些实施例提供一种用于对如上所述的驱动电路01驱动的方法，在一图像帧内，驱动电路具有多个扫描周期。
驱动电路01中的灰阶控制子电路30包括第一控制子电路301和第二控制子电路302。
在一个扫描周期S(例如第一扫描周期S1)内，该驱动电路驱动的方法，如图11所示，包括步骤S100～S103。
步骤S101包括向第一扫描信号端G_A提供第一扫描信号，向第一数据信号端D_A提供第一数据电压Vdata_A，第一数据电压Vdata_A通过写入子电路20写入至驱动子电路10。
如图9所示，在一个扫描周期S内，第一扫描信号端G_A提供的信号具有高电平和低电平两种状态，本申请实施例中，当第一扫描信号端G_A输入低电平时，可以作为用于开启上述写入子电路20的有效信号。当第一扫描信号端G_A输入高电平时，写入子电路20关闭。
步骤S102包括向第二扫描信号端G_B提供第二扫描信号，向第二数据信号端D_B提供第二数据电压Vdata_B，以使得第二控制子电路302在第二扫描信号和第二数据电压Vdata_B的控制下开启或关闭。
通过控制第一控制子电路301和第二控制子电路302开启的时长，可以达到控制电流通路的导通时长的目的。
第二扫描信号端G_B以及第二数据电压端D_B，如图9所示，具有高电平和低电平两种状态，本申请实施例中，当第二扫描信号端G_B输入低电平时且第二数据电压端D_B输入低电平时，可以作为用于开启第二控制子电路302的有效信号。在其他状态下，第二控制子电路302关闭。
需要说明的是，步骤S101和步骤S102可以在图9所示的一扫描周期内的第二阶段t2执行。
此外，在驱动电路01还包括补偿子电路40的情况下，当在第二阶段t2，当向第一扫描信号端G_A提供第一扫描信号时，补偿子电路40开启，从而对驱动子电路10中驱动晶体管Td的阈值电压Vth进行补偿。
步骤S103包括向发光控制信号端EM提供发光控制信号，第一工作电压端VL1提供的第一工作电压VDD通过第一控制子电路301传输至驱动子电路10，以使得发光器件L在发光控制信号、第一扫 描信号、第二扫描信号以及第二数据电压Vdata_B的控制下基于所述第一工作电压VDD和所述第一数据电压Vdata_A发光。其中，发光控制信号端EM如图9所示，具有高电平和低电平两种状态，本申请实施例中，当发光控制信号端EM提供低电平时，可以作为用于开启第一控制子电路301的有效信号。当发光控制信号端EM提供高电平时，第一控制子电路301关闭。
具体的，驱动子电路10根据第一数据电压Vdata_A和第一工作电压VDD，生成驱动电流I。驱动电流I通过第一控制子电路301传输至第二控制子电路302。由于第一控制子电路301和第二控制子电路302均开启，因此第一工作电压端VL1和第二工作电压端VL2之间的电流通路导通，驱动电流I经过该电流通路传输至发光器件L。发光器件L在电流通路中接收驱动电流I，并发光。
需要说明的是，步骤S103可以在图9所示的一扫描周期内的第三阶段t3执行。
此外，在驱动电路10还包括复位子电路50的情况下，S101之前，该驱动电路驱动的方法，如图11所示还包括：
步骤S100，向复位控制信号端RS提供复位控制信号，向复位电压端VINT提供复位电压，该复位电压通过复位子电路50传输至驱动子电路10。
其中，复位控制信号端RS如图9所示，具有高电平和低电平两种状态，本申请实施例中，当复位控制信号端RS输入低电平时，可以作为用于开启复位子电路50的有效信号。当复位控制信号端RS输入高电平时，复位子电路50关闭。
采用步骤S100可以对驱动子电路10中驱动晶体管Td的栅极进行复位。
步骤S100可以在图9所示的一扫描周期内的第一阶段t1执行。
需要说明的是的，当驱动电路10中各个子电路的结构如图7或图8所示时，该驱动电路10的驱动方法在前述实施例中该驱动电路10的工作过程中已经进行了详细的说明，此处不再赘述。此外，驱动电路的驱动方法具有与前述实施例提供的驱动电路相同的技术效 果，此处不再赘述。
此外，为了使得第一数据电压Vdata_A通过写入子电路20稳定的写入至驱动子电路10后，第二控制子电路302再开启，可选的，如图12所示，在一扫描周期S中的第二阶段t2，第二扫描信号端G_A输出有效信号的时间晚于第一扫描信号端G_B输出有效信号的时间。从而使得驱动子电路10产生的驱动电流I稳定后，第二控制子电路302再开启以将电流通路导通。有效信号的说明同上所述，此处不再赘述。
此外，在驱动子电路10包括驱动晶体管Td和第二电容C2，该驱动晶体管Td的栅极连接第二电容C2的一端，第二电容C2的另一端连接第二电压端V2的情况下，由于第二电压端V2与第一工作电压端VL1的位置较近，因此为了使得电路版图设计更加简便，该第二电压端V2与第一工作电压端VL1输入的电压相同。这样一来，可以将第一工作电压端VL1与第二电压端V2电连接。在驱动子电路10工作时，第一工作电压端VL1提供的第一工作电压VDD可以传输至第二电压端V2。
根据本公开的另一实施例，如图13所示，驱动器件100可以仅包括第二灰阶控制子电路302和驱动晶体管Td、第二晶体管T2。可以理解的是，驱动子电路Td可以根据第三电压端V3提供的源极信号以及第四电压端V4提供的栅极信号生成用于驱动发光器件L的驱动电流。发光器件L的驱动时长可以受第二晶体管T2和第二控制子电路302的控制。
参照图14，根据本公开的实施例，驱动子电路10可以仅包括驱动晶体管Td，驱动晶体管的栅极连接第四电压端V4，第一极连接所述写入子电路，第二极连接所述灰阶控制子电路。第四电压端V4用于为驱动晶体管Td的栅极提供合适的电压信号，以使驱动晶体管Td导通。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。 因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种驱动电路，包括驱动器件，用于驱动待驱动元件工作；
    所述驱动器件和所述待驱动元件串联于第一工作电压端和第二工作电压端之间；所述驱动器件用于向所述待驱动元件提供驱动信号，并控制所述第一工作电压端和所述第二工作电压端之间信号通路的导通时长；
    所述驱动器件包括驱动子电路、写入子电路以及灰阶控制子电路；
    所述写入子电路连接第一扫描信号端、第一数据信号端以及所述驱动子电路；所述写入子电路用于在所述第一扫描信号端的控制下，将所述第一数据信号端提供的第一数据电压写入至所述驱动子电路；
    所述灰阶控制子电路连接驱动控制信号端、第二扫描信号端、第二数据信号端、所述驱动子电路；
    所述灰阶控制子电路用于在所述驱动控制信号端的控制下，将所述第一工作电压端提供的第一工作电压传输至所述驱动子电路；
    所述驱动子电路用于根据所述第一数据电压和所述第一工作电压，生成所述驱动信号；
    所述灰阶控制子电路还用于在所述驱动控制信号端、所述第二扫描信号端以及所述第二数据信号端的控制下，控制所述电流通路的导通时长。
  2. 根据权利要求1所述的驱动电路，其中，所述灰阶控制子电路包括第一控制子电路和第二控制子电路；
    所述第一控制子电路连接所述驱动控制信号端、所述驱动子电路以及所述第二控制子电路；所述第一控制子电路用于在所述驱动控制信号端的控制下，将所述第一工作电压端提供的第一工作电压传输至所述驱动子电路；
    所述第一控制子电路还用于在所述驱动控制信号端的控制下， 将所述驱动子电路产生的驱动电流传输至所述第二控制子电路，并控制所述电流通路的导通时长；
    所述第二控制子电路还连接所述第二扫描信号端、所述第二数据信号端；所述第二控制子电路用于在所述第二扫描信号端和所述第二数据信号端的控制下，控制所述电流通路的导通时长。
  3. 根据权利要求1所述的驱动电路，其中，所述驱动电路还包括补偿子电路；
    所述补偿子电路连接所述第一扫描信号端以及所述驱动子电路；所述补偿子电路用于在所述第一扫描信号端的控制下，对所述驱动子电路的阈值电压进行补偿。
  4. 根据权利要求1所述的驱动电路，其中，所述驱动电路还包括复位子电路；
    所述复位子电路连接复位电压端、复位控制信号端以及所述驱动子电路；所述复位子电路用于在所述复位控制信号端的控制下，将所述复位电压端提供的复位电压传输至所述驱动子电路。
  5. 根据权利要求2所述的驱动电路，其中，所述第一控制子电路包括第一晶体管和第二晶体管；
    所述待驱动元件的阳极连接所述第二控制子电路，所述待驱动元件的阴极连接所述第二工作电压端；所述第一晶体管的栅极连接所述驱动控制信号端，第一极连接所述第一工作电压端，第二极连接所述驱动子电路；
    所述第二晶体管的栅极连接所述驱动控制信号端，第一极连接所述驱动子电路，第二极连接所述第二控制子电路。
  6. 根据权利要求2所述的驱动电路，其中，所述第一控制子电路包括第一晶体管和第二晶体管；
    所述待驱动元件的阳极连接所述第一工作电压端；所述第一晶 体管的栅极连接所述驱动控制信号端，第一极连接所述待驱动元件的阴极，第二极连接所述驱动子电路；
    所述第二晶体管的栅极连接所述驱动控制信号端，第一极连接所述驱动子电路，第二极连接所述第二控制子电路。
  7. 根据权利要求2所述的驱动电路，其中，所述第二控制子电路还连接第一电压端；所述第二控制子电路包括第三晶体管、第四晶体管以及第一电容；
    所述第三晶体管的栅极连接所述第二扫描信号端，第一极连接所述第二数据信号端，第二极连接所述第四晶体管的栅极；
    所述第一电容的一端与所述第三晶体管的第二极相连接，所述第一电容的另一端连接所述第一电压端；
    所述待驱动元件的阴极连接所述第二工作电压端；所述第四晶体管的第一极连接所述第一控制子电路，第二极与所述待驱动元件的阳极相连接。
  8. 根据权利要求2所述的驱动电路，其中，所述第二控制子电路还连接第一电压端；所述第二控制子电路包括第三晶体管、第四晶体管以及第一电容；
    所述第三晶体管的栅极连接所述第二扫描信号端，第一极连接所述第二数据信号端，第二极连接所述第四晶体管的栅极；
    所述第一电容的一端与所述第三晶体管的第二极相连接，所述第一电容的另一端连接所述第一电压端；
    所述待驱动元件的阳极连接所述第一工作电压端，所述待驱动元件的阴极连接所述第一控制子电路；所述第四晶体管的第一极连接所述第一控制子电路，第二极与所述第二工作电压端相连接。
  9. 根据权利要求1所述的驱动电路，其中，所述驱动子电路还连接第二电压端，所述驱动子电路包括驱动晶体管；
    所述驱动晶体管的栅极连接所述第二电压端，第一极连接所述 写入子电路，第二极连接所述灰阶控制子电路。
  10. 根据权利要求3或4任一项所述的驱动电路，其中，所述驱动子电路还连接第二电压端，所述驱动子电路包括驱动晶体管和第二电容；
    所述驱动晶体管的栅极连接所述第二电容的一端，第一极连接所述写入子电路，第二极连接所述灰阶控制子电路；
    所述第二电容的另一端连接所述第二电压端。
  11. 根据权利要求1所述的驱动电路，其中，所述写入子电路包括第五晶体管；
    所述第五晶体管的栅极连接所述第一扫描信号端，第一极连接所述第一数据信号端，第二极与所述驱动子电路相连接。
  12. 根据权利要求3所述的驱动电路，其中，所述补偿子电路包括第六晶体管；
    所述第六晶体管的栅极连接所述第一扫描信号端，第一极和第二极均连接所述驱动子电路。
  13. 根据权利要求4所述的驱动电路，其中，所述复位子电路包括第七晶体管；
    所述第七晶体管的栅极连接所述复位控制信号端，第一极连接所述复位电压端，第二极与所述驱动子电路相连接。
  14. 根据权利要求1所述的驱动电路，其中，所述待驱动元件为微型发光二极管。
  15. 一种驱动电路，用于驱动待驱动元件工作，所述驱动电路包括第一晶体管至第七晶体管、第一电容、第二电容、驱动晶体管、复位控制信号端、驱动控制信号端、第一数据信号端、第二数据信号端、 第一扫描信号端、第二扫描信号端、第一工作电压端、第一电压端和第二电压端，其中，
    所述驱动控制信号端连接至所述第一晶体管的栅极和所述第二晶体管的栅极，
    所述第一数据信号端连接至所述第五晶体管的第一极，
    所述第二数据信号端连接至所述第三晶体管的第一极，
    所述第一扫描信号端连接至第五晶体管的栅极和第六晶体管的栅极，
    所述第二扫描信号端连接至所述第三晶体管的栅极，
    所述第一工作电压端连接至所述第一晶体管的第一极，
    所述第一电压端连接至所述第一电容的一端，
    所述第二电压端连接至所述第二电容的一端，
    所述复位控制信号端连接至所述第七晶体管的栅极，
    所述复位电压端连接至所述第七晶体管的第一极，
    所述第一晶体管的第二极、所述第五晶体管的第二极连接至所述驱动晶体管的第一极，
    所述第二电容的另一端、所述第六晶体管的第二极、所述第七晶体管的第二极连接至所述驱动晶体管的栅极，
    所述第二晶体管的第一极、所述第六晶体管的第一极连接至所述驱动晶体管的第二极，
    所述第二晶体管的第二极连接至所述第四晶体管的第一极，
    所述第一电容的另一端、所述第三晶体管的第二极连接至所述第四晶体管的栅极，
    所述第四晶体管的第二极连接至待驱动元件。
  16. 一种驱动电路，用于驱动待驱动元件工作，所述驱动电路包括第一晶体管至第七晶体管、第一电容、第二电容、驱动晶体管、复位控制信号端、驱动控制信号端、第一数据信号端、第二数据信号端、第一扫描信号端、第二扫描信号端、电源电压端、第一电压端和第二电压端，其中，
    所述驱动控制信号端连接至所述第一晶体管的栅极和所述第二晶体管的栅极，
    所述第一数据信号端连接至所述第五晶体管的第一极，
    所述第二数据信号端连接至所述第三晶体管的第一极，
    所述第一扫描信号端连接至第五晶体管的栅极和第六晶体管的栅极，
    所述第二扫描信号端连接至所述第三晶体管的栅极，
    所述电源电压端连接至所述第四晶体管的第二极，
    所述第一电压端连接至所述第一电容的一端，
    所述第二电压端连接至所述第二电容的一端，
    所述复位控制信号端连接至所述第七晶体管的栅极，
    所述复位电压端连接至所述第七晶体管的第一极，
    所述第一晶体管的第二极、所述第五晶体管的第二极连接至所述驱动晶体管的第一极，
    所述第二电容的另一端、所述第六晶体管的第二极、所述第七晶体管的第二极连接至所述驱动晶体管的栅极，
    所述第二晶体管的第一极、所述第六晶体管的第一极连接至所述驱动晶体管的第二极，
    所述第二晶体管的第二极连接至所述第四晶体管的第一极，
    所述第一电容的另一端、所述第三晶体管的第二极连接至所述第四晶体管的栅极，
    所述第一晶体管的第一极连接至所述待驱动元件。
  17. 一种显示装置，包括基板，所述显示基板的显示区域具有多个亚像素，至少一个亚像素内设置有如权利要求1-15任一项所述的驱动电路和待驱动元件，所述驱动电路用于向所述待驱动元件提供驱动信号。
  18. 一种用于对如权利要求1-16任一项所述的驱动电路的驱动方法，其中，在一图像帧内，驱动电路具有多个扫描周期；所述灰阶 控制子电路包括第一控制子电路和第二控制子电路；在一个所述扫描周期内，所述驱动电路驱动的方法包括：
    向第一扫描信号端提供第一扫描信号，向第一数据信号端提供第一数据电压，所述第一数据电压通过写入子电路写入至驱动子电路；
    向第二扫描信号端提供第二扫描信号，向第二数据信号端提供第二数据电压，以使得第二控制子电路在所述第二扫描信号和所述第二数据电压的控制下开启或关闭；
    向驱动控制信号端提供驱动控制信号，向所述第一工作电压端提供第一工作电压，所述第一工作电压通过第一控制子电路传输至驱动子电路，以使得待驱动元件在所述驱动控制信号、所述第一扫描信号、所述第二扫描信号以及所述第二数据电压的控制下基于所述第一数据电压和所述第一工作电压工作。
  19. 根据权利要求18所述的驱动方法，其中，所述方法还包括：
    在一个所述扫描周期内，所述第二扫描信号端输出有效信号的时间晚于所述第一扫描信号端输出有效信号的时间。
  20. 根据权利要求18所述的驱动方法，其中，所述驱动电路还包括复位子电路，所述向第一扫描信号端提供第一扫描信号，向第一数据信号端提供第一数据电压，所述第一数据电压通过写入子电路写入至驱动子电路之前，所述驱动电路驱动的方法还包括：
    向复位控制信号端提供复位控制信号，向复位电压端提供复位电压，所述复位电压通过所述复位子电路传输至所述驱动子电路。
  21. 根据权利要求18所述的驱动方法，其中，所述驱动子电路包括驱动晶体管和第二电容；所述驱动晶体管的栅极连接所述第二电容的一端，所述第二电容的另一端连接第二电压端，所述第二电压端与所述第一工作电压端输入的电压相同。
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CN108538241A (zh) 2018-09-14
KR20200057785A (ko) 2020-05-26
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