WO2020019170A1 - 一种终端及Type C接口防腐蚀方法 - Google Patents

一种终端及Type C接口防腐蚀方法 Download PDF

Info

Publication number
WO2020019170A1
WO2020019170A1 PCT/CN2018/096893 CN2018096893W WO2020019170A1 WO 2020019170 A1 WO2020019170 A1 WO 2020019170A1 CN 2018096893 W CN2018096893 W CN 2018096893W WO 2020019170 A1 WO2020019170 A1 WO 2020019170A1
Authority
WO
WIPO (PCT)
Prior art keywords
pin
interface
terminal
type
pull
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/096893
Other languages
English (en)
French (fr)
Inventor
陈建立
李辰龙
邱钰鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to CN201880078065.4A priority Critical patent/CN111433756B/zh
Priority to PCT/CN2018/096893 priority patent/WO2020019170A1/zh
Priority to EP18927724.7A priority patent/EP3812909B1/en
Priority to RU2021104296A priority patent/RU2764146C1/ru
Priority to JP2021503921A priority patent/JP7270719B2/ja
Priority to US17/261,961 priority patent/US11947481B2/en
Publication of WO2020019170A1 publication Critical patent/WO2020019170A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4081—Live connection to bus, e.g. hot-plugging
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0042—Universal serial bus [USB]

Definitions

  • the embodiments of the present application relate to the field of electronic science and technology, and in particular, to a method for preventing corrosion of a terminal and a Type C interface.
  • Type C (Type C) interface is a common universal serial bus (USB) interface. Because of its small size, high maximum data transmission speed, and no need to distinguish between front and back, it has gradually become the mainstream USB interface. One.
  • the Type C interface includes channel configuration (CC) pins.
  • One of its main functions is to identify the type of peripherals, determine the master-slave relationship, and configure the operating mode based on the master-slave relationship.
  • the working mode of the CC pin includes a dual role port (DRP) mode, an upstream port (UFP) mode, and a downstream port (DFP) mode.
  • DRP mode is a mode in which the UFP mode and the DPF mode are cyclically switched.
  • the Type C interface can identify peripherals in different interface modes such as UFP mode and DFP mode, and determine the master between the terminal and the peripherals. Slave relationship, so most Type C interfaces are in DRP mode when headless access.
  • the level of the CC pin is low.
  • the CC pin of the Type C interface is mostly in UFP mode.
  • DFP mode the level of the CC pin is high.
  • the terminal is the master device, the CC pin of the Type C interface is mostly in DFP mode.
  • the CC pin is set adjacent to the VBUS pin. Because the Type C interface has no peripheral connection, the effective level of the CC pin is high, and the VBUS pin is mostly low, which makes the CC pin and VBUS pin have a higher voltage difference. When liquid is used, the adjacent CC pin and VBUS pin are prone to electrochemical corrosion, which causes a short circuit between the CC pin and the VBUS pin, which causes a series of problems, such as the failure of the super fast charge function, and the terminal cannot enter. The terminal consumes too much power due to the standby state. Therefore, how to reduce the probability of electrochemical corrosion between the pins of USB Type C is one of the important research directions of Type C interface.
  • the embodiments of the present application provide a terminal and a Type C interface anti-corrosion method, which are used to reduce the probability of electrochemical corrosion between a CC pin and other pins in the Type C interface.
  • an embodiment of the present application provides a terminal including a processor, an interface chip, a motion sensor, and a first Type C interface; wherein the processor is connected to the motion sensor and the interface chip, respectively; the interface chip is connected to the processor and the processor, respectively.
  • the CC pin in the first Type C interface is connected; a motion sensor is used to monitor the motion state of the terminal; a processor is used to determine the motion state of the terminal from the mobile state to stand still according to the motion state of the terminal monitored by the motion sensor In the state, the control interface chip configures the CC pin of the first Type C interface to a low level mode.
  • the terminal configures the CC pin to a low level mode, which can reduce the effectiveness of the CC pin.
  • Level because the effective level of the CC pin is positively related to the probability of electrochemical corrosion between the CC pin and other pins, so reducing the effective level of the CC pin can reduce the CC pin and Chance of electrochemical corrosion between other pins.
  • the interface chip is also connected to the VBUS pin in the first Type C interface to obtain the VBUS voltage of the VBUS pin; the processor is further configured to: obtain the VBUS pin from the interface chip.
  • the voltage state wherein the voltage state of the VBUS pin is determined by the interface chip according to whether the VBUS voltage of the VBUS pin is lower than a preset threshold; it is determined that the motion state of the terminal changes from a moving state to a stationary state and the VBUS pin is at a low level
  • the control interface chip configures the CC pin of the first Type C interface to a low level mode.
  • the motion sensor has a certain failure rate.
  • the processor further determines that the VBUS pin is in a first voltage state that is lower than a preset threshold while determining that the motion state of the terminal has changed from a mobile state to a stationary state to ensure that the terminal is disconnected from the external device. After that, configure low mode for the CC pin. Because the terminal cannot recognize the external device in the low-level mode, ensure that the low-level mode is configured for the CC pin after the terminal is disconnected from the external device, which reduces the risk of the CC pin being incorrectly configured with the low-level mode. Prevent the terminal from recognizing the possibility of situations such as external devices.
  • the processor is further configured to: when it is determined that the terminal is connected to the external device through the first type C interface, the control interface chip configures the CC pin of the first Type C interface to an alternating high and low level mode .
  • the interface chip in the terminal can identify the external device connected through the first Type C interface, and then the data or power can be transmitted. Therefore, when the processor determines that the terminal is connected to the external device through the first Type C interface, the control interface chip configures the CC pin to a high-low level mode so that the interface chip can identify the external device.
  • the processor is specifically configured to: obtain the voltage status of the VBUS pin from the interface chip; wherein the voltage status of the VBUS pin is whether the interface chip has a VBUS voltage lower than a preset threshold according to the VBUS pin Certain; when it is determined that the VBUS pin is in a second voltage state that is not lower than a preset threshold, the control interface chip configures the CC pin of the first Type C interface to an alternating high-low level mode.
  • Some external devices with a Type C interface after establishing a physical connection with the terminal through the Type C interface, will increase the VBUS voltage on the VBUS pin in the Type C interface of the terminal.
  • the processor determines that the VBUS pin is at the VBUS voltage. When the second voltage state is lower than a preset threshold, it can be determined that the terminal is connected to an external device.
  • the processor is further configured to: when determining that the motion state of the terminal changes from a stationary state to a moving state, the control interface chip configures the CC pin of the first Type C interface to an alternating high and low level mode.
  • the change in the motion state reflects that the terminal is establishing a connection with an external device.
  • the terminal controls the interface chip to configure the CC pin of the first Type C interface to high and low levels. Alternate mode enables the terminal to establish a physical connection with an external device, and the interface chip in the terminal immediately recognizes the external device through the CC pin in the high-low alternate mode.
  • the processor is further configured to: when it is determined that the display screen of the terminal is bright, the control interface chip configures the CC pin of the first Type C interface to an alternating high and low level mode.
  • the above technical solution provides a way for the user to force the CC pin of the first Type C interface to be configured as an alternating high and low level mode. After connecting the terminal to an external device, if the interface chip in the terminal fails When the external device is identified, the user can light up the display and force the CC pin of the first Type C interface to be configured to alternate between high and low levels, so that the interface chip in the terminal can identify the external device.
  • the interface chip is further configured to cache the current working mode of the CC pin; the processor is further configured to: obtain the current working mode of the CC pin from the interface chip; and the current working mode of the CC pin
  • the stop control interface chip configures the CC pin as a low-level mode or an alternate high-low level; wherein the transmission mode is that the interface chip works according to the CC pin of the second Type C interface of the external device as Corresponding working mode of CC pin configuration.
  • the processor stops controlling the interface chip to configure the CC pin as a low-level mode or a high-low level alternate mode to avoid affecting Data or power transmission between the terminal and external equipment.
  • the interface chip configures the working mode of the CC pin according to a control signal provided by the processor;
  • the interface chip includes a control circuit, a pull-up power supply, a pull-up switch, a pull-up resistor, a pull-down switch, and a pull-down
  • One end of the pull-up resistor is connected to the pull-up power supply, the other end of the pull-up resistor is connected to the first electrode of the pull-up switch, and the second electrode of the pull-up switch is connected to the CC pin;
  • the other end of the pull-down resistor is connected to the first electrode of the pull-down switch, and the second electrode of the pull-down switch is connected to the CC pin;
  • the control circuit is respectively connected to the control electrode of the pull-up switch and the pull-down switch. Control the pull-up switch and pull-down switch on and off.
  • control circuit is specifically configured to: disconnect the pull-up switch and turn on the pull-down switch according to the first control signal.
  • the control circuit disconnects the pull-up switch according to the first control signal, and the CC pin no longer receives the high level provided by the pull-up power. At the same time, the pull-down switch is turned on, so that the CC pin is discharged to the ground, and the level on the CC pin gradually approaches 0, thereby achieving a low-level mode.
  • control circuit is specifically configured to turn off the pull-up switch and the pull-down switch according to the first control signal.
  • the control circuit disconnects the pull-up switch and the pull-down switch according to the first control signal, and the CC pin no longer receives the high level provided by the pull-up power supply. Although the control circuit turns off the pull-down switch at the same time, the CC pin can still discharge to ground through the leakage current of the pull-down switch, so that the level on the CC pin slowly approaches 0, thereby achieving a low-level mode.
  • the terminal further includes a first resistor; one end of the first resistor is connected to the CC pin, and the other end of the first resistor is grounded; the first resistor is used to provide a discharge path for the CC pin.
  • the first resistor can provide a path for the CC pin to discharge to ground, so that the level of the CC pin approaches 0 more quickly, thereby achieving Low mode.
  • control circuit is further configured to: periodically turn on the pull-up switch and the pull-down switch according to the second control signal.
  • the control circuit turns on the pull-up switch.
  • the CC pin is high; when the pull-up switch is turned off and the pull-down switch is turned on, the CC pin is low. Therefore, the control circuit can alternately turn on the pull-up switch and the pull-down switch according to the second control signal, so that the CC pin can be configured with a high-low level alternating mode.
  • control circuit is specifically configured to: keep the first switch and the second switch turned off for a preset time interval after alternately turning on the pull-up switch and the pull-down switch for several cycles, and preset the After the indirect interval, the pull-up switch and the pull-down switch are alternately turned on again for several cycles until the first command is received or the working mode of the CC pin in the second Type C interface is recognized.
  • the interface chip includes a power transmission PD chip, or a CC control controller chip.
  • the motion sensor includes an acceleration sensor Gsensor, and / or, a gyroscope, and / or a gravity sensor.
  • an embodiment of the present application provides a Type C interface anti-corrosion method.
  • the method is applied to a processor in a terminal.
  • the terminal further includes an interface chip, a first Type C interface, and a motion sensor.
  • the interface chip is connected to the motion sensor, and the interface chip is respectively connected to the processor and the first Type C interface.
  • the Type C interface anti-corrosion method includes: according to the motion state of the terminal monitored by the motion sensor, determining the motion state of the terminal is determined by the movement state When entering the static state, the control interface chip configures the CC pin of the first Type C interface to a low level mode.
  • the method further includes: obtaining a voltage state of the VBUS pin from the interface chip; wherein the voltage state of the VBUS pin is determined by the interface chip according to whether the VBUS voltage of the VBUS pin is lower than a preset threshold ; When it is determined that the motion state of the terminal is changed from a mobile state to a stationary state and the VBUS pin is at a first voltage state lower than a preset threshold, the control interface chip configures the CC pin of the first Type C interface to a low level mode .
  • the method further includes: when it is determined that the terminal is connected to the external device through the first Type C interface, the control interface chip configures the CC pin of the first Type C interface to an alternating high and low level mode.
  • determining that the terminal is connected to the external device through the first Type C interface includes: obtaining the voltage status of the VBUS pin from the interface chip; wherein the voltage status of the VBUS pin is based on the VBUS pin of the interface chip It is determined whether the VBUS voltage is lower than a preset threshold. When it is determined that the VBUS pin is in a second voltage state that is not lower than the preset threshold, the control interface chip configures the CC pin of the first Type C interface to alternate high and low levels. mode.
  • the method further includes: when it is determined that the motion state of the terminal changes from a stationary state to a moving state, the control interface chip configures the CC pin of the first Type C interface to an alternating high and low level mode.
  • the method further includes: when it is determined that the display screen of the terminal is bright, the control interface chip configures the CC pin of the first Type C interface to an alternating high and low level mode.
  • the interface chip is also used to cache the current working mode of the CC pin; the method further includes: obtaining the current working mode of the CC pin from the interface chip; the current working mode of the CC pin is transmission In the mode, the stop control interface chip configures the CC pin as a low-level mode or a high-low level alternate mode.
  • the transmission mode is that the interface chip is a CC pin according to the working mode of the CC pin in the second Type C interface of the external device. The corresponding working mode of the pin configuration.
  • FIG. 1 is a schematic structural diagram of a feasible terminal according to an embodiment of the present application.
  • FIGS. 2a to 2d are schematic diagrams of a connection stage between a terminal and an external device according to an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of a feasible terminal according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a feasible terminal according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an interface chip according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of a feasible terminal according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a level signal according to an embodiment of the present application.
  • FIG. 8 is a schematic flowchart of a Type C interface anticorrosion method according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a Type C interface anti-corrosion device according to an embodiment of the present application.
  • the embodiment of the present application provides a terminal, which may be a terminal suitable for a Type C interface such as a laptop computer, a smart phone, a tablet computer, a personal digital assistant, a digital video camera, and a smart home.
  • the terminal 100 in the embodiment of the present application may be a mobile phone.
  • the illustrated terminal 100 is only an example of the terminal provided in the embodiment of the present application, and the terminal 100 may have more or fewer components than those shown in the figure, and two or more may be combined Multiple components, or may have different component configurations.
  • the various components shown in the figures can be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and / or application specific integrated circuits.
  • the terminal 100 may specifically include: one or more processors 101, radio frequency (RF) circuits 102, memory 103, touch screen 104, Bluetooth device 105, one or more sensors 106, Wi-Fi The device 107, the positioning device 108, the audio circuit 109, the peripheral interface 110, and the power supply device 111 and other components. These components can communicate via one or more communication buses or signal lines (not shown in FIG. 1). Those skilled in the art can understand that the hardware structure shown in FIG. 1 does not constitute a limitation on the terminal 100.
  • the terminal 100 may include more or fewer components than shown in the figure, or combine certain components, or arrange different components. .
  • the processor 101 is a control center of the terminal 100, and uses various interfaces and lines to connect various parts of the terminal 100, and runs or executes an application program (Application, App) stored in the memory 103, and calls the stored program in the memory 103. Data and instructions perform various functions of the terminal 100 and process data.
  • the processor 101 may include one or more processing units; the processor 101 may further integrate an application processor and a modem processor; wherein the application processor mainly processes an operating system, a user interface, and an application program, etc.
  • the modem processor mainly handles wireless communication. It can be understood that the foregoing modem processor may not be integrated into the processor 101.
  • the processor 101 may be a Kirin 960 chip manufactured by Huawei Technologies Co., Ltd.
  • the processor also includes a sensor hub (sensorhub) for managing the sensor data of the sensor 106 and the touchpad 104-1, and can perform low-power consumption work when the processor 101 is sleeping.
  • the radio frequency circuit 102 can be used for receiving and sending wireless signals during the process of transmitting and receiving information or during a call. Specifically, the radio frequency circuit 102 may receive the downlink data of the base station and process it to the processor 101; in addition, send the uplink data to the base station. Generally, the radio frequency circuit includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, and the like. In addition, the radio frequency circuit 102 can also communicate with other devices through wireless communication. The wireless communication may use any communication standard or protocol, including but not limited to a global mobile communication system, a general packet wireless service, code division multiple access, wideband code division multiple access, long-term evolution, email, short message service, and the like.
  • the memory 103 is configured to store application programs and data, and the processor 101 executes various functions and data processing of the terminal 100 by running the application programs and data stored in the memory 103.
  • the memory 103 mainly includes a storage program area and a storage data area, where the storage program area can store an operating system and at least one application required by a function (such as a sound playback function, an image playback function, etc.); the storage data area can store data according to the terminal used Data created at 100 (such as audio data, phone book, etc.).
  • the memory 103 may include a high-speed random access memory, and may also include a non-volatile memory, such as a magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices.
  • the memory 103 can store various operating systems, such as those developed by Apple Inc. Operating system, developed by Google Operating system, etc. Exemplarily, the storage 103 stores application programs related to the embodiments of the present application, such as a Taskcard store, Twitter, a phone book, Weibo, and the like.
  • the touch screen 104 may include a touch pad 104-1 and a display 104-2.
  • the touchpad 104-1 may collect touch events on or near the user of the terminal 100 (for example, the user uses a finger, a stylus, or any suitable object on the touchpad 104-1 or the touchpad 104 Near -1), and send the collected touch information to other devices such as the processor 101.
  • the display (also referred to as a display screen) 104-2 can be used to display information input by the user or information provided to the user and various menus of the terminal 100, including a display driving chip for driving under the control of the processor 101
  • the diode and LCD screen work in the display.
  • the terminal 100 may further include at least one sensor 106, such as a light sensor, a motion sensor, and other sensors.
  • the motion sensor may include an acceleration sensor (Gsensor), and the acceleration sensor may monitor the magnitude of acceleration in various directions (generally three axes), so that the motion status of the terminal 100 may be monitored.
  • the motion sensor in addition to determining whether the terminal has a displacement, can also implement functions related to identifying the terminal ’s posture and vibration recognition based on the magnitude and direction of the monitored gravity.
  • the motion sensor may further include a gyroscope, a gravity sensor, etc. to increase the types of motion states that can be monitored.
  • the sensor 106 includes at least a motion sensor. Therefore, in the embodiment of the present application, the motion sensor is identified by reference numeral 106.
  • the Wi-Fi device 107 is used to provide the terminal 100 with network access that complies with Wi-Fi related standard protocols.
  • the terminal 100 can access the Wi-Fi access point through the Wi-Fi device 107 to help users send and receive email, Browse the web and access streaming media, etc., it provides users with wireless broadband Internet access.
  • the positioning device 108 is configured to provide a geographic location for the terminal 100. It can be understood that the positioning device 108 may specifically be a receiver of a positioning system such as a global positioning system (GPS) or a Beidou satellite navigation system. After receiving the geographic position sent by the positioning system, the positioning device 108 sends the information to the processor 101 for processing, or sends the information to the memory 103 for storage.
  • GPS global positioning system
  • Beidou satellite navigation system After receiving the geographic position sent by the positioning system, the positioning device 108 sends the information to the processor 101 for processing, or sends the information to the memory 103 for storage.
  • the audio circuit 109, the speaker 113, and the microphone 114 may provide an audio interface between the user and the terminal 100.
  • the audio circuit 109 may transmit the received electrical data converted electrical signal to the speaker 113, which is converted into a sound signal by the speaker 113.
  • the microphone 114 converts the collected sound signal into an electrical signal, and the audio circuit 109 After receiving, it is converted into audio data, and then the audio data is output to the RF circuit 102 for sending to, for example, a terminal, or the audio data is output to the memory 103 for further processing.
  • the peripheral interface 110 is used to provide various interfaces for external devices (such as a keyboard, a mouse, an external display, an external memory, a user identification module card, etc.). For example, it is connected to a mouse through a universal serial bus interface, and connected to a subscriber identity module (SIM) card provided by a telecommunications operator through a metal contact on the card slot of the subscriber identity module.
  • SIM subscriber identity module
  • the peripheral interface 110 may be used to couple the above-mentioned input / output external devices to the processor 101 and the memory 103.
  • the peripheral interface 110 includes a physical interface 110-1 and an interface chip 110-2.
  • the peripheral interface 110 is used to establish a physical connection with an external device, and the interface chip 110-2 is used to implement a suitable connection between the terminal 100 and the external device. Configuration, so that the data transmitted through the physical interface 110-1 conforms to the provisions of the interface protocol.
  • the physical interface 110-1 may be a Type C interface. Therefore, in the embodiment of the present application, the Type C interface is identified by reference numeral 110-1.
  • the interface chip 110-2 may be a power delivery (PD) chip or a CC controller chip.
  • the interface chip 110-2 is used to identify an external device and perform adaptation between the terminal 100 and the external device. To make the data passed through the Type C interface comply with the requirements of the Type C protocol.
  • the terminal 100 may further include a power supply device 111 (such as a battery and a power management chip) for supplying power to various components.
  • the battery may be logically connected to the processor 101 through the power management chip, so that the power supply device 111 manages charging, discharging, and power management. Consumption management and other functions.
  • the terminal 100 may further include a camera, for example, a front camera and a rear camera.
  • the front camera may be used to capture facial feature information, and the processor 101 may perform facial analysis on the facial feature information. Identify, and then carry out subsequent processing.
  • the terminal 100 may further include a flash, a micro-projection device, a near field communication (NFC) device, and the like, and details are not described herein.
  • NFC near field communication
  • the processor 101 may obtain the motion status of the terminal through the motion sensor 106, so as to control the interface chip 110-2 in the peripheral interface 110 to the physical interface 110-1 (Type C interface 110-1) according to the motion status of the terminal. Configure the work mode.
  • connection phase between the terminal and the external device during use is roughly divided into the following four for explanation, including: not connected to the external device, being connected to the external device, and connected to the external device Disconnecting from external devices.
  • the terminal 100 is in a stage of not being connected to an external device.
  • the terminal 100 in this stage has a Type C interface 110-1 that is not connected to the external device, and does not attempt to connect to the external device.
  • the terminal 100 is in the stage of establishing a connection with an external device 200.
  • this stage also includes a stage in which the terminal 100 and the external device 200 establish a physical connection, and then perform a mode identification and a transmission mode configuration through the Type C interfaces 110-1 and 201.
  • the terminal 100 is in a stage of connecting with the external device 200, and data or power is transmitted between the terminal 100 and the external device 200 according to a transmission mode configured when the connection is established.
  • FIG. 2c the terminal 100 is in a stage of connecting with the external device 200, and data or power is transmitted between the terminal 100 and the external device 200 according to a transmission mode configured when the connection is established.
  • the terminal 100 is in a stage of being disconnected from the external device 200. After the stage shown in FIG. 2d, the terminal 100 returns to the stage where the external device 200 is not connected as shown in FIG. 2a. It should be understood that there is no strict division between the stages shown in FIG. 2a to FIG. 2d.
  • the four stages provided in the embodiment of the present application are only for explaining the technical solution provided by the embodiment of the present application.
  • Type C interface 110-1 of the terminal 100 may be in the form of a plug or a socket.
  • the Type C interface 110-1 of the terminal 100 may be directly connected to the Type C interface of an external device.
  • the external device may be An external device with a Type C interface can also be an external device that is connected to the Type C data cable and connected to the terminal through the Type C interface on the Type C data cable.
  • FIG. 3 is a schematic structural diagram of a feasible terminal provided by an embodiment of the present application.
  • the terminal 100 includes a processor 101, an interface chip 110-2, a motion sensor 106, and a Type C interface 110-1.
  • the processor 101 is connected to the interface chip 110-2 and the motion sensor 106 respectively.
  • the interface chip 110-2 is connected to the processor 101 and also connected to the Type C interface 110-1.
  • the motion sensor 106 can monitor the motion status of the terminal 100, and the processor 101 can, according to the motion status monitored by the motion sensor 106, determine the motion status of the terminal 100 from the mobile status to the stationary status, and control the interface chip 110-2 to change the Type C interface 110
  • the CC pin of -1 is configured in low mode, which reduces the active level of the CC pin. Since the probability of electrochemical corrosion between pins is positively related to the voltage difference between the pins, reducing the effective level of the CC pin can reduce the CC pin and other pins in the Type 110C interface 110-1 Chance of electrochemical corrosion.
  • the terminal 100 when the terminal 100 is in the stage of disconnecting from the external device 200 shown in FIG. 1d, the terminal 100 needs to move a distance in the direction shown by the arrow in the figure before the two Type C interfaces (110-1 And 201) to disconnect the physical connection. Therefore, the motion state of the terminal 100 monitored by the motion sensor 106 at this time is a moving state.
  • the terminal After the stage shown in FIG. 1d, that is, after the Type C interface 201 of the external device 200 is separated from the Type C interface 110-1 of the terminal 100, the terminal enters a phase not connected to the external device shown in FIG. 1a. In the stage shown in FIG. 1a, the terminal 100 often has a stationary state.
  • the movement state of the terminal 100 monitored by the motion sensor 106 is a stationary state. Therefore, when the processor 101 determines that the movement state of the terminal 100 has changed from a moving state to a stationary state, it can be considered that the terminal 100 has entered a stage shown in FIG. 1a that is neither connected to nor connected with an external device. At this stage, In the process, the processor 101 controls the interface chip 110-2 to configure the CC pin in the Type C interface 110-1 to a low level mode, which does not affect the use of the Type C interface 110-1, and can reduce the Type C interface 110- Chance of electrochemical corrosion between CC pin and other pins in 1.
  • the processor 101 may acquire the motion state of the terminal 100 from the motion sensor 106 through an electrical connection with the motion sensor 106.
  • the motion sensor 106 and the processor 101 may include connections such as an integrated circuit (I2C), an interrupt signal line (Interrupt, INT), and the like.
  • I2C integrated circuit
  • INT interrupt signal line
  • FIG. 4 the motion sensor 106 and the processor 101 are connected through an I2C.
  • the I2C connection includes a serial clock line (SCL) and a serial data line (SDA).
  • the processor 101 may periodically obtain the motion sensor 106 through an I2C connection with the motion sensor 106.
  • the motion state of the terminal 100 is monitored to determine a change in the motion state of the terminal 100.
  • the processor 101 and the motion sensor 106 further include an INT connection. After the motion sensor 106 detects a change in the motion state of the terminal 100, the motion sensor 106 sends an interrupt signal to the processor 101 through an INT connection with the processor 101. The interrupt signal can wake up the processor 101. After receiving the interrupt signal, the processor 101 obtains the motion status of the terminal 100 from the motion sensor 106 through the I2C connection.
  • the processor 101 may determine that the movement state of the terminal 100 has changed from a stationary state to a moving state; the movement state of the terminal 100 obtained from the motion sensor 106 is a stationary state At this time, the processor 101 may determine that the motion state of the terminal 100 is changed from a moving state to a stationary state. In this implementation manner, the processor 101 does not need to frequently obtain the motion state of the terminal 100 from the motion sensor 106, which is beneficial to reducing the power consumption of the terminal 100.
  • the processor 101 is specifically connected to the motion sensor 106 through its internal sensor hub, and the sensorhub receives the interrupt signal sent by the motion sensor 106 through the INT connection, and the sensorhub uses the I2C connection to remove the motion from the motion sensor 106.
  • the sensor 106 acquires the motion status of the terminal 100, so that when the motion status of the terminal 100 changes, the interrupt signal sent by the motion sensor 106 will only wake up the sensorhub in the processor 101, and will not wake up the processor 101 as a whole, which is beneficial
  • the power consumption of the terminal 100 is further reduced.
  • the processor 101 may also be connected to the interface chip 110-2 through a sensorhub to reduce the power consumption of the terminal 100.
  • the processor 101 may configure the working mode of the CC pin in the Type C interface 110-1 according to the motion state control interface chip 110-2 of the terminal 100 monitored by the motion sensor 106. Specifically, the processor 101 may generate a control signal according to the motion state of the terminal 100, and control the interface chip 110-2 to configure the working mode of the CC pin in the TypeC interface 110-1 through the control signal. In the terminal 100 shown in FIG. 4, the processor 101 and the interface chip 110-2 may be connected through I2C. The processor 101 may send a control signal to the interface chip 110-2 through the I2C connection (SDA and SCL), so as to control the interface chip 110-2 to configure the working mode of the CC pin in the Type C interface 110-1.
  • I2C connection SDA and SCL
  • the processor 101 controls the interface chip 110-2 to switch the terminal 100 in a non-stationary state.
  • the CC pin in the Type C interface 110-1 is configured to a low level mode, which will cause the interface chip 110-2 in the terminal 100 to fail to recognize an OTG (on-the-go) type external device. This is because in the TypeC interface of an OTG type external device, the working mode of the CC pin is fixed to UFP mode. Only when the CC pin is in DRP mode or DFP mode in the Type C interface 110-1, the interface chip 110-2 In order to be able to identify the external device.
  • the processor 101 can further determine whether the VBUS voltage of the VBUS pin in the Type C interface 110-1 is lower than Preset threshold.
  • the interface chip 110-2 is also connected to the VBUS pin in the Type C interface 110-1.
  • the interface chip 110-2 can obtain the VBUS voltage on the VBUS pin, and according to the VBUS voltage and a preset threshold The relative size relationship determines the voltage state of the VBUS pin.
  • the voltage state of the VBUS pin includes a first voltage state where the VBUS voltage is lower than a preset threshold and a second voltage state where the VBUS voltage is not lower than a preset threshold.
  • the processor 101 determines that the terminal 100 is in a stationary state from the mobile state, it can also obtain the current voltage state of the VBUS pin through the I2C connection with the interface chip 110-2, and when it is determined that the VBUS pin is in the first voltage state
  • the working mode of the CC pin in the Type C interface 110-1 is configured to a low level mode.
  • the VBUS voltage of the VBUS pin in the Type C interface 110-1 of the terminal 100 is low level.
  • the VBUS pin is in the first voltage state.
  • the movement state of the terminal 100 is changed from a moving state to a stationary state, and the VBUS voltage state of the VBUS pin is a first voltage state that is lower than a preset threshold value, it means that the terminal 100 is now shown in FIG. 1a to a large extent.
  • the processor 101 controls the interface chip 110-2 to configure the CC pin in the Type C interface 110-1 to a low level mode, which is helpful to reduce the The low-level configuration of the pin causes the interface chip 110-2 in the terminal 100 to fail to recognize the possibility that the situation of the external device occurs.
  • the processor 101 may control the interface chip 110-2 to configure the working mode of the CC pin in the Type C interface 110-1.
  • the interface chip 110-2 is connected to the Type C interface 110-1, and can receive the control signal sent by the processor 101, and configure the working mode of the Type C interface 110-1 according to the received control signal.
  • the interface chip 110-2 can be connected to multiple pins in the Type C interface 110-1, including two CC pins in the Type C interface 110-1, between CC1 and CC2. After receiving the control signal, the interface chip 110-2 can configure the working modes of CC1 and CC2 respectively according to the control signal.
  • FIG. 5 is a schematic structural diagram of an interface chip according to an embodiment of the present application.
  • the interface chip 110-2 includes a control circuit 1031, a pull-up switch 1032, a pull-up resistor 1033, a pull-up power supply 1034, Pull-down resistor 1035 and pull-down switch 1036.
  • One end of the pull-up resistor 1033 is connected to the pull-up power supply 1034.
  • the other end of the pull-up resistor 1033 is connected to the first electrode of the pull-up switch 1032.
  • the second electrode of the pull-up switch 1032 is connected to the CC of the Type C interface 110-1.
  • One end of the pull-down resistor 1035 is grounded, the other end of the pull-down resistor 1035 is connected to the first electrode of the pull-down switch 1036, and the second electrode of the pull-down switch 1036 is connected to the CC pin of the Type C interface 110-1.
  • the control circuit 1031 is connected to the control electrodes of the pull-up switch 1032 and the pull-down switch 1036, respectively, and is used to control the pull-up switch 1032 and the pull-down switch 1036 to be turned on and off according to a control signal sent by the processor 101.
  • the pull-up power supply is used to provide a high level for the CC pin, which can be a DC / DC (DC / DC) converter in the terminal 100, or a low dropout linear regulator (low dropout regulator). , LDO).
  • a DC / DC (DC / DC) converter in the terminal 100 or a low dropout linear regulator (low dropout regulator). , LDO).
  • the working mode configured by the interface chip 110-2 for the CC pin corresponds to the DFP mode; when the pull-up switch 1032 is turned off, the pull-down switch 1036 is turned on At the time, the working mode configured by the interface chip 110-2 for the CC pin corresponds to the UFP mode; when the pull-up switch 1032 and the pull-down switch 1036 are alternately turned on periodically, for example, in a period T, the pull-up switch is in the first t1 time interval 1032 is turned off, and the pull-down switch 1036 is turned on.
  • the pull-up switch 1032 is turned on, and the pull-down switch 1036 is turned off.
  • the interface chip 110-2 is configured for the CC pin working mode. Corresponds to the DRP mode.
  • the processor 101 may control the interface chip 110-2 to configure the CC pin in the Type C interface 110-1 to a low level mode by sending the first control signal to the interface chip 110-2.
  • the interface chip 110-2 can configure a low-level mode for the CC pin of the Type C interface 110-1 in at least the following two ways.
  • the control circuit 1031 turns off the pull-up switch 1032 and turns on the pull-down switch 1036 according to the first control signal.
  • the CC pin stops receiving the high level from the pull-up power supply 1034, and discharges to ground through the pull-down switch 1036 and the pull-down resistor 1035, so that the level on the CC pin gradually approaches 0, thereby achieving the low-level mode.
  • the working mode of the CC pin of the Type C interface 110-1 corresponds to the UFP mode specified in the Type C protocol.
  • the control circuit 1031 turns off the pull-up switch 1032 and the pull-down switch 1036 at the same time according to the first control signal, the CC pin stops receiving the high level from the pull-up power supply 1034, and due to the pull-down switch 1036 The existence of the medium leakage current can still gradually discharge to ground, so that the level on the CC pin slowly goes to 0.
  • the terminal 100 further includes a first resistor 115; one end of the first resistor 115 is connected to the CC pin, and the other end of the first resistor 115 is grounded.
  • the first resistor 115 can provide a path for the CC pin to discharge to ground when the control circuit 1031 turns off the pull-up switch 1032 and the pull-down switch 1036 at the same time.
  • the CC pin can be discharged to ground through the first resistor 115, so that the level on the CC pin approaches 0 faster, so that the CC pin can be configured to the low-level mode more quickly.
  • the resistance of the first resistor 115 in order to reduce the influence of the first resistor 115 on the level of the CC pin in the DFP mode and the UFP mode, the resistance of the first resistor 115 should be much larger than the pull-up resistor 1033. And the resistance value of the pull-down resistor 1035, so that in the UFP mode and the DFP mode, the ground path formed by the first resistor 115 can be approximated to an open circuit. Moreover, the resistance value of the pull-down resistor 1035 is 5.1 k. In order not to affect the accuracy of the pull-down switch 1036, the resistance of the first resistor 115 may be 500 k or 1 Mohm.
  • the working mode of the CC pin can be configured as a low-level working mode, thereby reducing the effective level of the CC pin before the terminal 100 is next connected to an external device, thereby reducing the CC pin. Chance of electrochemical corrosion with other pins.
  • the control interface chip 110-2 configures the CC pin of the Type C interface 110-1 to a low-level mode.
  • the interface chip 110-2 can pass the CC pin in the high-low level alternate mode Identify the CC pin in the Type C interface 201 of the external device 200. If the CC pin in the Type C interface 110-1 of the terminal 100 is still in the low level mode in the stage shown in FIG.
  • the interface chip 110-2 will not be able to identify the CC pin in the Type C interface 201 of the external device 200. Foot working mode. Based on this, the embodiments of the present application provide at least the following three feasible implementation manners to ensure that the interface chip 110-2 can recognize the working mode of the CC pin in the Type C interface 201 at the stage shown in FIG. 1b.
  • the control interface chip 110-2 controls the Type C interface 110-1
  • the CC pin is configured for high-low alternating mode.
  • the terminal 100 needs to move a certain distance in the direction of the arrow in the figure before it can establish a physical connection with the external device 200. Therefore, when the terminal 100 enters the mobile state from a stationary state, it means that the terminal 100 may Entered the stage shown in FIG. 1b.
  • the processor 101 controls the interface chip 110-2 to configure the CC pin in an alternating high and low level mode, thereby ensuring that when the terminal 100 is in the stage of FIG. 1b, the The interface chip 110-2 can identify the working mode of the CC pin in the Type C interface 201 of the external device 200 after the terminal 100 establishes a physical connection with the external device 200.
  • the processor 101 determines that the terminal 100 is connected to the external device 200 through the Type C interface 110-1, the processor 101 controls the interface chip 110-2 to configure the CC pins of the Type C interface 110-1 High and low level alternate mode.
  • the processor 101 may obtain the current voltage state of the VBUS pin from the interface chip 110-2, and control the interface chip 110-2 when it is determined that the VBUS pin is in a second voltage state where the VBUS voltage is not lower than a preset threshold.
  • the CC pin in the Type C interface 110-1 is configured to a high-low alternating mode.
  • the interface chip 110-2 can also send an interrupt signal to the processor 101 when the voltage state of the VBUS pin changes from the first voltage state to the second voltage state. After receiving the interrupt signal, the processor 101 can It is determined that the terminal 100 has established a physical connection with the external device 200, so that the control interface chip 110-2 configures the CC pin of the Type C interface 110-1 to an alternating high-low level mode.
  • the type of the external device 200 is not fixed.
  • it can be divided into at least the following two types: 1.
  • the terminal establishes a physical connection with the first type of external device 200
  • the VBUS pin of the Type C interface 110-1 The VBUS pin of the Type C interface 110-1 will still be in the first voltage state after the physical connection between the terminal 100 and the second type of external device 200 is established.
  • the VBUS pin in the Type C interface 110-1 of the terminal 100 will change from the first voltage state to the second voltage state.
  • the second implementation manner is more suitable for the case where the terminal 100 is connected to the first type of external device 200, and can be used in combination with the first feasible implementation manner in specific implementation.
  • the control interface chip 110-2 configures the CC pin of the Type C interface 110-1 to an alternating high and low level mode.
  • the terminal 100 further includes a display driving chip 104-3; the display driving chip 104-3 is connected to the processor 101 and is used to brighten the screen. At this time, an interrupt signal is sent to the processor 101, and the interrupt signal can wake up the processor 101. After receiving the interrupt signal sent by the display driver chip 104-3, the processor 101 controls the interface chip 110-2 to configure the CC pin in the Type C interface 110-1 to an alternating high and low level mode. Obviously, in a specific implementation, the display driving chip 104-3 may also be connected to the sensorhub of the processor 101 to reduce the power consumption of the terminal 100.
  • the third feasible implementation method provides a way for the end user to force the CC pin of the Type C interface 110-1 to be in a high-low alternating mode.
  • the interface chip 110-2 of the terminal 100 fails to recognize the Type C interface 201 of the external device 200.
  • the user can manually configure the CC pin of the Type C interface 110-1 to alternate between high and low levels by manually lighting the display screen.
  • the interface chip 110-2 can identify the Type C interface 201 of the external device 200.
  • the processor 101 is configured with different priorities for the three implementations.
  • the interrupt signal provided by the display driver chip 104-3 has the highest priority, and the priority of the motion status of the terminal 100 provided by the motion sensor 106 is the second.
  • the voltage status of the VBUS pin provided by the interface chip 110-2 has the lowest priority.
  • the processor 101 After receiving the interrupt signal sent by the display driver chip 104-3, the processor 101 immediately controls the interface chip 110-2 regardless of the voltage state of the VBUS pin and the movement state of the terminal 100 at this time.
  • the CC pin in the Type C interface 110-1 is configured to a high-low alternating mode.
  • the processor 101 may control the interface chip 110-2 to configure the CC pin in the Type C interface 110-1 to an alternating high and low level mode.
  • the processor 101 may provide the interface chip 110 to the interface chip 110. -2 sends a second control signal to control the interface chip 110-2 to configure the CC pin in the Type C interface 110-1 to an alternating high and low level mode.
  • the control circuit 1031 After the interface chip 110-2 receives the second control signal, the control circuit 1031 periodically turns on the pull-up switch 1032 and the pull-down switch 1036 according to the second control signal.
  • the working mode of the pin corresponds to the DRP mode specified by the Type C protocol.
  • the level signal provided by the interface chip 110-2 for the CC pin can be shown as signal a in FIG. 7, where T is a DRP period, t1 is a low-level duration in a DRP period, and t2 is High duration in one DRP cycle.
  • T can be 65ms
  • t1 can be 50ms
  • t2 can be 15ms.
  • the CC pin is low, and the interface chip 110-2 can recognize the external device in DFP mode through the CC pin.
  • the CC pin is high and the interface chip 110-2 can An external device in UFP mode is identified through the CC pin.
  • the interface chip 110-2 can recognize that the CC pin is in a different working mode through the CC pin in the high-low alternating mode. External devices.
  • the control circuit 1031 alternately turns on the pull-up switches 1032 and Within a preset time interval after several cycles of the pull-down switch 1036, the pull-up switch 1032 is turned off, the pull-down switch 1036 is turned on, and after the preset time interval, the pull-up switch 1032 and the pull-down switch 1036 are alternately turned on again for several cycles.
  • the control circuit 1031 turns on the pull-up switch 1032 and the pull-down switch 1036 alternately, and then turns off the pull-up switch at the time interval of t3, and turns on the pull-down switch, so that the CC pin Keep low level during t3 time interval, generally t3 can be 500ms.
  • the pull-up switch 1032 and the pull-down switch 1036 are repeatedly turned on and off alternately.
  • the Type C protocol specifies the duty cycle and DRP cycle length of the pull-down switch 1036 in the DRP mode. If the low level in the time interval t3 in Figure 7 is configured by the CC pin in UFP mode (that is, the pull-down is turned on) The implementation of the switch 1036 and disconnecting the pull-up switch 1032) will cause the duty cycle of the pull-down switch 1036 to exceed the duty cycle of the pull-down switch in the DRP mode specified in the Type C protocol.
  • the interface chip 110-2 achieves a low level by disconnecting the pull-up switch 1032 and the pull-down switch 1036 within the time interval of t3, and the first resistor 115 is provided for the CC pin Discharge path to ground.
  • the interface chip 110-2 disconnects the pull-up switch 1032 and the pull-down switch 1036 at the same time, the CC pin is not configured in the DRP mode, so the implementation method described above does not violate the provisions of the Type C protocol.
  • the low level in the time interval t1 can also be achieved by turning off the pull-up switch 1032 and the pull-down switch 1036.
  • the Type C interface of the external device 200 can be identified by monitoring the voltage change of the CC pin in the high-low alternating mode.
  • the working mode of the CC pin in 201 can further configure the CC pin of the Type C interface 110-1 to the corresponding transmission mode.
  • the transmission mode configured for the CC pin of the Type C interface 110-1 is the UFP mode
  • the transmission mode configured for the CC pin of the Type C interface 110-1 is DFP mode
  • the processor 101 may also obtain the current working mode of the CC pin of the Type C interface 110-1 from the interface chip 110-2; when the current working mode of the CC pin is the transmission mode, The stop control interface chip 110-2 configures the CC pin of the Type C interface 110-1 to a low-level mode or a high-low level alternate mode.
  • the processor 101 may periodically obtain the current working mode of the CC pin of the Type C interface 110-1 from the interface chip 110-2, or configure the Type C interface 110-1 of the control interface chip 110-2 After the working mode of the CC pin, the current working mode of the CC pin is obtained. If the CC pin is currently in the transmission mode, the control of the interface chip is not performed. Obviously, the interface chip 110-2 can also refuse to execute the control signal of the processor 101 when the working mode of the CC pin is the above-mentioned transmission mode, and it is also possible to avoid changing the current transmission mode of the CC pin.
  • FIG. 8 is a schematic flowchart of a Type C interface anticorrosion method provided by an embodiment of the present application. As shown in FIG. 8, it mainly includes:
  • control interface chip 110-2 sets the CC pin of the Type C interface 110-1 to low Level mode.
  • the method further includes:
  • the voltage status of the VBUS pin is determined by the interface chip 110-2 according to whether the VBUS voltage of the VBUS pin is lower than a preset threshold;
  • control interface chip 110-2 configures the CC pin of the Type C interface 110-1 to be low Level mode.
  • the method further includes:
  • the control interface chip 110-2 configures the CC pin of the first Type C interface to a high-low level alternating mode.
  • determining that the terminal 100 is connected to an external device through the Type 110C interface 110-1 includes:
  • the voltage status of the VBUS pin is determined by the interface chip 110-2 according to whether the VBUS voltage of the VBUS pin is lower than a preset threshold;
  • control interface chip 110-2 configures the CC pin of the Type C interface 110-1 to an alternating high-low level mode.
  • the method further includes:
  • control interface chip 110-2 configures the CC pin of the Type C interface 110-1 to an alternating high and low level mode.
  • the method further includes:
  • control interface chip 110-2 configures the CC pin of the Type C interface 110-1 to an alternating high and low level mode.
  • the interface chip 110-2 is also used to cache the current working mode of the CC pin; the method further includes:
  • the transmission mode When the current working mode of the CC pin is the transmission mode, stop controlling the interface chip 110-2 to configure the CC pin as a low-level mode or an alternating high-low level; wherein, the transmission mode is the interface chip 110-2 according to an external device
  • the working mode of the CC pin in the Type C interface is the corresponding working mode of the CC pin configuration in the Type C interface 110-1.
  • Type C interface anti-corrosion method shown in FIG. 8 can be regarded as a method executed by the processor 101 in the terminal shown in FIG. 3.
  • the Type C interface anti-corrosion method shown in FIG. 8 please refer to the related description in the terminal shown in FIG. 3.
  • the embodiment of the present application further provides a Type C interface anti-corrosion device, which can run in a processor, such as the processor 101 in FIG. 6.
  • the anti-corrosion state may be run in the sensorhub of the processor 101, so that the processor 101 executes the Type C interface anti-corrosion method provided by any of the foregoing embodiments.
  • the Type C interface anti-corrosion device 900 includes:
  • a control module 901 is configured to control the interface state of the Type 100 interface 110-1 by the interface chip 110-2 when determining that the movement state of the terminal 100 has changed from a moving state to a stationary state according to the movement state of the terminal 100 monitored by the motion sensor 106.
  • the pin is configured in low mode.
  • the Type C interface anti-corrosion device 900 further includes an acquisition mode 902.
  • the acquisition mode 902 is used to acquire the voltage status of the VBUS pin from the interface chip 110-2.
  • the voltage status of the VBUS pin is the interface chip 110-2. Determined according to whether the VBUS voltage of the VBUS pin in the Type 110C interface 110-1 is lower than a preset threshold;
  • the control module 901 is further configured to control the interface chip 110-2 to change the TypeC interface 110 when the movement state of the terminal 100 is changed from a moving state to a stationary state and the VBUS pin is at a first voltage state lower than the preset threshold.
  • the CC pin of -1 is configured in low mode.
  • control module 901 is further configured to: when it is determined that the terminal is connected to the external device through the Type C interface 110-1, the control interface chip 110-2 configures the CC pin of the Type C interface 110-1 to alternate between high and low levels mode.
  • control module 901 is specifically configured to: when determining that the VBUS pin in the Type C interface 110-1 is in a second voltage state that is not lower than a preset threshold, the control interface chip 110-2 controls the Type C interface 110-
  • the CC pin of 1 is configured for high-low alternating mode.
  • control module 901 is further configured to: when determining that the motion state of the terminal 100 is from a stationary state to a moving state, the control interface chip 110-2 configures the CC pin of the Type C interface 110-1 to an alternating high and low level mode .
  • control module 901 is further configured to: when it is determined that the display screen of the terminal 100 is bright, the control interface chip 110-2 configures the CC pin of the Type C interface 110-1 to an alternating high and low level mode.
  • the interface chip 110-2 is further configured to cache the current working mode of the CC pin; the obtaining module 902 is further configured to: obtain the current working mode of the CC pin from the interface chip 110-2;
  • the control module 901 is further configured to: when the current working mode of the CC pin is the transmission mode, stop controlling the interface chip 110-2 to configure the CC pin as the low-level mode or the high-low level alternate mode; wherein, the transmission mode is the interface
  • the chip 110-2 is a corresponding working mode configured by the CC pin in the Type C interface 110-1 according to the working mode of the CC pin in the Type C interface of the external device.
  • Type C interface anti-corrosion device 900 shown in FIG. 9 may be used to execute the Type C interface anti-corrosion method shown in FIG. 8, and the implementation not described in detail in the Type C interface anti-corrosion device 900 shown in FIG. 9
  • the method refer to the related description in the Type C interface anti-corrosion method shown in FIG. 8.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Telephone Function (AREA)
  • Power Sources (AREA)
  • Information Transfer Systems (AREA)

Abstract

本申请提供一种终端及Type C接口的防腐蚀方法，用于降低Type C接口中CC引脚与其它引脚之间发生电化学腐蚀的几率。在终端中，处理器分别与运动传感器和接口芯片连接；接口芯片分别与处理器和第一Type C接口中的CC引脚连接；运动传感器，用于监测终端的运动状态；处理器，用于根据运动传感器监测到的终端的运动状态，在确定终端的运动状态由移动状态进入静止状态时，控制接口芯片将第一Type C接口的CC引脚配置为低电平模式。由移动状态进入静止状态反应出终端与外接设备断开连接，在此情况下将CC引脚配置为低电平模式，可以降低CC引脚的有效电平，进而降低CC引脚与其它引脚之间发生电化学腐蚀的几率。

Description

一种终端及Type C接口防腐蚀方法 技术领域
本申请实施例涉及电子科学技术领域，尤其涉及一种终端及Type C接口防腐蚀方法。
背景技术
C型(Type C)接口是一种常见的通用串行总线(universal serial bus，USB)接口，因其尺寸小、最大数据传输速度高、无需区分正反面等特点而逐渐成为主流的USB接口之一。
在Type C接口中，包括通道配置(channel configuration，CC)引脚，其主要作用之一便是识别外设类型，确定主从关系，根据主从关系配置工作模式。通常，CC引脚的工作模式包括双角色端口(dual role port，DRP)模式、上行端口(upstream facing port，UFP)模式、下行端口(downstream facing port，DFP)模式。其中，DRP模式是一种在UFP模式和DPF模式之间循环切换的模式，可以使Type C接口识别UFP模式、DFP模式等不同接口模式下的外设，并确定终端与外设之间的主从关系，因此大多数Type C接口在无外设接入时都处于DRP模式。UFP模式下，CC引脚的电平为低电平，在终端为从设备时，Type C接口的CC引脚多处于UFP模式。DFP模式下，CC引脚的电平为高电平，在终端为主设备时，Type C接口的CC引脚多处于DFP模式。
在Type C接口中，CC引脚与VBUS引脚相邻设置。由于Type C接口在无外设连接时，CC引脚有效电平较高，而VBUS引脚多为低电平，使得CC引脚与VBUS引脚具有较高的电压差，在Type C接口进液时，相邻的CC引脚与VBUS引脚之间极易发生电化学腐蚀，从而造成CC引脚与VBUS引脚微短路，进而引发一系列问题，如超级快充功能失效，终端无法进入待机状态而导致的终端耗电过快等等。因此，如何降低USB Type C各引脚之间发生电化学腐蚀的几率是目前Type C接口研究的重要方向之一。
发明内容
本申请实施例提供一种终端及Type C接口防腐蚀方法，用于降低Type C接口中CC引脚与其它引脚之间发生电化学腐蚀的几率。
第一方面，本申请实施例提供一种终端，包括：处理器、接口芯片、运动传感器及第一Type C接口；其中，处理器分别与运动传感器和接口芯片连接；接口芯片分别与处理器和第一Type C接口中的CC引脚连接；运动传感器，用于监测终端的运动状态；处理器，用于根据运动传感器监测到的终端的运动状态，在确定终端的运动状态由移动状态进入静止状态时，控制接口芯片将第一Type C接口的CC引脚配置为低电平模式。
终端的运动状态由移动状态进入静止状态时，该运动状态的变化反应出终端与外接设备断开连接，终端在此情况下将CC引脚配置为低电平模式，可以降低CC引脚的有效电平，由于CC引脚的有效电平的高低与CC引脚与其它引脚之间发生电化学腐蚀的几率正相关，因此，降低CC引脚的有效电平，便可以降低CC引脚与其它引脚之间发生电化学腐蚀的几率。
在一种可能的实现方式中，接口芯片，还与第一Type C接口中的VBUS引脚连接，用于获取VBUS引脚的VBUS电压；处理器还用于：从接口芯片获取VBUS引脚的电压 状态，其中，VBUS引脚的电压状态是接口芯片根据VBUS引脚的VBUS电压是否低于预设阈值确定的；在确定所述终端的运动状态由移动状态进入静止状态且VBUS引脚处于低于预设阈值的第一电压状态时，控制接口芯片将第一Type C接口的CC引脚配置为低电平模式。
运动传感器有一定的失效率，处理器在确定终端的运动状态由移动状态进入静止状态的同时进一步确定VBUS引脚处于低于预设阈值的第一电压状态，以确保终端与外接设备断开连接后，再为CC引脚配置低电平模式。由于低电平模式下终端无法识别外接设备，因此确保在终端与外接设备断开连接后再为CC引脚配置低电平模式，降低了由于CC引脚被错误地配置了低电平模式而使终端无法识别外接设备等情况发生的可能性。
在一种可能的实现方式中，处理器还用于：在确定终端通过第一type C接口与外接设备连接时，控制接口芯片将第一Type C接口的CC引脚配置为高低电平交替模式。
由于只有在CC引脚处于高低电平交替模式下时，终端中的接口芯片才能够识别通过第一Type C接口接入的外接设备，进而才能实现数据或电能的传输。因此，处理器在确定终端通过第一Type C接口与外接设备连接时，控制接口芯片将CC引脚配置为高低电平模式从而使接口芯片可以识别外接设备。
在一种可能的实现方式中，处理器具体用于：从接口芯片获取VBUS引脚的电压状态；其中，VBUS引脚的电压状态是接口芯片根据VBUS引脚的VBUS电压是否低于预设阈值确定的；在确定VBUS引脚处于不低于预设阈值的第二电压状态时，控制接口芯片将所述第一Type C接口的CC引脚配置为高低电平交替模式。
一些具有Type C接口的外接设备，在与终端通过Type C接口建立物理连接后，会使终端Type C接口内的VBUS引脚上的VBUS电压升高，处理器在确定VBUS引脚处于VBUS电压不低于预设阈值的第二电压状态时，便可以确定终端接入了外接设备。
在一种可能的实现方式中，处理器还用于：在确定终端的运动状态由静止状态进入移动状态时，控制接口芯片将第一Type C接口的CC引脚配置为高低电平交替模式。
终端的运动状态由静止状态进入移动状态时，该运动状态的变化反应出终端正在与外接设备建立连接，终端在此情况下控制接口芯片将第一Type C接口的CC引脚配置为高低电平交替模式，可以使终端与外接设备建立物理连接后，终端中的接口芯片立即通过高低电平交替模式下的CC引脚识别外接设备。
在一种可能的实现方式中，处理器还用于：在确定终端的显示屏亮屏时，控制接口芯片将第一Type C接口的CC引脚配置为高低电平交替模式。
以上技术方案为用户提供了一种可以强制将第一Type C接口的CC引脚配置为高低电平交替模式的途径，用户在将终端与外接设备连接后，若终端中的接口芯片未能成功识别外接设备，用户便可以点亮显示屏，强制将第一Type C接口的CC引脚配置为高低电平交替模式，从而使终端中的接口芯片能够识别外接设备。
在一种可能的实现方式中，接口芯片还用于缓存CC引脚当前的工作模式；处理器，还用于：从接口芯片获取CC引脚当前的工作模式；在CC引脚当前的工作模式为传输模式时，停止控制接口芯片将CC引脚配置为低电平模式或高低电平交替模式；其中，传输模式为接口芯片根据外接设备的第二Type C接口中CC引脚的工作模式为CC引脚配置的对应的工作模式。
终端在于外接设备建立连接之后，也可能出现运动状态的变化、显示屏亮屏等情况， 此时不论将CC引脚配置为低电平模式还是高低电平交替模式都有可能影响到终端与外接设备之间的数据或电能的传输，因此，在CC引脚的当前工作模式为传输模式时，处理器停止控制接口芯片将CC引脚配置为低电平模式或高低电平交替模式，以免影响终端与外接设备之间数据或电能的传输。
在一种可能的实现方式中，接口芯片是根据处理器提供的控制信号配置CC引脚的工作模式的；接口芯片包括控制电路、上拉电源、上拉开关、上拉电阻、下拉开关和下拉电阻；其中，上拉电阻的一端与上拉电源连接，上拉电阻的另一端与上拉开关的第一电极连接，上拉开关的第二电极与CC引脚相连；下拉电阻的一端接地，下拉电阻另一端与下拉开关的第一电极连接，下拉开关的第二电极与CC引脚连接；控制电路分别与上拉开关和下拉开关的控制电极连接，控制电路用于根据处理器的控制信号控制上拉开关和下拉开关的开启和断开。
在一种可能的实现方式中，控制电路具体用于：根据第一控制信号断开上拉开关，并开启下拉开关。
控制电路根据第一控制信号断开上拉开关，CC引脚不再接收上拉电源提供的高电平。同时，开启下拉开关，使CC引脚向地放电，CC引脚上的电平逐渐趋近于0，从而实现低电平模式。
在一种可能的实现方式中，控制电路具体用于：根据第一控制信号断开上拉开关和下拉开关。
控制电路根据第一控制信号断开上拉开关和下拉开关，CC引脚不再接收上拉电源提供的高电平。虽然控制电路同时断开了下拉开关，但CC引脚仍可通过下拉开关的漏电流向地放电，使CC引脚上的电平缓慢趋近于0，从而实现低电平模式。
在一种可能的实现方式中，终端还包括第一电阻；第一电阻的一端与CC引脚相连，第一电阻的另一端接地；第一电阻用于为CC引脚提供放电路径。
在控制电路根据第一控制信号断开上拉开关和下拉开关的情况下，第一电阻可以提供CC引脚向地放电的路径，使CC引脚的电平更快趋近于0，从而实现低电平模式。
在一种可能的实现方式中，控制电路还用于：根据第二控制信号周期性交替开启上拉开关和下拉开关。
控制电路开启上拉开关，断开下拉开关时，CC引脚为高电平；断开上拉开关，开启下拉开关时，CC引脚为低电平。因此，控制电路根据第二控制信号周期性交替开启上拉开关和下拉开关，便可以为CC引脚配置高低电平交替模式。
在一种可能的实现方式中，控制电路具体用于：在交替开启上拉开关和下拉开关若干个周期之后的预设时间间隔内，保持断开第一开关和第二开关，并在预设间接间隔之后，再次交替开启上拉开关和下拉开关若干个周期，直至接收到第一指令或识别到第二Type C接口中CC引脚的工作模式。
周期性交替开启上拉开关和下拉开关若干个周期之后，保持断开第一开关和第二开关可以延长高低电平交替模式下CC引脚的低电平实现，从而降低CC引脚的有效电平，有利于进一步降低CC引脚与其它引脚发生电化学腐蚀的几率。
在一种可能的实现方式中，接口芯片包括功率传输PD芯片，或，CC控制controller芯片。
在一种可能的实现方式中，运动传感器包括加速度传感器Gsensor，和/或，陀螺仪， 和/或，重力传感器。
第二方面，本申请实施例提供一种Type C接口防腐蚀方法，该方法应用于终端内的处理器，该终端还包括接口芯片、第一Type C接口和运动传感器，其中，处理器分别与接口芯片和运动传感器连接，接口芯片分别与处理器和第一Type C接口连接，该Type C接口防腐蚀方法包括：根据运动传感器监测到的终端的运动状态，在确定终端的运动状态由移动状态进入静止状态时，控制接口芯片将第一Type C接口的CC引脚配置为低电平模式。
在一种可能的实现方式中，该方法还包括：从接口芯片获取VBUS引脚的电压状态；其中，VBUS引脚的电压状态是接口芯片根据VBUS引脚的VBUS电压是否低于预设阈值确定的；在确定终端的运动状态由移动状态进入静止状态且VBUS引脚处于低于预设阈值的第一电压状态时，控制接口芯片将第一Type C接口的CC引脚配置为低电平模式。
在一种可能的实现方式中，该方法还包括：在确定终端通过第一Type C接口与外接设备连接时，控制接口芯片将第一Type C接口的CC引脚配置为高低电平交替模式。
在一种可能的实现方式中，确定终端通过第一Type C接口与外接设备连接，包括：从接口芯片获取VBUS引脚的电压状态；其中，VBUS引脚的电压状态是接口芯片根据VBUS引脚的VBUS电压是否低于预设阈值确定的；在确定VBUS引脚处于不低于预设阈值的第二电压状态时，控制接口芯片将第一Type C接口的CC引脚配置为高低电平交替模式。
在一种可能的实现方式中，该方法还包括：在确定终端的运动状态由静止状态进入移动状态时，控制接口芯片将第一Type C接口的CC引脚配置为高低电平交替模式。
在一种可能的实现方式中，该方法还包括：在确定终端的显示屏亮屏时，控制接口芯片将第一Type C接口的CC引脚配置为高低电平交替模式。
在一种可能的实现方式中，接口芯片还用于缓存CC引脚当前的工作模式；该方法还包括：从接口芯片获取CC引脚当前的工作模式；在CC引脚当前的工作模式为传输模式时，停止控制接口芯片将CC引脚配置为低电平模式或高低电平交替模式；其中，传输模式为接口芯片根据外接设备的第二Type C接口中CC引脚的工作模式为CC引脚配置的对应的工作模式。
附图说明
图1为本申请实施例提供的一种可行的终端结构示意图；
图2a～图2d为本申请实施例提供的一种终端与外接设备之间连接阶段示意图；
图3为本申请实施例提供的一种可行的终端结构示意图；
图4为本申请实施例提供的一种可行的终端结构示意图；
图5为本申请实施例提供的一种接口芯片结构示意图；
图6为本申请实施例提供的一种可行的终端结构示意图；
图7为本申请实施例提供的一种电平信号示意图；
图8为本申请实施例提供的一种Type C接口防腐蚀方法流程示意图；
图9为本申请实施例提供的一种Type C接口防腐蚀装置结构示意图。
具体实施方式
以下结合附图及实施例，对本申请实施例进行进一步详细说明。
本申请实施例提供一种终端，该终端可以是笔记本电脑、智能手机、平板电脑、个人数字助理、数字视屏摄像机、智能家居等适用Type C接口的终端。示例性地，如图1所示，本申请实施例中的终端100可以为手机，下面以终端100为手机时的结构为例对实施例进行具体说明。应该理解的是，图示终端100仅是本申请实施例所提供的终端的一个范例，并且终端100可以具有比图中所示出的更多的或者更少的部件，可以组合两个或更多的部件，或者可以具有不同的部件配置。图中所示出的各种部件可以在包括一个或多个信号处理和/或专用集成电路在内的硬件、软件、或硬件和软件的组合中实现。
如图1所示，终端100具体可以包括：一个或多个处理器101、射频(radio frequency，RF)电路102、存储器103、触摸屏104、蓝牙装置105、一个或多个传感器106、Wi-Fi装置107、定位装置108、音频电路109、外设接口110以及电源装置111等部件。这些部件可通过一根或多根通信总线或信号线(图1中未示出)进行通信。本领域技术人员可以理解，图1中示出的硬件结构并不构成对终端100的限定，终端100可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。
下面结合图1对终端100的各个部件进行具体的介绍：
处理器101是终端100的控制中心，利用各种接口和线路连接终端100的各个部分，通过运行或执行存储在存储器103内的应用程序(Application，简称App)，以及调用存储在存储器103内的数据和指令，执行终端100的各种功能和处理数据。在一些实施例中，处理器101可包括一个或多个处理单元；处理器101还可以集成应用处理器和调制解调处理器；其中，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调处理器主要处理无线通信。可以理解的是，上述调制解调处理器也可以不集成到处理器101中。举例来说，处理器101可以是华为技术有限公司制造的麒麟960芯片。此外，处理器还包括传感器集线器(sensorhub)，用于管理传感器106和触控板104-1的传感数据，可以在处理器101休眠时，进行低功耗工作。
射频电路102可用于在收发信息或通话过程中，无线信号的接收和发送。具体地，射频电路102可以将基站的下行数据接收后，给处理器101处理；另外，将涉及上行的数据发送给基站。通常，射频电路包括但不限于天线、至少一个放大器、收发信机、耦合器、低噪声放大器、双工器等。此外，射频电路102还可以通过无线通信和其他设备通信。所述无线通信可以使用任一通信标准或协议，包括但不限于全球移动通讯系统、通用分组无线服务、码分多址、宽带码分多址、长期演进、电子邮件、短消息服务等。
存储器103用于存储应用程序以及数据，处理器101通过运行存储在存储器103的应用程序以及数据，执行终端100的各种功能以及数据处理。存储器103主要包括存储程序区以及存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序(比如声音播放功能、图像播放功能等)；存储数据区可以存储根据使用终端100时所创建的数据(比如音频数据、电话本等)。此外，存储器103可以包括高速随机存取存储器，还可以包括非易失存储器，例如磁盘存储器件、闪存器件或其他非易失性固态存储器件等。存储器103可以存储各种操作系统，例如苹果公司所开发的
Figure PCTCN2018096893-appb-000001
操作系统，谷歌公司所开发的
Figure PCTCN2018096893-appb-000002
操作系统等。示例性地，存储器103中存储了与本申请实施例相关的应用程序，例如Taskcard store、推特、电话本、微博等。
触摸屏104可以包括触控板104-1和显示器104-2。其中，触控板104-1可采集终端100的用户在其上或附近的触摸事件(比如用户使用手指、触控笔等任何适合的物体在触 控板104-1上或在触控板104-1附近的操作)，并将采集到的触摸信息发送给其他器件例如处理器101。显示器(也称为显示屏)104-2可用于显示由用户输入的信息或提供给用户的信息以及终端100的各种菜单，其中包括显示屏驱动芯片，用于在处理器101的控制下驱动显示屏中二极管、液晶屏等工作。
终端100还可以包括至少一种传感器106，比如光传感器、运动传感器以及其他传感器。其中，运动传感器可以包括加速度传感器(Gsensor)，加速度传感器可监测各个方向上(一般为三轴)加速度的大小，从而可以监测终端100的运动状态。具体实现中，运动传感器除了可以判断终端是否发生了位移，还可以根据监测出的重力的大小及方向，实现识别终端姿态、振动识别相关功能等。此外，运动传感器还可以进一步包括陀螺仪、重力传感器等，以增加可以监测的运动状态类型。在本申请实施例中，传感器106至少包括运动传感器，因此本申请实施例中将运动传感器以标号106进行标识。
Wi-Fi装置107，用于为终端100提供遵循Wi-Fi相关标准协议的网络接入，终端100可以通过Wi-Fi装置107接入到Wi-Fi接入点，进而帮助用户收发电子邮件、浏览网页和访问流媒体等，它为用户提供了无线的宽带互联网访问。
定位装置108，用于为终端100提供地理位置。可以理解的是，该定位装置108具体可以是全球定位系统(global positioning system，GPS)、北斗卫星导航系统等定位系统的接收器。定位装置108在接收到上述定位系统发送的地理位置后，将该信息发送给处理器101处理，或者发送给存储器103保存。
音频电路109、扬声器113、麦克风114可提供用户与终端100之间的音频接口。音频电路109可将接收到的音频数据转换后的电信号，传输到扬声器113，由扬声器113转换为声音信号输出；另一方面，麦克风114将收集的声音信号转换为电信号，由音频电路109接收后转换为音频数据，再将音频数据输出至RF电路102以发送给比如一个终端，或者将音频数据输出至存储器103以便进一步处理。
外设接口110，用于为外接设备(例如键盘、鼠标、外接显示器、外部存储器、用户识别模块卡等)提供各种接口。例如通过通用串行总线接口与鼠标连接，通过用户识别模块卡卡槽上的金属触点与电信运营商提供的用户识别模块(subscriber identity module，SIM)卡连接。外设接口110可以被用来将上述输入/输出的外接设备耦接到处理器101和存储器103。具体的，外设接口110包括物理接口110-1和接口芯片110-2，外设接口110用于与外接设备建立物理连接，接口芯片110-2用于实现终端100与外接设备之间的适配，使通过物理接口110-1传递的数据符合接口协议的规定。在本申请实施例中，物理接口110-1可以是Type C接口，因此，本申请实施例中将Type C接口以标号110-1进行标识。接口芯片110-2可以是功率传输(powerdelivery，PD)芯片，也可以是CC控制(CC controller)芯片，接口芯片110-2用于识别外接设备，并进行终端100与外接设备之间的适配，使通过Type C接口传递的数据符合Type C协议的规定。
此外，终端100还可以包括给各个部件供电的电源装置111(比如电池和电源管理芯片)，电池可以通过电源管理芯片与处理器101逻辑相连，从而通过电源装置111实现管理充电、放电、以及功耗管理等功能。
尽管图1未示出，终端100还可以包括摄像头，例如前置摄像头、后置摄像头，其中，前置摄像头可以用于捕捉人脸特征信息，处理器101可以对该人脸特征信息进行人脸识别，进而进行后续处理。终端100还可以包括闪光灯、微型投影装置、近场通信(near field  communication，NFC)装置等，在此不予赘述。
以下实施例均可以在具有上述硬件结构的终端(例如终端、平板电脑等)中实现。具体地，处理器101可以通过运动传感器106获取终端的运动状态，从而根据终端的运动状态控制外设接口110中的接口芯片110-2对物理接口110-1(Type C接口110-1)的工作模式进行配置。
为了便于理解，本申请将终端在使用过程中，与外接设备之间的连接阶段大致分为以下四种以供说明，包括：未与外接设备连接、正在与外接设备建立连接、与外接设备连接、正在与外接设备断开连接。如图2a所示，终端100处于未与外接设备连接阶段，处于该阶段的终端100，其Type C接口110-1没有与外接设备连接，也没有尝试与外接设备连接。如图2b所示，为终端100处于正在与外接设备200建立连接阶段，该阶段终端100和外接设备200按照图中箭头所示方向移动，使终端100的Type C接口110-1与外接设备200的Type C接口201相连，实现了终端100与外接设备200之间的物理连接。此外，在本申请实施例中该阶段还包括了终端100与外接设备200建立物理连接之后，二者之间通过Type C接口110-1和201进行模式识别和配置传输模式的阶段。如图2c所示，终端100处于与外接设备200连接的阶段，终端100与外接设备200之间按照在建立连接时配置的传输模式实现数据或者电能的传输。如图2d所示，终端100处于正在与外接设备200断开连接的阶段。在图2d所示的阶段之后，终端100便又恢复至图2a所示的未与外接设备200连接阶段。应理解，图2a至图2d所示各个阶段之间并没有严格的划分界限，本申请实施例提供该四个阶段仅是为了解释本申请实施例所提供的技术方案。
应理解，终端100的Type C接口110-1既可以是插头形式，也可以是插座形式，终端100的Type C接口110-1可以直接与外接设备的Type C接口连接，该外接设备可以是自带有Type C接口的外接设备，也可以是与Type C数据线连接，以Type C数据线上的Type C接口与终端实现连接的外接设备。
图3为本申请实施例提供的一种可行的终端结构示意图，如图3所示，终端100包括处理器101、接口芯片110-2、运动传感器106和Type C接口110-1。其中，处理器101分别与接口芯片110-2和运动传感器106连接，此外，接口芯片110-2与处理器101连接的同时，还与Type C接口110-1连接。运动传感器106可以监测终端100的运动状态，处理器101可以根据运动传感器106监测的运动状态，在确定终端100的运动状态由移动状态进入静止状态时，控制接口芯片110-2将Type C接口110-1的CC引脚配置为低电平模式，从而降低CC引脚的有效电平。由于引脚之间发生电化学腐蚀的几率与引脚之间电压差的大小正相关，因此降低CC引脚的有效电平可以降低CC引脚与Type C接口110-1中其它引脚之间发生电化学腐蚀的几率。
例如，在终端100处于图1d所示的正在与外接设备200断开连接的阶段时，终端100需沿图中箭头所示方向移动一段距离后，才可以使两个Type C接口(110-1和201)断开物理连接，因此，运动传感器106此时所监测到的终端100的运动状态为移动状态。在图1d所示阶段之后，即外接设备200的Type C接口201与终端100的Type C接口110-1分离后，终端进入图1a所示的未与外接设备连接的阶段。图1a所示阶段中终端100往往会存在静止的情况，此时运动传感器106所监测到的终端100的运动状态为静止状态。因此处理器101在确定终端100的运动状态由移动状态进入静止状态时，便可以认为终端100进入图1a所示的既不与外接设备连接，也不尝试与外接设备连接的阶段，在此阶段中，处 理器101控制接口芯片110-2将Type C接口110-1中的CC引脚配置为低电平模式，既不影响Type C接口110-1的使用，又可以降低Type C接口110-1中CC引脚与其它引脚之间发生电化学腐蚀的几率。
在图3所示的终端100中，处理器101可以通过与运动传感器106之间的电连接从运动传感器106获取终端100的运动状态。具体的，运动传感器106与处理器101之间可以包括集成电路总线(inter－integratedcircuit，I2C)、中断信号线(interrupt，INT)等连接。如图4所示，运动传感器106和处理器101通过I2C连接。I2C连接包括串行时钟线(serial clockline，SCL)和串行数据线(serial data line，SDA)。基于图4所示的运动传感器106与处理器101之间的连接方式，在一种可行的实现方式中，处理器101可以周期性地通过与运动传感器106之间的I2C连接来获取运动传感器106监测到的终端100的运动状态，从而确定终端100运动状态的变化。
在另一种可行的实现方式中，如图4所示，处理器101和运动传感器106之间还包括INT连接。运动传感器106在监测到终端100的运动状态发生变化后，运动传感器106通过与处理器101之间的INT连接向处理器101发送中断信号。中断信号可以唤醒处理器101，处理器101在接收到中断信号后，再通过I2C连接从运动传感器106获取终端100的运动状态。在从运动传感器106获取的终端100的运动状态为移动状态时，处理器101便可以确定终端100的运动状态由静止状态进入移动状态；在从运动传感器106获取的终端100的运动状态为静止状态时，处理器101便可以确定终端100的运动状态由移动状态进入静止状态。在本实现方式中，处理器101无需频繁地从运动传感器106获取终端100的运动状态，有利于降低终端100的功耗。
此外，如图4所示，处理器101具体通过其内部的传感器集线器(sensorhub)与运动传感器106相连，由sensorhub通过INT连接接收运动传感器106发送的中断信号，以及，由sensorhub通过I2C连接从运动传感器106获取终端100的运动状态，使得在终端100的运动状态发生变化时，运动传感器106所发送的中断信号只会唤醒处理器101中的sensorhub，并不会将处理器101整体唤醒，有利于进一步降低终端100的功耗。基于类似的原理，如图4所示，处理器101也可以通过sensorhub与接口芯片110-2连接，以降低终端100的功耗。
在本申请实施例中，处理器101可以根据运动传感器106监测到的终端100的运动状态控制接口芯片110-2配置Type C接口110-1中CC引脚的工作模式。具体的，处理器101可以根据终端100的运动状态生成控制信号，并通过控制信号控制接口芯片110-2配置TypeC接口110-1中CC引脚的工作模式。在图4所示的终端100中，处理器101与接口芯片110-2之间可以通过I2C实现连接。处理器101可以通过I2C连接(SDA和SCL)向接口芯片110-2发送控制信号，从而控制接口芯片110-2配置Type C接口110-1中CC引脚的工作模式。
由于考虑到运动传感器106有一定的失效率，如果由于运动传感器106单体问题导致误检测到终端100由运动状态进入静止状态，使得处理器101控制接口芯片110-2将非静止状态下终端100的Type C接口110-1内的CC引脚配置为低电平模式，会导致终端100中的接口芯片110-2无法识别OTG(on-the-go)类型的外接设备。这是因为，OTG类型的外接设备的TypeC接口中，CC引脚的工作模式固定为UFP模式，只有在Type C接口110-1中CC引脚为DRP模式或DFP模式时，接口芯片110-2才能够识别外接设备。
因此，为了提高对图1a所示阶段判断的可靠性，处理器101在确定终端100由移动状态进入静止状态后，还可以进一步判断Type C接口110-1中VBUS引脚的VBUS电压是否低于预设阈值。如图3所示，接口芯片110-2还与Type C接口110-1中的VBUS引脚连接，接口芯片110-2可以获取VBUS引脚上的VBUS电压，并根据VBUS电压与预设阈值之间的相对大小关系确定VBUS引脚的电压状态。在本申请实施例中，VBUS引脚的电压状态包括VBUS电压低于预设阈值的第一电压状态和VBUS电压不低于预设阈值的第二电压状态。处理器101在确定终端100由移动状态进入静止状态后，还可以通过与接口芯片110-2之间的I2C连接获取VBUS引脚当前的电压状态，并在确定VBUS引脚处于第一电压状态时，才会控制接口芯片110-2将Type C接口110-1中CC引脚的工作模式配置为低电平模式。
通常，在图1a所示的未与外接设备连接阶段，终端100的Type C接口110-1中VBUS引脚的VBUS电压为低电平，此时VBUS引脚处于第一电压状态，因此，在终端100的运动状态由移动状态进入静止状态，且VBUS引脚的VBUS电压状态为低于预设阈值的第一电压状态时，便在很大程度上意味着终端100此时处于图1a所示的未与外接设备连接的阶段，此时，处理器101再控制接口芯片110-2将Type C接口110-1中的CC引脚配置为低电平模式，有利于降低由于错误地为CC引脚配置低电平模式致使终端100中的接口芯片110-2无法识别外接设备的情况发生的可能性。
在本申请实施例中，处理器101可以控制接口芯片110-2配置Type C接口110-1中CC引脚的工作模式。其中，接口芯片110-2与Type C接口110-1连接，可以接收处理器101发送的控制信号，并根据所接收到的控制信号配置Type C接口110-1的工作模式。在具体实现中，接口芯片110-2可以与Type C接口110-1中的多个引脚分别连接，其中包括了与Type C接口110-1中的两个CC引脚—CC1和CC2之间的连接，接口芯片110-2在接收到控制信号后可以根据控制信号分别配置CC1和CC2的工作模式。
基于此，图5为本申请实施例提供的一种接口芯片结构示意图，如图5所示，接口芯片110-2包括控制电路1031、上拉开关1032、上拉电阻1033、上拉电源1034、下拉电阻1035和下拉开关1036。
其中，上拉电阻1033的一端与上拉电源1034连接，上拉电阻1033的另一端与上拉开关1032的第一电极连接，上拉开关1032的第二电极与Type C接口110-1的CC引脚相连；下拉电阻1035的一端接地，下拉电阻1035另一端与下拉开关1036的第一电极连接，下拉开关1036的第二的电极与Type C接口110-1的CC引脚连接。控制电路1031，分别与上拉开关1032和下拉开关1036的控制电极连接，用于根据处理器101发送的控制信号控制上拉开关1032和下拉开关1036的开启和断开。
在具体实现时，上拉电源用于为CC引脚提供高电平，其可以是终端100中的直流/直流(DC/DC)转换器，也可以是低压差线性稳压器(low dropout regulator，LDO)。
基于Type C协议规定，在上拉开关1032开启，下拉开关1036断开时，接口芯片110-2为CC引脚配置的工作模式对应于DFP模式；在上拉开关1032断开，下拉开关1036开启时，接口芯片110-2为CC引脚配置的工作模式对应于UFP模式；在上拉开关1032和下拉开关1036周期性交替开启时，如在一个周期T内，前t1时间间隔内上拉开关1032断开，下拉开关1036开启，在后t2(t1+t2＝T)时间间隔内，上拉开关1032开启，下拉开关1036断开，此时接口芯片110-2为CC引脚配置的工作模式对应于DRP模式。
在本申请实施例中，处理器101通过向接口芯片110-2发送第一控制信号可以控制接口芯片110-2将Type C接口110-1中的CC引脚配置为低电平模式。接口芯片110-2在接收到处理器101发送的第一控制信号后，至少可通过以下两种方式为Type C接口110-1的CC引脚配置低电平模式。
在一种可行的实现方式中，控制电路1031根据第一控制信号断开上拉开关1032，并开启下拉开关1036。此时，CC引脚停止接收来自上拉电源1034的高电平，并经下拉开关1036和下拉电阻1035向地放电，使得CC引脚上的电平逐渐趋于0，从而实现低电平模式。此时，Type C接口110-1的CC引脚的工作模式对应于Type C协议中规定的UFP模式。
在另一种可行的实现方式中，控制电路1031根据第一控制信号同时断开上拉开关1032和下拉开关1036，CC引脚停止接收来自上拉电源1034的高电平，并由于下拉开关1036中漏电流的存在，仍可以逐渐向地放电，使CC引脚上的电平缓慢地趋于0。更进一步的，如图5所示，终端100中还包括第一电阻115；第一电阻115的一端与CC引脚相连，第一电阻115的另一端接地。第一电阻115可以在控制电路1031同时断开上拉开关1032和下拉开关1036时，为CC引脚提供向地放电的路径。CC引脚可以通过第一电阻115向地放电，使得CC引脚上的电平更快地趋近于0，从而能够更快地将CC引脚配置为低电平模式。
此外，在该实现方式中，为了减小第一电阻115在DFP模式和UFP模式中对CC引脚的电平所带来的影响，第一电阻115的阻值应远远大于上拉电阻1033和下拉电阻1035的阻值，使得在UFP模式和DFP模式下，第一电阻115所构成的接地路径可以近似于断路。而且，下拉电阻1035的阻值为5.1k，为了不影响下拉开关1036的精度，第一电阻115的阻值可以为500k或1Mohm。
通过以上两种可行的实现方式，皆可以将CC引脚的工作模式配置为低电平工作模式，从而降低CC引脚在终端100下一次连接外接设备之前的有效电平，进而降低CC引脚与其它引脚发生电化学腐蚀的几率。
在本申请实施例中，处理器101在终端100处于未与外接设备连接阶段时，控制接口芯片110-2将Type C接口110-1的CC引脚配置为低电平模式。然而，在终端100处于图1b所示的正在与外接设备200建立连接的阶段时，终端100与外接设备200建立物理连接后，接口芯片110-2可以通过高低电平交替模式下的CC引脚识别外接设备200的Type C接口201中的CC引脚。若在图1b所示的阶段中，终端100的Type C接口110-1中的CC引脚仍处于低电平模式，接口芯片110-2将无法识别外接设备200的Type C接口201中CC引脚的工作模式。基于此，本申请实施例提供至少以下三种可行的实现方式，以保证在图1b所示阶段，接口芯片110-2能够实现对Type C接口201中CC引脚的工作模式的识别。
第一种
在第一种可行的实现方式中，处理器101在根据运动传感器106提供的终端100的运动状态，确定终端100由静止状态进入移动状态时，控制接口芯片110-2将Type C接口110-1的CC引脚配置为高低电平交替模式。在图1b所示的阶段，终端100需沿图中箭头方向移动一段距离之后，才能与外接设备200建立物理连接，因此，终端100在由静止状态进入移动状态时，便意味着终端100有可能进入了图1b所示的阶段，在此情况下，处理器101控制接口芯片110-2将CC引脚配置为高低电平交替模式，从而可以保证终端100在图1b 阶段时，终端100中的接口芯片110-2可以在终端100与外接设备200建立物理连接后，识别外接设备200的Type C接口201中CC引脚的工作模式。
第二种
在第二种可行的实现方式中，处理器101可以在确定终端100通过Type C接口110-1与外接设备200连接时，控制接口芯片110-2将Type C接口110-1的CC引脚配置为高低电平交替模式。
具体地，处理器101可以从接口芯片110-2获取VBUS引脚当前的电压状态，并在确定VBUS引脚处于VBUS电压不低于预设阈值的第二电压状态时，控制接口芯片110-2将Type C接口110-1中的CC引脚配置为高低电平交替模式。显然，接口芯片110-2也可以在VBUS引脚的电压状态由第一电压状态转变为第二电压状态时，向处理器101发送中断信号，处理器101在接收到该中断信号后，便可以确定终端100与外接设备200建立了物理连接，从而控制接口芯片110-2将Type C接口110-1的CC引脚配置为高低电平交替模式。
在本申请实施例中，外接设备200的类型并不固定，例如至少可以分为如下两类：一、终端与第一类外接设备200建立物理连接之后，Type C接口110-1的VBUS引脚便会由第一电压状态转变为第二电压状态；二、终端100与第二类外接设备200建立物理连接之后，Type C接口110-1的VBUS引脚仍会处于第一电压状态，只有在终端100与外接设备200完成识别并配置好传输模式之后，终端100的Type C接口110-1中的VBUS引脚才会由第一电压状态转变为第二电压状态。可见，第二种实现方式较适用于终端100与第一类外接设备200连接的情况，在具体实现时可以与第一种可行的实现方式结合使用。
第三种
在第三种可行的实现方式中，处理器101还可以在确定显示屏亮屏时，控制接口芯片110-2将Type C接口110-1的CC引脚配置为高低电平交替模式。
在一种具体可行的实现方式中，如图6所示，终端100中还包括显示屏驱动芯片104-3；显示屏驱动芯片104-3，与处理器101连接，用于在显示屏亮屏时，向处理器101发送中断信号，该中断信号可以唤醒处理器101。处理器101在接收到显示屏驱动芯片104-3发送的中断信号后，控制接口芯片110-2将Type C接口110-1中的CC引脚配置为高低电平交替模式。显然，在具体实现中，显示屏驱动芯片104-3也可以与处理器101的sensorhub相连，以降低终端100的功耗。
第三种可行的实现方式为终端用户提供了一种强制将Type C接口110-1的CC引脚配置为高低电平交替模式的途径，用户在将终端100与外接设备200物理连接后，若终端100的接口芯片110-2未能识别到外接设备200的Type C接口201，用户可以通过手动点亮显示屏的方式将Type C接口110-1的CC引脚配置为高低电平交替模式，使接口芯片110-2可以识别到外接设备200的Type C接口201。
应理解，以上三种实现方式互相之间并不排斥，可以同时在终端100中实现。例如，处理器101为三种实现方式分别配置不同的优先级，显示屏驱动芯片104-3所提供的中断信号具有最高的优先级，运动传感器106提供的终端100的运动状态的优先级次之，接口芯片110-2提供的VBUS引脚的电压状态的优先级最低。处理器101在接收到显示屏驱动芯片104-3发送的中断信号后，无论此时VBUS引脚的电压状态和终端100的运动状态具体为何种状态，处理器101都立即控制接口芯片110-2将Type C接口110-1中的CC引脚 配置为高低电平交替模式。
在本申请实施例中，处理器101可以控制接口芯片110-2将Type C接口110-1中的CC引脚配置为高低电平交替模式，具体实现时，处理器101可以通过向接口芯片110-2发送第二控制信号以控制接口芯片110-2将Type C接口110-1中的CC引脚配置为高低电平交替模式。
请参考图5所示的接口芯片110-2，接口芯片110-2在接收到第二控制信号后，控制电路1031根据第二控制信号周期性交替开启上拉开关1032和下拉开关1036，CC引脚的工作模式对应于Type C协议规定的DRP模式。此时，接口芯片110-2为CC引脚提供的电平信号可以如图7中的信号a所示，其中，T为一个DRP周期，t1为一个DRP周期内的低电平时长，t2为一个DRP周期内的高电平时长。一般，T可以为65ms，t1可以为50ms，t2可以为15ms。在t1时间内，CC引脚为低电平，接口芯片110-2可以通过CC引脚识别到DFP模式的外接设备，在t2时间内，CC引脚为高电平，接口芯片110-2可以通过CC引脚识别到UFP模式的外接设备。通过周期性交替开启接口芯片110-2中的上拉开关1032和下拉开关1036，接口芯片110-2便可以通过高低电平交替模式下的CC引脚识别到CC引脚为不同工作模式下的外接设备。
为了进一步降低Type C接口110-1的CC引脚在终端100处于正在与外接设备建立连接阶段中的有效电平，在一种可行的实现方式中，控制电路1031在交替开启上拉开关1032和下拉开关1036若干个周期之后的预设时间间隔内，断开上拉开关1032，开启下拉开关1036，并在预设时间间隔之后，再次交替开启上拉开关1032和下拉开关1036若干个周期。
以图7中信号b为例，控制电路1031在交替开启上拉开关1032和下拉开关1036两个周期之后，在t3的时间间隔内断开上拉开关，并开启下拉开关，使CC引脚在t3时间间隔内保持低电平，一般t3可以为500ms。在t3时间间隔之后，重复交替开启上拉开关1032和下拉开关1036两个周期。通过延长高低电平交替模式中的低电平时长，从而降低了CC引脚在终端100处于图1b所示阶段时的有效电平，进一步降低了Type C接口110-1中CC引脚与其它引脚发生电化学腐蚀的几率。
在Type C协议中规定了DRP模式下下拉开关1036开启时间的占空比和DRP周期长度，若图7中t3时间间隔内的低电平是通过将CC引脚配置为UFP模式(即开启下拉开关1036，断开上拉开关1032)而实现，则会使下拉开关1036开启时间的占空比超过Type C协议对DRP模式中对下拉开关开启时间的占空比的规定。
基于此，在另一种可行的实现方式中，接口芯片110-2在t3时间间隔内通过断开上拉开关1032和下拉开关1036而实现低电平，由第一电阻115为CC引脚提供向地放电路径。在接口芯片110-2同时断开上拉开关1032和下拉开关1036时，CC引脚并没有被配置为DRP模式，因此采用上述实现方式并未违反Type C协议的规定。显然，在此情况下t1时间间隔内的低电平也可以通过断开上拉开关1032和下拉开关1036实现。
接口芯片110-2将Type C接口110-1的CC引脚配置为高低电平交替模式之后，通过监测高低电平交替模式下CC引脚的电压变化便可以识别出外接设备200的Type C接口201中CC引脚的工作模式，进而便可以将Type C接口110-1的CC引脚配置为对应的传输模式。
例如，接口芯片110-2在识别到外接设备200的Type C接口201中CC引脚的工作模式为DFP模式时，则为Type C接口110-1的CC引脚配置的传输模式为UFP模式；接口 芯片110-2在识别到外接设备200的Type C接口201中CC引脚的工作模式为UFP模式时，则为Type C接口110-1的CC引脚配置的传输模式为DFP模式；接口芯片110-2在识别到外接设备200的Type C接口201中CC引脚的工作模式为DRP模式时，则通过Type C接口110-1的CC引脚与外接设备200的接口芯片进行协商，从而确定Type C接口110-1的CC引脚的传输模式。
考虑到终端100处于图1c所示的与外接设备200连接阶段时，也有可能会出现运动状态变化、显示屏被点亮等情况，为了不影响终端100与外接设备200之间数据或电能的传输，在一种可行的实现方式中，处理器101还可以从接口芯片110-2获取Type C接口110-1的CC引脚当前的工作模式；在CC引脚当前的工作模式为传输模式时，停止控制接口芯片110-2将Type C接口110-1的CC引脚配置为低电平模式或高低电平交替模式。
具体实现时，处理器101可以周期性从接口芯片110-2获取Type C接口110-1的CC引脚当前的工作模式，也可以在确定控制接口芯片110-2配置Type C接口110-1的CC引脚的工作模式后，获取CC引脚的当前工作模式，若CC引脚当前处于传输模式，则不执行对接口芯片的控制。显然，也可以由接口芯片110-2在CC引脚的工作模式为上述传输模式时，拒绝执行处理器101的控制信号，同样可以避免改变CC引脚当前的传输模式。
基于相同的技术构思，本申请实施例还提供一种Type C接口防腐蚀方法，该方法可以应用于上述任一实施例所提供的终端中的处理器。以图6所示终端为例，图8为本申请实施例提供的一种Type C接口防腐蚀方法流程示意图，如图8所示，主要包括：
S801：根据运动传感器106监测到的终端100的运动状态，在确定终端100的运动状态由移动状态进入静止状态时，控制接口芯片110-2将Type C接口110-1的CC引脚配置为低电平模式。
可选的，该方法还包括：
从接口芯片110-2获取VBUS引脚的电压状态；该VBUS引脚的电压状态是接口芯片110-2根据VBUS引脚的VBUS电压是否低于预设阈值确定的；
在确定终端100的运动状态由移动状态进入静止状态且VBUS引脚处于低于预设阈值的第一电压状态时，控制接口芯片110-2将Type C接口110-1的CC引脚配置为低电平模式。
可选的，该方法还包括：
在确定终端100通过Type C接口110-1与外接设备连接时，控制接口芯片110-2将第一Type C接口的CC引脚配置为高低电平交替模式。
可选的，确定终端100通过Type C接口110-1与外接设备连接，包括：
从接口芯片110-2获取VBUS引脚的电压状态；该VBUS引脚的电压状态是接口芯片110-2根据VBUS引脚的VBUS电压是否低于预设阈值确定的；
在确定VBUS引脚处于不低于预设阈值的第二电压状态时，控制接口芯片110-2将Type C接口110-1的CC引脚配置为高低电平交替模式。
可选的，该方法还包括：
在确定终端100的运动状态由静止状态进入移动状态时，控制接口芯片110-2将Type C接口110-1的CC引脚配置为高低电平交替模式。
可选的，该方法还包括：
在确定终端100的显示屏亮屏时，控制接口芯片110-2将Type C接口110-1的CC引 脚配置为高低电平交替模式。
可选的，接口芯片110-2还用于缓存CC引脚当前的工作模式；该方法还包括：
从接口芯片110-2获取CC引脚当前的工作模式；
在CC引脚当前的工作模式为传输模式时，停止控制接口芯片110-2将CC引脚配置为低电平模式或高低电平交替模式；其中，传输模式为接口芯片110-2根据外接设备的Type C接口中CC引脚的工作模式为Type C接口110-1中的CC引脚配置的对应的工作模式。
需要说明的是，图8所示的Type C接口防腐蚀方法可视为执行图3所示的终端中处理器101所执行的方法。图8所示的Type C接口防腐蚀方法中未详尽描述的实现方式及技术效果可参见图3所示的终端中的相关描述。
基于相同的技术构思，本申请实施例还提供一种Type C接口防腐蚀装置，该装置可以运行于处理器中，如图6中的处理器101。具体的，该防腐蚀状态可以运行于处理器101的sensorhub中，使处理器101执行上述任一实施例所提供的Type C接口防腐蚀方法。如图9所示，Type C接口防腐蚀装置900包括：
控制模块901，用于根据运动传感器106监测到的终端100的运动状态，在确定终端100的运动状态由移动状态进入静止状态时，控制接口芯片110-2将Type C接口110-1的CC引脚配置为低电平模式。
可选的，Type C接口防腐蚀装置900还包括获取模式902，获取模式902用于从接口芯片110-2获取VBUS引脚的电压状态；其中，VBUS引脚的电压状态是接口芯片110-2根据Type C接口110-1中VBUS引脚的VBUS电压是否低于预设阈值确定的；
控制模块901，还用于在确定终端100的运动状态由移动状态进入静止状态且VBUS引脚处于低于所述预设阈值的第一电压状态时，控制接口芯片110-2将Type C接口110-1的CC引脚配置为低电平模式。
可选的，控制模块901还用于：在确定终端通过Type C接口110-1与外接设备连接时，控制接口芯片110-2将Type C接口110-1的CC引脚配置为高低电平交替模式。
可选的，控制模块901具体用于：在确定Type C接口110-1中的VBUS引脚处于不低于预设阈值的第二电压状态时，控制接口芯片110-2将Type C接口110-1的CC引脚配置为高低电平交替模式。
可选的，控制模块901还用于：在确定终端100的运动状态由静止状态进入移动状态时，控制接口芯片110-2将Type C接口110-1的CC引脚配置为高低电平交替模式。
可选的，控制模块901还用于：在确定终端100的显示屏亮屏时，控制接口芯片110-2将Type C接口110-1的CC引脚配置为高低电平交替模式。
可选的，接口芯片110-2还用于缓存CC引脚当前的工作模式；获取模块902还用于：从接口芯片110-2获取CC引脚当前的工作模式；
控制模块901还用于：在CC引脚当前的工作模式为传输模式时，停止控制接口芯片110-2将CC引脚配置为低电平模式或高低电平交替模式；其中，传输模式为接口芯片110-2根据外接设备的Type C接口中CC引脚的工作模式为Type C接口110-1中的CC引脚配置的对应的工作模式。
需要说明的是，图9所示的Type C接口防腐蚀装置900可用于执行图8所示的Type C接口防腐蚀方法，图9所示的Type C接口防腐蚀装置900中未详尽描述的实现方式可参见图8所示的Type C接口防腐蚀方法中的相关描述。尽管已描述了本申请实施例的优选实施 例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请实施例范围的所有变更和修改。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的精神和范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包括这些改动和变型在内。

Claims (20)

  1. 一种终端，其特征在于，包括：处理器、接口芯片、运动传感器及第一Type C接口；
    所述处理器分别与所述运动传感器和所述接口芯片连接；所述接口芯片分别与所述处理器和所述第一Type C接口中的CC引脚连接；
    所述运动传感器，用于监测所述终端的运动状态；
    所述处理器，用于根据所述运动传感器监测到的终端的运动状态，在确定所述终端的运动状态由移动状态进入静止状态时，控制所述接口芯片将所述第一Type C接口的CC引脚配置为低电平模式。
  2. 如权利要求1所述的终端，其特征在于，所述接口芯片，还与所述第一Type C接口中的VBUS引脚连接，用于获取所述VBUS引脚的VBUS电压；
    所述处理器还用于：
    从所述接口芯片获取所述VBUS引脚的电压状态；所述VBUS引脚的电压状态是所述接口芯片根据所述VBUS引脚的VBUS电压是否低于预设阈值确定的；
    在确定所述终端的运动状态由移动状态进入静止状态且所述VBUS引脚处于低于所述预设阈值的第一电压状态时，控制所述接口芯片将所述第一Type C接口的CC引脚配置为低电平模式。
  3. 如权利要求1或2所述的终端，其特征在于，所述处理器还用于：在确定所述终端通过所述第一type C接口与外接设备连接时，控制所述接口芯片将所述第一Type C接口的CC引脚配置为高低电平交替模式。
  4. 如权利要求3所述的终端，其特征在于，所述处理器具体用于：
    从所述接口芯片获取所述VBUS引脚的电压状态；所述VBUS引脚的电压状态是所述接口芯片根据所述VBUS引脚的VBUS电压是否低于预设阈值确定的；
    在确定所述VBUS引脚处于不低于所述预设阈值的第二电压状态时，控制所述接口芯片将所述第一Type C接口的CC引脚配置为所述高低电平交替模式。
  5. 如权利要求1或2所述的终端，其特征在于，所述处理器还用于：在确定所述终端的运动状态由静止状态进入移动状态时，控制所述接口芯片将所述第一Type C接口的CC引脚配置为高低电平交替模式。
  6. 如权利要求1或2所述的终端，其特征在于，所述处理器还用于：
    在确定所述终端的显示屏亮屏时，控制所述接口芯片将所述第一Type C接口的CC引脚配置为高低电平交替模式。
  7. 如权利要求3至6中任一项所述的终端，其特征在于，所述接口芯片还用于缓存所述CC引脚当前的工作模式；
    所述处理器，还用于：
    从所述接口芯片获取所述CC引脚当前的工作模式；
    在所述CC引脚当前的工作模式为传输模式时，停止控制所述接口芯片将所述CC引脚配置为低电平模式或高低电平交替模式；所述传输模式为所述接口芯片根据外接设备的Type C接口中第二Type C接口中CC引脚的工作模式为所述CC引脚配置的对应的工作模式。
  8. 如权利要求3至7中任一项所述的终端，其特征在于，所述接口芯片是根据所述处理器提供的控制信号配置所述CC引脚的工作模式的；
    所述接口芯片包括控制电路、上拉电源、上拉开关、上拉电阻、下拉开关和下拉电阻；
    所述上拉电阻的一端与所述上拉电源连接，所述上拉电阻的另一端与所述上拉开关的第一电极连接，所述上拉开关的第二电极与所述CC引脚相连；
    所述下拉电阻的一端接地，所述下拉电阻另一端与所述下拉开关的第一电极连接，所述下拉开关的第二电极与所述CC引脚连接；
    所述控制电路，分别与所述上拉开关和所述下拉开关的控制电极连接，用于根据所述处理器的控制信号控制所述上拉开关和下拉开关的开启和断开。
  9. 如权利要求8所述的终端，其特征在于，所述控制电路具体用于：根据第一控制信号断开所述上拉开关和所述下拉开关。
  10. 如权利要求9所述的终端，其特征在于，所述终端还包括第一电阻；
    所述第一电阻的一端与所述CC引脚相连，所述第一电阻的另一端接地，所述第一电阻用于为所述CC引脚提供放电路径。
  11. 如权利要求8至10中任一项所述的终端，其特征在于，所述控制电路还用于：根据第二控制信号周期性交替开启所述上拉开关和所述下拉开关；在交替开启所述上拉开关和所述下拉开关若干个周期之后的预设时间间隔内，保持断开所述第一开关和所述第二开关，并在所述预设间接间隔之后，再次交替开启所述上拉开关和所述下拉开关若干个周期，直至接收到所述第一控制信号或识别到所述第二Type C接口中CC引脚的工作模式。
  12. 如权利要求1至11任一项所述的终端，其特征在于，所述接口芯片包括功率传输PD芯片，或，CC控制controller芯片。
  13. 如权利要求1至12任一项所述的终端，其特征在于，所述运动传感器包括加速度传感器Gsensor，和/或，陀螺仪，和/或，重力传感器。
  14. 一种Type C接口防腐蚀方法，其特征在于，应用于终端内的处理器，所述终端还包括接口芯片、第一Type C接口和运动传感器，所述处理器分别与所述接口芯片和所述运动传感器连接，所述接口芯片分别与所述处理器和所述第一Type C接口连接，所述方法包括：
    根据所述运动传感器监测到的终端的运动状态，在确定所述终端的运动状态由移动状态进入静止状态时，控制所述接口芯片将所述第一Type C接口的CC引脚配置为低电平模式。
  15. 如权利要求14所述的方法，其特征在于，所述方法还包括：
    从所述接口芯片获取所述VBUS引脚的电压状态；所述VBUS引脚的电压状态是所述接口芯片根据所述VBUS引脚的VBUS电压是否低于预设阈值确定的；
    在确定所述终端的运动状态由移动状态进入静止状态且所述VBUS引脚处于低于所述预设阈值的第一电压状态时，控制所述接口芯片将所述第一Type C接口的CC引脚配置为低电平模式。
  16. 如权利要求14或15所述的方法，其特征在于，还包括：
    在确定所述终端通过所述第一Type C接口与外接设备连接时，控制所述接口芯片将所述第一Type C接口的CC引脚配置为高低电平交替模式。
  17. 如权利要求16所述的方法，其特征在于，确定所述终端通过所述第一Type C接 口与外接设备连接，包括：
    从所述接口芯片获取所述VBUS引脚的电压状态；所述VBUS引脚的电压状态是所述接口芯片根据所述VBUS引脚的VBUS电压是否低于预设阈值确定的；
    在确定所述VBUS引脚处于不低于所述预设阈值的第二电压状态时，控制所述接口芯片将所述第一Type C接口的CC引脚配置为所述高低电平交替模式。
  18. 如权利要求14或15所述的方法，其特征在于，还包括：
    在确定所述终端的运动状态由静止状态进入移动状态时，控制所述接口芯片将所述第一Type C接口的CC引脚配置为高低电平交替模式。
  19. 如权利要求14或15所述的方法，其特征在于，还包括：
    在确定所述终端的显示屏亮屏时，控制所述接口芯片将所述第一Type C接口的CC引脚配置为高低电平交替模式。
  20. 如权利要求16至19中任一项所述的方法，其特征在于，所述接口芯片还用于缓存所述CC引脚当前的工作模式；所述方法还包括：
    从所述接口芯片获取所述CC引脚当前的工作模式；
    在所述CC引脚当前的工作模式为传输模式时，停止控制所述接口芯片将所述CC引脚配置为低电平模式或高低电平交替模式；所述传输模式为所述接口芯片根据外接设备的第二Type C接口中CC引脚的工作模式为所述CC引脚配置的对应的工作模式。
PCT/CN2018/096893 2018-07-24 2018-07-24 一种终端及Type C接口防腐蚀方法 Ceased WO2020019170A1 (zh)

Priority Applications (6)

Application Number Priority Date Filing Date Title
CN201880078065.4A CN111433756B (zh) 2018-07-24 2018-07-24 一种终端及Type C接口防腐蚀方法
PCT/CN2018/096893 WO2020019170A1 (zh) 2018-07-24 2018-07-24 一种终端及Type C接口防腐蚀方法
EP18927724.7A EP3812909B1 (en) 2018-07-24 2018-07-24 Terminal, and type c interface anti-corrosion method
RU2021104296A RU2764146C1 (ru) 2018-07-24 2018-07-24 Терминал и способ защиты от коррозии интерфейса type c
JP2021503921A JP7270719B2 (ja) 2018-07-24 2018-07-24 端末およびＴｙｐｅＣインタフェース防食方法
US17/261,961 US11947481B2 (en) 2018-07-24 2018-07-24 Terminal and type C interface anti-corrosion method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/096893 WO2020019170A1 (zh) 2018-07-24 2018-07-24 一种终端及Type C接口防腐蚀方法

Publications (1)

Publication Number Publication Date
WO2020019170A1 true WO2020019170A1 (zh) 2020-01-30

Family

ID=69181097

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/096893 Ceased WO2020019170A1 (zh) 2018-07-24 2018-07-24 一种终端及Type C接口防腐蚀方法

Country Status (6)

Country Link
US (1) US11947481B2 (zh)
EP (1) EP3812909B1 (zh)
JP (1) JP7270719B2 (zh)
CN (1) CN111433756B (zh)
RU (1) RU2764146C1 (zh)
WO (1) WO2020019170A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113030794B (zh) * 2021-03-02 2022-07-15 Oppo广东移动通信有限公司 设备检测方法及装置、计算机可读介质和电子设备
CN115575452B (zh) * 2022-02-25 2024-03-26 荣耀终端有限公司 进液检测电路和电子设备
CN115185863A (zh) * 2022-07-11 2022-10-14 北京中航世科电子技术有限公司 一种主从设备模式切换电路及其工作方法
CN116032272B (zh) * 2023-01-09 2026-03-13 上海南芯半导体科技股份有限公司 一种接口电路和接口设备
CN116069697B (zh) * 2023-03-06 2023-08-22 荣耀终端有限公司 Type-C接口电平控制方法及相关装置
CN119621633B (zh) * 2024-11-18 2026-01-27 苏州元脑智能科技有限公司 信号传输方法及装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106021161A (zh) * 2016-05-30 2016-10-12 歌尔股份有限公司 用于Type-C接口的防腐蚀电路、Type-C接口及Type-C数据线
CN108268403A (zh) * 2016-12-30 2018-07-10 维沃移动通信有限公司 一种Type-C接口保护电路及方法、移动终端
CN108268091A (zh) * 2016-12-30 2018-07-10 维沃移动通信有限公司 一种接口保护装置、移动终端和方法

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9146888B2 (en) * 2012-07-05 2015-09-29 Apple Inc. Techniques for monitoring contacts in a connector
RU2547067C2 (ru) * 2013-07-16 2015-04-10 Нух Махмудович Якупов Устройство для предотвращения коррозии
EP3126780A4 (en) * 2014-03-31 2017-12-27 Intel Corporation Inertial measurement unit for electronic devices
CN106291210B (zh) * 2015-05-22 2020-05-05 快捷半导体(苏州)有限公司 Usb接口检测器、检测方法、usb连接器及电子设备
US9400546B1 (en) 2015-06-19 2016-07-26 Cypress Semiconductor Corporation Low-power implementation of Type-C connector subsystem
US10014637B2 (en) 2015-10-20 2018-07-03 Sony Mobile Communications Inc. Connector receptacle interfacing circuit and method of operation
CN106897239A (zh) 2015-12-21 2017-06-27 小米科技有限责任公司 状态切换方法及装置
KR102628011B1 (ko) 2016-01-29 2024-01-22 삼성전자주식회사 Usb 전력 전송 장치와 이를 포함하는 시스템
EP3722960A1 (en) * 2016-03-11 2020-10-14 Huawei Technologies Co., Ltd. Method for establishing connection between devices having universal serial bus usb type-c interfaces, and terminal device
US10236683B2 (en) 2016-06-10 2019-03-19 Apple Inc. Corrosion mitigation for an external connector of an electronic device
CN105954644B (zh) 2016-06-30 2020-02-07 成绎半导体技术（上海）有限公司 一种USB Type-C接口公头智能检测和保护电路
KR102675073B1 (ko) 2016-07-12 2024-06-14 삼성전자주식회사 Usb 인터페이스를 지원하는 전자 장치 및 usb 인터페이스 제어 방법
KR102707374B1 (ko) 2016-08-31 2024-09-13 삼성전자주식회사 반도체 장치 및 그 동작 방법
JP6792389B2 (ja) 2016-09-16 2020-11-25 キヤノン株式会社 電子機器及び電子機器の制御方法
CN106648857B (zh) * 2016-11-29 2019-11-01 维沃移动通信有限公司 一种移动终端的otg功能的开启方法及移动终端
KR102663256B1 (ko) * 2016-12-23 2024-05-07 삼성전자주식회사 커넥터의 부식을 방지하는 전자 장치 및 방법
JP2018106555A (ja) 2016-12-27 2018-07-05 キヤノン株式会社 電子機器及びその制御方法、プログラム、記憶媒体
CN108268089A (zh) * 2016-12-30 2018-07-10 维沃移动通信有限公司 一种接口保护装置、移动终端和方法
CN108268389A (zh) * 2016-12-30 2018-07-10 维沃移动通信有限公司 一种设备的插入检测方法及移动终端
US10928343B2 (en) * 2017-07-07 2021-02-23 Samsung Electronics Co., Ltd. Water recognition system, electronic device including the same, and method of recognizing water thereby
CN207353874U (zh) * 2017-09-28 2018-05-11 维沃移动通信有限公司 一种TypeC接口保护电路及移动终端
EP3674904B1 (en) * 2017-09-30 2022-02-23 Huawei Technologies Co., Ltd. Electronic device having type c usb interface, control method for type c usb interface, and storage medium
CN107742912A (zh) 2017-11-08 2018-02-27 深圳天珑无线科技有限公司 充电方法、快充设备及计算机可读存储介质
CN111443625B (zh) * 2019-01-17 2024-10-18 恩智浦有限公司 一种用于串行总线连接器的腐蚀保护电路
US11275456B2 (en) * 2019-09-27 2022-03-15 Apple Inc. Finger-wearable input assembly for controlling an electronic device
CN114501123A (zh) * 2019-11-08 2022-05-13 广州视源电子科技股份有限公司 数据传输方法及数据传输设备

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106021161A (zh) * 2016-05-30 2016-10-12 歌尔股份有限公司 用于Type-C接口的防腐蚀电路、Type-C接口及Type-C数据线
CN108268403A (zh) * 2016-12-30 2018-07-10 维沃移动通信有限公司 一种Type-C接口保护电路及方法、移动终端
CN108268091A (zh) * 2016-12-30 2018-07-10 维沃移动通信有限公司 一种接口保护装置、移动终端和方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3812909A4 *

Also Published As

Publication number Publication date
EP3812909A1 (en) 2021-04-28
US20210294766A1 (en) 2021-09-23
EP3812909B1 (en) 2022-08-31
US11947481B2 (en) 2024-04-02
EP3812909A4 (en) 2021-07-07
RU2764146C1 (ru) 2022-01-13
CN111433756A (zh) 2020-07-17
CN111433756B (zh) 2022-01-28
JP2021532479A (ja) 2021-11-25
JP7270719B2 (ja) 2023-05-10

Similar Documents

Publication Publication Date Title
CN111433756B (zh) 一种终端及Type C接口防腐蚀方法
US7631126B2 (en) System and method for interfacing an electronic device with a host system
US12468365B2 (en) Charging control method, electronic device, and charging control system
EP1550045B1 (en) Device operable as both a host and a non-host (i.e. dual-mode device)
CN107635069B (zh) Uart与usb复用电路以及移动终端
CN101790225A (zh) 上网模块电源管理的方法和装置
US20170139468A1 (en) Methods and apparatus for reducing power consumption wihtin embedded systems
EP3570404B1 (en) Power supply control method and apparatus, storage medium, and electronic device
WO2020024116A1 (zh) 一种接口配置方法、终端设备及接口
CN107577508A (zh) 应用程序处理方法、装置、可读存储介质和移动终端
US20210092686A1 (en) Power supply method and electronic device therefor
CN115428571A (zh) 支持共享频带的异构通信技术的电子装置和方法
CN111988864A (zh) 基于无线充电设备的数据传输方法及装置
CN104953631A (zh) 一种电流控制方法及终端设备
CN105098854B (zh) 充电方法与电子装置
CN111026684B (zh) 接口控制方法、接口控制装置及存储介质
CN102821444B (zh) 自动功耗控制方法及系统
CN110109529A (zh) Sd卡供电控制方法、装置、存储介质及电子设备
CN115441528A (zh) 充电控制方法、装置、终端设备及存储介质
CN223986322U (zh) 一种电子设备
CN111984107B (zh) 一种终端设备供电异常处理方法和装置
CN113055515B (zh) 超宽带数据传输方法及设备支架
CN111371154B (zh) 一种充电结构、充电方法及终端
CN111638897B (zh) 系统更新方法、装置、终端设备及存储介质
WO2025145427A1 (zh) Uwb通信方法、装置、存储介质及电子设备

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18927724

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2021503921

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2018927724

Country of ref document: EP

Effective date: 20210125