WO2020038041A1 - 阵列基板、其检测方法、显示面板及显示装置 - Google Patents

阵列基板、其检测方法、显示面板及显示装置 Download PDF

Info

Publication number
WO2020038041A1
WO2020038041A1 PCT/CN2019/089333 CN2019089333W WO2020038041A1 WO 2020038041 A1 WO2020038041 A1 WO 2020038041A1 CN 2019089333 W CN2019089333 W CN 2019089333W WO 2020038041 A1 WO2020038041 A1 WO 2020038041A1
Authority
WO
WIPO (PCT)
Prior art keywords
array substrate
line
switching transistor
detection
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/089333
Other languages
English (en)
French (fr)
Inventor
程鸿飞
郝学光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Technology Development Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US16/621,416 priority Critical patent/US11569329B2/en
Priority to JP2019565314A priority patent/JP7411415B2/ja
Priority to EP19835226.2A priority patent/EP3843146A4/en
Publication of WO2020038041A1 publication Critical patent/WO2020038041A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12—Test circuits or failure detection circuits included in a display system, as permanent part thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and particularly to an array substrate, a detection method thereof, a display panel, and a display device.
  • OLED Organic Light-Emitting Diode, organic electroluminescence
  • the flexible display device is prepared by using a flexible substrate, but the edges of the flexible substrate are liable to form cracks.
  • the crack will expand in the direction of the display area. When the crack extends into the display area, water and oxygen will enter the display area through the crack and affect the service life of the flexible display panel.
  • an array substrate including:
  • a base substrate having a display area and a peripheral area surrounding the display area
  • a plurality of sub-pixel units, and a plurality of the sub-pixel unit arrays are arranged in the display area;
  • At least one first switching transistor the first switching transistor is located on a first side of the peripheral region, a drain of the first switching transistor is electrically connected to a data line, and is connected to the first switching transistor;
  • the data line connected to the drain is a first data line;
  • a gate control line which is located on a first side of the peripheral region, and the gate control line is electrically connected to a gate of the first switching transistor;
  • the detection line is located at least on a first side and a second side of the peripheral area, the first side and the second side are adjacent sides, and the detection line and the The source of the first switching transistor is electrically connected.
  • the first switching transistor is located at a first end of the corresponding first data line
  • the detection line includes a first end of the first data line, a first end extending along a first side, a second side, and a third side of the peripheral area to a second end of the first data line.
  • the third side is a side opposite to the first side.
  • the signal input end of the detection line is located on the first side; the detection line further includes: a second edge of the first data line From the third side, the second side, and the first side of the peripheral area to the second branch of the signal input terminal.
  • a portion of the detection line on the second side of the peripheral region has a plurality of circuitous routing portions.
  • the circuitous routing portion is located in the second branch.
  • a detection line is provided in the peripheral area
  • the sum of the first and second sections of the detection line surrounds the display area at least once.
  • the first branch is a circuitous branch located on a first side of the peripheral region.
  • two detection lines are provided in the peripheral area
  • the first segment and the second segment in each of the detection lines are located on the same side of the peripheral region.
  • the two detection lines are arranged symmetrically.
  • the same detection line is electrically connected to the sources of a plurality of the first switching transistors.
  • the sub-pixel units electrically connected to the first data line are all green sub-pixel units.
  • the array substrate provided in the embodiment of the present disclosure further includes second switching transistors located in the peripheral area and corresponding to each of the data lines except the first data line. ;
  • each second switching transistor is electrically connected to a display detection power line
  • the gate of each second switching transistor is electrically connected to the gate control line
  • the drain of each second switching transistor is They are electrically connected to the corresponding data lines.
  • the first switching transistor and the second switching transistor are located on a first side of the peripheral region.
  • each of the first switching transistors is electrically connected to the detection line through a selection control circuit
  • the selection control circuit is configured to control the source of the first switching transistor to be connected to the detection line when detecting whether the array substrate is cracked, and control the first electrode when detecting whether the display of the array substrate is normal.
  • a source of a switching transistor is connected to the display detection power line.
  • the display detection power line is disposed in parallel with the gate control line.
  • an embodiment of the present disclosure further provides a method for detecting an array substrate according to the first aspect, including:
  • an embodiment of the present disclosure further provides a display panel including the array substrate described in the first aspect.
  • the display panel is an organic electroluminescence display panel.
  • an embodiment of the present disclosure further provides a display device including the display panel according to the third aspect provided by an embodiment of the present disclosure.
  • FIG. 1 is one of the structural schematic diagrams of an array substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a second schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 3 is a third structural schematic diagram of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 4 is a fourth structural schematic view of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is a fifth schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 6 is a sixth schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 7 is a seventh schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram 8 of an array substrate according to an embodiment of the present disclosure.
  • FIG. 9 is a ninth schematic structural diagram of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 10 is a schematic structural view 10 of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a pixel unit in an array substrate according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic plan view of a pixel unit in an array substrate according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic cross-sectional structure view taken along the direction a-a 'of FIG. 12;
  • FIG. 14 is a flowchart of a method for detecting an array substrate according to an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides an array substrate, as shown in FIGS. 1 to 10, including:
  • a base substrate 01 having a display area A and a peripheral area B surrounding the display area A;
  • each data line da is electrically connected to a sub-pixel unit of a corresponding column;
  • At least one first switching transistor T1 the first switching transistor T1 is located on a first side of the peripheral region, and a drain of the first switching transistor T1 is electrically connected to a data line da, and data connected to a drain of the first switching transistor T1 Line da is the first data line;
  • a gate control line 012 which is located on the first side a1 of the peripheral area, and the gate control line 012 is electrically connected to the gate of the first switching transistor T1;
  • the detection line 011 is located at least on the first side a1 and the second side a2 of the peripheral area, the first side a1 and the second side a2 are adjacent sides, and the detection line 011 and the first The source of the switching transistor T1 is electrically connected.
  • At least one detection line and at least one first switching transistor electrically connected to the detection line are provided in a peripheral area.
  • the source of the first switching transistor is electrically connected to the detection line, and the drain is electrically connected to the first A data line is electrically connected, and the gate is electrically connected to the gate control line.
  • a detection signal of a preset voltage is applied to the detection line, and a gate control signal is applied to the gate control line, and the difference between the voltage of the gate control signal and the preset voltage
  • the value is smaller than the threshold voltage of the first switching transistor; when there is a crack in the area where the array substrate passes through the detection substrate, the detection line will be pulled down with the crack, so that the resistance on the detection line will increase, which will be applied to the first switching transistor.
  • the voltage of the source becomes smaller, and the first switching transistor is turned on, so the sub-pixel unit electrically connected to the first data line emits light; when there is no crack in the area where the array substrate passes through the detection line, the first switching transistor is turned off, Therefore, the sub-pixel unit electrically connected to the first data line does not emit light. Therefore, it can be detected whether there is a crack in the array substrate by detecting that the resistance on the line changes with the crack.
  • the first switching transistor T1 is located at the first end of the corresponding first data line;
  • the detection line 011 includes a first section extending from the first end of the first data line along the first side a1, the second side a2, and the third side a3 of the peripheral area B to the second end of the first data line 011a, the third side a3 is a side opposite to the first side a1. This can at least ensure that the detection line can detect the side of the array substrate along the data line direction.
  • the detection lines are generally metal traces.
  • the same detection line 011 may be connected to the sources of the plurality of first switching transistors T1.
  • the more data lines connected to the detection line, that is, the more the first switching transistor is set the higher the stability of the detection result.
  • one end of the detection line 011 for receiving the detection signal is provided with the first side a1 of the first switching transistor T1 by the peripheral region B. Lead out.
  • the side on which the first switching transistor T1 is provided is generally used to set the driving circuit, so the end of the detection line 011 for receiving the detection signal is led from the side where the driving circuit is provided, and it is more convenient to apply the detection signal to the detection line. .
  • the gate control line is connected to the gate of the first switching transistor.
  • the gate control line 012 The first side a1 located in the peripheral region B, that is, the gate control line 012 is located on the side where the first switching transistor is disposed in the peripheral region B.
  • the signal input end of the detection line is located on the first side a1; the detection line further includes: The third side a3, the second side a2, and the first side a1 of the peripheral region to the second branch 011b of the signal input terminal.
  • the second branch of the detection line is required, and the second The setting of the branch increases the effective area of the detection line, which can improve the accuracy of the detection.
  • the portion of the detection line 011 on the second side a2 of the peripheral region has a plurality of circuitous routing portions.
  • the setting of the circuitous routing portion can further increase the accuracy of the detection line detection.
  • the existence of cracks means that the more obvious the resistance change on the detection line is, the higher the detection accuracy is.
  • the circuitous routing portion is located at the second branch portion 011 b.
  • the circuitous routing portion is set at the second branch of the detection line, that is, the position near the edge of the array substrate can effectively detect the edge.
  • a crack at the location to take measures to repair and prevent water and oxygen from affecting the display area.
  • a crack in the array substrate provided by the embodiments of the present disclosure, a crack can be detected only after passing through the detection line. Therefore, in order to effectively detect a crack in a circle around the array substrate, the detection line can be set to the first The sum of the segment and the second segment surrounds the display area at least once.
  • a detection line is provided in the peripheral area B;
  • the sum of the first segment 011a and the second segment 011b of the detection line surrounds the display area A at least once.
  • the portion of the first branch located on the first side of the peripheral area may be a roundabout portion.
  • each detection line 011 The first branch 011a and the second branch 011b in each detection line 011 are located on the same side of the peripheral region B. That is, each detection line 011 surrounds the display area A for half a circle.
  • the two detection lines 011 are symmetrically disposed.
  • the detection lines 011 are in a roundabout distribution in the peripheral area B.
  • multiple detection lines may be provided on each side of the array substrate. Other inspection lines enable crack detection.
  • the sub-pixel units connected to the data line connected to the first switching transistor are all green sub-pixel units. This is because the human eye is more sensitive to green light. When a crack exists, the green sub-pixel unit emits light easily and can be detected by the human eye.
  • the color of the sub-pixel unit connected to the data line connected to the first switching transistor is not limited.
  • the array substrate further includes: located in the peripheral area B, and being in line with each data line da except the first data line.
  • each second switching transistor T2 is electrically connected to the display detection power line 013, the gate of each second switching transistor T2 is electrically connected to the gate control line 012, and the drain of each second switching transistor T2 corresponds to The data line da is electrically connected.
  • the second switching transistor and the display detection power line are provided to implement detection of the sub-pixel unit on the array substrate.
  • a voltage is provided to the display detection power line.
  • the second The switching transistor is turned off, and the corresponding sub-pixel unit does not emit light.
  • the second switching transistor is turned on and the corresponding sub-pixel unit emits light.
  • the corresponding sub-pixel unit when the difference between the voltage on the gate control line and the voltage on the display detection power line is less than the threshold voltage of the second switching transistor, the corresponding sub-pixel unit does not emit light.
  • the resistance on the detection line becomes larger, so the voltage applied to the source of the first switching transistor becomes smaller, and the first switching transistor is turned on and connected to the first switching transistor.
  • the sub-pixel units connected to the connected data lines emit light, that is, there are bright lines on the array substrate.
  • the first switching transistor is turned off, and the sub-pixel unit connected to the data line connected to the first switching transistor does not emit light, that is, the entire array substrate is a black screen.
  • the corresponding sub-pixel unit when the difference between the voltage on the gate control line and the voltage on the display detection power line is greater than the threshold voltage of the second switching transistor, the corresponding sub-pixel unit emits light. Apply a preset voltage to the detection line. When there is a crack in the array substrate, the resistance on the detection line becomes larger, so the voltage applied to the source of the first switching transistor becomes smaller, and the first switching transistor is turned on and connected to the first data line. The connected sub-pixel units emit light, that is, the array substrate has a white screen. When the array substrate has no cracks, the first switching transistor is turned off, and the sub-pixel unit connected to the first data line does not emit light, that is, there are dark lines in the white screen of the array substrate.
  • the first switching transistor T1 and the second switching transistor T2 are located on the first side a1 of the peripheral region B, that is, the first switch The transistor T1 and the second switching transistor T2 are located on the same side of the peripheral region B. It is convenient for the gate control line 012 to be electrically connected to the first switching transistor T1 and the second switching transistor T2.
  • each first switching transistor T1 is electrically connected to the detection line 011 through a selection control circuit S1;
  • the selection control circuit S1 is configured to control the source of the first switching transistor T1 and the detection line 011 to be turned on when detecting whether there is a crack in the array substrate, and to control the source and display of the first switching transistor T1 when detecting whether the display of the array substrate is normal.
  • the power line 013 is detected to be conductive. This can detect whether each sub-pixel unit on the array substrate emits light.
  • the display detection power supply line 013 and the gate control line 012 are arranged in parallel.
  • each sub-pixel unit on the array substrate in order to ensure that each sub-pixel unit on the array substrate can be detected whether to emit light, as shown in FIG. 10, for each data line, a corresponding first Two switching transistors T2, the source of each second switching transistor T2 are connected to the display detection power line 013, the gates of each second switching transistor T2 are connected to the gate control line 012, and the drains of each second switching transistor T2 Connected to the corresponding data lines da.
  • an embodiment of the present disclosure also provides a method for detecting an array substrate, as shown in FIG. 14, including:
  • the embodiments of the present disclosure provide a display panel, including an array substrate provided by any of the above embodiments, wherein the array substrate provided by the above embodiments can be applied to a liquid crystal display panel or an OLED display panel, etc., which is not limited herein. .
  • the array substrate provided by the embodiments of the present disclosure is particularly suitable for the OLED display panel.
  • a sub-pixel unit when an array substrate is applied to an OLED display panel, a sub-pixel unit generally includes a pixel circuit. Taking the most basic pixel circuit as an example, as shown in FIG. 11, it includes a switching transistor M1, a driving transistor M2, a storage capacitor C, and an OLED. Lighting unit. The planar structure of the sub-pixel unit is shown in FIG. 12.
  • FIG. 13 a cross-sectional view of a pixel region according to an embodiment of the present disclosure is shown in FIG. 13.
  • base substrate 01 active layer 21, gate insulating layer 22, gate 23, interlayer insulating layer 24, source 25 and drain 26, data line da, passivation layer 27, flat layer 28, and anode 29 ,
  • the anode 29 is connected to the drain 26 through a via.
  • the active layer 21 may be low-temperature polysilicon or oxide, which is not limited herein.
  • the gate, source, and drain can be made of metal materials such as Cu, Al, Mo, Ti, Cr, and W, or an alloy of these materials, and can be a single-layer structure or Multi-layer structures, such as Mo ⁇ Al ⁇ Mo, Ti ⁇ Cu ⁇ Ti, or MoTi ⁇ Cu, are not limited here.
  • the gate insulating layer may be silicon nitride or silicon oxide; the gate insulating layer may be a single-layer structure, and the gate insulating layer may also be a multi-layer structure, such as silicon oxide ⁇ silicon nitride. Not limited.
  • the interlayer insulating layer may be silicon nitride or silicon oxide; the interlayer insulating layer may be a single-layer structure, and the gate insulating layer may also be a multi-layer structure, such as silicon oxide ⁇ silicon nitride. Not limited.
  • the passivation layer may be silicon nitride or silicon oxide; the passivation layer may be a single-layer structure, and the gate insulating layer may also be a multilayer structure, such as silicon oxide ⁇ silicon nitride, which is not limited herein. .
  • the flat layer may be made of a resin material
  • the pixel defining layer may be made of a resin material, which is not limited herein.
  • the anode may be made of ITO or ITO / Ag / ITO, which is not limited herein.
  • the cathode may be prepared by using Al or Ag, which is not limited herein.
  • an embodiment of the present disclosure further provides a display device, including a display panel provided by an embodiment of the present disclosure. Since the principle of the display device for solving the problem is similar to that of the foregoing array substrate and display panel, implementation of the display device can refer to the implementation of the foregoing array substrate and display panel, and repeated descriptions will not be repeated.
  • the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc., which is not limited herein.
  • a detection method, a display panel, and a display device thereof are provided with at least one detection line and at least one first switching transistor connected to the detection line and a source of the first switching transistor in a peripheral area. Connected to the detection line, the drain is connected to the first data line, and the gate is connected to the gate control line.
  • a detection signal of a preset voltage is applied to the detection line, and a gate control signal is applied to the gate control line, and the difference between the voltage of the gate control signal and the preset voltage
  • the value is smaller than the threshold voltage of the first switching transistor; when there is a crack in the area where the array substrate passes through the detection substrate, the detection line will be pulled down with the crack, so that the resistance on the detection line will increase, which will be applied to the first switching transistor
  • the voltage of the source becomes smaller, and the first switching transistor is turned on, so the sub-pixel unit connected to the first data line emits light; when the array substrate has no cracks in the area where the detection line passes, the first switching transistor is turned off, so The sub-pixel unit connected to the first data line does not emit light. Therefore, it can be detected whether there is a crack in the array substrate by detecting that the resistance on the line changes with the crack.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板、其检测方法、显示面板及显示装置，该阵列基板包括：衬底基板（01），衬底基板（01）具有显示区域（A）和包围显示区域（A）的周边区域（B）；多个亚像素单元，多个亚像素单元阵列排布于显示区域（A）内；多条数据线（da），各条数据线（da）与对应列的亚像素单元电连接；至少一个第一开关晶体管（T1），第一开关晶体管（T1）位于周边区域（B）的第一侧边（a1），第一开关晶体管（T1）的漏极与一数据线（da）电连接，与第一开关晶体管（T1）的漏极连接的数据线（da）为第一数据线；栅极控制线（012），栅极控制线（012）位于周边区域（B）的第一侧边（a1），栅极控制线（012）与第一开关晶体管（T1）的栅极电连接；至少一条检测线（011），检测线（011）至少位于周边区域（B）的第一侧边（a1）和第二侧边（a2），第一侧边（a1）和第二侧边（a2）为相邻的侧边，检测线（011）与第一开关晶体管（T1）的源极电连接。

Description

阵列基板、其检测方法、显示面板及显示装置
本公开要求在2018年08月24日提交中国专利局、公开号为201810973788.2、公开名称为“一种阵列基板、其检测方法及显示装置”的中国专利公开的优先权，其全部内容以引入的方式并入本公开中。
技术领域
本公开涉及显示技术领域，尤指阵列基板、其检测方法、显示面板及显示装置。
背景技术
目前，OLED(Organic Light-Emitting Diode，有机电致发光)器件被认为是最有发展潜力的平板显示器件，同时被认为是最有可能制作成柔性显示器件的显示技术。
柔性显示器件采用柔性基板制备而成，但是柔性基板的边缘容易形成裂缝(crack)。裂缝会向显示区方向扩展，当裂缝扩展至显示区时，水氧会通过裂缝进入到显示区进而影响柔性显示面板的使用寿命。
发明内容
第一方面，本公开实施例提供了阵列基板，包括：
衬底基板，所述衬底基板具有显示区域和包围所述显示区域的周边区域；
多个亚像素单元，多个所述亚像素单元阵列排布于所述显示区域内；
多条数据线，各条所述数据线与对应列的所述亚像素单元电连接；
至少一个第一开关晶体管，所述第一开关晶体管位于所述周边区域的第一侧边，所述第一开关晶体管的漏极与一所述数据线电连接，与所述第一开关晶体管的漏极连接的所述数据线为第一数据线；
栅极控制线，所述栅极控制线位于所述周边区域的第一侧边，所述栅极 控制线与所述第一开关晶体管的栅极电连接；
至少一条检测线，所述检测线至少位于所述周边区域的第一侧边和第二侧边，所述第一侧边和第二侧边为相邻的侧边，所述检测线与所述第一开关晶体管的源极电连接。
可选地，在本公开实施例提供的阵列基板中，所述第一开关晶体管位于对应的所述第一数据线的第一端；
所述检测线包括由所述第一数据线的第一端，沿所述周边区域的第一侧边、第二侧边和第三侧边延伸至所述第一数据线的第二端的第一分部，所述第三侧边为与所述第一侧边相对的侧边。
可选地，在本公开实施例提供的阵列基板中，所述检测线的信号输入端位于所述第一侧边；所述检测线还包括：由所述第一数据线的第二端沿着所述周边区域的第三侧边、第二侧边和第一侧边至所述信号输入端的第二分部。
可选地，在本公开实施例提供的阵列基板中，所述检测线在所述周边区域的第二侧边的部分具有多个迂回走线部。
可选地，在本公开实施例提供的阵列基板中，所述迂回走线部位于所述第二分部。
可选地，在本公开实施例提供的阵列基板中，所述周边区域设置有一条检测线；
所述检测线的所述第一分部与所述第二分部之和至少包围所述显示区域一圈。
可选地，在本公开实施例提供的阵列基板中，所述第一分部位于所述周边区域的第一侧边呈迂回分部。
可选地，在本公开实施例提供的阵列基板中，所述周边区域设置有两条检测线；
每条所述检测线中的所述第一分部和所述第二分部位于所述周边区域的侧边相同。
可选地，在本公开实施例提供的阵列基板中，两条所述检测线呈对称设 置。
可选地，在本公开实施例提供的阵列基板中，同一所述检测线与多个所述第一开关晶体管的源极电连接。
可选地，在本公开实施例提供的阵列基板中，与所述第一数据线所电连接的亚像素单元均为绿色亚像素单元。
可选地，在本公开实施例提供的阵列基板中，还包括：位于所述周边区域，且与除了所述第一数据线之外的其它各所述数据线一一对应的第二开关晶体管；
各所述第二开关晶体管的源极均与显示检测电源线电连接，各所述第二开关晶体管的栅极均与所述栅极控制线电连接，各所述第二开关晶体管的漏极分别与对应的数据线电连接。
可选地，在本公开实施例提供的阵列基板中，所述第一开关晶体管和所述第二开关晶体管位于所述周边区域的第一侧边。
可选地，在本公开实施例提供的阵列基板中，各所述第一开关晶体管通过选择控制电路与所述检测线电连接；
所述选择控制电路被配置为在检测所述阵列基板是否有裂缝时控制所述第一开关晶体管的源极与所述检测线导通，在检测所述阵列基板显示是否正常时控制所述第一开关晶体管的源极与所述显示检测电源线导通。
可选地，在本公开实施例提供的阵列基板中，所述显示检测电源线与所述栅极控制线平行设置。
第二方面，本公开实施例还提供了第一方面的阵列基板的检测方法，包括：
向所述检测线施加预设电压的检测信号，并向所述栅极控制线施加栅极控制信号，且所述栅极控制信号的电压与所述预设电压之间的差值小于所述第一开关晶体管的阈值电压；
当与所述第一数据线电连接的亚像素单元发光时，确定所述阵列基板存在裂缝，当与所述第一数据线电连接的亚像素单元不发光时，确定所述阵列 基板不存在裂缝。
第三方面，本公开实施例还提供了显示面板，包括第一方面所述的阵列基板。
可选地，在本公开实施例提供的显示面板中，所述显示面板为有机电致发光显示面板。
第四方面，本公开实施例还提供了显示装置，包括本公开实施例提供的第三方面所述的显示面板。
附图说明
图1为本公开实施例提供的阵列基板的结构示意图之一；
图2为本公开实施例提供的阵列基板的结构示意图之二；
图3为本公开实施例提供的阵列基板的结构示意图之三；
图4为本公开实施例提供的阵列基板的结构示意图之四；
图5为本公开实施例提供的阵列基板的结构示意图之五；
图6为本公开实施例提供的阵列基板的结构示意图之六；
图7为本公开实施例提供的阵列基板的结构示意图之七；
图8为本公开实施例提供的阵列基板的结构示意图之八；
图9为本公开实施例提供的阵列基板的结构示意图之九；
图10为本公开实施例提供的阵列基板的结构示意图之十；
图11为本公开实施例提供的阵列基板中像素单元的结构示意图；
图12为本公开实施例提供的阵列基板中像素单元的平面结构示意图；
图13为图12沿a-a’方向的剖面结构示意图；
图14为本公开实施例提供的阵列基板的检测方法的流程图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开作进一步地详细描述，显然，所描述的实施例仅是本公开一部分实施例， 而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本公开保护的范围。
附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
本公开实施例提供了阵列基板，如图1至图10所示，包括：
衬底基板01，衬底基板01具有显示区域A和包围显示区域A的周边区域B；
多个亚像素单元(图中未视出)，多个亚像素单元阵列排布于显示区域A内；
多条数据线da，各条数据线da与对应列的亚像素单元电连接；
至少一个第一开关晶体管T1，第一开关晶体管T1位于周边区域的第一侧边，第一开关晶体管T1的漏极与一数据线da电连接，与第一开关晶体管T1的漏极连接的数据线da为第一数据线；
栅极控制线012，栅极控制线012位于周边区域的第一侧边a1，栅极控制线012与第一开关晶体管T1的栅极电连接；
至少一条检测线011，检测线011至少位于周边区域的第一侧边a1和第二侧边a2，第一侧边a1和第二侧边a2为相邻的侧边，检测线011与第一开关晶体管T1的源极电连接。
本公开实施例提供的阵列基板，在周边区域设置有至少一条检测线，以及与检测线电连接的至少一个第一开关晶体管，第一开关晶体管的源极与检测线电连接，漏极与第一数据线电连接，栅极与栅极控制线电连接。当用于检测阵列基板上是否有裂缝时，向检测线施加预设电压的检测信号，并向栅极控制线施加栅极控制信号，且栅极控制信号的电压与预设电压之间的差值小于第一开关晶体管的阈值电压；当阵列基板在检测线所经过的区域有裂缝时，检测线会随着裂缝被拉细，从而检测线上的电阻变大，从而施加到第一开关晶体管源极的电压变小，使第一开关晶体管导通，所以与第一数据线所电连接的亚像素单元发光；当阵列基板在检测线所经过的区域没有裂缝时， 第一开关晶体管截止，所以与第一数据线所电连接的亚像素单元不发光。从而通过检测线上电阻会随裂缝发生变化而实现对阵列基板是否有裂缝进行检测。
可选地，在本公开实施例提供的阵列基板中，如图1至图10所示，第一开关晶体管T1位于对应的第一数据线的第一端；
检测线011包括由第一数据线的第一端，沿周边区域B的第一侧边a1、第二侧边a2和第三侧边a3延伸至第一数据线的第二端的第一分部011a，第三侧边a3为与第一侧边a1相对的侧边。这样至少可以保证检测线能够对阵列基板沿数据线方向的侧边进行检测。
在具体实施时，在本公开实施例提供的阵列基板中，检测线一般为金属走线。
具体地，在本公开实施例提供的阵列基板中，如图2至图7所示，同一检测线011可以与多个第一开关晶体管T1的源极相连。在一定范围内，检测线连接的数据线越多，即第一开关晶体管设置的越多，检测结果的稳定性越高。
可选地，在本公开实施例提供的阵列基板中，如图3至图10所示，检测线011用于接收检测信号的一端由周边区域B设置第一开关晶体管T1的第一侧边a1引出。这是由于一般设置第一开关晶体管T1的一侧是用于设置驱动电路的，因此将检测线011用于接收检测信号的一端由设置驱动电路一侧引出，向检测线施加检测信号会比较方便。
具体地，栅极控制线与第一开关晶体管的栅极连接，为了便于布线，可选地，在本公开实施例提供的阵列基板中，如图1至图10所示，栅极控制线012位于周边区域B的第一侧边a1，即栅极控制线012位于周边区域B设置第一开关晶体管的一侧。
可选地，在本公开实施例提供的阵列基板中，如图6所示，检测线的信号输入端位于第一侧边a1；检测线还包括：由第一数据线的第二端沿着周边区域的第三侧边a3、第二侧边a2和第一侧边a1至信号输入端的第二分部011b。
当一条检测线仅围绕显示区域的半圈，且检测线的信号输入端与第一开关晶体管均设置在第一侧边时，为实现检测功能需将检测线的第二分部，且第二分部的设置增加了检测线的有效面积，可以提高检测的精确度。
可选地，在本公开实施例提供的阵列基板中，如图7所示，检测线011在周边区域的第二侧边a2的部分具有多个迂回走线部。
该迂回走线部的设置，可以进一步增加检测线检测的精确度。当检测线在周边区域所占的面积越大，存在裂缝是，检测线上的电阻变化越明显，检测精度越高。
可选地，在本公开实施例提供的阵列基板中，如图7所示，迂回走线部位于第二分部011b。
越靠近阵列基板边缘的位置出现裂缝的可能性越大，因此将迂回走线部设置在检测线的第二分部处，即设置在靠近阵列基板边缘的位置处，可以有效的检测出靠近边缘位置处的裂缝，以便采取措施进行修补，防止水氧对显示区域产生影响。
在具体实施时，在本公开实施例提供的阵列基板中，当裂缝经过检测线时才能被检测到，因此为了有效的检测阵列基板周边区域一圈内的裂缝，可以将检测线设置为第一分部与第二分部之和至少包围显示区域一圈。
可选地，在本公开实施例提供的阵列基板中，如图4和图5所示，周边区域B设置有一条检测线；
该检测线的第一分部011a与第二分部011b之和至少包围显示区域A一圈。
为了保证检测线在第一侧边的部分为有效检测区域，可以将第一分部位于周边区域的第一侧边的部分为呈迂回分部。
或者，为了避免当一条检测线发生断路后影响整个阵列基板的检测，可选地，在本公开实施例提供的阵列基板中，如图6至图10所示，周边区域B设置有两条检测线011；
每条检测线011中的第一分部011a和第二分部011b位于周边区域B的 侧边相同。即各检测线011包围显示区域A半圈。
可选地，在本公开实施例提供的阵列基板中，如图6至图10所示，两条检测线011呈对称设置。
在具体实施时，在本公开实施例提供的阵列基板中，当检测线在周边区域所占的面积越大，当有裂缝时，检测线上的电阻变化越明显，检测精度越高，因此，可选地，在本公开实施例提供的阵列基板中，如图5和图7所示，检测线011在周边区域B呈迂回分布。
进一步地，在本公开实施例提供的阵列基板中，为了避免检测线断路后不能实现裂缝检测，在阵列基板的每一侧，可以设置多条检测线，这样，当其中一条断路后，还有其它的检测线能够实现裂缝检测。
可选地，在本公开实施例提供的阵列基板中，与第一开关晶体管连接的数据线所连接的亚像素单元均为绿色亚像素单元。这是因为人眼对绿光比较敏感，采用有裂缝存在时，绿色亚像素单元发光容易被人眼察觉。在具体实施时，对与第一开关晶体管连接的数据线所连接的亚像素单元的颜色不作限定。
可选地，在本公开实施例提供的阵列基板中，如图8和图9所示，阵列基板还包括：位于周边区域B，且与除了第一数据线之外的其它各数据线da一一对应的第二开关晶体管T2；
各第二开关晶体管T2的源极均与显示检测电源线013电连接，各第二开关晶体管T2的栅极均与栅极控制线012电连接，各第二开关晶体管T2的漏极分别与对应的数据线da电连接。
在具体实施时，设置第二开关晶体管以及显示检测电源线是为了实现对阵列基板上的亚像素单元实现检测。当检测亚像素单元是否能点亮时，向显示检测电源线提供电压，当栅极控制线上的电压和显示检测电源线上的电压的差值小于第二开关晶体管的阈值电压时，第二开关晶体管截止，对应的亚像素单元不发光。当栅极控制线上的电压和显示检测电源线上的电压的差值大于第二开关晶体管的阈值电压时，第二开关晶体管导通，对应的亚像素单 元发光。
具体地，当栅极控制线上的电压和显示检测电源线上的电压的差值小于第二开关晶体管的阈值电压，对应的亚像素单元不发光时。向检测线施加预设电压，当阵列基板有裂缝时，检测线上的电阻变大，从而施加到第一开关晶体管源极的电压变小，使第一开关晶体管导通，与第一开关晶体管连接的数据线所连接的亚像素单元发光，即阵列基板上存在亮线。当阵列基板没有裂缝时，第一开关晶体管截止，与第一开关晶体管连接的数据线所连接的亚像素单元不发光，即整个阵列基板为黑屏。
具体地，当栅极控制线上的电压和显示检测电源线上的电压的差值大于第二开关晶体管的阈值电压，对应的亚像素单元发光时。向检测线施加预设电压，当阵列基板有裂缝时，检测线上的电阻变大，从而施加到第一开关晶体管源极的电压变小，使第一开关晶体管导通，与第一数据线连接的亚像素单元发光，即阵列基板为白色画面。当阵列基板没有裂缝时，第一开关晶体管截止，与第一数据线连接的亚像素单元不发光，即阵列基板的白画面中存在暗线。
可选地，在本公开实施例提供的阵列基板中，如图8至图10所示，第一开关晶体管T1和第二开关晶体管T2位于周边区域B的第一侧边a1，即第一开关晶体管T1和第二开关晶体管T2位于周边区域B的同一侧。方便栅极控制线012与第一开关晶体管T1和第二开关晶体管T2电连接。
可选地，在本公开实施例提供的阵列基板中，如图9所示，各第一开关晶体管T1通过选择控制电路S1与检测线011电连接；
选择控制电路S1被配置为在检测阵列基板是否有裂缝时控制第一开关晶体管T1的源极与检测线011导通，在检测阵列基板显示是否正常时控制第一开关晶体管T1的源极与显示检测电源线013导通。这样可以对阵列基板上的每一亚像素单元是否发光进行检测。
可选地，在本公开实施例提供的阵列基板中，如图8至图10所示，显示检测电源线013与栅极控制线012平行设置。
可选地，在本公开实施例提供的阵列基板中，为了保证可以对阵列基板上的每一亚像素单元是否发光进行检测，如图10所示，针对每一数据线，均设置对应的第二开关晶体管T2，各第二开关晶体管T2的源极均与显示检测电源线013相连，各第二开关晶体管T2的栅极均与栅极控制线012相连，各第二开关晶体管T2的漏极分别与对应的数据线da相连。
基于同一发明构思，本公开实施例还提供了一种阵列基板的检测方法，如图14所示，包括：
S1401、向检测线施加预设电压的检测信号，并向栅极控制线施加栅极控制信号，且栅极控制信号的电压与预设电压之间的差值小于第一开关晶体管的阈值电压；
S1402、当与第一数据线电连接的亚像素单元发光时，确定阵列基板存在裂缝；
S1403、当与第一数据线电连接的亚像素单元不发光时，确定阵列基板不存在裂缝。
基于同一发明构思，本公开实施例提供了显示面板，包括上述任一实施例提供的阵列基板，其中，上述实施例提供的阵列基板可以应用于液晶显示面板或OLED显示面板等，在此不作限定。
由于裂缝对OLED显示面板的影响尤为重要，因此，本公开实施例提供的阵列基板尤为适用于OLED显示面板。
具体地，当阵列基板应用于OLED显示面板时，亚像素单元一般包括像素电路，以最基本的像素电路为例，如图11所示，包括开关晶体管M1、驱动晶体管M2、存储电容C和OLED发光单元。其中，亚像素单元的平面结构图如图12所示。
在具体实施时，本公开实施例的像素区剖面图如图13所示。包括衬底基板01、有源层21、栅极绝缘层22、栅极23、层间绝缘层24、源极25和漏极26、数据线da、钝化层27、平坦层28、阳极29、像素界定层30、发光层31、阴极32。阳极29通过过孔连接漏极26。
本公开实施例中，有源层21可以为低温多晶硅或氧化物，在此不作限定。
本公开实施例中，栅极、源极、漏极可以采用Cu、Al、Mo、Ti、Cr、W等金属材料制备，也可以采用这些材料的合金制备，可以是单层结构，也可以采用多层结构，如Mo\Al\Mo、Ti\Cu\Ti或MoTi\Cu等，在此不作限定。
本公开实施例中，栅极绝缘层可以采用氮化硅或氧化硅；栅极绝缘层可以是单层结构，栅极绝缘层也可以是多层结构，例如氧化硅\氮化硅，在此不作限定。
本公开实施例中，层间绝缘层可以采用氮化硅或氧化硅；层间绝缘层可以是单层结构，栅极绝缘层也可以是多层结构，例如氧化硅\氮化硅，在此不作限定。
本公开实施例中，钝化层可以采用氮化硅或氧化硅；钝化层可以是单层结构，栅极绝缘层也可以是多层结构，例如氧化硅\氮化硅，在此不作限定。
本公开实施例中，平坦层可以采用树脂材料制备，像素界定层可以采用树脂材料制备，在此不作限定。
本公开实施例中，阳极可采用ITO、或者ITO/Ag/ITO制备，在此不作限定。
本公开实施例中，阴极可采用Al或者Ag制备，在此不作限定。
基于同一发明构思，本公开实施例还提供了显示装置，包括本公开实施例提供的显示面板。由于该显示装置解决问题的原理与前述一种阵列基板及显示面板相似，因此该显示装置的实施可以参见前述阵列基板及显示面板的实施，重复之处不再赘述。
在具体实施时，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件，在此不作限定。
本公开实施例提供的上述阵列基板，其检测方法、显示面板及显示装置，在周边区域设置有至少一条检测线，以及与检测线连接的至少一个第一开关晶体管，第一开关晶体管的源极与检测线连接，漏极与第一数据线连接，栅 极与栅极控制线连接。当用于检测阵列基板上是否有裂缝时，向检测线施加预设电压的检测信号，并向栅极控制线施加栅极控制信号，且栅极控制信号的电压与预设电压之间的差值小于第一开关晶体管的阈值电压；当阵列基板在检测线所经过的区域有裂缝时，检测线会随着裂缝被拉细，从而检测线上的电阻变大，从而施加到第一开关晶体管源极的电压变小，使第一开关晶体管导通，所以与第一数据线连接的亚像素单元发光；当阵列基板在检测线所经过的区域没有裂缝时，第一开关晶体管截止，所以与第一数据线连接的亚像素单元不发光。从而通过检测线上电阻会随裂缝发生变化而实现对阵列基板是否有裂缝进行检测。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (19)

  1. 一种阵列基板，其中，包括：
    衬底基板，所述衬底基板具有显示区域和包围所述显示区域的周边区域；
    多个亚像素单元，多个所述亚像素单元阵列排布于所述显示区域内；
    多条数据线，各条所述数据线与对应列的所述亚像素单元电连接；
    至少一个第一开关晶体管，所述第一开关晶体管位于所述周边区域的第一侧边，所述第一开关晶体管的漏极与一所述数据线电连接，与所述第一开关晶体管的漏极连接的所述数据线为第一数据线；
    栅极控制线，所述栅极控制线位于所述周边区域的第一侧边，所述栅极控制线与所述第一开关晶体管的栅极电连接；
    至少一条检测线，所述检测线至少位于所述周边区域的第一侧边和第二侧边，所述第一侧边和第二侧边为相邻的侧边，所述检测线与所述第一开关晶体管的源极电连接。
  2. 如权利要求1所述的阵列基板，其中，所述第一开关晶体管位于对应的所述第一数据线的第一端；
    所述检测线包括由所述第一数据线的第一端，沿所述周边区域的第一侧边、第二侧边和第三侧边延伸至所述第一数据线的第二端的第一分部，所述第三侧边为与所述第一侧边相对的侧边。
  3. 如权利要求2所述的阵列基板，其中，所述检测线的信号输入端位于所述第一侧边；所述检测线还包括：由所述第一数据线的第二端沿着所述周边区域的第三侧边、第二侧边和第一侧边至所述信号输入端的第二分部。
  4. 如权利要求3所述的阵列基板，其中，所述检测线在所述周边区域的第二侧边的部分具有多个迂回走线部。
  5. 如权利要求4所述的阵列基板，其中，所述迂回走线部位于所述第二分部。
  6. 如权利要求3所述的阵列基板，其中，所述周边区域设置有一条检测 线；
    所述检测线的所述第一分部与所述第二分部之和至少包围所述显示区域一圈。
  7. 如权利要求6所述的阵列基板，其中，所述第一分部位于所述周边区域的第一侧边呈迂回分部。
  8. 如权利要求3-5任一项所述的阵列基板，其中，所述周边区域设置有两条检测线；
    每条所述检测线中的所述第一分部和所述第二分部位于所述周边区域的侧边相同。
  9. 如权利要求8所述的阵列基板，其中，两条所述检测线呈对称设置。
  10. 如权利要求1-7任一项所述的阵列基板，其中，同一所述检测线与多个所述第一开关晶体管的源极电连接。
  11. 如权利要求1-7任一项所述的阵列基板，其中，与所述第一数据线所电连接的亚像素单元均为绿色亚像素单元。
  12. 如权利要求1-7任一项所述的阵列基板，其中，还包括：位于所述周边区域，且与除了所述第一数据线之外的其它各所述数据线一一对应的第二开关晶体管；
    各所述第二开关晶体管的源极均与显示检测电源线电连接，各所述第二开关晶体管的栅极均与所述栅极控制线电连接，各所述第二开关晶体管的漏极分别与对应的数据线电连接。
  13. 如权利要求12所述的阵列基板，其中，所述第一开关晶体管和所述第二开关晶体管均位于所述周边区域的第一侧边。
  14. 如权利要求12所述的阵列基板，其中，各所述第一开关晶体管通过选择控制电路与所述检测线电连接；
    所述选择控制电路被配置为在检测所述阵列基板是否有裂缝时控制所述第一开关晶体管的源极与所述检测线导通，在检测所述阵列基板显示是否正常时控制所述第一开关晶体管的源极与所述显示检测电源线导通。
  15. 如权利要求13所述的阵列基板，其中，所述显示检测电源线与所述栅极控制线平行设置。
  16. 一种如权利要求1-15任一项所述的阵列基板的检测方法，其中，包括：
    向所述检测线施加预设电压的检测信号，并向所述栅极控制线施加栅极控制信号，且所述栅极控制信号的电压与所述预设电压之间的差值小于所述第一开关晶体管的阈值电压；
    当与所述第一数据线电连接的亚像素单元发光时，确定所述阵列基板存在裂缝，当与所述第一数据线电连接的亚像素单元不发光时，确定所述阵列基板不存在裂缝。
  17. 一种显示面板，其中，包括如权利要求1-15任一项所述的阵列基板。
  18. 如权利要求17所述的显示面板，其中，所述显示面板为有机电致发光显示面板。
  19. 一种显示装置，其中，包括如权利要求17或18所述的显示面板。
PCT/CN2019/089333 2018-08-24 2019-05-30 阵列基板、其检测方法、显示面板及显示装置 Ceased WO2020038041A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US16/621,416 US11569329B2 (en) 2018-08-24 2019-05-30 Array substrate and detection method therefor, display panel and display device
JP2019565314A JP7411415B2 (ja) 2018-08-24 2019-05-30 アレイ基板、その検出方法、ディスプレイパネル及びディスプレイデバイス
EP19835226.2A EP3843146A4 (en) 2018-08-24 2019-05-30 Array substrate, detection method thereof, display panel, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810973788.2A CN110858603A (zh) 2018-08-24 2018-08-24 一种阵列基板、其检测方法及显示装置
CN201810973788.2 2018-08-24

Publications (1)

Publication Number Publication Date
WO2020038041A1 true WO2020038041A1 (zh) 2020-02-27

Family

ID=69592381

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/089333 Ceased WO2020038041A1 (zh) 2018-08-24 2019-05-30 阵列基板、其检测方法、显示面板及显示装置

Country Status (5)

Country Link
US (1) US11569329B2 (zh)
EP (1) EP3843146A4 (zh)
JP (1) JP7411415B2 (zh)
CN (1) CN110858603A (zh)
WO (1) WO2020038041A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111540294A (zh) * 2020-06-04 2020-08-14 京东方科技集团股份有限公司 一种显示面板及其裂纹检测方法、显示装置

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111696459B (zh) * 2020-05-26 2023-10-20 京东方科技集团股份有限公司 检测模组、裂纹检测方法、显示面板和显示装置
CN112086050B (zh) * 2020-09-21 2023-12-26 京东方科技集团股份有限公司 显示基板、其裂纹的检测方法及显示装置
CN112259587B (zh) * 2020-10-21 2024-02-20 京东方科技集团股份有限公司 一种显示面板、制作方法、检测方法和显示装置
US12183230B2 (en) 2020-10-27 2024-12-31 Beijing Boe Technology Development Co., Ltd. Display substrate, detection method therefor, and display device
CN112419947B (zh) * 2020-11-20 2023-05-26 武汉天马微电子有限公司 一种显示面板及其裂纹检测方法、显示装置
CN112419949B (zh) * 2020-12-15 2022-04-05 武汉华星光电半导体显示技术有限公司 显示面板及显示装置
CN113487970A (zh) * 2021-07-21 2021-10-08 武汉华星光电技术有限公司 显示面板及其裂纹检测方法、移动终端
CN114415858B (zh) * 2022-01-19 2025-03-21 维信诺科技股份有限公司 触控面板及其检测方法
CN114822337A (zh) * 2022-05-05 2022-07-29 武汉天马微电子有限公司 显示面板及其检测方法、显示装置
CN115763431B (zh) * 2022-11-17 2026-02-06 武汉天马微电子有限公司 显示面板及其裂纹检测方法、显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140176844A1 (en) * 2012-12-20 2014-06-26 Japan Display Inc. Display device
CN107464512A (zh) * 2017-09-15 2017-12-12 上海天马微电子有限公司 柔性显示装置
CN107658233A (zh) * 2016-07-26 2018-02-02 三星显示有限公司 具有裂缝感测线的显示设备
CN107680481A (zh) * 2016-08-01 2018-02-09 三星显示有限公司 显示装置
CN108417561A (zh) * 2018-03-06 2018-08-17 京东方科技集团股份有限公司 一种显示面板以及显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102446857B1 (ko) * 2015-05-26 2022-09-23 삼성디스플레이 주식회사 표시 장치
KR102769951B1 (ko) * 2016-08-22 2025-02-18 삼성디스플레이 주식회사 표시 장치
KR102718898B1 (ko) * 2016-12-06 2024-10-17 삼성디스플레이 주식회사 표시 장치
CN107845646A (zh) * 2017-10-25 2018-03-27 上海中航光电子有限公司 一种阵列基板及其制作方法、显示面板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140176844A1 (en) * 2012-12-20 2014-06-26 Japan Display Inc. Display device
CN107658233A (zh) * 2016-07-26 2018-02-02 三星显示有限公司 具有裂缝感测线的显示设备
CN107680481A (zh) * 2016-08-01 2018-02-09 三星显示有限公司 显示装置
CN107464512A (zh) * 2017-09-15 2017-12-12 上海天马微电子有限公司 柔性显示装置
CN108417561A (zh) * 2018-03-06 2018-08-17 京东方科技集团股份有限公司 一种显示面板以及显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3843146A4

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111540294A (zh) * 2020-06-04 2020-08-14 京东方科技集团股份有限公司 一种显示面板及其裂纹检测方法、显示装置
CN111540294B (zh) * 2020-06-04 2023-09-12 京东方科技集团股份有限公司 一种显示面板及其裂纹检测方法、显示装置

Also Published As

Publication number Publication date
US20200388664A1 (en) 2020-12-10
JP2021535413A (ja) 2021-12-16
JP7411415B2 (ja) 2024-01-11
EP3843146A1 (en) 2021-06-30
EP3843146A4 (en) 2022-05-18
CN110858603A (zh) 2020-03-03
US11569329B2 (en) 2023-01-31

Similar Documents

Publication Publication Date Title
KR102550650B1 (ko) 표시 장치
JP7411415B2 (ja) アレイ基板、その検出方法、ディスプレイパネル及びディスプレイデバイス
US11657744B2 (en) Display device having a detection line and method for inspection thereof
US20230252923A1 (en) Display device and inspecting method thereof
CN109659335B (zh) 显示装置
CN107871764B (zh) 具有裂纹感测线的显示装置
KR102400302B1 (ko) 표시 패널 및 이의 점등 검사선 형성 방법
KR102269919B1 (ko) 터치 센서를 포함하는 표시 장치
KR20160129156A (ko) 표시 장치
US11561660B2 (en) Display apparatuses and self-capacitance touch panels thereof
CN104679369A (zh) 包括触摸传感器的柔性显示装置
US10665820B2 (en) Display device
CN110993811B (zh) 显示装置
CN110416254A (zh) 阵列基板及显示面板
US20230354659A1 (en) Display panel and display device
KR20220106264A (ko) 표시 장치 및 포토 마스크
US20260076059A1 (en) Display panel and display device
JP2025516505A (ja) 表示装置
JP2017187581A (ja) 表示装置
KR20160122901A (ko) 표시 패널
WO2016029542A1 (zh) 阵列基板及显示装置
CN106897692B (zh) 指纹识别组件和显示装置
KR20160122899A (ko) 터치 패널 및 표시 장치
KR20240144738A (ko) 표시 장치
TW202318081A (zh) 觸控顯示裝置

Legal Events

Date Code Title Description
ENP Entry into the national phase

Ref document number: 2019565314

Country of ref document: JP

Kind code of ref document: A

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19835226

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2019835226

Country of ref document: EP

Effective date: 20210324