WO2020073294A1 - 一种发光二极管芯片及其制作方法 - Google Patents

一种发光二极管芯片及其制作方法 Download PDF

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Publication number
WO2020073294A1
WO2020073294A1 PCT/CN2018/109910 CN2018109910W WO2020073294A1 WO 2020073294 A1 WO2020073294 A1 WO 2020073294A1 CN 2018109910 W CN2018109910 W CN 2018109910W WO 2020073294 A1 WO2020073294 A1 WO 2020073294A1
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Prior art keywords
conductive layer
layer
semiconductor layer
emitting diode
type semiconductor
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PCT/CN2018/109910
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English (en)
French (fr)
Inventor
张灿源
黄少华
曾晓强
徐宸科
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Xiamen Sanan Optoelectronics Technology Co Ltd
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Xiamen Sanan Optoelectronics Technology Co Ltd
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Application filed by Xiamen Sanan Optoelectronics Technology Co Ltd filed Critical Xiamen Sanan Optoelectronics Technology Co Ltd
Priority to KR1020217006656A priority Critical patent/KR20210035301A/ko
Priority to PCT/CN2018/109910 priority patent/WO2020073294A1/zh
Priority to CN201880003520.4A priority patent/CN109791964A/zh
Priority to JP2020571519A priority patent/JP7263404B2/ja
Priority to EP18936599.2A priority patent/EP3866211A4/en
Publication of WO2020073294A1 publication Critical patent/WO2020073294A1/zh
Priority to US17/225,137 priority patent/US12176459B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
    • H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/831—Electrodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/018—Bonding of wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/816—Bodies having carrier transport control structures, e.g. highly-doped semiconductor layers or current-blocking structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/83—Electrodes
    • H10H20/831—Electrodes characterised by their shape
    • H10H20/8312—Electrodes characterised by their shape extending at least partially through the bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/84—Coatings, e.g. passivation layers or antireflective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/858—Means for heat extraction or cooling
    • H10H20/8581—Means for heat extraction or cooling characterised by their material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/858—Means for heat extraction or cooling
    • H10H20/8582—Means for heat extraction or cooling characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/032—Manufacture or treatment of electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
    • H10H20/0364—Manufacture or treatment of packages of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
    • H10H20/0365—Manufacture or treatment of packages of means for heat extraction or cooling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls

Definitions

  • the present invention relates to the field of semiconductor technology, and particularly to a chip structure and manufacturing process of a light-emitting diode.
  • LEDs High-power, high-brightness light-emitting diodes
  • LEDs have highlighted their importance in the current high-brightness lighting market.
  • the horizontal structure LED with sapphire as the substrate due to the heat dissipation problem and current crowding effect of sapphire, operation at high current density is very easy to overheat and cause the chip to burn, so the high-power LED cannot adopt the horizontal structure.
  • the vertical structure LED because its substrate can be replaced with a material with good heat dissipation and thermal conductivity (for example: Si, CuW, etc.), and the vertical structure has no current crowding effect, the current can be well expanded, so it can operate at ultra high Under the current density (for example: 2.5A / mm2 or more), to achieve high-power high-brightness LED.
  • a material with good heat dissipation and thermal conductivity for example: Si, CuW, etc.
  • the vertical structure has no current crowding effect
  • the current can be well expanded, so it can operate at ultra high Under the current density (for example: 2.5A / mm2 or more), to achieve high-power high-brightness LED.
  • the current density for example: 2.5A / mm2 or more
  • the object of the present invention is to provide a thin film light-emitting diode structure with higher efficiency, higher current density, better electrical performance and reliable performance under high voltage.
  • the present invention provides a light-emitting diode chip, having:
  • a semiconductor layer sequence having an active layer between the first type semiconductor layer and the second type semiconductor layer designed to generate radiation wherein
  • the first type of semiconductor layer is located on the positive side of the semiconductor layer sequence
  • the semiconductor layer sequence comprises at least one recess whose sidewall is covered with an insulating layer, the recess extending from the back side of the semiconductor layer sequence opposite the front side through the active layer to the first type semiconductor layer,
  • the first type semiconductor layer is electrically connected by the first conductive layer passing through the recess,
  • the first conductive layer and the second conductive layer are electrically insulated from each other by means of an insulating layer extending in the recess,
  • Both the first conductive layer and the second conductive layer are located on the back side of the semiconductor layer sequence, where the first conductive layer located on the back side of the semiconductor layer sequence mainly refers to the first conductive layer excluding the recess,
  • the second conductive layer is in direct contact with the back side of the second type semiconductor layer, and the conductive layer is selected from materials with good heat dissipation.
  • a substrate for supporting and heat dissipation the substrate is not a growth substrate on which a semiconductor layer sequence is epitaxially grown, but an independent support element, and the semiconductor layer sequence has no growth substrate in the above structure.
  • no growth substrate means that the growth substrate used for growth as necessary is removed from the semiconductor layer sequence or at least greatly thinned.
  • the first conductive layer is connected to the front side of the substrate, the contact area of the first conductive layer and the back side of the first type semiconductor layer is greater than 1.5% of the area of the first type semiconductor layer, and the first conductive layer exposes at least part of the front side For setting the first electrode, at least a portion of the second conductive layer is exposed on the positive side for setting the second electrode.
  • the exposed first conductive layer and the second conductive layer have the same height.
  • the semiconductor layer to the first conductive layer it is only necessary to remove the semiconductor layer to the first conductive layer to realize the exposed window without the need to pierce through the more difficult parts such as the insulating layer or the metal layer, which shortens the process cycle and improves the process reliability,
  • the insulating layer extending from the recess is covered in the first The back side of the conductive layer and the second conductive layer.
  • the insulating layer extending from the recess covers the back side of the second conductive layer means that the insulating layer extending horizontally from the recess covers at least the back side of the partial area of the second conductive layer, in some embodiments All the back sides of the second conductive layer may cover the insulating layer.
  • the second conductive layer, especially the first conductive layer may be arranged in multiple layers in the vertical direction. There may be a structure in which the positive side covers the insulating layer. The first electrode and the second electrode face the positive side.
  • the second conductive layer is completely covered on the front side of the insulating layer, and the first electrode and the second electrode in the present invention refer to electrical contact areas, such as bonding pads, suitable for the front side Electrically contact the light-emitting diode body.
  • the first electrode and the second electrode are made on the same plane, that is, the first conductive layer and the second conductive layer are exposed to serve as a window for making the electrode.
  • the same plane is conducive to the production of the overall structure, simplifies the process, and produces contour electrodes.
  • Unequal height electrodes increase the difficulty of wire bonding and reduce the efficiency of wire bonding.
  • the first electrode and the second electrode are located on the side of the semiconductor layer sequence, which not only prevents the first electrode and / or the second electrode from being arranged above the semiconductor layer sequence and causes shielding of radiation, reduces radiation efficiency, and facilitates wire bonding.
  • the first electrode is designed to be electrically connected to the positive side of the first conductive layer
  • the second electrode is designed to be electrically connected to the positive side of the second conductive layer.
  • the first conductive layer is respectively connected to the heat dissipation substrate and the first type semiconductor layer, forming a good heat conduction channel, and guiding heat from the first type semiconductor layer to the heat dissipation substrate. Since the excitation radiation of the multi-quantum well is emitted through the first type semiconductor layer, the heat is easily accumulated in the first type semiconductor layer, and the first conductive layer of the present invention draws the heat from the first type semiconductor layer to the heat dissipation substrate well.
  • first electrode and the second electrode are directed to the positive side at the same time, the exposed first conductive layer and the second conductive layer have the same height, the exposed first conductive layer and the exposed second conductive layer are located in the semiconductor layer sequence
  • the side part is suitable for making multiple series and / or parallel structures on the growth substrate, which is advantageous as a unit component designed as a high-voltage structure.
  • the back contact area between the first conductive layer and the first type semiconductor layer is 2.3% or more to 2.8% or less of the area of the first type semiconductor layer 2.8% to less than 4% or greater than or equal to 4% to less than or equal to 6%, where greater than or equal to 4% to less than or equal to 6% is more conducive to achieving heat extraction from the first type semiconductor layer.
  • the first conductive layer and / or the second conductive layer is a metal material, and the metal conductive material has better thermal conductivity than the non-metallic conductive material.
  • the diameter of the opening of the recess is greater than or equal to 15pm to less than 32pm, or greater than or equal to 32pm to less than or equal to 401, the smaller the diameter of the opening of the recess will lead to an increase in thermal resistance, not simply by increasing the recess
  • the number to increase the total area can achieve better thermal conductivity and heat dissipation characteristics.
  • the diameter of the recess opening is greater than or equal to 34 [xm to less than or equal to 36pm, the number of recesses is 20-25.
  • the thickness of the first type semiconductor layer is not less than 2pm, the depth of the recess in the first type semiconductor layer is not less than 0.6pm, this design focuses more on solving the first The problem of heat accumulation in the type semiconductor layer.
  • the first type half The thickness of the conductor layer is 2 [xm ⁇ 3 [xm.
  • the role of the insulating layer is to electrically isolate the first conductive layer and the second conductive layer from each other.
  • the electrical isolation here does not mean that there is no electrical connection with each other, but refers to the first conductive layer and
  • the second conductive layer is not in direct electrical contact to avoid short circuits, and the materials that can be selected include silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, or ceramic.
  • the first conductive layer includes an ohmic contact layer, a metal reflective layer, a metal bonding layer, or any combination of the above.
  • the second conductive layer includes a transparent conductive layer, a metal reflective layer, a metal diffusion barrier layer, or any combination of the above layers.
  • the first conductive layer includes an ohmic contact layer having good electrical connection performance with the first type semiconductor layer, such as Cr, Ni, Au, Li, and the like.
  • the radiation-generating semiconductor layer sequence is applied or constructed between the support element, in particular between the support substrate and the semiconductor layer sequence, with a metal reflective layer that reflects at least part of the electromagnetic radiation generated in the semiconductor layer sequence back to the semiconductor
  • the radiation-generating semiconductor layer sequence is particularly a radiation-generating epitaxial layer sequence
  • the metal reflective layer material is, for example, Ag.
  • the bonding layer mainly refers to the metal material of the first conductive layer with good bonding characteristics on the side in contact with the substrate, such as common Au.
  • a TCL transparent contact layer is also added between the conductive layer and the semiconductor layer, for example, an ITO layer is added.
  • the conductive layer mentioned here includes a first conductive layer and a second The conductive layer, the semiconductor layer includes a semiconductor layer corresponding to the first type and a second conductive layer in sequence, and optionally a TCL transparent contact layer is inserted into one or both groups.
  • the material of the second conductive layer is Ag, Au, Ti, Al, Cr, Pt, TiW, Ni, or any combination of the above, wherein Ag is suitable as a metal reflective material, and TiW is suitable as a metal Coating material to prevent metal diffusion, Cr, Ni, Au are suitable as ohmic contact materials.
  • the height of the semiconductor layer sequence is preferably a thin film structure from 5 pm or more to m or less, or from 7 pm to 8 pm or less.
  • the first electrical connection layer and the second conductive layer are at least partially made and designed together, and are located on the same plane, and the bare first conductive layer and the first on the back side of the insulating layer
  • the conductive layer is made by different processes.
  • the chip includes a second conductive layer, an insulating layer and a second layer stacked in order from top to bottom A conductive layer. Since the first conductive layer is in direct contact with the heat dissipation substrate, the first conductive layer can also dissipate the heat of the insulating layer.
  • the thermal conductivity of the substrate at 100 ° C is not less than 150W / (mk), for example, Si, Cu or ceramic, especially a chip using a ceramic substrate, on the one hand, the ceramic substrate has a good Heat dissipation characteristics, cooperate with the first conductive layer to better dissipate heat from the first conductive layer, on the other hand, due to the insulating properties of the ceramic substrate, it is beneficial to make multiple semiconductors in series and / or on the same substrate in high-voltage products
  • the first conductive layer covers the entire positive side of the ceramic substrate.
  • the entire positive side of the substrate mentioned here refers to the first conductive layer covering most of the area above the substrate, but not necessarily 100% coverage Because in the actual product, some margin space may be reserved on the substrate for, for example, facilitating the separation process.
  • the present invention also provides a method of manufacturing a light-emitting diode chip, including steps:
  • Step 1 A semiconductor layer sequence is fabricated on the growth substrate by an epitaxial process such as MOCVD metal chemical vapor deposition.
  • the semiconductor layer sequence includes a first type semiconductor layer, an active layer, a second type semiconductor layer, and a first type semiconductor layer ,
  • the active layer and the second type semiconductor layer constitute a PN junction with radiation capability;
  • Step 2 Digging a recess that penetrates the second type semiconductor layer and the active layer from the back side of the second type semiconductor layer, the recess at least penetrates to the first type semiconductor layer, and the recess is one or more;
  • Step 3 Covering the conductive layer on the surface of the second type semiconductor layer in a non-recessed position. Because of the limitation of process accuracy, the surface of the second type semiconductor layer near the recess is not covered with the conductive layer.
  • the conductive layers include the same The first conductive layer and the second conductive layer on the horizontal plane cover the conductive layer, the bottom of the recess and the side wall with an insulating layer;
  • Step 4 Digging holes in the insulating layer to expose at least the first type semiconductor layer and part of the first conductive layer at the bottom of the recess;
  • Step 5 At the bottom of the recess, the insulating layer, and a portion of the first conductive layer continue to cover the material of the first conductive layer.
  • the ohmic contact layer, metal reflective layer, and The metal bonding layer and the like contacted by the substrate are defined as the first conductive layer.
  • the material of the first conductive layer in this step is an ohmic contact material at the bottom of the recess, on the insulating layer and on the exposed first conductive layer are Metal bonding layer;
  • Step 6 Directly connect the heat dissipation substrate on the back side of the first conductive layer;
  • Step 7. Remove the growth substrate
  • Step 8 Remove a part of the semiconductor layer sequence from the positive side of the first type semiconductor layer, and remove the semiconductor layer sequence until the conductive layer is exposed;
  • Step 9 A first electrode is formed on the first conductive layer of the exposed conductive layer, and a second electrode is formed on the second conductive layer.
  • the present invention provides a light emitting diode chip, and the technical effects include:
  • the first electrode and the second electrode face the positive side, the first conductive layer is in contact with the front side of the substrate, the back side of the first type semiconductor layer, the contact area is greater than 1.5% of the area of the first type semiconductor layer, through the first
  • the conductive layer leads the heat of the semiconductor layer sequence to the heat dissipation substrate, increases the reliability of the product, and in particular leads the heat of the first type semiconductor layer.
  • the current flows vertically through the semiconductor layer sequence, and has the characteristics that the current of the vertical light emitting diode is evenly distributed,
  • the first electrode and the second electrode face the positive side, and the current is evenly distributed through the recess, which facilitates the design of multiple series and / or parallel, and multiple series and / or parallel structures are fabricated on the same growth substrate, It is beneficial for the unit component (COB, chip on board market) designed as a high-voltage structure to have excellent high-voltage characteristics.
  • COB chip on board market
  • UV light is more easily absorbed by the material of the semiconductor layer sequence, and the problem of heat dissipation is amplified.
  • the heat of the first type semiconductor layer is conducted away from the heat dissipation substrate.
  • a light emitting diode element is further designed, including a plurality of light emitting diode units,
  • the semiconductor layer sequences between the light emitting diode units are isolated from each other, and the above-mentioned serial connection more refers to connecting the mutually isolated semiconductor layer sequences in series, the semiconductor layer sequence having the first type semiconductor layer and the second Active layers between types of semiconductor layers designed to produce radiation, where
  • the first type semiconductor layer is located on the positive side of the semiconductor layer sequence
  • the semiconductor layer sequence comprises one or more recesses covered with an insulating layer, the recesses extending from the back side of the semiconductor layer sequence opposite the front side through the active layer to the first type semiconductor layer, [0051]
  • the first conductive layer passes through the recess to electrically connect the first type semiconductor layer, and the second conductive layer electrically connects the second type semiconductor layer,
  • the first conductive layer and the second conductive layer are electrically insulated from each other by the insulating layer of the recess,
  • the first light emitting diode unit of the plurality of light emitting diode units exposes at least a portion of the first conductive layer, has a first electrode electrically connected to the exposed first conductive layer, and the last light emitting diode unit exposes at least the second portion
  • the conductive layer has a second electrode electrically connected to the second conductive layer, the first electrode and the second electrode are located outside the light-emitting diode element, and the light-emitting area can be concentrated inside the light-emitting diode element, which has a relatively strong light concentration;
  • the first electrode and the second electrode face the front side, the back side of the first conductive layer is connected to the front side of the substrate, and the contact area of the front side of the first conductive layer and the back side of the first type semiconductor layer is larger than that of the first type semiconductor layer 210 1.5% of area
  • An insulating layer extending from the recess covers the back side of the second conductive layer, and any two adjacent light-emitting diode units of one of the second conductive layer of the light-emitting diode unit and the first conductive layer of the other light-emitting diode unit are provided The integrally connected connection part.
  • the plurality of light emitting diode units share the same support and heat dissipation substrate, the substrate is not a growth substrate on which the semiconductor layer sequence is epitaxially grown, but an independent support element, and the semiconductor layer sequence has no growth substrate in the above structure .
  • no growth substrate means that the growth substrate used for growth as necessary is removed from the semiconductor layer sequence or at least greatly thinned.
  • At least the exposed portions of the mutually isolated semiconductor layer sequences are integrally connected, for example, one of the light emitting diode units exposes the second conductive layer, and the other light emitting diode unit exposes the first
  • the conductive layer, the two conductive layers are integrally connected, and the integrally connected connection part is exposed between the semiconductor layer sequences isolated from each other.
  • the exposed second conductive layer of the first light emitting diode unit and the exposed first conductive layer of the second light emitting diode unit have the same height, where the constant height mainly refers to the exposed second conductive layer of the first light emitting diode unit and the second light emitting diode
  • the exposed first conductive layer of the unit has the same height on the positive side.
  • the second conductive layer of the first light emitting diode unit and the first A conductive layer is isolated, and the first conductive layer of the second light emitting diode unit and the second conductive layer thereof may be isolated, where the second conductive layer of the first light emitting diode unit and the first conductive of the second light emitting diode unit
  • the layer does not refer to the entire conductive layer structure, but specifically refers to a part of the second conductive layer and a part of the second of the first light emitting diode unit close to the semiconductor layer sequence
  • the first conductive layer of the light emitting diode unit, in addition to these conductive layers, subsequent conductive layers such as a metal bonding layer may be fabricated through more processes such as evaporation.
  • each light emitting diode unit exposes a part of the insulating layer from the positive side, at least a part of the integrally connected connection part is located below the part of the insulation layer, to avoid damage to the directly exposed connection part and cause performance degradation .
  • the plurality of light-emitting diode units have the same chip structure, where the same chip structure refers to the production of periodic patterns, produced with a semiconductor layer sequence close to the first conductive layer, The structure of the second conductive layer and the insulating layer.
  • the same chip structure does not need to be exactly the same, especially the electrode (bonding wire electrode) part can be designed into different shapes or combinations according to actual needs.
  • a plurality of light-emitting diode units are fabricated by a semiconductor layer sequence co-grown on the same growth substrate.
  • the contact area of the back side of the first conductive layer and the first type semiconductor layer is 4% or more and 6% or less of the area of the first type semiconductor layer 210.
  • the contact area of the back side of the first conductive layer and the first type semiconductor layer is 4% or more and 6% or less of the area of the first type semiconductor layer 210.
  • the first conductive layer and / or the second conductive layer include a metal material, and the metal conductive material has better thermal conductivity than the non-metallic conductive material.
  • the height of the semiconductor layer sequence is not higher than 7pm, and belongs to a semiconductor thin film chip.
  • Each light emitting diode unit includes a second conductive layer, an insulating layer, and a first conductive layer that are sequentially stacked from top to bottom. Since the first conductive layer is in direct contact with the heat dissipation substrate, the first conductive layer can also dissipate the heat of the insulating layer
  • the substrate material is ceramics. Compared with metal materials, ceramics can not only ensure excellent heat dissipation characteristics, but also use insulation to improve the reliability of the entire component.
  • the first conductive layers of two adjacent light emitting diode units are separated by an insulating layer.
  • the light emitting diode element includes 3 to 6, or 7 to 9 light emitting diode units, the more light emitting diode units are connected in series, relative to the existing structure, this Invention The more it has the advantages of light concentration or heat dissipation.
  • a method for manufacturing a light-emitting diode element for manufacturing a high-voltage light-emitting device including steps:
  • Step 1 Fabricating a semiconductor layer sequence on the growth substrate, the semiconductor layer sequence includes a first type semiconductor layer, an active layer, and a second type semiconductor layer;
  • Step 2 Digging a plurality of recesses penetrating the second type semiconductor layer and the active layer from the back side of the second type semiconductor layer, and the recesses penetrate at least to the first type semiconductor layer;
  • Step 3 Cover the conductive layer on the non-recessed surface of the second type semiconductor layer, the conductive layer includes n pairs of the first conductive layer and the second conductive layer located on the same horizontal plane, where n ⁇ 2, toward the conductive layer, The bottom and side walls of the recess are covered with an insulating layer;
  • Step 4 Digging holes in the insulating layer to expose at least the first type semiconductor layer at the bottom of the recess and part of the n first conductive layers;
  • Step 5 At the bottom of the recess, the insulating layer, and the partial areas of the n first conductive layers continue to cover the material of the first conductive layer, an insulating layer is provided between the n first conductive layers to isolate them.
  • the order of text description determines the order of covering the material of the first conductive layer in the process, that is, the order can be arbitrarily adjusted according to requirements;
  • Step 6 Directly connect the heat dissipation substrate on the back side of the first conductive layer;
  • Step 7. Remove the growth substrate
  • Step 8 Remove part of the semiconductor layer sequence from the front side of the first type semiconductor layer, remove the semiconductor layer sequence to expose the first conductive layer and the second conductive layer, and form n mutually isolated semiconductor layer sequences;
  • Step 9 A first electrode is fabricated on the first conductive layer exposed by the first semiconductor layer sequence, and a second electrode is fabricated on the second conductive layer exposed by the last semiconductor layer sequence.
  • the present invention provides a light-emitting diode chip, the technical effects include: providing a high-voltage light-emitting diode with a good heat dissipation function, the structure of the light-emitting diode unit designed by the present invention can be easily manufactured in series High voltage light emitting diode array.
  • FIG. 1 is a schematic structural view of steps 1 to 3 of Example 1;
  • FIG. 2 is a schematic diagram of the structure produced in step 4 of embodiment 1;
  • FIG. 3 is a schematic diagram of the structure produced in step 5 of Embodiment 1;
  • FIG. 4 is a schematic structural view of steps 6 to 7 of embodiment 1;
  • FIG. 5 is a schematic structural diagram of steps 8 to 9 of embodiment 1;
  • FIG. 6 is a schematic plan view of the LED structure of Embodiment 1;
  • FIG. 7 to FIG. 12 are comparison graphs of the aging data of the new structure of Example 1 and the old structure of the prior art
  • FIG. 13 is a schematic structural view of steps 1 to 2 of Embodiment 7;
  • FIG. 14 is a schematic structural view of step 7 of Example 7;
  • FIG. 15 is a schematic structural view of step 7 of Example 7.
  • FIG. 16 is a schematic view of the structure made in step 5 of Example 7;
  • FIG. 17 is a schematic structural diagram of steps 6 to 9 of embodiment 7;
  • FIG. 18 is a schematic structural view of an LED of Embodiment 9;
  • FIGS. 1 to 5 show the method for manufacturing an optoelectronic semiconductor body according to the first embodiment in schematic cross-sectional views at different stages of the method.
  • Step 1 Fabricate a semiconductor layer sequence 200 as a light-emitting epitaxial layer on the growth substrate 100, the semiconductor layer sequence 200 includes a first type semiconductor layer 210, an active layer 230, and a second type semiconductor layer 220, in this embodiment
  • the semiconductor layer sequence 200 is essentially a light-emitting PN junction
  • the first type semiconductor layer 210 is an N-type semiconductor layer
  • the second type semiconductor layer 220 is a P-type semiconductor layer, or the order can be reversed according to the design
  • the active layer 230 is used for Generating a multi-quantum well for radiation; step 2.
  • Step 3 Cover the patterned conductive layer on the non-recessed surface of the second type semiconductor layer, the conductive layer includes the first conductive layer 310 and the second conductive layer 320 at the same horizontal plane, Cover the insulating layer 400 on the conductive layer, the bottom of the recess and the side walls;
  • step 4 Further fabricate a circuit structure with conductive channels, dig holes in the insulating layer 400 to remove part of the insulating material that serves as an electrical isolation barrier, and at least expose the first type semiconductor layer 210 at the bottom of the recess, Also exposed part of the first conductive layer 310;
  • step 5 At the bottom of the recess, the insulating layer 400, and the portion of the first conductive layer 310 exposed at step 4 continues to cover the material of the first conductive layer 310, so as to fill the recess with the first conductive layer 310
  • the melting point of the material of the first conductive layer 310 in this step is lower than the bonding temperature and has good fluidity, for example, Ni or Sn is adopted, which is beneficial to reduce the first
  • the holes at the internal matching layer of the conductive layer 310 increase the heat dissipation and reliability of the product;
  • step 6 Directly connect the back side of the first conductive layer 310 for supporting and dissipating the substrate 500.
  • the direct connection usually uses a metal bonding process or an adhesion process. If a bonding process is used Often, a layer of bonding metal is also made on the substrate 500 and the first conductive layer 310 before step 6, where the bonding metal is collectively the first conductive layer 310; for step 7, the growth substrate 100 is removed; [0102] Referring to FIG. 5, the structures of steps 8 to 9 are described. Step 8.
  • the semiconductor layer sequence 200 of a partial region is removed from the positive side of the first type semiconductor layer 210, and the semiconductor layer sequence 200 is removed.
  • one of the advantages of this process is that the semiconductor layer sequence 200 can be directly etched and removed to form an electrode window without removing hard materials such as an insulating medium or a conductive layer.
  • a light-emitting diode structure that can be manufactured by using the above-mentioned process method, can improve reliability, and can be simplified into a high-voltage core particle process.
  • a semiconductor layer sequence 200 for radiation which has a first type semiconductor layer 210 and a second type semiconductor layer 220, and a first type semiconductor layer 210 and a second type semiconductor layer 220
  • the active layer 230 for generating radiation is designed between, wherein the first type semiconductor layer 210 is adjacent to the positive side of the semiconductor layer sequence 200, for example based on III / V compound semiconductor materials or based on II / VI compounds semiconductors.
  • the II / V compound semiconductor material has at least elements from the third main group, such as Al, Ga, In, and elements from the fifth main group, such as B, N, P, As.
  • III / V compound semiconductor material includes a group of binary, ternary or quaternary compounds containing at least one element from the third main group and at least one element from the fifth main group, In particular, nitride compound semiconductors and phosphide compound semiconductors. Such binary, ternary or quaternary compounds can also have, for example, one or more dopants and additional components.
  • III / V compound semiconductor materials include Group III nitride compound semiconductor materials and Group III phosphide compound semiconductor materials, such as GaN, GaAs, and InGaAlP.
  • the height of the semiconductor layer sequence 200 is greater than or equal to 5 pm to less than or equal to 7 [ xm, or greater than 7 [ xm to less than or equal to 8 [ xm.
  • the height of the semiconductor layer sequence 200 is not higher than 7 ⁇ m, and considering the process performance, the semiconductor layer sequence 200 is not lower than 5 pm.
  • the semiconductor layer sequence 200 includes at least one recess covered by the insulating layer 400.
  • the number of recesses is 20-25, and the recesses are from the back side of the semiconductor layer sequence 200 opposite to the front side Extends through the active layer 230 to the first type semiconductor layer 210, the back side of the first conductive layer 310 is connected to the front side of the substrate 500, the first conductive layer 310 exposes at least part of the front side for setting the first electrode 610,
  • the conductive layer 320 has at least a portion of the exposed positive side for providing the second electrode 620, the exposed connection layer of the first electrode 610 and the second conductive layer 320 have the same height, and the height mainly means that the upper surface is located on a horizontal plane with the same height.
  • the contour design is actually It is manufactured by designing the first conductive layer 310 and the second conductive layer 320 close to the semiconductor layer sequence 200 together.
  • the first electrode 610 connected to the first conductive layer 310, the second electrode 620 connected to the second conductive layer 320, the first electrode 610 and the second electrode 620 face the positive side, and the first electrode 610 and the second electrode 620 mainly refer to It is the metal electrode used to encapsulate the wire bonding.
  • the first type semiconductor layer 210 is electrically connected by the first conductive layer 310 through the recess, the contact area of the front side of the first conductive layer 310 and the back side of the first type semiconductor layer 210 is larger than the area of the first type semiconductor layer 210 1. 5%,
  • the first conductive layer 310 and the second conductive layer 320 are electrically insulated from each other by the insulating layer 400 of the recess, and the insulating layer 400 extending from the recess covers the back sides of the first conductive layer 310 and the second conductive layer 320
  • the insulating layer 400 covering the first conductive layer 310 does not mean covering the entire back side of the first conductive layer 310, but only a partial area of the first conductive layer 310 to prevent the reduction of heat dissipation effect.
  • the material of the insulating layer 400 includes silicon oxide, silicon nitride, aluminum nitride, aluminum oxide, or ceramic.
  • the first conductive layer 310 and / or the second conductive layer 320 are metallic materials.
  • a substrate 500 for supporting and heat dissipation is made of Si, Cu or ceramic, especially a chip using a ceramic substrate 500.
  • the ceramic substrate 500 has good heat dissipation characteristics and cooperates with the first conductive layer 310 It is good to dissipate heat from the first conductive layer 310.
  • due to the insulating properties of the ceramic substrate 500 it is advantageous to form a plurality of semiconductor series structures on the same substrate 500 in a high-voltage product.
  • the material of the first conductive layer 310 and / or the second conductive layer 320 is Ag, Au, Ti, Al, Cr, Pt, TiW alloy, Ni or any combination of the above.
  • the portion where the first conductive layer 310 contacts the first electrode 610, and the portion where the second conductive layer 320 contacts the second electrode 620 are Ti, Pt, Au, Cr, which have relatively stable performance.
  • TiW alloy the material of the first conductive layer 310 used to fill the recess includes reflective materials such as Al, Cr, or Ag.
  • the second conductive layer 320 located below the light-emitting area is in turn ITO for current spreading, Ag, Ni or TiW reflecting light from the light-emitting area, and a stable metal material Ti, Pt, Au, Cr or TiW, etc.
  • FIG. 6 in order to further explain the structure of this embodiment, a schematic top view of a chip embodying the structure of the present invention from a top view is provided.
  • a plurality of light emitting surfaces are evenly distributed
  • the concave design has good current spreading and heat dissipation characteristics.
  • the first electrode 610 and the second electrode 620 are disposed outside the chip.
  • the light-emitting diode chip structure has simple and clear stacking of various materials, and has the advantages of simple manufacturing process and high reliability.
  • the aging test is performed under the condition of external interference junction temperature.
  • the conventional old structure quickly appears dead light phenomenon under the condition of 125 ° C junction temperature and 2000mA current, so the new structure of the present invention is provided More unfavorable aging test conditions, the new structure uses 125 ° C junction temperature to perform aging test under 2000mA current condition, while the old structure uses 75 ° C junction temperature to perform aging test under 1500mA current condition.
  • Figure 8 shows the forward voltage change value AV F of the new structure and the old structure within 1000 hours. For comparison, AVF is the difference from the initial forward voltage, and the difference between the two is not large.
  • Figure 9 compares the leakage current AIR of the new structure and the old structure within 1000 hours.
  • AIR is the difference between the initial leakage current
  • the new structure basically has no leakage current, and the leakage current of the old structure gradually increases as the aging process progresses. Based on the above test data, it can be basically concluded that the reliability of the new structure of the present invention is higher than that of the conventional old structure under the conditions of high temperature and large current density.
  • the aging test is performed under the condition of external interference junction temperature. Both the new structure and the old structure are subjected to the aging test under a medium current density of 1500mA at a junction temperature of 125 ° C.
  • Figure 11 compares the brightness ALOP and the forward voltage change value A VF of the new structure and the old structure within 1000 hours. It can be seen that the gap between the new structure and the old structure is relatively small within 1000 hours, and the stability is close. Compared with the brightness of the new structure and the old structure, the new structure basically has no leakage current. The leakage current of the old structure gradually increases with the progress of the aging process. Based on the above test data, it can basically be concluded that the reliability of the new structure of the present invention is higher than that of the conventional old structure under the conditions of high temperature and medium and large current density.
  • Embodiment 3 is a variation of Embodiment 2.
  • the back contact area between the first conductive layer 310 and the first type semiconductor layer 210 is enlarged, and the contact area is the area of the first type semiconductor layer 210. From 2.3% or more to 2.8% or less, from 2.8% to 4% or from 4% to 6%.
  • the diameter of the opening of the recess is greater than or equal to 15pm to less than 32pm.
  • the direct contact area of the first conductive layer 310 and the first type semiconductor layer 210 is increased to solve the heat dissipation problem of high-power products, such as large-size chips or high-voltage chips.
  • Embodiment 4 is a further design of Embodiment 3. Although the total contact area of the first conductive layer 310 and the first type semiconductor layer 210 is generally guaranteed, the heat dissipation characteristics can be improved, but if the opening diameter is small The thinner first conductive layer 310 has a thermal resistance that exceeds a linear ratio. To ensure heat dissipation in this case, the design of this embodiment is to design the recess opening to be greater than or equal to 32 pm to less than or equal to 4 (Vm. As a In a preferred embodiment, when the diameter of the recess opening is greater than or equal to 34 pm to less than or equal to 36 pm, the number of recesses is set to 20-25.
  • the thickness of the first type semiconductor layer 210 in embodiment 5 is designed to be thicker, for example, the thickness is not less than 2 pm, the recess is recessed in the depth of the first type semiconductor layer 210 Digging to no less than lpm will better extract heat from the first type semiconductor layer 210.
  • the thickness of the first type semiconductor layer 210 is 2 [xm ⁇ 3 [xm.
  • Embodiment 6 of the present invention the LED chips of Embodiment 1 to Embodiment 5 are connected by wire bonding, the first electrode 610 of the first LED chip is connected to an external circuit, and the first The second electrode 620 of the light-emitting diode chip and the first electrode 610 of the second light-emitting diode chip are connected by a gold wire.
  • a plurality of light-emitting diode chips are connected in series in series through a gold wire circuit.
  • the two electrodes 620 are connected to an external circuit to form a series of LED chip strings connected in series.
  • multiple light-emitting diode chips connected in series often have a relatively high operating voltage due to the fixed current of the external circuit.
  • the light-emitting diode chips of this structure can be conveniently designed in series, and have obvious effects under high voltage Reliability advantage.
  • Embodiment 7 of the present invention a method for manufacturing a light-emitting diode element with a relatively simple process and high reliability is disclosed for manufacturing a high-voltage light-emitting device, including the following process steps:
  • step 1 First, an epitaxial structure of a light emitting diode element is fabricated, and a semiconductor layer sequence 200 is fabricated on a growth substrate 100.
  • the semiconductor layer sequence 200 includes a first type semiconductor layer 210, an active layer 230, and a second Three types of semiconductor layers 220, three of which constitute a semiconductor PN junction; Step 2.
  • a plurality of second type semiconductor layers 220 and active layers 230 are dug from the back side of the second type semiconductor layers 220 by, for example, wet etching or dry etching The recess at least penetrates to the first type semiconductor layer 210.
  • step 3 A conductive layer is covered in a non-recessed position on the surface of the second type semiconductor layer 220, the conductive layer is discretely distributed, and a corresponding graphic design is made for subsequent circuit connection.
  • the conductive layer includes n pairs located on the same The first conductive layer 310 and the second conductive layer 320 on the horizontal plane, each pair of the first conductive layer 310 and the second conductive layer 320 are located in a separate semiconductor layer sequence 200 to be produced later, where n22 is then applied to each part of the conductive layer The bottom of the recess and the sidewall cover the insulating layer 400.
  • step 4 Digging holes in some areas of the insulating layer 400 to expose at least the first type semiconductor layer 210 at the bottom of the recess and a portion of the n first conductive layers 310, the exposed bottom of the recess Type 1 semiconducting
  • the body layer 210 and the n first conductive layers 310 are used to make electrical connection windows;
  • step 5 At the bottom of the recess, the insulating layer 400, and a part of the n first conductive layers 310 continue to cover the material of the first conductive layer 310, where the first conductive layer 310 mainly refers to A plurality of material layers are formed together, which is uniformly defined as the first conductive layer 310, and an insulating layer 400 is provided between the n first conductive layers 310 to isolate, and the electrical connection is exported to the step 3 through the newly covered first conductive layer 310 material On the first conductive layer 310 of the same height as the second conductive layer 320;
  • the heat dissipation substrate 500 is directly connected to the back side of the first conductive layer 310.
  • the heat dissipation substrate 500 includes ceramic or metal.
  • the direct connection generally uses a metal bonding process or an adhesion process. If a bonding process is used, a layer of bonding metal is often formed on the substrate 500 and the first conductive layer 310 before step 6, where the bonding metal becomes the first conductive layer 310; Step 7.
  • the growth substrate is removed 100.
  • removing the growth substrate 100 includes removing all of the growth substrate 100 or thinning the growth substrate 100; Step 8.
  • the partial semiconductor layer sequence 200 is removed from the positive side of the first type semiconductor layer 210, and the semiconductor layer is removed.
  • Sequence 200 to expose the first conductive layer 310 and the second conductive layer 320 because the design of the process can be directly removed to relatively stable materials such as the first conductive layer 310 and the second conductive layer 320, so the process is controllable, Forming n mutually isolated semiconductor layer sequences 200; Step 9.
  • the first electrode 610 is formed on the first conductive layer 310 exposed by the first semiconductor layer sequence 200, while A second electrode 620 is formed on the second conductive layer 320 exposed by the latter semiconductor layer sequence 200, and the first electrode 610 and the second electrode 620 are used to connect with an external circuit.
  • a light-emitting diode element structure mainly used for high-voltage devices is provided according to the above process.
  • the light-emitting diode units are connected in series, and the light-emitting diode element Including 3 to 6, or 7 to 9 LED units.
  • the semiconductor layer sequences 200 between the LED units are isolated from each other, and are electrically connected in series by the conductive layer inside the semiconductor layer sequence 200; the semiconductor layer sequence 200 has the first type semiconductor layer 210 and the first An active layer 230 between two types of semiconductor layers 220 designed to generate radiation, wherein the first type semiconductor layer 210 is located on the positive side of the semiconductor layer sequence 200, and the semiconductor layer sequence 200 includes one or more insulating layers 400
  • the recess which serves as a current channel, extends from the back side of the semiconductor layer sequence 200 opposite the front side through the active layer 230 to the first type semiconductor layer 210, and the first conductive layer 310 having conductive properties passes through the recess
  • the conductive layer 320 is electrically connected to the second type semiconductor layer 220, the first conductive layer 310 and the second conductive layer 320 are electrically insulated from each other by an insulating layer 400 extending from the recess, the first
  • the back side of the first conductive layer 310 is connected to the front side of the substrate 500, and the contact area of the front side of the first conductive layer 310 and the back side of the first type semiconductor layer 210 is greater than 1.5% of the area of the first type semiconductor layer 210, from the concave
  • the insulating layer 400 extending at the top covers the back side of the second conductive layer 320, any two adjacent light-emitting diode units, one of the second conductive layer 320 of the light-emitting diode unit and the first conductive layer 31 of the other light-emitting diode unit An integrally connected connection portion is provided, and the first conductive layers 310 of two adjacent light-emitting diode units are separated by an insulating layer 400. In some areas of the light emitting diode unit, a second conductive layer 320, an insulating layer 400, and a first conductive layer 310 are sequentially stacked from top to bottom.
  • a plurality of light emitting diode units share the same support and heat dissipation substrate 500.
  • the height of the semiconductor layer sequence 200 is not higher than 7 pm.
  • the first conductive layer 310 and / or the second conductive layer 320 are mainly metal materials, and may also be provided with current spreading materials such as ITO for current spreading. At least the exposed portions of the integrated connection between the semiconductor layer sequences 200 that are separated from each other are at least exposed. This structure is mainly convenient for manufacturing the isolated semiconductor layer sequence 200. The removal process only needs to be performed to the connection portion, which is easier to control in the process.
  • Embodiment 9 proposes Embodiment 9, where each LED unit exposes a portion of the insulating layer from the positive side 400, at least a part of the integrally connected connection part is located under the part of the insulating layer 400, from a structural point of view, it is only necessary to change the position of the insulating layer 400 for isolation in the manufacturing process step 5 in the horizontal direction, and the removal in step 8 The position of the semiconductor layer sequence 200 can be realized until the insulating layer 400 is exposed.
  • Embodiment 8 and Embodiment 9 a plurality of light-emitting diode units are fabricated by a semiconductor layer sequence 200 co-grown on the same growth substrate 100, and the plurality of light-emitting diode units have the same chip structure, That is, in FIGS. 11 and 12, the periodic cell structure can be seen.
  • the expansion The contact area of the first conductive layer 310 and the back side of the first type semiconductor layer 210 is designed to be greater than or equal to 4% to less than or equal to 6% of the area of the first type semiconductor layer 210.

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Abstract

本发明公开了一种发光二极管芯片，其第一电极和第二电极朝向正侧，第一导电层背侧与基板正侧直接连接，第一导电层正侧与第一类型半导体层的背侧接触面积大于第一类型半导体层面积的1.5%，第一导电层至少裸露出正侧一部分用于设置第一电极，第二导电层至少裸露出正侧一部分用于设置第二电极，裸露出的第一导电层和裸露出第二导电层等高，从凹处延伸的绝缘层覆盖在第二导电层的背侧，具有比较强的散热能力，避免或减少发光二极管芯片在大电流条件下寿命降低的情况。

Description

说明书 发明名称:一种发光二极管芯片及其制作方法 技术领域
[0001] 本发明涉及半导体技术领域， 特别涉及一种发光二极管的芯片结构和制作工艺 背景技术
[0002] 高功率高亮度发光二极管 （LED） 在当下高亮度照明市场的需求下凸显出了其 重要性。 在蓝宝石为衬底的水平结构 LED上， 由于蓝宝石的散热问题和电流拥挤 效应， 在高电流密度下操作极易过热导致芯片烧毁， 因此高功率 LED无法采用水 平结构。 而垂直结构 LED， 因其衬底可以置换成散热性和导热性良好的材料 （例 如： Si， CuW等） ， 并且垂直结构无电流拥挤效应， 电流可以很好的扩展， 所以 可以操作在超高电流密度下 （例如： 2.5A/mm2以上） ， 实现大功率高亮度 LED 。 为了获得更优的电流扩展， 如何在垂直 LED上进一步实现更高的电流密度、 亮度和可靠性实现大功率发光二极管是目前 LED市场的一个热点。
发明概述
技术问题
问题的解决方案
技术解决方案
[0003] 本发明的目的是提供一种在高压下具有更强效率、 更高的电流密度、 更好电性 能和可靠性能的薄膜发光二极管结构。 这些目的是通过独立权利要求的薄膜发 光二极管结构和制造该结构工艺方法来解决。 本发明的扩展方案和改进方案分 别在从属权利要求中说明， 它们的公开内容特此被明确地结合于说明书中。
[0004] 为了解决背景技术中关于提升亮度的需求， 一方面， 本发明提供了一种发光二 极管芯片， 具有：
[0005] 半导体层序列， 其具有在第一类型半导体层和第二类型半导体层之间的、 设计 用于产生辐射的有源层， 其中
[0006] 第一类型半导体层位于半导体层序列的正侧， [0007] 半导体层序列包含至少一个侧壁覆盖有绝缘层的凹处， 凹处从半导体层序列的 与正侧对置的背侧穿过有源层延伸到第一类型半导体层，
[0008] 与第一导电层连接的第一电极， 与第二导电层连接的第二电极，
[0009] 借助第一导电层穿过所述凹处来电连接第一类型半导体层，
[0010] 第一导电层与第二导电层借助凹处延伸的绝缘层来彼此电绝缘，
[0011] 第一导电层和第二导电层都位于半导体层序列的背侧， 此处位于半导体层序列 背侧的第一导电层主要指的是不包括凹处内的第一导电层， 第二导电层与第二 类型半导体层的背侧直接接触， 导电层选择散热性良好的材料。
[0012] 用于支撑和散热的基板， 基板并不是其上外延生长了半导体层序列的生长衬底 ， 而是独立的支承元件， 半导体层序列在上述结构中没有生长衬底。 在此， “没 有生长衬底”表示必要时为了生长而使用的生长衬底被从半导体层序列去除或者 至少被大大薄化。
[0013] 第一导电层与基板正侧连接， 第一导电层与第一类型半导体层的背侧接触面积 大于第一类型半导体层面积的 1.5%， 第一导电层至少裸露出正侧一部分用于设 置第一电极， 第二导电层至少裸露出正侧一部分用于设置第二电极， 露出的第 一导电层和第二导电层等高， 该等高设计在去除半导体层序列制作打线窗口时 ， 只需移除半导体层至第一导电层即可实现露出窗口， 而不需要打穿绝缘层或 者金属层等较难移除的部分， 缩短了工艺制程周期， 且提高了工艺可靠性， 例 如避免 ICP离子束辅助自由基刻蚀， 将金属打到半导体层序列侧壁造成电路短路 ， 又或者湿法蚀刻金属和绝缘层效率较低等问题， 从凹处延伸的绝缘层覆盖在 第一导电层和第二导电层的背侧。 在此， “从凹处延伸的绝缘层覆盖第二导电层 的背侧”， 表示从凹处向水平延伸的绝缘层至少覆盖在第二导电层的部分区域的 背侧， 在一些实施例中， 第二导电层的全部背侧可以全部覆盖绝缘层， 第二导 电层、 特别是第一导电层可以在竖直方向上多层设置， 可能存在正侧覆盖绝缘 层的结构。 第一电极和第二电极朝向正侧。 在本发明的实施例中， 第二导电层 是全部覆盖在绝缘层正侧的， 在本发明的第一电极和第二电极指的是电接触区 ， 比如接合焊盘， 适于从正侧电接触发光二极管本体。 第一电极和第二电极制 作在同一平面， 即第一导电层和第二导电层裸露出来作为制作电极的窗口位于 同一平面， 有利于整体结构的制作， 简化工艺， 制作出等高电极， 不等高电极 会增加打线的难度降低打线的效率。 第一电极和第二电极位于半导体层序列的 侧部， 既避免第一电极和 /或第二电极设置在半导体层序列的上方而造成对辐射 的遮挡， 降低辐射效率， 又方便制作打线。 第一电极被设计用于与第一导电层 正侧电连接， 相同地， 第二电极被设计用于与第二导电层正侧电连接。
[0014] 有利的是， 第一导电层分别与散热基板和第一类型半导体层连接， 构成良好的 导热通道， 将热量从第一类型半导体层引向散热基板。 由于多量子阱的激发辐 射经由第一类型半导体层射出， 热量容易在第一类型半导体层堆积， 本发明的 第一导电层将热量很好地从第一类型半导体层引出至散热基板。
[0015] 除此之外第一电极和第二电极同时朝向正侧， 露出的第一导电层和第二导电层 等高， 露出的第一导电层和露出的第二导电层位于半导体层序列的侧部， 适合 同生长衬底上制作出多颗串和 /或并联结构， 有利于作为设计成高压结构的单元 部件。
[0016] 在本发明的一些扩展实施例中， 优选的， 第一导电层与第一类型半导体层的背 侧接触面积为第一类型半导体层面积的大于等于 2.3%到小于等于 2.8%、 大于 2.8 %到小于 4%或者大于等于 4%到小于等于 6%， 其中大于等于 4%到小于等于 6%更 有利于实现热量从第一类型半导体层导出。
[0017] 根据本发明， 优选的， 第一导电层和 /或第二导电层为金属材料， 金属导电材 料相对非金属导电材料来说具有更加好的导热特性。
[0018] 根据本发明， 优选的， 凹处的开口直径大于等于 15pm到小于 32pm， 或者大于 等于 32pm至小于等于 40 1， 凹处开口直径变小将导致热阻增加， 并非是单纯依 靠增加凹处数量来提高总面积就可以实现更好的导热散热特性。
[0019] 在本发明的一些实施例中， 优选的， 当凹处开口直径大于等于 34[xm到小于等 于 36pm时， 凹处的数量为 20~25个。
[0020] 在本发明的一些扩展实施例中， 优选的， 第一类型半导体层的厚度不小于 2pm ， 凹处在第一类型半导体层内的深度不小于 0.6pm， 本设计更侧重解决第一类型 半导体层内的热量堆积问题。
[0021] 根据本发明， 优选的， 为了减少第一类型半导体层对辐射的吸收， 第一类型半 导体层厚度为 2[xm~3 [xm。
[0022] 根据本发明， 优选的， 绝缘层的作用在于将第一导电层和第二导电层彼此电隔 离， 这里说的电隔离并不是相互没有电连接， 而指的是第一导电层和第二导电 层不直接电接触， 避免短路， 可选择材料包括氧化硅、 氮化硅、 氮化铝、 氧化 铝或者陶瓷。
[0023] 根据本发明， 优选的， 第一导电层包括欧姆接触层、 金属反射层、 金属键合层 或者以上任意组合。
[0024] 根据本发明， 优选的， 第二导电层包括透明导电层、 金属反射层、 金属扩散阻 挡层或者以上各层任意组合。
[0025] 第一导电层包括与第一类型半导体层具有良好电连接性能的欧姆接触层， 比如 Cr、 Ni、 Au、 Li等。 产生辐射的半导体层序列的朝向支撑元件、 特别是支撑基 板与半导体层序列之间施加或者构建有金属反射层， 该金属反射层将在半导体 层序列中产生的电磁辐射的至少一部分反射回该半导体层序列中， 其中产生辐 射的半导体层序列特别是产生辐射的外延层序列， 金属反射层材料例如 Ag。 键 合层主要是指与基板接触一侧的具有良好键合特性的第一导电层金属材料， 比 如常见的 Au。 为了提高导电层和半导体层的接触， 降低二者电阻， 也会在导电 层和半导体层之间增加 TCL透明接触层， 例如增加一层 ITO , 这里说的导电层包 括第一导电层和第二导电层， 半导体层包括依次对应第一类型半导体层和第二 导电层， 任选在其中一组或者两组插入 TCL透明接触层。
[0026] 根据本发明， 优选的， 第二导电层的材料为 Ag、 Au、 Ti、 Al、 Cr、 Pt、 TiW、 Ni或以上的任意组合， 其中 Ag适合作为金属反射材料， TiW适合作为金属包覆 材料， 防止金属扩散， Cr、 Ni、 Au适合作为欧姆接触材料。
[0027] 根据本发明， 优选的， 半导体层序列的高度较佳为大于等于 5pm到小于等于 m的薄膜结构， 或者为大于 7pm到小于等于 8pm。
[0028] 根据本发明， 优选的， 第一电连接层和第二导电层至少部分为一起制作设计的 ， 位于同一平面上， 而裸露的第一导电层与处于绝缘层的背面侧的第一导电层 是通过不同工艺制作的。
[0029] 根据本发明， 优选的， 芯片包括从上到下依次层叠的第二导电层、 绝缘层和第 一导电层。 由于第一导电层和散热基板直接接触， 第一导电层也可导出绝缘层 的热量。
[0030] 根据本发明， 优选的， 基板在 100°C时的导热系数不小于 150W/ (m-k) , 例如 为 Si、 Cu或者陶瓷， 特别是采用陶瓷基板的芯片， 一方面陶瓷基板具有良好的 散热特性， 与第一导电层配合更好地将热量从第一导电层导出， 另一方面由于 陶瓷基板的绝缘特性， 有利于在高压产品中在同一基板上制作成多颗半导体串 联和 /或并联结构， 第一导电层覆盖在陶瓷基板的整个正侧， 这里提到的基板的 整个正侧指的是第一导电层覆盖在基板上方的绝大多数区域， 但并不一定是 100 %覆盖， 因为在实际产品中可能会在基板上预留一些用于例如便于分离工艺处理 的余量空间。
[0031] 基于上述发光二极管芯片结构， 本发明还提供了一种发光二极管芯片的制作方 法， 包括步骤：
[0032] 步骤 1、 在生长衬底上例如 MOCVD金属化学气相沉积等外延工艺制作半导体层 序列， 半导体层序列包括第一类型半导体层、 有源层、 第二类型半导体层， 第 一类型半导体层、 有源层和第二类型半导体层构成具备辐射能力的 PN结；
[0033] 步骤 2、 从第二类型半导体层背侧挖出贯穿第二类型半导体层和有源层的凹处 ， 凹处至少贯穿至第一类型半导体层， 凹处为一个或复数个；
[0034] 步骤 3、 在第二类型半导体层表面的非凹处位置覆盖导电层， 因为受到工艺精 度的限制， 在靠近凹处的第二类型半导体层表面没有覆盖导电层， 导电层包括 位于同一水平面的第一导电层和第二导电层， 向导电层、 凹处底部和侧壁覆盖 绝缘层；
[0035] 步骤 4、 在绝缘层上挖孔， 至少露出凹处底部的第一类型半导体层和部分第一 导电层；
[0036] 步骤 5、 在凹处底部、 绝缘层、 部分第一导电层继续覆盖第一导电层材料， 为 了方便描述本发明将与第一类型半导体层接触的欧姆接触层、 金属反射层、 与 基板接触的金属键合层等都定义为了第一导电层， 本步骤说的第一导电层材料 在凹处底部为欧姆接触材料、 在绝缘层上和在露出的部分第一导电层上主要为 金属键合层； [0037] 步骤 6、 在第一导电层的背侧直接连接散热基板；
[0038] 步骤 7、 去除生长衬底；
[0039] 步骤 8、 从第一类型半导体层的正侧开始移除部分半导体层序列， 移除半导体 层序列至露出导电层；
[0040] 步骤 9、 在露出的导电层的第一导电层上制作第一电极， 在第二导电层上制作 第二电极。
[0041] 与现有技术相比， 本发明提供发光二极管芯片， 技术效果包括：
[0042] 第一电极和第二电极朝向正侧， 第一导电层分别与基板正侧、 第一类型半导体 层的背侧接触， 接触面积大于第一类型半导体层面积的 1.5%， 通过第一导电层 将半导体层序列的热量导出到散热基板上， 增加产品可靠性， 特别将第一类型 半导体层的热量导出。
[0043] 在工作时电流垂直通过半导体层序列， 具有垂直发光二极管的电流均匀分布的 特性，
[0044] 第一电极和第二电极朝向正侧， 并且通过凹处实现电流均匀分布， 方便进行多 颗串联和 /或并联设计， 同生长衬底上制作出多颗串和 /或并联结构， 有利于作为 设计成高压结构的单元部件 (COB , chip on board市场) 具有优良的高压特性。
[0045] 在例如用于 UV固化领域的 UVLED特殊应用中， UV光更容易被半导体层序列 的材料吸收， 而放大散热的问题， 本发明的芯片结构的热电分离设计可以很好 地将出光面第一类型半导体层的热量从散热基板弓 I导出去。
[0046] 根据上文的发光二极管芯片结构以及制作方法， 进一步设计出一种发光二极管 元件， 包括复数个发光二极管单元，
[0047] 发光二极管单元之间采用串联式连接；
[0048] 发光二极管单元之间的半导体层序列相互隔离， 上述串联式的连接更多指的是 在将相互隔离的半导体层序列串联在一起， 半导体层序列具有在第一类型半导 体层和第二类型半导体层之间的、 设计用于产生辐射的有源层， 其中
[0049] 第一类型半导体层位于半导体层序列的正侧，
[0050] 半导体层序列包含一个或复数个覆盖有绝缘层的凹处， 凹处从半导体层序列的 与正侧对置的背侧穿过有源层延伸到第一类型半导体层， [0051] 第一导电层穿过凹处来电连接第一类型半导体层， 第二导电层电连接第二类型 半导体层，
[0052] 第一导电层与第二导电层借助凹处的绝缘层来彼此电绝缘，
[0053] 复数个发光二极管单元的第一个发光二极管单元至少裸露出部分第一导电层， 具有与其裸露的第一导电层电连接的第一电极， 最后一个发光二极管单元至少 裸露出部分第二导电层， 具有与其第二导电层电连接的第二电极， 第一电极和 第二电极位于发光二极管元件的外侧， 发光区域可集中在发光二极管元件的内 部， 具有比较强的出光集中度；
[0054] 第一电极和第二电极朝向正侧， 第一导电层背侧与基板正侧连接， 第一导电层 正侧与第一类型半导体层的背侧接触面积大于第一类型半导体层 210面积的 1.5%
， 从凹处延伸的绝缘层覆盖在第二导电层的背侧， 任意相邻的两个发光二极管 单元其中一个发光二极管单元的第二导电层与另一个发光二极管单元的第一导 电层设有一体连接的连接部。
[0055] 复数个发光二极管单元共用同一支撑和散热基板的， 基板并不是其上外延生长 了半导体层序列的生长衬底， 而是独立的支承元件， 半导体层序列在上述结构 中没有生长衬底。 在此， “没有生长衬底”表示必要时为了生长而使用的生长衬底 被从半导体层序列去除或者至少被大大薄化。
[0056] 在本发明一些实施例中， 相互隔离的半导体层序列之间至少裸露出部分一体连 接的连接部， 例如， 其中一个发光二极管单元露出第二导电层， 另一个发光二 极管单元露出第一导电层， 两个导电层一体连接， 在相互隔离的半导体层序列 之间露出一体连接的连接部。 第一发光二极管单元裸露的第二导电层和第二发 光二极管单元裸露的第一导电层等高， 此处等高主要指的是第一发光二极管单 元裸露的第二导电层和第二发光二极管单元裸露的第一导电层在正侧的高度相 等， 更进一步地， 具有相同的厚度、 材料和构造， 只需在导电层图形化时， 将 第一发光二极管单元的第二导电层和其第一导电层隔离开， 将第二发光二极管 单元的第一导电层和其第二导电层隔离开即可， 这里的第一发光二极管单元的 第二导电层和第二发光二极管单元的第一导电层并不是指整个导电层结构， 而 是特指靠近半导体层序列的部分第一发光二极管单元的第二导电层和部分第二 发光二极管单元的第一导电层， 除了这些导电层后续还会通过蒸镀等更多的工 艺制作出其他部分的导电层， 例如金属键合层。
[0057] 上述实施例中， 将每个发光二极管单元从正侧裸露出一部分绝缘层， 至少部分 一体连接的连接部位于该部分绝缘层的下方， 避免直接裸露的连接部被破坏而 造成性能降低。
[0058] 根据本发明， 优选的， 复数个发光二极管单元具有相同的芯片结构， 这里的相 同的芯片结构指的是制作周期性图形， 制得具有相接近的半导体层序列、 第一 导电层、 第二导电层以及绝缘层结构。 这里相同的芯片结构并不需要完全一模 一样， 特别是电极 （焊线电极） 部分， 可以根据实际需要设计成不同的形状或 者组合。
[0059] 根据本发明， 优选的， 复数个发光二极管单元通过在同一生长衬底上共同生长 的半导体层序列来制作而成的。
[0060] 在本发明的一些实施例中， 优选的， 第一导电层与第一类型半导体层的背侧接 触面积为第一类型半导体层 210面积的大于等于 4%到小于等于 6%， 用以适应更 高的散热要求， 例如解决在更大负载情况下的散热问题。
[0061] 在本发明的一些实施例中， 优选的， 第一导电层和 /或第二导电层包括金属材 料， 金属导电材料相对非金属导电材料来说具有更加好的导热特性。
[0062] 在本发明的一些实施例中， 优选的， 半导体层序列的高度不高于 7pm， 属于半 导体薄膜芯片。
[0063] 每个发光二极管单元包括从上到下依次层叠的第二导电层、 绝缘层和第一导电 层。 由于第一导电层和散热基板直接接触， 第一导电层也可导出绝缘层的热量
[0064] 在本发明的一些实施例中， 优选的， 基板材料为陶瓷， 相对金属材料来说， 陶 瓷既能保证优良的散热特性， 又能利用绝缘性提升整个元件的可靠性。
[0065] 在本发明的一些实施例中， 优选的， 相邻两个发光二极管单元的第一导电层通 过绝缘层隔离。
[0066] 在本发明的一些实施例中， 优选的， 发光二极管元件包括 3个至 6个， 或者 7个 至 9个发光二极管单元， 越多发光二极管单元串联， 相对与现有的结构， 本发明 越具有光集中或者散热的优势。
[0067] 一种发光二极管元件的制作方法， 用于制作高压发光装置， 包括步骤：
[0068] 步骤 1、 在生长衬底上制作半导体层序列， 半导体层序列包括第一类型半导体 层、 有源层、 第二类型半导体层；
[0069] 步骤 2、 从第二类型半导体层背侧挖出多个贯穿第二类型半导体层和有源层的 凹处， 凹处至少贯穿至第一类型半导体层；
[0070] 步骤 3、 在第二类型半导体层表面的非凹处位置覆盖导电层， 导电层包括 n对位 于同一水平面的第一导电层和第二导电层， 其中 n^2， 向导电层、 凹处底部和侧 壁覆盖绝缘层；
[0071] 步骤 4、 在绝缘层上挖孔， 至少露出凹处底部的第一类型半导体层和 n个第一导 电层的部分区域；
[0072] 步骤 5、 在凹处底部、 绝缘层、 n个第一导电层的部分区域继续覆盖第一导电层 材料， n个第一导电层之间设置绝缘层隔离， 制作时并不必严格按文字描述的顺 序来决定工艺中覆盖第一导电层材料的先后顺序， 即先后可以根据需求来任意 调整；
[0073] 步骤 6、 在第一导电层的背侧直接连接散热基板；
[0074] 步骤 7、 去除生长衬底；
[0075] 步骤 8、 从第一类型半导体层的正侧开始移除部分半导体层序列， 移除半导体 层序列至露出第一导电层和第二导电层， 形成 n个相互隔离的半导体层序列；
[0076] 步骤 9、 在第一个半导体层序列露出的第一导电层上制作第一电极， 同时在最 后一个半导体层序列露出的第二导电层上制作第二电极。
[0077] 与现有技术相比， 本发明提供发光二极管芯片， 技术效果包括： 提供一种具有 良好散热功能的高压发光二极管， 利用本发明设计的发光二极管单元的结构可 方便的制作出串联的高压发光二极管阵列。
发明的有益效果
有益效果
[0078] 本发明的其它特征和优点将在随后的说明书中阐述， 并且， 部分地从说明书中 变得显而易见， 或者通过实施本发明而了解。 本发明的目的和其他优点可通过 在说明书、 权利要求书以及附图中所特别指出的结构来实现和获得。
对附图的简要说明
附图说明
[0079] 附图用来提供对本发明的进一步理解， 并且构成说明书的一部分， 与本发明的 实施例一起用于解释本发明， 并不构成对本发明的限制。 此外， 附图数据是描 述概要， 不是按比例绘制。
[0080] 图 1是实施例 1步骤 1~3制作出的结构示意图；
[0081] 图 2是实施例 1步骤 4制作出的结构示意图；
[0082] 图 3是实施例 1步骤 5制作出的结构示意图；
[0083] 图 4是实施例 1步骤 6至步骤 7制作的结构示意图；
[0084] 图 5是实施例 1步骤 8至步骤 9制作的结构示意图；
[0085] 图 6是实施例 1的 LED结构俯视示意图；
[0086] 图 7~图12是实施例 1的新结构和现有技术的旧结构老化数据对比曲线图；
[0087] 图 13是实施例 7步骤 1~2的结构示意图；
[0088] 图 14是实施例 7步骤 3制作的结构示意图；
[0089] 图 15是实施例 7步骤 4制作的结构示意图；
[0090] 图 16是实施例 7步骤 5制作的结构示意图；
[0091] 图 17是实施例 7步骤 6至步骤 9制作的结构示意图；
[0092] 图 18是实施例 9的 LED结构示意图；
[0093] 图中各标号表示如下： 100、 生长衬底； 200、 半导体层序列； 210、 第一类型 半导体层； 220、 第二类型半导体层； 230、 有源层； 310、 第一导电层； 320、 第二导电层； 400、 绝缘层； 500、 基板； 610、 第一电极； 620、 第二电极。 发明实施例
本发明的实施方式
[0094] 下面结合示意图对本发明的发光二极管芯片及其制作方法进行详细的描述， 在 进一步介绍本发明之前， 应当理解， 由于可以对特定的实施例进行改造， 因此 ， 本发明并不限于下述的特定实施例。 还应当理解， 由于本发明的范围只由所 附权利要求限定， 因此所采用的实施例只是介绍性的， 而不是限制性的。 除非 另有说明， 否则这里所用的所有技术和科学用语与本领域的普通技术人员所普 遍理解的意义相同。
[0095] 图 1至图 5以在方法的不同阶段的示意性截面图示出根据第一实施例的用于制造 光电子半导体本体的方法。
[0096] 在第一个实施例中， 先提供的是一种被设计从正侧出光的发光二极管芯片的制 作工艺步骤， 包括：
[0097] 参看图 1， 对步骤 1到步骤 3制作出结构进行了展示，
[0098] 步骤 1、 在生长衬底 100上制作作为发光外延层的半导体层序列 200, 半导体层 序列 200包括第一类型半导体层 210、 有源层 230、 第二类型半导体层 220, 本实 施例的半导体层序列 200实质为发光 PN结， 第一类型半导体层 210为 N型半导体 层， 第二类型半导体层 220为 P型半导体层， 也可以根据设计对调顺序， 有源层 2 30为用于产生辐射多量子阱； 步骤 2、 从第二类型半导体层 220背侧挖出贯穿第 二类型半导体层 220和有源层 230的凹处， 凹处至少贯穿至第一类型半导体层 210 ， 也可以贯穿到第一类型半导体层 210内； 步骤 3、 在第二类半导体层表面的非 凹处位置覆盖图形化导电层， 导电层包括位于同一水平面的第一导电层 310和第 二导电层 320， 在导电层、 凹处底部和侧壁上覆盖绝缘层 400;
[0099] 参看图 2， 步骤 4、 进一步制作具有导电通道的电路结构， 在绝缘层 400上挖孔 去除部分作为电隔离障碍的绝缘材料， 至少露出凹处底部的第一类型半导体层 2 10, 也露出部分第一导电层 310;
[0100] 参看图 3， 步骤 5、 在凹处底部、 绝缘层 400、 步骤 4露出的部分第一导电层 310 处继续覆盖第一导电层 310材料， 以便于利用第一导电层 310填充凹处后构建第 一电极 610和第一类型半导体层 210的电连接， 该步骤的第一导电层 310材料熔点 低于键合温度、 具有比较好的流动性， 例如采用 Ni或者 Sn， 利于减少第一导电 层 310内部配合处的孔洞， 增加产品散热及可靠性；
[0101] 参看图 4, 步骤 6、 在第一导电层 310的背侧直接连接用于支撑和散热基板 500, 该直接连接通常采用的是金属键合工艺或者粘合工艺， 若采用键合工艺， 往往 在步骤 6前还会在基板 500和第一导电层 310上制作一层键合金属， 这里的键合金 属统成为第一导电层 310; 对步骤 7、 去除生长衬底 100; [0102] 参看图 5 , 对步骤 8到步骤 9的结构进行了描述， 步骤 8、 从第一类型半导体层 21 0的正侧开始移除部分区域的半导体层序列 200, 移除半导体层序列 200至露出第 一导电层 310和第二导电层 320, 本工艺的其中一个优势在于可以直接蚀刻移除 半导体层序列 200形成电极窗口， 而不需要移除绝缘介质或者导电层等难移除材 料， 相对工艺简单、 高效和可靠； 步骤 9、 在露出的第一导电层 310上制作第一 电极 610， 在露出的第二导电层 320上制作第二电极 620。
[0103] 在本发明的第二个实施例中， 提供了一款可利用上述工艺方法制得的能提高可 靠性、 可简化制作成高压芯粒流程的发光二极管结构。
[0104] 参看图 5 , 首先具有用于辐射的半导体层序列 200, 其具有第一类型半导体层 21 0和第二类型半导体层 220, 和在第一类型半导体层 210和第二类型半导体层 220 之间的设计用于产生辐射的有源层 230, 其中第一类型半导体层 210与半导体层 序列 200的正侧相邻， 半导体层序列 200例如基于 III/V化合物半导体材料或者基 于 II/VI化合物半导体材料。 II/V化合物半导体材料至少具有来自第三主族的元素 ， 例如 Al、 Ga、 In， 以及来自第五主族的元素， 例如 B、 N、 P、 As。 特别地， 术语“III/V化合物半导体材料”包括二元、 三元或者四元化合物的族， 这些化合物 包含来自第三主族的至少一种元素和来自第五主族的至少一种元素， 特别是氮 化物化合物半导体和磷化物化合物半导体。 这种二元、 三元或四元化合物此外 例如可以具有一种或者多种掺杂剂以及附加的组成部分。 属于 III/V化合物半导 体材料的例如有第 III族氮化物化合物半导体材料和第 III族磷化物化合物半导体 材料， 譬如 GaN、 GaAs和 InGaAlP。 半导体层序列 200的高度大于等于 5pm到小 于等于 7[xm， 或者大于 7[xm到小于等于 8[xm。 半导体层序列 200的高度在此不高于 7^m, 考虑到工艺性能， 半导体层序列 200不低于 5pm。
[0105] 半导体层序列 200包含至少一个被绝缘层 400覆盖的凹处， 在此实施例， 凹处的 数量为 20~25个， 凹处从半导体层序列 200的与正侧对置的背侧穿过有源层 230延 伸到第一类型半导体层 210, 第一导电层 310背侧与基板 500正侧连接， 第一导电 层 310至少裸露出正侧一部分用于设置第一电极 610, 第二导电层 320至少裸露出 正侧一部分用于设置第二电极 620, 露出的第一电极 610连接层和第二导电层 320 等高， 该等高主要指的是上表面位于高度一致的水平面上， 该等高设计实际是 通过对靠近半导体层序列 200的第一导电层 310和第二导电层 320—体设计制作而 成的。 与第一导电层 310连接的第一电极 610， 与第二导电层 320连接的第二电极 620， 第一电极 610和第二电极 620朝向正侧， 第一电极 610和第二电极 620主要指 的是用于封装打线的金属电极。
[0106] 借助第一导电层 310穿过凹处来电连接第一类型半导体层 210, 第一导电层 310 正侧与第一类型半导体层 210的背侧接触面积大于第一类型半导体层 210面积的 1. 5% ,
[0107] 第一导电层 310与第二导电层 320借助凹处的绝缘层 400来彼此电绝缘， 从凹处 延伸的绝缘层 400覆盖在第一导电层 310和第二导电层 320的背侧， 绝缘层 400覆 盖在第一导电层 310并不是指覆盖第一导电层 310整个背侧， 而只是第一导电层 3 10的部分区域， 以防止降低散热效果。 绝缘层 400的材料包括氧化硅、 氮化硅、 氮化铝、 氧化铝或者陶瓷， 第一导电层 310和 /或第二导电层 320为金属材料，
[0108] 用于支撑和散热的基板 500， 基板 500材料为 Si、 Cu或者陶瓷， 特别是采用陶瓷 基板 500的芯片， 一方面陶瓷基板 500具有良好的散热特性， 与第一导电层 310配 合更好地将热量从第一导电层 310导出， 另一方面由于陶瓷基板 500的绝缘特性 ， 有利于在高压产品中在同一基板 500上制作成多颗半导体串联结构。
[0109] 第一导电层 310和 /或第二导电层 320的材料为 Ag、 Au、 Ti、 Al、 Cr、 Pt、 TiW 合金、 Ni或以上的任意组合。 具体来说， 在本实施例中， 第一导电层 310与第一 电极 610接触的部分、 第二导电层 320与第二电极 620接触的部分为性能较为稳定 的 Ti、 Pt、 Au、 Cr、 TiW合金， 用于填充凹处的第一导电层 310材料包括 Al、 Cr 或者 Ag等反射材料。 位于发光区域下方的第二导电层 320依次为用于电流扩展的 ITO、 对发光区域出光进行反射的 Ag、 Ni或 TiW、 用于防止上述材料扩散的稳定 金属材料 Ti、 Pt、 Au、 Cr或 TiW等。
[0110] 参看图 6， 为了进一步对本实施例的结构进行解释， 提供了从俯视角度体现本 发明结构的一种芯片俯视示意图， 在该示意图中， 可以看到在出光面位置均匀 分布着多个凹处设计， 该设计具有很好的电流扩展性和散热特性， 第一电极 610 和第二电极 620设置在芯片的外侧。 本发光二极管芯片结构具有简单清晰的各材 料叠层， 具有制作工艺简单、 可靠性高等优势。 [0111] 参看图 7~图9， 在外部干涉结温的条件下进行老化试验， 常规的旧结构在 125°C 结温及 2000mA电流条件下快速出现死灯现象， 因此对本发明的新结构提供更不 利的老化测试条件， 新结构采用 125°C的结温在 2000mA的电流条件下进行老化测 试， 而旧结构采用 75°C的结温在 1500mA的电流条件下进行老化测试， 图 7对 1000 小时内新结构和旧结构亮度 ALOP进行比对， 可以看到新结构在 1000小时内亮度 波动更小， 亮度稳定性好， 图 8对 1000小时内新结构和旧结构正向电压变化值 AV F进行比对， AVF是与初始正向电压的差值， 二者差距不大， 图 9对对 1000小时 内新结构和旧结构漏电电流 AIR进行比对， AIR是与初始漏电电流的差值， 新结 构基本没有漏电电流， 旧结构的漏电电流随着老化进程的推进而逐步增高。 综 合上述试验数据， 基本可以得到结论， 本发明的新结构在高温、 大电流密度的 条件下， 可靠性高于常规旧结构。
[0112] 参看图 10~图12， 在外部干涉结温的条件下进行老化试验， 新结构、 旧结构均 采用 125°C的结温在 1500mA的中等电流密度条件下进行老化测试， 图 10和图 11对 1000小时内新结构和旧结构亮度 ALOP、 正向电压变化值 A VF进行比对， 可以看 到新结构和旧结构在 1000小时内差距比较小， 稳定性接近， 图 12对 1000小时内 新结构和旧结构亮度 AIR进行比较， 新结构基本没有漏电电流， 旧结构的漏电电 流随着老化进程的推进而逐步增高。 综合上述试验数据， 基本可以得到结论， 本发明的新结构在高温、 中大电流密度的条件下， 可靠性高于常规旧结构。
[0113] 实施例 3为实施例 2的一些变形方式， 在本实施例中扩大第一导电层 310与第一 类型半导体层 210的背侧接触面积， 接触面积是第一类型半导体层 210面积的大 于等于 2.3%到小于等于 2.8%、 大于 2.8%到小于 4%或者大于等于 4%到小于等于 6 %。 凹处的开口直径大于等于 15pm到小于 32pm。 与前面的实施例不同， 增加第 一导电层 310和第一类型半导体层 210的直接接触面积， 而解决高功率产品的散 热问题， 而高功率例如大尺寸芯片或者高压芯片等。
[0114] 实施例 4为实施例 3的进一步设计， 虽然大体来说保证第一导电层 310与第一类 型半导体层 210的总接触面积， 可以提高散热特性， 但如果开口直径较小的情况 下， 较细的第一导电层 310具有超过线性比例的热阻， 为保证该情况下的散热， 本实施例的设计是将凹处开口设计为大于等于 32pm至小于等于 4(Vm。 作为一种 较佳实施方式， 当凹处开口直径大于等于 34pm到小于等于 36pm时， 凹处的数量 设置为 20~25个。
[0115] 如实施例 2到实施例 4那样的结构， 实施例 5中第一类型半导体层 210厚度设计较 厚时， 例如厚度不小于 2pm， 将凹处在第一类型半导体层 210内的深度挖到不小 于 lpm， 更好地从第一类型半导体层 210将热量引出。 例如第一类型半导体层 210 厚度为 2[xm~3[xm。
[0116] 在本发明的实施例 6中， 将实施例 1~实施例 5的发光二极管芯片通过打线连接， 将第一颗发光二极管芯片的第一电极 610与外部电路连接， 将第一颗发光二极管 芯片的第二电极 620和第二颗发光二极管芯片的第一电极 610通过金线连接， 通 过该方式， 依次串联多颗发光二极管芯片通过金线电路连接， 最后一颗发光二 极管芯片的第二电极 620与外部电路连接， 构成一连串串联连接的发光二极管芯 片串。 在应用中， 串联的多颗发光二极管芯片由于外部电路的电流固定， 往往 具有比较高的使用电压， 相比其他结构， 该结构的发光二极管芯片可以方便地 进行串联设计， 且在高压下具有明显的可靠性优势。
[0117] 在本发明的实施例 7中， 公开了一种相对工艺简单、 可靠性高的发光二极管元 件的制作方法， 用于制作高压发光装置， 包括如下工艺步骤：
[0118] 参看图 13， 步骤 1、 首先制作发光二极管元件的外延结构， 在生长衬底 100上制 作半导体层序列 200, 半导体层序列 200包括第一类型半导体层 210、 有源层 230 、 第二类型半导体层 220, 三者构成半导体 PN结； 步骤 2、 从第二类型半导体层 2 20背侧例如通过湿法蚀刻或者干法蚀刻挖出多个贯穿第二类型半导体层 220和有 源层 230的凹处， 凹处至少贯穿至第一类型半导体层 210。
[0119] 参看图 14, 步骤 3、 在第二类型半导体层 220表面的非凹处位置覆盖导电层， 该 导电层是离散分布， 为后续电路连接做相应图形设计， 导电层包括 n对位于同一 水平面的第一导电层 310和第二导电层 320， 每一对第一导电层 310和第二导电层 320位于后续制作出的独立的半导体层序列 200中， 其中 n22， 然后向各部分导电 层、 凹处底部和侧壁覆盖绝缘层 400。
[0120] 参看图 15 , 步骤 4、 在绝缘层 400—些区域挖孔， 至少露出凹处底部的第一类型 半导体层 210和 n个第一导电层 310的部分区域， 露出的凹处底部的第一类型半导 体层 210和 n个第一导电层 310用于制作电连接窗口；
[0121] 参看图 16， 步骤 5、 在凹处底部、 绝缘层 400、 n个第一导电层 310的部分区域继 续覆盖第一导电层 310材料， 这里说的第一导电层 310主要指的是多种材料层共 同构成的， 统一定义为第一导电层 310， n个第一导电层 310之间设置绝缘层 400 隔离， 通过新覆盖的第一导电层 310材料将电连接导出到步骤 3制作的与第二导 电层 320等高的第一导电层 310上；
[0122] 参看图 17 , 步骤 6、 在第一导电层 310的背侧直接连接散热基板 500, 散热基板 5 00包括陶瓷或者金属， 该直接连接通常采用的是金属键合工艺或者粘合工艺， 若采用键合工艺， 往往在步骤 6前还会在基板 500和第一导电层 310上制作一层键 合金属， 这里的键合金属统成为第一导电层 310; 步骤 7、 去除生长衬底 100, 这 里的去除生长衬底 100包括去除全部生长衬底 100或者减薄生长衬底 100; 步骤 8 、 从第一类型半导体层 210的正侧开始移除部分半导体层序列 200, 移除半导体 层序列 200至露出第一导电层 310和第二导电层 320, 因为该工艺的设计可以直接 移除至第一导电层 310和第二导电层 320等相对稳定的材料， 因此工艺可控性好 ， 形成 n个相互隔离的半导体层序列 200; 步骤 9、 在第一个半导体层序列 200露 出的第一导电层 310上制作第一电极 610， 同时在最后一个半导体层序列 200露出 的第二导电层 320上制作第二电极 620， 第一电极 610和第二电极 620用于与外部 电路连接。
[0123] 参看图 17 , 根据上述工艺提供了主要用于高压器件的发光二极管元件结构， 在 本发明的实施例 8中， 在该结构中， 发光二极管单元之间采用串联式连接， 发光 二极管元件包括 3个至 6个， 或者 7个至 9个发光二极管单元。 为了设计成串联形 式， 发光二极管单元之间的半导体层序列 200相互隔离， 彼此之间通过半导体层 序列 200内部的导电层构成串联电连接； 半导体层序列 200具有在第一类型半导 体层 210和第二类型半导体层 220之间的、 设计用于产生辐射的有源层 230, 其中 第一类型半导体层 210位于半导体层序列 200的正侧， 半导体层序列 200包含一个 或复数个覆盖有绝缘层 400的凹处， 凹处作为电流通道从半导体层序列 200的与 正侧对置的背侧穿过有源层 230延伸到第一类型半导体层 210, 具有导电特性的 第一导电层 310穿过凹处来电连接第一类型半导体层 210, 具有导电特性的第二 导电层 320电连接第二类型半导体层 220， 第一导电层 310与第二导电层 320借助 从凹处延伸的绝缘层 400来彼此电绝缘， 复数个发光二极管单元的第一个发光二 极管单元至少裸露出部分第一导电层 310, 具有与其裸露的第一导电层 310电连 接的第一电极 610, 最后一个发光二极管单元至少裸露出部分第二导电层 320， 具有与其第二导电层 320电连接的第二电极 620， 第一电极 610和第二电极 620位 于发光二极管元件的外侧， 第一电极 610和第二电极 620朝向正侧。
[0124] 第一导电层 310背侧与基板 500正侧连接， 第一导电层 310正侧与第一类型半导 体层 210的背侧接触面积大于第一类型半导体层 210面积的 1.5%， 从凹处延伸的 绝缘层 400覆盖在第二导电层 320的背侧， 任意相邻的两个发光二极管单元其中 一个发光二极管单元的第二导电层 320与另一个发光二极管单元的第一导电层 31 0设有一体连接的连接部， 相邻两个发光二极管单元的第一导电层 310通过绝缘 层 400隔离。 在发光二极管单元的一些区域包括从上到下依次层叠的第二导电层 320、 绝缘层 400和第一导电层 310。
[0125] 复数个发光二极管单元共用同一支撑和散热基板 500的。 在一些薄膜型发光二 极管元件中， 半导体层序列 200的高度不高于 7pm。
[0126] 在本实施例中， 第一导电层 310和 /或第二导电层 320主要为金属材料， 也可能 设有用于电流扩展的 ITO等电流扩展材料。 相互隔离的半导体层序列 200之间至 少裸露出部分一体连接的连接部， 该结构主要是方便制作相互隔离的半导体层 序列 200时移除工艺只需进行到连接部， 在工艺上较为容易控制。
[0127] 参看图 18 , 根据上述实施例 8 , 为了保护连接部、 减少外部环境直接影响甚至 破坏连接部， 本发明提出了实施例 9 , 在每个发光二极管单元从正侧裸露出一部 分绝缘层 400， 至少部分一体连接的连接部位于该部分绝缘层 400的下方， 从结 构上看仅需要在水平方向上改变制作工艺步骤 5中用于隔离的绝缘层 400位置， 在步骤 8中的移除半导体层序列 200的位置至露出绝缘层 400即可实现。
[0128] 在实施例 8和实施例 9中， 复数个发光二极管单元通过在同一生长衬底 100上共 同生长的半导体层序列 200来制作而成的， 复数个发光二极管单元具有相同的芯 片结构， 即在图 11和图 12中， 可看出的周期性单元结构。
[0129] 在本发明的实施例 10中， 针对多个半导体层序列 200串联的高压条件下， 扩大 第一导电层 310与第一类型半导体层 210的背侧接触面积， 接触面积设计为第一 类型半导体层 210面积的大于等于 4%到小于等于 6%。
[0130] 应当理解的是， 上述具体实施方案仅为本发明的部分优选实施例， 以上实施例 还可以进行各种组合、 变形。 本发明的范围不限于以上实施例， 凡依本发明所 做的任何变更， 皆属本发明的保护范围之内。

Claims

权利要求书
[权利要求 1] 一种发光二极管芯片， 具有：
半导体层序列， 其具有第一类型半导体层、 第二类型半导体层和位于 两者间设计用于产生辐射的有源层， 其中
第一类型半导体层位于半导体层序列的正侧，
半导体层序列包含至少一个侧壁覆盖有绝缘层的凹处， 凹处从半导体 层序列的与正侧对置的背侧穿过有源层延伸到第一类型半导体层， 第一导电层和第二导电层都位于半导体层序列的背侧， 第二导电层与 第二类型半导体层的背侧直接接触，
与第一导电层连接的第一电极， 借助第一导电层穿过凹处来电连接第 一类型半导体层，
与第二导电层连接的第二电极，
第一导电层与第二导电层借助凹处延伸的绝缘层来彼此电绝缘， 用于 支撑和散热的基板；
其特征在于： 第一电极和第二电极朝向正侧， 第一导电层背侧与基板 正侧直接连接， 第一导电层正侧与第一类型半导体层的背侧接触面积 大于第一类型半导体层面积的 1.5%， 第一导电层至少裸露出正侧一部 分用于设置第一电极， 第二导电层至少裸露出正侧一部分用于设置第 二电极， 从凹处延伸的绝缘层覆盖在第二导电层的背侧。
[权利要求 2] 根据权利要求 1所述的一种发光二极管芯片， 其特征在于： 第一导电 层与第一类型半导体层的背侧接触面积为第一类型半导体层面积的大 于等于 2.3%到小于等于 2.8%、 大于 2.8%到小于 4%或者大于等于 4%到 小于等于 6%。
[权利要求 3] 根据权利要求 1所述的一种发光二极管芯片， 其特征在于： 第一导电 层和 /或第二导电层包括金属材料。
[权利要求 4] 根据权利要求 1所述的一种发光二极管芯片， 其特征在于： 凹处的开 口直径大于等于 15[xm到小于 32[xm， 或者大于等于 32[xm至小于等于 40 [xm。
[权利要求 5] 根据权利要求 1所述的一种发光二极管芯片， 其特征在于： 当凹处开 口直径大于等于 34pm到小于等于 36pm时， 凹处的数量为 20~25个。
[权利要求 6] 根据权利要求 1所述的一种发光二极管芯片， 其特征在于： 第一类型 半导体层的厚度不小于 2pm， 凹处在第一类型半导体层内的深度不小 于 0.6[xm。
[权利要求 7] 根据权利要求 1所述的一种发光二极管芯片， 其特征在于： 第一类型 半导体层厚度为 2[xm~3[xm。
[权利要求 8] 根据权利要求 1所述的一种发光二极管芯片， 其特征在于： 绝缘层的 材料包括氧化硅、 氮化硅、 氮化铝或者氧化铝。
[权利要求 9] 根据权利要求 1所述的一种发光二极管芯片， 其特征在于： 第一导电 层覆盖在基板的整个正侧。
[权利要求 10] 根据权利要求 1所述的一种发光二极管芯片， 其特征在于： 第一导电 层和 /或第二导电层的材料为 Ag、 Au、 Al、 Cr、 Ni、 Pt、 Sn、 Ti、 Ti W或以上的任意组合。
[权利要求 11] 根据权利要求 1所述的一种发光二极管芯片， 其特征在于： 第一导电 层包括欧姆接触层、 金属反射层、 金属键合层或者以上各层任意组合
[权利要求 12] 根据权利要求 1所述的一种发光二极管芯片， 其特征在于： 第二导电 层包括透明导电层、 金属反射层、 金属扩散阻挡层或者以上各层任意 组合。
[权利要求 13] 根据权利要求 1所述的一种发光二极管芯片， 其特征在于： 半导体层 序列的高度大于等于 5pm到小于等于 7pm， 或者大于 7pm到小于等于 8 [xm。
[权利要求 14] 根据权利要求 1所述的一种发光二极管芯片， 其特征在于： 基板在 100
°C时的导热系数不小于 150W/ （m，k） 。
[权利要求 15] 根据权利要求 1所述的一种发光二极管芯片， 其特征在于： 基板材料 为陶瓷、 Si或者 Cu。
[权利要求 16] 根据权利要求 1所述的一种发光二极管芯片， 其特征在于： 第一导电 层和第二导电层至少部分为一起制作， 位于同一平面上。
[权利要求 17] 根据权利要求 1所述的一种发光二极管芯片， 其特征在于： 第二导电 层的背侧与第一导电层正侧之间设置有从凹处延伸出来的绝缘层。
[权利要求 18] 根据权利要求 1所述的一种发光二极管芯片， 其特征在于： 裸露出的 第一导电层和裸露出第二导电层等高。
[权利要求 19] 一种发光二极管芯片的制作方法， 包括步骤：
步骤 1、 在生长衬底上制作半导体层序列， 半导体层序列包括第一类 型半导体层、 有源层、 第二类型半导体层；
步骤 2、 从第二类型半导体层背侧挖出贯穿第二类型半导体层和有源 层的凹处， 凹处至少贯穿至第一类型半导体层； 步骤 3、 在第二类型半导体层表面的非凹处位置覆盖导电层， 导电层 包括位于同一水平面的第一导电层和第二导电层， 向导电层、 凹处底 部和侧壁覆盖绝缘层；
步骤 4、 在绝缘层上挖孔， 至少露出凹处底部的第一类型半导体层和 部分第一导电层；
步骤 5、 在凹处底部、 绝缘层、 部分第一导电层继续覆盖第一导电层 材料；
步骤 6、 在第一导电层的背侧直接连接散热基板； 步骤 7、 去除生长衬底；
步骤 8、 从第一类型半导体层的正侧开始移除部分半导体层序列， 移 除半导体层序列至露出第一导电层和第二导电层； 步骤 9、 在露出的第一导电层上制作第一电极， 在露出的第二导电层 上制作第二电极。
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