WO2020093886A1 - 移位寄存器及其驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2020093886A1
WO2020093886A1 PCT/CN2019/113404 CN2019113404W WO2020093886A1 WO 2020093886 A1 WO2020093886 A1 WO 2020093886A1 CN 2019113404 W CN2019113404 W CN 2019113404W WO 2020093886 A1 WO2020093886 A1 WO 2020093886A1
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Prior art keywords
terminal
output
circuit
signal
pull
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PCT/CN2019/113404
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English (en)
French (fr)
Inventor
袁志东
李永谦
袁粲
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to EP19882587.9A priority Critical patent/EP3879532B1/en
Priority to US16/766,634 priority patent/US11295827B2/en
Publication of WO2020093886A1 publication Critical patent/WO2020093886A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/188—Organisation of a multiplicity of shift registers, e.g. regeneration, timing or input-output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present disclosure relates to the field of display technology, and more specifically to a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • organic light-emitting diode OLED Organic Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • AMOLED active matrix organic light-emitting diode
  • the pixel circuits are generally all designed using N-type thin film transistors (TFTs).
  • TFTs N-type thin film transistors
  • a shift register and a driving method thereof, a gate driving circuit, and a display device are provided.
  • inventions of the present disclosure provide a shift register.
  • the thought register includes: a scanning circuit configured to generate a first signal for causing a gate shift signal output by the shift register to have a row shift portion during a scanning period; and a sensing circuit configured to generate a A second signal having a frame shift portion in the gate drive signal during the blanking period; and a random shift circuit electrically connected to the scanning circuit and the sensing circuit, respectively, and configured to be based on the The first signal and the second signal generate a gate drive signal having the line shift portion and randomly having the frame shift portion.
  • the first signal includes at least one of a signal at a pull-up node of the scan circuit, a signal at a pull-down node of the scan circuit, or a signal at an output end of the scan circuit; and the first The two signals include at least one of a signal at the pull-up node of the sensing circuit, a signal at the pull-down node of the sensing circuit, or a signal at the output end of the sensing circuit.
  • the random shift circuit includes:
  • the cascade output control sub-circuit is connected to the output enable terminal, the first control output terminal, the second control output terminal, the output terminal of the sensing circuit and the output terminal of the scanning circuit, and is configured to Under the control of the output enable terminal, a signal from the output terminal of the sensing circuit is provided to the first control output terminal and a signal from the output terminal of the scanning circuit is provided to the second control output terminal;
  • the pull-up node is connected and is configured at the output enable terminal, the pull-up node of the sensing circuit, the pull-down node of the sensing circuit, the random clock signal terminal, the first reference signal terminal Under control, transfer the frame shift clock signal from the frame shift clock signal terminal to the pull-up node of the scanning circuit;
  • the output sub-circuit is connected to the output clock signal terminal, the pull-up node and the pull-down node of the scanning circuit, the second reference signal terminal and the output terminal of the shift register, and is configured to Under the control of the pull-up node and the pull-down node of the scanning circuit, one of the output clock signal from the output clock signal terminal and the second reference signal from the second reference signal terminal is selectively transferred to the shift
  • the output terminal of the register serves as the gate drive signal output by the shift register.
  • the random shift circuit includes:
  • the cascade output control sub-circuit is connected to the signal switching terminal, the first control output terminal, the second control output terminal, the output terminal of the sensing circuit and the output terminal of the scanning circuit, and is configured to Under the control of the switching end, the signal from the output end of the sensing circuit is provided to the first control output end and the signal from the output end of the scanning circuit is provided to the second control output end;
  • the nodes are connected and configured to be under the control of the output enable terminal, the pull-up node of the sensing circuit, the pull-down node of the sensing circuit, the random clock signal terminal and the first reference signal terminal , Passing the frame shift clock signal from the frame shift clock signal terminal to the pull-up node of the scanning circuit;
  • the output sub-circuit is connected to the output clock signal terminal, the pull-up node and the pull-down node of the scanning circuit, the second reference signal terminal and the output terminal of the shift register, and is configured to Under the control of the pull-up node and the pull-down node of the scanning circuit, one of the output clock signal from the output clock signal terminal and the second reference signal from the second reference signal terminal is selectively transferred to the shift
  • the output terminal of the register serves as the gate drive signal output by the shift register.
  • the cascade output control sub-circuit includes a first transistor and a sixth transistor
  • the control terminal of the first transistor is connected to the signal switching terminal, the first terminal is connected to the output terminal of the sensing circuit, and the second terminal is connected to the first control output terminal;
  • the control terminal of the sixth transistor is connected to the signal switching terminal, the first terminal is connected to the output terminal of the scanning circuit, and the second terminal is connected to the second control output terminal.
  • the frame shift sub-circuit includes a second transistor, a third transistor, a fourth transistor, and a fifth transistor,
  • the control terminal of the second transistor is connected to the pull-up node of the sensing circuit, the first terminal is connected to the random clock signal terminal, and the second terminal is connected to the control terminal of the fourth transistor;
  • the control terminal of the third transistor is connected to the pull-down node of the sensing circuit, the first terminal is connected to the first reference signal terminal, and the second terminal is connected to the control terminal of the fourth transistor;
  • the first terminal of the fourth transistor is connected to the frame shift clock signal terminal, and the second terminal is connected to the first terminal of the fifth transistor;
  • the control terminal of the fifth transistor is connected to the output enable terminal, and the second terminal is connected to the pull-up node of the scanning circuit.
  • the random shift circuit includes:
  • the cascade output control sub-circuit is connected to the output enable terminal, the first control output terminal, the second control output terminal, the output terminal of the sensing circuit and the output terminal of the scanning circuit, and is configured to Under the control of the output enable terminal, a signal from the output terminal of the sensing circuit is provided to the first control output terminal and a signal from the output terminal of the scanning circuit is provided to the second control output terminal;
  • the frame shift sub-circuit is connected to the output enable terminal, the output terminal of the sensing circuit, the frame shift clock signal terminal and the pull-up node of the scanning circuit, and is configured to The frame shift clock signal from the frame shift clock signal terminal is transferred to the pull-up node of the scan circuit under the control of the output terminal of the sensing circuit;
  • the output sub-circuit is connected to the output clock signal terminal, the pull-up node and the pull-down node of the scanning circuit, the second reference signal terminal and the output terminal of the shift register, and is configured to Under the control of the pull-up node and the pull-down node, one of the output clock signal from the output clock signal terminal and the second reference signal from the second reference signal terminal is selectively transferred to the shift register Is used as the gate drive signal output by the shift register.
  • the scanning circuit and the sensing circuit are further configured to selectively receive an input signal under the control of a signal switching terminal, and the output terminal of the sensing circuit serves as a first control output terminal, and the The output terminal of the scanning circuit serves as the second control output terminal.
  • the random shift circuit includes:
  • the frame shift sub-circuit is connected to the output enable terminal, the output terminal of the sensing circuit, the frame shift clock signal terminal, and the pull-up node of the scanning circuit, and is configured to be at the output enable terminal And under the control of the output terminal of the sensing circuit, transfer the frame shift clock signal from the frame shift clock signal terminal to the pull-up node of the scanning circuit;
  • the output sub-circuit is connected to the output clock signal terminal, the pull-up node and the pull-down node of the scanning circuit, the second reference signal terminal and the output terminal of the shift register, and is configured to be at the pull-up node Under the control of the pull-down node, one of the output clock signal from the output clock signal terminal and the second reference signal from the second reference signal terminal is selectively passed to the output terminal of the shift register as The output signal of the shift register.
  • the frame shift sub-circuit includes a fourth transistor and a fifth transistor
  • the control terminal of the fourth transistor is connected to the output terminal of the sensing circuit, the first terminal is connected to the frame shift clock signal terminal, and the second terminal is connected to the first terminal of the fifth transistor;
  • the control terminal of the fifth transistor is connected to the output enable terminal, and the second terminal is connected to the pull-up node of the scanning circuit.
  • the cascade output control sub-circuit includes an inverter, a first transistor, and a sixth transistor,
  • the first terminal of the inverter is connected to the output enable terminal, and the second terminal is connected to the control terminal of the first transistor and the control terminal of the sixth transistor;
  • the first terminal of the first transistor is connected to the output terminal of the sensing circuit, and the second terminal is connected to the first control output terminal;
  • the first terminal of the sixth transistor is connected to the output terminal of the scanning circuit, and the second terminal is connected to the second control output terminal.
  • the output sub-circuit includes a seventh transistor and an eighth transistor,
  • the control terminal of the seventh transistor is connected to the pull-up node of the scanning circuit, the first terminal is connected to the output clock signal terminal, and the second terminal is connected to the output terminal of the shift register;
  • the control terminal of the eighth transistor is connected to the pull-down node of the scanning circuit, the first terminal is connected to the second reference signal terminal, and the second terminal is connected to the output terminal of the shift register.
  • a gate drive circuit including a plurality of cascaded shift registers described above.
  • a display device including the above gate drive circuit.
  • a method for driving the above shift register including:
  • the first signal for causing the gate drive signal to have a row shift portion in the scanning period is generated by the scanning circuit under the control of the output clock signal from the output clock signal terminal;
  • a second signal for making the gate drive signal have a frame shift portion in the blanking period under the control of the random clock signal from the random clock signal terminal by the sensing circuit;
  • the output clock signal from the output clock signal terminal, and the output enable signal from the output enable terminal by the random shift circuit, based on the first signal and the The second signal is to generate a gate drive signal with random frame shift.
  • the shift register further includes a signal switching terminal connected to the random shift circuit or the scanning circuit and the sensing circuit.
  • the random shift circuit When the signal at the signal switching terminal is When the signals at the output enable terminal are inverse to each other, the random shift circuit generates a gate drive signal having a frame shift portion randomly according to the first signal and the second signal.
  • the shift register further includes a signal switching terminal connected to the random shift circuit or the scanning circuit and the sensing circuit, when the signal at the signal switching terminal is constant high
  • the random shift circuit generates a gate drive signal having a frame shift portion sequentially according to the first signal and the second signal.
  • FIG. 1 is a circuit schematic diagram illustrating an example pixel circuit according to an embodiment of the present disclosure.
  • FIG. 2 is an operation timing diagram illustrating a gate driving signal of an example pixel circuit according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram showing the configuration of an example shift register according to an embodiment of the present disclosure.
  • FIG. 4 is a circuit schematic diagram illustrating an example shift register according to an embodiment of the present disclosure.
  • FIG. 5 is a diagram showing a connection relationship of an example gate driving circuit according to an embodiment of the present disclosure.
  • FIG. 6 is an example operation timing diagram illustrating an example shift register according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram showing the configuration of an example shift register according to another embodiment of the present disclosure.
  • FIG. 8 is a circuit schematic diagram illustrating an example shift register according to another embodiment of the present disclosure.
  • FIG. 9 is a circuit schematic diagram illustrating an example shift register according to yet another embodiment of the present disclosure.
  • FIG. 10 is a circuit diagram showing an example shift register according to still another embodiment of the present disclosure.
  • the terms “including” and “containing” and their derivatives are intended to include, but not limit; the term “or” is inclusive, meaning and / or.
  • the azimuth terms used such as “upper”, “lower”, “left”, “right”, etc., are used to indicate the relative positional relationship to assist those skilled in the art to understand the present disclosure Embodiments, and therefore those skilled in the art should understand that: “upper” / “lower” in one direction may become “lower” / “upper” in the opposite direction, and may become other in the other direction Positional relationship, such as “left” / "right”, etc.
  • control terminal is generally used to refer to the gate or base of the transistor, etc .
  • first terminal and second terminal of the transistor may refer to The source and drain of the transistor are vice versa, or they can refer to the collector and emitter of the transistor or vice versa
  • first end and second end of the capacitor can refer to their two electrodes, respectively.
  • the 3T2C pixel circuit design as shown in FIG. 1 can be generally used, namely three transistors T1, T2 and T3 and two capacitors C st and C VC Driven by the first gate drive signal (or scan signal) G1, the transistor T1 conducts the data signal from the data line V data to the gate of the transistor T3, and thereby enables the drive voltage VDD to be selectively selected according to the data signal
  • the EL transmitted to the light emitting device (for example, OLED light emitting device) causes it to emit light.
  • the transistor T2 is selectively turned on or off under the drive of the second gate driving signal (or sensing signal) G2, so that the voltage applied to the light emitting device can be sensed and provided to the analog-to-digital converter ADC for Processing and calculation, and then adjustment of the corresponding data signal / first gate drive signal, makes the light emission more uniform.
  • FIG. 2 shows an example timing diagram of the first gate driving signal G1 and the second gate driving signal G2 employed for the above purpose.
  • the period of each frame includes a blanking period and a scanning period.
  • the gate driving signal has a row shift portion during the scanning period and a frame shift portion during the blanking period.
  • the row shift part refers to the part of the gate drive signal generated by the register that is shifted row by row. For example, as shown in FIG.
  • each of the "first frame”, “second frame”, and “third frame” In the frame the gate drive signals are sequentially shifted in the same frame on adjacent rows, thereby implementing progressive scanning of pixels in the same frame.
  • the frame shift part refers to the part of the gate drive signal generated by the register that is shifted frame by frame, for example, as shown by the dashed box in FIG. 2, the gate drive signal shows the order between adjacent frames on adjacent rows Shift so that each frame senses a row of pixels.
  • the gate drive circuit In a general external compensation method, as shown in FIG. 2, in the blank period of each frame, the gate drive circuit generates a gate drive signal with sequential frame shift timing.
  • this method is likely to cause compensation stripes in the OLED display device and affect the display picture quality. Therefore, in order to realize the "random frame shift" that can eliminate the compensation of horizontal stripes, it is necessary to provide a scheme that can output the gate drive signal of the "random frame shift".
  • a shift register capable of providing a gate driving signal for random frame shift, a driving method thereof, a gate driving circuit, and a display device of embodiments of the present disclosure will be described in detail with reference to FIGS. 3 to 10.
  • each embodiment of the present disclosure will be described in detail using the second gate driving signal G2 for controlling the transistor T2 as an example.
  • the principles of the following embodiments of the present disclosure can also be applied to other occasions that require a shift register.
  • the following embodiments can be simply changed to be applicable to the first gate driving signal G1 of the control transistor T1 shown in FIG. 1.
  • the thin film transistors TFTs used are all N-type transistors.
  • the present disclosure is not limited to this, in fact, it is only necessary to make simple changes to the input levels, connection relationships, etc. of the embodiments of the present disclosure to make it applicable to P-type transistors.
  • FIG. 3 is a schematic diagram showing an example shift register 300 according to an embodiment of the present disclosure.
  • the shift register 300 may include a sensing circuit 310, a scanning circuit 320, and a random shift circuit 330.
  • the scanning circuit 320 may be configured to generate a first signal for causing a row shift portion in the gate driving signal during the scanning period.
  • the sensing circuit 310 may be configured to generate a second signal for causing a frame shift portion in the gate driving signal during the blanking period.
  • the random shift circuit 330 may be electrically connected to the scanning circuit 320 and the sensing circuit 310 respectively, and is configured to generate a line shift portion based on the first and second signals described above and randomly have The gate drive signal of the frame shift portion.
  • first signal and second signal used herein may refer to one or more signals, respectively, and are not limited to a single signal.
  • the sensing circuit 310 is connected to a random clock signal terminal CLKf, a power supply signal terminal (such as a third voltage signal terminal) VGH, and a first reference signal terminal (such as a first voltage signal terminal) LVGL;
  • the scanning circuit 320 is connected to an output clock Signal terminal CLK, power signal terminal VGH and first reference signal terminal LVGL;
  • random shift circuit 330 is connected to enable terminal OE, frame shift clock signal terminal CLKs, random clock signal terminal CLKf, power signal terminal VGH, first reference signal The terminal LVGL, the second reference signal terminal (for example, the second voltage signal terminal) VGL, and the output terminal OUT of the shift register 300.
  • the sensing circuit 310 and / or the scanning circuit 320 may adopt any conventional or future developed shift register design.
  • either or both of these can be a gate-in-panel GIP (Gate In Panel) shift register unit, which can provide a standard signal shift function according to a clock signal.
  • GIP Gate In Panel
  • it may also adopt a specific example configuration as described below in conjunction with FIG. 9 or FIG. 10, and the present disclosure is not limited thereto.
  • FIG. 3 Although an example connection relationship between each circuit and each signal line is shown in FIG. 3, the present disclosure is not limited thereto. In fact, other connection relationships, such as FIG. 4, FIG. 7, FIG. 8, FIG. 9, and FIG. 10, or other connection relationships can be used.
  • FIG. 4, FIG. 6, and FIG. 8 show that the two output clock signal terminals CLK1 and CLK2 respectively receive the first output clock signal and the second output clock signal, and the first output clock signal is the second output clock The inverse of the signal. For each shift register, the two can be used alternatively.
  • the output clock signal terminal of the odd-numbered shift register unit may be connected to receive the first output clock signal, and the output clock signal of the even-numbered shift register The terminal may be connected to receive the second output clock signal.
  • the following two random clock signal terminals CLKf1 and CLKf2 respectively receive the first random clock signal and the second random clock signal in FIG. 4, FIG. 6, and FIG. 8, the first random clock signal is the second random clock signal Inverting signal.
  • the two can be used alternatively.
  • the random clock signal terminal of the odd-numbered shift register unit may be connected to receive the first random clock signal
  • the random clock of the even-numbered shift register The signal terminal may be connected to receive the second random clock signal.
  • FIG. 4 is a circuit schematic diagram illustrating an example shift register 400 according to an embodiment of the present disclosure.
  • the shift register 400 shown in FIG. 4 may be a specific example of the shift register 300 shown in FIG. 3.
  • the sensing circuit 410 and / or the scanning circuit 420 may be conventional or future developed shift register designs, so FIG. 4 does not show the specific circuits of the two, but this does not affect the technology in the art The personnel reasonably selects the appropriate circuit design of these two to achieve the desired function according to the rest.
  • the sensing circuit 410 may be connected to the random clock signal terminal CLKf.
  • the sensing circuit 410 may respond to a random change in the signal waveform of the random clock signal terminal CLKf during the scanning period, so that the signal at the pull-up node Q1 of the sensing circuit 410 remains valid during the scanning period and the blanking period.
  • the random shift circuit 430 may be connected to the pull-up node Q1 of the sensing circuit 410, the pull-up node Q2 of the scanning circuit 420, and the frame shift clock signal terminal CLKs.
  • the random shift circuit 430 may cause the scanning circuit 420 to store the voltage of the frame shift clock signal terminal CLKs at its pull-up node Q2 under the control of the signal at the pull-up node Q1 of the sensing circuit 410 during the blanking period, and based on The stored voltage generates the gate driving signal having the frame shift portion.
  • the random shift circuit 430 may include a cascade output control sub-circuit 431, a frame shift sub-circuit 433, and an output sub-circuit 435.
  • the cascade output control sub-circuit 431 may be connected to the output enable terminal OE, the output terminal P1 of the sensing circuit 410, the output terminal P2 of the scanning circuit 420, the first control output terminal CR1 ⁇ n> and the second Control output terminal CR2 ⁇ n> (in this embodiment, it is assumed that the shift register shown in FIG. 4 is the nth stage shift register, and ⁇ n> represents the number of stages it is in).
  • the first control output terminal CR1 ⁇ n> and the second control output terminal CR2 ⁇ n> may be connected to the input terminal or the reset terminal of the adjacent shift register to form a cascade structure.
  • the cascaded output control sub-circuit 431 can provide the signal from the output terminal P1 of the sensing circuit 410 to the first control output terminal CR1 ⁇ n> (and thus to the adjacent shift register) under the control of the output enable terminal OE,
  • the signal from the output terminal P2 of the scanning circuit 420 is supplied to the second control output terminal CR2 ⁇ n> as an input signal or a reset signal of the adjacent shift register.
  • the frame shift sub-circuit 433 may be connected to the output enable terminal OE, the pull-up node Q1 and the pull-down node Qb1 of the sensing circuit 410, the frame shift clock signal terminal CLKs, and the random clock signal terminal (in FIG.
  • the two clock signal terminals CLKf1 and CLKf2 that respectively receive the first random clock signal and the second random clock signal are shown in, but this is only an illustration, and one of them can be selected and used as needed.
  • the first random clock signal terminal CLKf1 is used to receive the first random clock signal
  • the first voltage signal terminal (first reference signal terminal) LVGL and the pull-up node Q2 of the scanning circuit 420 are connected, and are configured to be enabled at the output Under the control of the terminal OE, the pull-up node Q1, the pull-down node Qb1, the first random clock signal terminal CLKf1, and the first voltage signal terminal LVGL
  • the frame shift clock signal from the frame shift clock signal terminal CLKs is transferred to the pull-up node Q2 .
  • the output sub-circuit 435 may be connected to the clock signal terminal (although in FIG. 4 although two clock signal terminals CLK1 and CLK2 are shown, which are respectively connected to the first output clock signal and the second output clock signal, this is only It is a schematic, and one of them can be used as needed.
  • the second voltage signal terminal VGL is connected to the output terminal of the shift register 400, and is configured to connect the first output clock signal from the first output clock signal terminal CLK1 and from the first output clock signal terminal CLK1 under the control of the pull-up node Q2 and the pull-down node Qb2.
  • One of the second voltage signals of the second voltage signal terminal (second reference signal terminal) VGL is selectively delivered to the output terminal OUT of the shift register 400 as an output signal of the shift register 400 (ie, the gate drive signal).
  • the cascade output control sub-circuit 431 may include an inverter INV, a first transistor T1, and a sixth transistor T6.
  • the first terminal of the inverter INV may be connected to the output enable terminal OE, and the second terminal may be connected to the control terminal of the first transistor T1 and the control terminal of the sixth transistor.
  • the first terminal of the first transistor T1 may be connected to the output terminal P1 of the sensing circuit 410, and the second terminal may be connected to the first control output terminal CR1 ⁇ n> to sense the shift register of the next stage
  • the input terminal of the circuit and / or the reset terminal of the sensing circuit of the shift register of the previous stage are connected.
  • the first terminal of the sixth transistor T6 may be connected to the output terminal P2 of the scanning circuit 420, and the second terminal may be connected to the second control output terminal CR2 ⁇ n>, thereby connecting with the scanning circuit of the shift register of the next stage
  • the input terminal and / or the reset terminal of the scanning circuit of the shift register of the previous stage are connected.
  • the inverter INV may be an inverter formed by a transistor, and may be implemented as a desired structure according to needs, which is not described in detail here.
  • the frame shift sub-circuit 433 may include a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5.
  • the control terminal of the second transistor T2 may be connected to the pull-up node Q1 of the sensing circuit 410, the first terminal may be connected to the first random clock signal terminal CLKf1, and the second terminal may be connected to the control terminal of the fourth transistor T4.
  • the control terminal of the third transistor T3 may be connected to the pull-down node Qb1 of the sensing circuit 410, the first terminal is connected to the first voltage signal terminal LVGL, and the second terminal may be connected to the control terminal of the fourth transistor T4.
  • the first terminal of the fourth transistor T4 may be connected to the frame shift clock signal terminal CLKs, and the second terminal may be connected to the first terminal of the fifth transistor T5.
  • the control terminal of the fifth transistor T5 may be connected to the output enable terminal OE, and the second terminal may be connected to the pull-up node Q2 of the scan circuit 420.
  • the output sub-circuit 435 may include a seventh transistor T7 and an eighth transistor T8.
  • the control terminal of the seventh transistor T7 may be connected to the pull-up node Q2 of the scan circuit 420, the first terminal may be connected to the first output clock signal terminal CLK1, and the second terminal may be connected to the output terminal OUT of the shift register 400.
  • the control terminal of the eighth transistor T8 may be connected to the pull-down node Qb2 of the scan circuit 420, the first terminal may be connected to the second voltage signal terminal VGL, and the second terminal may be connected to the output terminal OUT of the shift register 400.
  • CR1 ⁇ n> represents the cascade output (first control output) of the sensing circuit 410 of the shift register 400 of the nth row, which leads to the shift register of the n + 1th row The input terminal of the sensing circuit of the sensor and / or the reset terminal of the sensing circuit of the shift register of the n-1th row.
  • CR2 ⁇ n> represents the cascade output (second control output) of the scanning circuit 420 of the shift register 400 of the nth row, which leads to the input terminal of the scanning circuit of the shift register of the n + 1th row and / Or the reset terminal of the scan circuit of the shift register in the n-1th row.
  • the second signal generated by the sensing circuit 410 may include, for example, an output signal output from its output terminal P1, a level signal of its pull-up node Q1 and pull-down node Qb1, and so on.
  • the first signal generated by the scanning circuit 420 may include, for example, an output signal output from its output terminal P2, a level signal of its pull-up node Q2 and pull-down node Qb2, and so on.
  • the first voltage signal terminal LVGL and the second voltage signal terminal VGL may provide a low voltage signal, and the two may have different voltages, for example, one is -5V and the other is 0V; the third voltage signal The terminal VGH may provide a high-voltage signal, for example, it may provide a + 5V voltage signal, however, the present disclosure is not limited thereto, which depends entirely on the specific circuit design.
  • the first voltage signal terminal LVGL and the second voltage signal terminal VGL may provide low voltage signals having the same voltage.
  • FIG. 5 is a diagram showing a connection relationship of an example gate driving circuit 500 according to an embodiment of the present disclosure.
  • the gate driving circuit 500 may be formed by cascading a plurality of cascaded shift registers (for example, shift registers 300 or 400), wherein the output of the sensing circuit or the scanning circuit of the previous stage It may be the input (or set) of the sensing circuit or scanning circuit of the current stage, and the output of the sensing circuit or scanning circuit of the next stage may be the reset of the sensing circuit or scanning circuit of the current stage.
  • cascaded shift registers for example, shift registers 300 or 400
  • the first control output terminal CR1 ⁇ n-1> of the n-1th stage shift register is connected to the input terminal of the sensing circuit of the nth stage shift register, and the second control output terminal CR2 ⁇ n-1> is connected to The input terminal of the scanning circuit of the n-th shift register;
  • the first control output terminal CR1 ⁇ n + 1> of the n + 1-th shift register is connected to the reset terminal of the sensing circuit of the n-th shift register,
  • the second control output terminal CR1 ⁇ n + 2> of the n + 1-level shift register is connected to the reset terminal of the scan circuit of the n-th shift register, so that the sensing circuit and the scan circuit form their respective cascade structures.
  • the clock signal terminals of adjacent stages can receive clock signals that are in opposite phases in different orders.
  • the first output clock signal terminal CLK1 and the second clock signal terminal CLK2 of the shift register of the n-1th stage are connected to the clock signal lines CLK1 and CLK2, respectively, the first output clock of the shift register of the nth stage
  • the signal terminal CLK1 and the second clock signal terminal CLK2 may be connected to the clock signal lines CLK2 and CLK1, and so on.
  • the shift register of the nth stage A random clock signal terminal CLKf1 and a second random clock signal terminal CLKf2 may be connected to the random clock signal lines CLKf2 and CLKf1, and so on.
  • FIG. 6 is an example operation timing diagram illustrating an example shift register 400 according to an embodiment of the present disclosure.
  • the first output clock signal terminal CLK1 and the second output clock signal terminal CLK2 of the shift register 400 are connected to the first output clock signal line CLK1 and the second output clock signal line CLK2, respectively, and the first random clock of the shift register 400
  • the signal terminal CLKf1 and the second random clock signal terminal CLKf2 are connected to the first random clock signal line CLKf1 and the second random clock signal line CLKf2, respectively. Therefore, in this embodiment, without loss of generality, the corresponding clock signal terminal and the corresponding clock signal line are equivalent.
  • the first output clock signal line CLK1 and the second clock signal line CLK2 provide clock signals that are inverted to each other during the scanning period.
  • the first random clock signal line CLKf1 and the second random clock signal line CLKf2 provide a random clock signal in the scanning period.
  • the random clock signal may be a periodic pulse signal, and the waveform of the periodic pulse signal changes at a random time, for example, it continues to be a low level after the random time.
  • the random clock signals provided by the first random clock signal line CLKf1 and the second clock signal line CLK2 have ended after several pulse periods, the period during which the next pulse should appear should not appear.
  • the pulse is replaced with a continuous low level.
  • the random clock signal terminal may be randomly maintained at a continuous potential under the control of the random signal.
  • the random clock signal can be implemented by forcibly and continuously pulling down the level of the periodic pulse signal through a random pulse signal.
  • the random pulse signal may be generated by a field programmable gate array (FPGA).
  • the gate required for the output sensing of the stage of the shift register can be controlled during the blanking period
  • the polar drive signal will be described in detail below.
  • the clock signals on the first and second random clock signal lines CLKf1 and CLKf2 are equivalent to the random clock signals used to select the corresponding row of shift registers.
  • FIG. 6 shows that during the scan of the first frame, a high-level pulse marked with a dotted line in the first random clock signal on the first random clock signal line CLKf1 indicates that a virtual "random pulse" appears at that moment, That is, the next pulse should have appeared at that moment, but it did not appear, but was replaced with a continuous low level.
  • FIG. 6 shows the virtual random pulse.
  • the virtual pulse is not an actual signal, but indicates that the high level that should have appeared at the time shown by the dotted line does not appear, but is replaced by Low level.
  • the shift register of the Mth row during the virtual "random pulse" in the scanning period, the shift register of the Mth row generates the output signal OUT ⁇ M>, so that the shift register of the Mth row is selected, and the selected Mth row is shifted
  • the register will generate a high-level output signal during the blanking period for driving the corresponding row of pixel units for sensing, while other row shift registers that are not selected will generate a low-level output signal.
  • the shift register 400 shown in FIG. 4 is the shift register of the Mth row. Since the CLKf1 high-level pulse marked by the dotted line is a random pulse that does not actually appear, the sensing circuit 410 of the shift register 400 shown in FIG.
  • the sensing circuit 410 of the shift register 400 may output a high level only when a clock pulse corresponding thereto occurs within a frame time.
  • the random clock signal terminal CLKf to which the sensing circuit 410 of the current stage (ie, the Mth stage) is connected should be Is high to make the sensing circuit 410 output a high level (for example, see the setting of the T10 transistor shown in FIG. 9, which is responsible for outputting the signal at the random clock signal terminal CLKf to the output terminal P1), but at this time as before
  • the absence of the high level causes the Mth sensing circuit 410 to no longer output a high level, so that all subsequent sensing circuits 410 of the shift register unit have no high level input and naturally have no high level Output.
  • the scanning circuit 420 is connected to the first output clock signal line CLK1, so during the period when the random pulse occurs, it actually maintains a normal clock signal output, as shown in FIG. 6 As shown in the "M row Q2", the high potential is maintained in the corresponding period, and is subsequently reset by the output signal from the scanning circuit of the M + 1th row to become a low potential.
  • the output enable terminal OE is always kept at a low level, so after it becomes a high level through the inverter INV, the first transistor T1 and the sixth transistor T6 are turned on, thereby making the sensing circuit
  • the cascade outputs CR1 ⁇ M> and CR2 ⁇ M> of 410 and the scanning circuit 420 maintain normal output.
  • the output enable terminal OE is always kept at a low level, the fifth transistor T5 is always kept off under its control, so the frame shift will not appear on the output terminal OUT of the shift register 400 during scanning. Therefore, as shown in FIG. 6, during the scanning period, the output terminal OUT ⁇ M> of the shift register unit is a normal gate scanning signal, that is, it is high level in the corresponding period, and remains low level for the rest of the time.
  • the output enable terminal OE remains high, so after it goes low through the inverter IN, the first transistor T1 and the sixth transistor T6 are turned off, and thus the sensing circuit 410 and The first control output terminal CR1 ⁇ M> and the second control output terminal CR2 ⁇ M> of the scanning circuit 420 do not output high levels, thereby causing no subsequent shift register to output high levels.
  • the output enable terminal OE is always maintained at a high level, the fifth transistor T5 is turned on under its control, and thus the path from the fourth transistor T4 to the pull-up node Q2 of the scan circuit 420 is turned on.
  • the pull-up node Q1 of the sensing circuit 410 always maintains a high level in the late period of the scanning period (that is, after the occurrence of the random pulse), so the second transistor T2 is turned on, thereby making the first random clock signal line
  • the signal of CLKf1 is transmitted to the gate of the fourth transistor T4.
  • the first random clock signal line CLKf1 is a high-level signal at the beginning of the blanking period, so that the fourth transistor T4 is turned on accordingly, and makes the high-level signal from the frame shift clock signal terminal CLKs
  • the fourth transistor T4 and the fifth transistor T5 turned on previously are transferred to the pull-up node Q2 of the scanning circuit 420.
  • the high level at the point Q2 will turn on, for example, the eighteenth transistor T18 and cause the second capacitor C2 to start charging.
  • the pull-up node Q2 still maintains a high level at this time, and the first output clock signal from the first output clock signal terminal CLK1 changes from low level It is a high level, and the potential of the pull-up node Q2 is raised to a higher level by the bootstrap effect of the second capacitor C2, as shown in "M row Q2" in FIG.
  • the seventh transistor T7 is turned on by the high potential of the pull-up node Q2, so that the output terminal OUT ⁇ M> outputs the first output clock signal from the first output clock signal terminal CLK1 as the output signal, thereby obtaining The output signal shown in "OUT ⁇ M>" in Figure 6.
  • the output signal may be, for example, the second gate driving signal G2 of the pixel circuit shown in FIG. 1.
  • the shift register in the N-th row generates a high-level output signal at the output terminal OUT ⁇ N>. It is assumed here that the shift register in the Mth row is connected to the random clock signal terminal CLKf1 and the output clock signal terminal CLK1, and the shift register in the Nth row is connected to the random clock signal terminal CLKf2 and the output clock signal terminal CLK2, as shown in FIG. 5.
  • the output terminal OUT ⁇ N> of the shift register in the Nth row outputs the second clock signal from the second clock signal terminal CLK2, thereby obtaining the "OUT ⁇ " in FIG. 6 N> "indicates the output signal during the second frame.
  • the output signal may be, for example, the second gate driving signal G2 of the pixel circuit shown in FIG. 1.
  • the driving method described in conjunction with FIG. 6 may include: the first output clock signal from the output clock signal terminal (for example, the first output clock signal terminal CLK1 or the second output clock signal terminal CLK2 by the scanning circuit 420 Under the control of the second output clock signal), a first signal for generating a row shift portion in the gate drive signal during the scanning period is generated; the first random clock from the first random clock signal terminal CLKf1 is sensed by the sensing circuit 410 Under the control of a signal (such as a first random clock signal from the first random clock signal terminal CLKf1 or a second random clock signal from the second random clock signal terminal CLKf2) for controlling the gate drive signal during the blanking period
  • the second signal of the frame shift portion and the frame shift clock signal from the frame shift clock signal terminal CLKs and the output clock signal from the output clock signal terminal (for example, from the first output clock signal terminal CLK1) by the random shift circuit 430
  • the first output clock signal) the random clock signal from the random clock signal terminal (for example, the first random clock signal from
  • FIG. 7 is a schematic diagram showing an example shift register 700 according to another embodiment of the present disclosure.
  • the shift register 700 may include a sensing circuit 710, a scanning circuit 720 and a random shift circuit 730. Similar to FIG. 3, in some embodiments, the scanning circuit 720 may be configured to generate a first signal for causing a row shift portion in the gate driving signal during the scanning period. In addition, in some embodiments, the sensing circuit 710 may be configured to generate a second signal for causing a frame shift portion in the gate driving signal during the blanking period.
  • the random shift circuit 730 may be electrically connected to the scanning circuit 720 and the sensing circuit 710, respectively, and is configured to be able to generate a line shift portion based on the first signal and the second signal described above and have frames randomly The gate drive signal of the shift portion.
  • the sensing circuit 710 and / or the scanning circuit 720 may adopt any conventional or future developed shift register design.
  • either or both of these two can be a GIP shift register unit, which can provide a standard signal shift function according to a random clock signal.
  • it may also adopt a specific example configuration as described below in conjunction with FIG. 9 or FIG. 10, and the present disclosure is not limited thereto.
  • connection relationship between each circuit and each signal line is shown in FIG. 7, the present disclosure is not limited thereto. In fact, other connection relationships can be used, such as the connection relationships of FIG. 3, FIG. 4, FIG. 8, FIG. 9, and FIG. 10.
  • the first output clock signal at the first output clock signal terminal CLK1 and the second output clock signal at the second output clock signal terminal CLK2 are inverse to each other, and the first random clock signal at the first random clock signal terminal CLKf1 and the second The second random clock signals of the random clock signal terminal CLKf2 are inverse to each other, and one of them can be selected for use.
  • the odd-numbered shift register in the gate drive circuit may be connected to the first output clock signal terminal CLK1 and the first random clock signal terminal CLKf1, and the second output clock signal terminal CLK2 and the second random The clock signal terminal CLKf2, and connects the even-numbered shift register unit to the second output clock signal terminal CLK2 and the second random clock signal terminal CLKf2, other situations are similarly established.
  • FIG. 8 is a circuit schematic diagram illustrating an example shift register 800 according to another embodiment of the present disclosure.
  • the shift register 800 shown in FIG. 8 may be a specific example of the shift register 700 shown in FIG. 7. Since the sensing circuit 810 and / or the scanning circuit 820 indicated above can be a conventional or future developed shift register design, FIG. 8 does not show the specific circuits of the two, but this does not affect the technology in the art The personnel reasonably selects the appropriate circuit design of these two to achieve the desired function according to the rest.
  • the random shift circuit 830 may include: a cascade output control sub-circuit 831, a frame shift sub-circuit 833, and an output sub-circuit 835.
  • the cascade output control sub-circuit 831 may be connected to the signal switching terminal SW, the output terminal P1 of the sensing circuit 810, the output terminal P2 of the scanning circuit 820, the first control output terminal CR1 ⁇ n> and the second control
  • the output terminal CR2 ⁇ n> is connected to the input terminal or the reset terminal of the adjacent shift register, and is configured to, under the control of the signal switching terminal SW, to the first control output terminal CR1 ⁇ n> and the second control output terminal CR2 ⁇ n> (therefore to the adjacent shift register) provides output signals from the output terminal of the sensing circuit 810 and the output terminal of the scanning circuit 820, respectively, as an input signal or a reset signal of the adjacent shift register.
  • the frame shift sub-circuit 833 may be connected to the output enable terminal OE, the pull-up node Q1 and the pull-down node Qb1 of the sensing circuit 810, the frame shift clock signal terminal CLKs, the first random clock signal terminal ACLKf1,
  • the first voltage signal terminal LVGL is connected to the pull-up node Q2 of the scanning circuit 820, and is configured to be at the output enable terminal OE, the pull-up node Q1, the pull-down node Qb1, the first random clock signal terminal CLKf1, the first voltage signal terminal Under the control of LVGL, the frame shift clock signal from the frame shift clock signal terminal CLKs is transferred to the pull-up node Q2.
  • the output sub-circuit 835 may be connected to the first output clock signal terminal CLK1, the pull-up node Q2 and the pull-down node Qb2 of the scan circuit 820, the second voltage signal terminal VGL and the output terminal of the shift register 800, and It is configured to selectively transfer one of the first output clock signal from the first output clock signal terminal CLK1 and the second voltage signal from the second voltage signal terminal VGL under the control of the pull-up node Q2 and the pull-down node Qb2
  • the output terminal OUT of the shift register 800 serves as the output signal of the shift register 800.
  • the cascade output control sub-circuit 831 may include a first transistor T1 and a sixth transistor T6.
  • the control terminal of the first transistor T1 is connected to the signal switching terminal SW, the first terminal can be connected to the output terminal P1 of the sensing circuit 810, and the second terminal can be connected to the first control output terminal CR1 ⁇ n>
  • the input terminal of the sensing circuit of the first-level shift register and / or the reset terminal of the sensing circuit of the previous-level shift register are connected.
  • control terminal of the sixth transistor T6 may be connected to the signal switching terminal SW, the first terminal may be connected to the output terminal P2 of the scanning circuit 820, and the second terminal may be connected to the second control output terminal CR2 ⁇ n>, thereby The input terminal of the scanning circuit of the shift register of the next stage and / or the reset terminal of the scanning circuit of the shift register of the previous stage are connected.
  • the frame shift sub-circuit 833 and the output sub-circuit 835 may have the same or similar structure as the frame shift sub-circuit 433 and the output sub-circuit 435 shown in FIG. 4, which will not be repeated here.
  • the cascade output control sub-circuit 831 in the shift register 800 shown in FIG. 8 is controlled by a control signal of a separate signal switching terminal SW.
  • the random shift circuit 830 may be configured to The two signals and the first signal output by the scanning circuit 820 generate a gate drive signal having a line shift portion and randomly having a frame shift portion. More specifically, when the signal switching terminal SW in FIG. 8 outputs a signal inverted from the output enable terminal OE, it is substantially equivalent to the output enable terminal OE shown in FIG. 4 plus an inverter, so that The shift register 800 shown in FIG. 8 can achieve the same function as the shift register 400 shown in FIG. 4.
  • the random shift circuit 830 may be configured to be able to generate the first signal output from the scanning circuit 820 according to the second signal output from the sensing circuit 810 To generate a gate driving signal having a line scanning portion and sequentially having a frame shift portion. More specifically, when the signal switching terminal SW in FIG. 8 always outputs a high-level signal, the cascade output terminals of the sensing circuit 810 and the scanning circuit 820 (ie, the first control output terminal CR1 ⁇ n> and the second control output Terminal CR2 ⁇ n>) will always output the signal normally.
  • the shift register 800 in conjunction with the random clock signal of the first random clock signal terminal CLKf1 and / or the second random clock signal terminal CLKf2 (for example, a random pulse that appears sequentially, it may also be referred to as a sequential pulse at this time), which can make the shift register 800 can output a gate driving signal having a frame shift portion in sequence like an ordinary shift register. Therefore, by adjusting the output signal of the signal switching terminal SW, the same shift register can support both random frame shift and sequential frame shift.
  • the shift register 900 may include a sensing circuit 910, a scanning circuit 920 and a random shift circuit 930.
  • the random shift circuit 930 includes first to eighth transistors T1 to T8.
  • the sensing circuit 910 may include a ninth transistor T9 to a sixteenth transistor T16 and a first capacitor C1.
  • the control terminal of the ninth transistor T9 is connected to the cascade output (ie, the first control output terminal CR1 ⁇ n-1>) of the sensing circuit from the shift register of the previous stage to receive the input signal,
  • the first terminal is connected to the third voltage signal terminal VGH, and the second terminal is connected to the pull-up node Q1.
  • the input sub-circuit of the sensing circuit 910 includes a ninth transistor T9, and may be configured to transmit a third voltage signal (eg, high level VGH) to the pull-up node under the control of the input signal at CR1 ⁇ n-1> Q1.
  • the control terminal of the tenth transistor T10 is connected to the pull-up node Q1, the first terminal is connected to the first random clock signal terminal CLKf1, and the second terminal is connected to the output terminal P1 of the sensing circuit 910.
  • the first terminal of the first capacitor C1 is connected to the pull-up node Q1, and the second terminal of the first capacitor C1 is connected to the output terminal P1 of the sensing circuit 910.
  • the tenth transistor T10 and the first capacitor C1 may constitute an output sub-circuit of the sensing circuit 910, which may be configured to transmit the signal from the first random clock signal terminal CLKf1 to the sensing circuit under the control of the pull-up node Q1 910 output.
  • the control terminal of the eleventh transistor T11 is connected to the cascade output (ie, the first control signal terminal CR1 ⁇ n + 1>) of the sensing circuit from the shift register of the next stage to receive the input
  • the first terminal of the signal is connected to the first voltage signal terminal LVGL, and the second terminal is connected to the pull-up node Q1.
  • the reset sub-circuit of the sensing circuit 910 includes an eleventh transistor T11, and may be configured to transmit a first voltage signal (for example, a low-level LVGL) to a pull-up node under the control of an input signal at CR1 ⁇ n + 1> Q1, so that the sensing circuit 910 is reset.
  • the control terminal of the twelfth transistor T12 is connected to the total reset line Total_Rs1, its first terminal is connected to the first voltage signal terminal LVGL, and the second terminal is connected to the pull-up node Q1.
  • the total reset sub-circuit of the sensing circuit 910 includes a twelfth transistor T12, and may be configured to transmit a first voltage signal (for example, a low level LVGL) to the pull-up node Q1 under the control of the input signal Total_Rs1, so that The test circuit 910 is reset.
  • the control terminal of the thirteenth transistor T13 is connected to the pull-down node Qb1 of the sensing circuit 910, the first terminal is connected to the first voltage signal terminal LVGL, and the second terminal is connected to the output terminal of the sensing circuit 910 P1 connection.
  • the output pull-down sub-circuit of the sensing circuit 910 includes a thirteenth transistor T13, and can be configured to transmit a first voltage signal (for example, a low-level LVGL) to the output of the sensing circuit 910 under the control of the pull-down node Qb1 P1, so that it outputs a low-level signal.
  • the control terminal of the fourteenth transistor T14 is connected to the pull-down node Qb1 of the sensing circuit 910, the first terminal is connected to the first voltage signal terminal LVGL, and the second terminal is connected to the pull-up node Q1.
  • the pull-up node pull-down sub-circuit of the sensing circuit 910 includes a fourteenth transistor T14, and may be configured to transmit a first voltage signal (for example, a low level LVGL) to the pull-up node Q1 under the control of the pull-down node Qb1, to Therefore, when the pull-down node Qb1 becomes a high level, the pull-up node Q1 remains at a low level.
  • control terminal of the fifteenth transistor T15 is connected to the pull-up node Q1
  • first terminal is connected to the first voltage signal terminal LVGL
  • second terminal is connected to the pull-down node Qb1.
  • the control terminal and the first terminal of the sixteenth transistor T16 are connected to the third voltage signal terminal VGH, and the second terminal is connected to the pull-down node Qb1.
  • the pull-down node control sub-circuit of the sensing circuit 910 includes a fifteenth transistor T15 and a sixteenth transistor T16, and may be configured to control the third voltage signal (for example, high level VGH) under the control of the pull-up node Q1 or One of the first voltage signals (for example, low-level LVGL) is selectively transmitted to the pull-down node Qb1, so that when the pull-up node Q1 is high, the pull-down node Qb1 remains low while the pull-up node When Q1 is low, the pull-down node Qb1 remains high.
  • the third voltage signal for example, high level VGH
  • One of the first voltage signals for example, low-level LVGL
  • the above-mentioned configuration of the sensing circuit 910 can make it realize the shift function.
  • the scanning circuit 920 may include a seventeenth transistor T17 to a twenty-eighth transistor T28 and a second capacitor C2.
  • the control terminal of the seventeenth transistor T17 is connected to the cascade output (ie, the second control output terminal CR2 ⁇ n-1>) of the scan circuit from the shift register of the previous stage, the first The terminal is connected to the third voltage signal terminal VGH, and the second terminal is connected to the pull-up node Q2.
  • the input sub-circuit of the scanning circuit 920 includes a seventeenth transistor T17, and may be configured to transmit a third voltage signal (eg, high level VGH) to the pull-up node under the control of the input signal at CR2 ⁇ n-1> Q2.
  • control terminal of the eighteenth transistor T18 is connected to the pull-up node Q2, the first terminal is connected to the first output clock signal terminal CLK1, and the second terminal is connected to the output terminal P2 of the scanning circuit 920.
  • first terminal of the second capacitor C2 is connected to the pull-up node Q2, and the second terminal of the second capacitor C2 is connected to the output terminal P2 of the scanning circuit 920.
  • the output sub-circuit of the scanning circuit 920 includes an eighth transistor T18 and a second capacitor C2, and can be configured to transmit the signal from the first output clock signal terminal CLK1 to the output of the scanning circuit 920 under the control of the pull-up node Q2 ⁇ P2.
  • control terminal of the nineteenth transistor T19 is connected to the cascade output (ie, the second control output terminal CR2 ⁇ n + 1>) of the scan circuit from the shift register of the next stage, the first The terminal is connected to the first voltage signal terminal LVGL, and the second terminal is connected to the pull-up node Q2.
  • the control terminal of the twentieth transistor T20 is also connected to the cascade output (ie, the second control output terminal CR2 ⁇ n + 1>) of the scan circuit from the shift register of the next stage, and its first terminal is connected to the second voltage The signal terminal VGL is connected, and the second terminal is connected to the output terminal OUT of the shift register 900.
  • the reset sub-circuit of the scanning circuit 920 includes a nineteenth transistor T19 and a twentieth transistor T20, and may be configured to convert the first voltage signal (eg, low level LVGL) under the control of the input signal CR2 ⁇ n + 1> And the second voltage signal (for example, low level VGL) are respectively transmitted to the pull-up node Q2 and the output terminal OUT of the shift register 900 to reset the scanning circuit 920 and make the entire output of the shift register 900 low.
  • the first voltage signal eg, low level LVGL
  • the second voltage signal for example, low level VGL
  • the control terminal of the twenty-first transistor T21 is connected to the total reset line Total_Rs2 (in some embodiments, Total_Rs2 and Total_Rs1 may be the same line or a signal line providing the same operation timing), and the first end It is connected to the first voltage signal terminal LVGL, and the second terminal is connected to the pull-up node Q2.
  • the control terminal of the twenty-second transistor T22 is also connected to the total reset line Total_Rs2, its first terminal is connected to the second voltage signal terminal VGL, and the second terminal is connected to the output terminal OUT of the shift register 900.
  • the total reset sub-circuit of the scanning circuit 920 includes a twenty-first transistor T21 and a twenty-second transistor T22, and may be configured to convert the first voltage signal (for example, a low level LVGL) and the first voltage under the control of the input signal Total_Rs2
  • the two voltage signals (for example, low level VGL) are respectively transmitted to the pull-up node Q2 and the output terminal OUT of the shift register 900 to reset the scanning circuit 920 and make the overall output of the shift register 900 low.
  • the control terminal of the twenty-third transistor T23 is connected to the pull-down node Qb2 of the scanning circuit 920, the first terminal is connected to the first voltage signal terminal LVGL, and the second terminal is connected to the output terminal P2 of the scanning circuit 920 connection.
  • the output pull-down sub-circuit of the scanning circuit 920 includes a twenty-third transistor T23, and may be configured to transmit a first voltage signal (for example, a low level LVGL) to the output terminal P2 of the scanning circuit 920 under the control of the pull-down node Qb2 , So that it outputs a low-level signal.
  • the control terminal of the twenty-fourth transistor T24 is connected to the pull-down node Qb2 of the scanning circuit 920, the first terminal is connected to the first voltage signal terminal LVGL, and the second terminal is connected to the pull-up node Q2.
  • the pull-up node pull-down sub-circuit of the scan circuit 920 includes a twenty-fourth transistor T24, and may be configured to transmit a first voltage signal (for example, a low level LVGL) to the pull-up node Q2 under the control of the pull-down node Qb2, to Therefore, when the pull-down node Qb2 becomes a high level, the pull-up node Q2 maintains a low level.
  • control terminal and the first terminal of the twenty-fifth transistor T25 are connected to the first output clock signal terminal CLK1, and the second terminal is connected to the control terminal of the twenty-sixth transistor T26.
  • the first terminal of the twenty-sixth transistor T26 is connected to the first output clock signal terminal CLK1, and the second terminal is connected to the pull-down node Qb2.
  • the control terminal of the twenty-seventh transistor T27 is connected to the output terminal P2 of the scanning circuit 920, the first terminal is connected to the second voltage signal terminal VGL, and the second terminal is connected to the control terminal of the twenty-sixth transistor T26.
  • the control terminal of the 28th transistor T28 is connected to the output terminal P2 of the scanning circuit 920, the first terminal is connected to the first voltage signal terminal LVGL, and the second terminal is connected to the pull-down node Qb2.
  • the pull-down node control sub-circuit of the scanning circuit 920 includes a twenty-fifth transistor T25, a twenty-sixth transistor T26, a twenty-seventh transistor T27, and a twenty-eighth transistor T28, and can be configured to control the pull-up node Q2
  • One of the high-level clock signal or the first voltage signal (for example, low-level LVGL) of the first output clock signal terminal CLK1 is selectively transmitted to the pull-down node Qb2, so that the pull-up node Q2 is high In this case, the pull-down node Qb2 maintains a low level, and when the pull-up node Q2 is a low level, the pull-down node Qb2 maintains a high level.
  • the above-mentioned configuration of the scanning circuit 920 can make it realize the shift function.
  • the sensing circuit and the scanning circuit of any of the embodiments described above with reference to FIGS. 4 to 7 may have the same structure as the sensing circuit 910 and the scanning circuit 920 described above, respectively.
  • the transistors N2 and N3 can form an inverter, and together can achieve the same function as the inverter shown in FIG. 4, the random shift circuit 930 of FIG. 9 and the random The shift circuit 430 is similar, except that at least the second transistor T2 and the third transistor T3 shown in FIG. 4 are omitted. That is, in the embodiment shown in FIG. 9, when the output enable terminal OE is low, the transistor N3 is turned off, so that the high-level signal of the third voltage signal terminal VGH is transmitted to the first transistor via the turned-on transistor N2 The control terminal of T1, so that the sensing circuit 910 normally outputs a cascade output during the scanning period shown in FIG.
  • the cascade output control sub-circuit may include a first transistor T1, a sixth transistor T6, and an inverter formed by transistors N2 and N3, which realizes the The cascade output control sub-circuit 431 has a similar function.
  • the output sub-circuit of the random shift circuit 930 shown in FIG. 9 has the same structure as the output sub-circuit 435 of the random shift circuit 430 shown in FIG. 4 and will not be repeated here.
  • the frame shift sub-circuit of the random shift circuit 930 shown in FIG. 9 includes a fourth transistor T4 and a fifth transistor T5.
  • the control terminal of the fourth transistor T4 in FIG. 4 which is jointly controlled by the second transistor T2 and the third transistor T3
  • the control terminal of the fourth transistor T4 in FIG. 9 is controlled by the output terminal P1 of the sensing circuit 910.
  • the timing diagram shown in FIG. 6 it can be seen from the timing diagram shown in FIG. 6 that the two can achieve the same or similar functions after being combined with the fifth transistor T5, which will not be repeated here.
  • both the shift register 900 shown in FIG. 9 and the shift register 400 shown in FIG. 4 can provide a “random frame shift” function.
  • FIG. 10 is a circuit diagram illustrating an example shift register 1000 according to yet another embodiment of the present disclosure.
  • the shift register 1000 may include a sensing circuit 1010, a scanning circuit 1020, and a random shift circuit 1030.
  • the random shift circuit 1030 includes, for example, a fourth transistor T4, a fifth transistor T5, a seventh transistor T7, and an eighth transistor T8.
  • transistors and capacitors having the same reference numerals as in FIG. 9 may generally have the same or similar functions as the transistors and capacitors shown in FIG. / Or connection relationship, no more details here.
  • the shift register 1000 shown in FIG. 10 will be used to control the cascade output of the sensing circuit 1010 and the scanning circuit 1020 (ie, the first control output terminal CR1 ⁇ n> and the first The two transistors of the second control output terminal CR2 ⁇ n>), namely the first transistor T1 and the sixth transistor T6, are moved to the sensing circuit 1010 and the scanning circuit 1020 respectively to receive input signals.
  • the control of the cascade output ie, the first control output terminal CR1 ⁇ n> and the second control output terminal CR2 ⁇ n>
  • the shift register 900 shows the same or similar functions.
  • the pull-down control sub-circuits in the sensing circuit 1010 and the scanning circuit 1020 in FIG. 10 are implemented as inverters, respectively. In the case of the timing diagram shown in FIG. 6, they can actually achieve the same or similar functions as the pull-down node control sub-circuits in the sensing circuit 910 and the scanning circuit 920 of FIG.
  • the period of the output enable terminal OE may be the frame frequency, that is, the period of one period may be the same as the period of one frame.
  • the frame shift clock signal terminal CLKs can also adopt this period, and its output signal can be used as the charge signal of the pull-up node Q2 at the same time, and can also be used as the discharge signal of the pull-up node Q2.
  • some embodiments of the present disclosure provide a gate drive circuit (eg, gate drive circuit 500, etc.) including multiple cascaded shift registers (eg, shift registers 300, 400, 700, 800) , 900, 1000, etc.).
  • a gate drive circuit eg, gate drive circuit 500, etc.
  • multiple cascaded shift registers eg, shift registers 300, 400, 700, 800
  • 900, 1000 etc.
  • the display device may include the aforementioned gate driving circuit (for example, the gate driving circuit 500, etc.).
  • the gate driving circuit and the display device By using the shift register and the driving method, the gate driving circuit and the display device according to the embodiment of the present disclosure, the required composite pulse can be generated when the external compensation scheme is adopted, and the correct driving of the pixel circuit can be realized, thereby enabling the OLED display
  • the device emits light more uniformly and the user experience is better.
  • functions described as pure hardware, pure software, and / or firmware in this document can also be realized through a combination of dedicated hardware, general hardware, and software.
  • functions described as being implemented by dedicated hardware eg, field programmable gate array (FPGA), application specific integrated circuit (ASIC), etc.
  • general purpose hardware eg, central processing unit (CPU), digital signal processing DSP (DSP)
  • software and vice versa.

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Abstract

一种移位寄存器及其驱动方法、栅极驱动电路和显示装置。该移位寄存器包括：扫描电路（320），被配置为生成用于在扫描时段使栅极驱动信号中具有行移位部分的第一信号；感测电路（310），被配置为生成用于在消隐时段使所述栅极驱动信号中具有帧移位部分的第二信号；以及随机移位电路（330），与所述扫描电路和所述感测电路分别电连接，并被配置为能够基于所述第一信号和所述第二信号来生成具有所示行移位部分并且随机具有所述帧移位部分的栅极驱动信号。

Description

移位寄存器及其驱动方法、栅极驱动电路和显示装置
本申请要求于2018年11月9日提交的、申请号为201811336183.9的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，且更具体地涉及移位寄存器及其驱动方法、栅极驱动电路和显示装置。
背景技术
随着技术的进步，有机发光二极管OLED(Organic Light Emitting Diode)显示技术得到广泛应用。例如主动矩阵有机发光二极管(AMOLED)显示器因高对比度、可视角度广以及响应速度快有望取代液晶成为下一代显示器的主流选择。在传统OLED产品的像素电路设计中，考虑到工艺的限制，像素电路一般全部利用N型薄膜晶体管(TFT)设计。为了使得显示器发光保持均匀性，因此需要对像素电路中的驱动电压加以补偿。
发明内容
根据本公开一些实施例，提供了移位寄存器及其驱动方法、栅极驱动电路和显示装置。
根据一个方面，本公开的实施例提供了一种移位寄存器。该以为寄存器包括：扫描电路，被配置为生成用于在扫描时段使所述移位寄存器输出的栅极驱动信号中具有行移位部分的第一信号；感测电路，被配置为生成用于在消隐时段使所述栅极驱动信号中具有帧移位部分的第二信号；以及随机移位电路，与所述扫描电路和所述感测电路分别电连接，并被配置为基于所述第一信号和所述第二信号来生成具有所述行移位部分并且随机地具有所述帧移位部分的栅极驱动信号。
例如，所述第一信号包括所述扫描电路的上拉节点处的信号、所述扫描电路的下拉节点处的信号或所述扫描电路的输出端处的信号中的至少一个；并且所述第二信号包括所述感测电路的上拉节点处的信号、所述感测电路的下拉节点处的信号或所述感测电路的输出端处的信号中的至少一个。
在一些实施例中，所述随机移位电路包括：
级联输出控制子电路，与输出使能端、第一控制输出端、第二控制输出端、所述感测电路的输出端和所述扫描电路的输出端连接，并被配置为在所述输出使能端的控制下，向第一控制输出端提供来自所述感测电路的输出端的信号并且向所述第二控制输出端提供来自所述扫描电路的输出端的信号；
帧移位子电路，与所述输出使能端、所述感测电路的上拉节点和下拉节点、帧移位时钟信号端、随机时钟信号端、第一参考信号端和所述扫描电路的上拉节点连接，并被配置为在所述输出使能端、所述感测电路的上拉节点、所述感测电路的下拉节点、所述随机时钟信号端、所述第一参考信号端的控制下，将来自所述帧移位时钟信号端的帧移位时钟信号传递至所述扫描电路的上拉节点；以及
输出子电路，与所述输出时钟信号端、所述扫描电路的上拉节点和下拉节点、第二参考信号端和所述移位寄存器的输出端连接，并被配置为在所述扫描电路的上拉节点和所述扫描电路的下拉节点的控制下，将来自所述输出时钟信号端的输出时钟信号和来自所述第二参考信号端的第二参考信号之一选择性地传递至所述移位寄存器的输出端，作为所述移位寄存器输出的栅极驱动信号。
在一些实施例中，所述随机移位电路包括：
级联输出控制子电路，与信号切换端、第一控制输出端、第二控制输出端、所述感测电路的输出端和所述扫描电路的输出端连接，并被配置为在所述信号切换端的控制下，向所述第一控制输出端提供来自所述感测电路的输出端的信号并且向所述第二控制输出端提供来自所述扫描电路的输出端的信号；
帧移位子电路，与输出使能端、所述感测电路的上拉节点和下拉节点、帧移位时钟信号端、随机时钟信号端、第一参考信号端和所述扫描电路的上拉节点连接，并被配置为在所述输出使能端、所述感测电路的上拉节点、所述感测电路的下拉节点、所述随机时钟信号端和所述第一参考信号端的控制下，将来自所述帧移位时钟信号端的帧移位时钟信号传递至所述扫描电路的上拉节点；以及
输出子电路，与所述输出时钟信号端、所述扫描电路的上拉节点和下拉节点、第二参考信号端和所述移位寄存器的输出端连接，并被配置为在所述扫描电路的上拉节点和所述扫描电路的下拉节点的控制下，将来自所述输出时钟信号端的输出时钟信号和来自所述第二参考信号端的第二参考信号之一选择性地传递至所述移位寄存器的输出端，作为所述移位寄存器输出的栅极驱动信号。
在一些实施例中，所述级联输出控制子电路包括第一晶体管和第六晶体管，
所述第一晶体管的控制端与信号切换端连接，第一端与所述感测电路的输出端连接，以及第二端与所述第一控制输出端连接；以及
所述第六晶体管的控制端与所述信号切换端连接，第一端与所述扫描电路的输出端连接，以及第二端与所述第二控制输出端连接。
在一些实施例中，所述帧移位子电路包括第二晶体管、第三晶体管、第四晶体管和第五晶体管，
所述第二晶体管的控制端与所述感测电路的上拉节点连接，第一端与所述随机时钟信号端连接，以及第二端与所述第四晶体管的控制端连接；
所述第三晶体管的控制端与所述感测电路的下拉节点连接，第一端与所述第一参考信号端连接，以及第二端与所述第四晶体管的控制端连接；
所述第四晶体管的第一端与所述帧移位时钟信号端连接，以及第二端与所述第五晶体管的第一端连接；以及
所述第五晶体管的控制端与所述输出使能端连接，以及第二端与所述扫描电路的上拉节点连接。
在一些实施例中，所述随机移位电路包括：
级联输出控制子电路，与输出使能端、第一控制输出端、第二控制输出端、所述感测电路的输出端和所述扫描电路的输出端连接，并被配置为在所述输出使能端的控制下，向第一控制输出端提供来自所述感测电路的输出端的信号并且向所述第二控制输出端提供来自所述扫描电路的输出端的信号；
帧移位子电路，与输出使能端、所述感测电路的输出端、帧移位时钟信号端和所述扫描电路的上拉节点连接，并被配置为在所述输出使能端和所述感测电路的输出端的控制下，将来自所述帧移位时钟信号端的帧移位时钟信号传递至所述扫描电路的上拉节点；以及
输出子电路，与所述输出时钟信号端、所述扫描电路的上拉节点和下拉节点、第二参考信号端和所述移位寄存器的输出端连接，并被配置为在所述扫描电路的所述上拉节点和所述下拉节点的控制下，将来自所述输出时钟信号端的输出时钟信号和来自所述第二参考信号端的第二参考信号之一选择性地传递至所述移位寄存器的输出端，作为所述移位寄存器输出的栅极驱动信号。
在一些实施例中，所述扫描电路和所述感测电路还被配置为在信号切换端的控制 下选择性接收输入信号，所述感测电路的输出端作为第一控制输出端，以及所述扫描电路的输出端作为第二控制输出端。
在一些实施例中，所述随机移位电路包括：
帧移位子电路，与输出使能端、所述感测电路的输出端、帧移位时钟信号端、和所述扫描电路的上拉节点连接，并被配置为在所述输出使能端和所述感测电路的输出端的控制下，将来自所述帧移位时钟信号端的帧移位时钟信号传递至所述扫描电路的上拉节点；以及
输出子电路，与所述输出时钟信号端、所述扫描电路的上拉节点和下拉节点、第二参考信号端和所述移位寄存器的输出端连接，并被配置为在所述上拉节点和所述下拉节点的控制下，将来自所述输出时钟信号端的输出时钟信号和来自所述第二参考信号端的第二参考信号之一选择性地传递至所述移位寄存器的输出端，作为所述移位寄存器的输出信号。
在一些实施例中，所述帧移位子电路包括第四晶体管和第五晶体管，
所述第四晶体管的控制端与所述感测电路的输出端连接，第一端与所述帧移位时钟信号端连接，以及第二端与所述第五晶体管的第一端连接；以及
所述第五晶体管的控制端与所述输出使能端连接，以及第二端与所述扫描电路的上拉节点连接。
在一些实施例中，所述级联输出控制子电路包括反相器、第一晶体管和第六晶体管，
所述反相器的第一端与所述输出使能端连接，以及第二端与所述第一晶体管的控制端和所述第六晶体管的控制端连接；
所述第一晶体管的第一端与所述感测电路的输出端连接，以及第二端与所述第一控制输出端连接；以及
所述第六晶体管的第一端与所述扫描电路的输出端连接，以及第二端与所述第二控制输出端连接。
在一些实施例中，所述输出子电路包括第七晶体管和第八晶体管，
所述第七晶体管的控制端与所述扫描电路的上拉节点连接，第一端与输出时钟信号端连接，以及第二端与所述移位寄存器的输出端连接；以及
所述第八晶体管的控制端与所述扫描电路的下拉节点连接，第一端与第二参考信号端连接，以及第二端与所述移位寄存器的输出端连接。
根据另一方面，提供了一种栅极驱动电路，包括多个级联的上述移位寄存器。
根据另一方面，提供了一种显示装置，包括上述栅极驱动电路。
根据另一方面，提供了一种用于驱动上述移位寄存器的方法，包括：
由扫描电路在来自输出时钟信号端的输出时钟信号的控制下生成用于在扫描时段使栅极驱动信号中具有行移位部分的第一信号；
由感测电路在来自随机时钟信号端的随机时钟信号的控制下生成用于在消隐时段使所述栅极驱动信号中具有帧移位部分的第二信号；以及
由随机移位电路在来自帧移位时钟信号端的帧移位时钟信号、来自输出时钟信号端的输出时钟信号和来自输出使能端的输出使能信号的控制下，基于所述第一信号和所述第二信号来生成具有随机帧移位的栅极驱动信号。
在一些实施例中，所述移位寄存器还包括与所述随机移位电路或与所述扫描电路和所述感测电路相连的信号切换端，当所述信号切换端处的信号与所述输出使能端处的信号互为反相时，所述随机移位电路根据所述第一信号和所述第二信号来生成随机具有帧移位部分的栅极驱动信号。
在一些实施例中，所述移位寄存器还包括与所述随机移位电路或与所述扫描电路和所述感测电路相连的信号切换端，当所述信号切换端处的信号为恒定高电平信号时，所述随机移位电路根据所述第一信号和所述第二信号来生成顺序地具有帧移位部分的栅极驱动信号。
附图说明
通过下面结合附图说明本公开的优选实施例，将使本公开的上述及其它目的、特征和优点更加清楚，其中：
图1是示出了根据本公开实施例的示例像素电路的电路原理图。
图2是示出了根据本公开实施例的示例像素电路的栅极驱动信号的工作时序图。
图3是示出了根据本公开实施例的示例移位寄存器的构造示意图。
图4是示出了根据本公开实施例的示例移位寄存器的电路原理图。
图5是示出了根据本公开实施例的示例栅极驱动电路的连接关系图。
图6是示出了根据本公开实施例的示例移位寄存器的示例工作时序图。
图7是示出了根据本公开另一实施例的示例移位寄存器的构造示意图。
图8是示出了根据本公开另一实施例的示例移位寄存器的电路原理图。
图9是示出了根据本公开又一实施例的示例移位寄存器的电路原理图。
图10是示出了根据本公开再一实施例的示例移位寄存器的电路原理图。
具体实施方式
下面参照附图对本公开的部分实施例进行详细说明，在描述过程中省略了对于本公开来说是不必要的细节和功能，以防止对本公开的理解造成混淆。在本说明书中，下述用于描述本公开原理的各种实施例只是说明，不应该以任何方式解释为限制公开的范围。参照附图的下述描述用于帮助全面理解由权利要求及其等同物限定的本公开的示例性实施例。下述描述包括多种具体细节来帮助理解，但这些细节应认为仅仅是示例性的。因此，本领域普通技术人员应认识到，在不脱离本公开的范围和精神的情况下，可以对本文中描述的实施例进行多种改变和修改。此外，为了清楚和简洁起见，省略了公知功能和结构的描述。此外，贯穿附图，相同的附图标记用于相同或相似的功能、器件和/或操作。此外，在附图中，各部分并不一定按比例来绘制。换言之，附图中的各部分的相对大小、长度等并不一定与实际比例相对应。
在本公开中，术语“包括”和“含有”及其派生词意为包括而非限制；术语“或”是包含性的，意为和/或。此外，在本公开的以下描述中，所使用的方位术语，例如“上”、“下”、“左”、“右”等均用于指示相对位置关系，以辅助本领域技术人员理解本公开实施例，且因此本领域技术人员应当理解：在一个方向上的“上”/“下”，在相反方向上可变为“下”/“上”，且在另一方向上，可能变为其他位置关系，例如“左”/“右”等。
此外，在本公开的上下文中，如无相反声明，则术语“控制端”通常用来指代晶体管的栅极或基极等；晶体管的“第一端”和“第二端”可以分别指晶体管的源极和漏极或反之，或者可以指晶体管的集电极和发射极或反之；而电容的“第一端”和“第二端”可以分别指代其两个电极。
如前所述，为了实现对像素电路中的驱动电压的补偿，通常可以采用如图1所示意的3T2C像素电路设计，即三个晶体管T1、T2和T3以及两个电容C st和C VC，其中晶体管T1在第一栅极驱动信号(或扫描信号)G1的驱动下，将来自数据线V data的数据信号传导至晶体管T3的栅极，并进而使得驱动电压VDD能够根据数据信号来选择性传输至发光器件(例如，OLED发光器件)EL使其发光。此外，晶体管T2在第二栅极驱动信号(或感测信号)G2的驱动下选择性导通或关闭，使得施加在发光器件上的电压能 够被感测并提供至模数转换器ADC以便进行处理和计算，进而对相应的数据信号/第一栅极驱动信号的调整，使得发光更为均匀。
与此相对应地，图2示出了为了实现上述目的所采用的第一栅极驱动信号G1和第二栅极驱动信号G2的示例时序图。需要注意的是，尽管图2中只示出了用于三行的第一和第二栅极驱动信号G1和G2在三帧期间的工作时序，但本领域技术人员可以据此确定用于任意行的第一和第二栅极驱动信号G1和G2在任意帧期间的工作时序。如图2所示，每一帧的周期包括消隐时段和扫描时段，栅极驱动信号在扫描时段具有行移位部分，在消隐时段具有帧移位部分。行移位部分指的是寄存器产生的栅极驱动信号中逐行移位的部分，例如图2所示，在“第一帧”、“第二帧”、“第三帧”中的每一帧，栅极驱动信号在相邻行上在同一帧内顺序移位，从而实现同一帧内对像素的逐行扫描。帧移位部分指的是寄存器产生的栅极驱动信号中逐帧移位的部分，例如图2中由虚线框所示，栅极驱动信号在相邻行上在相邻帧之间呈现出顺序移位，从而实现每一帧对一行像素进行感测。
在通常的外部补偿方式中，如图2所示，在每一帧的消隐(Blank)时段中，栅极驱动电路产生顺序帧移位时序的栅极驱动信号。不过这种方法容易导致OLED显示装置产生补偿横纹、影响显示画面质量。因此，为了实现能够消除补偿横纹的“随机帧移位”，需要提供一种能够输出“随机帧移位”的栅极驱动信号的方案。
以下，将结合图3～图10来详细描述本公开实施例的能够提供随机帧移位的栅极驱动信号的移位寄存器及其驱动方法、栅极驱动电路和显示装置。在下文中，将以用于控制晶体管T2的第二栅极驱动信号G2为例来详细描述本公开的各实施例。然而，需要注意的是：可以将本公开以下实施例的原理同样应用于需要移位寄存器的其它场合。例如，可以将以下实施例进行简单的改变，就可以适用于图1所示的控制晶体管T1的第一栅极驱动信号G1。此外，在本文中，如无特别声明，所使用的薄膜晶体管TFT均为N型晶体管。然而本公开不限于此，事实上只需要对本公开实施例的各个输入电平、连接关系等进行简单变化，即可使其适用于P型晶体管。
图3是示出了根据本公开实施例的示例移位寄存器300的构造示意图。如图3所示，移位寄存器300可以包括感测电路310、扫描电路320和随机移位电路330。在一些实施例中，扫描电路320可被配置为生成用于在扫描时段使栅极驱动信号中具有行移位部分的第一信号。在一些实施例中，感测电路310可被配置为生成用于在消隐时段使该栅极驱动信号中具有帧移位部分的第二信号。此外，在一些实施例中，随机移位电路330可 与扫描电路320和感测电路310分别电连接，并被配置为基于上述第一信号和第二信号来生成具有行移位部分并且随机具有帧移位部分的栅极驱动信号。需要注意的是：本文中所使用的“第一信号”和“第二信号”可以分别指代一个或多个信号，而不限于单个信号。
在图3中，感测电路310连接随机时钟信号端CLKf、电源信号端(例如第三电压信号端)VGH和第一参考信号端(例如第一电压信号端)LVGL；扫描电路320连接输出时钟信号端CLK、电源信号端VGH和第一参考信号端LVGL；随机移位电路330连接使能端OE、帧移位时钟信号端CLKs、随机时钟信号端CLKf、电源信号端VGH、第一参考信号端LVGL、第二参考信号端(例如第二电压信号端)VGL以及移位寄存器300的输出端OUT。
理论上，感测电路310和/或扫描电路320可以采用任何传统或将来开发的移位寄存器设计。例如，这二者中的任一者或全部二者可以为面板内栅极GIP(Gate In Panel)移位寄存器单元，其可以根据时钟信号来提供标准的信号移位功能。此外，其也可以采用如下文中结合图9或图10所描述的具体示例构造，本公开不限于此。
此外，尽管图3中示出了各个电路与各条信号线之间的示例连接关系，但是本公开不限于此。事实上完全可以采用其它的连接关系，例如图4、图7、图8、图9和图10或其他的连接关系。此外，以下图4、图6、和图8的示例中示出两个输出时钟信号端CLK1和CLK2分别接收第一输出时钟信号和第二输出时钟信号，第一输出时钟信号是第二输出时钟信号的反相信号。对于每个移位寄存器而言，二者可以择一使用。例如，在包括多级级联的移位寄存器单元的栅极驱动电路中，奇数级移位寄存器单元的输出时钟信号端可以连接为接收第一输出时钟信号，偶数级移位寄存器的输出时钟信号端可以连接为接收第二输出时钟信号。类似地，以下图4、图6、和图8中示出两个随机时钟信号端CLKf1和CLKf2分别接收第一随机时钟信号和第二随机时钟信号，第一随机时钟信号是第二随机时钟信号的反相信号。对于每个移位寄存器而言，二者可以择一使用。例如，同样在包括多级级联的移位寄存器单元的栅极驱动电路中，奇数级移位寄存器单元的随机时钟信号端可以连接为接收第一随机时钟信号，偶数级移位寄存器的随机时钟信号端可以连接为接收第二随机时钟信号。
图4是示出了根据本公开实施例的示例移位寄存器400的电路原理图。图4所示的移位寄存器400可以是图3所示的移位寄存器300的一个具体示例。如前文所述，感测电路410和/或扫描电路420可以为传统的或将来开发的移位寄存器设计，因此图4并未 示出这二者的具体电路，然而这并不影响本领域技术人员根据其余部分来合理选用这二者恰当的电路设计来实现期望的功能。
如图4所示，感测电路410可以与随机时钟信号端CLKf相连。感测电路410可以响应于在扫描时段随机时钟信号端CLKf的信号波形发生随机变化，使感测电路410的上拉节点Q1处的信号在扫描时段和消隐时段均保持有效。随机移位电路430可以与感测电路410的上拉节点Q1、扫描电路420的上拉节点Q2和帧移位时钟信号端CLKs相连。随机移位电路430可以在消隐时段在感测电路410的上拉节点Q1处的信号的控制下使扫描电路420在其上拉节点Q2处存储帧移位时钟信号端CLKs的电压，并基于所存储的电压产生具有所述帧移位部分的栅极驱动信号。
如图4所示，随机移位电路430可包括级联输出控制子电路431、帧移位子电路433和输出子电路435。在一些实施例中，级联输出控制子电路431可与输出使能端OE、感测电路410的输出端P1、扫描电路420的输出端P2、第一控制输出端CR1<n>和第二控制输出端CR2<n>(在本实施例中假定图4所示的移位寄存器为第n级移位寄存器，<n>表示其所在的级数)。第一控制输出端CR1<n>和第二控制输出端CR2<n>可以与相邻移位寄存器的输入端或复位端连接以形成级联结构。
级联输出控制子电路431可以在输出使能端OE的控制下，向第一控制输出端CR1<n>(从而向相邻移位寄存器)提供来自感测电路410的输出端P1的信号，向第二控制输出端CR2<n>提供来自扫描电路420的输出端P2的信号，以作为相邻移位寄存器的输入信号或复位信号。在一些实施例中，帧移位子电路433可与输出使能端OE、感测电路410的上拉节点Q1和下拉节点Qb1、帧移位时钟信号端CLKs、随机时钟信号端(在图4中虽然示出了分别接收第一随机时钟信号和第二随机时钟信号的两个时钟信号端CLKf1和CLKf2，但这仅仅是示意，可以根据需要选择二者之一来使用，在本实施例中假设使用第一随机时钟信号端CLKf1来接收第一随机时钟信号)、第一电压信号端(第一参考信号端)LVGL和扫描电路420的上拉节点Q2连接，并被配置为在输出使能端OE、上拉节点Q1、下拉节点Qb1、第一随机时钟信号端CLKf1、第一电压信号端LVGL的控制下，将来自帧移位时钟信号端CLKs的帧移位时钟信号传递至上拉节点Q2。在一些实施例中，输出子电路435可与时钟信号端(在图4中虽然示出了分别连接第一输出时钟信号和第二输出时钟信号的两个时钟信号端CLK1和CLK2，但这仅仅是示意，可以根据需要选择二者之一来使用，在本实施例中假设使用第一输出时钟信号端CLK1来接收第一输出时钟信号)、扫描电路420的上拉节点Q2和下拉节点Qb2、第二电压信 号端VGL和移位寄存器400的输出端连接，并被配置为在上拉节点Q2和下拉节点Qb2的控制下，将来自第一输出时钟信号端CLK1的第一输出时钟信号和来自第二电压信号端(第二参考信号端)VGL的第二电压信号之一选择性地传递至移位寄存器400的输出端OUT，作为移位寄存器400的输出信号(即栅极驱动信号)。
在一些实施例中，级联输出控制子电路431可包括反相器INV、第一晶体管T1和第六晶体管T6。该反相器INV的第一端可与输出使能端OE连接，以及第二端可与第一晶体管T1的控制端和第六晶体管的控制端连接。此外，第一晶体管T1的第一端可与感测电路410的输出端P1连接，以及第二端可与第一控制输出端CR1<n>相连，从而与下一级移位寄存器的感测电路的输入端和/或上一级移位寄存器的感测电路的复位端连接。此外，第六晶体管T6的第一端可与扫描电路420的输出端P2连接，以及第二端可与第二控制输出端CR2<n>相连，从而与下一级移位寄存器的扫描电路的输入端和/或上一级移位寄存器的扫描电路的复位端连接。此外，在一些实施例中，该反相器INV可以是由晶体管形成的反相器，可以根据需要实现为期望的结构，这里不再详细描述。
此外，在一些实施例中，帧移位子电路433可包括第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5。第二晶体管T2的控制端可与感测电路410的上拉节点Q1连接，第一端可与第一随机时钟信号端CLKf1连接，以及第二端可与第四晶体管T4的控制端连接。第三晶体管T3的控制端可与感测电路410的下拉节点Qb1连接，第一端与第一电压信号端LVGL连接，以及第二端可与第四晶体管T4的控制端连接。第四晶体管T4的第一端可与帧移位时钟信号端CLKs连接，以及第二端可与第五晶体管T5的第一端连接。此外，第五晶体管T5的控制端可与输出使能端OE连接，以及第二端可与扫描电路420的上拉节点Q2连接。
此外，在一些实施例中，输出子电路435可包括第七晶体管T7和第八晶体管T8。第七晶体管T7的控制端可与扫描电路420的上拉节点Q2连接，第一端可与第一输出时钟信号端CLK1连接，以及第二端可与移位寄存器400的输出端OUT连接。此外，第八晶体管T8的控制端可与扫描电路420的下拉节点Qb2连接，第一端可与第二电压信号端VGL连接，以及第二端可与移位寄存器400的输出端OUT连接。
在图4所示实施例中，CR1<n>表示该第n行移位寄存器400的感测电路410的级联输出(第一控制输出端)，其通向第n+1行移位寄存器的感测电路的输入端和/或第n-1行移位寄存器的感测电路的复位端。类似地，CR2<n>表示该第n行移位寄存器400的扫描电路420的级联输出(第二控制输出端)，其通向第n+1行移位寄存器的扫描电 路的输入端和/或第n-1行移位寄存器的扫描电路的复位端。
此外，如结合图3所描述的，感测电路410所生成的第二信号可以包括例如其输出端P1输出的输出信号、其上拉节点Q1和下拉节点Qb1的电平信号等等。类似地，扫描电路420所生成的第一信号可以包括例如其输出端P2输出的输出信号、其上拉节点Q2和下拉节点Qb2的电平信号等等。
此外，在一些实施例中，第一电压信号端LVGL和第二电压信号端VGL可以提供低电压信号，这二者可以具有不同电压，例如一个是-5V，另一个是0V；第三电压信号端VGH可以提供高电压信号，例如其可以提供+5V电压信号，然而本公开不限于此，这完全取决于具体的电路设计。例如，在另一些实施例中，第一电压信号端LVGL和第二电压信号端VGL可以提供具有相同电压的低电压信号。
图5是示出了根据本公开实施例的示例栅极驱动电路500的连接关系图。如图5所示，栅极驱动电路500可以由多个级联的移位寄存器(例如，移位寄存器300或400)级联而成，其中，前一级的感测电路或扫描电路的输出可以是当前级的感测电路或扫描电路的输入(或置位)，而下一级的感测电路或扫描电路的输出可以是当前级的感测电路或扫描电路的复位。例如第n-1级移位寄存器的第一控制输出端CR1<n-1>连接至第n级移位寄存器的感测电路的输入端，第二控制输出端CR2<n-1>连接至第n级移位寄存器的扫描电路的输入端；第n+1级移位寄存器的第一控制输出端CR1<n+1>连接至第n级移位寄存器的感测电路的复位端，第n+1级移位寄存器的第二控制输出端CR1<n+2>连接至第n级移位寄存器的扫描电路的复位端，从而使感测电路和扫描电路分别形成各自的级联结构。
此外，相邻级的时钟信号端可以不同顺序接收互为反相的时钟信号。例如，如果第n-1级的移位寄存器的第一输出时钟信号端CLK1和第二时钟信号端CLK2分别连接到时钟信号线CLK1和CLK2，则第n级的移位寄存器的第一输出时钟信号端CLK1和第二时钟信号端CLK2可分别连接到时钟信号线CLK2和CLK1，以此类推。类似地，如果第n-1级的移位寄存器的第一随机时钟信号端CLKf1和第二随机时钟信号端CLKf2分别连接到随机时钟信号线CLKf1和CLKf2，则第n级的移位寄存器的第一随机时钟信号端CLKf1和第二随机时钟信号端CLKf2可分别连接到随机时钟信号线CLKf2和CLKf1，以此类推。
以下，将结合图4和图5来详细说明图6所示的移位寄存器400的工作时序。图6是示出了根据本公开实施例的示例移位寄存器400的示例工作时序图。
假定移位寄存器400的第一输出时钟信号端CLK1和第二输出时钟信号端CLK2分别连接到第一输出时钟信号线CLK1和第二输出时钟信号线CLK2，且移位寄存器400的第一随机时钟信号端CLKf1和第二随机时钟信号端CLKf2分别连接到第一随机时钟信号线CLKf1和第二随机时钟信号线CLKf2。因此，在本实施例中，在不失一般性的情况下，将相应时钟信号端与相应时钟信号线加以等同。
如图6所示，第一输出时钟信号线CLK1和第二时钟信号线CLK2在扫描时段提供互为反相的时钟信号。此外，第一随机时钟信号线CLKf1和第二随机时钟信号线CLKf2在扫描时段中提供随机时钟信号。该随机时钟信号可以为周期脉冲信号，该周期脉冲信号的波形在一随机时刻发生变化，例如在该随机时刻之后持续为低电平。例如，如图6所示，第一随机时钟信号线CLKf1和第二时钟信号线CLK2提供的随机时钟信号在若干个脉冲周期结束之后，在本来应该出现下一个脉冲的时段，并未出现下一个脉冲，而是取代以持续的低电平。在一些实施例中，可以使随机时钟信号端在随机信号控制下随机地保持持续电位。例如可以通过一随机脉冲信号将周期脉冲信号的电平强制地持续性拉低来实现上述随机时钟信号。在一些实施例中，该随机脉冲信号可以由现场可编程门阵列(FPGA)产生。
根据图4所示的移位寄存器400的电路设计，如果在该随机时刻或时段某一级移位寄存器产生输出信号，则可以在消隐时段控制该级移位寄存器输出感测所需的栅极驱动信号，下文中将详细说明。换言之，第一和第二随机时钟信号线CLKf1和CLKf2上的时钟信号相当于用于选择相应行移位寄存器的随机时钟信号。
以图6为例，在第一帧扫描期间，第一随机时钟信号线CLKf1上的第一随机时钟信号中以虚线标出的高电平脉冲表示在该时刻出现一个虚拟的“随机脉冲”，即，在该时刻本来应该出现下一个脉冲，但是并未出现，而是取代以持续的低电平。为了更清楚地说明这一点，图6示出了该虚拟的随机脉冲，该虚拟脉冲并非实际信号，而是表示在虚线所示的时刻本应出现的高电平并未出现，而是取代以低电平。在图6中，在扫描时段中虚拟的“随机脉冲”期间，第M行移位寄存器产生输出信号OUT<M>，从而使第M行移位寄存器被选择，被选择的第M行移位寄存器将在消隐时段产生高电平的输出信号以用于驱动相应行像素单元从而进行感测，而未被选择的其他行移位寄存器产生低电平的输出信号。
接下来，同时参考图4和图6来详细说明实现随机帧移位的原理。假定图4所示的移位寄存器400就是该第M行的移位寄存器。由于由虚线标出的CLKf1高电平脉冲是 并未实际出现的随机脉冲，导致图4所示的移位寄存器400的感测电路410在与该随机脉冲相对应的时段中输出低电平，从而使得从第M+1行开始的后续各行移位寄存器的感测电路的输入/输出都始终保持低电平，进而使得第M行的移位寄存器400的感测电路410不会被来自第M+1行的感测电路的输出信号所复位，使得其第一点Q1始终保持为高电平，如图6“M行Q1”所示。具体地，移位寄存器400的感测电路410在一帧的时间中可以在与其相对应的时钟脉冲出现时才输出高电平。换言之，在级联的前M-1个感测电路都按顺序输出了自己的高电平之后，本来当前级(即，第M级)的感测电路410所连接的随机时钟信号端CLKf应当为高电平以使感测电路410输出高电平(例如，参见图9所示的T10晶体管的设置，其负责向输出端P1输出随机时钟信号端CLKf处的信号)，但此时如前所述高电平未出现，导致第M个感测电路410不再输出高电平，从而后续所有级移位寄存器单元的感测电路410都没有高电平输入，自然也都没有高电平输出。
此外，与感测电路410不同的是，扫描电路420所连接的是第一输出时钟信号线CLK1，因此在该随机脉冲发生的时段，其实际上保持正常的时钟信号输出，从而如图6中“M行Q2”所示，在其相应的时段中保持高电位，而后续被来自第M+1行的扫描电路的输出信号所复位，变为低电位。
进一步地，在扫描期间，输出使能端OE始终保持低电平，因此在其经过反向器INV变为高电平之后，第一晶体管T1和第六晶体管T6导通，进而使得感测电路410和扫描电路420的级联输出CR1<M>和CR2<M>保持正常输出。此外，由于输出使能端OE始终保持低电平，因此第五晶体管T5在其控制下始终保持关闭状态，因此帧移位将不会在扫描期间出现在移位寄存器400的输出端OUT上。从而，如图6所示，在扫描时段，移位寄存器单元的输出端OUT<M>为正常的栅极扫描信号，即在相应的时段中为高电平，其余时间保持低电平。
接下来，在消隐期间，输出使能端OE保持高电平，因此在其经过反向器IN变为低电平之后，第一晶体管T1和第六晶体管T6关闭，进而感测电路410和扫描电路420的第一控制输出端CR1<M>和第二控制输出端CR2<M>不会输出高电平，从而不会引起后续移位寄存器输出高电平。此外，由于输出使能端OE始终保持高电平，因此第五晶体管T5在其控制下导通，进而从第四晶体管T4到扫描电路420的上拉节点Q2的路径导通。
如前所述，感测电路410的上拉节点Q1在扫描时段的后期(即，随机脉冲出现之 后)开始始终保持高电平，因此第二晶体管T2导通，从而使得第一随机时钟信号线CLKf1的信号传输到第四晶体管T4的栅极。如图6所示，第一随机时钟信号线CLKf1在消隐时段开始时是高电平信号，从而使得第四晶体管T4相应导通，并使得来自帧移位时钟信号端CLKs的高电平信号通过第四晶体管T4和前述导通的第五晶体管T5传输到扫描电路420的上拉节点Q2处。
在图4所示的扫描电路420中，类似于图9所示的扫描电路920，Q2点的高电平将导通例如第十八晶体管T18，并使得第二电容C2开始充电。在来自帧移位时钟信号端CLKs的高电平信号结束之后，由于此时上拉节点Q2依然保持高电平，且来自第一输出时钟信号端CLK1的第一输出时钟信号从低电平变为高电平，进而通过第二电容C2的自举作用将上拉节点Q2的电位提升到更高，如图6中“M行Q2”所示。此外，由于没有来自下一级移位寄存器的扫描电路的复位信号，因此该高电位将保持到出现总复位信号Total_Rs1为止。从而，第七晶体管T7在该上拉节点Q2的高电位的作用下导通，使得输出端OUT<M>输出来自第一输出时钟信号端CLK1的第一输出时钟信号作为输出信号，从而得到如图6中“OUT<M>”所示的输出信号。该输出信号可以例如作为如图1所示的像素电路的第二栅极驱动信号G2。
在第一帧中，在与第M级不同的第N级的移位寄存器中，由于其感测电路的上拉节点Q1并未像第M级移位寄存器400中的感测电路410的上拉节点Q1一样在扫描期间保持高电位，因此其在消隐期间将始终保持低电位，如图6中“N行Q1”所示，进而使得其得到相应的上拉节点Q2低电位和输出端低电位，分别如图6中“N行Q2”和“OUT<N>”所示。
类似地，在第二帧扫描期间，在第二随机时钟信号线CLKf2上的以虚线标出的高电平脉冲表示虚拟随机脉冲到来(更清楚地，可参见“随机脉冲”行的脉冲)，在该虚拟脉冲期间第N行移位寄存器在输出端OUT<N>产生高电平的输出信号。这里假定第M行移位寄存器连接随机时钟信号端CLKf1和输出时钟信号端CLK1，第N行移位寄存器连接随机时钟信号端CLKf2和输出时钟信号端CLK2，如图5中所示。
与前面针对第M行移位寄存器的描述类似地，第N行移位寄存器的输出端OUT<N>输出来自第二时钟信号端CLK2的第二时钟信号，从而得到如图6中“OUT<N>”所示的在第二帧期间的输出信号。该输出信号可以例如作为如图1所示的像素电路的第二栅极驱动信号G2。
在第二帧中，在与第N级不同的第M级的移位寄存器中，由于其感测电路的上拉 节点Q1并未像第N行的移位寄存器中的感测电路的上拉节点Q1一样在扫描期间保持高电位，因此其在消隐期间将始终保持低电位，如图6中“M行Q1”所示，进而使得其得到相应的上拉节点Q2低电位和输出端低电位，分别如图6中“M行Q2”和“OUT<M>”所示。
可见，如图6所示，在连续的两帧中，分别在第M级和第N级的移位寄存器中输出帧移位，从而实现了随机帧移位功能。
更一般地，结合图6所描述的驱动方法可以包括：由扫描电路420在来自输出时钟信号端(例如第一输出时钟信号端CLK1的第一输出时钟信号或来自第二输出时钟信号端CLK2的第二输出时钟信号)的控制下生成用于在扫描时段使栅极驱动信号中具有行移位部分的第一信号；由感测电路410在来自第一随机时钟信号端CLKf1的第一随机时钟信号(例如来自第一随机时钟信号端CLKf1的第一随机时钟信号或来自第二随机时钟信号端CLKf2的第二随机时钟信号)的控制下生成用于在消隐时段使栅极驱动信号中具有帧移位部分的第二信号；以及由随机移位电路430在来自帧移位时钟信号端CLKs的帧移位时钟信号、来自输出时钟信号端的输出时钟信号(例如来自第一输出时钟信号端CLK1的第一输出时钟信号)、来自随机时钟信号端的随机时钟信号(例如来自第一随机时钟信号端CLKf1的第一随机时钟信号)、来自输出使能端OE的输出使能信号的控制下基于前述第一信号和前述第二信号来生成具有行移位部分并且随机具有帧移位部分的栅极驱动信号。
图7是示出了根据本公开另一实施例的示例移位寄存器700的构造示意图。如图7所示，移位寄存器700可以包括感测电路710、扫描电路720和随机移位电路730。与图3相类似地，在一些实施例中，扫描电路720可被配置为生成用于在扫描时段使栅极驱动信号中具有行移位部分的第一信号。此外，在一些实施例中，感测电路710可被配置为生成用于在消隐时段使该栅极驱动信号中具有帧移位部分的第二信号。在一些实施例中，随机移位电路730可与扫描电路720和感测电路710分别电连接，并被配置为能够基于上述第一信号和第二信号来生成具有行移位部分并且随机具有帧移位部分的栅极驱动信号。
类似地，感测电路710和/或扫描电路720可以采用任何传统的或将来开发的移位寄存器设计。例如，这二者中的任一者或全部二者可以为GIP移位寄存器单元，其可以根据随机时钟信号来提供标准的信号移位功能。此外，其也可以采用如下文中结合图9或图10所描述的具体示例构造，本公开不限于此。
此外，尽管图7中示出了各个电路与各条信号线之间的示例连接关系，但是本公开不限于此。事实上完全可以采用其它的连接关系，例如图3、图4、图8、图9和图10等的连接关系。此外，第一输出时钟信号端CLK1的第一输出时钟信号和第二输出时钟信号端CLK2的第二输出时钟信号互为反相，第一随机时钟信号端CLKf1的第一随机时钟信号和第二随机时钟信号端CLKf2的第二随机时钟信号互为反相，可以选择二者之一来使用。例如，可以使栅极驱动电路中的奇数级移位寄存器连接第一输出时钟信号端CLK1和第一随机时钟信号端CLKf1，通过反相器等来形成第二输出时钟信号端CLK2和第二随机时钟信号端CLKf2，并将偶数级移位寄存器单元连接到第二输出时钟信号端CLK2和第二随机时钟信号端CLKf2，其它情况也类似成立。
图8是示出了根据本公开另一实施例的示例移位寄存器800的电路原理图。图8所示的移位寄存器800可以是图7所示的移位寄存器700的一个具体示例。由于上文指出的感测电路810和/或扫描电路820可以为传统的或将来开发的移位寄存器设计，因此图8并未示出这二者的具体电路，然而这并不影响本领域技术人员根据其余部分来合理选用这二者恰当的电路设计来实现期望的功能。
如图8所示，随机移位电路830可包括：级联输出控制子电路831、帧移位子电路833和输出子电路835。在一些实施例中，级联输出控制子电路831可与信号切换端SW、感测电路810的输出端P1、扫描电路820的输出端P2以及第一控制输出端CR1<n>和第二控制输出端CR2<n>以便与相邻移位寄存器的输入端或复位端连接，并被配置为在信号切换端SW的控制下，向第一控制输出端CR1<n>和第二控制输出端CR2<n>(从而向相邻移位寄存器)分别提供来自感测电路810的输出端和扫描电路820的输出端的输出信号，作为相邻移位寄存器的输入信号或复位信号。在一些实施例中，帧移位子电路833可与输出使能端OE、感测电路810的上拉节点Q1和下拉节点Qb1、帧移位时钟信号端CLKs、第一随机时钟信号端ACLKf1、第一电压信号端LVGL和扫描电路820的上拉节点Q2连接，并被配置为在输出使能端OE、上拉节点Q1、下拉节点Qb1、第一随机时钟信号端CLKf1、第一电压信号端LVGL的控制下，将来自帧移位时钟信号端CLKs的帧移位时钟信号传递至上拉节点Q2。在一些实施例中，输出子电路835可与第一输出时钟信号端CLK1、扫描电路820的上拉节点Q2和下拉节点Qb2、第二电压信号端VGL和移位寄存器800的输出端连接，并被配置为在上拉节点Q2、下拉节点Qb2的控制下，将来自第一输出时钟信号端CLK1的第一输出时钟信号和来自第二电压信号端VGL的第二电压信号之一选择性地传递至移位寄存器800的输出端OUT，作为移位 寄存器800的输出信号。
在一些实施例中，级联输出控制子电路831可包括第一晶体管T1和第六晶体管T6。该第一晶体管T1的控制端与信号切换端SW连接，第一端可与感测电路810的输出端P1连接，以及第二端可与第一控制输出端CR1<n>连接，从而与下一级移位寄存器的感测电路的输入端和/或上一级移位寄存器的感测电路的复位端连接。此外，第六晶体管T6的控制端可与信号切换端SW连接，第一端可与扫描电路820的输出端P2连接，以及第二端可与第二控制输出端CR2<n>连接，从而与下一级移位寄存器的扫描电路的输入端和/或上一级移位寄存器的扫描电路的复位端连接。
此外，在一些实施例中，帧移位子电路833和输出子电路835可以与图4所示的帧移位子电路433和输出子电路435具有相同或类似的结构，这里就不再赘述。
与图4所示移位寄存器400不同的是，图8所示的移位寄存器800中的级联输出控制子电路831是通过单独的信号切换端SW的控制信号来控制的。换言之，在一些实施例中，当信号切换端SW提供的信号与输出使能端OE提供的信号互为反相时，则随机移位电路830可被配置为能够根据感测电路810输出的第二信号和扫描电路820输出的第一信号来生成具有行移位部分并且随机具有帧移位部分的栅极驱动信号。更具体地，当图8中的信号切换端SW输出与输出使能端OE反相的信号时，其实质上就相当于图4所示的输出使能端OE加上反相器，从而使得图8所示的移位寄存器800能够实现与图4所示移位寄存器400相同的功能。
在另一些实施例中，当信号切换端SW输出恒定高电平信号时，则随机移位电路830可被配置为能够根据感测电路810输出的第二信号和扫描电路820输出的第一信号来生成具有行扫描部分并且顺序具有帧移位部分的栅极驱动信号。更具体地，当图8中的信号切换端SW始终输出高电平信号时，感测电路810和扫描电路820的级联输出端(即第一控制输出端CR1<n>和第二控制输出端CR2<n>)将始终正常输出信号。此时配合第一随机时钟信号端CLKf1和/或第二随机时钟信号端CLKf2的随机时钟信号(例如，顺序出现的随机脉冲，此时也可以将其称为顺序脉冲)，可以使得移位寄存器800可以像普通移位寄存器一样输出顺序地具有帧移位部分的栅极驱动信号。从而，通过调整信号切换端SW的输出信号，可以使得同一个移位寄存器可以既支持随机帧移位也支持顺序帧移位。
图9是示出了根据本公开又一实施例的示例移位寄存器900的电路原理图。如图9所示，移位寄存器900可以包括感测电路910、扫描电路920和随机移位电路930。如图 9所示，随机移位电路930包括第一晶体管T1至第八晶体管T8。
在一些实施例中，感测电路910可以包括第九晶体管T9至第十六晶体管T16以及第一电容C1。在一些实施例中，第九晶体管T9的控制端与来自上一级的移位寄存器的感测电路的级联输出(即第一控制输出端CR1<n-1>)连接以接收输入信号，其第一端与第三电压信号端VGH连接，以及第二端与上拉节点Q1连接。感测电路910的输入子电路包括第九晶体管T9，并且可被配置为在CR1<n-1>处的输入信号的控制下将第三电压信号(例如，高电平VGH)传输至上拉节点Q1。
在一些实施例中，第十晶体管T10的控制端与上拉节点Q1连接，其第一端与第一随机时钟信号端CLKf1连接，以及第二端与感测电路910的输出端P1连接。此外，在一些实施例中，第一电容C1的第一端与上拉节点Q1连接，其第二端与感测电路910的输出端P1连接。第十晶体管T10和第一电容C1可以构成感测电路910的输出子电路，其可被配置为在上拉节点Q1的控制下，将来自第一随机时钟信号端CLKf1的信号传输至感测电路910的输出端。
在一些实施例中，第十一晶体管T11的控制端与来自下一级的移位寄存器的感测电路的级联输出(即，第一控制信号端CR1<n+1>)连接以接收输入信号，其第一端与第一电压信号端LVGL连接，以及第二端与上拉节点Q1连接。感测电路910的复位子电路包括第十一晶体管T11，并且可被配置为在CR1<n+1>处的输入信号控制下将第一电压信号(例如，低电平LVGL)传输至上拉节点Q1，以使得感测电路910复位。
在一些实施例中，第十二晶体管T12的控制端与总复位线Total_Rs1连接，其第一端与第一电压信号端LVGL连接，以及第二端与上拉节点Q1连接。感测电路910的总复位子电路包括第十二晶体管T12，并且可被配置为在输入信号Total_Rs1的控制下将第一电压信号(例如，低电平LVGL)传输至上拉节点Q1，以使得感测电路910复位。
在一些实施例中，第十三晶体管T13的控制端与感测电路910的下拉节点Qb1连接，其第一端与第一电压信号端LVGL连接，以及第二端与感测电路910的输出端P1连接。感测电路910的输出下拉子电路包括第十三晶体管T13，并且可被配置为在下拉节点Qb1的控制下将第一电压信号(例如，低电平LVGL)传输至感测电路910的输出端P1，以使得其输出低电平信号。
在一些实施例中，第十四晶体管T14的控制端与感测电路910的下拉节点Qb1连接，其第一端与第一电压信号端LVGL连接，以及第二端与上拉节点Q1连接。感测电路910的上拉节点下拉子电路包括第十四晶体管T14，并且可被配置为在下拉节点Qb1的控制 下将第一电压信号(例如，低电平LVGL)传输至上拉节点Q1，以使得在下拉节点Qb1变为高电平的情况下，上拉节点Q1保持低电平。
在一些实施例中，第十五晶体管T15的控制端与上拉节点Q1连接，其第一端与第一电压信号端LVGL连接，以及第二端与下拉节点Qb1连接。第十六晶体管T16的控制端和第一端与第三电压信号端VGH连接，以及第二端与下拉节点Qb1连接。感测电路910的下拉节点控制子电路包括第十五晶体管T15和第十六晶体管T16，并且可被配置为在上拉节点Q1的控制下将第三电压信号(例如，高电平VGH)或第一电压信号(例如，低电平LVGL)之一选择性传输至下拉节点Qb1，以使得在上拉节点Q1为高电平的情况下，下拉节点Qb1保持低电平，而在上拉节点Q1为低电平的情况下，下拉节点Qb1保持高电平。
从而，感测电路910的上述构造可以使得其实现移位功能。
在一些实施例中，扫描电路920可以包括第十七晶体管T17至第二十八晶体管T28以及第二电容C2。在一些实施例中，第十七晶体管T17的控制端与来自上一级的移位寄存器的扫描电路的级联输出(即，第二控制输出端CR2<n-1>)连接，其第一端与第三电压信号端VGH连接，以及第二端与上拉节点Q2连接。扫描电路920的输入子电路包括第十七晶体管T17，并且可被配置为在CR2<n-1>处的输入信号的控制下将第三电压信号(例如，高电平VGH)传输至上拉节点Q2。
在一些实施例中，第十八晶体管T18的控制端与上拉节点Q2连接，其第一端与第一输出时钟信号端CLK1连接，以及第二端与扫描电路920的输出端P2连接。此外，在一些实施例中，第二电容C2的第一端与上拉节点Q2连接，其第二端与扫描电路920的输出端P2连接。扫描电路920的输出子电路包括第八晶体管T18和第二电容C2，并且可被配置为在上拉节点Q2的控制下，将来自第一输出时钟信号端CLK1的信号传输至扫描电路920的输出端P2。
在一些实施例中，第十九晶体管T19的控制端与来自下一级的移位寄存器的扫描电路的级联输出(即，第二控制输出端CR2<n+1>)连接，其第一端与第一电压信号端LVGL连接，以及第二端与上拉节点Q2连接。第二十晶体管T20的控制端也与来自下一级的移位寄存器的扫描电路的级联输出(即，第二控制输出端CR2<n+1>)连接，其第一端与第二电压信号端VGL连接，以及第二端与移位寄存器900的输出端OUT连接。扫描电路920的复位子电路包括第十九晶体管T19和第二十晶体管T20，并且可被配置为在输入信号CR2<n+1>的控制下将第一电压信号(例如，低电平LVGL)和第二电压信号 (例如，低电平VGL)分别传输至上拉节点Q2和移位寄存器900的输出端OUT，以使得扫描电路920复位并使得移位寄存器900的整体输出为低电平。
在一些实施例中，第二十一晶体管T21的控制端与总复位线Total_Rs2连接(在一些实施例中，Total_Rs2和Total_Rs1可以是同一根线或提供相同工作时序的信号线)，其第一端与第一电压信号端LVGL连接，以及第二端与上拉节点Q2连接。第二十二晶体管T22的控制端也与总复位线Total_Rs2连接，其第一端与第二电压信号端VGL连接，以及第二端与移位寄存器900的输出端OUT连接。扫描电路920的总复位子电路包括第二十一晶体管T21和第二十二晶体管T22，并且可被配置为在输入信号Total_Rs2的控制下将第一电压信号(例如，低电平LVGL)和第二电压信号(例如，低电平VGL)分别传输至上拉节点Q2和移位寄存器900的输出端OUT，以使得扫描电路920复位并使得移位寄存器900的整体输出为低电平。
在一些实施例中，第二十三晶体管T23的控制端与扫描电路920的下拉节点Qb2连接，其第一端与第一电压信号端LVGL连接，以及第二端与扫描电路920的输出端P2连接。扫描电路920的输出下拉子电路包括第二十三晶体管T23，并且可被配置为在下拉节点Qb2的控制下将第一电压信号(例如，低电平LVGL)传输至扫描电路920的输出端P2，以使得其输出低电平信号。
在一些实施例中，第二十四晶体管T24的控制端与扫描电路920的下拉节点Qb2连接，其第一端与第一电压信号端LVGL连接，以及第二端与上拉节点Q2连接。扫描电路920的上拉节点下拉子电路包括第二十四晶体管T24，并且可被配置为在下拉节点Qb2的控制下将第一电压信号(例如，低电平LVGL)传输至上拉节点Q2，以使得在下拉节点Qb2变为高电平的情况下，上拉节点Q2保持低电平。
在一些实施例中，第二十五晶体管T25的控制端和第一端与第一输出时钟信号端CLK1连接，以及第二端与第二十六晶体管T26的控制端连接。第二十六晶体管T26的第一端与第一输出时钟信号端CLK1连接，以及第二端与下拉节点Qb2连接。第二十七晶体管T27的控制端与扫描电路920的输出端P2连接，其第一端与第二电压信号端VGL连接，以及第二端与第二十六晶体管T26的控制端连接。第二十八晶体管T28的控制端与扫描电路920的输出端P2连接，第一端与第一电压信号端LVGL连接，以及第二端与下拉节点Qb2连接。扫描电路920的下拉节点控制子电路包括第二十五晶体管T25、第二十六晶体管T26、第二十七晶体管T27和第二十八晶体管T28，并且可被配置为在上拉节点Q2的控制下将第一输出时钟信号端CLK1的高电平时钟信号或第一电压信号 (例如，低电平LVGL)之一选择性传输至下拉节点Qb2，以使得在上拉节点Q2为高电平的情况下，下拉节点Qb2保持低电平，而在上拉节点Q2为低电平的情况下，下拉节点Qb2保持高电平。
从而，扫描电路920的上述构造可以使得其实现移位功能。
以上参考图4至图7描述的任意实施例的感测电路和扫描电路可以分别具有与上述感测电路910和扫描电路920相同的结构。
在图9所示的实施例中，晶体管N2和N3可以形成反相器，凑个能够实现与图4所示的反相器相同的功能，图9的随机移位电路930与图4的随机移位电路430类似，区别至少在于省略了图4所示的第二晶体管T2和第三晶体管T3。即，在图9所示实施例中，当输出使能端OE为低电平时，晶体管N3关闭，使得第三电压信号端VGH的高电平信号经由导通的晶体管N2被传输至第一晶体管T1的控制端，从而使得感测电路910在图6所示的扫描时段期间正常输出级联输出(即，在第一控制输出端CR1<n>正常输出)。当输出使能端OE为高电平时，第三晶体管T3导通，使得来自第一电压信号端LVGL的低电平信号经由导通的第三晶体管T3到达第一晶体管T1的控制端，从而使得感测电路910在图6所示的消隐时段期间不输出级联输出(即，第一控制输出端CR1<n>始终为低电平)。对于第六晶体管T6，同样如此。因此，在图9所示实施例中，级联输出控制子电路可以包括第一晶体管T1、第六晶体管T6以及反由晶体管N2和N3形成的反相器，其实现了与结合图4所示的级联输出控制子电路431相类似的功能。此外，图9所示的随机移位电路930的输出子电路与图4所示的随机移位电路430的输出子电路435的构成相同，这里不再赘述。
与图4所示实施例不同之处至少在于，图9所示的随机移位电路930的帧移位子电路包括第四晶体管T4和第五晶体管T5。与图4中第四晶体管T4的控制端由第二晶体管T2和第三晶体管T3联合控制不同的是，图9中第四晶体管T4的控制端由感测电路910的输出端P1来控制。然而结合图6所示的时序图可以看出来，二者各自与第五晶体管T5的结合之后能够实现相同或类似的功能，这里不再赘述。
从而，图9所示的移位寄存器900与图4所示的移位寄存器400都可以提供“随机帧移位”功能。
图10是示出了根据本公开再一实施例的示例移位寄存器1000的电路原理图。如图10所示，移位寄存器1000可以包括感测电路1010、扫描电路1020和随机移位电路1030。随机移位电路1030包括例如第四晶体管T4、第五晶体管T5、第七晶体管T7和第八晶 体管T8。此外，除非另行明确说明，否则在图10所示的移位寄存器1000中，具有与图9相同附图标记的晶体管和电容通常可具有与图9所示的晶体管和电容相同或相似的功能和/或连接关系，这里不再赘述。
与图9所示移位寄存器900相比，图10所示的移位寄存器1000将用于控制感测电路1010和扫描电路1020的级联输出(即第一控制输出端CR1<n>和第二控制输出端CR2<n>)的两个晶体管，即第一晶体管T1和第六晶体管T6分别移动到感测电路1010和扫描电路1020中用来接收输入信号。换言之，将对级联输出(即第一控制输出端CR1<n>和第二控制输出端CR2<n>)的控制从移位寄存器的控制输出端转移到了输入端，即转移到上一级移位寄存器的输出控制输入端处。从而，在例如图6所示的工作时序的情况下，再考虑到图7和图8中采用信号切换端SW的原理，可以看出图10所示的移位寄存器1000能够实现与图9所示移位寄存器900相同或类似的功能。
此外，图10中的感测电路1010和扫描电路1020中的下拉控制子电路分别被实现为反相器。在图6所示的时序图的情况下，它们实际上可以实现与图9的感测电路910和扫描电路920中的下拉节点控制子电路相同或类似的功能，这里不再赘述其具体结构。
此外，在一些实施例中，输出使能端OE的周期可以为帧频，即其一个周期的时间长度可以与一帧的时间长度相同。此外，帧移位时钟信号端CLKs也可以采用该周期，其输出信号可同时作为上拉节点Q2的充电信号，也可作为上拉节点Q2的放电信号。
此外，本公开的一些实施例提供了一种栅极驱动电路(例如，栅极驱动电路500等)，包括多个级联的上述移位寄存器(例如，移位寄存器300、400、700、800、900和1000等)。
此外，本公开的一些实施例提供了一种显示装置。该显示装置可包括前述栅极驱动电路(例如，栅极驱动电路500等)。
通过采用根据本公开实施例的移位寄存器及其驱动方法、栅极驱动电路和显示装置，可在采用外部补偿方案时产生所需的复合脉冲，实现对像素电路的正确驱动，从而使得OLED显示装置发光更为均匀、用户体验更好。
至此已经结合优选实施例对本公开进行了描述。应该理解，本领域技术人员在不脱离本公开的精神和范围的情况下，可以进行各种其它的改变、替换和添加。因此，本公开的范围不局限于上述特定实施例，而应由所附权利要求所限定。
此外，在本文中被描述为通过纯硬件、纯软件和/或固件来实现的功能，也可以通过专用硬件、通用硬件与软件的结合等方式来实现。例如，被描述为通过专用硬件(例 如，现场可编程门阵列(FPGA)、专用集成电路(ASIC)等)来实现的功能，可以由通用硬件(例如，中央处理单元(CPU)、数字信号处理器(DSP))与软件的结合的方式来实现，反之亦然。

Claims (19)

  1. 一种移位寄存器，包括：
    扫描电路，被配置为生成用于在扫描时段使所述移位寄存器输出栅极驱动信号中的具有行移位部分的第一信号；
    感测电路，被配置为生成用于在消隐时段使所述栅极驱动信号中的具有帧移位部分的第二信号；以及
    随机移位电路，与所述扫描电路和所述感测电路分别电连接，并被配置为基于所述第一信号和所述第二信号来生成具有所述行移位部分并且随机地具有所述帧移位部分的栅极驱动信号。
  2. 根据权利要求1所述的移位寄存器，其中，
    所述第一信号包括所述扫描电路的上拉节点处的信号、所述扫描电路的下拉节点处的信号或所述扫描电路的输出端处的信号中的至少一个；并且
    所述第二信号包括所述感测电路的上拉节点处的信号、所述感测电路的下拉节点处的信号或所述感测电路的输出端处的信号中的至少一个。
  3. 根据权利要求2所述的移位寄存器，其中，
    所述感测电路与随机时钟信号端相连，并且被配置为响应于在扫描时段所述随机时钟信号端的信号波形发生随机变化，使所述感测电路的上拉节点处的信号在所述扫描时段和所述消隐时段均保持有效；并且
    所述随机移位电路与所述感测电路的上拉节点、所述扫描电路的上拉节点和帧移位时钟信号端相连，并且被配置为在消隐时段在所述感测电路的上拉节点处的信号的控制下使所述扫描电路的上拉节点处存储帧移位时钟信号端的电压，并基于所存储的电压产生具有所述帧移位部分的栅极驱动信号。
  4. 根据权利要求2所述的移位寄存器，其中，所述随机移位电路包括：
    级联输出控制子电路，与输出使能端、第一控制输出端、第二控制输出端、所述感测电路的输出端和所述扫描电路的输出端连接，并被配置为在所述输出使能端的控制下，向第一控制输出端提供来自所述感测电路的输出端的信号并且向所述第二控制输出端提供来自所述扫描电路的输出端的信号；
    帧移位子电路，与所述输出使能端、所述感测电路的上拉节点和下拉节点、帧移位时钟信号端、随机时钟信号端、第一参考信号端和所述扫描电路的上拉节点连接，并被配置为在所述输出使能端、所述感测电路的上拉节点、所述感测电路的下拉节点、 所述随机时钟信号端、所述第一参考信号端的控制下，将来自所述帧移位时钟信号端的帧移位时钟信号传递至所述扫描电路的上拉节点；以及
    输出子电路，与所述输出时钟信号端、所述扫描电路的上拉节点和下拉节点、第二参考信号端和所述移位寄存器的输出端连接，并被配置为在所述扫描电路的上拉节点和所述扫描电路的下拉节点的控制下，将来自所述输出时钟信号端的输出时钟信号和来自所述第二参考信号端的第二参考信号之一选择性地传递至所述移位寄存器的输出端，作为所述移位寄存器输出的栅极驱动信号。
  5. 根据权利要求3或4所述的移位寄存器，其中，所述随机时钟信号端被配置为在随机信号控制下随机地保持持续电位。
  6. 根据权利要求2所述的移位寄存器，其中，所述随机移位电路包括：
    级联输出控制子电路，与信号切换端、第一控制输出端、第二控制输出端、所述感测电路的输出端和所述扫描电路的输出端连接，并被配置为在所述信号切换端的控制下，向所述第一控制输出端提供来自所述感测电路的输出端的信号并且向所述第二控制输出端提供来自所述扫描电路的输出端的信号；
    帧移位子电路，与输出使能端、所述感测电路的上拉节点和下拉节点、帧移位时钟信号端、随机时钟信号端、第一参考信号端和所述扫描电路的上拉节点连接，并被配置为在所述输出使能端、所述感测电路的上拉节点、所述感测电路的下拉节点、所述随机时钟信号端和所述第一参考信号端的控制下，将来自所述帧移位时钟信号端的帧移位时钟信号传递至所述扫描电路的上拉节点；以及
    输出子电路，与所述输出时钟信号端、所述扫描电路的上拉节点和下拉节点、第二参考信号端和所述移位寄存器的输出端连接，并被配置为在所述扫描电路的上拉节点和所述扫描电路的下拉节点的控制下，将来自所述输出时钟信号端的输出时钟信号和来自所述第二参考信号端的第二参考信号之一选择性地传递至所述移位寄存器的输出端，作为所述移位寄存器输出的栅极驱动信号。
  7. 根据权利要求6所述的移位寄存器，其中，所述级联输出控制子电路包括第一晶体管和第六晶体管，
    所述第一晶体管的控制端与信号切换端连接，第一端与所述感测电路的输出端连接，以及第二端与所述第一控制输出端连接；以及
    所述第六晶体管的控制端与所述信号切换端连接，第一端与所述扫描电路的输出端连接，以及第二端与所述第二控制输出端连接。
  8. 根据权利要求4或6所述的移位寄存器，其中，所述帧移位子电路包括第二晶体管、第三晶体管、第四晶体管和第五晶体管，
    所述第二晶体管的控制端与所述感测电路的上拉节点连接，第一端与所述随机时钟信号端连接，以及第二端与所述第四晶体管的控制端连接；
    所述第三晶体管的控制端与所述感测电路的下拉节点连接，第一端与所述第一参考信号端连接，以及第二端与所述第四晶体管的控制端连接；
    所述第四晶体管的第一端与所述帧移位时钟信号端连接，以及第二端与所述第五晶体管的第一端连接；以及
    所述第五晶体管的控制端与所述输出使能端连接，以及第二端与所述扫描电路的上拉节点连接。
  9. 根据权利要求2所述的移位寄存器，其中，所述随机移位电路包括：
    级联输出控制子电路，与输出使能端、第一控制输出端、第二控制输出端、所述感测电路的输出端和所述扫描电路的输出端连接，并被配置为在所述输出使能端的控制下，向第一控制输出端提供来自所述感测电路的输出端的信号并且向所述第二控制输出端提供来自所述扫描电路的输出端的信号；
    帧移位子电路，与输出使能端、所述感测电路的输出端、帧移位时钟信号端和所述扫描电路的上拉节点连接，并被配置为在所述输出使能端和所述感测电路的输出端的控制下，将来自所述帧移位时钟信号端的帧移位时钟信号传递至所述扫描电路的上拉节点；以及
    输出子电路，与所述输出时钟信号端、所述扫描电路的上拉节点和下拉节点、第二参考信号端和所述移位寄存器的输出端连接，并被配置为在所述扫描电路的所述上拉节点和所述下拉节点的控制下，将来自所述输出时钟信号端的输出时钟信号和来自所述第二参考信号端的第二参考信号之一选择性地传递至所述移位寄存器的输出端，作为所述移位寄存器输出的栅极驱动信号。
  10. 根据权利要求2所述的移位寄存器，其中，所述扫描电路和所述感测电路还被配置为在信号切换端的控制下选择性接收输入信号，所述感测电路的输出端作为第一控制输出端，以及所述扫描电路的输出端作为第二控制输出端。
  11. 根据权利要求10所述的移位寄存器，其中，所述随机移位电路包括：
    帧移位子电路，与输出使能端、所述感测电路的输出端、帧移位时钟信号端、和所述扫描电路的上拉节点连接，并被配置为在所述输出使能端和所述感测电路的输出 端的控制下，将来自所述帧移位时钟信号端的帧移位时钟信号传递至所述扫描电路的上拉节点；以及
    输出子电路，与所述输出时钟信号端、所述扫描电路的上拉节点和下拉节点、第二参考信号端和所述移位寄存器的输出端连接，并被配置为在所述上拉节点和所述下拉节点的控制下，将来自所述输出时钟信号端的输出时钟信号和来自所述第二参考信号端的第二参考信号之一选择性地传递至所述移位寄存器的输出端，作为所述移位寄存器的输出信号。
  12. 根据权利要求9或11所述的移位寄存器，其中，所述帧移位子电路包括第四晶体管和第五晶体管，
    所述第四晶体管的控制端与所述感测电路的输出端连接，第一端与所述帧移位时钟信号端连接，以及第二端与所述第五晶体管的第一端连接；以及
    所述第五晶体管的控制端与所述输出使能端连接，以及第二端与所述扫描电路的上拉节点连接。
  13. 根据权利要求4或9所述的移位寄存器，其中，所述级联输出控制子电路包括反相器、第一晶体管和第六晶体管，
    所述反相器的第一端与所述输出使能端连接，以及第二端与所述第一晶体管的控制端和所述第六晶体管的控制端连接；
    所述第一晶体管的第一端与所述感测电路的输出端连接，以及第二端与所述第一控制输出端连接；以及
    所述第六晶体管的第一端与所述扫描电路的输出端连接，以及第二端与所述第二控制输出端连接。
  14. 根据权利要求4、6、9或11所述的移位寄存器，其中，所述输出子电路包括第七晶体管和第八晶体管，
    所述第七晶体管的控制端与所述扫描电路的上拉节点连接，第一端与输出时钟信号端连接，以及第二端与所述移位寄存器的输出端连接；以及
    所述第八晶体管的控制端与所述扫描电路的下拉节点连接，第一端与第二参考信号端连接，以及第二端与所述移位寄存器的输出端连接。
  15. 一种栅极驱动电路，包括多个级联的根据权利要求1～14中任一项所述的移位寄存器。
  16. 一种显示装置，包括根据权利要求15所述的栅极驱动电路。
  17. 一种用于驱动根据权利要求1～14中任一项所述的移位寄存器的方法，包括：
    由扫描电路在来自输出时钟信号端的输出时钟信号的控制下生成用于在扫描时段使栅极驱动信号中具有行移位部分的第一信号；
    由感测电路在来自随机时钟信号端的随机时钟信号的控制下生成用于在消隐时段使所述栅极驱动信号中具有帧移位部分的第二信号；以及
    由随机移位电路在来自帧移位时钟信号端的帧移位时钟信号、来自输出时钟信号端的输出时钟信号和来自输出使能端的输出使能信号的控制下，基于所述第一信号和所述第二信号来生成具有随机帧移位的栅极驱动信号。
  18. 根据权利要求17所述的方法，其中，所述移位寄存器还包括与所述随机移位电路或与所述扫描电路和所述感测电路相连的信号切换端，当所述信号切换端处的信号与所述输出使能端处的信号互为反相时，所述随机移位电路根据所述第一信号和所述第二信号来生成随机具有帧移位部分的栅极驱动信号。
  19. 根据权利要求17所述的移位寄存器，其中，所述移位寄存器还包括与所述随机移位电路或与所述扫描电路和所述感测电路相连的信号切换端，当所述信号切换端处的信号为恒定高电平信号时，所述随机移位电路根据所述第一信号和所述第二信号来生成顺序地具有帧移位部分的栅极驱动信号。
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