WO2020098569A1 - 控制电路、液晶显示驱动模组及液晶显示装置 - Google Patents

控制电路、液晶显示驱动模组及液晶显示装置 Download PDF

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Publication number
WO2020098569A1
WO2020098569A1 PCT/CN2019/116588 CN2019116588W WO2020098569A1 WO 2020098569 A1 WO2020098569 A1 WO 2020098569A1 CN 2019116588 W CN2019116588 W CN 2019116588W WO 2020098569 A1 WO2020098569 A1 WO 2020098569A1
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Prior art keywords
input terminal
field effect
effect transistor
type field
capacitor
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PCT/CN2019/116588
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English (en)
French (fr)
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WO2020098569A8 (zh
Inventor
文亮
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Vivo Mobile Communication Co Ltd
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Vivo Mobile Communication Co Ltd
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Priority to KR1020217017563A priority Critical patent/KR102552625B1/ko
Priority to JP2021525802A priority patent/JP7315671B2/ja
Priority to EP19883779.1A priority patent/EP3882903B1/en
Priority to ES19883779T priority patent/ES3058058T3/es
Publication of WO2020098569A1 publication Critical patent/WO2020098569A1/zh
Priority to US17/319,404 priority patent/US11462190B2/en
Anticipated expiration legal-status Critical
Publication of WO2020098569A8 publication Critical patent/WO2020098569A8/zh
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/296—Time-programme switches providing a choice of time-intervals for executing more than one switching action and automatically terminating their operation after the programme is completed
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/025—Reduction of instantaneous peaks of current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/026—Arrangements or methods related to booting a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/028—Generation of voltages supplied to electrode drivers in a matrix display other than LCD
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • the present disclosure relates to the field of communication technology, and in particular, to a control circuit, a liquid crystal display driving module, and a liquid crystal display device.
  • the external power supply of the driver chip of the LCD driver module mainly includes the VDDI signal, AVDD signal and AVEE signal. Normally, the VDDI signal is powered on before the AVDD signal and the AVEE signal, and the VDDI signal is powered off after the AVDD signal and the AVEE signal. , The three work together to make the LCD driver module work normally.
  • the AVDD signal and the AVEE signal may be powered on before the VDDI signal, or the AVDD signal and the AVEE signal may be powered off after the VDDI signal, and the probability of damage to the driver chip is relatively high.
  • Some embodiments of the present disclosure provide a control circuit, a liquid crystal display driving module, and a liquid crystal display device to solve the problem of a relatively high probability of damage to the driving chip under abnormal conditions.
  • some embodiments of the present disclosure provide a control circuit for controlling the on and off timing of a plurality of power signals input to a driving chip of a display module, the control circuit includes receiving different external power signals respectively The first input terminal and the second input terminal, the control circuit sequentially controls the first input terminal and the second input terminal to input a power signal to the driving chip, and sequentially controls the second input terminal and the second input terminal The first input terminal is powered down.
  • some embodiments of the present disclosure also provide a liquid crystal display drive module, including a drive chip, and the liquid crystal display drive module further includes the above control circuit.
  • some embodiments of the present disclosure also provide a liquid crystal display device, including the above-mentioned liquid crystal display driving module.
  • a control circuit of some embodiments of the present disclosure is used to control the on-off timing of a plurality of power signals input to a driving chip of a display module, the control circuit includes first input terminals respectively receiving different external power signals And a second input terminal, the control circuit sequentially controls the first input terminal and the second input terminal to input a power signal to the driving chip, and sequentially controls the second input terminal and the first input terminal Power down.
  • the control circuit includes first input terminals respectively receiving different external power signals And a second input terminal, the control circuit sequentially controls the first input terminal and the second input terminal to input a power signal to the driving chip, and sequentially controls the second input terminal and the first input terminal Power down.
  • FIG. 2 is a second structural schematic diagram of a control circuit provided by some embodiments of the present disclosure.
  • FIG. 3 is a third structural schematic diagram of a control circuit provided by some embodiments of the present disclosure.
  • FIG. 4 is a fourth structural diagram of a control circuit provided by some embodiments of the present disclosure.
  • FIG. 5 is a fifth schematic structural diagram of a control circuit provided by some embodiments of the present disclosure.
  • FIG. 6 is a sixth structural diagram of a control circuit provided by some embodiments of the present disclosure.
  • FIG. 1 is a schematic structural diagram of a control circuit provided by some embodiments of the present disclosure.
  • the control circuit is used to control the on and off timing of multiple external power signals input to the driving chip of the display module, as shown in FIG.
  • the control circuit includes a first input terminal 101 and a second input terminal 102 respectively receiving different external power signals, and the control circuit sequentially controls the input of the first input terminal 101 and the second input terminal 102 A power signal is sent to the driving chip, and the second input terminal 102 and the first input terminal 101 are controlled to be powered off in sequence.
  • the first input terminal 101 may be a VDDI input terminal
  • the second input terminal 102 may be an AVDD input terminal or an AVEE input terminal. This ensures that the VDDI signal is input to the driver chip before the AVDD signal or AVEE signal, and the AVDD signal or AVEE signal is powered down before the VDDI signal.
  • the above control circuit includes a capacitor, and the second input terminal and the first input terminal are sequentially controlled to be powered down by the capacitor.
  • the second input terminal includes a second sub-input terminal and a third sub-input terminal, the second sub-input terminal and the third sub-input terminal respectively receive different external power signals, and the control circuit Sequentially controlling the first input end, the second sub-input end, and the third sub-input end to input a power signal to the driving chip, and sequentially controlling the third sub-input end, the second sub-input The input terminal and the first input terminal are powered off.
  • the second input terminal includes a second sub-input terminal and a third sub-input terminal, the second sub-input terminal and the third sub-input terminal respectively receive different external power signals, and the control circuit Sequentially controlling the first input end, the second sub-input end, and the third sub-input end to input a power signal to the driving chip, and sequentially controlling the third sub-input end, the second sub-input The input terminal and the first input terminal are powered off. In this way, the normal timing of multiple different power signals can be ensured, thereby reducing the probability of damage to the driver chip.
  • the first input terminal is a VDDI input terminal
  • the second sub-input terminal is an AVEE input terminal
  • the third sub-input terminal is an AVDD input terminal
  • the first input terminal is a VDDI input terminal
  • the second sub-input terminal is an AVDD input terminal
  • the third sub-input terminal is an AVEE input terminal.
  • the first input terminal is a VDDI input terminal
  • the second sub-input terminal is an AVEE input terminal
  • the third sub-input terminal is an AVDD input terminal
  • the first input terminal is a VDDI input terminal
  • the second sub-input terminal is an AVDD input terminal
  • the third sub-input terminal is an AVEE input terminal
  • the first input terminal is a VDDI input terminal
  • the second sub-input terminal is an AVEE input terminal
  • the third sub-input terminal is an AVDD input terminal
  • the control circuit includes:
  • a first resistor R1, a first end of the first resistor R1 is connected to the VDDI input terminal;
  • N-type field effect transistor M1 the gate of the N-type field effect transistor M1 is connected to the second terminal of the first resistor R1, and the first pole of the N-type field effect transistor M1 is connected to the AVEE input terminal , The second pole of the N-type field effect transistor M1 is connected to the driving chip;
  • a first capacitor C1 the first end of the first capacitor C1 is connected to the second end of the first resistor R1, the second end of the first capacitor C1 is grounded, or the second end of the first capacitor C1 The terminal is connected to the second electrode of the N-type field effect transistor M1;
  • a second resistor R2, the first end of the second resistor R2 is connected to the second electrode of the N-type field effect transistor M1;
  • the gate of the P-type field effect transistor M2 is connected to the second terminal of the second resistor R2, and the first pole of the P-type field effect transistor M2 is connected to the AVDD input terminal , The second pole of the P-type field effect transistor M2 is connected to the driving chip;
  • a second capacitor C2 the first end of the second capacitor C2 is connected to the second end of the second resistor R2, the second end of the second capacitor C2 is grounded, or the second end of the second capacitor C2 The terminal is connected to the second electrode of the P-type field effect transistor M2.
  • the portion where the second electrode of the N-type field effect transistor M1 is connected to the driving chip is different from the portion where the second electrode of the P-type field effect transistor M2 is connected to the driving chip.
  • the first electrode and the second electrode of the field effect transistor may be a source electrode and a drain electrode, or a drain electrode and a source electrode, respectively.
  • the second terminal of the first capacitor C1 is grounded, and the second terminal of the second capacitor C2 is grounded.
  • the VDDI signal serves as the gate control signal for the N-type field effect transistor M1.
  • the VDDI voltage reaches, for example, 1.8V
  • the VDDI signal first charges the first capacitor C1 through the first resistor R1, and the first capacitor C1 charges for a certain time to reach the N-type field
  • the AVEE signal starts to be input through the N-type field effect transistor M1.
  • the input AVEE signal is divided into multiple paths, all the way into the booster circuit of the driving chip.
  • the other input AVEE signal charges the second capacitor C2 through the second resistor R2.
  • the AVDD signal is input through the P-type field effect transistor M2. Therefore, even if the external power supply is abnormal, the AVDD signal or AVEE signal is supplied before the VDDI signal, and it cannot be input into the driver chip in advance.
  • the VDDI signal voltage is 1.8V
  • the first resistor R1 is 10K ohms
  • the first capacitor C1 is 4.7 ⁇ F.
  • the AVEE signal voltage is -5.5V
  • the second resistor R2 is 1K ohm
  • the second capacitor C2 is 1 ⁇ F.
  • the AVDD signal is powered first, the AVEE signal is second, and the last abnormal power-up of the VDDI signal occurs, because neither the N-type field effect transistor M1 nor the P-type field effect transistor M2 is turned on until the VDDI signal is powered on, the first capacitor C1 After the potential rises, the N-type field effect transistor M1 is turned on after a few milliseconds, the AVEE signal is powered on, then the second capacitor C2 is charged, and the AVDD signal is powered on. In this way, it is ensured that the VDDI signal is input first in the three-way power supply, so that the driver chip works normally. After the VDDI signal is input for a period of time, input the AVEE signal. After the AVEE signal is input for a period of time, then the AVDD signal is input, so that the boost circuit of the driving chip works under the drive of the AVEE signal and the AVDD signal.
  • the first capacitor C1 and the second capacitor C2 are fully charged when the host is powered on.
  • the power supply of VDDI, AVDD and AVEE is disconnected, the AVDD signal will be powered down due to the existence of other capacitors and parasitic capacitors. After the capacitor is discharged for a period of time without input. Since the first capacitor C1 and the second capacitor C2 store more power, they will continue to input for a period of time.
  • the expected state that the AVDD signal is powered down first, the AVEE signal is second, and the VDDI signal is finally powered down occurs.
  • the host power is turned off, under the control of the circuit, first turn off the AVDD signal, then turn off the AVEE signal, and finally turn off the VDDI signal.
  • circuit structure shown in Fig. 2 no matter how abnormal the external voltage power supply and abnormal power failure, by setting the circuit can be in accordance with the order of power supply required power supply order or power down in the desired order.
  • the second terminal of the first capacitor C1 is connected to the second terminal of the N-type field effect transistor M1, and the second terminal of the second capacitor C2 is connected to the P-type field effect
  • the second electrode of the transistor M2 is connected.
  • the VDDI signal charges the first capacitor C1 to turn on the N-type field effect transistor M1
  • the AVEE signal (generally -5.5V) is input to the node N1, so that the voltage difference between the node N3 and the node N1 increases, accelerating the charging of the first capacitor C1 speed.
  • the voltage difference between the gate and the source and the gate and the drain of the N-type field effect transistor M1 increases, so that the speed of the AVEE signal current passing through the N-type field effect transistor M1 is accelerated, that is, the AVEE signal reaches the preset value from 0V -The speed of 5.5V is accelerated.
  • the rapid increase in the voltage difference between node N4 and node N2 increases the speed of powering up the AVDD signal.
  • the rapid power-up of the AVDD signal and the AVEE signal to a predetermined voltage can reduce the probability that the logic of the booster circuit of the driver chip is chaotic and cause latch-up high current to burn the driver chip, optimizing the power-on process of the booster circuit.
  • the first input terminal is a VDDI input terminal
  • the second sub-input terminal is an AVDD input terminal
  • the third sub-input terminal is an AVEE input terminal
  • the control circuit includes:
  • a third resistor R3, a first end of the third resistor R3 is connected to the VDDI input terminal;
  • a third capacitor C3, the first end of the third capacitor C3 is connected to the second end of the third resistor R3, the second end of the third capacitor C3 is grounded, or the second end of the third capacitor C3 The terminal is connected to the second electrode of the first N-type field effect transistor M3;
  • a fourth resistor R4, a first end of the fourth resistor R4 is connected to the second electrode of the first N-type field effect transistor M3;
  • a second N-type field effect transistor M4 the gate of the second N-type field effect transistor M4 is connected to the second end of the fourth resistor R4, and the first pole of the second N-type field effect transistor M4 is connected to The AVEE input terminal is connected, and the second electrode of the second N-type field effect transistor M4 is connected to the driving chip;
  • a fourth capacitor C4 the first end of the fourth capacitor C4 is connected to the second end of the fourth resistor R4, the second end of the fourth capacitor C4 is grounded, or the second end of the fourth capacitor C4 The terminal is connected to the second electrode of the second N-type field effect transistor M4.
  • the portion where the second electrode of the first N-type field effect transistor M3 is connected to the driving chip is different from the portion where the second electrode of the second N-type field effect transistor M4 is connected to the driving chip .
  • the first electrode and the second electrode of the field effect transistor may be a source electrode and a drain electrode, or a drain electrode and a source electrode, respectively.
  • FIG. 4 is a schematic structural diagram of a control circuit provided by some embodiments of the present disclosure.
  • the second end of the third capacitor C3 is grounded, and the second end of the fourth capacitor C4 is grounded.
  • the third capacitor C3 is charged.
  • the third capacitor C3 reaches about 0.3V, it can start to reach the threshold voltage for turning on the first N-type field effect transistor M3.
  • the third capacitor C3 continues to boost and then turns on the first
  • the N-type field effect transistor M3 the AVDD signal is input through the first N-type field effect transistor M3, all the way into the boost circuit of the driver chip, and the other way charges the fourth capacitor C4 through the fourth resistor R4, with the voltage of the fourth capacitor C4 Ascending turns on the second N-type field effect transistor M4, and the AVEE signal can be input into the driving chip. In this way, it is ensured that the VDDI signal is powered first, then the AVDD signal, and finally the power-on sequence of the AVEE signal.
  • control circuit includes:
  • a third N-type field effect transistor M5 the VDDI input terminal is connected to the gate of the third N-type field effect transistor M5 through the selection circuit, and the first electrode of the third N-type field effect transistor M5 is The AVDD input terminal is connected, and the second electrode of the third N-type field effect transistor M5 is connected to the driving chip;
  • a fourth N-type field effect transistor M6 the VDDI input terminal is connected to the gate of the fourth N-type field effect transistor M6 through the selection circuit, the first pole of the fourth N-type field effect transistor M6 is connected to The AVEE input terminal is connected, and the second electrode of the fourth N-type field effect transistor M6 is connected to the driving chip;
  • the selection circuit is used for sequentially selecting a first target field effect transistor and a second target field effect transistor from the third N-type field effect transistor M5 and the fourth N-type field effect transistor M6, and sequentially delaying the conduction Through the source and drain of the first target field effect transistor and the second target field effect transistor.
  • the portion where the second electrode of the third N-type field effect transistor M5 is connected to the driving chip is different from the portion where the second electrode of the fourth N-type field effect transistor M6 is connected to the driving chip .
  • the first electrode and the second electrode of the field effect transistor may be a source electrode and a drain electrode, or a drain electrode and a source electrode, respectively.
  • the selection circuit may include different capacitors for controlling the power-up and power-down timing of the AVDD signal and the AVEE signal.
  • the second sub-input is the AVEE input
  • the third sub-input is the AVDD input
  • the second sub-input The terminal is the AVDD input terminal AVEE input terminal
  • the third sub-input terminal is the AVEE input terminal.
  • the specific way may set the selection circuit according to actual requirements, and this embodiment is not limited thereto.
  • FIG. 5 is a schematic structural diagram of a control circuit provided by some embodiments of the present disclosure.
  • the selection circuit works and outputs the drive signal.
  • the third N-type field effect transistor M5 and the fourth N-type field effect transistor M6 are turned on successively.
  • AVEE signal input. It can be programmed in advance to be solidified inside the driver chip, or when the VDDI signal is powered up and the driver chip is working, program the driver chip internally, determine the power-up sequence of the AVDD signal and the AVEE signal, and select the circuit to output the corresponding sequence control signal. In this way, you can flexibly control the input of the AVDD signal and the AVEE signal through programming.
  • a thermistor is connected in series on the path between the AVEE input terminal and the driving chip;
  • a thermistor is connected in series on the path between the AVDD input terminal and the driving chip.
  • the boost circuit of the driving chip when the boost circuit of the driving chip generates a latching large current, the increase in current causes the thermistor to generate heat and the resistance increases, and the increase in resistance reduces the current flow.
  • the size of the driver chip can be protected.
  • FIG. 6 is a schematic structural diagram of a control circuit provided by some embodiments of the present disclosure.
  • the thermistor R5 is connected in series with the path of the AVEE input terminal and the driving chip; and thermistor R6 is connected in series with the path of the AVDD input terminal and the driving chip.
  • the AVEE signal and the AVDD signal draw a large current, especially when the boost circuit of the drive chip latches a large current, the increase in current causes the thermistor to heat up and the resistance increases, and the resistance increase decreases The magnitude of the current flowing through the thermistor, thereby protecting the driver chip.
  • the circuit in this embodiment can also be implemented by using a thyristor to control the current of the power supply.
  • the resistors, thermistors, and capacitors in the circuit can be provided on an external circuit board or integrated into the driver chip.
  • Various optional embodiments introduced in some embodiments of the present disclosure may be implemented in combination with each other, or may be implemented separately, which is not limited in some embodiments of the present disclosure.
  • a control circuit of some embodiments of the present disclosure is used to control the on and off timing of a plurality of power signals input to a driving chip of a display module.
  • the control circuit includes a circuit that receives different external power signals, respectively.
  • a first input terminal 101 and a second input terminal 102 the control circuit sequentially controls the first input terminal 101 and the second input terminal 102 to input a power signal to the driving chip, and sequentially controls the second input Terminal 102, the first input terminal 101 is powered off.
  • the timing of different power signals the normal timing of different power signals is guaranteed as much as possible, thereby reducing the probability of damage to the driver chip.
  • Some embodiments of the present disclosure also provide a liquid crystal display driving module, including a driving chip, and the liquid crystal display driving module further includes the above control circuit.
  • Some embodiments of the present disclosure also provide a liquid crystal display device including the above-mentioned liquid crystal display driving module.
  • the liquid crystal display device may be a mobile phone, a tablet computer (Tablet Personal Computer), a laptop computer (Laptop Computer), a personal digital assistant (PDA), a mobile Internet device (Mobile Internet) Device, MID) or Wearable Device (Wearable Device), etc.

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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Engineering & Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
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Abstract

一种控制电路、液晶显示驱动模组及液晶显示装置，控制电路包括分别接收不同的外部电源信号的第一输入端（101）和第二输入端（102），控制电路依次控制第一输入端（101）、第二输入端（102）输入电源信号至驱动芯片，且依次控制第二输入端（102）、第一输入端（101）掉电。

Description

控制电路、液晶显示驱动模组及液晶显示装置
相关申请的交叉引用
本申请主张在2018年11月14日在中国提交的中国专利申请号No.201811353013.1的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及通信技术领域，尤其涉及一种控制电路、液晶显示驱动模组及液晶显示装置。
背景技术
随着液晶显示技术的迅速发展，液晶显示装置在人们生活中已经很常见，并且为用户带来了新的视觉体验。液晶显示驱动模组的驱动芯片的外部电源供电主要包括VDDI信号、AVDD信号和AVEE信号，正常情况下是VDDI信号在AVDD信号和AVEE信号之前上电，VDDI信号在AVDD信号和AVEE信号之后下电，三者共同作用以使液晶显示驱动模组正常工作。
但是，在异常情况下，AVDD信号、AVEE信号可能在VDDI信号之前上电，或者AVDD信号、AVEE信号可能在VDDI信号之后下电，对驱动芯片造成损坏的概率比较大。
发明内容
本公开的一些实施例提供一种控制电路、液晶显示驱动模组及液晶显示装置，以解决在异常情况下，对驱动芯片造成损坏的概率比较大的问题。
为了解决上述技术问题，本公开是这样实现的：
第一方面，本公开的一些实施例提供了一种控制电路，用于控制输入至显示模组的驱动芯片的多个电源信号的通断时序，所述控制电路包括分别接收不同的外部电源信号的第一输入端和第二输入端，所述控制电路依次控制所述第一输入端、所述第二输入端输入电源信号至所述驱动芯片，且依次控制所述第二输入端、所述第一输入端掉电。
第二方面，本公开的一些实施例还提供一种液晶显示驱动模组，包括驱动芯片，所述液晶显示驱动模组还包括上述控制电路。
第三方面，本公开的一些实施例还提供一种液晶显示装置，包括上述液晶显示驱动模组。
本公开的一些实施例的一种控制电路，用于控制输入至显示模组的驱动芯片的多个电源信号的通断时序，所述控制电路包括分别接收不同的外部电源信号的第一输入端和第二输入端，所述控制电路依次控制所述第一输入端、所述第二输入端输入电源信号至所述驱动芯片，且依次控制所述第二输入端、所述第一输入端掉电。这样，通过控制不同电源信号的时序，尽可能的保证了不同电源信号正常的时序，从而减小了驱动芯片损坏的概率。
附图说明
为了更清楚地说明本公开的一些实施例的技术方案，下面将对本公开的一些实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本公开的一些实施例提供的控制电路的结构示意图之一；
图2是本公开的一些实施例提供的控制电路的结构示意图之二；
图3是本公开的一些实施例提供的控制电路的结构示意图之三；
图4是本公开的一些实施例提供的控制电路的结构示意图之四；
图5是本公开的一些实施例提供的控制电路的结构示意图之五；
图6是本公开的一些实施例提供的控制电路的结构示意图之六。
具体实施方式
下面将结合本公开的一些实施例中的附图，对本公开的一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
参见图1，图1是本公开的一些实施例提供的控制电路的结构示意图，所述控制电路用于控制输入至显示模组的驱动芯片的多个外部电源信号的通断时序，如图1所示，所述控制电路包括分别接收不同的外部电源信号的第一输入端101和第二输入端102，所述控制电路依次控制所述第一输入端101、所述第二输入端102输入电源信号至所述驱动芯片，且依次控制所述第二输入端102、所述第一输入端101掉电。
本实施例中，上述第一输入端101可以为VDDI输入端，上述第二输入端102可以为AVDD输入端或者AVEE输入端。这样可以保证VDDI信号在AVDD信号或者AVEE信号之前输入至驱动芯片，以及AVDD信号或者AVEE信号在VDDI信号之前掉电。上述控制电路包括电容，通过电容依次控制所述第二输入端、所述第一输入端掉电。
这样，通过控制不同电源信号的时序，尽可能的保证了不同电源信号正常的时序，从而减小了驱动芯片损坏的概率。
可选的，所述第二输入端包括第二子输入端和第三子输入端，所述第二子输入端、所述第三子输入端分别接收不同的外部电源信号，所述控制电路依次控制所述第一输入端、所述第二子输入端、以及所述第三子输入端输入电源信号至所述驱动芯片，且依次控制所述第三子输入端、所述第二子输入端、以及所述第一输入端掉电。
该实施方式中，上述第二输入端包括第二子输入端和第三子输入端，所述第二子输入端、所述第三子输入端分别接收不同的外部电源信号，所述控制电路依次控制所述第一输入端、所述第二子输入端、以及所述第三子输入端输入电源信号至所述驱动芯片，且依次控制所述第三子输入端、所述第二子输入端、以及所述第一输入端掉电。这样，可以保证多个不同电源信号的正常时序，从而减小了驱动芯片损坏的概率。
可选的，所述第一输入端为VDDI输入端，所述第二子输入端为AVEE输入端，所述第三子输入端为AVDD输入端；
或者，所述第一输入端为VDDI输入端，所述第二子输入端为AVDD输入端，所述第三子输入端为AVEE输入端。
该实施方式中，若所述第一输入端为VDDI输入端，所述第二子输入端 为AVEE输入端，所述第三子输入端为AVDD输入端，那么可以保证VDDI信号、AVEE信号、AVDD信号依次输入至驱动芯片；以及AVDD信号、AVEE信号、VDDI信号在驱动芯片端依次掉电。
该实施方式中，若所述第一输入端为VDDI输入端，所述第二子输入端为AVDD输入端，所述第三子输入端为AVEE输入端，那么可以保证VDDI信号、AVDD信号、AVEE信号依次输入至驱动芯片；以及AVEE信号、AVDD信号、VDDI信号在驱动芯片端依次掉电。
这样，通过控制AVDD信号、AVEE信号和VDDI信号的正常时序，减小了驱动芯片内部闩锁大电流而损坏的概率。
可选的，所述第一输入端为VDDI输入端，所述第二子输入端为AVEE输入端，所述第三子输入端为AVDD输入端，所述控制电路包括：
第一电阻R1，所述第一电阻R1的第一端与所述VDDI输入端连接；
N型场效晶体管M1，所述N型场效晶体管M1的栅极与所述第一电阻R1的第二端连接，所述N型场效晶体管M1的第一极与所述AVEE输入端连接，所述N型场效晶体管M1的第二极与所述驱动芯片连接；
第一电容C1，所述第一电容C1的第一端与所述第一电阻R1的第二端连接，所述第一电容C1的第二端接地，或者所述第一电容C1的第二端与所述N型场效晶体管M1的第二极连接；
第二电阻R2，所述第二电阻R2的第一端与所述N型场效晶体管M1的第二极连接；
P型场效晶体管M2，所述P型场效晶体管M2的栅极与所述第二电阻R2的第二端连接，所述P型场效晶体管M2的第一极与所述AVDD输入端连接，所述P型场效晶体管M2的第二极与所述驱动芯片连接；
第二电容C2，所述第二电容C2的第一端与所述第二电阻R2的第二端连接，所述第二电容C2的第二端接地，或者所述第二电容C2的第二端与所述P型场效晶体管M2的第二极连接。
该实施方式中，上述N型场效晶体管M1的第二极与所述驱动芯片连接的部位，与上述P型场效晶体管M2的第二极与所述驱动芯片连接的部位不同。上述场效晶体管的第一极和第二极可以分别为源极和漏极，或者分别为 漏极和源极。为了更好的理解上述电路，可以参阅图2和图3，图2和图3均为本公开的一些实施例提供的控制电路的结构示意图。
首先可以参阅图2，此时所述第一电容C1的第二端接地，并且所述第二电容C2的第二端接地。VDDI信号作为N型场效晶体管M1的gate控制信号，当VDDI电压到达时，例如1.8V，VDDI信号首先通过第一电阻R1对第一电容C1充电，第一电容C1充电一定时间到达N型场效晶体管M1的开启电压后，AVEE信号通过N型场效晶体管M1开始输入。输入的AVEE信号分成多路，一路进入驱动芯片的升压电路。另一路输入的AVEE信号通过第二电阻R2对第二电容C2进行充电，当第二电容C2充电一段时间达到P型场效晶体管M2的开启电压后，AVDD信号通过P型场效晶体管M2输入。因此，即使外部供电发生异常，AVDD信号或者AVEE信号比VDDI信号先供电，也不能提前输入到驱动芯片内。
例如VDDI信号电压为1.8V，第一电阻R1为10K欧姆，第一电容C1为4.7μF。AVEE信号电压为-5.5V，第二电阻R2为1K欧姆，第二电容C2为1μF。假如AVDD信号先上电，AVEE信号其次，VDDI信号最后的异常上电情况发生，由于N型场效晶体管M1和P型场效晶体管M2均未导通，直到VDDI信号上电，第一电容C1电位上升，几个毫秒时候后打开N型场效晶体管M1，AVEE信号上电，然后第二电容C2充电，AVDD信号上电输入。这样，保证了三路电源中首先输入VDDI信号，使得驱动芯片正常工作起来。VDDI信号输入一段时间后，再输入AVEE信号。AVEE信号输入一段时间后，接着输入AVDD信号，使得驱动芯片的升压电路在AVEE信号和AVDD信号的驱动下工作起来。
当主机关机或者主机电源发生异常掉电等情况时，由于第一电容C1和第二电容C2在开机情况下充满了电。VDDI、AVDD和AVEE电源断开时，AVDD信号会由于其他电容以及寄生电容存在，电容放电一段时间后没有输入而掉电。第一电容C1和第二电容C2由于存储了更多电量，将会多持续输入一段时间。并且，可以设置R1C1大于R2C2，保证VDDI信号持续输入的时间大于AVEE信号持续输入的时间。从而可以做到AVDD信号先掉电，AVEE信号其次，VDDI信号最后掉电的期望状态发生。这样，当主机电源关 闭的时候，在电路的控制下，先关闭AVDD信号，再关闭AVEE信号，最后关闭VDDI信号。
图2所示的电路结构，不管外部电压如何异常供电以及异常掉电，通过设置电路可以按照设定需要的电源供电顺序供电或者按照期望的顺序掉电。
请再参阅图3，此时所述第一电容C1的第二端与所述N型场效晶体管M1的第二极连接，所述第二电容C2的第二端与所述P型场效晶体管M2的第二极连接。当VDDI信号对第一电容C1进行充电打开N型场效晶体管M1时，AVEE信号(一般-5.5V)输入到节点N1，使得节点N3与节点N1压差增大，加速第一电容C1充电的速度。同时N型场效晶体管M1晶体管的栅极与源极以及栅极与漏极压差增大，使得AVEE信号的电流通过N型场效晶体管M1的速度加快，即AVEE信号从0V达到预设值-5.5V的速度加快。同样节点N4与节点N2的压差快速增大提高了AVDD信号上电的速度。AVDD信号和AVEE信号的快速上电达到预定电压，可以降低驱动芯片的升压电路逻辑混乱而产生闩锁大电流烧毁驱动芯片的概率，优化了升压电路的电源上电过程。
可选的，所述第一输入端为VDDI输入端，所述第二子输入端为AVDD输入端，所述第三子输入端为AVEE输入端，所述控制电路包括：
第三电阻R3，所述第三电阻R3的第一端与所述VDDI输入端连接；
第一N型场效晶体管M3，所述第一N型场效晶体管M3的栅极与所述第三电阻R3的第二端连接，所述第一N型场效晶体管M3的第一极与所述AVDD输入端连接，所述第一N型场效晶体管M3的第二极与所述驱动芯片连接；
第三电容C3，所述第三电容C3的第一端与所述第三电阻R3的第二端连接，所述第三电容C3的第二端接地，或者所述第三电容C3的第二端与所述第一N型场效晶体管M3的第二极连接；
第四电阻R4，所述第四电阻R4的第一端与所述第一N型场效晶体管M3的第二极连接；
第二N型场效晶体管M4，所述第二N型场效晶体管M4的栅极与所述第四电阻R4的第二端连接，所述第二N型场效晶体管M4的第一极与所述 AVEE输入端连接，所述第二N型场效晶体管M4的第二极与所述驱动芯片连接；
第四电容C4，所述第四电容C4的第一端与所述第四电阻R4的第二端连接，所述第四电容C4的第二端接地，或者所述第四电容C4的第二端与所述第二N型场效晶体管M4的第二极连接。
该实施方式中，上述第一N型场效晶体管M3的第二极与所述驱动芯片连接的部位，与上述第二N型场效晶体管M4的第二极与所述驱动芯片连接的部位不同。上述场效晶体管的第一极和第二极可以分别为源极和漏极，或者分别为漏极和源极。为了更好的理解上述电路，可以参阅图4，图4为本公开的一些实施例提供的控制电路的结构示意图。
如图4所示，此时所述第三电容C3的第二端接地，所述第四电容C4的第二端接地。VDDI信号上电后，对第三电容C3充电，一般第三电容C3达到约0.3V即可开始达到开启第一N型场效晶体管M3的阈值电压，第三电容C3继续升压后打开第一N型场效晶体管M3，AVDD信号通过第一N型场效晶体管M3输入，一路进入驱动芯片的升压电路，另一路通过第四电阻R4对第四电容C4充电，随着第四电容C4电压上升打开第二N型场效晶体管M4，AVEE信号即可输入到驱动芯片内。这样，保证了VDDI信号先上电，然后AVDD信号，最后AVEE信号的上电顺序。
可选的，所述控制电路包括：
选择电路；
第三N型场效晶体管M5，所述VDDI输入端通过所述选择电路与所述第三N型场效晶体管M5的栅极连接，所述第三N型场效晶体管M5的第一极与所述AVDD输入端连接，所述第三N型场效晶体管M5的第二极与所述驱动芯片连接；
第四N型场效晶体管M6，所述VDDI输入端通过所述选择电路与所述第四N型场效晶体管M6的栅极连接，所述第四N型场效晶体管M6的第一极与所述AVEE输入端连接，所述第四N型场效晶体管M6的第二极与所述驱动芯片连接；
所述选择电路用于从所述第三N型场效晶体管M5和所述第四N型场效 晶体管M6中依次选择第一目标场效晶体管、第二目标场效晶体管，并依次延时导通所述第一目标场效晶体管、所述第二目标场效晶体管的源极和漏极。
该实施方式中，上述第三N型场效晶体管M5的第二极与所述驱动芯片连接的部位，与上述第四N型场效晶体管M6的第二极与所述驱动芯片连接的部位不同。上述场效晶体管的第一极和第二极可以分别为源极和漏极，或者分别为漏极和源极。上述第一目标场效晶体管为第三N型场效晶体管M5时，第二目标场效晶体管就为第四N型场效晶体管M6；上述第一目标场效晶体管为第四N型场效晶体管M6时，第二目标场效晶体管就为第三N型场效晶体管M5。
该实施方式中，选择电路可以包括不同的电容，用于控制AVDD信号和AVEE信号的上电和掉电时序。当AVEE信号早于AVDD信号输入至驱动芯片时，第二子输入端为AVEE输入端，第三子输入端为AVDD输入端；当AVDD信号早于AVEE信号输入至驱动芯片时，第二子输入端为AVDD输入端AVEE输入端，第三子输入端为AVEE输入端。当然，具体的方式可以根据实际的需求对选择电路进行设置，对此本实施方式不作限定。
为了更好的理解上述电路，可以参阅图5，图5为本公开的一些实施例提供的控制电路的结构示意图。
如图5所示，VDDI信号输入的情况下，选择电路工作起来后输出驱动信号，在事先设置好的顺序下，先后打开第三N型场效晶体管M5、第四N型场效晶体管M6，以控制AVDD信号先输入，AVEE信号再输入的顺序。可以事先编好程序固化在驱动芯片的内部，也可以VDDI信号上电后驱动芯片工作起来时，对驱动芯片内部编程，确定好AVDD信号和AVEE信号的上电顺序，选择电路输出相应顺序的控制信号。这样，可以通过编程方式灵活控制AVDD信号和AVEE信号的输入。
可选的，所述AVEE输入端与所述驱动芯片的通路上串联有热敏电阻；
和/或，所述AVDD输入端与所述驱动芯片的通路上串联有热敏电阻。
该实施方式中，通过串联热敏电阻的方式，当驱动芯片的升压电路发生闩锁大电流时，电流的增大引起热敏电阻发热而电阻增大，电阻增大降低了流过的电流的大小，从而可以保护驱动芯片。
为了更好的理解上述电路结构，可以参阅图6，图6为本公开的一些实施例提供的控制电路的结构示意图。如图6所示，所述AVEE输入端与所述驱动芯片的通路上串联有热敏电阻R5；以及，所述AVDD输入端与所述驱动芯片的通路上串联有热敏电阻R6。当驱动芯片启动工作时AVEE信号和AVDD信号抽取大电流时，特别是驱动芯片的升压电路发生闩锁大电流时，电流的增大引起热敏电阻发热而电阻增大，电阻增大降低了流过热敏电阻的电流大小，从而保护驱动芯片。
需要说明的是，本实施例中的电路中除了使用晶体管控制之外，也可以使用晶闸管控制电源的电流来实现。并且，电路中的电阻、热敏电阻和电容可以设置在外部的电路板上，也可以集成到驱动芯片的内部。本公开的一些实施例中介绍的多种可选的实施方式，彼此可以相互结合实现，也可以单独实现，对此本公开的一些实施例不作限定。
本公开的一些实施例的一种控制电路，所述控制电路用于控制输入至显示模组的驱动芯片的多个电源信号的通断时序，所述控制电路包括分别接收不同的外部电源信号的第一输入端101和第二输入端102，所述控制电路依次控制所述第一输入端101、所述第二输入端102输入电源信号至所述驱动芯片，且依次控制所述第二输入端102、所述第一输入端101掉电。这样，通过控制不同电源信号的时序，尽可能的保证了不同电源信号正常的时序，从而减小了驱动芯片损坏的概率。
本公开的一些实施例还提供一种液晶显示驱动模组，包括驱动芯片，所述液晶显示驱动模组还包括上述控制电路。
本公开的一些实施例还提供一种液晶显示装置，包括上述液晶显示驱动模组。
本公开的一些实施例中，上述液晶显示装置可以是手机、平板电脑(Tablet Personal Computer)、膝上型电脑(Laptop Computer)、个人数字助理(personal digital assistant，PDA)、移动上网装置(Mobile Internet Device，MID)或可穿戴式设备(Wearable Device)等等。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者 装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
上面结合附图对本公开的实施例进行了描述，但是本公开并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本公开的启示下，在不脱离本公开宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本公开的保护之内。

Claims (9)

  1. 一种控制电路，用于控制输入至显示模组的驱动芯片的多个电源信号的通断时序，所述控制电路包括分别接收不同的外部电源信号的第一输入端和第二输入端，所述控制电路依次控制所述第一输入端、所述第二输入端输入电源信号至所述驱动芯片，且依次控制所述第二输入端、所述第一输入端掉电。
  2. 根据权利要求1所述的控制电路，其中，所述第二输入端包括第二子输入端和第三子输入端，所述第二子输入端、所述第三子输入端分别接收不同的外部电源信号，所述控制电路依次控制所述第一输入端、所述第二子输入端、以及所述第三子输入端输入电源信号至所述驱动芯片，且依次控制所述第三子输入端、所述第二子输入端、以及所述第一输入端掉电。
  3. 根据权利要求2所述的控制电路，其中，所述第一输入端为VDDI输入端，所述第二子输入端为AVEE输入端，所述第三子输入端为AVDD输入端；
    或者，所述第一输入端为VDDI输入端，所述第二子输入端为AVDD输入端，所述第三子输入端为AVEE输入端。
  4. 根据权利要求3所述的控制电路，其中，所述第一输入端为VDDI输入端，所述第二子输入端为AVEE输入端，所述第三子输入端为AVDD输入端，所述控制电路包括：
    第一电阻，所述第一电阻的第一端与所述VDDI输入端连接；
    N型场效晶体管，所述N型场效晶体管的栅极与所述第一电阻的第二端连接，所述N型场效晶体管的第一极与所述AVEE输入端连接，所述N型场效晶体管的第二极与所述驱动芯片连接；
    第一电容，所述第一电容的第一端与所述第一电阻的第二端连接，所述第一电容的第二端接地，或者所述第一电容的第二端与所述N型场效晶体管的第二极连接；
    第二电阻，所述第二电阻的第一端与所述N型场效晶体管的第二极连接；
    P型场效晶体管，所述P型场效晶体管的栅极与所述第二电阻的第二端 连接，所述P型场效晶体管的第一极与所述AVDD输入端连接，所述P型场效晶体管的第二极与所述驱动芯片连接；
    第二电容，所述第二电容的第一端与所述第二电阻的第二端连接，所述第二电容的第二端接地，或者所述第二电容的第二端与所述P型场效晶体管的第二极连接。
  5. 根据权利要求3所述的控制电路，其中，所述第一输入端为VDDI输入端，所述第二子输入端为AVDD输入端，所述第三子输入端为AVEE输入端，所述控制电路包括：
    第三电阻，所述第三电阻的第一端与所述VDDI输入端连接；
    第一N型场效晶体管，所述第一N型场效晶体管的栅极与所述第三电阻的第二端连接，所述第一N型场效晶体管的第一极与所述AVDD输入端连接，所述第一N型场效晶体管的第二极与所述驱动芯片连接；
    第三电容，所述第三电容的第一端与所述第三电阻的第二端连接，所述第三电容的第二端接地，或者所述第三电容的第二端与所述第一N型场效晶体管的第二极连接；
    第四电阻，所述第四电阻的第一端与所述第一N型场效晶体管的第二极连接；
    第二N型场效晶体管，所述第二N型场效晶体管的栅极与所述第四电阻的第二端连接，所述第二N型场效晶体管的第一极与所述AVEE输入端连接，所述第二N型场效晶体管的第二极与所述驱动芯片连接；
    第四电容，所述第四电容的第一端与所述第四电阻的第二端连接，所述第四电容的第二端接地，或者所述第四电容的第二端与所述第二N型场效晶体管的第二极连接。
  6. 根据权利要求3所述的控制电路，还包括：
    选择电路；
    第三N型场效晶体管，所述VDDI输入端通过所述选择电路与所述第三N型场效晶体管的栅极连接，所述第三N型场效晶体管的第一极与所述AVDD输入端连接，所述第三N型场效晶体管的第二极与所述驱动芯片连接；
    第四N型场效晶体管，所述VDDI输入端通过所述选择电路与所述第四 N型场效晶体管的栅极连接，所述第四N型场效晶体管的第一极与所述AVEE输入端连接，所述第四N型场效晶体管的第二极与所述驱动芯片连接；
    所述选择电路用于从所述第三N型场效晶体管和所述第四N型场效晶体管中依次选择第一目标场效晶体管、第二目标场效晶体管，并依次延时导通所述第一目标场效晶体管、所述第二目标场效晶体管的源极和漏极。
  7. 根据权利要求3至6中任一项所述的控制电路，其中，所述AVEE输入端与所述驱动芯片的通路上串联有热敏电阻；
    和/或，所述AVDD输入端与所述驱动芯片的通路上串联有热敏电阻。
  8. 一种液晶显示驱动模组，包括驱动芯片，所述液晶显示驱动模组还包括权利要求1至7中任一项所述的控制电路。
  9. 一种液晶显示装置，包括权利要求8所述的液晶显示驱动模组。
PCT/CN2019/116588 2018-11-14 2019-11-08 控制电路、液晶显示驱动模组及液晶显示装置 Ceased WO2020098569A1 (zh)

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