WO2020103385A1 - Pcb设计版图的开短路检查方法、检测系统及电子设备 - Google Patents

Pcb设计版图的开短路检查方法、检测系统及电子设备

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Publication number
WO2020103385A1
WO2020103385A1 PCT/CN2019/082645 CN2019082645W WO2020103385A1 WO 2020103385 A1 WO2020103385 A1 WO 2020103385A1 CN 2019082645 W CN2019082645 W CN 2019082645W WO 2020103385 A1 WO2020103385 A1 WO 2020103385A1
Authority
WO
WIPO (PCT)
Prior art keywords
netlist
pcb
design layout
group
pcb design
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/082645
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English (en)
French (fr)
Inventor
钱胜杰
刘丰收
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vayo Shanghai Technology Co Ltd
Original Assignee
Vayo Shanghai Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vayo Shanghai Technology Co Ltd filed Critical Vayo Shanghai Technology Co Ltd
Priority to US17/296,230 priority Critical patent/US11604916B2/en
Priority to JP2021528897A priority patent/JP7141669B2/ja
Priority to EP19887400.0A priority patent/EP3916512A4/en
Publication of WO2020103385A1 publication Critical patent/WO2020103385A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3953—Routing detailed
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/02—Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]

Definitions

  • the invention relates to the technical field of printed circuit boards, in particular to an open and short circuit inspection method, detection system and electronic equipment for PCB design layout.
  • PCB Printed Circuit Board
  • PCB design layout is also PCB layout layout design, is the last link of circuit design. After the PCB wiring is completed, it will enter the bare board manufacturing process of the PCB. The bare board manufacturing process of PCB needs to be completed according to PCB design data (Gerber file and hole data). It can be seen that the PCB design layout is the premise and foundation of the entire PCB manufacturing, and the quality of the design determines the quality status of the entire PCB and even electronic products. The quality problem that is most likely to occur in the design layout of the PCB is the problem of open and short circuit of the PCB circuit, and this problem is also the main problem that each designer and PCB bare board manufacturer must solve.
  • bare board manufacturers will modify the PCB design data (eg Gerber files) before the bare board is manufactured, so that the actual bare PCB board can meet the design function, and In the process of modification, it may cause an open or short circuit of the line.
  • PCB design data eg Gerber files
  • the object of the present invention is to provide an open and short circuit inspection method, detection system and electronic equipment for PCB design layout, which can quickly and efficiently verify whether the PCB design data is consistent with the initial netlist of the wiring, and Ensure the accuracy of PCB design data.
  • the present invention provides an open and short circuit inspection method for PCB design layout, including: reading the PCB data of the PCB design layout to be inspected, and then outputting each PCB included in the PCB design layout Layer image; perform a first connectivity analysis on each of the PCB layer images to group the pad patterns in the same layer into the same subnet group; drill holes on the PCB design layout The second connectivity analysis is performed on each plated hole of each to group the sub-network groups where the pad patterns connected to each of the plated holes through different PCB layers are grouped into the same parent network group; read the PCB Design the IPC netlist data of the layout to obtain the netlist network group where the pad patterns are located; determine whether the netlist network relationship of the pad patterns and the network relationship after the second connectivity analysis If they are consistent, it is determined that the PCB design layout does not have an open and short circuit problem; otherwise, it is determined that the PCB design layout has an open and short circuit problem.
  • the step of determining whether the PCB design layout has open or short circuit problems according to the netlist network relationship of each of the pad patterns and the network relationship after the second connectivity analysis specifically includes: If the pad patterns belonging to the same netlist network group do not belong to the same parent network group, it is determined that there is an open circuit problem in the PCB design layout, and the open circuit problem occurs in the netlist network group and the specific location of the open circuit It may be that the pad patterns of the individual parent net group names in the net list net group are inconsistent with other parent net group names; if the pad patterns belonging to the same parent net group do not belong to the same net list net group, it is determined The PCB design layout has a short circuit problem, and the short circuit problem occurs in the parent network group, and the specific location of the short circuit may be a pad pattern in which the individual netlist network group names in the parent network group are inconsistent with other netlist network group names; If the pad patterns belonging to the same netlist net group also belong to the same parent net group, or if the pad patterns belonging to
  • the method further includes: outputting an image of the IPC netlist data; the IPC netlist data includes coordinates of each pad pattern; and searching for the existence from the IPC netlist data The coordinates of the pad pattern included in the network group of the open and short circuit problem; highlight the coordinate positions obtained by the search on the image of the IPC netlist data.
  • the method further includes: generating an inspection report; the inspection report includes identification information of each pad pattern, information of a netlist network group to which it belongs, information of a parent network group to which it belongs, and inspection result.
  • the present invention provides an open and short circuit inspection system for PCB design layout, including: a PCB data reading module for reading PCB data of a PCB design layout to be inspected, and outputting the An image of each PCB layer included in the PCB design layout; a connectivity analysis module, which is used to perform a first connectivity analysis on the images of each of the PCB layers, to classify the patterns of the pads that are in contact with each other in the same layer The same subnet group; and for performing a second connectivity analysis on each plated hole of the drilled layer of the PCB design layout, so as to connect each plated hole through the different PCB layers and connect each pad pattern
  • Each of the sub-network groups is grouped into the same parent network group; an IPC netlist data reading module is used to read the IPC netlist data of the PCB design layout to obtain the netlist network where each pad pattern is located Group; open and short check module, used to determine whether the netlist network relationship of each pad pattern is consistent with the network relationship after the second connectivity
  • the open-short inspection module determines whether there is an open-short problem in the PCB design layout according to the netlist network relationship of each pad pattern and the network relationship after the second connectivity analysis
  • the implementation method includes: if each pad pattern belonging to the same netlist network group does not belong to the same parent network group, it is determined that the PCB design layout has an open circuit problem, and the open circuit problem occurs in the netlist network group, And the specific location of the open circuit may be the pad pattern of the individual parent net group names in the net list net group that are inconsistent with other parent net group names; if the pad patterns belonging to the same parent net group do not belong to the same net list Network group, it is determined that there is a short circuit problem in the PCB design layout, and the short circuit problem occurs in the parent network group, and the specific location of the short circuit may be that the individual netlist network group names in the parent network group are inconsistent with other netlist network group names Land pattern; if each land pattern belonging to the same netlist network group also belongs to the same parent network group, or
  • the IPC netlist data reading module is further used to: output an image of the IPC netlist data; wherein, the IPC netlist data includes coordinates of each of the pad patterns;
  • the system also includes: a highlighting module, used to: find the coordinates of the pad pattern contained in the network group with open and short circuit problems from the IPC netlist data; find on the image of the IPC netlist data To highlight the coordinate position.
  • the system further includes: an inspection report generation module for generating an inspection report; the inspection report includes identification information of each pad pattern, information of a netlist network group to which it belongs, and a parent to which it belongs Network group information and inspection results.
  • the present invention provides a storage medium in which a computer program is stored, and when the computer program is loaded and executed by a processor, the method for inspecting the open and short circuit of the PCB design layout is realized.
  • the present invention provides an electronic device, including: a processor and a memory; wherein the memory is used to store a computer program; the processor is used to load and execute the computer program, so that all The electronic device executes the open-short inspection method of the PCB design layout.
  • the PCB design layout open-short inspection method, detection system and electronic equipment of the present invention automatically and intelligently realize the PCB design layout open-short inspection before manufacturing the bare PCB board, which reduces the production of finished products
  • the workload of opening and short circuit inspection of PCB with testing equipment can be used in PCB design enterprises and bare board manufacturing factories, and effectively prevents the open circuit short-circuit defects of the manufactured bare PCB boards, thereby avoiding scrapping large quantities of bare PCB boards.
  • the present invention also objectively improves the production efficiency of the bare board manufacturing plant, reduces the loss and risk of enterprise losses, and contributes to the improvement of the overall competitiveness of the enterprise.
  • FIG. 1 is a schematic flowchart of an open-short inspection method of a PCB design layout in an embodiment of the present invention.
  • Figure 2 shows a schematic diagram of the structure of the PCB physical layer.
  • FIG. 3A shows an image output according to the read PCB data in an embodiment of the present invention.
  • FIG. 3B is a partially enlarged view of part H in FIG. 3A.
  • Figure 4 shows the output image of Figure 3 after connectivity analysis.
  • FIG. 5 shows an image output according to the read IPC netlist data in an embodiment of the present invention.
  • FIG. 6 shows a schematic block diagram of an open and short circuit inspection system of a PCB design layout in an embodiment of the invention.
  • FIG. 7 is a schematic diagram of an electronic device in an embodiment of the invention.
  • this embodiment provides an open and short circuit inspection method for PCB design layout, including the following steps:
  • S1 Read the PCB data of the PCB design layout to be checked, and output images of each PCB layer included in the PCB design layout accordingly.
  • the read PCB data is the physical layer data required for manufacturing the bare PCB board.
  • the physical layer includes: a front signal layer, an intermediate signal layer (the number of intermediate layers is between 0 and n), a reverse signal layer, and a drilled layer. Among them, there may be multiple files in the drilled layer, including electroplating and non-plating, and those that penetrate the different layers will be divided into multiple files.
  • the file format of PCB data includes but is not limited to Gerber / Barco DPF / MDA.
  • Figure 2 shows the copper foil pattern for the front signal layer.
  • the layers output according to the PCB data are arranged in the order of the actual PCB layers, in order: front signal layer 21, middle signal layers 22 and 23, and back signal layer 24, of which, between the front signal layer 21 and the middle signal layer 22,
  • the intermediate signal layer 22 and the intermediate signal layer 23 and the intermediate signal layer 23 and the reverse signal layer 24 are separated by an insulating layer 25.
  • the plated holes 26 and the non-plated holes 27 penetrate the front signal layer 21, the intermediate signal layers 22 and 23, the back signal layer 24, and the insulating layers 25, respectively.
  • the plated hole 26 connects the front signal layer 21 and the back signal layer 24, while the non-plated hole 27 does not connect the layer through which it penetrates.
  • Reference numeral 28 denotes copper foil.
  • FIG. 3A shows an image of each PCB layer contained in it, which is output according to the PCB data of the PCB design layout to be inspected.
  • FIG. 3B is a partially enlarged view of part H in FIG. 3A. Since the connectivity analysis has not been performed at this time, the pad patterns on the PCB layer have not been regrouped, "NETNAME" is empty, and the network relationship between the pad patterns has not been redefined.
  • S2 Perform a first connectivity analysis on the images of each of the PCB layers, so as to group the patterns of the pads contacting together in the same layer into the same subnet group.
  • the first connectivity analysis is the first stage of connectivity analysis.
  • the image processing algorithm analyzes whether the pad patterns in FIG. 3A are connected together. Taking part H as an example, referring to FIG. 3B, after the image analysis, it is concluded that the pad patterns in the H1 area are connected together, while the pad patterns in the H2 area and the pad patterns in the H1 area are both Is separate. Therefore, after the first connectivity analysis, each pad pattern in the H1 area is classified as the same subnet group 1, the pad pattern in the H2 area is classified as a subnet group 2, and so on.
  • S3 Perform a second connectivity analysis on each plated hole of the drilled layer of the PCB design layout to penetrate the plated holes through the different PCB layers and connect the subnet groups where the pad patterns are connected Grouped into the same parent network group.
  • the second connectivity analysis is the second stage of connectivity analysis. In this stage, the connection relationship between layers should be analyzed. Step S1 will recognize whether the hole layer is electroplated after reading in the PCB data of the drilled layer, and identify which associated layers are drilled through the plated hole layer. Subsequently, when performing the second connectivity analysis, the sub-network group where the pad patterns of different PCB layers connected to the plating holes are located will be classified as the same parent network group.
  • each pad pattern on the front signal layer is divided into subnet group 1, subnet group 2, and subnet group 3; each pad pattern on the back signal layer is Divided into subnet group 1 ', subnet group 2', subnet group 3 ', because the plating hole penetrates the front signal layer and the back signal layer, so subnet group 1 and subnet group 1' are Is grouped into the same parent network group NET1, child network group 2 and child network group 2 'are grouped into the same parent network group NET2, child network group 3 and child network group 3' are grouped into the same parent network group NET3, And so on.
  • IPC netlist data includes IPC-D-356 netlist data or similar data.
  • the IPC-D-356 netlist data contains the network names and coordinates of all the pad patterns on the signal layers on the front and back sides of the PCB.
  • each pad pattern has a netlist net name.
  • the netlist net names are the same and can be regarded as belonging to the same netlist net group, and the netlist net relationship of each pad pattern is determined accordingly.
  • Figure 5 shows the images of each PCB layer contained in the IPC netlist data output of the PCB design layout to be inspected, in which the netname network name NetName of the pad pattern highlighted is "N18289723".
  • step S5 Determine whether the netlist network relationship of each pad pattern is consistent with the network relationship after the second connectivity analysis; if they are consistent, step S6 is performed; otherwise, step S7 is performed.
  • the network relationship of each pad pattern is formed by the relationship between netlist network groups; and after the connectivity analysis, the network relationship of each pad pattern is formed by the relationship between parent network groups.
  • the pad patterns belonging to the same netlist net group also belong to the same parent net group after connectivity analysis, or if the pad patterns belonging to the same parent net group also belong to the same net list net group, It means that the network relationship before and after is consistent; if the pad patterns belonging to the same netlist network group do not belong to the same parent network group after connectivity analysis, or if the pad patterns belong to the same netlist network group If they do not belong to the same parent network group, it means that the network relationship before and after is inconsistent.
  • the PCB design is determined There is no open or short circuit problem in the layout.
  • each pad pattern belonging to the same netlist net group does not belong to the same parent net group, it is determined that there is an open circuit problem in the PCB design layout, and the open circuit problem occurs in the netlist net group, and
  • the specific location of the open circuit may be the pad pattern of the individual parent network group name in the netlist net group that is inconsistent with other parent net group names, or it may be in a line or a hole of the netlist net group; if it belongs to the same If the pad patterns of the parent network group do not belong to the same netlist network group, it is determined that the PCB design layout has a short circuit problem, and the short circuit problem occurs in the parent network group, and the specific location of the short circuit may be in the parent The pad patterns of individual netlist netgroup names in the netgroup that are inconsistent with other netlist netgroup names may also be on a line or a hole in the parent netgroup.
  • the method further includes the step of generating an inspection report.
  • the inspection report includes identification information of each of the pad patterns, information of the netlist network group to which it belongs, information of the parent network group to which it belongs, and the inspection result.
  • Table 1 is sorted by network name 1 as the main keyword.
  • the "network name 1" is the name of the "netlist network group” introduced above; the network name 2 is ranked first by the number of occurrences of the name, and the “network name 2 "is the name of the" parent network group "introduced above.
  • “A18289723” corresponds to the largest number of "NET1”, so “NET1” is ranked first, and “NET3” is ranked behind;
  • VCC corresponds to the largest number of "NET6”, so “NET6” is ranked first , And “NET3” and “NET22” come next.
  • Table 2 is sorted by network name 2 as the main keyword.
  • the "network name 2" is the name of the "parent network group” introduced above; the network name 1 is ranked first by the number of occurrences of the name, and the “network name 1" "Is the name of the" netlist netgroup “introduced above.
  • "NET3" corresponds to the largest number of "GND”, so “GND” is ranked first, while “A18289723" and “VCC” are ranked behind.
  • the PCB data graphic number is the identification of the pad pattern in the "parent network group”
  • the net list graphic number is the identification of the pad pattern in the "net list network group”.
  • the pad pattern with PCB data pattern number “187” actually refers to the pad pattern with netlist pattern number “7”, and so on.
  • the pad pattern is identified by "PCB data pattern number” by default. Of course, it is equivalent to the way of identifying the pad pattern by "netlist pattern number”. In the following, the short-circuit judgment process is explained in detail using the "net list pattern number" of the pad pattern.
  • the IPC netlist data includes coordinates of each of the pad patterns.
  • step S7 when it is determined that a certain netlist net group has open and short circuit problems, the output image of the IPC netlist data shown in FIG. 5 and the image shown in FIG. 4 are superimposed to extract the IPC netlist data Find the coordinates of the pad pattern with open and short circuit problems, and highlight the positions of these coordinates on the image of the IPC netlist data, so that it is convenient to view the cause of the open and short circuit.
  • protection scope of the open and short circuit inspection method of the PCB design layout described in the present invention is not limited to the execution order of the steps enumerated in this embodiment, and any increase or decrease of the prior art steps and steps according to the principles of the present invention The solutions implemented by the replacement are all included in the protection scope of the present invention.
  • the present invention also provides a computer program product, including one or more computer instructions.
  • the computer instructions may be stored in a computer-readable storage medium.
  • the computer-readable storage medium may be any available medium that can be stored by a computer or a data storage device including a server, a data center, and the like integrated with one or more available media.
  • the usable media may be magnetic media (such as floppy disk, hard disk, magnetic tape), optical media (such as DVD), or semiconductor media (such as Solid State Disk (SSD)), etc.
  • this embodiment provides a PCB design layout open and short circuit inspection system 600, which is installed as a piece of software in an electronic device to perform the PCB design layout open and short circuit inspection method described in the foregoing method embodiment at runtime. . Since the technical principle of the embodiment of the system is similar to that of the foregoing method embodiment, the same technical details will not be repeated repeatedly.
  • the open circuit and short circuit inspection system 600 of the PCB design layout of this embodiment specifically includes: a PCB data reading module 601, a connectivity analysis module 602, an IPC netlist data reading module 603, an open and short circuit inspection module 604, and further includes: an inspection report Generate the module.
  • the PCB data reading module 601 is used to perform step S1 described in the foregoing method embodiment
  • the connectivity analysis module 602 is used to perform steps S2 to S3 described in the foregoing method embodiment.
  • the IPC netlist data reading module 603 is used to perform step S4 described in the foregoing method embodiment
  • the open / short check module 604 is used to perform steps S5 to S7 described in the foregoing method embodiment.
  • the inspection report generation module is used to generate an inspection report.
  • each module in the embodiment of FIG. 6 is only a division of logical functions, and may be integrated in whole or part into one or more physical entities in actual implementation.
  • these modules can be implemented in the form of software invocation through processing elements, or in the form of hardware, and some modules can be implemented in the form of software invocation of processing elements, and some modules can be implemented in the form of hardware.
  • the connectivity analysis module 602 can be a separate processing element or can be integrated in a certain chip.
  • it can also be stored in the memory in the form of program code, which can be called by a processing element and perform connectivity analysis.
  • the function of the module 602. The implementation of other modules is similar.
  • the processing element described here may be an integrated circuit with signal processing capabilities.
  • each step of the above method or each of the above modules may be completed by an integrated logic circuit of hardware in the processor element or instructions in the form of software.
  • the electronic device may be a desktop computer, a portable computer, a smart phone, or the like.
  • the electronic device includes at least: a memory 72 and a processor 73 connected by a bus 71, wherein the memory 72 is used to store a computer program, and the processor 73 is used to execute the computer program stored in the memory 72 to execute the foregoing method embodiment All or part of the steps.
  • the system bus mentioned above may be a peripheral component interconnection standard (Peripheral Pomponent Interconnect, abbreviated as PCI) bus or an extended industry standard structure (Extended Industry Standard Architecture, abbreviated as EISA) bus, etc.
  • PCI peripheral component interconnection standard
  • EISA Extended Industry Standard Architecture
  • the system bus can be divided into address bus, data bus, control bus and so on. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.
  • the communication interface is used to implement communication between the database access device and other devices (such as client, read-write library, and read-only library).
  • the memory may include random access memory (Random Access Memory, RAM for short), or may also include non-volatile memory (non-volatile memory), such as at least one disk memory.
  • the aforementioned processor may be a general-purpose processor, including a central processor (Central Processing Unit, CPU for short), a network processor (Network Processor, short for NP), etc .; or a digital signal processor (Digital Signal Processing, DSP for short) , Application Specific Integrated Circuit (ASIC), Field-Programmable Gate Array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • a central processor Central Processing Unit, CPU for short
  • a network processor Network Processor, short for NP
  • DSP Digital Signal Processing
  • ASIC Application Specific Integrated Circuit
  • FPGA Field-Programmable Gate Array
  • the PCB design layout open-short inspection method, detection system and electronic equipment of the present invention effectively overcome various shortcomings in the prior art and have high industrial utilization value.

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Abstract

一种PCB设计版图的开短路检查方法，以检查PCB设计数据的正确性，包括：读取待检查的PCB设计版图的PCB数据，输出PCB设计版图所包含的各PCB层的图像（S1）；对各PCB层的图像分别进行第一连通性分析，以将同层中接触在一起的各焊盘图形归为同一子网络组（S2）；对PCB设计版图的钻孔层的各电镀孔分别进行第二连通性分析，以将各电镀孔贯穿不同PCB层而连接的各焊盘图形所在的各子网络组归为同一父网络组（S3）；读取PCB设计版图的IPC网表数据，获得各焊盘图形所在的网表网络组（S4）；判断各焊盘图形的网表网络关系与经第二连通性分析之后的网络关系是否一致（S5）；若一致，则判定PCB设计版图不存在开短路问题（S6）；反之，则存在开短路问题（S7）。

Description

PCB设计版图的开短路检查方法、检测系统及电子设备 技术领域
本发明涉及印刷电路板技术领域，特别是涉及PCB设计版图的开短路检查方法、检测系统及电子设备。
背景技术
PCB(Printed Circuit Board，印刷电路板)是各种电子元器件的载体，在现代电子产品中，几乎都要使用PCB。随着技术的不断发展以及工艺水平的不断提高，电子产品趋于更轻、更薄、更小的趋势发展，PCB便朝着高密度、小元件、细间距、层数更多的方向发展，这使得PCB的质量检验工作越来越具有挑战性。
PCB设计版图也就是PCB Layout布线设计，是电路设计的最后一个环节。在PCB布线结束后，将进入PCB的裸板制造环节。PCB的裸板制造环节需要依据PCB设计数据(Gerber文件和孔数据)完成。由此可见，PCB设计版图是整个PCB制造的前提和基础，设计质量的优劣决定着整个PCB甚至电子产品的质量状态。而PCB的设计版图最容易出现的质量问题就是PCB线路的开短路问题，并且该问题也是每个设计人员及PCB裸板制造厂商必须解决的主要问题。
通常情况下，导致PCB线路出现开短路的原因有以下几点：
1、从PCB布线软件中输出的PCB设计数据存在错误(例如：Gerber文件存在bug或PCB布线设计本身就有误)，从而导致设计的版图与最初的网表连通关系不一样，形成线路的开路或短路。
2、基于PCB裸板的制造工艺，裸板制造厂商在裸板制造前会对PCB设计数据(例如：Gerber文件)进行适当的修改，以使实际制造出的PCB裸板能够满足设计功能，而在修改的过程中有可能造成线路的开路或短路。
鉴于PCB的裸板生产是根据PCB设计数据实现的，因此只有保证PCB设计数据的正确性才能有效地降低甚至避免PCB线路出现开短路问题。可见，保证PCB设计数据的正确性具有重要意义。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供PCB设计版图的开短路检查方法、检测系统及电子设备，能够快速高效地验证PCB设计数据与布线最初时的网表是否一 致，进而保证PCB设计数据的正确性。
为实现上述目的及其他相关目的，本发明提供一种PCB设计版图的开短路检查方法，包括：读取待检查的PCB设计版图的PCB数据，据以输出所述PCB设计版图所包含的各PCB层的图像；对各所述PCB层的图像分别进行第一连通性分析，以将同层中接触在一起的各焊盘图形归为同一子网络组；对所述PCB设计版图的钻孔层的各电镀孔分别进行第二连通性分析，以将各所述电镀孔贯穿不同PCB层而连接的各焊盘图形所在的各所述子网络组归为同一父网络组；读取所述PCB设计版图的IPC网表数据，据以获得各所述焊盘图形所在的网表网络组；判断各所述焊盘图形的网表网络关系与经所述第二连通性分析之后的网络关系是否一致；若一致，则判定所述PCB设计版图不存在开短路问题；反之，则判定所述PCB设计版图存在开短路问题。
于本发明一实施例中，根据各所述焊盘图形的网表网络关系与经所述第二连通性分析之后的网络关系判断所述PCB设计版图是否存在开短路问题的步骤，具体包括：若属于同一所述网表网络组的各焊盘图形不属于同一所述父网络组，则判定所述PCB设计版图存在开路问题，且开路问题出现在该网表网络组，且开路的具体位置可能在于该网表网络组中个别父网络组名与其它父网络组名不一致的焊盘图形；若属于同一所述父网络组的各焊盘图形不属于同一所述网表网络组，则判定所述PCB设计版图存在短路问题，且短路问题出现在该父网络组，且短路的具体位置可能在于该父网络组中个别网表网络组名与其它网表网络组名不一致的焊盘图形；若属于同一网表网络组的各焊盘图形也属于同一父网络组，或者，若属于同一父网络组的各焊盘图形也属于同一网表网络组，则判定所述PCB设计版图不存在开短路问题。
于本发明一实施例中，所述方法还包括：输出所述IPC网表数据的图像；所述IPC网表数据包含各所述焊盘图形的坐标；从所述IPC网表数据中查找存在开短路问题的网络组所包含的焊盘图形的坐标；在所述IPC网表数据的图像上对查找得到的坐标位置做突出显示。
于本发明一实施例中，所述方法还包括：生成检查报告；所述检查报告包括各所述焊盘图形的标识信息、所属网表网络组的信息、所属父网络组的信息、及检查结果。
为实现上述目的及其他相关目的，本发明提供一种PCB设计版图的开短路检查系统，包括：PCB数据读取模块，用于读取待检查的PCB设计版图的PCB数据，据以输出所述PCB设计版图所包含的各PCB层的图像；连通性分析模块，用于对各所述PCB层的图像分别进行第一连通性分析，以将同层中接触在一起的各焊盘图形归为同一子网络组；以及用于对所述PCB设计版图的钻孔层的各电镀孔分别进行第二连通性分析，以将各所述电镀孔贯穿不同 PCB层而连接的各焊盘图形所在的各所述子网络组归为同一父网络组；IPC网表数据读取模块，用于读取所述PCB设计版图的IPC网表数据，据以获得各所述焊盘图形所在的网表网络组；开短路检查模块，用于判断各所述焊盘图形的网表网络关系与经所述第二连通性分析之后的网络关系是否一致；若一致，则判定所述PCB设计版图不存在开短路问题；反之，则判定所述PCB设计版图存在开短路问题。
于本发明一实施例中，所述开短路检查模块根据各所述焊盘图形的网表网络关系与经所述第二连通性分析之后的网络关系判断所述PCB设计版图是否存在开短路问题的实现方式包括：若属于同一所述网表网络组的各焊盘图形不属于同一所述父网络组，则判定所述PCB设计版图存在开路问题，且开路问题出现在该网表网络组，且开路的具体位置可能在于该网表网络组中个别父网络组名与其它父网络组名不一致的焊盘图形；若属于同一所述父网络组的各焊盘图形不属于同一所述网表网络组，则判定所述PCB设计版图存在短路问题，且短路问题出现在该父网络组，且短路的具体位置可能在于该父网络组中个别网表网络组名与其它网表网络组名不一致的焊盘图形；若属于同一网表网络组的各焊盘图形也属于同一父网络组，或者，若属于同一父网络组的各焊盘图形也属于同一网表网络组，则判定所述PCB设计版图不存在开短路问题。
于本发明一实施例中，所述IPC网表数据读取模块还用于：输出所述IPC网表数据的图像；其中，所述IPC网表数据包含各所述焊盘图形的坐标；所述系统还包括：突出标记模块，用于：从所述IPC网表数据中查找存在开短路问题的网络组所包含的焊盘图形的坐标；在所述IPC网表数据的图像上对查找得到的坐标位置做突出显示。
于本发明一实施例中，所述系统还包括：检查报告生成模块，用于生成检查报告；所述检查报告包括各所述焊盘图形的标识信息、所属网表网络组的信息、所属父网络组的信息、及检查结果。
为实现上述目的及其他相关目的，本发明提供一种存储介质，其中存储有计算机程序，所述计算机程序被处理器加载执行时，实现所述的PCB设计版图的开短路检查方法。
为实现上述目的及其他相关目的，本发明提供一种电子设备，包括：处理器及存储器；其中，所述存储器用于存储计算机程序；所述处理器用于加载执行所述计算机程序，以使所述电子设备执行所述的PCB设计版图的开短路检查方法。
如上所述，本发明的PCB设计版图的开短路检查方法、检测系统及电子设备，在PCB裸板制造前，自动化、智能化地实现了PCB设计版图的开短路检查，减少了制造出成品后用检测设备进行PCB的开短路检查的工作量。本发明可以在PCB设计企业和裸板制造工厂使 用，有效防止了制造出来的PCB裸板的开路短路缺陷，从而避免大批量的PCB裸板报废。当然，本发明还从客观上提高了裸板制造工厂的生产效率，降低了企业损的耗和风险，更有助于企业整体竞争能力的提升。
附图说明
图1显示为本发明一实施例中的PCB设计版图的开短路检查方法的流程示意图。
图2显示为PCB物理层的结构示意图。
图3A显示为本发明一实施例中的根据读入的PCB数据所输出的图像。
图3B显示为图3A中H部分的局部放大图。
图4显示为图3经连通性分析后所输出的图像。
图5显示为本发明一实施例中的根据读入的IPC网表数据所输出的图像。
图6显示为本发明一实施例中的PCB设计版图的开短路检查系统的模块示意图。
图7显示为本发明一实施例中的电子设备的示意图。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。需说明的是，在不冲突的情况下，以下实施例及实施例中的特征可以相互组合。
需要说明的是，以下实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
如图1所示，本实施例提供一种PCB设计版图的开短路检查方法，包括以下步骤：
S1：读取待检查的PCB设计版图的PCB数据，据以输出所述PCB设计版图所包含的各PCB层的图像。
读入的PCB数据为制造PCB裸板所需的物理层数据，物理层包括：正面信号层、中间信号层(中间层的数量在0到n之间)、反面信号层，以及钻孔层。其中，钻孔层有可能有多个文件，包括电镀和不电镀，且贯通不同层的会分为多个文件。PCB数据的文件格式包括但不限于Gerber/Barco DPF/MDA。图2显示为正面信号层的铜箔图形。将根据PCB数据输 出的各层按照实际PCB层的顺序排列，依次为：正面信号层21、中间信号层22及23、反面信号层24，其中，正面信号层21与中间信号层22之间、中间信号层22与中间信号层23之间、中间信号层23与反面信号层24之间由绝缘层25隔开。电镀孔26和非电镀孔27分别贯通正面信号层21、中间信号层22及23、反面信号层24、各绝缘层25。电镀孔26连接正面信号层21与反面信号层24，而非电镀孔27则不会连接其所贯通的层。标号28表示铜箔。
图3A展示为根据待检测PCB设计版图的PCB数据输出的其所包含的各PCB层的图像。图3B显示为图3A中H部分的局部放大图。由于此时尚未进行连通性分析，因而PCB层上各个焊盘图形并没有被重新划分组别，“NETNAME”为空，各个焊盘图形之间的网络关系也没有被重新定义。
S2：对各所述PCB层的图像分别进行第一连通性分析，以将同层中接触在一起的各焊盘图形归为同一子网络组。
第一连通性分析是连通性分析的第一个阶段。在该阶段中，通过图像处理算法分析图3A中的各焊盘图形是否连接在一起。以H部分为例，参阅图3B，经图像分析之后得出结论：H1区域中的各个焊盘图形是连接在一起的，而H2区域中的焊盘图形与H1区域中的各焊盘图形皆是分离的。由此，经第一连通性分析后，H1区域中的各焊盘图形被归为同一子网络组1，H2区域中的焊盘图形被归为一子网络组2，以此类推。
S3：对所述PCB设计版图的钻孔层的各电镀孔分别进行第二连通性分析，以将各所述电镀孔贯穿不同PCB层而连接的各焊盘图形所在的各所述子网络组归为同一父网络组。
第二连通性分析是连通性分析的第二个阶段。在该阶段中，要分析层间的连接关系。步骤S1在读入钻孔层的PCB数据后会识别出孔层是否为电镀，并识别电镀孔层钻通哪些关联层。随后，在进行第二连通性分析时，电镀孔所连接的不同PCB层的焊盘图形所在的子网络组会被归为同一父网络组。例如，经第一连通性分析后，正面信号层上的各焊盘图形被划分为子网路组1、子网路组2、子网路组3；反面信号层上的各焊盘图形被划分为子网路组1’、子网路组2’、子网路组3’，因电镀孔贯穿了正面信号层与反面信号层，故子网路组1与子网路组1’被归为同一父网络组NET1，子网路组2与子网路组2’被归为同一父网络组NET2，子网路组3与子网路组3’被归为同一父网络组NET3，以此类推。
如图4所示，如此，图3中“NETNAME”原本为空的焊盘图形被赋予了父网络组名“Net1”。
值得说明的是，在父网络组确定之后，连通性分析也即完成。此时，各焊盘图形经连通性分析之后形成的网络关系也就随之确定。
S4：读取所述PCB设计版图的IPC网表数据，以获得各所述焊盘图形所在的网表网络组。
IPC网表数据包括IPC-D-356网表数据或类似数据。IPC-D-356网表数据包含PCB正反面信号层上所有焊盘图形的网络名和坐标。也就是说，在这些行业标准的网表数据中，各焊盘图形是具有网表网络名的。网表网络名相同，可被视为属于同一网表网络组，各焊盘图形的网表网络关系也就随之确定。
图5显示为根据待检测PCB设计版图的IPC网表数据输出的其所包含的各PCB层的图像，其中，被重点标记的焊盘图形的网表网络名NetName为“N18289723”。
S5：判断各所述焊盘图形的网表网络关系与经所述第二连通性分析之后的网络关系是否一致；若一致，则执行步骤S6；反之，则执行步骤S7。
在进行连通性分析之前，各焊盘图形的网络关系由网表网络组之间的关系构成；而在进行连通性分析之后，各焊盘图形的网络关系由父网络组之间的关系构成。详细而言，若属于同一网表网络组的各焊盘图形在经连通性分析后也属于同一父网络组，或者，若属于同一父网络组的各焊盘图形也属于同一网表网络组，则说明前后网络关系一致；若属于同一所述网表网络组的各焊盘图形在经连通性分析后不属于同一所述父网络组，或者，若属于同一网表网络组的各焊盘图形不属于同一父网络组，则说明前后网络关系不一致。
S6：判定所述PCB设计版图不存在开短路问题。
详细而言，若属于同一网表网络组的各焊盘图形也属于同一父网络组，或者，若属于同一父网络组的各焊盘图形也属于同一网表网络组，则判定所述PCB设计版图不存在开短路问题。
S7：判定所述PCB设计版图存在开短路问题。
详细而言，若属于同一所述网表网络组的各焊盘图形不属于同一所述父网络组，则判定所述PCB设计版图存在开路问题，且开路问题出现在该网表网络组，且开路的具体位置可能在于该网表网络组中个别父网络组名与其它父网络组名不一致的焊盘图形，也可能在该网表网络组的某个线路或某个孔处；若属于同一所述父网络组的各焊盘图形不属于同一所述网表网络组，则判定所述PCB设计版图存在短路问题，且短路问题出现在该父网络组，且短路的具体位置可能在于该父网络组中个别网表网络组名与其它网表网络组名不一致的焊盘图形，也可能在该父网络组的某个线路或某个孔处。
在一实施例中，进一步地，所述方法还包括生成检查报告的步骤。所述检查报告包括各所述焊盘图形的标识信息、所属网表网络组的信息、所属父网络组的信息、及检查结果。
例如，如表1所示，
表1
Figure PCTCN2019082645-appb-000001
表1按网络名1为主要关键字排序，该“网络名1”即上文中介绍的“网表网络组”的名称；网络名2内按名字出现次数多的排在前面，该“网络名2”即上文中介绍的“父网络组”的名称。于表1中，“A18289723”对应的“NET1”数量最多，所以“NET1”排在前面，而“NET3”排在后面；“VCC”对应的“NET6”数量最多，所以“NET6”排在前面，而“NET3”、“NET22”排在后面。
对于PCB数据图形编号为“121”、“12”、“143”、“154”、“105”、“176”的焊盘图形而言，它们在连通性分析前都在“A18289723”组中，而在连通性分析后，前5个在“NET1”组中而最后1个在“NET3”组中，对于前5个焊盘图形来说，它们的前后网络关系没有发生变化，而对于最后1个焊盘图形来说，它的前后网络关系不再保持一致，可见，“A18289723”组存在开路问题，且焊盘图形“176”可能是存在开路问题的具体位置。
对于PCB数据图形编号为“187”、“98”、“209”、“220”、“231”的焊盘图形而言，它们在连通性分析前都在“GND”组中，在连通性分析后都在“NET3”组中，它们的前后网络关系没有发生变化，可见，“GND”组不存在开短路问题。
对于PCB数据图形编号为“253”、“264”、“242”、“2333”的焊盘图形而言，它们在连通性分析前都在“VCC”组中，而在连通性分析后，前2个在“NET6”组中，而“242”在“NET3”组中、“2333”在“NET22”组中，对于前2个焊盘图形来说，它们的前后网络关系没有发生变化，而对于后2个焊盘图形来说，它的前后网络关系不再保持一致，可见，“VCC”组存在开路问题，且焊盘图形“242”、“2333”可能是存在开路问题的具体位置。
又例如，如表2所示，
表2
Figure PCTCN2019082645-appb-000002
表2按网络名2为主要关键字排序，该“网络名2”即上文中介绍的“父网络组”的名称；网络名1内按名字出现次数多的排在前面，该“网络名1”即上文中介绍的“网表网络组”的名称。于表2中，“NET3”对应的“GND”数量最多，所以“GND”排在前面，而“A18289723”、“VCC”排在后面。
需要说明的是，PCB数据图形编号是焊盘图形在“父网络组”中的身份标识，而网表图形编号是该焊盘图形在“网表网络组”中的身份标识。也就是说，PCB数据图形编号为“187”的焊盘图形实际上也就是指网表图形编号“7”的焊盘图形，以此类推。在表1的分析中，默认以“PCB数据图形编号”来识别焊盘图形，当然，其与以“网表图形编号”来识别焊盘图形的方式是等同的。以下，利用焊盘图形的“网表图形编号”详细阐述短路的判断过程。
对于网表图形编号为“6”～“12”的焊盘图形而言，“7”～“11”在连通性分析前都在“GND”组中，“6”在“A18289723”组中，“12”在“VCC”组中，而在连通性分析后，它们都在“NET3”组中。对于焊盘图形“7”～“11”而言，它们的前后网络关系没有发生变化，而对于焊盘图形“6”和“12”而言，它的前后网络关系不再保持一致，可见，“NET3”组存在短路问题，且焊盘图形“6”、“12”可能是存在短路问题的具体位置。
对于网表图形编号为“1”～“5”的焊盘图形而言，它们在连通性分析前都在“A18289723”组中，在连通性分析后都在“NET1”组中，它们的前后网络关系没有发生变化，可见，“NET1”组不存在短路问题。
对于网表图形编号为“13”～“14”的焊盘图形而言，它们在连通性分析前都在“VCC” 组中，而在连通性分析后都在“NET6”组中，它们的前后网络关系没有发生变化，可见，“NET6”组不存在短路问题。
在一实施例中，进一步地，所述IPC网表数据包含各所述焊盘图形的坐标。在步骤S7判断出某网表网络组存在开短路问题时，将输出的如图5所示的IPC网表数据的图像与如图4所示的图像加以重叠，以从所述IPC网表数据中查找存在开短路问题的焊盘图形的坐标，并在所述IPC网表数据的图像上将这些坐标的位置突出显示，从而方便查看造成开短路的原因。
需要说明的是，本发明所述的PCB设计版图的开短路检查方法的保护范围不限于本实施例列举的步骤执行顺序，凡是根据本发明的原理所做的现有技术的步骤增减、步骤替换所实现的方案都包括在本发明的保护范围内。
实现上述各方法实施例的全部或部分步骤可以通过计算机程序相关的硬件来完成。基于这样的理解，本发明还提供一种计算机程序产品，包括一个或多个计算机指令。所述计算机指令可以存储在计算机可读存储介质中。所述计算机可读存储介质可以是计算机能够存储的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质(如：软盘、硬盘、磁带)、光介质(如：DVD)、或者半导体介质(如：固态硬盘Solid State Disk(SSD))等。
参阅图6，本实施例提供一种PCB设计版图的开短路检查系统600，作为一款软件搭载于电子设备中，以在运行时执行前述方法实施例所述的PCB设计版图的开短路检查方法。由于本系统实施例的技术原理与前述方法实施例的技术原理相似，因而不再对同样的技术细节做重复性赘述。
本实施例的PCB设计版图的开短路检查系统600具体包括：PCB数据读取模块601、连通性分析模块602、IPC网表数据读取模块603、开短路检查模块604，进一步还包括：检查报告生成模块。PCB数据读取模块601用于执行前述方法实施例介绍的步骤S1，连通性分析模块602用于执行前述方法实施例介绍的步骤S2～S3。IPC网表数据读取模块603用于执行前述方法实施例介绍的步骤S4，开短路检查模块604用于执行前述方法实施例介绍的步骤S5～S7。检查报告生成模块用于生成检查报告。
本领域技术人员应当理解，图6实施例中的各个模块的划分仅仅是一种逻辑功能的划分，实际实现时可以全部或部分集成到一个或多个物理实体上。且这些模块可以全部以软件通过处理元件调用的形式实现，也可以全部以硬件的形式实现，还可以部分模块通过处理元件调用软件的形式实现，部分模块通过硬件的形式实现。例如，连通性分析模块602可以为单独 设立的处理元件，也可以集成在某一个芯片中实现，此外，也可以以程序代码的形式存储于存储器中，由某一个处理元件调用并执行连通性分析模块602的功能。其它模块的实现与之类似。这里所述的处理元件可以是一种集成电路，具有信号的处理能力。在实现过程中，上述方法的各步骤或以上各个模块可以通过处理器元件中的硬件的集成逻辑电路或者软件形式的指令完成。
参阅图7，本实施例提供一种电子设备，电子设备可以是台式机、便携式电脑、智能手机等设备。详细的，电子设备至少包括通过总线71连接的：存储器72、处理器73，其中，存储器72用于存储计算机程序，处理器73用于执行存储器72存储的计算机程序，以执行前述方法实施例中的全部或部分步骤。
上述提到的系统总线可以是外设部件互连标准(Peripheral Pomponent Interconnect，简称PCI)总线或扩展工业标准结构(Extended Industry Standard Architecture，简称EISA)总线等。该系统总线可以分为地址总线、数据总线、控制总线等。为便于表示，图中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。通信接口用于实现数据库访问装置与其他设备(例如客户端、读写库和只读库)之间的通信。存储器可能包含随机存取存储器(Random Access Memory，简称RAM)，也可能还包括非易失性存储器(non-volatile memory)，例如至少一个磁盘存储器。
上述的处理器可以是通用处理器，包括中央处理器(Central Processing Unit，简称CPU)、网络处理器(Network Processor，简称NP)等；还可以是数字信号处理器(Digital Signal Processing，简称DSP)、专用集成电路(Application Specific Integrated Circuit，简称ASIC)、现场可编程门阵列(Field－Programmable Gate Array，简称FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。
综上所述，本发明的PCB设计版图的开短路检查方法、检测系统及电子设备，有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种PCB设计版图的开短路检查方法，其特征在于，包括：
    读取待检查的PCB设计版图的PCB数据，据以输出所述PCB设计版图所包含的各PCB层的图像；
    对各所述PCB层的图像分别进行第一连通性分析，以将同层中接触在一起的各焊盘图形归为同一子网络组；
    对所述PCB设计版图的钻孔层的各电镀孔分别进行第二连通性分析，以将各所述电镀孔贯穿不同PCB层而连接的各焊盘图形所在的各所述子网络组归为同一父网络组；
    读取所述PCB设计版图的IPC网表数据，据以获得各所述焊盘图形所在的网表网络组；
    判断各所述焊盘图形的网表网络关系与经所述第二连通性分析之后的网络关系是否一致；若一致，则判定所述PCB设计版图不存在开短路问题；反之，则判定所述PCB设计版图存在开短路问题。
  2. 根据权利要求1所述的方法，其特征在于，根据各所述焊盘图形的网表网络关系与经所述第二连通性分析之后的网络关系判断所述PCB设计版图是否存在开短路问题的步骤，具体包括：
    若属于同一所述网表网络组的各焊盘图形不属于同一所述父网络组，则判定所述PCB设计版图存在开路问题，且开路问题出现在该网表网络组；
    若属于同一所述父网络组的各焊盘图形不属于同一所述网表网络组，则判定所述PCB设计版图存在短路问题，且短路问题出现在该父网络组；
    若属于同一网表网络组的各焊盘图形也属于同一父网络组，或者，若属于同一父网络组的各焊盘图形也属于同一网表网络组，则判定所述PCB设计版图不存在开短路问题。
  3. 根据权利要求2所述的方法，其特征在于，还包括：
    输出所述IPC网表数据的图像；所述IPC网表数据包含各所述焊盘图形的坐标；
    从所述IPC网表数据中查找存在开短路问题的网络组所包含的焊盘图形的坐标；
    在所述IPC网表数据的图像上对查找得到的坐标位置做突出显示。
  4. 根据权利要求2所述的方法，其特征在于，还包括：生成检查报告；所述检查报告包括各所述焊盘图形的标识信息、所属网表网络组的信息、所属父网络组的信息、及检查结果。
  5. 一种PCB设计版图的开短路检查系统，其特征在于，包括：
    PCB数据读取模块，用于读取待检查的PCB设计版图的PCB数据，据以输出所述 PCB设计版图所包含的各PCB层的图像；
    连通性分析模块，用于对各所述PCB层的图像分别进行第一连通性分析，以将同层中接触在一起的各焊盘图形归为同一子网络组；以及用于对所述PCB设计版图的钻孔层的各电镀孔分别进行第二连通性分析，以将各所述电镀孔贯穿不同PCB层而连接的各焊盘图形所在的各所述子网络组归为同一父网络组；
    IPC网表数据读取模块，用于读取所述PCB设计版图的IPC网表数据，据以获得各所述焊盘图形所在的网表网络组；
    开短路检查模块，用于判断各所述焊盘图形的网表网络关系与经所述第二连通性分析之后的网络关系是否一致；若一致，则判定所述PCB设计版图不存在开短路问题；反之，则判定所述PCB设计版图存在开短路问题。
  6. 根据权利要求5所述的系统，其特征在于，所述开短路检查模块根据各所述焊盘图形的网表网络关系与经所述第二连通性分析之后的网络关系判断所述PCB设计版图是否存在开短路问题的实现方式包括：
    若属于同一所述网表网络组的各焊盘图形不属于同一所述父网络组，则判定所述PCB设计版图存在开路问题，且开路问题出现在该网表网络组；
    若属于同一所述父网络组的各焊盘图形不属于同一所述网表网络组，则判定所述PCB设计版图存在短路问题，且短路问题出现在该父网络组；
    若属于同一网表网络组的各焊盘图形也属于同一父网络组，或者，若属于同一父网络组的各焊盘图形也属于同一网表网络组，则判定所述PCB设计版图不存在开短路问题。
  7. 根据权利要求6所述的系统，其特征在于，所述IPC网表数据读取模块还用于：输出所述IPC网表数据的图像；其中，所述IPC网表数据包含各所述焊盘图形的坐标；所述系统还包括：突出标记模块，用于：
    从所述IPC网表数据中查找存在开短路问题的网络组所包含的焊盘图形的坐标；
    在所述IPC网表数据的图像上对查找得到的坐标位置做突出显示。
  8. 根据权利要求6所述的系统，其特征在于，还包括：检查报告生成模块，用于生成检查报告；所述检查报告包括各所述焊盘图形的标识信息、所属网表网络组的信息、所属父网络组的信息、及检查结果。
  9. 一种存储介质，其中存储有计算机程序，其特征在于，所述计算机程序被处理器加载执行时，实现如权利要求1至4中任一所述的PCB设计版图的开短路检查方法。
  10. 一种电子设备，其特征在于，包括：处理器及存储器；其中，
    所述存储器用于存储计算机程序；
    所述处理器用于加载执行所述计算机程序，以使所述电子设备执行如权利要求1至4中任一所述的PCB设计版图的开短路检查方法。
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