WO2020107887A1 - 晶体硅太阳能电池及其制备方法、光伏组件 - Google Patents

晶体硅太阳能电池及其制备方法、光伏组件 Download PDF

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Publication number
WO2020107887A1
WO2020107887A1 PCT/CN2019/093529 CN2019093529W WO2020107887A1 WO 2020107887 A1 WO2020107887 A1 WO 2020107887A1 CN 2019093529 W CN2019093529 W CN 2019093529W WO 2020107887 A1 WO2020107887 A1 WO 2020107887A1
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Prior art keywords
layer
crystalline silicon
silicon substrate
carrier collection
passivation layer
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PCT/CN2019/093529
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English (en)
French (fr)
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尹海鹏
单伟
汤坤
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Jingao Solar Co Ltd
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Ja Solar Co Ltd
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Priority to JP2021500331A priority Critical patent/JP7068541B2/ja
Priority to KR1020217015076A priority patent/KR20210062096A/ko
Priority to EP19890987.1A priority patent/EP3886181B1/en
Priority to CN201980078416.6A priority patent/CN113330583B/zh
Priority to ES19890987T priority patent/ES3057756T3/es
Priority to MYPI2021002733A priority patent/MY200704A/en
Priority to US17/296,492 priority patent/US11961930B2/en
Priority to AU2019390365A priority patent/AU2019390365B2/en
Publication of WO2020107887A1 publication Critical patent/WO2020107887A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/30—Coatings
    • H10F77/306—Coatings for devices having potential barriers
    • H10F77/311—Coatings for devices having potential barriers for photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
    • H10F10/146—Back-junction photovoltaic cells, e.g. having interdigitated base-emitter regions on the back side
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16—Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H10F10/166—Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/121—The active layers comprising only Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/16—Material structures, e.g. crystalline structures, film structures or crystal plane orientations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present disclosure relates to the technical field of solar cells, in particular to a crystalline silicon solar cell, a preparation method thereof, and a photovoltaic component.
  • Photovoltaic power generation is a power generation method that uses large-area P-N junction diodes to convert solar energy into electrical energy. It is a clean, sustainable and relatively cost-effective power generation method.
  • the aforementioned P-N junction diode is called a solar cell.
  • the crystalline silicon solar cell is a solar cell that is widely used.
  • the photoelectric conversion performance of a crystalline silicon solar cell depends on its internal minority carrier concentration. The annihilation of minority carriers will cause the loss of voltage and current of the crystalline silicon solar cell, thereby reducing the photoelectric conversion efficiency of the crystalline silicon solar cell.
  • For crystalline silicon solar cells there are defects on the surface of the crystalline silicon substrate, which is a serious recombination center.
  • a passivation structure needs to be provided between the surface of the crystalline silicon substrate and the electrode to passivate the surface of the crystalline silicon substrate to reduce the recombination rate of minority carriers on the surface of the crystalline silicon substrate to improve the photoelectric conversion efficiency of the crystalline silicon solar cell.
  • the related art provides a crystalline silicon solar cell with a tunnel oxidation passivation contact structure (as shown in FIG. 1), which includes a crystalline silicon substrate 1'and a passivation tunneling layer 2'provided on the crystalline silicon substrate 1' , A carrier collection layer 3'provided on the passivation tunneling layer 2', and an electrode 5'forming ohmic contact with the carrier collection layer 3'.
  • the crystalline silicon solar cell of this structure can effectively solve the passivation problem between the surface of the crystalline silicon substrate 1'and the electrode 5'.
  • the passivation tunneling layer cannot achieve effective carrier transport, which results in higher series resistance of the crystalline silicon solar cell and affects the photoelectric conversion efficiency of the crystalline silicon solar cell.
  • the embodiments of the present disclosure provide a crystalline silicon solar cell, a method for manufacturing the same, and a photovoltaic module, which can solve the above problems of high series resistance of the crystalline silicon solar cell and unsatisfactory photoelectric conversion efficiency.
  • an embodiment of the present disclosure provides a crystalline silicon solar cell, including:
  • a passivation layer provided with through holes on the crystalline silicon substrate
  • a carrier collection layer provided on the passivation layer, and,
  • Electrodes in contact with the carrier collection layer are Electrodes in contact with the carrier collection layer
  • the carrier collection layer is in contact with the crystalline silicon substrate through the through hole in the passivation layer.
  • the cross-sectional shape of the through hole is linear, circular, or polygonal.
  • a plurality of through holes are provided on the passivation layer.
  • the electrode has a portion corresponding to the through hole on the passivation layer.
  • the passivation layer is an oxide layer.
  • the thickness of the passivation layer is 0.3 nm to 100 nm.
  • the carrier collection layer is a doped silicon layer.
  • the carrier collection layer is a doped polysilicon layer or a doped amorphous silicon layer.
  • the thickness of the carrier collection layer is 30 nm to 500 nm.
  • the crystalline silicon solar cell further includes: an anti-reflection layer disposed on the carrier collection layer; the electrode passes through the anti-reflection layer and contacts the carrier collection layer.
  • an embodiment of the present disclosure provides another crystalline silicon solar cell, including:
  • a carrier collection layer provided on the passivation layer,
  • the first electrode in contact with the carrier collection layer
  • a doped layer provided on the other side of the crystalline silicon substrate, and,
  • the carrier collection layer is in contact with the crystalline silicon substrate through the through hole in the passivation layer;
  • the conductivity type of the carrier collection layer is opposite to the conductivity type of the doped layer.
  • the cross-sectional shape of the through hole is linear, circular, or polygonal.
  • a plurality of through holes are provided on the passivation layer.
  • the electrode has a portion opposite to the through hole on the passivation layer.
  • the passivation layer is an oxide layer.
  • the thickness of the passivation layer is 0.3 nm to 100 nm.
  • the carrier collection layer is a doped silicon layer.
  • the carrier collection layer is a doped polysilicon layer or a doped amorphous silicon layer.
  • the thickness of the carrier collection layer is 30 nm to 500 nm.
  • the crystalline silicon solar cell further includes: a first anti-reflection layer disposed on the carrier collection layer, and/or a second anti-reflection layer disposed on the doped layer; the A first electrode contacts the carrier collection layer through the first anti-reflection layer, and the second electrode contacts the doped layer through the second anti-reflection layer.
  • embodiments of the present disclosure provide yet another crystalline silicon solar cell, including:
  • a first carrier collection layer provided on the first passivation layer
  • a second carrier collection layer provided on the second passivation layer, and,
  • a second electrode in contact with the second carrier collection layer
  • the first carrier collection layer is in contact with the crystalline silicon substrate through the through hole on the first passivation layer; the second carrier collection layer passes through the The through hole is in contact with the crystalline silicon substrate;
  • the first carrier collection layer and the second carrier collection layer have opposite conductivity types.
  • the cross-sectional shape of the through hole is linear, circular, or polygonal.
  • both the first passivation layer and the second passivation layer are provided with a plurality of through holes.
  • the first electrode has a portion opposite to the through hole on the first passivation layer; the second electrode has a portion opposite to the through hole on the second passivation layer.
  • the first passivation layer is an oxide layer
  • the second passivation layer is an oxide layer
  • the thickness of the first passivation layer is 0.3 nm to 100 nm
  • the thickness of the second passivation layer is 0.3 nm to 100 nm.
  • the first carrier collection layer is a doped silicon layer
  • the second carrier collection layer is a doped silicon layer
  • the first carrier collection layer is a doped polysilicon layer or a doped amorphous silicon layer
  • the second carrier collection layer is a doped polysilicon layer or a doped amorphous silicon layer.
  • the thickness of the first carrier collection layer is 30 nanometers to 500 nanometers
  • the thickness of the second carrier collection layer is 30 nanometers to 500 nanometers
  • the crystalline silicon solar cell further includes: a first anti-reflection layer disposed on the first carrier collection layer, and/or a second anti-reflection layer disposed on the second carrier collection layer Anti-reflection layer; the first electrode passes through the first anti-reflection layer and contacts the first carrier collection layer, the second electrode passes through the second anti-reflection layer and the second carrier The collector layer contacts.
  • embodiments of the present disclosure provide yet another crystalline silicon solar cell, including:
  • a carrier collection layer provided on the passivation layer and having first and second regions of opposite conductivity types,
  • a second electrode in contact with the second region of the carrier collection layer, and,
  • a doped layer provided on the other side of the crystalline silicon substrate
  • the carrier collection layer is in contact with the crystalline silicon substrate through the through hole in the passivation layer;
  • the conductivity type of the doped layer is the same as the conductivity type of the crystalline silicon substrate.
  • the carrier collection layer has a plurality of the first regions and a plurality of the second regions, and the plurality of first regions and the plurality of second regions are distributed alternately.
  • the cross-sectional shape of the through hole is linear, circular, or polygonal.
  • a plurality of through holes are provided on the passivation layer.
  • the first electrode has a portion opposite to the through hole on the passivation layer
  • the second electrode has a portion opposite to the through hole on the passivation layer
  • the passivation layer is an oxide layer.
  • the thickness of the passivation layer is 0.3 nm to 100 nm.
  • the carrier collection layer is a doped silicon layer.
  • the carrier collection layer is a doped polysilicon layer or a doped amorphous silicon layer.
  • the thickness of the carrier collection layer is 30 nm to 500 nm.
  • the crystalline silicon solar cell further includes: a first anti-reflection layer disposed on the carrier collection layer, and/or a second anti-reflection layer disposed on the doped layer; the The first electrode passes through the first anti-reflection layer and contacts the first region of the carrier collection layer, and the second electrode passes through the second anti-reflection layer and the first region of the carrier collection layer Two area contacts.
  • an embodiment of the present disclosure provides a method for preparing a crystalline silicon solar cell, including:
  • An electrode in contact with the carrier collection layer is formed.
  • the preparation method further includes: forming an anti-reflection layer on the carrier collection layer.
  • the forming a passivation layer with a through hole on the crystalline silicon substrate includes:
  • a through hole is opened in the passivation layer.
  • the forming of a carrier collection layer on the passivation layer and on a portion of the crystalline silicon substrate opposite to the through hole of the passivation layer includes:
  • an embodiment of the present disclosure provides another method for preparing a crystalline silicon solar cell, including:
  • a second electrode in contact with the doped layer is formed.
  • the preparation method further includes:
  • a second anti-reflection layer is formed on the doped layer.
  • the forming a passivation layer with a through hole on the crystalline silicon substrate includes:
  • the through hole is opened on the passivation layer.
  • the forming of a carrier collection layer on the passivation layer and on a portion of the crystalline silicon substrate opposite to the through hole of the passivation layer includes:
  • embodiments of the present disclosure provide yet another method for preparing a crystalline silicon solar cell, including:
  • a second electrode in contact with the second carrier collection layer is formed.
  • the preparation method further includes:
  • a second anti-reflection layer is formed on the second carrier collection layer.
  • the forming a first passivation layer with a through hole on the crystalline silicon substrate includes:
  • the forming a second passivation layer with a through hole on the crystalline silicon substrate includes:
  • a through hole is opened in the second passivation layer.
  • the forming of a first carrier collection layer on the first passivation layer and a portion of the crystalline silicon substrate opposite to the through hole of the first passivation layer includes:
  • the forming of a second carrier collection layer on the second passivation layer and a portion of the crystalline silicon substrate opposite to the through hole of the second passivation layer includes:
  • embodiments of the present disclosure provide yet another method for preparing a crystalline silicon solar cell, including:
  • a second electrode in contact with the second region of the carrier collection layer is formed.
  • the preparation method further includes:
  • a second anti-reflection layer is formed on the doped layer.
  • the forming a passivation layer with a through hole on the crystalline silicon substrate includes:
  • the through hole is opened on the passivation layer.
  • a carrier collection layer having a first region and a second region of opposite conductivity types is formed on the passivation layer and a portion of the crystalline silicon substrate opposite to the through hole of the passivation layer, include:
  • an embodiment of the present disclosure provides a photovoltaic module, including: a cover plate, a first encapsulating adhesive film, a battery string, a second encapsulating adhesive film, and a back sheet disposed in sequence, the battery string includes a plurality of solar cells
  • the solar cell is the aforementioned crystalline silicon solar cell.
  • a through hole is formed in the passivation layer, and the carrier collection layer is in contact with the crystalline silicon substrate through the through hole in the passivation layer, on the basis of ensuring good surface passivation
  • the carrier can be collected by the electrode through the interface of the crystalline silicon substrate and the carrier collection layer to achieve more effective carrier transmission, reduce the series resistance of the crystalline silicon solar cell, and increase the fill factor of the crystalline silicon solar cell , Thereby improving the photoelectric conversion efficiency of crystalline silicon solar cells.
  • FIG. 1 is a schematic structural diagram of a crystalline silicon solar cell provided by the related art
  • FIG. 2 is a schematic structural diagram of a crystalline silicon solar cell provided by an embodiment of the present disclosure
  • 3a is a schematic structural diagram of a passivation layer through hole in a crystalline silicon solar cell provided by an embodiment of the present disclosure
  • 3b is a schematic structural diagram of another passivation layer through hole in a crystalline silicon solar cell provided by an embodiment of the present disclosure
  • FIG. 4a is a schematic diagram of a position relationship between a through hole and an electrode in a crystalline silicon solar cell provided by an embodiment of the present disclosure
  • 4b is a schematic diagram of another through hole and electrode position relationship in a crystalline silicon solar cell provided by an embodiment of the present disclosure
  • FIG. 4c is a schematic diagram of another through hole and electrode position relationship in a crystalline silicon solar cell provided by an embodiment of the present disclosure
  • 4d is a schematic diagram showing the relationship between another through hole and the electrode position in the crystalline silicon solar cell provided by the embodiment of the present disclosure
  • 4e is a schematic diagram of the relationship between another through hole and the electrode position in the crystalline silicon solar cell provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of another crystalline silicon solar cell provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of yet another crystalline silicon solar cell provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of yet another crystalline silicon solar cell provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of yet another crystalline silicon solar cell provided by an embodiment of the present disclosure.
  • 9a-9g are schematic diagrams of the preparation method of the crystalline silicon solar cell shown in FIG. 5;
  • 10a to 10g are schematic diagrams of the preparation method of the crystalline silicon solar cell shown in FIG. 6;
  • FIG. 7 are schematic diagrams of the method for preparing the crystalline silicon solar cell shown in FIG. 7;
  • 12a-12b are schematic diagrams of the method for preparing the crystalline silicon solar cell shown in FIG. 8.
  • Tunneling passivation layer for crystalline silicon solar cells provided by related technologies
  • Improving the photoelectric conversion efficiency of crystalline silicon solar cells is an effective way to increase the output power of photovoltaic power generation and reduce the cost of electricity.
  • one of the important factors limiting the photoelectric conversion efficiency of monolithic crystalline silicon solar cells is the annihilation of minority carriers in crystalline silicon solar cells.
  • the annihilation of minority carriers will cause the loss of voltage and current in crystalline silicon solar cells, thereby reducing the photoelectric conversion efficiency of crystalline silicon solar cells.
  • Setting a passivation structure on the surface of the crystalline silicon substrate can reduce the recombination rate of minority carriers on the surface of the crystalline silicon substrate, which is beneficial to improve the photoelectric conversion efficiency of the crystalline silicon solar cell.
  • the embodiments of the present disclosure optimize and improve the structure of the crystalline silicon solar cell, while ensuring the passivation effect, and improving the carrier transmission capacity, thereby improving the photoelectric conversion efficiency of the crystalline silicon solar cell.
  • FIG. 2 is a schematic structural diagram of a crystalline silicon solar cell provided by an embodiment of the present disclosure.
  • the crystalline silicon solar cell includes: a crystalline silicon substrate 1 provided on the crystalline silicon substrate 1 with a through hole X The passivation layer 2, the carrier collection layer 3 provided on the passivation layer 2, and the electrode 5 in contact with the carrier collection layer 3.
  • the through hole X refers to a hole penetrating the thickness direction of the passivation layer 2, and the carrier collection layer 3 is in contact with the crystalline silicon substrate 1 through the through hole X in the passivation layer 2.
  • the passivation layer 2 and the carrier collection layer 3 provided on the crystalline silicon substrate 1 work together as a passivation function to ensure that the crystalline silicon solar cell has a higher open circuit voltage and short circuit Current, on this basis, the passivation layer 2 is provided with a through hole X, the carrier collection layer 3 is in contact with the crystalline silicon substrate 1 through the through hole X in the passivation layer 2, the carrier can pass through the crystalline silicon
  • the interface between the substrate 1 and the carrier collection layer 3 is collected by the electrode 5 to realize more effective carrier transmission, reduce the series resistance of the crystalline silicon solar cell, increase the fill factor of the crystalline silicon solar cell, and thereby improve the crystalline silicon solar cell Photoelectric conversion efficiency.
  • the shape of the through hole X on the passivation layer 2 is not strictly limited.
  • the cross section of the through hole X (the cross section refers to the The shape of the crystalline silicon substrate 1 in the surface direction) can be linear, circular (as shown in FIG. 3a), elliptical or polygonal.
  • the linear hole can be linear (as shown in Figure 3b), can also be curvilinear, polyline, etc.;
  • the polygonal hole can be triangular, quadrilateral, pentagonal, hexagonal, etc., can be an ordinary polygon, or It can be a regular polygon.
  • a plurality of through holes X on the passivation layer 2 may be provided, and the plurality of through holes X may be arranged according to a certain rule. For example, it may be arranged in a row ⁇ b column (a ⁇ 1, b ⁇ 1, where a and b are not 1 at the same time).
  • the diameter of the through hole X may be 0.01 mm to 1 mm, for example, 0.01 mm, 0.02 mm, 0.03 Mm, 0.04 mm, 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm, 0.1 mm, 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1 mm, etc. .
  • the distance between two adjacent through holes X in the same column (the size indicated by P1 in FIG.
  • the distance between the edges of the two through holes X) may be 0.3 mm to 3 mm, for example, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1 mm, 1.1 mm, 1.2 mm, 1.3 mm, 1.4 mm, 1.5 mm, 1.6 mm, 1.7 mm, 1.9 mm, 2 mm, 2.1 mm, 2.2 mm , 2.3 mm, 2.4 mm, 2.5 mm, 2.6 mm, 2.7 mm, 2.8 mm, 2.9 mm, 3 mm, etc.; the distance between two adjacent through holes X in the same row (the size indicated by P2 in Figure 3a, The distance between the edges of the two through holes X) may be 0.3 mm to 3 mm, such as 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1 mm,
  • All the through holes X may have the same shape, or part of the through holes X may have the same shape.
  • the ratio of the total opening area of all the through holes X to the area of the passivation layer 2 may be: 0.1% to 5%, for example, 0.1%, 0.2%, 0.4%, 0.5%, 0.6%, 0.8% , 1.0%, 1.2%, 1.4%, 1.5%, 1.6%, 1.8%, 2.0%, 2.2%, 2.4%, 2.5%, 2.6%, 2.8%, 3.0%, 3.2%, 3.4%, 3.5%, 3.6 %, 3.8%, 4%, 4.2%, 4.4%, 4.5%, 4.6%, 4.8%, 5.0%, etc.
  • the electrode 5 may have a portion corresponding to the through hole X on the passivation layer 2.
  • the "correspondence” mentioned here means that on a plane parallel to the surface of the crystalline silicon substrate, the projection of the electrode 5 and the projection of the through hole X have a portion that coincides.
  • the electrode 5 may include a plurality of sub-regions (for example, each gate line of the electrode 5 of the gate line structure).
  • Each sub-region may have a part corresponding to the via X (for example, each gate line has a part corresponding to the via X); or a part of the sub-region may have a part corresponding to the via X, and another part of the sub-region may not have A portion corresponding to the passage X (for example, a portion of the gate line has a portion corresponding to the via X, and another portion of the gate line does not have an area corresponding to the via X).
  • the through holes X are circular and arranged in multiple rows, the width of the gate line is substantially the same as the diameter of the through hole X, and the center line of the gate line is the same as the row of through holes X
  • the centerlines of the two basically coincide.
  • the through holes X are circular and arranged in multiple rows, the width of the gate line is smaller than the diameter of the through hole X, and the center line of the gate line is The center lines basically coincide.
  • the through holes X are circular and arranged in multiple rows, the width of the gate line is greater than the diameter of the through hole X, and the center line of the gate line is The center lines basically coincide.
  • the through holes X are circular and arranged in multiple rows, the width of the gate line is substantially the same as the diameter of the through hole X, and the center line of the gate line is the same as the row of through holes
  • the center line of X is parallel but not coincident, and there is a certain distance between the two.
  • the through hole X is linear, the center line of the gate line does not coincide with the center line of the linear through hole, and there is a certain angle between the two.
  • the shape of the through hole X can be set to the same shape as the electrode 5, so that the projection of the electrode 5 completely coincides with the projection of the through hole X on a plane parallel to the surface of the crystalline silicon substrate.
  • the electrode 5 may not have a portion corresponding to the through hole X at all.
  • the crystalline silicon substrate 1 may be single crystal silicon or polycrystalline silicon.
  • the conductivity type of the crystalline silicon substrate 1 may be P-type or N-type.
  • the resistivity of the crystalline silicon substrate 1 may be 0.5 ⁇ cm to 15 ⁇ cm, such as 0.5 ⁇ cm, 1.0 ⁇ cm, 1.5 ⁇ cm, 2.0 ⁇ cm, 2.5 ⁇ cm, 3.0 ⁇ cm, 3.5 ⁇ cm, 4.0 ⁇ cm, 4.5 ⁇ cm, 5 ⁇ cm, 5.5 ⁇ cm, 6 ⁇ cm, 6.5 ⁇ cm, 7.0 ⁇ cm, 7.5 ⁇ cm, 8.0 ⁇ cm, 8.5 ⁇ cm, 9.0 ⁇ cm, 9.5 ⁇ cm, 10.0 ⁇ cm, 10.5 ⁇ cm, 11.0 ⁇ cm, 11.5 ⁇ cm, 12.0 ⁇ cm, 12.5 ⁇ cm, 13.0 ⁇ cm, 13.5 ⁇ cm cm, 14.0 ⁇ cm, 14.5 ⁇ cm, 15.0 ⁇ cm, etc., preferably
  • the cross-sectional shape of the crystalline silicon substrate 1 may be a square, or a square with four corners rounded, or other shapes may be adopted as needed.
  • the thickness of the crystalline silicon substrate 1 may be 50 microns to 500 microns, such as 50 microns, 60 microns, 70 microns, 80 microns, 90 microns, 100 microns, 110 microns, 120 microns, 130 microns, 140 microns, 150 microns, 160 microns , 170 microns, 180 microns, 190 microns, 200 microns, 210 microns, 220 microns, 230 microns, 240 microns, 250 microns, 260 microns, 270 microns, 280 microns, 290 microns, 300 microns, 310 microns, 320 microns, 330 Micron, 340 microns, 350 microns, 360 microns, 370 microns, 380 microns, 390 microns
  • the passivation layer 2 may be an oxide layer, such as a silicon oxide (SiO x ) layer, a titanium oxide (TiO x ) layer, an aluminum oxide (AlO x ) layer, a tantalum oxide (TaO x ), a silicon oxynitride (SiN x O y ), etc., that is, the passivation layer 2 may be a single oxide layer alone, or may be a stacked structure of multiple oxide layers.
  • the oxide passivation layer can play the role of chemical passivation and field passivation at the same time.
  • the thickness of the passivation layer 2 may be from 0.3 nm to 100 nm, for example, 0.3 nm, 0.4 nm, 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, 1 nm, 2 nm, 3 nm, 4 nm, and 5 nm , 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 25 nm, 30 Nano, 31, 32, 33, 34, 35, 35, 36, 37, 38, 39, 40, 45, 50, 55, 60, 65, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, etc.
  • the passivation layer 2 in the crystalline silicon solar cell provided by the embodiments of the present disclosure may be thicker, thereby facilitating the preparation of the passivation layer 2.
  • the carrier collection layer 3 may be conductive, and the conductivity type of the carrier collection layer 3 may be the same as the conductivity type of the crystalline silicon substrate 1 or may be reversed.
  • the carrier collection layer mainly plays a role of field passivation.
  • the carrier collection layer 3 can serve as the emitter (ie, PN junction) of the crystalline silicon solar cell; when the carrier collection layer 3
  • the carrier collection layer 3 When the conductivity type is the same as that of crystalline silicon, the carrier collection layer 3 can serve as a surface field of the crystalline silicon solar cell.
  • the carrier collection layer 3 may be a doped silicon layer, specifically a doped polycrystalline silicon layer or a doped amorphous silicon layer.
  • the doping element in the doped silicon layer can be a P-type doping element, such as boron (B), aluminum (Al), gallium (Ga), indium (In) and other Group III elements; it can also be an N-type doping Elements such as phosphorus (P), arsenic (As), bismuth (Bi), antimony (Sb) and other Group V elements.
  • the thickness of the carrier collection layer 3 may be 30 nm to 500 nm, for example, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, 260 nm, 270 nm, 280 nm, 290 nm, 300 nm , 310 nm, 320 nm, 330 nm, 340 nm, 350 nm, 360 nm, 370 nm, 380 nm, 390 nm, 400 nm, 410 nm, 420 nm, 430 nm, 440 nm
  • the resistance value of the contact surface between the electrode 5 and the carrier collection layer 3 is much smaller than the resistance value of the carrier collection layer.
  • the electrode 5 is a metal electrode (such as a silver electrode)
  • the carrier collection layer 3 is a doped silicon layer
  • an ohmic contact should be formed between the two.
  • the end of the electrode 5 in contact with the carrier collection layer 3 may be located inside the carrier collection layer 3, further, when the electrode 5 has a portion corresponding to the through hole X of the passivation layer 2 , The portion of the electrode 5 corresponding to the through hole X may be located inside the through hole X, however, the end of the electrode 5 located inside the through hole X and the crystalline silicon substrate 1 should have a certain distance, that is, the electrode 5 is not connected to the crystalline silicon substrate 1 Contact.
  • the electrode 5 may be directly disposed on the carrier collection layer 3, or an anti-reflection layer 4 may be disposed on the carrier collection layer 3, and the electrode 5 passes through the anti-reflection layer 4 and the carrier collection layer 3 contacts.
  • the anti-reflection layer 4 may specifically be a single or multiple stacked structure of a silicon nitride (SiN x ) layer, a silicon oxide layer, a silicon oxynitride (SiO x N y ) layer, or an aluminum oxide layer.
  • the thickness of the anti-reflection layer 4 may be 30 nm to 300 nm, for example, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, 130 nm, 140 nm , 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, 260 nm, 270 nm, 280 nm, 290 nm, 300 nm, etc.
  • the refractive index of the anti-reflection layer 4 may be 1.2-2.8, such as 1.2, 1.25, 1.3, 1.35, 1.4, 1.45, 1.5, 1.55, 1.6, 1.65, 1.7, 1.75, 1.8, 1.85, 1.9, 1.95, 2.0, 2.05, 2.1, 2.15, 2.2, 2.25, 2.3, 2.35, 2.4, 2.45, 2.5, 2.55, 2.6, 2.65, 2.7, 2.75, 2.8, etc. It should be noted that while the anti-reflection layer 4 has an anti-reflection function, it can also play a certain passivation role.
  • the above-mentioned passivation layer 2 and carrier collection layer 3 may be provided only on one side of the crystalline silicon substrate 1, or the above-mentioned passivation layer 2 and Carrier collection layer 3.
  • the doped layer 6 may be provided on the other side of the crystalline silicon substrate 1.
  • the above-mentioned passivation layer 2 and carrier collection layer 3 are provided only on one side of the crystalline silicon substrate 1, and doping is provided on the other side of the crystalline silicon substrate 1
  • the hybrid layer 6 uses "first" and "second" to distinguish the structures with the same names on both sides of the crystalline silicon substrate 1 for convenience of description.
  • the crystalline silicon solar cell includes: a crystalline silicon substrate 1, a passivation layer 2 having a through hole X provided on one side of the crystalline silicon substrate 1, and a carrier collection layer 3 provided on the passivation layer 2, The first electrode 51 in contact with the carrier collection layer 3, the doped layer 6 provided on the other side of the crystalline silicon substrate 1, and the second electrode 52 in contact with the doped layer 6.
  • the carrier collection layer 3 is in contact with the crystalline silicon substrate 1 through the through hole X on the passivation layer 2; the conductivity type of the carrier collection layer 3 is opposite to that of the doped layer 6.
  • the doped layer 6 can be formed by directly doping a side surface of the crystalline silicon substrate 1 with a doping element.
  • the doping element in the doped layer 6 may be a P-type doping element, such as boron (B), aluminum (Al), gallium (Ga), indium (In) and other Group III elements; it may also be an N-type doping Elements such as phosphorus (P), arsenic (As), bismuth (Bi), antimony (Sb) and other Group V elements.
  • the conductivity type of the doped layer 6 and the conductivity type of the crystalline silicon substrate 1 may be the same or different.
  • the position and conductivity type of the carrier collection layer 3 and the doped layer 6 in the crystalline silicon solar cell may have the following four cases.
  • the doped layer 6 is located on the side of the front surface of the crystalline silicon substrate 1 (that is, the light-receiving surface of the crystalline silicon substrate 1, the same applies hereinafter) and the conductivity type is opposite to that of the crystalline silicon substrate 1, the passivation layer 2
  • the carrier collection layer 3 is located on the side of the back surface of the crystalline silicon substrate 1 (that is, the backlight surface of the crystalline silicon substrate 1, the same below) and the conductivity type of the carrier collection layer 3 is the same as that of the crystalline silicon substrate 1.
  • the doped layer 6 is P-type, and the carrier collection layer 3 is N-type; when the crystalline silicon substrate 1 is P-type silicon, the doped layer 6 is N Type, the carrier collection layer 3 is P-type.
  • the doped layer 6 serves as the emitter of the crystalline silicon solar cell
  • the carrier collection layer 3 serves as the back surface field of the crystalline silicon solar cell.
  • the doped layer 6 is located on the front surface side of the crystalline silicon substrate 1 and the conductivity type is the same as that of the crystalline silicon substrate 1, the passivation layer 2 and the carrier collection layer 3 are located on the crystalline silicon substrate 1
  • the conductivity type of the carrier collection layer 3 on the back surface side is opposite to that of the crystalline silicon substrate 1.
  • the doped layer 6 is N-type, and the carrier collection layer 3 is P-type; when the crystalline silicon substrate 1 is P-type silicon, the doped layer 6 is P Type, the carrier collection layer 3 is N-type.
  • the doped layer 6 serves as the front surface field of the crystalline silicon solar cell
  • the carrier collection layer 3 serves as the emitter of the crystalline silicon solar cell.
  • the passivation layer 2 and the carrier collection layer 3 are located on the front surface side of the crystalline silicon substrate 1 and the conductivity type of the carrier collection layer 3 is opposite to that of the crystalline silicon substrate 1, doped
  • the layer 6 is located on the back surface side of the crystalline silicon substrate 1 and has the same conductivity type as the crystalline silicon substrate 1.
  • the carrier collection layer 3 is P-type
  • the doped layer 6 is N-type
  • the carrier collection layer 3 It is N-type
  • the doped layer 6 is P-type
  • the carrier collection layer 3 serves as the emitter of the crystalline silicon solar cell
  • the doped layer 6 serves as the back surface field of the crystalline silicon solar cell.
  • the passivation layer 2 and the carrier collection layer 3 are located on the front surface side of the crystalline silicon substrate 1 and the conductivity type of the carrier collection layer 3 is the same as that of the crystalline silicon substrate 1, doped
  • the layer 6 is located on the back surface side of the crystalline silicon substrate 1 and has a conductivity type opposite to that of the crystalline silicon substrate 1.
  • the carrier collection layer 3 is N-type, and the doped layer 6 is P-type; when the crystalline silicon substrate 1 is P-type silicon, the carrier collection layer 3 It is P-type, and the doped layer 6 is N-type.
  • the carrier collection layer 3 serves as the front surface field of the crystalline silicon solar cell
  • the doped layer 6 serves as the emitter of the crystalline silicon solar cell.
  • a first anti-reflection layer 41 may be provided on the carrier collection layer 3 and/or a second anti-reflection layer 42 may be provided on the doped layer 6.
  • the first electrode 51 passes through the first anti-reflection layer 41 and carriers
  • the collecting layer 3 contacts, and the second electrode 52 contacts the doped layer 6 through the second anti-reflection layer 42.
  • the second anti-reflection layer 42 provided on the doped layer 6
  • the composition of the first anti-reflection layer 41 and the second anti-reflection layer 42 may be the same or different.
  • Both the first electrode 51 and the second electrode 52 may have a grid structure, forming a crystalline silicon solar cell that can transmit light on both sides and generate electricity on both sides.
  • the specific structures of the first electrode 51 and the second electrode 52 may be the same or different.
  • the above-mentioned passivation layer 2 and carrier collection layer 3 are provided on both sides of the crystalline silicon substrate 1.
  • first and second To distinguish the structures with the same names on both sides of the crystalline silicon substrate 1.
  • the crystalline silicon solar cell includes: a crystalline silicon substrate 1, a first passivation layer 21 having a through hole X provided on one side of the crystalline silicon substrate 1, and a first carrier provided on the first passivation layer 21
  • the carrier collection layer 31, the first electrode 51 in contact with the first carrier collection layer 31, is provided on the other side of the crystalline silicon substrate 1 with a second passivation layer 22 having a through hole X, and is provided on the second passivation
  • the first carrier collection layer 31 is in contact with the crystalline silicon substrate 1 through the through hole X in the first passivation layer 21; the second carrier collection layer 32 is in contact with the through hole X in the second passivation layer 22
  • the crystalline silicon substrate 1 is in contact; the first carrier collection layer 31 and the second carrier collection layer 32 have opposite conductivity types.
  • one of the first carrier collection layer 31 and the second carrier collection layer 32 has an N-type conductivity and the other has a P-type conductivity.
  • the conductivity type of the first carrier collection layer 31 is the same as the conductivity type of the crystalline silicon substrate 1
  • the conductivity type of the second carrier collection layer 32 is opposite to the conductivity type of the crystalline silicon substrate 1
  • the conductivity type of the second carrier collection layer 32 is the same as the conductivity type of the crystalline silicon substrate 1.
  • the carrier collection layer 3 opposite to the conductivity type of the crystalline silicon substrate 1 serves as the emitter of the crystalline silicon solar cell, and the carrier collection layer 3 having the same conductivity type as the crystalline silicon substrate 1 serves as the surface field of the crystalline silicon solar cell.
  • the carrier collection layer 3 opposite to the conductivity type of the crystalline silicon substrate 1 may be located on the front side of the crystalline silicon substrate 1, and accordingly, the carrier collection layer 3 having the same conductivity type as the crystalline silicon substrate 1 is located on the crystalline silicon substrate 1
  • the back surface side serves as the back surface field of the crystalline silicon solar cell; the carrier collection layer 3 opposite to the conductivity type of the crystalline silicon substrate 1 can also be located on the back surface side of the crystalline silicon substrate 1, correspondingly, to the crystalline silicon substrate 1
  • the carrier collection layer 3 of the same conductivity type is located on the front surface side of the crystalline silicon substrate 1 as a front surface field of the crystalline silicon solar cell.
  • the specific composition of the first passivation layer 21 and the second passivation layer 22 may be the same or different.
  • the shape, size, number, etc. of the through holes X on the first passivation layer 21 and the second passivation layer 22 may be the same or different.
  • the first anti-reflection layer 41 may be provided on the first carrier collection layer 31 and/or the second anti-reflection layer 42 may be provided on the second carrier collection layer 32, and the first electrode 51 passes through the first anti-reflection
  • the layer 41 is in contact with the first carrier collection layer 31, and the second electrode 52 is in contact with the second carrier collection layer 32 through the second anti-reflection layer 42.
  • the composition of the first anti-reflection layer 41 and the second anti-reflection layer 42 may be the same or different.
  • the passivation layer 2 and the carrier collection layer 3 are provided on one side of the crystalline silicon substrate 1, and the carrier collection layer 3 has areas with opposite conductivity types, and the electrode 5 It is provided on the side of the crystalline silicon substrate 1 where the carrier collection layer 3 is provided.
  • “first” and “second” are used to distinguish the structures with the same name on both sides of the crystalline silicon substrate 1.
  • the crystalline silicon solar cell includes: a crystalline silicon substrate 1, a passivation layer 2 having a through hole X provided on one side of the crystalline silicon substrate 1, and a second conductive layer provided on the passivation layer 2 and having an opposite conductivity type
  • the carrier collection layer 3 in a region 301 and the second region 302, the first electrode 51 in contact with the first region 301 of the carrier collection layer 3, and the third electrode in contact with the second region 302 of the carrier collection layer 3
  • the two electrodes 52 and the doped layer 6 provided on the other side of the crystalline silicon substrate 1.
  • the carrier collection layer 3 is in contact with the crystalline silicon substrate 1 through the through hole X on the passivation layer 2; the conductivity type of the doped layer 6 is the same as that of the crystalline silicon substrate 1.
  • one of the conductivity types of the first region 301 and the second region 302 of the carrier collection layer 3 is N-type, and the other is P-type.
  • the doped layer 6 can be formed by directly doping a side surface of the crystalline silicon substrate 1 with a doping element.
  • the doping element in the doped layer 6 may be a P-type doping element, such as boron (B), aluminum (Al), gallium (Ga), indium (In) and other Group III elements; it may also be an N-type doping Elements such as phosphorus (P), arsenic (As), bismuth (Bi), antimony (Sb) and other Group V elements.
  • one of the first region 301 and the second region 302 of the carrier collection layer 3 is the same as the conductivity type of the crystalline silicon substrate 1 and the other is opposite to the conductivity type of the crystalline silicon substrate 1.
  • the region of the carrier collection layer 3 opposite to the conductivity type of the crystalline silicon substrate 1 serves as the emitter of the crystalline silicon solar cell.
  • the carrier collection layer 3 may be provided on the front surface side of the crystalline silicon substrate 1 or on the back surface side of the crystalline silicon substrate 1. In an alternative embodiment, the carrier collection layer 3 is provided on the back surface side of the crystalline silicon substrate 1 and the doped layer 6 is provided on the front surface side of the crystalline silicon substrate 1. At this time, the first electrode 51 Both the second electrode 52 and the second electrode 52 are located on the back surface side of the crystalline silicon substrate 1. The front surface side of the crystalline silicon substrate 1 is not blocked by the electrode 5, which can increase the amount of incident light and help to improve the photoelectric conversion efficiency of the crystalline silicon solar cell.
  • the carrier collection layer 3 may have a plurality of first regions 301 and a plurality of second regions 302, and the plurality of first regions 301 and the plurality of second regions 302 are distributed alternately.
  • both the first region 301 and the second region 302 are rectangular regions, and the plurality of first regions 301 and the plurality of second regions 302 are arranged alternately along the side length direction of the crystalline silicon substrate 1.
  • An adjacent first region 301 and the second region 302 may be separated by a certain distance or an insulating structure is provided to insulate the first region 301 and the second region 302.
  • the shape, size and number of the through holes X in the passivation layer 2 corresponding to the first region 301 and the second region 302 of the carrier collection layer 3 may be the same or different.
  • finger electrodes may be used for the first electrode 51 and the second electrode 52.
  • a first anti-reflection layer 41 may be provided on the carrier collection layer 3 and/or a second anti-reflection layer 42 may be provided on the doped layer 6.
  • the first electrode 51 passes through the first anti-reflection layer 41 and the first carrier
  • the carrier collection layer 31 contacts, and the second electrode 52 contacts the doped layer 6 through the second anti-reflection layer 42.
  • the composition of the first anti-reflection layer 41 and the second anti-reflection layer 42 may be the same or different.
  • the doped layer 6 is provided in the form of a first region 301 and a second region 302 having opposite conductivity types, the first electrode 51 and the second electrode 52 are respectively in contact with the first region 301 and the second region of the doped layer 6 302.
  • the regions of the first region 301 and the second region 302 of the doped layer 6 opposite to the conductivity type of the crystalline silicon substrate 1 serve as the emitter of the crystalline silicon solar cell, and the carrier collection layer 3 has a single and The same conductivity type as the surface field of crystalline silicon solar cells.
  • the doped layer 6 is located on the back surface of the crystalline silicon substrate 1 and the carrier transport layer is located on the front surface side of the crystalline silicon substrate 1 so that the electrode 5 is located on the back surface side of the crystalline silicon substrate 1 There is no electrode 5 blocking on the side.
  • the carrier collection layer 3 having the first region 301 and the second region 302 of opposite conductivity types is located on the back surface side of the crystalline silicon substrate 1 so that the electrode 5 is located on the back surface side of the crystalline silicon substrate 1 , The electrode 5 is not blocked on the front surface side.
  • the front surface of the crystalline silicon substrate 1 may have a textured structure to reduce the reflection of incident light; the back surface of the crystalline silicon substrate 1 may be relatively flat and smooth after being polished or wet etched, etc.
  • the surface may also have a textured structure.
  • ком ⁇ онент such as "layer” or “region” involved in the embodiments of the present disclosure is located or disposed on another component, the component may be directly located or disposed on another component, both There is no other component in between, and it can also be indirectly located or arranged on another component, with one or more intermediate components in between.
  • the passivation layer 2 is directly disposed on one side surface of the crystalline silicon substrate 1, and the carrier collection layer 3 is directly disposed on the passivation layer 2.
  • other structures may be provided between the crystalline silicon substrate 1 and the passivation layer 2 and/or between the carrier collection layer 3 and the passivation layer 2 according to actual needs. It can be understood that in the crystal Other structures provided between the silicon substrate 1 and the passivation layer 2 and/or between the carrier collection layer 3 and the passivation layer 2 also need to be provided with a through hole corresponding to the through hole X on the passivation layer 2 X, so that the carrier collection layer 3 can contact the crystalline silicon substrate 1.
  • the preparation method of the crystalline silicon solar cell mainly includes providing a crystalline silicon substrate 1, forming a passivation layer 2 having a through hole X on the crystalline silicon substrate 1, and forming the crystalline silicon substrate 1 and the crystalline silicon substrate 1 on the passivation layer 2 Carrier collection layer 3 is formed on a portion of passivation layer 2 opposite to through hole X, and electrode 5 in contact with carrier collection layer 3 is formed.
  • the crystalline silicon solar cell produced by the preparation method provided by the embodiment of the present disclosure has good carrier transmission performance and high photoelectric conversion efficiency on the basis of good passivation effect.
  • the steps of cleaning the crystalline silicon substrate and texturing the surface of the crystalline silicon substrate are necessary in the solar cell preparation process.
  • the sequence of the above steps and specific implementation manners are also different. The preparation methods of crystalline silicon solar cells with different structures are described below.
  • the manufacturing method of the solar cell includes the following steps.
  • Step A01 the crystalline silicon substrate 1 is washed, and the front surface of the crystalline silicon substrate 1 is textured, and a textured structure is formed on the front surface of the crystalline silicon substrate 1.
  • the crystalline silicon substrate 1 can be washed with a mixed aqueous solution of sodium hydroxide (NaOH) and hydrogen peroxide (H 2 O 2 ) to remove contaminants and damage layers on the surface of the crystalline silicon substrate 1.
  • NaOH sodium hydroxide
  • H 2 O 2 hydrogen peroxide
  • the mass concentration can be 0.5% to 5% (such as 0.5%, 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 4.5%, 5 %, etc.) aqueous sodium hydroxide at a temperature of 75°C to 90°C (eg 75°C, 76°C, 78°C, 80°C, 82°C, 84°C, 85°C, 86°C, 88°C, 90°C, etc.) Under the texturing.
  • 75°C to 90°C eg 75°C, 76°C, 78°C, 80°C, 82°C, 84°C, 85°C, 86°C, 88°C, 90°C, etc.
  • the reflectivity of the surface of the single crystal silicon substrate 1 can be 10% to 18% (eg 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, etc.) ), the reflectivity of the surface of the polycrystalline silicon substrate 1 may be 6% to 20% (for example, 6%, 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14%, 15% , 16%, 17%, 18%, 19%, 20%, etc.).
  • the texturing of the front and back surfaces of the crystalline silicon substrate 1 can be completed in this step.
  • Step A02 a passivation layer 2 is formed on one side of the crystalline silicon substrate 1.
  • the step is specifically to form the passivation layer 2 on the front surface side of the crystalline silicon substrate 1; when the passivation layer 2 is provided on the crystal When the silicon substrate 1 is on the back surface side, this step is specifically to form the passivation layer 2 on the back surface side of the crystalline silicon substrate 1.
  • the process of forming the passivation layer 2 may be selected according to the specific composition of the passivation layer 2, including but not limited to an atomic layer deposition (Aatomic Layer Deposition, ALD) process, or a chemical vapor deposition (Chemical Vapor Deposition, CVD) process, and the like.
  • ALD atomic Layer Deposition
  • CVD chemical vapor deposition
  • a silicon oxide layer is directly formed on the surface of the crystalline silicon substrate 1 as the passivation layer 2
  • a high-temperature thermal oxidation process, a nitric acid oxidation process, a dry ozone oxidation process, a wet ozone oxidation process, etc. can also be used on the crystalline silicon substrate 1
  • a silicon oxide layer is formed on the surface.
  • the mass concentration of nitric acid may be 1% to 20%, such as 1%, 2%, 4%, 5%, 6%, and 8% , 10%, 12%, 14%, 15%, 16%, 18%, 20%, etc.
  • the treatment time with nitric acid can be 2 minutes to 20 minutes, such as 2 minutes, 4 minutes, 5 minutes, 6 minutes, 8 Minutes, 10 minutes, 12 minutes, 14 minutes, 15 minutes, 16 minutes, 18 minutes, 20 minutes, etc.
  • Step A03 a through hole X is opened in the passivation layer 2.
  • the portion corresponding to the passivation layer 2 is removed according to the pattern of the set through hole X, and the through hole X is formed on the passivation layer 2.
  • a laser etching process or a chemical etching mask process may be used to open the through hole X in the passivation layer 2.
  • the laser pattern is the same as the through hole X pattern on the passivation layer 2; in the chemical etching mask process, the pattern of the mask hollow area and the through hole X pattern on the passivation layer 2 the same.
  • the openings of other structures can be completed at the same time to make the crystal The portion of the silicon substrate 1 opposite to the through hole X is exposed.
  • Step A04 a carrier collection layer 3 is formed on the passivation layer 2 and the portion of the crystalline silicon substrate 1 opposite to the through hole X of the passivation layer 2 (ie, the exposed portion of the crystalline silicon substrate 1).
  • the process of forming the carrier collection layer 3 can be selected according to the specific composition of the carrier collection layer 3.
  • the doped silicon layer is used as the carrier collection layer 3
  • the following optional manner may be used to form the doped silicon layer.
  • Manner 1 During the process of growing the intrinsic silicon layer, a doping source is passed to obtain a doped silicon layer, that is, a doped silicon layer is formed in an environment where the doping source exists.
  • phosphane can be used as a doping source of phosphorus element
  • borane can be used as a doping source of boron element.
  • the heating peak temperature may be 800°C to 1000°C, such as 800°C, 820°C, 840°C, 850°C, 860°C, 870°C, 880°C, 900°C, 920°C, 940°C, 950°C, 960 °C, 980 °C, 1000 °C, etc.
  • heat treatment time can be 30 minutes to 200 minutes, such as 30 minutes, 40 minutes, 50 minutes, 60 minutes, 70 minutes, 80 minutes, 90 minutes, 100 minutes, 110 minutes, 120 minutes , 130 minutes, 140 minutes, 150 minutes, 160 minutes, 170 minutes, 180 minutes, 190 minutes, 200 minutes, etc.
  • Method 2 First, an intrinsic silicon layer is grown, and then doped elements are doped into the intrinsic silicon layer to form a doped silicon layer.
  • the doping of the intrinsic silicon layer may specifically include: implanting doping ions (such as phosphorus ions or boron ions) into the intrinsic silicon layer using an ion implantation device, and then annealing to obtain the doped silicon layer ; Or forming a silicon glass layer containing a doping source (such as phosphorus silicate glass PSG or borosilicate glass BSG) on the intrinsic silicon layer, and then annealing to make the doping source in the silicon glass layer into the intrinsic silicon layer to be doped Doped silicon layer; or directly doping the intrinsic silicon layer by thermal diffusion.
  • doping ions such as phosphorus ions or boron ions
  • the above-mentioned silicon glass containing a doping source can be prepared by using APCVD equipment.
  • the annealing temperature during the above annealing process may be 600°C to 950°C, such as 600°C, 620°C, 640°C, 650°C, 660°C, 680°C, 700°C, 720°C, 740°C, 750°C, 760°C, 780 °C, 800°C, 820°C, 840°C, 850°C, 860°C, 880°C, 900°C, 920°C, 940°C, 950°C, etc.,
  • the intrinsic silicon layer can be prepared by using LPCVD equipment.
  • Step A05 a doped layer 6 is formed on the side of the crystalline silicon substrate 1 opposite to the passivation layer 2.
  • the doped layer 6 is formed on the back surface side of the crystalline silicon substrate 1 in this step; when in step A02 When the passivation layer 2 is formed on the back surface side of the crystalline silicon substrate 1, the doped layer 6 is formed on the front surface side of the crystalline silicon substrate 1 in this step.
  • the doping layer 6 may be specifically formed by implanting doping ions (such as phosphorus ions or boron ions) onto the surface of the crystalline silicon substrate 1 opposite to the passivation layer 2 using an ion implantation device, and then performing annealing Obtain a doped layer 6; or form a silicon glass layer containing a doping source on the surface of the crystalline silicon substrate 1 opposite to the passivation layer 2 (for example, phosphorous silicon glass PSG or borosilicate glass BSG), and then anneal the silicon The doping source in the glass layer enters the intrinsic silicon layer to obtain the doped layer 6; or the surface of the crystalline silicon substrate 1 opposite to the passivation layer 2 is directly doped by thermal diffusion to form the doped layer 6 .
  • doping ions such as phosphorus ions or boron ions
  • step A05 may be performed after step A04 (as shown in FIGS. 10a to 10g), or after step A01 and before step A02 (as shown in FIGS. 9a to 9g).
  • step A05 is performed between step A01 and step A02; when the doped layer 6 is located on the back surface side of the crystalline silicon substrate 1, step A05 The step is performed after step A04.
  • Step A06 a first anti-reflection layer 41 is formed on the carrier collection layer 3 and/or a second anti-reflection layer 42 is formed on the doped layer 6.
  • the specific formation method of the first anti-reflection layer 41 and the second anti-reflection layer 42 can be determined according to the specific composition of the two.
  • the silicon nitride layer as the anti-reflection layer 4
  • the silicon nitride layer can be formed by a PECVD process.
  • the first anti-reflection layer 41 and the second anti-reflection layer 42 may be separately formed in a certain order.
  • the composition of one anti-reflection layer 4 and the second anti-reflection layer 42 is the same, the two may be formed at the same time.
  • Step A07 a first electrode 51 in contact with the carrier collection layer 3 is formed, and a second electrode 52 in contact with the doped layer 6 is formed.
  • the paste for forming the first electrode 51 and the second electrode 52 is printed on the corresponding anti-reflection layer 4 Then, sintering is performed to form the first electrode 51 and the second electrode 52.
  • the carrier collection layer 3 and/or the doped layer 6 is printed directly to form the first electrode 51, the first The slurry of the second electrode 52.
  • the sintering conditions can be determined according to the composition of the specific slurry.
  • the slurry is sintered at a temperature of 750°C, 760°C, 780°C, 800°C, 820°C, 840°C, 850°C, 860°C, 880°C, 900°C, etc.).
  • the manufacturing method of the solar cell includes the following steps.
  • Step B01 the crystalline silicon substrate 1 is cleaned, and the front surface of the crystalline silicon substrate 1 is textured, and a textured structure is formed on the front surface of the crystalline silicon substrate 1.
  • Step B02 a first passivation layer 21 having a through hole X is formed on one side of the crystalline silicon substrate 1, and a second passivation layer 22 having a through hole X is formed on the other side of the crystalline silicon substrate 1.
  • step A02 For the specific process of forming the first passivation layer 21 and the second passivation layer 22, reference may be made to the description in step A02, and details are not described herein again.
  • first passivation layer 21 and the second passivation layer 22 may be separately formed in order, and when the first passivation layer 21 and the second passivation layer 22 have the same composition, the two may be simultaneously formed.
  • step B03 through holes X are opened in the first passivation layer 21 and the second passivation layer 22, respectively.
  • Step B04 a first carrier collection layer 31 is formed on the first passivation layer 21 and the portion of the crystalline silicon substrate 1 opposite to the through hole X of the first passivation layer 21, on the second passivation layer 22 and On the portion of the crystalline silicon substrate 1 opposite to the through hole X of the second passivation layer 22, a second carrier collection layer 32 opposite to the first carrier conductivity type is formed.
  • the specific formation method of the first carrier collection layer 31 and the second carrier collection layer 32 can refer to the description in the above step A04, and will not be repeated here.
  • the first intrinsic silicon layer and A second intrinsic silicon layer is formed on the second passivation layer 22, and then the first intrinsic silicon layer and the second intrinsic silicon layer are doped.
  • the first intrinsic silicon layer and the second intrinsic silicon layer are ion implanted separately, or the first intrinsic silicon layer and the second intrinsic silicon layer are formed respectively first.
  • an annealing is performed to complete the doping of the first intrinsic silicon layer and the second intrinsic silicon layer.
  • Step B05 a first anti-reflection layer 41 is formed on the first carrier collection layer 31 and/or a second anti-reflection layer 42 is formed on the second carrier collection layer 32.
  • the specific formation method of the first anti-reflection layer 41 and the second anti-reflection layer 42 can refer to the description in step A06, and will not be repeated here.
  • Step B06 a first electrode 51 in contact with the first carrier collection layer 31 is formed, and a second electrode 52 in contact with the second carrier collection layer 32 is formed.
  • the anti-reflection layer 4 is provided on the first carrier collection layer 31 and the second carrier collection layer 32, the corresponding anti-reflection layer 4 is printed to form the first electrode 51, the first The slurry of the two electrodes 52 is then sintered to form the first electrode 51 and the second electrode 52.
  • the first carrier collection layer 31 and/or the second carrier collection layer 32 is directly The paste for forming the first electrode 51 and the second electrode 52 is printed thereon.
  • the sintering conditions of the paste for forming the first electrode 51 and the second electrode 52 can refer to the description in the above step A07, and will not be repeated here.
  • the manufacturing method of the solar cell includes the following steps.
  • Step C01 the crystalline silicon substrate 1 is cleaned, and the front surface of the crystalline silicon substrate 1 is textured, and a textured structure is formed on the front surface of the crystalline silicon substrate 1.
  • Step C02 a passivation layer 2 is formed on one side of the crystalline silicon substrate 1.
  • the specific process of forming the passivation layer 2 can refer to the description in the above step A02, which will not be repeated here.
  • Step C03 a through hole X is opened in the passivation layer 2.
  • a carrier collection layer 3 having a first region 301 and a second region 302 of opposite conductivity types is formed on the passivation layer 2 and a portion of the crystalline silicon substrate 1 opposite to the through hole X of the passivation layer 2.
  • the intrinsic silicon layer can be grown first, and then different regions of the intrinsic silicon layer can be treated with the first and second doping sources of opposite conductivity types. Doping is performed to form a doped silicon layer having first regions 301 and second regions 302 having opposite conductivity types.
  • An ion implantation device may be used to implant different doping ions into different regions of the intrinsic silicon layer, such as implanting phosphorus ions and boron ions, and then performing annealing to obtain a doped silicon layer with phosphorus doped regions and boron doped regions.
  • the specific formation method of the intrinsic silicon layer, the specific process of ion implantation and annealing can refer to the description of the above step A04, and will not be repeated here.
  • step C05 a doped layer 6 of the same conductivity type as the crystalline silicon substrate 1 is formed on the side of the crystalline silicon substrate 1 opposite to the carrier collection layer 3.
  • the specific formation method of the doped layer 6 can refer to the description of the above step A05, which will not be repeated here.
  • step C05 may be performed after step C04, or after step C01 and before step C02.
  • Step C06 forming a first anti-reflection layer 41 on the carrier collection layer 3 and/or forming a second anti-reflection layer 42 on the doped layer 6.
  • the specific forming method of the first anti-reflection layer 41 and the second anti-reflection layer 42 can refer to the description in step A06, and will not be repeated here.
  • Step C07 a first electrode 51 in contact with the first region 301 of the carrier collection layer 3 is formed, and a second electrode 52 in contact with the second region 302 of the carrier collection layer 3 is formed.
  • the position corresponding to the first region 301 of the carrier collection layer 3 is printed on the first anti-reflection layer 41 for printing
  • the paste forming the first electrode 51 is printed on the first anti-reflection layer 41 at a position corresponding to the second region 302 of the carrier collection layer 3 to form the paste for forming the second electrode 52, and then sintered to form the first ⁇ electrode 51 and second electrode 52.
  • the first anti-reflection layer 41 is not provided on the carrier collection layer 3
  • the first region 301 and the second region 302 of the carrier collection layer 3 are printed directly to form the first electrode 51 and the second electrode 52. Slurry.
  • the sintering conditions of the paste for forming the first electrode 51 and the second electrode 52 can refer to the description in the above step A07, and will not be repeated here.
  • the embodiments of the present disclosure also provide a photovoltaic module using the above crystalline silicon solar cell.
  • the photovoltaic module includes a cover plate, a first encapsulating adhesive film, a battery string, a second encapsulating adhesive film, and a back plate that are arranged in sequence, wherein the battery string includes a plurality of crystalline silicon solar cells provided by embodiments of the present disclosure.
  • the passivation layer is provided with a through hole, and the carrier collection layer contacts the crystalline silicon substrate through the through hole in the passivation layer, thereby ensuring the surface Based on the passivation effect, carriers can be collected by the electrode through the interface of the crystalline silicon substrate and the carrier collection layer, which can effectively transport the carriers, improve the photoelectric conversion efficiency of the crystalline silicon solar cell, and thus improve the application
  • the photovoltaic module of the crystalline silicon solar cell has higher output power, reduces the cost of electricity, and improves the cost performance of photovoltaic power generation.
  • the cover plate is a glass plate
  • the material of the first encapsulation film and the second encapsulation film may be EVA (ethylene-vinyl acetate copolymer) or POE (ethylene-octene copolymer)
  • the back plate may It is a glass plate or a TPT (PVF/PET/PVF) plate.
  • the photovoltaic module also includes a frame, which can be filled with a sealant (such as silicone).
  • the crystalline silicon solar cell may be a square or a square-shaped whole cell with rounded corners, or a sliced cell obtained by cutting the whole cell.
  • the photovoltaic assembly provided in the embodiments of the present disclosure may include multiple strings of battery strings, and the battery pieces in each string of strings may be connected by welding tape, or may be connected by conductive adhesive or other conductive materials.
  • a certain gap can be left between adjacent battery slices, or the edges of adjacent battery slices can be overlapped, that is, connected by shingling.
  • the carrier collection layer is in contact with the crystalline silicon substrate through the through holes in the passivation layer, thereby ensuring the surface passivation effect , So that the carriers can be collected by the electrode through the interface of the crystalline silicon substrate and the carrier collection layer, which can effectively transport the carriers, reduce the series resistance of the crystalline silicon solar cell, and increase the filling factor of the crystalline silicon solar cell, In turn, it improves the photoelectric conversion efficiency of crystalline silicon solar cells, reduces the cost of electricity, and improves the cost performance of photovoltaic power generation.

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Abstract

本公开涉及一种晶体硅太阳能电池及其制备方法、光伏组件，属于太阳能电池技术领域。其中，晶体硅太阳能电池包括晶体硅基体、设置在所述晶体硅基体上的具有通孔的钝化层、设置在所述钝化层上的载流子收集层、以及与所述载流子收集层接触的电极；所述载流子收集层通过所述钝化层上的通孔与所述晶体硅基体接触。该晶体硅太阳能电池中，在钝化层上开设通孔，并且载流子收集层通过钝化层上的通孔与晶体硅基体接触，在保证良好表面钝化效果的基础上，载流子可穿过晶体硅基体与载流子收集层接触的界面被电极收集，实现更加有效的载流子传输，降低晶体硅太阳能电池的串联电阻，提高晶体硅太阳能电池的填充因子，提高晶体硅太阳能电池的光电转换效率。

Description

晶体硅太阳能电池及其制备方法、光伏组件
本公开要求于2018年11月27日提交中国国家知识产权局、申请号为201821965911.8、发明名称为“晶体硅太阳能电池及光伏组件”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及太阳能电池技术领域，具体涉及一种晶体硅太阳能电池及其制备方法、光伏组件。
背景技术
光伏发电是利用大面积P-N结二极管将太阳能转化为电能的发电方式，是一种清洁、可持续性及性价比相对较高的发电方式。上述的P-N结二极管称为太阳能电池。晶体硅太阳能电池是一种应用较为广泛的太阳能电池。晶体硅太阳能电池的光电转换性能依赖于其内部少数载流子浓度，少数载流子的复合湮灭会造成晶体硅太阳能电池电压和电流的流失，从而降低晶体硅太阳能电池的光电转换效率。对于晶体硅太阳能电池来说，在晶体硅基体表面存在缺陷，是严重的复合中心。通常需要在晶体硅基体表面和电极之间设置钝化结构以钝化晶体硅基体表面，以降低晶体硅基体表面少数载流子的复合速率，来提高晶体硅太阳能电池的光电转化效率。
相关技术中提供了一种具有隧道氧化钝化接触结构的晶体硅太阳能电池(如图1所示)，包括晶体硅基体1’，设置在晶体硅基体1’上的钝化隧穿层2’，设置在钝化隧穿层2’上的载流子收集层3’，以及与载流子收集层3’形成欧姆接触的电极5’。该结构的晶体硅太阳能电池可有效解决晶体硅基体1’表面和电极5’之间的钝化问题。
然而，钝化隧穿层不能很好地实现载流子的有效传输，导致晶体硅太阳能电池的串联电阻较高，影响晶体硅太阳能电池的光电转换效率。
公开内容
本公开实施例提供了一种晶体硅太阳能电池及其制备方法、光伏组件，能够解决上述晶体硅太阳能电池串联电阻较高、光电转换效率不理想的问题。
具体而言，包括以下的技术方案。
第一方面，本公开实施例提供了一种晶体硅太阳能电池，包括：
晶体硅基体，
设置在所述晶体硅基体上的具有通孔的钝化层，
设置在所述钝化层上的载流子收集层，以及，
与所述载流子收集层接触的电极；
其中，所述载流子收集层通过所述钝化层上的通孔与所述晶体硅基体接触。
可选地，在沿着平行于所述晶体硅基体表面的方向上，所述通孔的截面形状为线形、圆形或者多边形。
可选地，所述钝化层上设置有多个通孔。
可选地，所述电极具有与所述钝化层上的通孔对应的部分。
可选地，所述钝化层为氧化物层。
可选地，所述钝化层的厚度为0.3纳米～100纳米。
可选地，所述载流子收集层为掺杂硅层。
可选地，所述载流子收集层为掺杂多晶硅层或者掺杂非晶硅层。
可选地，所述载流子收集层的厚度为30纳米～500纳米。
可选地，所述晶体硅太阳能电池还包括：设置在所述载流子收集层上的减反射层；所述电极穿过所述减反射层与所述载流子收集层接触。
第二方面，本公开实施例提供了另一种晶体硅太阳能电池，包括：
晶体硅基体，
设置在所述晶体硅基体一侧的具有通孔的钝化层，
设置在所述钝化层上的载流子收集层，
与所述载流子收集层接触的第一电极，
设置在所述晶体硅基体另一侧的掺杂层，以及，
与所述掺杂层接触的第二电极；
其中，所述载流子收集层通过所述钝化层上的通孔与所述晶体硅基体接触；
所述载流子收集层的导电类型与所述掺杂层的导电类型相反。
可选地，在沿着平行于所述晶体硅基体表面的方向上，所述通孔的截面形状为线形、圆形或者多边形。
可选地，所述钝化层上设置有多个通孔。
可选地，所述电极具有与所述钝化层上的通孔相对的部分。
可选地，所述钝化层为氧化物层。
可选地，所述钝化层的厚度为0.3纳米～100纳米。
可选地，所述载流子收集层为掺杂硅层。
可选地，所述载流子收集层为掺杂多晶硅层或者掺杂非晶硅层。
可选地，所述载流子收集层的厚度为30纳米～500纳米。
可选地，所述晶体硅太阳能电池还包括：设置在所述载流子收集层上的第一减反射层，和/或设置在所述掺杂层上的第二减反射层；所述第一电极穿过所述第一减反射层与所述载流子收集层接触，所述第二电极穿过所述第二减反射层与所述掺杂层接触。
第三方面，本公开实施例提供了又一种晶体硅太阳能电池，包括：
晶体硅基体，
设置在所述晶体硅基体一侧的具有通孔的第一钝化层，
设置在所述第一钝化层上的第一载流子收集层，
一与所述第一载流子收集层接触的第一电极，
设置在所述晶体硅基体另一侧的具有通孔的第二钝化层，
设置在所述第二钝化层上的第二载流子收集层，以及，
与所述第二载流子收集层接触的第二电极；
其中，所述第一载流子收集层通过所述第一钝化层上的通孔与所述晶体硅基体接触；所述第二载流子收集层通过所述第二钝化层上的通孔与所述晶体硅基体接触；
所述第一载流子收集层与所述第二载流子收集层的导电类型相反。
可选地，在沿着平行于所述晶体硅基体表面的方向上，所述通孔的截面形状为线形、圆形或者多边形。
可选地，所述第一钝化层和所述第二钝化层均上设置有多个通孔。
可选地，所述第一电极具有与所述第一钝化层上的通孔相对的部分；所述第二电极具有与所述第二钝化层上的通孔相对的部分。
可选地，所述第一钝化层为氧化物层，所述第二钝化层为氧化物层。
可选地，所述第一钝化层的厚度为0.3纳米～100纳米，所述第二钝化层的厚度为0.3纳米～100纳米。
可选地，所述第一载流子收集层为掺杂硅层，所述第二载流子收集层为掺杂硅层。
可选地，所述第一载流子收集层为掺杂多晶硅层或者掺杂非晶硅层，所述第二载流子收集层为掺杂多晶硅层或者掺杂非晶硅层。
可选地，所述第一载流子收集层的厚度为30纳米～500纳米，所述第二载流子收集层的厚度为30纳米～500纳米。
可选地，所述晶体硅太阳能电池还包括：设置在所述第一载流子收集层上的第一减反射层，和/或设置在所述第二载流子收集层上的第二减反射层；所述第一电极穿过所述第一减反射层与所述第一载流子收集层接触，所述第二电极穿过所述第二减反射层与所述第二载流子收集层接触。
第四方面、本公开实施例提供了再一种晶体硅太阳能电池，包括：
晶体硅基体，
设置在所述晶体硅基体一侧的具有通孔的钝化层，
设置在所述钝化层上、且具有导电类型相反的第一区域和第二区域的载流子收集层，
与所述载流子收集层的第一区域接触的第一电极，
与所述载流子收集层的第二区域接触的第二电极，以及，
设置在所述晶体硅基体另一侧的掺杂层；
其中，所述载流子收集层通过所述钝化层上的通孔与所述晶体硅基体接触；
所述掺杂层的导电类型与所述晶体硅基体的导电类型相同。
可选地，所述载流子收集层具有多个所述第一区域和多个所述第二区域，多个所述第一区域和多个所述第二区域相间分布。
可选地，在沿着平行于所述晶体硅基体表面的方向上，所述通孔的截面形状为线形、圆形或者多边形。
可选地，所述钝化层上设置有多个通孔。
可选地，所述第一电极具有与所述钝化层上的通孔相对的部分，所述第二电极具有与所述钝化层上的通孔相对的部分，
可选地，所述钝化层为氧化物层。
可选地，所述钝化层的厚度为0.3纳米～100纳米。
可选地，所述载流子收集层为掺杂硅层。
可选地，所述载流子收集层为掺杂多晶硅层或者掺杂非晶硅层。
可选地，所述载流子收集层的厚度为30纳米～500纳米。
可选地，所述晶体硅太阳能电池还包括：设置在所述载流子收集层上的第一减反射层，和/或设置在所述掺杂层上的第二减反射层；所述第一电极穿过所述第一减反射层与所述载流子收集层的第一区域接触，所述第二电极穿过所述第二减反射层与所述载流子收集层的第二区域接触。
第五方面，本公开实施例提供了一种晶体硅太阳能电池的制备方法，包括：
提供晶体硅基体；
在所述晶体硅基体上形成具有通孔的钝化层；
在所述钝化层上以及所述晶体硅基体与所述钝化层的通孔相对的部位上形成载流子收集层；
形成与所述载流子收集层接触的电极。
可选地，所述制备方法还包括：在所述载流子收集层上形成减反射层。
可选地，所述在所述晶体硅基体上形成具有通孔的钝化层，包括：
在所述晶体硅基体上形成所述钝化层；
在所述钝化层上开设通孔。
可选地，所述在所述钝化层上以及所述晶体硅基体与所述钝化层的通孔相对的部位上形成载流子收集层，包括：
在存在掺杂源的环境中，在所述钝化层以及所述晶体硅基体与所述钝化层的通孔相对的部位上形成掺杂硅层；
或者，
在所述钝化层以及所述晶体硅基体与所述钝化层的通孔相对的部位上形成本征硅层；
对所述本征硅层进行掺杂形成掺杂硅层。
第六方面，本公开实施例提供了另一种晶体硅太阳能电池的制备方法，包括：
提供晶体硅基体，
在所述晶体硅基体一侧形成具有通孔的钝化层，
在所述钝化层上以及所述晶体硅基体与所述钝化层的通孔相对的部位上形成载流子收集层；
在所述晶体硅基体另一侧形成与所述载流子收集层导电类型相反的掺杂层，
形成与所述载流子收集层接触的第一电极，
形成与所述掺杂层接触的第二电极。
可选地，所述制备方法还包括：
在所述载流子收集层上形成第一减反射层；
在所述掺杂层上形成第二减反射层。
可选地，所述在所述晶体硅基体上形成具有通孔的钝化层，包括：
在所述晶体硅基体上形成所述钝化层；
在所述钝化层上开设所述通孔。
可选地，所述在所述钝化层上以及所述晶体硅基体与所述钝化层的通孔相对的部位上形成载流子收集层，包括：
在存在掺杂源的环境中，在所述钝化层以及所述晶体硅基体与所述钝化层的通孔相对的部位上形成掺杂硅层；
或者，
在所述钝化层以及所述晶体硅基体与所述钝化层的通孔相对的部位上形成本征硅层；
对所述本征硅层进行掺杂形成掺杂硅层。
第七方面，本公开实施例提供了又一种晶体硅太阳能电池的制备方法，包括：
提供晶体硅基体；
在所述晶体硅基体一侧形成具有通孔的第一钝化层；
在所述晶体硅基体另一侧形成具有通孔的第二钝化层；
在所述第一钝化层上以及所述晶体硅基体与所述第一钝化层的通孔相对的部位上形成第一载流子收集层；
在所述第二钝化层上以及所述晶体硅基体与所述第二钝化层的通孔相对的部位上形成与所述第一载流子导电类型相反的第二载流子收集层；
形成与所述第一载流子收集层接触的第一电极，
形成与所述第二载流子收集层接触的第二电极。
可选地，所述制备方法还包括：
在所述第一载流子收集层上形成第一减反射层；
在所述第二载流子收集层上形成第二减反射层。
可选地，所述在所述晶体硅基体上形成具有通孔的第一钝化层，包括：
在所述晶体硅基体上形成所述第一钝化层；
在所述第一钝化层上开设通孔；
所述在所述晶体硅基体上形成具有通孔的第二钝化层，包括：
在所述晶体硅基体上形成所述第二钝化层；
在所述第二钝化层上开设通孔。
可选地，所述在所述第一钝化层上以及所述晶体硅基体与所述第一钝化层的通孔相对的部位上形成第一载流子收集层，包括：
在存在掺杂源的环境中，在所述第一钝化层以及所述晶体硅基体与所述第一钝化层的通孔相对的部位上形成第一掺杂硅层；
或者，
在所述第一钝化层以及所述晶体硅基体与所述第一钝化层的通孔相对的部位上形成第一本征硅层；
对所述第一本征硅层进行掺杂形成第一掺杂硅层；
所述在所述第二钝化层上以及所述晶体硅基体与所述第二钝化层的通孔相对的部位上形成第二载流子收集层，包括：
在存在掺杂源的环境中，在所述第二钝化层以及所述晶体硅基体与所述第二钝化层的通孔相对的部位上形成第二掺杂硅层；
或者，
在所述第二钝化层以及所述晶体硅基体与所述第二钝化层的通孔相对的部位上形成第二本征硅层；
对所述第二本征硅层进行掺杂形成第二掺杂硅层。
第八方面，本公开实施例提供了再一种晶体硅太阳能电池的制备方法，包括：
提供晶体硅基体；
在所述晶体硅基体一侧形成具有通孔的钝化层；
在所述钝化层上以及所述晶体硅基体与所述钝化层的通孔相对的部位上形成具有导电类型相反的第一区域和第二区域的载流子收集层；
在所述晶体硅基体另一侧形成与所述晶体硅基体导电类型相同的掺杂层；
形成与所述载流子收集层的第一区域接触的第一电极；
形成与所述载流子收集层的第二区域接触的第二电极。
可选地，所述制备方法还包括：
在所述载流子收集层上形成第一减反射层；
在所述掺杂层上形成第二减反射层。
可选地，所述在所述晶体硅基体上形成具有通孔的钝化层，包括：
在所述晶体硅基体上形成所述钝化层；
在所述钝化层上开设所述通孔。
可选地，在所述钝化层上以及所述晶体硅基体与所述钝化层的通孔相对的部位上形成具有导电类型相反的第一区域和第二区域的载流子收集层，包括：
在所述钝化层以及所述晶体硅基体与所述钝化层的通孔相对的部位上形成本征硅层；
采用导电类型相反的第一掺杂源和第二掺杂源对所述本征硅层的第一区域和第二区域进行掺杂，形成具有导电类型相反的第一区域和第二区域的掺杂硅层。
第九方面，本公开实施例提供了一种光伏组件，包括：依次设置的盖板、第一封装胶膜，电池串、第二封装胶膜和背板，所述电池串包括多个太阳能电池，所述太阳能电池为上述的晶体硅太阳能电池。
本公开实施例提供的技术方案的有益效果至少包括：
本公开实施例提供的晶体硅太阳能电池中，在钝化层上开设通孔，并且载流子收集层通过钝化层上的通孔与晶体硅基体接触，在保证良好表面钝化效果的基础上，载流子可穿过晶体硅基体与载流子收集层接触的界面被电极收集，实现更加有效的载流子传输，降低晶体硅太阳能电池的串联电阻，提高晶体硅太阳能电池的填充因子，从而提高晶体硅太阳能电池的光电转换效率。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍。
图1为相关技术提供晶体硅太阳能电池的结构示意图；
图2为本公开实施例提供的一种晶体硅太阳能电池的结构示意图；
图3a为本公开实施例提供的晶体硅太阳能电池中一种钝化层通孔的结构示意图；
图3b为本公开实施例提供的晶体硅太阳能电池中另一种钝化层通孔的结构示意图；
图4a为本公开实施例提供的晶体硅太阳能电池中一种通孔与电极位置关系示意图；
图4b为本公开实施例提供的晶体硅太阳能电池中另一种通孔与电极位置关系示意图；
图4c为本公开实施例提供的晶体硅太阳能电池中又一种通孔与电极位置关系示意图；
图4d为本公开实施例提供的晶体硅太阳能电池中再一种通孔与电极位置关系示意图；
图4e为本公开实施例提供的晶体硅太阳能电池中再一种通孔与电极位置关系示意图；
图5为本公开实施例提供的另一种晶体硅太阳能电池的结构示意图；
图6为本公开实施例提供的又一种晶体硅太阳能电池的结构示意图；
图7为本公开实施例提供的再一种晶体硅太阳能电池的结构示意图；
图8为本公开实施例提供的再一种晶体硅太阳能电池的结构示意图；
图9a～图9g为图5所示的晶体硅太阳能电池的制备方法的示意图；
图10a～图10g为图6所示的晶体硅太阳能电池的制备方法的示意图；
图11a～图11b为图7所示的晶体硅太阳能电池的制备方法的示意图；
图12a～图12b为图8所示的晶体硅太阳能电池的制备方法的示意图。
图中的附图标记分别表示：
1   晶体硅基体
2   钝化层
21  第一钝化层
22  第二钝化层
3   载流子收集层
31  第一载流子收集层
32  第二载流子收集层
301 第一区域
302 第二区域
4   减反射层
41  第一减反射层
42  第二减反射层
5   电极
51  第一电极
52  第二电极
6   掺杂层
X   通孔
T1  载流子收集层的厚度
D1  截面形状为圆形的通孔的直径
P1  同一列中相邻两个截面形状为圆形的通孔之间的距离
P2  同一行中相邻两个截面形状为圆形的通孔之间的距离
1’ 相关技术提供的晶体硅太阳能电池的晶体硅基体
2’ 相关技术提供的晶体硅太阳能电池的隧穿钝化层
3’ 相关技术提供的晶体硅太阳能电池的载流子收集层
5’ 相关技术提供的晶体硅太阳能电池的电极
具体实施方式
为使本公开的技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
除非另有定义，本公开实施例所用的所有技术术语均具有与本领域技术人员通常理解的相同的含义。
提高晶体硅太阳能电池的光电转换效率是提高光伏发电输出功率、降低度电成本的有效途径。目前，限制单片晶体硅太阳能电池光电转化效率的重要因素之一是晶体硅太阳能电池中少数载流子的复合湮灭。少数载流子的复合湮灭会造成晶体硅太阳能电池电压和电流的流失，从而降低晶体硅太阳能电池的光电转换效率。在晶体硅基体表面设置钝化结构能够降低晶体硅基体表面少数载流子的复合速率，有利于提高晶体硅太阳能电池的光电转换效率。
在传统隧道氧化钝化接触晶体硅太阳能电池中，载流子穿过钝化隧穿层进入载流子收集层，之后被电极收集。然而钝化隧穿层不能很好地实现载流子的有效传输，导致晶体硅太阳能电池的串联电阻较高，从而影响晶体硅太阳能电池的光电转换效率。
基于以上所述，本公开实施例对晶体硅太阳能电池的结构进行优化改进，在保证钝化效果的同时，提高载流子传输能力，从而提高晶体硅太阳能电池的光电转换效率。
图2为本公开实施例提供的一种晶体硅太阳能电池的结构示意图，如图2所示，该晶体硅太阳能电池包括：晶体硅基体1，设置在晶体硅基体1上的具有通孔X的钝化层2，设置在钝化层2上的载流子收集层3，以及，与载流子收集层3接触的电极5。
其中，通孔X是指贯穿钝化层2厚度方向的孔，载流子收集层3通过钝化层2上的通孔X与晶体硅基体1接触。
本公开实施例提供的太阳能电池中，设置在晶体硅基体1上的钝化层2和载流子收集层3共同起到钝化的作用，保证晶体硅太阳能电池具有较高的开路电压和短路电流，在此基础上，在钝化层2上设置有通孔X，载流子收集层3通过钝化层2上的通孔X与晶体硅基体1接触，载流子可穿过晶体硅基体1与载流子收集层3接触的界面被电极5收集，实现载流子更加有效地传输，降低晶体硅太阳能电池的串联电阻，提高晶体硅太阳能电池的填充因子，从而提高晶体硅太阳能电池的光电转换效率。
钝化层2上的通孔X的形状没有严格限制，示例地，在沿着平行于晶体硅基体1表面的方向上，通孔X的截面(后文如无特殊说明截面均指沿平行于晶体硅基体1表面方向上的截面)形状可以为线形、圆形(如图3a所示)、椭圆形或者多边形。其中，线形孔可以是直线形(如图3b所示)、也可以是曲线形、折线形等；多边形孔可以为三角形、四边形、五边形、六边形等，可以是普通的多边形，也可以是正多边形。
钝化层2上的通孔X可设置有多个，多个通孔X可以按照一定的规律排列。例如，可以按照a行×b列(a≥1，b≥1，其a，b不同时为1)的方式排列。
如图3a所示，以截面形状为圆形的通孔X为例，通孔X的直径(图3a中D1所指示的尺寸)可以为0.01毫米～1毫米，例如0.01毫米、0.02毫米、0.03毫米、0.04毫米、0.05毫米、0.06毫米、0.07毫米、0.08毫米、0.09毫米、0.1毫米、0.2毫米、0.3毫米、0.4毫米、0.5毫米、0.6毫米、0.7毫米、0.8毫米、0.9毫米、1毫米等。同一列中相邻两个通孔X之间的距离(图3a中P1所指示的尺寸，两个通孔X边缘之间的距离)可以为0.3毫米～3毫米，例如0.3毫米、0.4毫米、0.5毫米、0.6毫米、0.7毫米、0.8毫米、0.9毫米、1毫米、1.1毫米、1.2毫米、1.3毫米、1.4毫米、1.5毫米、1.6毫米、1.7毫米、1.9毫米、2毫米、2.1毫米、2.2毫米、2.3毫米、2.4毫米、2.5毫米、2.6毫米、2.7毫米、2.8毫米、2.9毫米、3毫米等；同一行中相邻两个通孔X之间的距离(图3a中P2所指示的尺寸，两个通孔X边缘之间的距离)可以为0.3毫米～3毫米，例如0.3毫米、0.4毫米、0.5毫米、0.6毫米、0.7毫米、0.8毫米、0.9毫米、1毫米、1.1毫米、1.2毫米、1.3毫米、1.4毫米、1.5毫米、1.6毫米、1.7毫米、1.9毫米、2毫米、2.1毫米、2.2毫米、2.3毫米、2.4毫米、2.5毫米、2.6毫米、2.7毫米、2.8毫米、2.9毫米、3毫米等。
所有通孔X的形状可以全部相同，也可以部分通孔X的形状相同。
每个通孔X的截面面积和通孔X的数量没有严格限制，可以根据实际需要进行设置。本公开实施例中，所有通孔X总的开孔面积占钝化层2面积的比例可以为：0.1％～5％，例如0.1％、0.2％、0.4％、0.5％、0.6％、0.8％、1.0％、1.2％、1.4％、1.5％、1.6％、1.8％、2.0％、2.2％、2.4％、2.5％、2.6％、2.8％、3.0％、3.2％、3.4％、3.5％、3.6％、3.8％、4％、4.2％、4.4％、4.5％、4.6％、4.8％、5.0％等。
本公开实施例中，电极5可以具有与钝化层2上的通孔X对应的部分。这里所述的“对应”是指在平行于晶体硅基体表面的平面上，电极5的投影与通孔X的投影具有重合的部分。
电极5可以包括多个子区域(例如栅线结构的电极5的各栅线)。可以各子区域均具有与通孔X对应的部分(例如每一条栅线均具有与通孔X对应的部分)；也可以一部分子区域具有与通孔X对应的部分，另一部分子区域不具有与通过X对应的部分(例如一部分栅线具有与通孔X对应的部分，另一部分栅线不具有与通孔X对应的区域)。
对于电极中某一个具有与通孔X对应部分的子区域来说，其与通孔X的相对位置关系又可以有不同的实施方式。下面以栅线结构电极为例，对电极5的单个子区域与通孔X的相对位置关系可能的实施方式进行举例说明。
一种可能的实施方式中，如图4a所示，通孔X呈圆形并排列成多行，栅线的宽度与通孔X的直径基本相同，且栅线的中心线与一行通孔X的中心线基本重合。
另一种可能的实施方式中，如图4b所示，通孔X呈圆形并排列成多行，栅线的宽度小于通孔X的直径，且栅线的中心线与一行通孔X的中心线基本重合。
又一种可能的实施方式中，如图4c所示，通孔X呈圆形并排列成多行，栅线的宽度大于通孔X的直径，且栅线的中心线与一行通孔X的中心线基本重合。
再一种可能的实施方式中，如图4d所示，通孔X呈圆形并排列成多行，栅线的宽度与通孔X的直径基本相同，且栅线的中心线与一行通孔X的中心线平行但不重合，二者之间具有一定距离。
再一种可能的实施方式中，如图4e，通孔X呈线形，栅线的中心线与线形通孔的中心线不重合，二者之间具有一定的夹角。
本公开实施例中，可以将通孔X的形状设置为与电极5相同的形状，使在平行于晶体硅基体表面的平面上，电极5的投影与通孔X的投影完全重合。
当然，电极5也可以完全不具有与通孔X对应的部分。
本公开实施例中，晶体硅基体1可以是单晶硅，也可以是多晶硅。晶体硅基体1的导电类型可以是P型，也可以是N型。晶体硅基体1的电阻率可以是0.5Ω·cm～15Ω·cm，例如0.5Ω·cm、1.0Ω·cm、1.5Ω·cm、2.0Ω·cm、2.5Ω·cm、3.0Ω·cm、3.5Ω·cm、4.0Ω·cm、4.5Ω·cm、5Ω·cm、5.5Ω·cm、6Ω·cm、6.5Ω·cm、7.0Ω·cm、7.5Ω·cm、8.0Ω·cm、8.5Ω·cm、9.0Ω·cm、9.5Ω·cm、10.0Ω·cm、10.5Ω·cm、11.0Ω·cm、11.5Ω·cm、12.0Ω·cm、12.5Ω·cm、13.0Ω·cm、13.5Ω·cm、14.0Ω·cm、14.5Ω·cm、15.0Ω·cm等，优选0.5Ω·cm～14Ω·cm。
晶体硅基体1的截面形状可以是正方形，也可以是四个角为圆角的正方形，或者可根据需要采用其他形状。晶体硅基体1的厚度可以为50微米～500微米，例如50微米、60微米、70微米、80微米、90微米、100微米、110微米、120微米、130微米、140微米、150微米、160微米、170微米、180微米、190微米、200微米、210微米、220微米、230微米、240微米、250微米、260微米、270微米、280微米、290微米、300微米、310微米、320微米、330微米、340微米、350微米、360微米、370微米、380微米、390微米、400微米、410微米、420微米、430微米、440微米、450微米、460微米、470微米、480微米、490微米、500微米等，优选120微米～200微米。
钝化层2可以为氧化物层，例如氧化硅(SiO x)层、氧化钛(TiO x)层、氧化铝(AlO x)层、氧化钽(TaO x)、氮氧化硅(SiN xO y)等中的至少一种，即钝化层2可以是单独某一种氧化物层，也可以是多种氧化层的叠层结构。氧化物钝化层可以同时起到化学钝化和场钝化作用。钝化层2的厚度可以为0.3纳米～100纳米，例如0.3纳米、0.4纳米、0.5纳米、0.6纳米、0.7纳米、0.8纳米、0.9纳米、1纳米、2纳米、3纳米、4纳米、5纳米、6纳米、7纳米、8纳米、9纳米、10纳米、11纳米、12纳米、13纳米、14纳米、15纳米、16纳米、17纳米、18纳米、19纳米、20纳米、25纳米、30纳米、31纳米、32纳米、33纳米、34纳米、35纳米、35纳米、36纳米、37纳米、38纳米、39纳米、40纳米、45纳米、50纳米、55纳米、60纳米、65纳米、70纳米、75纳米、80纳米、85纳米、90纳米、95纳米、100纳米等。可以看出，与相关技术中具有隧穿钝化结构的晶体硅太阳能电池相比，本公开实施例提供的晶体硅太阳能电池中钝化层2可以较厚，从而便于钝化层2的制备。
可以理解的是，载流子收集层3是可以导电的，载流子收集层3的导电类型可以与晶体硅基体1的导电类型相同，也可以相反。载流子收集层主要起到场钝化作用。当载流子收集层3的导电类型与晶体硅基体1的导电类型相反时，载流子收集层3可以作为晶体硅太阳能电池的发射极(即P-N结)；当载流子收集层3的导电类型与晶体硅的导电类型相同时，载流子收集层3可以作为晶体硅太阳能电池的表面场。
载流子收集层3可以为掺杂硅层，具体可以为掺杂多晶硅层或掺杂非晶硅层。掺杂硅层中的掺杂元素可以为P型掺杂元素，例如硼(B)、铝(Al)、镓(Ga)、铟(In)等第III族元素；也可以为N型掺杂元素，例如磷(P)、砷(As)、铋(Bi)、锑(Sb)等第V族元素。
载流子收集层3的厚度可以为30纳米～500纳米，例如30纳米、40纳米、50纳米、60纳米、70纳米、80纳米、90纳米、100纳米、110纳米、120纳米、130纳米、140纳米、150纳米、160纳米、170纳米、180纳米、190纳米、200纳米、210纳米、220纳米、230纳米、240纳米、250纳米、260纳米、270纳米、280纳米、290纳米、300纳米、310纳米、320纳米、330纳米、340纳米、350纳米、360纳米、370纳米、380纳米、390纳米、400纳米、410纳米、420纳米、430纳米、440纳米、450纳米、460纳米、470纳米、480纳米、490纳米、500纳米等。本公开实施例中，载流子收集层3的厚度是指载流子收集层3位于钝化层2上的部分的厚度，即图2中T1所指示的尺寸。
可以理解的是，电极5与载流子收集层3之间的接触面的电阻值远小于载流子收集层的电阻值。举例来说，当电极5为金属电极(例如银电极)，载流子收集层3为掺杂硅层时，二者之间应形成欧欧姆接触。
本公开实施例中，电极5与载流子收集层3接触的端部可以位于载流子收集层3的内部，进一步地，当电极5具有与钝化层2的通孔X对应的部分时，电极5与通孔X对应的部分可以位于通孔X内部，但 是，电极5位于通孔X内部的端部与晶体硅基体1之间应具有一定的距离，即电极5不与晶体硅基体1接触。
本公开实施例中，电极5可以直接设置在载流子收集层3上，也可以在载流子收集层3上设置减反射层4，电极5穿过减反射层4与载流子收集层3接触。减反射层4具体可以为氮化硅(SiN x)层、氧化硅层、氮氧化硅(SiO xN y)层或氧化铝层中的单独一种或者多种的叠层结构。减反射层4的厚度可以为30纳米～300纳米，例如30纳米、40纳米、50纳米、60纳米、70纳米、80纳米、90纳米、100纳米、110纳米、120纳米、130纳米、140纳米、150纳米、160纳米、170纳米、180纳米、190纳米、200纳米、210纳米、220纳米、230纳米、240纳米、250纳米、260纳米、270纳米、280纳米、290纳米、300纳米等。减反射层4的折射率可以是1.2～2.8，例如1.2、1.25、1.3、1.35、1.4、1.45、1.5、1.55、1.6、1.65、1.7、1.75、1.8、1.85、1.9、1.95、2.0、2.05、2.1、2.15、2.2、2.25、2.3、2.35、2.4、2.45、2.5、2.55、2.6、2.65、2.7、2.75、2.8等。需要说明的是减反射层4在具有减反射作用的同时，也可起到一定的钝化作用。
本公开实施例中，可以仅在晶体硅基体1的一侧设置上述的钝化层2和载流子收集层3，也可以在晶体硅基体1的两侧分别设置上述的钝化层2和载流子收集层3。当仅在晶体硅基体1一侧设置上述的钝化层2和载流子收集层3时，晶体硅基体1的另一侧可设置掺杂层6。下面，根据对不同结构的晶体硅太阳能电池分别进行说明。
以下描述中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，只是用来区分不同的组成部分，以便于描述。
第一种晶体硅太阳能电池结构
如图5或图6所示，该晶体硅太阳能电池中，仅在晶体硅基体1一侧设置上述的钝化层2和载流子收集层3，在晶体硅基体1的另一侧设置掺杂层6，为了便于描述，用“第一”和“第二”来区分晶体硅基体1两侧名称相同的结构。
具体来说，该晶体硅太阳能电池包括：晶体硅基体1，设置在晶体硅基体1一侧的具有通孔X的钝化层2，设置在钝化层2上的载流子收集层3，与载流子收集层3接触的第一电极51，设置在晶体硅基体1另一侧的掺杂层6，以及，与掺杂层6接触的第二电极52。
其中，载流子收集层3通过钝化层2上的通孔X与晶体硅基体1接触；载流子收集层3的导电类型与掺杂层6的导电类型相反。
掺杂层6可以通过向晶体硅基体1的一侧表面直接掺杂掺杂元素形成。掺杂层6中的掺杂元素可以为P型掺杂元素，例如硼(B)、铝(Al)、镓(Ga)、铟(In)等第III族元素；也可以为N型掺杂元素，例如磷(P)、砷(As)、铋(Bi)、锑(Sb)等第V族元素。掺杂层6的导电类型与晶体硅基体1的导电类型可以相同，也可以不相同。
该晶体硅太阳能电池中，载流子收集层3和掺杂层6在晶体硅太阳能电池中的位置及导电类型可以有以下四种情况。
(1)如图5所示，掺杂层6位于晶体硅基体1正表面(即晶体硅基体1受光面，下同)一侧且导电类型与晶体硅基体1导电类型相反，钝化层2和载流子收集层3位于晶体硅基体1背表面(即晶体硅基体1背光面，下同)一侧且载流子收集层3的导电类型与晶体硅基体1导电类型相同。
具体来说，当晶体硅基体1为N型硅时，掺杂层6为P型，载流子收集层3为N型；当晶体硅基体1为P型硅时，掺杂层6为N型，载流子收集层3为P型。
此时，掺杂层6作为晶体硅太阳能电池的发射极，载流子收集层3作为晶体硅太阳能电池的背表面场。
(2)如图5所示，掺杂层6位于晶体硅基体1正表面一侧且导电类型与晶体硅基体1导电类型相同，钝化层2和载流子收集层3位于晶体硅基体1背表面一侧且载流子收集层3的导电类型与晶体硅基体1导电类型相反。
具体来说，当晶体硅基体1为N型硅时，掺杂层6为N型，载流子收集层3为P型；当晶体硅基体1为P型硅时，掺杂层6为P型，载流子收集层3为N型。
此时，掺杂层6作为晶体硅太阳能电池的前表面场，载流子收集层3作为晶体硅太阳能电池的发射极。
(3)如图6所示，钝化层2和载流子收集层3位于晶体硅基体1正表面一侧且载流子收集层3的导电类型与晶体硅基体1导电类型相反，掺杂层6位于晶体硅基体1背表面一侧且导电类型与晶体硅基体1导电类型相同。
具体来说，当晶体硅基体1为N型硅时，载流子收集层3为P型，掺杂层6为N型；当晶体硅基体1为P型硅时，载流子收集层3为N型，掺杂层6为P型。
此时，载流子收集层3作为晶体硅太阳能电池的发射极，掺杂层6作为晶体硅太阳能电池的背表面场。
(4)如图6所示，钝化层2和载流子收集层3位于晶体硅基体1正表面一侧且载流子收集层3的导电类型与晶体硅基体1导电类型相同，掺杂层6位于晶体硅基体1背表面一侧且导电类型与晶体硅基体1导电类型相反。
具体来说，当晶体硅基体1为N型硅时，载流子收集层3为N型，掺杂层6为P型；当晶体硅基体1为P型硅时，载流子收集层3为P型，掺杂层6为N型。
此时，载流子收集层3作为晶体硅太阳能电池的前表面场，掺杂层6作为晶体硅太阳能电池的发射极。
可以在载流子收集层3上设置在第一减反射层41和/或在掺杂层6上设置第二减反射层42，第一电极51穿过第一减反射层41与载流子收集层3接触，第二电极52穿过第二减反射层42与掺杂层6接触。设置在掺杂层6上的第二减反射层42的成分、结构可参照上文对于设置在载流子收集层3上的第一减反射层41的描述，在此不再赘述。第一减反射层41和第二减反射层42的组成可以相同，也可以不相同。
第一电极51和第二电极52均可为栅线结构，形成可双面透光、双面发电的晶体硅太阳能电池。第一电极51和第二电极52具体的结构可以相同，也可以不相同。
第二种晶体硅太阳能电池结构
如图7所示，该晶体硅太阳能电池中，在晶体硅基体1两侧均设置有上述的钝化层2和载流子收集层3，为了便于描述，用“第一”和“第二”来区分晶体硅基体1两侧名称相同的结构。
具体来说，该晶体硅太阳能电池包括：晶体硅基体1，设置在晶体硅基体1一侧的具有通孔X的第一钝化层21，设置在第一钝化层21上的第一载流子收集层31，与第一载流子收集层31接触的第一电极51，设置在晶体硅基体1另一侧的具有通孔X的第二钝化层22，设置在第二钝化层22上的第二载流子收集层32，以及，与第二载流子收集层32接触的第二电极52。
其中，第一载流子收集层31通过第一钝化层21上的通孔X与晶体硅基体1接触；第二载流子收集层32通过第二钝化层22上的通孔X与晶体硅基体1接触；第一载流子收集层31与第二载流子收集层32的导电类型相反。
该晶体硅太阳能电池中，第一载流子收集层31和第二载流子收集层32的导电类型一个为N型，另一个为P型。当第一载流子收集层31的导电类型与晶体硅基体1的导电类型相同时，第二载流子收集层32的导电类型与晶体硅基体1的导电类型相反；而当第一载流子收集层31的导电类型与晶体硅基体1的导电类型相反时，第二载流子收集层32的导电类型与晶体硅基体1的导电类型相同。
与晶体硅基体1导电类型相反的载流子收集层3作为晶体硅太阳能电池的发射极，与晶体硅基体1导电类型相同的载流子收集层3作为晶体硅太阳能电池的表面场。与晶体硅基体1导电类型相反的载流子收集层3可以位于晶体硅基体1的正表侧面，相应地，与晶体硅基体1导电类型相同的载流子收集层3位于晶体硅基体1的背表面一侧，作为晶体硅太阳能电池的背表面场；与晶体硅基体1导电类型相反的载流子收集层3也可以位于晶体硅基体1的背表面一侧，相应地，与晶体硅基体1导电类型相同的载流子收集层3位于晶体硅基体1的正表侧面，作为晶体硅太阳能电池的前表面场。
第一钝化层21和第二钝化层22的具体组成可以相同，也可以不相同。第一钝化层21和第二钝化层22上的通孔X的形状、大小以及数量等可以相同，也可以不同。
可以在第一载流子收集层31上设置在第一减反射层41和/或在第二载流子收集层32上设置第二减反射层42，第一电极51穿过第一减反射层41与第一载流子收集层31接触，第二电极52穿过第二减反射层42与第二载流子收集层32接触。第一减反射层41和第二减反射层42的组成可以相同，也可以不相同。
第三种晶体硅太阳能电池结构
如图8所示，该晶体硅太阳能电池中，钝化层2和载流子收集层3设置在晶体硅基体1的一侧，并且载流子收集层3具有导电类型相反的区域，电极5设置在晶体硅基体1设置载流子收集层3的一侧，为了便于描述，用“第一”和“第二”来区分晶体硅基体1两侧名称相同的结构。
具体来说，该晶体硅太阳能电池包括：晶体硅基体1，设置在晶体硅基体1一侧的具有通孔X的钝化层2，设置在钝化层2上、且具有导电类型相反的第一区域301和第二区域302的载流子收集层3，与载流子收集层3的第一区域301接触的第一电极51，与载流子收集层3的第二区域302接触的第二电极52， 以及，设置在晶体硅基体1另一侧的掺杂层6。
其中，载流子收集层3通过钝化层2上的通孔X与晶体硅基体1接触；掺杂层6的导电类型与晶体硅基体1的导电类型相同。
该晶体硅太阳能电池中，载流子收集层3的第一区域301和第二区域302的导电类型一个为N型，另一个为P型。
掺杂层6可以通过向晶体硅基体1的一侧表面直接掺杂掺杂元素形成。掺杂层6中的掺杂元素可以为P型掺杂元素，例如硼(B)、铝(Al)、镓(Ga)、铟(In)等第III族元素；也可以为N型掺杂元素，例如磷(P)、砷(As)、铋(Bi)、锑(Sb)等第V族元素。
可以理解的是，载流子收集层3的第一区域301和第二区域302中的一个与晶体硅基体1的导电类型相同，另一个与晶体硅基体1的导电类型相反。其中，载流子收集层3中与晶体硅基体1导电类型相反的区域作为晶体硅太阳能电池的发射极。
载流子收集层3可以设置在晶体硅基体1的正表面一侧，也可以设置在晶体硅基体1的背表面一侧。在一种可选的实施方式中，载流子收集层3设置在晶体硅基体1的背表面一侧，掺杂层6设置在晶体硅基体1正表面一侧，此时，第一电极51和第二电极52均位于晶体硅基体1的背表面一侧，晶体硅基体1的正表面一侧没有电极5遮挡，可增加光的入射量，有利于提高晶体硅太阳能电池的光电转换效率。
该晶体硅太阳能电池中，载流子收集层3可具有多个第一区域301和多个第二区域302，多个第一区域301和多个第二区域302相间分布。可选地，第一区域301和第二区域302均为长方形区域，多个第一区域301和多个第二区域302沿着晶体硅基体1的边长方向相间排列。相邻的第一区域301和第二区域302之间可间隔有一定的距离或者设置绝缘结构，以使第一区域301和第二区域302之间绝缘。
与载流子收集层3的第一区域301和第二区域302对应的钝化层2上的通孔X的形状、大小及数量等可以相同，也可以不相同。
该晶体硅太阳能电池中，第一电极51和第二电极52可采用指状电极。
可以在载流子收集层3上设置在第一减反射层41和/或在掺杂层6上设置第二减反射层42，第一电极51穿过第一减反射层41与第一载流子收集层31接触，第二电极52穿过第二减反射层42与掺杂层6接触。第一减反射层41和第二减反射层42的组成可以相同，也可以不相同。
对于第三种晶体硅太阳能结构还可做以下变形：
(1)将掺杂层6设置为具有导电类型相反的第一区域301和第二区域302形式，第一电极51和第二电极52分别与掺杂层6的第一区域301和第二区域302。其中，掺杂层6的第一区域301和第二区域302中与晶体硅基体1导电类型相反的区域作为晶体硅太阳能电池的发射极，载流子收集层3具有单一且与晶体硅基体1相同的导电类型，作为晶体硅太阳能电池的表面场。可选地，掺杂层6位于晶体硅基体1的背面，载流子传输层位于晶体硅基体1的正表面一侧，从而使电极5位于晶体硅基体1的背表面一侧，正表面一侧没有电极5遮挡。
(2)将掺杂层6替换为钝化层2和具有单一且与晶体硅基体1相同的导电类型的载流子收集层3，即晶体硅基体1的两侧均具有钝化层2和载流子收集层3，其中一侧的载流子收集层3具有导电类型相反的第一区域301和第二区域302，第一电极51和第二电极52分别与第一区域301和第二区域302接触，与晶体硅基体1导电类型相反的区域作为晶体硅太阳能电池的发射极；另一侧的载流子收集层3导电类型单一且与晶体硅基体1的导电类型相同，作为晶体硅太阳能电池的表面场。可选地，具有导电类型相反的第一区域301和第二区域302的载流子收集层3位于晶体硅基体1的背表面一侧，从而使电极5位于晶体硅基体1的背表面一侧，正表面一侧没有电极5遮挡。
本公开实施例中，晶体硅基体1的正表面可以具有织构化结构，以减反射入射光的反射；晶体硅基体1的背表面可以是经过抛光或者湿刻等得到的较为平坦、光滑的表面，也可以具有织构化结构。
如无特别说明，本公开实施例中涉及的诸如“层”、“区域”等某个部件位于或者设置在另一个部件之上时，该部件可以直接位于或者设置在另一个部件上，二者之间没有其他部件，也可以间接位于或者设置在另一个部件上，二者之间存在一个或者多个中间部件。
在本公开实施例一种可选的实施方式，钝化层2直接设置在晶体硅基体1的一侧表面上，载流子收集层3直接设置在钝化层2上。本公开实施例中，可根据实际需要在晶体硅基体1和钝化层2之间，和/或载 流子收集层3和钝化层2之间设置其他结构，可以理解的是，在晶体硅基体1和钝化层2之间，和/或载流子收集层3和钝化层2之间设置的其他结构上也需设置与钝化层2上的通孔X相对应的通孔X，以使载流子收集层3能够与晶体硅基体1接触。
下面，对本公开实施例提供的晶体硅太阳能电池的制备方法进行说明。
本公开实施例提供的晶体硅太阳能电池的制备方法主要包括提供晶体硅基体1，在晶体硅基体1上形成具有通孔X的钝化层2，在钝化层2上以及晶体硅基体1与钝化层2的通孔X相对的部位上形成载流子收集层3，以及形成与载流子收集层3接触的电极5等步骤。根据上文所述，采用本公开实施例提供的制备方法制得到的晶体硅太阳能电池在具有良好钝化效果的基础上，还具有良好的载流子传输性能，具有较高的光电转换效率。
本公开实施例提供的制备方法中，除上述步骤外，还包括太阳能电池制备过程中必要的晶体硅基体清洗、晶体硅基体表面制绒等步骤。并且，对于不同结构的晶体硅太阳能电池来说，上述各个步骤的先后顺序以及具体实现方式也有不同。下面对不同结构晶体硅太阳能电池的制备方法分别进行说明。
图5及图6所示的第一种晶体硅太阳能电池的制备方法
如图9a～图9g，或者图10a～图10g所示，该太阳能电池的制备方法包括以下步骤。
步骤A01，对晶体硅基体1进行清洗，并在晶体硅基体1的正表面制绒，在晶体硅基体1的正表面形成织构化结构。
该步骤中，可以用氢氧化钠(NaOH)和过氧化氢(H 2O 2)的混合水溶液对晶体硅基体1进行清洗，以去除晶体硅基体1表面污染物及损伤层。
可以利用碱性溶液进行制绒，例如可利用质量浓度为0.5％～5％(例如0.5％、1％、1.5％、2％、2.5％、3％、3.5％、4％、4.5％、5％等)的氢氧化钠水溶液，在75℃～90℃(例如75℃、76℃、78℃、80℃、82℃、84℃、85℃、86℃、88℃、90℃等)的温度下进行制绒。
也可以利用酸性溶液制绒。
制绒后，单晶晶体硅基体1表面的反射率可以为10％～18％(例如10％、11％、12％、13％、14％、15％、16％、17％、18％等)，多晶晶体硅基体1表面的反射率可以为6％～20％(例如6％、7％、8％、9％、10％、11％、12％、13％、14％、15％、16％、17％、18％、19％、20％等)。
若晶体硅基体1的背表面也需要制绒，则可以在该步骤中同时完成晶体硅基体1正表面和背表面的制绒。
步骤A02，在晶体硅基体1的一侧形成钝化层2。
可以理解的是，当钝化层2设置在晶体硅基体1正表面一侧时，该步骤具体为在晶体硅基体1的正表面一侧形成钝化层2；当钝化层2设置在晶体硅基体1背表面一侧时，该步骤具体为在晶体硅基体1的背表面一侧形成钝化层2。
可根据钝化层2具体的组成来选择形成钝化层2的工艺，包括但不限于原子层沉积(Aatomic Layer Deposition，ALD)工艺、或者化学气相沉积(Chemical Vapor Deposition，CVD)工艺等。
对于直接在晶体硅基体1表面形成氧化硅层作为钝化层2的情况来说，还可以采用高温热氧化工艺、硝酸氧化工艺、干式臭氧氧化工艺、湿式臭氧氧化工艺等在晶体硅基体1表面形成氧化硅层。以利用硝酸氧化工艺制备厚度为0.3纳米～100纳米的氧化硅层为例，硝酸的质量浓度可以为1％～20％，例如1％、2％、4％、5％、6％、8％、10％、12％、14％、15％、16％、18％、20％等，用硝酸处理的时间可以为2分钟～20分钟，例如2分钟、4分钟、5分钟、6分钟、8分钟、10分钟、12分钟、14分钟、15分钟、16分钟、18分钟、20分钟等。
步骤A03，在钝化层2上开设通孔X。
该步骤中，根据设定好的通孔X的图案，去除钝化层2对应的部位，在钝化层2上形成通孔X。
可采用激光刻蚀工艺或者化学腐蚀掩膜工艺在钝化层2上开设通孔X。
可以理解的是，激光刻蚀工艺中，激光图案与钝化层2上的通孔X图案相同；化学腐蚀掩膜工艺中，掩膜镂空区域的图案与钝化层2上的通孔X图案相同。
如果在晶体硅基体1与钝化层2之间、钝化层2与载流子收集层3之间还设置有其他结构，则在该步 骤中可同时完成其他结构的开孔，以使晶体硅基体1上与通孔X相对的部位裸露出来。
步骤A04，在钝化层2上以及晶体硅基体1与钝化层2的通孔X相对的部位(即晶体硅基体1裸露的部位)上形成载流子收集层3。
可根据载流子收集层3具体的组成来选择形成载流子收集层3的工艺。
对于以掺杂硅层作为载流子收集层3的情况来说，可采用以下可选方式来形成掺杂硅层。
方式一，在生长本征硅层的过程中通入掺杂源得到掺杂硅层，即在存在掺杂源的环境中形成掺杂硅层。该方式中，可以以磷烷作为磷元素的掺杂源，以硼烷作为硼元素的掺杂源。在此过程中，加热峰值温度可以为800℃～1000℃，例如800℃、820℃、840℃、850℃、860℃、870℃、880℃、900℃、920℃、940℃、950℃、960℃、980℃、1000℃等，热处理时间可以为30分钟～200分钟，例如30分钟、40分钟、50分钟、60分钟、70分钟、80分钟、90分钟、100分钟、110分钟、120分钟、130分钟、140分钟、150分钟、160分钟、170分钟、180分钟、190分钟、200分钟等。
方式二，首先生长本征硅层，然后向本征硅层中掺杂掺杂元素形成掺杂硅层。
该方式中，向本征硅层中掺杂掺杂元素具体可以为：采用离子注入设备向本征硅层中注入掺杂离子(例如磷离子或者硼离子)，之后进行退火得到掺杂硅层；或者在本征硅层上形成含有掺杂源的硅玻璃层(例如磷硅玻璃PSG或者硼硅玻璃BSG)，之后进行退火使硅玻璃层中的掺杂源进入本征硅层中得到掺杂硅层；或者直接采用热扩散的方式对本征硅层进行掺杂。
上述含掺杂源的硅玻璃可采用APCVD设备制备得到。上述退火过程中的退火温度可以为600℃～950℃，例如600℃、620℃、640℃、650℃、660℃、680℃、700℃、720℃、740℃、750℃、760℃、780℃、800℃、820℃、840℃、850℃、860℃、880℃、900℃、920℃、940℃、950℃等，
上述方式一和方式二中，本征硅层可采用LPCVD设备制备得到。
步骤A05，在晶体硅基体1与钝化层2相对的一侧形成掺杂层6。
可以理解的是，当步骤A02中在晶体硅基体1的正表面一侧形成钝化层2时，该步骤中在晶体硅基体1的背表面一侧形成掺杂层6；当步骤A02中在晶体硅基体1的背表面一侧形成钝化层2时，该步骤中在晶体硅基体1的正表面一侧形成掺杂层6。
该步骤中，掺杂层6的形成方式具体可以为：采用离子注入设备向晶体硅基体1与钝化层2相对的一侧表面注入掺杂离子(例如磷离子或者硼离子)，之后进行退火得到掺杂层6；或者在晶体硅基体1与钝化层2相对的一侧表面上形成含有掺杂源的硅玻璃层(例如磷硅玻璃PSG或者硼硅玻璃BSG)，之后进行退火使硅玻璃层中的掺杂源进入本征硅层中得到掺杂层6；或者直接采用热扩散的方式对晶体硅基体1与钝化层2相对的一侧表面进行掺杂，形成掺杂层6。
需要说明的是，步骤A05可以在步骤A04之后进行(如图10a～图10g所示)，也可在步骤A01之后、步骤A02之前进行(如图9a～图9g所示)。一般来说，当掺杂层6位于晶体硅基体1正表面一侧时，步骤A05在步骤A01和步骤A02之间进行；当掺杂层6位于晶体硅基体1背表面一侧时，步骤A05步骤在步骤A04之后进行。
步骤A06，在载流子收集层3上形成第一减反射层41和/或在掺杂层6上形成第二减反射层42。
第一减反射层41和第二减反射层42的具体形成方式可根据二者的具体组成来确定。例如，对于以氮化硅层作为减反射层4来说，可通过PECVD工艺来形成氮化硅层。
可按照一定的先后顺序分别形成第一减反射层41和第二减反射层42，当一减反射层4和第二减反射层42组成相同时，二者可同时形成。
步骤A07，形成与载流子收集层3接触的第一电极51，形成与掺杂层6接触的第二电极52。
该步骤中，当载流子收集层3和掺杂层6上设置有减反射层4时，则在对应的减反射层4上印刷用于形成第一电极51、第二电极52的浆料，之后进行烧结形成第一电极51和第二电极52。
如果载流子收集层3和/或掺杂层6上未设置减反射层4时，则直接在载流子收集层3和/或掺杂层6上印刷用于形成第一电极51、第二电极52的浆料。
烧结的条件可根据具体浆料的成分进行确定，例如可在600℃～900℃(例如600℃、620℃、640℃、650℃、660℃、680℃、700℃、720℃、740℃、750℃、760℃、780℃、800℃、820℃、840℃、850℃、860℃、880℃、900℃等)的温度下对浆料进行烧结。
图7所示的第二种晶体硅太阳能电池的制备方法
如图11a～图11f所示，该太阳能电池的制备方法包括以下步骤。
步骤B01，对晶体硅基体1进行清洗，并在晶体硅基体1的正表面制绒，在晶体硅基体1的正表面形成织构化结构。
对晶体硅基体1清洗、制绒的具体过程可参照上述步骤A01中的描述，在此不再赘述。
步骤B02，在晶体硅基体1一侧形成具有通孔X的第一钝化层21，在晶体硅基体1另一侧形成具有通孔X的第二钝化层22。
上述形成第一钝化层21和第二钝化层22的具体过程可参照步骤A02中的描述，在此不再赘述。
需要说明的是，第一钝化层21和第二钝化层22可按先后顺序分别形成，当第一钝化层21和第二钝化层22组成相同时，二者可同时形成。
步骤B03，分别在第一钝化层21和第二钝化层22上开设通孔X。
在第一钝化层21和第二钝化层22上开设通孔X的具体方式可参照上述步骤A03的描述，在此不再赘述。
步骤B04，在第一钝化层21上以及晶体硅基体1与第一钝化层21的通孔X相对的部位上形成第一载流子收集层31，在第二钝化层22上以及晶体硅基体1与第二钝化层22的通孔X相对的部位上形成与第一载流子导电类型相反的第二载流子收集层32。
第一载流子收集层31和第二载流子收集层32的具体形成方式可参照上述步骤A04中的描述，在此不再赘述。
需要说明的是，当采用先形成本征硅层，再对本征硅层进行掺杂的方式形成掺杂硅层时，可先同时在第一钝化层21上形成第一本征硅层和在第二钝化层22上形成第二本征硅层，之后再对第一本征硅层和第二本征硅层进行掺杂。可选地，在掺杂过程中，先分别对第一本征硅层和第二本征硅层进行离子注入，或者先分别在第一本征硅层和第二本征硅层上形成含掺杂源的硅玻璃之后，进行一次退火完成对第一本征硅层和第二本征硅层的掺杂。
步骤B05，在第一载流子收集层31上形成第一减反射层41和/或在第二载流子收集层32上形成第二减反射层42。
该步骤中，第一减反射层41和第二减反射层42的具体形成方式可参照步骤A06中的描述，在此不再赘述。
步骤B06，形成与第一载流子收集层31接触的第一电极51，形成与第二载流子收集层32接触的第二电极52。
该步骤中，当第一载流子收集层31和第二载流子收集层32上设置有减反射层4时，则在对应的减反射层4上印刷用于形成第一电极51、第二电极52的浆料，之后进行烧结形成第一电极51和第二电极52。
如果第一载流子收集层31和/或第二载流子收集层32上未设置减反射层4，则直接在第一载流子收集层31和/或第二载流子收集层32上印刷用于形成第一电极51、第二电极52的浆料。
用于形成第一电极51、第二电极52的浆料的烧结条件可参照上述步骤A07中的描述，在此不再赘述。
图8所示的第三种晶体硅太阳能电池的制备方法
如图12a～图12g所示，该太阳能电池的制备方法包括以下步骤。
步骤C01，对晶体硅基体1进行清洗，并在晶体硅基体1的正表面制绒，在晶体硅基体1的正表面形成织构化结构。
对晶体硅基体1清洗、制绒的具体过程可参照上述步骤A01中的描述，在此不再赘述。
步骤C02，在晶体硅基体1的一侧形成钝化层2。
形成钝化层2的具体过程可参照上述步骤A02中的描述，在此不再赘述。
步骤C03，在钝化层2上开设通孔X。
在钝化层2上开设通孔X的具体过程可参照上述步骤A03中的描述，在此不再赘述。
步骤C04，在钝化层2上以及晶体硅基体1与钝化层2的通孔X相对的部位上形成具有导电类型相反的第一区域301和第二区域302的载流子收集层3。
对于以掺杂硅层作为载流子收集层3的情况来说，可首先生长本征硅层，然后利用导电类型相反的第一掺杂原和第二掺杂原对本征硅层的不同区域进行掺杂来形成具有导电类型相反的第一区域301和第二区 域302的掺杂硅层。
可采用离子注入设备向本征硅层的不同区域注入不同的掺杂离子，例如注入磷离子和硼离子，之后进行退火得到具有磷掺杂区域和硼掺杂区域的掺杂硅层。
该步骤中，本征硅层的具体形成方式、离子注入及退火的具体过程可参照上述步骤A04的描述，在此不再赘述。
步骤C05，在晶体硅基体1与载流子收集层3相对的一侧形成与晶体硅基体1导电类型相同的掺杂层6。
掺杂层6的具体形成方式可参照上述步骤A05的描述，在此不再赘述。
需要说明的是，步骤C05可以在步骤C04之后进行，也可在步骤C01之后、步骤C02之前进行。
步骤C06，在载流子收集层3上形成第一减反射层41和/或在掺杂层6上形成第二减反射层42。
第一减反射层41、第二减反射层42的具体形成方式可参照步骤A06中的描述，在此不再赘述。
步骤C07，形成与载流子收集层3的第一区域301接触的第一电极51，形成与载流子收集层3的第二区域302接触的第二电极52。
该步骤中，当载流子收集层3上设置有第一减反射层41时，则在第一减反射层41上与载流子收集层3的第一区域301相对应的位置印刷用于形成第一电极51的浆料，在第一减反射层41上与载流子收集层3的第二区域302相对应的位置印刷用于形成第二电极52的浆料，之后进行烧结形成第一电极51和第二电极52。
如果载流子收集层3上未设置第一减反射层41，则直接在载流子收集层3的第一区域301和第二区域302印刷用于形成第一电极51、第二电极52的浆料。
用于形成第一电极51、第二电极52的浆料的烧结条件可参照上述步骤A07中的描述，在此不再赘述。
基于上述的晶体硅太阳能电池，本公开实施例还提供了应用上述晶体硅太阳能电池的光伏组件。该光伏组件包括依次设置的盖板、第一封装胶膜、电池串、第二封装胶膜和背板，其中，电池串包括多个本公开实施例提供的晶体硅太阳能电池。
可以理解的是，由于本公开实施例提供的晶体硅太阳能电池中，钝化层上设置有通孔，载流子收集层通过钝化层上的通孔与晶体硅基体接触，从而在保证表面钝化效果的基础上，载流子可穿过晶体硅基体与载流子收集层接触的界面被电极收集，实现载流子的有效传输，提高晶体硅太阳能电池的光电转换效率，进而提高应用该晶体硅太阳电池的光伏组件具有较高的输出功率，降低度电成本，提高光伏发电的性价比。
本公开实施例中，盖板为玻璃板，第一封装胶膜和第二封装胶膜的材料可以为EVA(乙烯—醋酸乙烯共聚物)或者POE(乙烯—辛烯共聚物)，背板可以为玻璃板，也可以为TPT(PVF/PET/PVF)板。光伏组件还包括边框，边框内可填充密封胶(例如硅胶)。
本公开实施例提供的光伏组件中，晶体硅太阳能电池可以是正方形或者带有圆角的正方形的整片电池片，也可以是对整片电池片进行切割得到的切片电池片。
本公开实施例提供的光伏组件可以包括多串电池串，每一串电池串中的电池片之间可以通过焊带连接，也可以通过导电胶或者其他导电材料连接。每一串电池串中，相邻的电池片之间可以留有一定间隙，也可以使相邻的电池片的边缘重叠，即采用叠瓦方式连接。
综上所述，本公开实施例通过在钝化层上开设通孔，并且使载流子收集层通过钝化层上的通孔与晶体硅基体接触，从而在保证表面钝化效果的基础上，使得载流子可穿过晶体硅基体与载流子收集层接触的界面被电极收集，实现载流子的有效传输，降低晶体硅太阳能电池的串联电阻，提高晶体硅太阳能电池的填充因子，进而提高晶体硅太阳能电池的光电转换效率，降低度电成本，提高光伏发电的性价比。
以上所述仅是为了便于本领域的技术人员理解本公开的技术方案，并不用以限制本公开。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (10)

  1. 晶体硅太阳能电池，包括：
    晶体硅基体(1)，
    设置在所述晶体硅基体(1)上的具有通孔(X)的钝化层(2)，
    设置在所述钝化层(2)上的载流子收集层(3)，以及，
    与所述载流子收集层(3)接触的电极(5)；
    其中，所述载流子收集层(3)通过所述钝化层(2)上的通孔(X)与所述晶体硅基体(1)接触。
  2. 根据权利要求1所述的晶体硅太阳能电池，其特征在于，在沿着平行于所述晶体硅基体(1)表面的方向上，所述通孔(X)的截面形状为线形、圆形或者多边形。
  3. 根据权利要求1所述的晶体硅太阳能电池，其特征在于，所述钝化层(2)上设置有多个通孔(X)。
  4. 根据权利要求1～3任一项所述的晶体硅太阳能电池，其特征在于，所述电极(5)具有与所述钝化层(2)上的通孔(X)对应的部分。
  5. 根据权利要求1所述的晶体硅太阳能电池，其特征在于，所述晶体硅太阳能电池还包括：设置在所述载流子收集层(3)上的减反射层(4)；所述电极(5)穿过所述减反射层(4)与所述载流子收集层(3)接触。
  6. 晶体硅太阳能电池，包括：
    晶体硅基体(1)，
    设置在所述晶体硅基体(1)一侧的具有通孔(X)的钝化层(2)，
    设置在所述钝化层(2)上的载流子收集层(3)，
    与所述载流子收集层(3)接触的第一电极(51)，
    设置在所述晶体硅基体(1)另一侧的掺杂层(6)，以及，
    与所述掺杂层(6)接触的第二电极(52)；
    其中，所述载流子收集层(3)通过所述钝化层(2)上的通孔(X)与所述晶体硅基体(1)接触；
    所述载流子收集层(3)的导电类型与所述掺杂层(6)的导电类型相反。
  7. 晶体硅太阳能电池，包括：
    晶体硅基体(1)，
    设置在所述晶体硅基体(1)一侧的具有通孔(X)的第一钝化层(21)，
    设置在所述第一钝化层(21)上的第一载流子收集层(31)，
    一与所述第一载流子收集层(31)接触的第一电极(51)，
    设置在所述晶体硅基体(1)另一侧的具有通孔(X)的第二钝化层(22)，
    设置在所述第二钝化层(22)上的第二载流子收集层(32)，以及，
    与所述第二载流子收集层(32)接触的第二电极(52)；
    其中，所述第一载流子收集层(31)通过所述第一钝化层(21)上的通孔(X)与所述晶体硅基体(1)接触；所述第二载流子收集层(32)通过所述第二钝化层(22)上的通孔(X)与所述晶体硅基体(1)接触；
    所述第一载流子收集层(31)与所述第二载流子收集层(32)的导电类型相反。
  8. 晶体硅太阳能电池，包括：
    晶体硅基体(1)，
    设置在所述晶体硅基体(1)一侧的具有通孔(X)的钝化层(2)，
    设置在所述钝化层(2)上、且具有导电类型相反的第一区域(301)和第二区域(302)的载流子收集层(3)，
    与所述载流子收集层(3)的第一区域(301)接触的第一电极(51)，
    与所述载流子收集层(3)的第二区域(302)接触的第二电极(52)，以及，
    设置在所述晶体硅基体(1)另一侧的掺杂层(6)；
    其中，所述载流子收集层(3)通过所述钝化层(2)上的通孔(X)与所述晶体硅基体(1)接触；
    所述掺杂层(6)的导电类型与所述晶体硅基体(1)的导电类型相同。
  9. 晶体硅太阳能电池的制备方法，包括：
    提供晶体硅基体(1)；
    在所述晶体硅基体(1)上形成具有通孔(X)的钝化层(2)；
    在所述钝化层(2)上以及所述晶体硅基体(1)与所述钝化层(2)的通孔(X)相对的部位上形成载流子收集层(3)；
    形成与所述载流子收集层(3)接触的电极(5)。
  10. 光伏组件，包括：依次设置的盖板、第一封装胶膜，电池串、第二封装胶膜和背板，所述电池串包括多个太阳能电池，其特征在于，所述太阳能电池为权利要求1～8任一项所述的晶体硅太阳能电池。
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MY200704A (en) 2024-01-11
EP3886181B1 (en) 2025-12-17
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CN113330583B (zh) 2023-07-07
US11961930B2 (en) 2024-04-16
CN209389043U (zh) 2019-09-13
KR20210062096A (ko) 2021-05-28
AU2019390365A1 (en) 2021-06-17
US20220029040A1 (en) 2022-01-27
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