WO2020199036A1 - 电感器件布线架构、集成电路及通信设备 - Google Patents

电感器件布线架构、集成电路及通信设备 Download PDF

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Publication number
WO2020199036A1
WO2020199036A1 PCT/CN2019/080664 CN2019080664W WO2020199036A1 WO 2020199036 A1 WO2020199036 A1 WO 2020199036A1 CN 2019080664 W CN2019080664 W CN 2019080664W WO 2020199036 A1 WO2020199036 A1 WO 2020199036A1
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WIPO (PCT)
Prior art keywords
metal layer
metal
dummy
inductance device
inductor
Prior art date
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PCT/CN2019/080664
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English (en)
French (fr)
Inventor
叶辉
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to PCT/CN2019/080664 priority Critical patent/WO2020199036A1/zh
Priority to CN201980094514.9A priority patent/CN113614915B/zh
Priority to EP19923130.9A priority patent/EP3937232B1/en
Publication of WO2020199036A1 publication Critical patent/WO2020199036A1/zh
Priority to US17/489,649 priority patent/US12354954B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H01F17/0006—Printed inductances
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/20—Inductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/497—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H01F17/0006—Printed inductances
    • H01F2017/0046—Printed inductances with a conductive path having a bridge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H01F17/0006—Printed inductances
    • H01F2017/0073—Printed inductances with a special conductive pattern, e.g. flat spiral
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H01F17/0006—Printed inductances
    • H01F2017/008—Electric or magnetic shielding of printed inductances

Definitions

  • This application relates to the field of integrated circuit technology, and in particular to an inductive device wiring architecture, an integrated circuit and a communication device.
  • radio frequency integrated circuit With the rapid development of wireless communication technology, radio frequency integrated circuit (RFIC) has become more and more important.
  • the radio frequency integrated circuit can work at a frequency of 300 megahertz (MHz) to 300 gigahertz (GHz). Integrated circuits in the range.
  • MHz megahertz
  • GHz gigahertz
  • the integrated circuit connects multiple layers of electronic components through metal wires to form a complete logic circuit.
  • CMP chemical mechanical polishing
  • a common approach is to add dummy metal to the bottom metal of the metal wire to increase the metal arrangement area.
  • the virtual metal under the inductor will affect the performance of the inductor, resulting in poor performance of the inductor.
  • the embodiments of the present application provide an inductive device wiring structure, an integrated circuit, and a communication device.
  • the inductive device wiring structure can reduce the adverse effects on the performance of the inductive device and improve the product yield.
  • an embodiment of the present application provides a wiring structure for an inductor device.
  • the inductive device wiring structure can be applied to integrated circuits.
  • the inductance device wiring structure includes an inductance device and a plurality of dummy metals located under the inductance device.
  • the plurality of dummy metals are arranged in a multi-layer metal layer, and each metal layer in the multi-layer metal layer corresponds to a part of the dummy metal of the plurality of dummy metals, in a direction away from the inductance device,
  • the arrangement area of the dummy metal corresponding to at least two metal layers in the multi-layer metal layer is increased. That is, the arrangement area of the dummy metal corresponding to the at least two metal layers located under the inductance device increases.
  • the arrangement area of the dummy metal corresponding to at least two metal layers of the multilayer metal layer under the inductance device increases. At this time, the arrangement area of the dummy metal corresponding to the metal layer close to the inductance device is smaller, and the arrangement area of the dummy metal corresponding to the metal layer far from the inductance device is larger.
  • each metal layer under the inductance device has a relatively sufficient metal arrangement area, which can meet the processing requirements of chemical mechanical polishing, thereby improving the processing quality, so that the inductance device wiring structure and the application of the inductance device wiring structure The yield rate of integrated circuits is relatively high.
  • the space below the inductance device includes a space projected along the vertical direction of the metal layer where the inductance device is located in the wiring area of the inductance device.
  • the wiring area of the inductance device includes at least the area surrounded by the outer edge of the outermost wire of the inductance device.
  • the plurality of dummy metals are arranged in a stepped manner. That is, in the multi-layer metal layer below the inductance device, the dummy metal corresponding to the metal layer located below extends relative to the dummy metal corresponding to the metal layer located above to form a stepped shape.
  • the plurality of dummy metals under the inductance device are arranged in a stepped manner, the plurality of dummy metals can effectively improve the arrangement of the metals under the inductance device, so that the inductance
  • the device obtains higher manufacturing precision during the chemical mechanical polishing process, the product yield of the inductive device wiring structure and the integrated circuit using the inductive device wiring structure is higher, and the plurality of dummy metals can be arranged as little as possible It is arranged in the area close to the inductance device and arranged in the area far away from the inductance device, thereby reducing the bad influence of the virtual metal on the performance of the inductance device, and making the performance of the inductance device better.
  • the inductive device wiring structure may further include a plurality of dummy metals arranged in the same layer as the inductive device.
  • Part of the dummy metal arranged on the same layer as the inductance device may be arranged in a stepped manner together with a plurality of dummy metals located under the inductance device. At this time, part of the dummy metal arranged on the same layer as the inductive device has less impact on the performance of the inductive device, and the processing quality of the inductive device is higher, and the product yield rate of the inductive device wiring structure is higher .
  • the arrangement area of the dummy metal corresponding to the at least three metal layers adjacent to each other increases in a direction away from the inductance device.
  • the plurality of dummy metals under the inductance device present a continuous stepped shape, which is beneficial to further improve the processing quality of the inductance device wiring structure, and the plurality of dummy metals have less influence on the performance of the inductance device .
  • the arrangement area of the dummy metal corresponding to the i-th metal layer under the inductive device is equal to the arrangement area of the dummy metal corresponding to the i-1th metal layer, and the i-th metal layer is located at the The i-1th metal layer is away from the side of the inductance device, and i is an integer and greater than or equal to 2.
  • the lower part of the inductance device when the inductance device wiring structure satisfies the general arrangement rule from comb to dense, the lower part of the inductance device includes two metal layers with the same arrangement area corresponding to the dummy metal, so that the The arrangement of the plurality of dummy metals in the inductance device wiring structure is more flexible, and the arrangement manners are more diversified.
  • the plurality of dummy metals corresponding to the i-th metal layer are arranged at equal intervals, and the arrangement interval between two adjacent dummy metals is the i-th interval; the i-1th metal
  • the multiple virtual metals corresponding to the layers are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals is the i-1th interval; the i-1th interval is smaller than the ith interval.
  • the metal arrangement area of the i-th metal layer does not increase, the arrangement range of the plurality of dummy metals corresponding to the i-th metal layer is relatively large and the arrangement is relatively uniform, which can effectively improve the metal layer
  • the processing quality makes the product yield of the inductive device wiring structure higher.
  • the arrangement area of the dummy metal corresponding to the jth metal layer under the inductive device is smaller than the arrangement area of the dummy metal corresponding to the j-1th metal layer, and the jth metal layer is located at the The j-1th metal layer is far from the side of the inductance device, and j is an integer and greater than or equal to 2.
  • the lower part of the inductive device when the inductive device wiring structure satisfies the arrangement rule from comb to dense, the lower part of the inductive device includes two metal layers inverted corresponding to the arrangement area of the virtual metal, so that the The arrangement of the plurality of dummy metals in the inductance device wiring structure is more flexible, and the arrangement manners are more diversified.
  • the plurality of dummy metals corresponding to the jth metal layer are arranged at equal intervals, and the arrangement interval between two adjacent dummy metals is the jth interval; the j-1th metal
  • the multiple virtual metals corresponding to the layers are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals is the j-1th interval; the j-1th interval is smaller than the jth interval.
  • the multiple virtual metals corresponding to the j-th metal layer with a smaller metal arrangement area have a larger arrangement range and a more uniform arrangement, which can effectively improve the processing quality of the metal layer, so that the inductance device wiring structure The product yield rate is higher.
  • the number of dummy metals corresponding to each metal layer is multiple, and each layer The dummy metal corresponding to the metal layer is arranged crosswise with the dummy metal corresponding to the adjacent metal layer.
  • the arrangement of the plurality of dummy metals under the inductive device is relatively regular, which is beneficial to reducing the design cost and the production cost of the wiring structure of the inductive device.
  • the number of the dummy metal in each metal layer is multiple, and each layer is The dummy metal corresponding to the metal layer is aligned with the dummy metal corresponding to the adjacent metal layer.
  • the arrangement of the plurality of dummy metals under the inductive device is relatively regular, which is beneficial to reducing the design cost and the production cost of the wiring structure of the inductive device.
  • the number of dummy metals corresponding to each layer of the metal layer is multiple, and one or more The virtual metal corresponding to the metal layer is arranged crosswise with the virtual metal corresponding to the adjacent metal layer, and the virtual metal corresponding to one or more layers of the metal layer is aligned with the virtual metal corresponding to the adjacent metal layer.
  • part of the virtual metal under the inductive device of the inductive device wiring structure is aligned and part of the virtual metal is arranged crosswise, which enriches the arrangement of the plurality of virtual metals, so that the arrangement of the inductive device wiring structure
  • the cloth method is more diversified.
  • the inductance device is an inductor with two ports or a transformer with four ports.
  • Inductors with dual ports include, but are not limited to, spiral inductors, differential inductors, etc.
  • the inductance device can have multiple implementation structures, and the inductance device wiring structure has a wider application range.
  • the inductance devices are arranged in the same metal layer; or, the inductance device includes an upper inductance and a lower inductance, and the upper inductance and the lower inductance are arranged on two adjacent ones. Layer metal layer.
  • the upper inductance and the lower inductance can be connected by conductive materials, so that the inductance device is used as a multilayer metal series inductor.
  • the inductance device can have multiple implementation structures, and the inductance device wiring structure has a wider application range.
  • an embodiment of the present application also provides an integrated circuit, including the inductive device wiring structure described in any one of the above. Since the wiring structure of the inductance device is low in cost and has little adverse effect on the performance of the inductance device, the integrated circuit has low cost and good performance.
  • an embodiment of the present application also provides a communication device including the above-mentioned integrated circuit.
  • FIG. 1 is a schematic structural diagram of an integrated circuit provided by an embodiment of the present application.
  • FIG. 2 is a top view of the wiring structure of the inductance device shown in FIG. 1 in the first embodiment
  • FIG. 3 is a schematic cross-sectional view of a part of the inductance device wiring structure shown in FIG. 2 taken along the line A-A;
  • FIG. 4 is a top view of the wiring structure of the inductance device shown in FIG. 1 in the second embodiment
  • FIG. 5 is a schematic cross-sectional view of a part of the inductance device wiring structure shown in FIG. 4 taken along the line B-B;
  • FIG. 6 is a partial structural diagram of the inductance device wiring structure shown in FIG. 1 in the third embodiment
  • FIG. 7 is a partial structural diagram of the inductance device wiring structure shown in FIG. 1 in the fourth embodiment.
  • FIG. 8 is a schematic structural diagram of the inductance device wiring structure shown in FIG. 1 in the fifth embodiment
  • FIG. 9 is a partial structural diagram of the inductance device wiring structure shown in FIG. 1 in the sixth embodiment.
  • FIG. 10 is a schematic structural diagram of the inductance device wiring structure shown in FIG. 1 in the seventh embodiment
  • FIG. 11 is a schematic structural diagram of the inductance device wiring structure shown in FIG. 1 in the eighth embodiment.
  • FIG. 12 is a partial structural diagram of the inductance device wiring structure shown in FIG. 1 in the ninth embodiment
  • FIG. 13 is a partial structural diagram of the inductance device wiring structure shown in FIG. 1 in the tenth embodiment
  • FIG. 14 is an implementation structure of the inductance device of the inductance device wiring structure shown in FIG. 1;
  • 15 is another implementation structure of the inductor device of the inductor device wiring structure shown in FIG. 1;
  • 16 is another implementation structure of the inductance device of the inductance device wiring structure shown in FIG. 1;
  • FIG. 17 is another implementation structure of the inductance device of the inductance device wiring structure shown in FIG. 1;
  • FIG. 18 is another implementation structure of the inductance device of the inductance device wiring structure shown in FIG. 1;
  • FIG. 19 is another implementation structure of the inductance device of the inductance device wiring structure shown in FIG. 1.
  • the embodiment of the present application provides a communication device.
  • the communication device can be a wireless fidelity (Wi-Fi) device, a bluetooth device, an infrared device, a global positioning system (GPS) device, a near-field communication (NFC) device ) Equipment, mobile communication equipment, routers, optoelectronic equipment, base stations, microwave equipment, etc.
  • the communication equipment includes an integrated circuit (IC).
  • communication equipment includes high frequency integrated circuit (HFIC).
  • HFIC high frequency integrated circuit
  • the high frequency integrated circuit is an integrated circuit with an operating frequency greater than 100 megahertz (MHz).
  • MHz megahertz
  • the high-frequency integrated circuit may be a radio frequency integrated circuit (RFIC).
  • Radio frequency integrated circuits can work in the range of 300 megahertz to 300 gigahertz (GHz) to achieve specific radio frequency functions.
  • the integrated circuit includes an inductive device wiring structure.
  • the inductive device wiring structure includes inductive devices.
  • Inductance devices are one of the most important devices in integrated circuits. They are combined with resistors, capacitors, metal-oxide-semiconductor field-effect transistors (MOSFETs), and bipolar junction transistors (BJT) ), diodes and other devices are connected together through a special circuit structure to form an integrated circuit.
  • the integrated circuit has functions such as control, calculation and memory.
  • the integrated circuit may include one or more circuit modules.
  • the circuit module may include, but is not limited to, a Voltage Control Oscillator (VCO), a Low-noise Amplifier (LNA), a mixer, and a trans-impedance amplifier.
  • VCO Voltage Control Oscillator
  • LNA Low-noise Amplifier
  • mixer mixer
  • trans-impedance amplifier One or more of TIA), variable gain amplifier (VGA), or driver.
  • Inductance devices are widely used in these circuit modules.
  • FIG. 1 is a schematic structural diagram of an integrated circuit 100 according to an embodiment of the present application.
  • the integrated circuit 100 includes a substrate 110 and a multilayer metal layer 120 and a multilayer insulating layer 130 formed on the substrate 110. At least one insulating layer 130 is provided between any two adjacent metal layers 120.
  • the substrate 110 may be silicon material, glass material or ceramic material.
  • the material of the metal layer 120 may include one or more of copper, aluminum, silver, nickel, gold, titanium, indium, tungsten, or alloys thereof.
  • the material of the insulating layer 130 may include one or more of an electrically insulating polymer, an electrically insulating ceramic, or a dielectric material.
  • the metal layer 120 is a patterned metal layer. There are many ways to shape the patterned metal layer, for example:
  • the manufacturing method of the patterned metal layer includes: first, forming a groove on the insulating substrate according to the layout of the patterned metal layer. Then, metal deposition is deposited on the insulating substrate, so that the metal material fills the groove and overflows out of the groove. Then, the metal material overflowing out of the groove is removed by chemical-mechanical polishing (CMP). At this time, the metal materials remaining in the groove together form a patterned metal layer.
  • CMP chemical-mechanical polishing
  • the manufacturing method of the patterned metal layer includes: first depositing a metal film, then depositing a photoresist on the metal film, and then performing exposure, development (photolithography) and engraving through a mask. An etching process is used to pattern the metal film, and finally the patterned metal film is planarized to form a patterned metal layer.
  • the planarization process usually uses chemical mechanical polishing.
  • chemical mechanical polishing is usually required in the final step.
  • the degree of completion of chemical mechanical polishing usually depends on the metal arrangement area of the metal layer to be processed and the metal arrangement area of the underlying metal layer of the metal layer to be processed. If the metal arrangement area is insufficient, less grinding is likely to occur. As a result, the product yield of the patterned metal layer is very low.
  • the integrated circuit 100 includes an inductive device wiring structure 10.
  • the inductive device wiring structure 10 is a part of the integrated circuit 100.
  • the inductor device wiring structure 10 includes a part of the metal layer 120 and a part of the insulating layer 130.
  • the inductance device wiring structure 10 is formed synchronously with other parts of the integrated circuit 100 during the manufacturing process of the integrated circuit 100.
  • the specific number of layers of the inductance device wiring structure 10 may be less than or equal to the number of layers of the integrated circuit 100.
  • the inductive device wiring structure 10 includes an inductive device and a plurality of dummy metals located under the inductive device.
  • the inductance device wiring structure 10 can be stacked with multiple metal layers.
  • the metal layer of the inductor device wiring structure 10 is a part of the corresponding metal layer 120, and the metal layer of the inductor device wiring structure 10 is also a patterned metal layer.
  • the inductor devices are arranged on the top metal layer of the inductor device wiring structure 10.
  • a plurality of dummy metals under the inductor device are arranged in the multilayer metal layer under the inductor device.
  • Each metal layer in the multi-layer metal layer located under the inductance device corresponds to a part of the dummy metal in the plurality of dummy metals located under the inductance device.
  • the arrangement area of the dummy metal corresponding to at least two metal layers of the multilayer metal layer under the inductance device increases.
  • the arrangement area of the dummy metal corresponding to the metal layer close to the inductor device is smaller, and the arrangement area of the dummy metal corresponding to the metal layer far from the inductor device is larger. That is, when multiple dummy metals located under the inductance device are arranged, keep put from the inductance device as far as possible.
  • the area close to the inductance device has less dummy metal, and the area far away from the inductance device has more dummy metal. Reduce the bad influence of virtual metal on the performance of the inductance device, even without affecting the performance of the inductance device.
  • the metal layers under the inductor device have a relatively sufficient metal layout area, which can meet the processing requirements of chemical mechanical polishing, thereby improving the processing quality, so that the inductor device wiring structure 10 and the integrated circuit using the inductor device wiring structure 10 The product yield is higher.
  • FIG. 2 is a top view of the inductive device wiring structure 10 shown in FIG. 1 in the first embodiment
  • FIG. 3 is a part of the structure of the inductive device wiring structure 10 shown in FIG. 2 along the line AA Schematic cross-section cut.
  • the number of virtual metals 3 in each metal layer 2 in FIG. 3 is slightly reduced, but the overall arrangement law remains unchanged.
  • the inductance device wiring structure 10 includes an inductance device 1 and a plurality of dummy metals 3 located under the inductance device 1.
  • "below” only refers to the direction of the attached drawings. Therefore, the directional terms used are for the purpose of explaining and understanding this application, rather than indicating or implying that the device or element referred to must have a specific orientation and The specific azimuth structure and operation cannot be understood as a limitation of the application.
  • the inductance device 1 may be arranged on the top metal layer 120 of the integrated circuit 100.
  • the underside of the inductance device 1 refers to the space on the side of the inductance device 1 facing the substrate 110 of the integrated circuit 100. That is, the structure or component located under the inductor device 1 is located between the inductor device 1 and the substrate 110.
  • the underside of the inductance device 1 includes the underside of the wiring area of the inductance device 1 (as indicated by the outer dashed frame of the inductance device 1 in FIG. 2). That is, the space below the inductance device 1 includes the space where the wiring area of the inductance device 1 is projected along the vertical direction of the plane where the inductance device 1 is located.
  • the wiring area of the inductor device 1 covers the entire inductor device 1.
  • the wiring area of the inductance device 1 at least includes: the area surrounded by the outer edge of the outermost wire of the inductance device 1.
  • the aforementioned “vertical direction” is not strictly limited to a direction that forms an angle of 90° with the plane where the inductance device 1 is located, and may also be a direction close to 90°.
  • a plurality of dummy metals 3 under the inductance device 1 are located in the space under the inductance device 1.
  • the inductance device wiring structure 10 includes a multilayer metal layer 2 arranged in a stack.
  • the metal layer 2 is a part of the metal layer 120 of the corresponding integrated circuit 100.
  • a plurality of dummy metals 3 under the inductor device 1 are arranged in the multilayer metal layer 2 under the inductor device 1.
  • Each metal layer 2 in the multilayer metal layer 2 under the inductor device 1 includes a plurality of corresponding dummy metals 3 to increase the metal arrangement area of the metal layer 2.
  • the multilayer metal layer 2 under the inductor device 1 is the bottom structure of the inductor device 1.
  • a plurality of dummy metals 3 corresponding to the metal layer 2 under the inductance device 1 are spaced apart from each other.
  • two or more virtual metals 3 may also be combined into a continuous virtual metal with a larger area.
  • a plurality of disconnected virtual metals 3 in the embodiment shown in FIG. 2 may be combined into one continuous virtual metal.
  • the dummy metals 3 located in the two adjacent metal layers 2 may be connected through conductive materials in the via holes, or they may not be connected to each other.
  • the inductance device 1 is located on the first metal layer 21. Since the inductance device 1 is provided on the first metal layer 21, it can be processed to a larger thickness, thereby reducing resistance and improving the quality factor Q. There are second metal layers 22 to fifth metal layers 25 below the inductor device 1. The second metal layer 22 to the fifth metal layer 25 are the bottom structure of the inductor device 1. The plurality of dummy metals 3 under the inductor device 1 are arranged in the second metal layer 22, the third metal layer 23, the fourth metal layer 24 and the fifth metal layer 25.
  • the inductive device wiring structure 10 further includes a plurality of dummy metals 3 arranged on the metal layer 2 where the inductive device 1 is located.
  • the first metal layer 21 further includes a plurality of dummy metals 3, and the plurality of dummy metals 3 are arranged around the inductance device 1 and are arranged away from the inductance device 1.
  • the dummy metal 3 may also be arranged in the middle space.
  • the arrangement area of the dummy metal corresponding to the at least two metal layers 2 located under the inductance device 1 increases.
  • the arrangement area of the dummy metal corresponding to the metal layer 2 is the total arrangement area of the dummy metal 3 in the metal layer 2 under the inductor device 1.
  • the metal layer 2 with a larger arrangement area of the dummy metal 3 has a larger metal arrangement ratio.
  • the plurality of dummy metals 3 located under the inductance device 1 are arranged less in the area close to the inductance device 1 and more arranged in the area far away from the inductance device 1, thereby reducing the adverse effect on the performance of the inductance device 1. .
  • each metal layer 2 of the inductive device wiring structure 10 has a relatively sufficient metal layout area, which can meet the processing requirements of chemical mechanical polishing, so that the first metal layer 21 has good flatness. Therefore, the inductance device 1 has few metal residues and high processing quality, thereby reducing the risk of short circuits in the circuit, so that the inductance device wiring structure 10 and the integrated circuit 100 using the inductance device wiring structure 10 have a higher product yield.
  • the inductance device wiring structure 10 can increase the metal arrangement area of each metal layer 2 while reducing the adverse effects of the dummy metal 3 on the inductance device performance of the inductance device 1, thereby improving the product yield.
  • a plurality of dummy metals 3 located under the inductance device 1 are arranged in a stepped manner. That is, in the multi-layer metal layer 2 located below the inductance device 1, the dummy metal 3 corresponding to the metal layer 2 located below extends relative to the dummy metal 3 corresponding to the metal layer 2 located above to form a stepped shape. For example, in FIG. 3, the dummy metal 3 corresponding to the third metal layer 23 protrudes relative to the dummy metal 3 corresponding to the second metal layer 22 to form a stepped shape.
  • the dummy metal 3 located in the different metal layer 2 in the inductor device wiring structure 10 is filled with different patterns to distinguish.
  • the inductance device 1 and dummy metal 3 of the first metal layer 21 are filled with black patterns
  • the dummy metal 3 of the second metal layer 22 is filled with oblique lines
  • the dummy metal 3 of the third metal layer 23 is not filled with patterns (that is, White background).
  • the dummy metal 3 in the multi-layer metal layer 2 is aligned, and the dummy metal 3 of the bottom structure will be blocked by the dummy metal 3 of the top structure, for example, part of the dummy metal 3 in the second metal layer 22 It is blocked by the dummy metal 3 in the first metal layer 21.
  • a part of the dummy metal 3 in the second metal layer 22 extends relative to the dummy metal 3 in the first metal layer 21, and the relatively extended part of the dummy metal 3 is exposed.
  • the plurality of dummy metals 3 under the inductance device 1 are arranged in a stepped manner, the plurality of dummy metals 3 can effectively improve the metal arrangement under the inductance device 1, so that the inductance device 1 is in a chemical mechanical A higher manufacturing accuracy is obtained during the polishing process, the product yield of the inductor device wiring structure 10 and the integrated circuit 100 using the inductor device wiring structure 10 is higher, and the multiple dummy metals 3 located under the inductor device 1 can be minimized It is arranged in an area close to the inductance device 1 and arranged in an area far away from the inductance device 1, thereby reducing the bad influence of the dummy metal 3 on the inductance device performance of the inductance device 1 and making the performance of the inductance device 1 better.
  • Part of the dummy metal 3 arranged on the metal layer 2 where the inductance device 1 is located and the dummy metal 3 arranged under the inductance device 1 may also be arranged in a stepped manner.
  • the dummy metal 3 corresponding to the second metal layer 22 protrudes relative to the dummy metal 3 corresponding to the first metal layer 21 to form a stepped shape.
  • the plurality of dummy metals 3 of the first metal layer 21 are partially arranged around the inductor device 1 and partially arranged in the middle space surrounded by the inductor device 1.
  • a gap S1 is formed between the dummy metal 3 closest to the inductance device 1 among the dummy metals 3 located in the middle space of the inductance device 1 and the inductance device 1.
  • a gap S2 is formed between two adjacent dummy metals 3 located in the middle space of the inductance device 1. S1 is greater than S2.
  • the dummy metal 3 of the first metal layer 21 has a small effect on the performance of the inductor device 1, and the inductor device 1 has better inductor performance.
  • the distance between the part of the dummy metal 3 located on the outer periphery of the inductance device 1 and the inductance device 1 is greater than the distance between two adjacent dummy metals 3 located on the outer periphery of the inductance device 1.
  • the plurality of dummy metals 3 of the first metal layer 21 may be arranged at equal intervals or unequal intervals, which is not strictly limited in this application.
  • the “spacing” between two adjacent dummy metals 3 in this application refers to the spacing between two dummy metals 3 located on the same side of the inductor device 1.
  • the dummy metals 3 of the first metal layer 21 are approximately arranged in an array (the dummy metals 3 are not arranged in some areas of the array), and the distance between two adjacent dummy metals 3 is approximately equal.
  • the virtual metal 3 of the first metal layer 21 may also be arranged in other ways, for example, approximately in a diffuse ring arrangement, or scattered randomly.
  • the plurality of dummy metals 3 corresponding to the second metal layer 22 are as far away from the inductor device 1 as possible.
  • the second metal layer 22 arranges dummy metal 3 obliquely below a certain section of the trace of the inductor device 1 to maximize the metal arrangement area of the second metal layer 22, thereby improving the product of the inductor device wiring structure 10 Yield rate, and has little effect on the performance of the inductor device 1.
  • the distance S4 between two dummy metals 3 in the space directly below a certain section of the trace of the inductance device 1 is greater than or equal to the gap S5 between two adjacent dummy metals 3.
  • a part of the dummy metal 3 corresponding to the second metal layer 22 extends relative to the dummy metal 3 of the first metal layer 21, and the first metal layer 21 and the second metal layer 22 are close to the inductor device 1.
  • the plurality of dummy metals 3 are generally arranged in a stepped manner.
  • the structure and size design of the dummy metal 3 of the second metal layer 22 can refer to the dummy metal 3 of the first metal layer 21.
  • S5 is equal to S2.
  • the structure and size of the dummy metal 3 of the second metal layer 22 can be designed or different from the dummy metal of the first metal layer 21.
  • S1 can be in the range of 1 micrometer ( ⁇ m) to 15 micrometers.
  • S1 can be set according to the range of the electromagnetic field generated by the inductance device 1.
  • S2 can be in the range of 0.1 microns to 10 microns.
  • the width of a certain trace of the inductance device 1 is W1.
  • W1 can be in the range of 1 micrometer to 20 micrometers.
  • the width of the dummy metal 3 is W2.
  • W2 can be in the range of 0.1 microns to 10 microns.
  • the thickness direction (ie, Z direction) of the inductance device wiring structure 10 the thickness of the dummy metal 3 is T1.
  • T1 can be in the range of 0.1 microns to 4 microns.
  • the virtual metal 3 can be made of copper or aluminum.
  • the inductance device 1 can be made of copper or aluminum.
  • the material of the inductance device 1 is the same as the material of the dummy metal 3 of the first metal layer 21.
  • the arrangement area of the dummy metal 3 corresponding to the third metal layer 23 is larger than the arrangement area of the dummy metal 3 corresponding to the second metal layer 22. A part of the dummy metal 3 corresponding to the third metal layer 23 protrudes relative to the dummy metal 3 corresponding to the second metal layer 22.
  • the plurality of dummy metals 3 in the first metal layer 21, the second metal layer 22, and the third metal layer 23 are arranged in a stepped manner.
  • one of the dummy metals 3 in the third metal layer 23 is located directly below a certain section of the wiring of the inductance device 1, and the distance between the dummy metal 3 and the section of the wiring of the inductance device 1 is S3.
  • S3 can be in the range of 1 micron to 15 microns.
  • S3 can be designed according to the electromagnetic field range of the inductance device 1.
  • the structure and size design of the dummy metal 3 of the third metal layer 23 can refer to the dummy metal 3 of the first metal layer 21. In other embodiments, the structure and size of the dummy metal 3 of the third metal layer 23 can be designed or can be different from the dummy metal of the first metal layer 21.
  • the inductive device wiring structure 10 further includes a multilayer dielectric layer 4.
  • the dielectric layer 4 is a part of the corresponding insulating layer 130.
  • a dielectric layer 4 is provided between two adjacent metal layers 2. When a gap is formed between the dummy metals 3 in the metal layer 2, an insulating material is filled in the gap to form an insulating part, and the insulating part is connected to the dielectric layer 4.
  • each dielectric layer 4 of the inductance device wiring structure 10 may be the same.
  • the thickness of the dielectric layer 4 is T2.
  • T2 can be in the range of 0.1 microns to 4 microns.
  • the plurality of dummy metals 3 under the inductance device 1 are mainly arranged in a stepped manner.
  • the plurality of dummy metals 3 under the inductance device 1 may also be arranged in other ways under the condition that the processing requirements and performance requirements are met.
  • the plurality of dummy metals 3 under the inductance device 1 have substantially the same shape and size. In other embodiments, the plurality of dummy metals 3 under the inductance device 1 may also have different shapes and different sizes. Similarly, the plurality of dummy metals 3 provided on the same layer as the inductance device 1 may have substantially the same shape and size as the plurality of dummy metals 3 under the inductance device 1, or may be different.
  • the plurality of dummy metals 3 under the inductance device 1 are square.
  • the plurality of virtual metals 3 under the inductance device 1 may also be strips, triangles, circles, ellipses, polygons, special shapes, etc. This application does not strictly limit the shape and size of the virtual metal 3.
  • the inductor device wiring structure 10 further includes a polycrystalline silicon (polycrystalline silicon) layer (not shown in the figure) located under the multilayer metal layer 2.
  • the polysilicon layer includes a plurality of polysilicons, which are used as the PN junction of the integrated circuit 100 (the P-type semiconductor and the N-type semiconductor are made on the same semiconductor substrate, and a space charge area is formed at their interface, which is called PN junction. junction).
  • the arrangement of multiple polysilicons also needs to meet the processing requirements of chemical mechanical polishing, so as to planarize the multilayer metal layer 2.
  • For the arrangement law of multiple polysilicons please refer to the aforementioned arrangement law of multiple dummy metals 3.
  • the polysilicon in the polysilicon layer tends to be arranged far away from the inductor device 1.
  • the arrangement area of the polysilicon in the polysilicon layer and the arrangement area of the metal layer 2 located under the inductor device 1 corresponding to the dummy metal 3 increase in a direction away from the inductor device 1.
  • a plurality of polysilicons and a plurality of dummy metals 3 located under the inductance device 1 may be arranged in a stepped manner.
  • the plurality of dummy metals 3 under the inductance device 1 of the inductance device wiring structure 10 meets the following requirements: when the arrangement pattern is from comb to dense in the direction away from the inductance device 1, there can be multiple Arrangement method, for example:
  • the number of virtual metals 3 corresponding to each metal layer 2 is multiple, and the virtual metal 3 corresponding to each metal layer 2 corresponds to the adjacent metal layer 2.
  • the virtual metal 3 is arranged crosswise.
  • the dummy metal 3 below the inductance device 1 and the dummy metal 3 above or below the dummy metal 3 are generally in a positional relationship that is staggered from each other.
  • the arrangement of the plurality of dummy metals 3 under the inductance device 1 is relatively regular, which is beneficial to reduce the design cost and the production cost.
  • the number of dummy metals 3 corresponding to each metal layer 2 is multiple, and the dummy metal 3 corresponding to each metal layer 2 corresponds to the adjacent metal layer 2
  • the virtual metal 3 or aligned arrangement In other words, the dummy metal 3 below the inductance device 1 and the dummy metal 3 above or below it are substantially in a positional relationship that is directly opposite to each other. At this time, the arrangement of the plurality of dummy metals 3 under the inductance device 1 is relatively regular, which is beneficial to reduce the design cost and the production cost.
  • the number of dummy metals 3 corresponding to each metal layer 2 is multiple, and the dummy metals 3 corresponding to one or more metal layers 2 and adjacent metals
  • the dummy metals 3 corresponding to the layer 2 are arranged crosswise, and the dummy metals 3 corresponding to one or more metal layers 2 are aligned with the dummy metals 3 corresponding to the adjacent metal layers 2.
  • part of the dummy metals 3 under the inductor device 1 of the inductance device wiring structure 10 are aligned and some of the dummy metals 3 are arranged crosswise, which enriches the arrangement of the virtual metals 3, and makes the arrangement of the inductance device wiring structure 10 more diversification.
  • the dummy metal 3 corresponding to each metal layer 2 is aligned with the dummy metal 3 corresponding to the adjacent metal layer 2.
  • the dummy metals 3 corresponding to the second metal layer 22 to the fifth metal layer 25 are aligned.
  • FIG. 4 is a top view of the inductive device wiring structure 10 shown in FIG. 1 in the second embodiment
  • FIG. 5 is a part of the structure of the inductive device wiring structure 10 shown in FIG. 4 along the line BB Schematic cross-section cut.
  • the number of virtual metals 3 in each metal layer 2 in FIG. 5 is slightly reduced, but the overall arrangement law remains unchanged. Most of the technical content in this embodiment that is the same as the foregoing embodiment will not be repeated.
  • the dummy metal 3 corresponding to each metal layer 2 and the dummy metal 3 corresponding to the adjacent metal layer 2 are arranged crosswise.
  • the layer structure under the inductor device 1 has a more uniform metal arrangement area, which is beneficial to improve the processing accuracy of the inductor device 1 and makes the product yield of the inductor device wiring structure 10 higher.
  • the inductive device wiring structure 10 includes a first metal layer 21, a second metal layer 22, a third metal layer 23, a fourth metal layer 24, and a fifth metal layer 25.
  • the dummy metals 3 corresponding to the second metal layer 22, the third metal layer 23, the fourth metal layer 24, and the fifth metal layer 25 under the inductor device 1 are arranged in a cross.
  • Part of the dummy metal 3 of the first metal layer 21 where the inductance device 1 is located and the dummy metal 3 corresponding to the metal layer (22/23/24/25) under the inductance device 1 are arranged crosswise.
  • FIG. 6 is a partial structural diagram of the inductive device wiring structure 10 shown in FIG. 1 in the third embodiment. Most of the technical content in this embodiment that is the same as the foregoing embodiment will not be repeated.
  • the inductance device wiring structure 10 includes a first metal layer 21 where the inductance device 1 is located and a multi-layer metal layer (the second metal layer 22 to the ninth metal layer 29) located under the inductance device 1 .
  • the arrangement area of the dummy metal 3 corresponding to the second metal layer 22 to the sixth metal layer 26 increases.
  • the dummy metal 3 corresponding to one or more metal layers 2 and the dummy metal 3 corresponding to the adjacent metal layer 2 are arranged crosswise, and the dummy metal 3 corresponding to one or more metal layers 2 is intersected
  • the dummy metals 3 corresponding to the metal layer 2 are aligned.
  • the dummy metal 3 corresponding to the second metal layer 22, the dummy metal 3 corresponding to the third metal layer 23, and the dummy metal 3 corresponding to the fourth metal layer 24 are aligned.
  • the fourth metal layer 24, the fifth metal layer 25, the sixth metal layer 26, the seventh metal layer 27, the eighth metal layer 28, and the ninth metal layer 29 two adjacent metal layers 2 corresponds to the virtual metal 3 in a cross arrangement.
  • the arrangement of the plurality of dummy metals 3 under the inductance device 1 in the inductance device wiring structure 10 is more diverse.
  • Part of the dummy metal 3 of the first metal layer 21 and the dummy metal 3 corresponding to the second metal layer 22 are arranged crosswise. In other embodiments, part of the dummy metal 3 of the first metal layer 21 is aligned with the dummy metal 3 corresponding to the second metal layer 22.
  • the present application does not strictly limit the arrangement of the dummy metal 3 of the multilayer metal layer 2 of the inductive device wiring structure 10.
  • the arrangement area of the dummy metal 3 corresponding to at least three metal layers 2 adjacent to each other increases in the direction Z away from the inductance device 1.
  • the plurality of dummy metals 3 under the inductance device 1 present a continuous step shape, which is beneficial to further improve the processing quality of the inductance device wiring structure 10, and the plurality of dummy metals 3 under the inductance device 1 affect the performance of the inductance device 1. smaller.
  • the arrangement area of the dummy metal 3 corresponding to the i-th metal layer under the inductor device 1 is equal to the arrangement area of the dummy metal 3 corresponding to the i-1th metal layer.
  • the i-th metal layer is located on the side of the i-1th metal layer away from the inductor device 1, that is, the i-th metal layer is located under the i-1th metal layer.
  • i is an integer and greater than or equal to 2.
  • the inductance device 1 when the inductance device wiring structure 10 satisfies the general arrangement rule from comb to dense, the inductance device 1 includes two metal layers 2 with the same arrangement area corresponding to the dummy metal 3, so that the inductance device
  • the arrangement flexibility of the multiple dummy metals 3 located under the inductance device 1 in the wiring structure 10 is higher, and the arrangement manners are more diverse.
  • the plurality of dummy metals 3 corresponding to the i-th metal layer are arranged at equal intervals, and the arrangement interval between two adjacent dummy metals 3 is the i-th interval; the plurality of dummy metals 3 corresponding to the i-1th metal layer They are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals 3 is the i-1th interval; the i-1th interval is less than or equal to the i-th interval.
  • the i-1th interval is smaller than the i-th interval, although the arrangement area of the dummy metal 3 corresponding to the i-th metal layer does not increase, the arrangement range of the plurality of dummy metals 3 of the i-th metal layer is relatively large and arranged.
  • the processing quality of the metal layer 2 can be effectively improved, so that the product yield of the inductor device wiring structure 10 is higher.
  • the arrangement mode and arrangement spacing of the plurality of dummy metals 3 corresponding to the i-th metal layer and the i-1th metal layer may also be different from the above-mentioned solutions, and set according to requirements.
  • the arrangement area of the dummy metal 3 corresponding to the jth metal layer under the inductance device 1 is smaller than the arrangement area of the dummy metal 3 corresponding to the j-1th metal layer.
  • the j-th metal layer is located on the side of the j-1th metal layer away from the inductor device 1, that is, the j-th metal layer is located under the j-1th metal layer.
  • j is an integer and greater than or equal to 2.
  • the lower part of the inductance device 1 when the inductance device wiring structure 10 satisfies the general arrangement rule from comb to dense, the lower part of the inductance device 1 includes two metal layers 2 inverted corresponding to the arrangement area of the dummy metal 3, so that the inductance device
  • the arrangement flexibility of the multiple dummy metals 3 located under the inductance device 1 in the wiring structure 10 is higher, and the arrangement manners are more diverse.
  • Metal layer 2 In the inductance device wiring structure 10, there may also be more than three layers (including this number) of the metal layer 2 corresponding to the inverted arrangement area of the dummy metal 3.
  • the plurality of dummy metals 3 corresponding to the j-th metal layer are arranged at equal intervals, and the arrangement interval between two adjacent dummy metals 3 is the j-th interval; the plurality of dummy metals 3 corresponding to the j-1th metal layer They are arranged at equal intervals, and the arrangement interval between two adjacent virtual metals 3 is the j-1th interval; the j-1th interval is less than or equal to the jth interval.
  • the arrangement range of the plurality of dummy metals 3 corresponding to the jth metal layer with the smaller arrangement area of the dummy metal 3 is larger and the arrangement is more uniform, which can effectively improve the metal
  • the processing quality of the layer 2 makes the product yield of the inductive device wiring structure 10 higher.
  • the arrangement mode and arrangement spacing of the plurality of dummy metals 3 corresponding to the j-th metal layer and the j-1th metal layer may also be different from the above-mentioned solutions, and set according to requirements.
  • the inductive device wiring structure 10 can also obtain a higher product yield.
  • the above three embodiments can be used independently or in combination.
  • the inductor device 1 is arranged on the first metal layer 21.
  • the arrangement area of the dummy metal 3 corresponding to the second metal layer 22 and the third metal layer 23 below the inductor device 1 increases in a direction away from the inductor device 1.
  • the arrangement area of the dummy metal 3 corresponding to the fourth metal layer 24 (that is, the third metal layer under the inductor device 1) is equal to that of the third metal layer 23 (that is, the second metal layer under the inductor device 1) Arrangement area of virtual metal 3.
  • the arrangement area of the dummy metal 3 corresponding to the fifth metal layer 25 (that is, the fourth metal layer under the inductance device 1) is equal to that of the fourth metal layer 24 (that is, the third metal layer under the inductance device 1) Arrangement area of virtual metal 3.
  • the arrangement area of the dummy metal 3 corresponding to the i-th metal layer under the inductor device 1 is equal to the arrangement area of the dummy metal 3 corresponding to the i-1th metal layer, and the i-th metal layer is located on the i-1th metal layer away from the inductor.
  • i is an integer and greater than or equal to 2.
  • the plurality of dummy metals 3 corresponding to the fourth metal layer 24 are arranged at equal intervals, and the arrangement interval between two adjacent dummy metals 3 is the third interval.
  • the plurality of dummy metals 3 corresponding to the third metal layer 23 are arranged at equal intervals, and the arrangement interval between two adjacent dummy metals 3 is the second interval.
  • the second distance is equal to the third distance.
  • the plurality of dummy metals 3 corresponding to the fifth metal layer 25 (that is, the fourth metal layer under the inductor device 1) are arranged at equal intervals, and the arrangement interval between two adjacent dummy metals 3 is the fourth interval.
  • the fourth distance is equal to the third distance.
  • the arrangement area of the virtual metal 3 corresponding to the third metal layer 23 (that is, the second metal layer under the inductance device 1), and the fourth metal layer 24 (that is, the third metal layer under the inductance device 1) corresponds to
  • the arrangement area of the dummy metal 3 is equal to the arrangement area of the dummy metal 3 corresponding to the fifth metal layer 25 (that is, the fourth metal layer below the inductor device 1). That is, there are three or more metal layers 2 (including this number) corresponding to the same arrangement area of the dummy metal 3 under the inductance device 1.
  • the inductance device 1 is arranged on the first metal layer 21.
  • the second metal layer 22, the third metal layer 23, and the fourth metal layer 24 under the inductor device 1 are adjacently arranged, and the second metal layer 22, the third metal layer 23 and the fourth metal layer 24
  • the arrangement area of the corresponding dummy metal 3 increases in the direction Z away from the inductance device 1. That is, in the multilayer metal layer 2 under the inductor device 1, the arrangement area of the dummy metal 3 corresponding to at least three metal layers 2 adjacent to each other increases in the direction Z away from the inductor device 1.
  • the arrangement area of the dummy metal 3 corresponding to the fifth metal layer 25 (that is, the fourth metal layer under the inductance device 1) is smaller than that of the fourth metal layer 24 (that is, the third metal layer under the inductance device 1) Arrangement area of virtual metal 3.
  • the plurality of dummy metals 3 corresponding to the fifth metal layer 25 (that is, the fourth metal layer under the inductor device 1) are arranged at equal intervals, and the arrangement interval between two adjacent dummy metals 3 is the fourth interval.
  • the plurality of dummy metals 3 corresponding to the fourth metal layer 24 (that is, the third metal layer under the inductor device 1) are arranged at equal intervals, and the arrangement interval between two adjacent dummy metals 3 is the third interval.
  • the third distance is equal to the fourth distance.
  • the inductance device 1 is arranged on the first metal layer 21.
  • the second metal layer 22, the third metal layer 23, the fourth metal layer 24, the fifth metal layer 25, and the sixth metal layer 26 below the inductor device 1 are adjacently arranged, and the second metal layer 22
  • the arrangement area of the dummy metal 3 corresponding to the sixth metal layer 26 increases in the direction away from the inductor device 1.
  • the sixth metal layer 26 (that is, the fifth metal layer under the inductance device 1), the seventh metal layer 27 (that is, the sixth metal layer under the inductance device 1), and the eighth metal layer 28 (that is, the inductor
  • the arrangement area of the dummy metal 3 corresponding to the seventh metal layer under the device 1 and the ninth metal layer 29 (that is, the eighth metal layer under the inductor device 1) are equal.
  • the number of dummy metals 3 corresponding to each metal layer 2 is multiple and different
  • the arrangement pitch between two adjacent dummy metals 3 in the metal layer 2 is equal. In other embodiments, the arrangement pitch between two adjacent dummy metals 3 in different metal layers 2 may also be unequal.
  • FIG. 7 is a schematic structural diagram of the inductive device wiring structure 10 shown in FIG. 1 in the fourth embodiment. Most of the technical content in this embodiment that is the same as the foregoing embodiment will not be repeated.
  • the inductor device 1 is arranged on the first metal layer 21.
  • the arrangement area of the dummy metal 3 corresponding to the third metal layer 23 and the fourth metal layer 24 under the inductor device 1 increases in the direction Z away from the inductor device 1.
  • the second metal layer 22 and the fourth metal layer 24 are arranged at intervals, and the arrangement area of the dummy metal 3 corresponding to the second metal layer 22 and the fourth metal layer 24 increases in the direction Z away from the inductor device 1.
  • the arrangement area of the dummy metal 3 corresponding to the third metal layer 23 (that is, the second metal layer under the inductor device 1) is equal to that of the second metal layer 22 (that is, the first metal layer under the inductor device 1) Arrangement area of virtual metal 3.
  • the arrangement area of the dummy metal 3 of the fifth metal layer 25 (that is, the fourth metal layer under the inductance device 1) is equal to that of the fourth metal layer 24 (that is, the third metal layer under the inductance device 1) Arrangement area of virtual metal 3.
  • the inductance device 1 may include two or more sets of two metal layers 2 with the same arrangement area corresponding to the dummy metal 3.
  • the arrangement distance between two adjacent dummy metals 3 in the plurality of dummy metals 3 corresponding to the third metal layer 23 is the second interval S7.
  • the arrangement interval between two adjacent dummy metals 3 in the plurality of dummy metals 3 corresponding to the second metal layer 22 is the first interval S6.
  • the first distance S6 is equal to the second distance S7.
  • the fifth metal layer 25 (that is, the fourth metal layer under the inductance device 1) corresponds to the arrangement pitch between two adjacent dummy metals 3 among the plurality of dummy metals 3 is the fourth pitch.
  • the arrangement distance between two adjacent dummy metals 3 in the plurality of dummy metals 3 corresponding to the fourth metal layer 24 (that is, the third metal layer under the inductor device 1) is the third interval.
  • the third distance is equal to the fourth distance.
  • the third distance may be equal to or different from the second distance.
  • FIG. 8 is a schematic structural diagram of the inductive device wiring structure 10 shown in FIG. 1 in the fifth embodiment. Most of the technical content in this embodiment that is the same as the foregoing embodiment will not be repeated.
  • the inductor device 1 is arranged on the first metal layer 21.
  • the arrangement area of the dummy metal 3 corresponding to the third metal layer 23 and the fourth metal layer 24 under the inductor device 1 increases in the direction Z away from the inductor device 1.
  • the arrangement area of the dummy metal 3 corresponding to the third metal layer 23 (that is, the second metal layer under the inductor device 1) is equal to that of the second metal layer 22 (that is, the first metal layer under the inductor device 1) Arrangement area of virtual metal 3.
  • the arrangement distance between two adjacent dummy metals 3 in the plurality of dummy metals 3 corresponding to the third metal layer 23 is the second interval S7.
  • the arrangement interval between two adjacent dummy metals 3 in the plurality of dummy metals 3 corresponding to the second metal layer 22 (that is, the first metal layer under the inductor device 1) is the first interval S6.
  • the first distance S6 is smaller than the second distance S7.
  • the arrangement area of the dummy metal 3 corresponding to the fifth metal layer 25 (that is, the fourth metal layer under the inductance device 1) is smaller than that of the fourth metal layer 24 (that is, the third metal layer under the inductance device 1) Arrangement area of virtual metal 3.
  • the plurality of dummy metals 3 in the plurality of dummy metals 3 corresponding to the fifth metal layer 25 (that is, the fourth metal layer under the inductance device 1) are arranged at equal intervals, and the arrangement interval between two adjacent dummy metals 3 For the fourth pitch.
  • the plurality of dummy metals 3 corresponding to the fourth metal layer 24 are arranged at equal intervals, and the arrangement interval between two adjacent dummy metals 3 is the third interval.
  • the third distance is equal to the fourth distance.
  • FIG. 9 is a partial structural diagram of the inductive device wiring structure 10 shown in FIG. 1 in the sixth embodiment. Most of the technical content in this embodiment that is the same as the foregoing embodiment will not be repeated.
  • the inductor device 1 is arranged on the first metal layer 21.
  • the arrangement area of the dummy metal 3 corresponding to the second metal layer 22 and the third metal layer 23 below the inductor device 1 increases in a direction away from the inductor device 1.
  • the arrangement area of the dummy metal 3 corresponding to the fourth metal layer 24, the fifth metal layer 25 and the sixth metal layer 26 increases in a direction away from the inductor device 1.
  • the arrangement area of the dummy metal 3 corresponding to the fourth metal layer 24 (that is, the third metal layer under the inductor device 1) is equal to that of the third metal layer 23 (that is, the second metal layer under the inductor device 1) Arrangement area of virtual metal 3.
  • the sixth metal layer 26 (that is, the fifth metal layer under the inductance device 1), the seventh metal layer 27 (that is, the sixth metal layer under the inductance device 1), and the eighth metal layer 28 (that is, the inductor
  • the arrangement area of the dummy metal 3 corresponding to the seventh metal layer under the device 1 and the ninth metal layer 29 (that is, the eighth metal layer under the inductor device 1) are equal.
  • FIG. 10 is a schematic structural diagram of the inductive device wiring structure 10 shown in FIG. 1 in the seventh embodiment. Most of the technical content in this embodiment that is the same as the foregoing embodiment will not be repeated.
  • the inductance device 1 is arranged on the first metal layer 21.
  • the arrangement area of the dummy metal 3 corresponding to the third metal layer 23 and the fourth metal layer 24 under the inductor device 1 increases in a direction away from the inductor device 1.
  • the arrangement area of the dummy metal 3 corresponding to the third metal layer 23 (that is, the second metal layer under the inductor device 1) is smaller than that of the second metal layer 22 (that is, the first metal layer under the inductor device 1) Arrangement area of virtual metal 3.
  • the arrangement pitch between two adjacent dummy metals 3 in the plurality of dummy metals 3 corresponding to the third metal layer 23 (that is, the second metal layer under the inductor device 1) is the second interval S7.
  • the arrangement interval between two adjacent dummy metals 3 in the plurality of dummy metals 3 corresponding to the second metal layer 22 (that is, the first metal layer under the inductor device 1) is the first interval S6.
  • the first distance S6 is equal to the second distance S7.
  • the arrangement area of the dummy metal 3 corresponding to the fifth metal layer 25 (that is, the fourth metal layer under the inductance device 1) is equal to that of the fourth metal layer 24 (that is, the third metal layer under the inductance device 1) Arrangement area of virtual metal 3.
  • the fifth metal layer 25 (that is, the fourth metal layer under the inductance device 1) corresponds to the plurality of virtual metals 3 and the arrangement distance between adjacent two virtual metals 3 is equal to the fourth metal layer 24 (that is Is the arrangement distance between two adjacent dummy metals 3 among the plurality of dummy metals 3 corresponding to the third metal layer under the inductor device 1.
  • FIG. 11 is a schematic structural diagram of the inductive device wiring structure 10 shown in FIG. 1 in the eighth embodiment. Most of the technical content in this embodiment that is the same as the foregoing embodiment will not be repeated.
  • the inductor device 1 is arranged on the first metal layer 21.
  • the arrangement area of the dummy metal 3 corresponding to the third metal layer 23 and the fourth metal layer 24 under the inductor device 1 increases in a direction away from the inductor device 1.
  • the arrangement area of the dummy metal 3 corresponding to the third metal layer 23 (that is, the second metal layer under the inductor device 1) is smaller than that of the second metal layer 22 (that is, the first metal layer under the inductor device 1) Arrangement area of virtual metal 3.
  • the arrangement distance between two adjacent dummy metals 3 in the plurality of dummy metals 3 corresponding to the third metal layer 23 is the second interval S7.
  • the arrangement interval between two adjacent dummy metals 3 in the plurality of dummy metals 3 corresponding to the second metal layer 22 is the first interval S6.
  • the first distance S6 is smaller than the second distance S7.
  • the arrangement area of the dummy metal 3 corresponding to the fifth metal layer 25 (that is, the fourth metal layer under the inductance device 1) is equal to that of the fourth metal layer 24 (that is, the third metal layer under the inductance device 1) Arrangement area of virtual metal 3.
  • the fifth metal layer 25 (that is, the fourth metal layer under the inductance device 1) corresponds to the arrangement distance between two adjacent virtual metals 3 in the plurality of virtual metals 3, which is equal to the fourth metal layer 24 ( That is, the arrangement distance between two adjacent dummy metals 3 among the plurality of dummy metals 3 corresponding to the third metal layer under the inductance device 1.
  • FIG. 12 is a partial structural diagram of the inductive device wiring structure 10 shown in FIG. 1 in the ninth embodiment. Most of the technical content in this embodiment that is the same as the foregoing embodiment will not be repeated.
  • the inductor device 1 is arranged on the first metal layer 21.
  • the arrangement area of the third metal layer 23 and the fourth metal layer 24 under the inductor device 1 corresponding to the dummy metal 3 increases in a direction away from the inductor device 1.
  • the arrangement area of the fifth metal layer 25 and the sixth metal layer 26 corresponding to the dummy metal 3 increases in a direction away from the inductor device 1.
  • the arrangement area of the dummy metal 3 corresponding to the third metal layer 23 (that is, the second metal layer under the inductor device 1) is smaller than that of the second metal layer 22 (that is, the first metal layer under the inductor device 1) Arrangement area of virtual metal 3.
  • the arrangement area of the dummy metal 3 corresponding to the fifth metal layer 25 (that is, the fourth metal layer under the inductance device 1) is smaller than that of the fourth metal layer 24 (that is, the third metal layer under the inductance device 1) Arrangement area of virtual metal 3.
  • the plurality of dummy metals 3 in the plurality of dummy metals 3 corresponding to the third metal layer 23 are arranged at equal intervals, and the arrangement interval between two adjacent dummy metals 3 For the second spacing.
  • the plurality of dummy metals 3 corresponding to the third metal layer 23 (that is, the second metal layer under the inductor device 1) are arranged at equal intervals, and the arrangement interval between two adjacent dummy metals 3 is the first interval.
  • the first distance is equal to the second distance.
  • a plurality of dummy metals 3 corresponding to the fifth metal layer 25 (that is, the fourth metal layer under the inductor device 1) are arranged at equal intervals, and the arrangement interval between two adjacent dummy metals 3 is the fourth interval.
  • the plurality of dummy metals 3 corresponding to the fourth metal layer 24 (that is, the third metal layer under the inductor device 1) are arranged at equal intervals, and the arrangement interval between two adjacent dummy metals 3 is the third interval.
  • the third distance is equal to the fourth distance.
  • the sixth metal layer 26 (that is, the fifth metal layer under the inductance device 1), the seventh metal layer 27 (that is, the sixth metal layer under the inductance device 1), and the eighth metal layer 28 (that is, the inductor
  • the arrangement area of the dummy metal 3 corresponding to the seventh metal layer under the device 1 and the ninth metal layer 29 (that is, the eighth metal layer under the inductor device 1) are equal.
  • FIG. 13 is a partial structural diagram of the inductance device wiring structure 10 shown in FIG. 1 in the tenth embodiment. Most of the technical content in this embodiment that is the same as the foregoing embodiment will not be repeated.
  • the inductance device 1 is arranged on the first metal layer 21.
  • the arrangement area of the dummy metal 3 corresponding to the second metal layer 22 and the third metal layer 23 below the inductor device 1 increases in a direction away from the inductor device 1.
  • the fourth metal layer 24, the fifth metal layer 25, and the sixth metal layer 26 are arranged adjacent to each other, and in the direction away from the inductor device 1, the arrangement area of the corresponding dummy metal 3 increases.
  • the arrangement area of the dummy metal 3 corresponding to the second metal layer 22 corresponds to the dummy metal 3 corresponding to the first metal layer 21 (that is, the metal layer where the inductance device 1 is located)
  • the layout area is equal.
  • the second metal layer 22 corresponds to the arrangement distance between two adjacent virtual metals in the plurality of virtual metals 3, which is larger than the first metal layer 21 (that is, Is the arrangement distance between two adjacent virtual metals among the plurality of virtual metals 3 corresponding to the metal layer where the inductance device 1 is located.
  • the arrangement area of the dummy metal 3 corresponding to the fourth metal layer 24 (that is, the third metal layer under the inductance device 1) is smaller than that of the third metal layer 24 (that is, the second metal layer under the inductance device 1) Arrangement area of virtual metal 3.
  • the plurality of dummy metals 3 corresponding to the fourth metal layer 24 (that is, the third metal layer under the inductor device 1) are arranged at equal intervals, and the arrangement interval between two adjacent dummy metals 3 is the third interval.
  • the plurality of dummy metals 3 corresponding to the third metal layer 24 (that is, the second metal layer under the inductor device 1) are arranged at equal intervals, and the arrangement interval between two adjacent dummy metals 3 is the second interval.
  • the second distance is smaller than the third distance.
  • the sixth metal layer 26 that is, the fifth metal layer under the inductance device 1
  • the seventh metal layer 27 that is, the sixth metal layer under the inductance device 1
  • the eighth metal layer 28 that is, the inductor
  • the arrangement area of the dummy metal 3 corresponding to the seventh metal layer under the device 1 and the ninth metal layer 29 that is, the eighth metal layer under the inductor device 1) are equal.
  • the arrangement relationship of the plurality of dummy metals 3 under the inductance device 1 is schematically illustrated, and the arrangement of the plurality of dummy metals 3 under the inductance device 1 is not formed.
  • the arrangement relationship (for example, the arrangement spacing relationship in the single metal layer 2 and the arrangement spacing between the multilayer metal layers 2) is strictly limited.
  • the plurality of dummy metals 3 in the metal layer 2 under the inductance device 1 may also be randomly arranged or arranged in other patterns.
  • the inductance device 1 can have multiple implementation structures.
  • the inductance device 1 may be an inductor with two ports or a transformer with four ports.
  • the inductance device 1 may be arranged in the same metal layer; or, the inductance device 1 may include an upper inductor and a lower inductor, and the upper inductor and the lower inductor are arranged in two adjacent metal layers.
  • the inductor device 1 in the inductor device wiring structure 10 is an inductor with dual ports.
  • FIG. 14 is an implementation structure of the inductor device 1 of the inductor device wiring structure 10 shown in FIG. 1.
  • FIG. 14 illustrates a top view of the metal layer where the inductor device 1 of the inductor device wiring structure 10 is located.
  • the inductor device 1 in the inductor device wiring structure 10 is a spiral inductor with dual ports.
  • the spiral inductors are arranged in the same metal layer. A 180° is formed between the two ports 11 of the spiral inductor.
  • the main structure of the spiral inductor is arranged in the same metal layer.
  • the metal layer where the inductance device 1 is located also includes a plurality of dummy metals 3. Part of the dummy metal 3 is arranged around the outer circumference of the spiral inductor. Part of the dummy metal 3 is arranged in the middle space surrounded by the spiral inductor.
  • the wiring area of the inductor device 1 is indicated by the dashed frame on the outer periphery of the inductor device 1.
  • FIG. 15 is another implementation structure of the inductor device 1 of the inductor device wiring structure 10 shown in FIG. 1.
  • FIG. 15 illustrates a top view of the metal layer where the inductor device 1 of the inductor device wiring structure 10 is located.
  • the inductor device 1 in the inductor device wiring structure 10 is a spiral inductor with dual ports. 90° is formed between the two ports 11 of the spiral inductor.
  • the main structure of the spiral inductor is arranged in the same metal layer.
  • the metal layer where the inductance device 1 is located also includes a plurality of dummy metals 3. Part of the dummy metal 3 is arranged around the outer circumference of the spiral inductor. Part of the dummy metal 3 is arranged in the middle space surrounded by the spiral inductor.
  • the wiring area of the inductor device 1 is indicated by the dashed frame on the outer periphery of the inductor device 1.
  • FIG. 16 is another implementation structure of the inductor device 1 of the inductor device wiring structure 10 shown in FIG. 1.
  • FIG. 16 illustrates a top view of the metal layer where the inductor device 1 of the inductor device wiring structure 10 is located.
  • the inductor device 1 in the inductor device wiring structure 10 is a differential inductor with dual ports.
  • the main structure of the differential inductor is arranged in the same metal layer.
  • the metal layer where the inductance device 1 is located also includes a plurality of dummy metals 3. Part of the dummy metal 3 is arranged around the outer circumference of the differential inductor. Part of the dummy metal 3 is arranged in the middle space surrounded by the differential inductor.
  • the wiring area of the inductor device 1 is indicated by the dashed frame on the outer periphery of the inductor device 1.
  • FIG. 17 is another implementation structure of the inductor device 1 of the inductor device wiring structure 10 shown in FIG. 1.
  • FIG. 17 illustrates a top view of the metal layer where the inductor device 1 of the inductor device wiring structure 10 is located.
  • the inductor device 1 in the inductor device wiring structure 10 is a square inductor with dual ports.
  • the main structure of the square inductor is arranged in the same metal layer.
  • the metal layer where the inductance device 1 is located also includes a plurality of dummy metals 3. Part of the dummy metal 3 is arranged around the outer circumference of the square inductor. Part of the dummy metal 3 is arranged in the middle space surrounded by the square inductor.
  • the wiring area of the inductor device 1 is indicated by the dashed frame on the outer periphery of the inductor device 1.
  • the square inductor is a differential inductor.
  • the square inductor may also be other inductors.
  • the inductor may also be an inductor of other shapes, such as a circle, a polygon, etc., which is not strictly limited in this application.
  • FIG. 18 is another implementation structure of the inductor device 1 of the inductor device wiring structure 10 shown in FIG. 1.
  • FIG. 18 illustrates a top view of the metal layer where the inductor device 1 of the inductor device wiring structure 10 is located.
  • the inductor device 1 in the inductor device wiring structure 10 is a transformer with four ports.
  • the transformer includes two coils wound around each other. Each coil has two ports 11.
  • the main structure of the transformer is arranged in the same metal layer.
  • the metal layer where the inductance device 1 is located also includes a plurality of dummy metals 3. Part of the dummy metal 3 is arranged around the outer circumference of the transformer. Part of the virtual metal 3 is arranged in the middle space surrounded by the transformer.
  • the wiring area of the inductor device 1 is indicated by the dashed frame on the outer periphery of the inductor device 1.
  • FIG. 19 is another implementation structure of the inductor device 1 of the inductor device wiring structure 10 shown in FIG. 1.
  • FIG. 19 shows a schematic diagram of the three-dimensional structure of the inductor device 1.
  • the inductor device 1 may include an upper inductor 12 and a lower inductor 13.
  • the upper inductor 12 and the lower inductor 13 are arranged in two adjacent metal layers.
  • the upper inductor 12 and the lower inductor 13 can be connected through the conductive material 14 in the via, so that the inductor device 1 can be used as a multilayer metal serial inductor (serial).
  • the wiring area of the inductor device 1 includes the area surrounded by the outer edge of the outermost wire of the upper inductor 12 and the area surrounded by the outer edge of the outermost wire of the lower inductor 13.
  • the inductance device 1 in the inductance device wiring structure 10 can also be replaced with other transmission wires to form a transmission wire wiring structure.
  • Transmission wires can be used to transmit signals with frequencies greater than 100 MHz.
  • the transmission wire may be a key signal wire used to transmit radio frequency signals.

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Abstract

本申请实施例公开一种电感器件布线架构，包括电感器件及位于电感器件下方的多个虚拟金属。其中，多个虚拟金属排布在多层金属层中，多层金属层中每层金属层对应多个虚拟金属的部分虚拟金属，在远离电感器件的方向上，多层金属层中的至少两层金属层对应的虚拟金属的排布面积递增。上述电感器件布线架构能够减少对电感器件性能的不良影响，并提高产品良率。本申请实施例还公开一种集成电路和一种通信设备。

Description

电感器件布线架构、集成电路及通信设备 技术领域
本申请涉及集成电路技术领域，尤其涉及一种电感器件布线架构、一种集成电路以及一种通信设备。
背景技术
随着无线通信技术的迅猛发展，射频集成电路(radio frequency integrated circuit，RFIC)变得越来越重要，射频集成电路可以是一种工作在300兆赫兹(MHz)～300吉赫兹(GHz)频率范围内的集成电路。随着最新的第5代移动通信的到来，信号的频率将大大提高，这将为人们带来更加快速的通信体验，同时也给射频集成电路带来更大挑战和机遇。
集成电路通过金属导线将多层电子元器件层进行连接，以形成完整的逻辑电路。基于化学机械研磨(chemical mechanical polishing，CMP)工艺，集成电路中各层金属导线的成型质量与金属导线的底层金属层的金属排布面积紧密相关。若金属导线的底层金属层的金属排布面积不足，则金属导线的良率不佳，容易造成线路短路。
为解决这一问题，通常的做法是在金属导线的底层金属中增加虚拟金属(dummy metal)，以提高金属排布面积。然而，当金属导线用作电感器件时，电感器件下方的虚拟金属会对电感器件性能造成影响，导致电感器件性能不佳。
发明内容
本申请实施例提供一种电感器件布线架构、集成电路及通信设备，所述电感器件布线架构能够减少对电感器件性能的不良影响，并提高产品良率。
第一方面，本申请实施例提供一种电感器件布线架构。所述电感器件布线架构可应用于集成电路中。所述电感器件布线架构包括电感器件及位于所述电感器件下方的多个虚拟金属。其中，所述多个虚拟金属排布在多层金属层中，所述多层金属层中每层金属层对应所述多个虚拟金属的部分虚拟金属，在远离所述电感器件的方向上，所述多层金属层中的至少两层金属层对应的虚拟金属的排布面积递增。也即，位于所述电感器件下方的至少两层金属层对应的虚拟金属的排布面积递增。
在本实施例中，由于在远离所述电感器件的方向上，所述电感器件下方的所述多层金属层的至少两层金属层对应的虚拟金属的排布面积递增。此时，靠近所述电感器件的所述金属层对应的虚拟金属的排布面积较小，远离所述电感器件的所述金属层对应的虚拟金属的排布面积较大。也即，位于所述电感器件下方的所述多个虚拟金属在排布时，尽量远离所述电感器件，靠近所述电感器件的区域的所述虚拟金属较少，远离所述电感器件的区域的所述虚拟金属较多，从而降低所述虚拟金属对所述电感器件性能的不良影响、甚至不影响所述电感器件性能。并且，所述电感器件下方的各层金属层具有较为足够的金属排布面积，能够满足化学机械抛光的加工需求，从而提高加工质量，使得所述电感器件布线架构 及应用所述电感器件布线架构的集成电路的产品良率较高。
一种可选实施例中，所述电感器件下方的空间包括，所述电感器件的布线区域沿所述电感器件所在金属层的垂直方向投影的空间。所述电感器件的布线区域至少包括所述电感器件的最外圈走线的外边缘所围绕的区域。
一种可选实施例中，所述多个虚拟金属呈阶梯状排布。也即，在所述电感器件下方的所述多层金属层中，位于下方的金属层对应的虚拟金属相对于位于上方的金属层对应的虚拟金属伸出而形成阶梯形状。
在本实施例中，由于所述电感器件下方的所述多个虚拟金属呈阶梯状排布，因此所述多个虚拟金属能够有效改善所述电感器件下方的金属排布情况，使得所述电感器件在化学机械抛光工艺过程中获得较高的制作精度，所述电感器件布线架构及应用所述电感器件布线架构的集成电路的产品良率更高，并且所述多个虚拟金属能够尽量不排布在靠近所述电感器件的区域，而排布在远离所述电感器件的区域，从而减少所述虚拟金属对所述电感器件的性能的不良影响，使得所述电感器件的性能更佳。
其中，所述电感器件布线架构还可包括与所述电感器件同层排布的多个虚拟金属。与所述电感器件同层排布的部分虚拟金属可以与位于所述电感器件下方的多个虚拟金属共同呈阶梯状排布。此时，与所述电感器件同层排布的部分虚拟金属对所述电感器件的性能影响更小，且所述电感器件的加工质量更高，所述电感器件布线架构的产品良率更高。
一种可选实施例中，在所述多层金属层中，彼此相邻设置的至少三层金属层对应的虚拟金属的排布面积在远离所述电感器件的方向上递增。此时，所述电感器件下方的多个虚拟金属呈现连续的阶梯状，有利于进一步改善所述电感器件布线架构的加工质量，且所述多个虚拟金属对所述电感器件的性能影响更小。
一种可选实施例中，所述电感器件下方的第i金属层对应的虚拟金属的排布面积等于第i-1金属层对应的虚拟金属的排布面积，所述第i金属层位于所述第i-1金属层远离所述电感器件的一侧，i为整数且大于或等于2。
在本实施例中，所述电感器件布线架构在满足大体呈由梳到密的排布规律时，所述电感器件的下方包括对应虚拟金属的排布面积相同的两层金属层，使得所述电感器件布线架构中的所述多个虚拟金属的排布灵活性更高，排布方式更为多样化。
其中，所述电感器件布线架构中可以存在一组对应虚拟金属的排布面积相同的两层金属层，也可以是两组以上(包括本数)对应的虚拟金属的排布面积相同的两层金属层。所述电感器件布线架构中也可以存在对应的虚拟金属的排布面积相同的三层以上(包括本数)的金属层。
一种可选实施例中，所述第i金属层对应的多个虚拟金属等间距排布，且相邻两个虚拟金属之间的排布间距为第i间距；所述第i-1金属层对应的多个虚拟金属等间距排布，且相邻两个虚拟金属之间的排布间距为第i-1间距；所述第i-1间距小于所述第i间距。此时，虽然所述第i金属层的金属排布面积没有递增，但是所述第i金属层对应的多个虚拟金属的排布范围较大、排布较为均匀，因此能够有效提高金属层的加工质量，使得所述电感器件布线架构的产品良率较高。
一种可选实施例中，所述电感器件下方的第j金属层对应的虚拟金属的排布面积小于 第j-1金属层对应的虚拟金属的排布面积，所述第j金属层位于所述第j-1金属层远离所述电感器件的一侧，j为整数且大于或等于2。
在本实施方式中，所述电感器件布线架构在满足大体呈由梳到密的排布规律时，所述电感器件的下方包括对应虚拟金属的排布面积倒置的两层金属层，使得所述电感器件布线架构中的所述多个虚拟金属的排布灵活性更高，排布方式更为多样化。
其中，所述电感器件布线架构中可以存在一组对应虚拟金属的排布面积倒置的两层金属层，也可以是两组以上(包括本数)对应虚拟金属的排布面积倒置的两层金属层。所述电感器件布线架构中也可以存在对应虚拟金属的排布面积倒置的三层以上(包括本数)的金属层。
一种可选实施例中，所述第j金属层对应的多个虚拟金属等间距排布，且相邻两个虚拟金属之间的排布间距为第j间距；所述第j-1金属层对应的多个虚拟金属等间距排布，且相邻两个虚拟金属之间的排布间距为第j-1间距；所述第j-1间距小于所述第j间距。此时，金属排布面积较小的所述第j金属层对应的多个虚拟金属的排布范围较大、排布较为均匀，能够有效提高金属层的加工质量，使得所述电感器件布线架构的产品良率较高。
一种可选实施例中，在所述电感器件下方，每层所述金属层(所述多层金属层中的金属层)对应的虚拟金属的个数均为多个，且每层所述金属层对应的虚拟金属与相邻金属层对应的虚拟金属交叉排列。此时，所述电感器件下方的所述多个虚拟金属的排布较为规律，有利于所述电感器件布线架构的降低设计成本和生产成本。
一种可选实施例中，在所述电感器件下方，每层所述金属层(所述多层金属层中的金属层)的所述虚拟金属的个数均为多个，且每层所述金属层对应的虚拟金属与相邻金属层对应的虚拟金属对齐排列。此时，所述电感器件下方的所述多个虚拟金属的排布较为规律，有利于所述电感器件布线架构的降低设计成本和生产成本。
一种可选实施例中，在所述电感器件下方，每层所述金属层(所述多层金属层中的金属层)对应的虚拟金属的个数均为多个，且一层或多层所述金属层对应的虚拟金属与相邻金属层对应的虚拟金属交叉排列，一层或多层所述金属层对应的虚拟金属与相邻金属层对应的虚拟金属对齐排列。
此时，所述电感器件布线架构的所述电感器件下方的部分虚拟金属对齐排列、部分虚拟金属交叉排列，丰富了所述多个虚拟金属的排布方式，使得所述电感器件布线架构的排布方式更为多样化。
一种可选实施例中，所述电感器件为具有双端口的电感或者具有四端口的变压器。具有双端口的电感包括但不限于螺旋电感、差分电感等。在本申请中，所述电感器件可以有多种实现结构，所述电感器件布线架构应用范围更广。
一种可选实施例中，所述电感器件排布于同一层金属层中；或者，所述电感器件包括上电感和下电感，所述上电感和所述下电感排布于相邻的两层金属层中。其中，所述上电感和所述下电感可通过导电材料连接，而使所述电感器件作为多层金属串联电感使用。在本申请中，所述电感器件可以有多种实现结构，所述电感器件布线架构应用范围更广。
第二方面，本申请实施例还提供一种集成电路，包括上述任一项所述的电感器件布线架构。由于所述电感器件布线架构成本较低、且对电感器件的性能的不良影响较小，因此 所述集成电路的成本低且性能好。
第三方面，本申请实施例还提供一种通信设备，包括上述集成电路。
附图说明
图1是本申请实施例提供的一种集成电路的结构示意图；
图2是图1所示电感器件布线架构在第一实施例中的俯视图；
图3是图2所示电感器件布线架构的部分结构沿A-A线处剖开的截面示意图；
图4是图1所示电感器件布线架构在第二实施例中的俯视图；
图5是图4所示电感器件布线架构的部分结构沿B-B线处剖开的截面示意图；
图6是图1所示电感器件布线架构在第三实施例中的部分结构示意图；
图7是图1所示电感器件布线架构在第四实施例中的部分结构示意图；
图8是图1所示电感器件布线架构在第五实施例中的结构示意图；
图9是图1所示电感器件布线架构在第六实施例中的部分结构示意图；
图10是图1所示电感器件布线架构在第七实施例中的结构示意图；
图11是图1所示电感器件布线架构在第八实施例中的结构示意图；
图12是图1所示电感器件布线架构在第九实施例中的部分结构示意图；
图13是图1所示电感器件布线架构在第十实施例中的部分结构示意图；
图14是图1所示电感器件布线架构的电感器件的一种实现结构；
图15是图1所示电感器件布线架构的电感器件的另一种实现结构；
图16是图1所示电感器件布线架构的电感器件的再一种实现结构；
图17是图1所示电感器件布线架构的电感器件的再一种实现结构；
图18是图1所示电感器件布线架构的电感器件的再一种实现结构；
图19是图1所示电感器件布线架构的电感器件的再一种实现结构。
具体实施方式
下面结合本申请实施例中的附图对本申请实施例进行描述。
本申请实施例提供一种通信设备。该通信设备可以是无线保真(wireless fidelity，Wi-Fi)设备、蓝牙(bluetooth)设备、红外设备、全球定位系统(global positioning system，GPS)设备、近距离无线通信(near-field communication，NFC)设备、移动通信设备、路由器、光电设备、基站、微波设备等。
该通信设备包括集成电路(integrated circuit，IC)。例如，通信设备包括高频集成电路(high frequency integrated circuit，HFIC)。该高频集成电路是工作频率大于100兆赫兹(MHz)的集成电路。例如，该高频集成电路可以为射频集成电路(radio frequency integrated circuit，RFIC)。射频集成电路可以工作在300兆赫兹至300吉赫兹(GHz)范围内，用以实现特定的射频功能。
一种实施例中，集成电路包括电感器件布线架构。电感器件布线架构包括电感器件。电感器件是集成电路最主要的器件之一，它和电阻、电容、金属氧化物半导体场效晶体管 (metal-oxide-semiconductor field-effect Transistor，MOSFET)、双极结型晶体管(bipolar junction transistor，BJT)、二极管等器件一起通过特殊电路结构相连，共同组成了集成电路。该集成电路具有控制、计算、记忆等功能。
其中，集成电路可以包括一个或多个电路模块。该电路模块可以包括但不限于电压控振荡模块(Voltage Control Oscillator，VCO)、低噪声放大模块(Low-noise Amplifier，LNA)、混频模块(mixer)、跨阻放大模块(trans-impedance amplifier，TIA)、可变增益放大模块(variable gain amplifier，VGA)或驱动模块(driver)中的一者或多者。电感器件在这些电路模块中应用广泛。
请参阅图1，图1是本申请实施例提供的一种集成电路100的结构示意图。
一种实施例中，集成电路100包括衬底110及形成在衬底110上的多层金属层120和多层绝缘层130。任意相邻的两层金属层120之间均设置有至少一层绝缘层130。衬底110可采用硅材料、玻璃材料或陶瓷材料。金属层120的材料可包括铜、铝、银、镍、金、钛、铟、钨或其合金中的一种或多种。绝缘层130的材料可包括电绝缘聚合物、电绝缘陶瓷或介电材料中的一种或多种。
金属层120为图案化金属层。图案化金属层的成型方式可以有多种，例如：
一种实施方式中，图案化金属层的制作方法包括：首先，在绝缘基材上依据图案化金属层的版图形成凹槽。然后，在绝缘基材上沉积金属(metal deposition)，使金属材料填充凹槽且溢出到凹槽外。接着，通过化学机械抛光(chemical-mechanical polishing，CMP)方式去除溢出到凹槽外的金属材料。此时，留在凹槽中的金属材料共同形成图案化金属层。
另一种实施方式中，图案化金属层的制作方法包括：先沉积形成一层金属薄膜，然后在金属薄膜上面沉积光阻，接着通过掩膜版(mask)做曝光、显影(photolithography)及刻蚀(etching)处理、以图案化金属薄膜，最后平面化处理图案化后的金属薄膜，以形成图案化金属层。平面化处理通常采用化学机械抛光的方式。
故而，在图案化金属层的成型步骤中，通常都需要在最后的步骤中进行化学机械抛光处理。而化学机械抛光处理的完成度通常依赖于待处理金属层的金属排布面积、和待处理金属层的底层金属层的金属排布面积，若金属排布面积不足，则容易出现少研磨现象，而导致图案化金属层的产品良率很低。
一种实施例中，集成电路100包括电感器件布线架构10。电感器件布线架构10为集成电路100的一部分。电感器件布线架构10包括部分金属层120和部分绝缘层130。电感器件布线架构10在集成电路100的制备过程中，与集成电路100的其他部分同步成型。电感器件布线架构10的具体层数可以少于或等于集成电路100的层数。
一种实施例中，电感器件布线架构10包括电感器件和位于电感器件下方的多个虚拟金属(dummy metal)。电感器件布线架构10可层叠设置多层金属层。电感器件布线架构10的金属层为对应的金属层120的一部分，电感器件布线架构10的金属层也为图案化金属层。电感器件排布于电感器件布线架构10的顶层金属层。电感器件下方的多个虚拟金属排布于电感器件下方的多层金属层中。位于电感器件下方的多层金属层中的每层金属层、对应位于电感器件下方的多个虚拟金属中的部分虚拟金属。在远离电感器件的方向上，电感器件下方的多层金属层的至少两层金属层对应的虚拟金属的排布面积递增。此时，靠近电感器 件的金属层对应的虚拟金属的排布面积较小，远离电感器件的金属层对应的虚拟金属的排布面积较大。也即，位于电感器件下方的多个虚拟金属在排布时，尽量远离(keep put from)电感器件，靠近电感器件的区域的虚拟金属较少，远离电感器件的区域的虚拟金属较多，从而降低虚拟金属对电感器件性能的不良影响、甚至不影响电感器件性能。并且，电感器件下方的各层金属层具有较为足够的金属排布面积，能够满足化学机械抛光的加工需求，从而提高加工质量，使得电感器件布线架构10及应用电感器件布线架构10的集成电路的产品良率较高。
下面通过具体实施例进行介绍。
请一并参阅图2和图3，图2是图1所示电感器件布线架构10在第一实施例中的俯视图，图3是图2所示电感器件布线架构10的部分结构沿A-A线处剖开的截面示意图。其中，为了更清楚地表达图3中的结构，图3中各金属层2中的虚拟金属3的数量略有删减，但是整体排布规律不变。
电感器件布线架构10包括电感器件1及位于电感器件1下方的多个虚拟金属3。在本申请中，“下方”仅是参考附加图式的方向，因此，使用的方向用语是为了说明及理解本申请，而不是指示或暗指所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。例如，结合参阅图1和图3，在集成电路100中，电感器件1可排布在集成电路100的顶层金属层120上。电感器件1的下方是指电感器件1朝向集成电路100的衬底110的一侧空间。也即，位于电感器件1下方的结构或部件位于电感器件1与衬底110之间。
电感器件1下方包括电感器件1的布线区域(如图2中电感器件1的外周虚线框所示意)的下方。也即，电感器件1下方的空间包括：电感器件1的布线区域沿电感器件1所在平面的垂直方向投影的空间。电感器件1的布线区域覆盖整个电感器件1。电感器件1的布线区域至少包括：电感器件1的最外圈走线的外边缘所围绕区域。其中，在实际使用中，前述“垂直方向”不限定是严格的与电感器件1所在平面之间成90°夹角的方向，也可以是接近90°的方向。电感器件1下方的多个虚拟金属3位于电感器件1下方的空间内。
电感器件布线架构10包括层叠设置的多层金属层2。金属层2为对应的集成电路100的金属层120的一部分。电感器件1下方的多个虚拟金属3排布在电感器件1下方的多层金属层2中。电感器件1下方的多层金属层2中的每层金属层2均包括对应的多个虚拟金属3，以提高金属层2的金属排布面积。电感器件1下方的多层金属层2为电感器件1的底层结构。
在本实施例中，电感器件1下方的金属层2对应的多个虚拟金属3彼此间隔设置。在其他实施例中，两个或两个以上虚拟金属3也可以合并成一个连续的、面积较大的虚拟金属。例如，可以将图2所示实施例中的断开的多个虚拟金属3合并成一个连续的虚拟金属。
其中，位于相邻两层金属层2中的虚拟金属3之间，可以通过过孔内的导电材料实现连接，也可以彼此之间无连接关系。
本实施例中，电感器件1位于第一层金属层21。由于电感器件1设于第一层金属层21，因此能够加工成较大厚度，从而降低电阻，提高品质因子Q。电感器件1下方具有第二层金属层22至第五层金属层25。第二层金属层22至第五层金属层25为电感器件1的底层 结构。电感器件1下方的多个虚拟金属3排布在第二层金属层22、第三层金属层23、第四次金属层24及第五层金属层25中。
电感器件布线架构10还包括排布在电感器件1所在金属层2的多个虚拟金属3。例如，本实施例中，第一层金属层21还包括多个虚拟金属3，多个虚拟金属3围绕电感器件1设置，且远离电感器件1设置。其中，当电感器件1环绕出一个面积较大的中部空间时，中部空间也可以排布虚拟金属3。
其中，在远离电感器件1的方向(如图3中Z向)上，位于电感器件1下方的至少两层金属层2对应的虚拟金属的排布面积递增。金属层2对应的虚拟金属的排布面积为金属层2中、位于电感器件1下方的虚拟金属3的总排布面积。虚拟金属3的排布面积较大的金属层2的金属排布比例较大。此时，位于电感器件1下方的多个虚拟金属3在靠近电感器件1的区域排布较少，而在远离电感器件1的区域排布较多，从而降低对电感器件1的性能的不良影响。并且，由于电感器件1下方的金属层2对应的虚拟金属3的排布面积呈递增区域，因此电感器件1下方的金属层2大致呈现对应虚拟金属3的排布面积递增的趋势(也即大致呈上疏下密的趋势)，因此电感器件布线架构10的各层金属层2具有较为足够的金属排布面积，能够满足化学机械抛光的加工需求，使得第一层金属层21具有良好的平坦化，电感器件1的金属残留很少、加工质量高，从而降低电路发生短路的风险，使得电感器件布线架构10及应用电感器件布线架构10的集成电路100的产品良率较高。简言之，电感器件布线架构10能够在减少虚拟金属3对电感器件1的电感器件性能产生的不良影响的情况下，增加各层金属层2的金属排布面积，从而提高产品良率。
其中，位于电感器件1下方的多个虚拟金属3呈阶梯状排布。也即，位于电感器件1下方的多层金属层2中，位于下方的金属层2对应的虚拟金属3相对于位于上方的金属层2对应的虚拟金属3伸出而形成阶梯形状。例如，在图3中，第三层金属层23对应的虚拟金属3相对第二层金属层22对应的虚拟金属3伸出而形成阶梯形状。
图2中通过对电感器件布线架构10中位于不同金属层2的虚拟金属3填充不同的图案以进行区分。其中，第一层金属层21的电感器件1和虚拟金属3填充黑色图案，第二层金属层22的虚拟金属3填充倾斜线，第三层金属层23的虚拟金属3不填充图案(也即白色底色)。在本实施例中，多层金属层2中的虚拟金属3对齐排列，则底层结构的虚拟金属3会被顶层结构的虚拟金属3所遮挡，例如第二层金属层22中的部分虚拟金属3被第一层金属层21中的虚拟金属3遮挡。第二层金属层22中的部分虚拟金属3相对第一层金属层21中的虚拟金属3伸出，相对伸出的这部分虚拟金属3则露出。
在本实施例中，由于位于电感器件1下方的多个虚拟金属3呈阶梯状排布，因此多个虚拟金属3能够有效改善电感器件1下方的金属排布情况，使得电感器件1在化学机械抛光工艺过程中获得较高的制作精度，电感器件布线架构10及应用该电感器件布线架构10的集成电路100的产品良率更高，并且位于电感器件1下方的多个虚拟金属3能够尽量不排布在靠近电感器件1的区域，而排布在远离电感器件1的区域，从而减少虚拟金属3对电感器件1的电感器件性能的不良影响，使得电感器件1的性能更佳。
其中，排布于电感器件1所在金属层2的部分虚拟金属3与排布于电感器件1下方的虚拟金属3也可以呈阶梯状排布。例如，图3中，第二层金属层22对应的虚拟金属3相对 第一层金属层21对应的虚拟金属3伸出而形成阶梯形状。
例如：
如图3所示，第一层金属层21的多个虚拟金属3部分围绕电感器件1设置、部分排布于电感器件1所环绕的中部空间中。位于电感器件1的中部空间的虚拟金属3中最靠近电感器件1的虚拟金属3与电感器件1之间形成间距S1。位于电感器件1的中部空间的相邻的两个虚拟金属3之间形成间距S2。S1大于S2。此时，第一层金属层21的虚拟金属3对电感器件1的性能影响较小，电感器件1的电感性能较佳。同样的，位于电感器件1外周的部分虚拟金属3中与电感器件1之间的间距，大于位于电感器件1外周的相邻两个虚拟金属3之间的间距。
在本实施例中，第一层金属层21的多个虚拟金属3可以等间距排布、也可以不等间距排布，本申请对此不做严格限定。其中，本申请中相邻的两个虚拟金属3之间的“间距”是指位于电感器件1同一侧的两个虚拟金属3之间的间距。
在本实施例中，第一层金属层21的虚拟金属3大致呈阵列排布(阵列中的部分区域不排布虚拟金属3)，相邻两个虚拟金属3之间的间距大致相等。其他实施例中，第一层金属层21的虚拟金属3也可以有其他排布方式，例如大致呈扩散环形排布、或者零散随机排布等。
第二层金属层22对应的多个虚拟金属3尽量远离电感器件1。例如，第二层金属层22在电感器件1的某段走线的斜下方排布虚拟金属3，以尽量增加第二层金属层22的金属排布面积，从而提高电感器件布线架构10的产品良率，且对电感器件1的性能影响较小。在第二层金属层22中，靠近电感器件1的某段走线的正下方空间的两个虚拟金属3之间的间距S4大于或等于相邻的两个虚拟金属3之间的间隙S5。
在本实施例中，第二层金属层22对应的部分虚拟金属3相对第一层金属层21的虚拟金属3伸出，第一层金属层21和第二层金属层22中靠近电感器件1的多个虚拟金属3大致呈阶梯状排布。
本实施例中，第二层金属层22的虚拟金属3的结构及尺寸设计可参考第一层金属层21的虚拟金属3。例如，S5等于S2。其他实施例中，第二层金属层22的虚拟金属3的结构及尺寸可设计也可以与第一层金属层21的虚拟金属不同。
其中，S1可以在1微米(μm)至15微米范围内。S1可以依据电感器件1所产生的电磁场范围进行设定。S2可以在0.1微米至10微米范围内。电感器件1的某段走线的宽度为W1。W1可以在1微米至20微米的范围内。虚拟金属3的宽度为W2。W2可以在0.1微米至10微米的范围内。在电感器件布线架构10的厚度方向(也即Z向)上，虚拟金属3的厚度为T1。T1可以在0.1微米至4微米的范围内。其中，虚拟金属3可采用铜或铝材料。电感器件1可采用铜或铝材料。电感器件1的材料与第一层金属层21的虚拟金属3的材料相同。
第三层金属层23对应的虚拟金属3的排布面积大于第二层金属层22对应的虚拟金属3的排布面积。第三层金属层23对应的部分虚拟金属3相对第二层金属层22对应的虚拟金属3伸出。本实施例中，第一层金属层21、第二层金属层22及第三层金属层23中的多个虚拟金属3呈阶梯状排布。
其中，第三层金属层23中的其中一个虚拟金属3位于电感器件1的某段走线正下方，该虚拟金属3与电感器件1的该段走线之间的间距为S3。其中，S3可以在1微米至15微米范围内。S3可以依据电感器件1的电磁场范围进行设计。
其中，第三层金属层23的虚拟金属3的结构及尺寸设计可参考第一层金属层21的虚拟金属3。其他实施例中，第三层金属层23的虚拟金属3的结构及尺寸可设计也可以与第一层金属层21的虚拟金属不同。
在本实施例中，电感器件布线架构10还包括多层介质层4。介质层4为对应的绝缘层130的一部分。相邻的两层金属层2之间均设置有介质层4。当金属层2中的虚拟金属3之间形成间隙时，间隙内填充绝缘材料以形成绝缘部分，该绝缘部分连接介质层4。
其中，电感器件布线架构10的各层介质层4的厚度可以相同。例如，如图3所示，介质层4的厚度为T2。T2可以在0.1微米至4微米范围内。
如图2和图3所示，本实施例中，电感器件1下方的多个虚拟金属3主要以呈现阶梯状的方式进行排布。其他实施例中，在满足加工需求和性能要求的情况下，电感器件1下方的多个虚拟金属3也可以呈现其他排布方式。
如图2和图3所示，本实施例中，电感器件1下方的多个虚拟金属3具有大致相同的形状和大小。其他实施例中，电感器件1下方的多个虚拟金属3也可以具有不同的形状和不同的大小。同样的，与位于电感器件1同层设置的多个虚拟金属3可以与电感器件1下方的多个虚拟金属3具有大致相同的形状和大小，也可以不同。
如图2所示，本实施例中，电感器件1下方的多个虚拟金属3呈方形。其他实施例中，电感器件1下方的多个虚拟金属3也可以是长条形、三角形、圆形、椭圆形、多边形、特殊形状等。本申请不对虚拟金属3的形状和大小做严格限定。
一种实施例中，电感器件布线架构10还包括位于多层金属层2下方的多晶硅(polycrystalline silicon)层(图未示出)。多晶硅层中包括多个多晶硅，用作集成电路100的PN结(将P型半导体与N型半导体制作在同一块半导体基片上，在它们的交界面就形成空间电荷区称为PN结，即PN junction)的栅极。多个多晶硅的排布也需要满足化学机械研磨的加工需求，以使多层金属层2平坦化。多个多晶硅的排布规律参阅前述多个虚拟金属3的排布规律。例如，当多晶硅层与电感器件1的距离较近时，多晶硅层中的多晶硅呈现远离电感器件1的趋势排布。具体的，多晶硅层中的多晶硅的排布面积和位于电感器件1下方的金属层2对应虚拟金属3的排布面积在远离电感器件1的方向上递增。多个多晶硅可以与位于电感器件1下方的多个虚拟金属3共同呈现阶梯状排布。
进一步地，在本申请中，电感器件布线架构10的电感器件1下方的多个虚拟金属3在满足：在远离电感器件1的方向上呈现由梳到密的排布规律时，可以有多种排布方式，例如：
一种排布方式中，在电感器件1下方，每层金属层2对应的虚拟金属3的个数均为多个，且每层金属层2对应的虚拟金属3与相邻金属层2对应的虚拟金属3交叉排列。换言之，电感器件1下方的虚拟金属3与位于其上方或下方的虚拟金属3大致呈彼此错开的位置关系。此时，位于电感器件1下方的多个虚拟金属3的排布较为规律，有利于降低设计成本和生产成本。
另一种排布方式中，在电感器件1下方，每层金属层2对应的虚拟金属3的个数均为多个，且每层金属层2对应的虚拟金属3与相邻金属层2对应的虚拟金属3或对齐排列。换言之，电感器件1下方的虚拟金属3与位于其上方或下方的虚拟金属3大致呈彼此正对的位置关系。此时，位于电感器件1下方的多个虚拟金属3的排布较为规律，有利于降低设计成本和生产成本。
再一种排布方式中，在电感器件1下方，每层金属层2对应的虚拟金属3的个数均为多个，且一层或多层金属层2对应的虚拟金属3与相邻金属层2对应的虚拟金属3交叉排列，一层或多层金属层2对应的虚拟金属3与相邻金属层2对应的虚拟金属3对齐排列。此时，电感器件布线架构10的电感器件1下方的部分虚拟金属3对齐排列、部分虚拟金属3交叉排列，丰富了虚拟金属3的排布方式，使得电感器件布线架构10的排布方式更为多样化。
具体的：
在图2和图3所示的第一实施例中，在电感器件1下方，每层金属层2对应的虚拟金属3与相邻的金属层2对应的虚拟金属3对齐排列。例如，第二层金属层22至第五层金属层25所对应的虚拟金属3对齐排列。一种实施例中，电感器件1下方的多个虚拟金属3的尺寸相同，则每层金属层2对应的相邻的两个虚拟金属3之间的间距相等，例如S5＝S2。
请一并参阅图4和图5，图4是图1所示电感器件布线架构10在第二实施例中的俯视图，图5是图4所示电感器件布线架构10的部分结构沿B-B线处剖开的截面示意图。其中，为了更清楚地表达图5中的结构，图5中各金属层2中的虚拟金属3的数量略有删减，但是整体排布规律不变。本实施例中与前述实施例相同的大部分技术内容不再赘述。
在第二实施例中，在电感器件1下方，每层金属层2对应的虚拟金属3与相邻的金属层2对应的虚拟金属3交叉排列。此时，电感器件1下方的层结构具有更均匀的金属排布面积，有利于提高电感器件1的加工精度，使得电感器件布线架构10的产品良率更高。
本实施例中，电感器件布线架构10包括第一层金属层21、第二层金属层22、第三层金属层23、第四层金属层24及第五层金属层25。电感器件1下方的第二层金属层22、第三层金属层23、第四层金属层24及第五层金属层25对应的虚拟金属3交叉排列。电感器件1所在的第一层金属层21的部分虚拟金属3与电感器件1下方的金属层(22/23/24/25)对应的虚拟金属3交叉排列。
请参阅图6，图6是图1所示电感器件布线架构10在第三实施例中的部分结构示意图。本实施例中与前述实施例相同的大部分技术内容不再赘述。
在第三实施例中，电感器件布线架构10包括电感器件1所在的第一层金属层21和位于电感器件1下方的多层金属层(第二层金属层22至第九层金属层29)。在远离电感器件1的方向Z上，第二层金属层22至第六层金属层26对应的虚拟金属3的排布面积递增。
在电感器件1下方，一层或多层金属层2对应的虚拟金属3与相邻金属层2对应的虚拟金属3交叉排列，且一层或多层金属层2对应的虚拟金属3与相邻金属层2对应的虚拟金属3对齐排列。例如，第二层金属层22对应的虚拟金属3、第三层金属层23对应的虚拟金属3及第四层金属层24对应的虚拟金属3对齐排列。第四层金属层24、第五层金属层25、第六层金属层26、第七层金属层27、第八层金属层28及第九层金属层29中，相 邻的两层金属层2对应的虚拟金属3交叉排列。此时，电感器件布线架构10中的位于电感器件1下方的多个虚拟金属3的排布方式更为多样化。
其中，第一层金属层21的部分虚拟金属3与第二层金属层22对应的虚拟金属3交叉排列。其他实施例中，第一层金属层21的部分虚拟金属3与第二层金属层22对应的虚拟金属3对齐排列。本申请不对电感器件布线架构10的多层金属层2的虚拟金属3的排布方式做严格限定。
进一步地，在本申请中，电感器件1下方的多层金属层2对应的虚拟金属3的排布面积的关系有多种实施方式，例如：
一种实施方式中，电感器件1下方的多层金属层2中，彼此相邻设置的至少三层金属层2对应的虚拟金属3的排布面积在远离电感器件1的方向Z上递增。此时，电感器件1下方的多个虚拟金属3呈现连续的阶梯状，有利于进一步改善电感器件布线架构10的加工质量，且电感器件1下方的多个虚拟金属3对电感器件1的性能影响更小。
另一种实施方式中，电感器件1下方的第i金属层对应的虚拟金属3的排布面积等于第i-1金属层对应的虚拟金属3的排布面积。第i金属层位于第i-1金属层远离电感器件1的一侧，也即第i金属层位于第i-1金属层的下方。i为整数且大于或等于2。
在本实施方式中，电感器件布线架构10在满足大体呈由梳到密的排布规律时，电感器件1的下方包括对应虚拟金属3的排布面积相同的两层金属层2，使得电感器件布线架构10中位于电感器件1下方的多个虚拟金属3的排布灵活性更高，排布方式更为多样化。其中，电感器件布线架构10中可以存在一组对应虚拟金属3的排布面积相同的两层金属层2，也可以是两组以上(包括本数)对应虚拟金属3的排布面积相同的两层金属层2。电感器件布线架构10中也可以存在对应虚拟金属3的排布面积相同的三层以上(包括本数)的金属层2。
其中，第i金属层对应的多个虚拟金属3等间距排布，且相邻两个虚拟金属3之间的排布间距为第i间距；第i-1金属层对应的多个虚拟金属3等间距排布，且相邻两个虚拟金属3之间的排布间距为第i-1间距；第i-1间距小于或等于第i间距。当第i-1间距小于第i间距时，虽然第i金属层对应的虚拟金属3的排布面积没有递增，但是第i金属层的多个虚拟金属3的排布范围较大、排布较为均匀，因此能够有效提高金属层2的加工质量，使得电感器件布线架构10的产品良率较高。当然，在其他实施例中，第i金属层和第i-1金属层对应的多个虚拟金属3的排布方式和排布间距也可以与上述方案不同，而依据需求设置。
再一种实施方式中，电感器件1下方的第j金属层对应的虚拟金属3的排布面积小于第j-1金属层对应的虚拟金属3的排布面积。第j金属层位于第j-1金属层远离电感器件1的一侧，即第j金属层位于第j-1金属层的下方。j为整数且大于或等于2。
在本实施方式中，电感器件布线架构10在满足大体呈由梳到密的排布规律时，电感器件1的下方包括对应虚拟金属3的排布面积倒置的两层金属层2，使得电感器件布线架构10中位于电感器件1下方的多个虚拟金属3的排布灵活性更高，排布方式更为多样化。其中，电感器件布线架构10中可以存在一组对应虚拟金属3的排布面积倒置的两层金属层2，也可以是两组以上(包括本数)对应虚拟金属3的排布面积倒置的两层金属层2。电感器件布线架构10中也可以存在对应虚拟金属3的排布面积倒置的三层以上(包括本数)的金 属层2。
其中，第j金属层对应的多个虚拟金属3等间距排布，且相邻两个虚拟金属3之间的排布间距为第j间距；第j-1金属层对应的多个虚拟金属3等间距排布，且相邻两个虚拟金属3之间的排布间距为第j-1间距；第j-1间距小于或等于第j间距。当第j-1间距小于第j间距时，对应虚拟金属3的排布面积较小的第j金属层对应的多个虚拟金属3的排布范围较大、排布较为均匀，能够有效提高金属层2的加工质量，使得电感器件布线架构10的产品良率较高。当然，在其他实施例中，第j金属层和第j-1金属层对应的多个虚拟金属3的排布方式和排布间距也可以与上述方案不同，而依据需求设置。
换言之，当电感器件1下方的多层金属层2中，至少两层金属层2对应的虚拟金属3的排布面积在远离电感器件1的方向上递增时，一层或多层金属层2对应的虚拟金属3的排布面积可以与相邻金属层2对应的虚拟金属3的排布面积相同或递减(在远离电感器件1的方向Z上)。此时，电感器件布线架构10也能够获得较高的产品良率。
其中，上述三种实施方式可以独立使用或组合使用。
例如：
请参阅图3，在第一实施例中，电感器件1排布在第一层金属层21。电感器件1下方的第二层金属层22和第三层金属层23对应的虚拟金属3的排布面积在远离电感器件1的方向上递增。
第四层金属层24(即为电感器件1下方的第3金属层)对应的虚拟金属3的排布面积等于第三层金属层23(即为电感器件1下方的第2金属层)对应的虚拟金属3的排布面积。第五层金属层25(即为电感器件1下方的第4金属层)对应的虚拟金属3的排布面积等于第四层金属层24(即为电感器件1下方的第3金属层)对应的虚拟金属3的排布面积。即，电感器件1下方的第i金属层对应的虚拟金属3的排布面积等于第i-1金属层对应的虚拟金属3的排布面积，第i金属层位于第i-1金属层远离电感器件1的一侧，i为整数且大于或等于2。
第四层金属层24(即为电感器件1下方的第3金属层)对应的多个虚拟金属3等间距排列，相邻两个虚拟金属3之间的排布间距为第三间距。第三层金属层23(即为电感器件1下方的第2金属层)对应的多个虚拟金属3等间距排列，相邻两个虚拟金属3之间的排布间距为第二间距。第二间距等于第三间距。第五层金属层25(即为电感器件1下方的第4金属层)对应的多个虚拟金属3等间距排列，相邻两个虚拟金属3之间的排布间距为第四间距。第四间距等于第三间距。
第三层金属层23(即为电感器件1下方的第2金属层)对应的虚拟金属3的排布面积、第四层金属层24(即为电感器件1下方的第3金属层)对应的虚拟金属3的排布面积及第五层金属层25(即为电感器件1下方的第4金属层)对应的虚拟金属3的排布面积相等。即，电感器件1下方存在对应虚拟金属3的排布面积相同的三层以上(包括本数)的金属层2。
请参阅图5，在第二实施例中，电感器件1排布在第一层金属层21。电感器件1下方的第二层金属层22、第三层金属层23以及第四层金属层24相邻设置，且第二层金属层22、第三层金属层23以及第四层金属层24对应的虚拟金属3的排布面积在远离电感器件1的 方向Z上递增。即，电感器件1下方的多层金属层2中，彼此相邻设置的至少三层金属层2对应的虚拟金属3的排布面积在远离电感器件1的方向Z上递增。
第五层金属层25(即为电感器件1下方的第4金属层)对应的虚拟金属3的排布面积小于第四层金属层24(即为电感器件1下方的第3金属层)对应的虚拟金属3的排布面积。第五层金属层25(即为电感器件1下方的第4金属层)对应的多个虚拟金属3等间距排列，相邻两个虚拟金属3之间的排布间距为第四间距。第四层金属层24(即为电感器件1下方的第3金属层)对应的多个虚拟金属3等间距排列，相邻两个虚拟金属3之间的排布间距为第三间距。第三间距等于第四间距。
请参阅图6，在第三实施例中，电感器件1排布在第一层金属层21。电感器件1下方的第二层金属层22、第三层金属层23、第四层金属层24、第五层金属层25及第六层金属层26相邻设置，且第二层金属层22至第六层金属层26对应的虚拟金属3的排布面积在远离电感器件1的方向上递增。
第六层金属层26(即为电感器件1下方的第5金属层)、第七层金属层27(即为电感器件1下方的第6金属层)、第八层金属层28(即为电感器件1下方的第7金属层)及第九层金属层29(即为电感器件1下方的第8金属层)对应的虚拟金属3的排布面积相等。此时，电感器件1下方存在对应虚拟金属3的排布面积相同的三层以上(包括本数)的金属层2。
在第六层金属层26(即为电感器件1下方的第5金属层)、第七层金属层27(即为电感器件1下方的第6金属层)、第八层金属层28(即为电感器件1下方的第7金属层)及第九层金属层29(即为电感器件1下方的第8金属层)中，各层金属层2对应的虚拟金属3的数量为多个，且不同金属层2中的相邻两个虚拟金属3之间的排列间距相等。其他实施例中，不同金属层2中的相邻两个虚拟金属3之间的排列间距也可以不相等。
请参阅图7，图7是图1所示电感器件布线架构10在第四实施例中的结构示意图。本实施例中与前述实施例相同的大部分技术内容不再赘述。
在第四实施例中，电感器件1排布在第一层金属层21。电感器件1下方的第三层金属层23和第四层金属层24对应的虚拟金属3的排布面积在远离电感器件1的方向Z上递增。
第二层金属层22和第四层金属层24间隔设置，第二层金属层22和第四层金属层24对应的虚拟金属3的排布面积在远离电感器件1的方向Z上递增。
第三层金属层23(即为电感器件1下方的第2金属层)对应的虚拟金属3的排布面积等于第二层金属层22(即为电感器件1下方的第1金属层)对应的虚拟金属3的排布面积。第五层金属层25(即为电感器件1下方的第4金属层对应)的虚拟金属3的排布面积等于第四层金属层24(即为电感器件1下方的第3金属层)对应的虚拟金属3的排布面积。此时，电感器件1下方可包括两组或两组以上的对应虚拟金属3的排布面积相等的两层金属层2。
第三层金属层23(即为电感器件1下方的第2金属层)对应的多个虚拟金属3中相邻的两个虚拟金属3之间的排布间距为第二间距S7。第二层金属层22(即为电感器件1下方的第1金属层)对应的多个虚拟金属3中相邻的两个虚拟金属3之间的排布间距为第一间距S6。第一间距S6等于第二间距S7。
第五层金属层25(即为电感器件1下方的第4金属层)对应的多个虚拟金属3中相邻的两个虚拟金属3之间的排布间距为第四间距。第四层金属层24(即为电感器件1下方的第3金属层)对应的多个虚拟金属3中相邻的两个虚拟金属3之间的排布间距为第三间距。第三间距等于第四间距。第三间距可以与第二间距相等或不等。
请参阅图8，图8是图1所示电感器件布线架构10在第五实施例中的结构示意图。本实施例中与前述实施例相同的大部分技术内容不再赘述。
在第五实施例中，电感器件1排布在第一层金属层21。电感器件1下方的第三层金属层23和第四层金属层24对应的虚拟金属3的排布面积在远离电感器件1的方向Z上递增。
第三层金属层23(即为电感器件1下方的第2金属层)对应的虚拟金属3的排布面积等于第二层金属层22(即为电感器件1下方的第1金属层对应)的虚拟金属3的排布面积。第三层金属层23(即为电感器件1下方的第2金属层)对应的多个虚拟金属3中相邻的两个虚拟金属3之间的排布间距为第二间距S7。第二层金属层22(即为电感器件1下方的第1金属层)对应的多个虚拟金属3中相邻的两个虚拟金属3之间的排布间距为第一间距S6。第一间距S6小于第二间距S7。
第五层金属层25(即为电感器件1下方的第4金属层)对应的虚拟金属3的排布面积小于第四层金属层24(即为电感器件1下方的第3金属层)对应的虚拟金属3的排布面积。第五层金属层25(即为电感器件1下方的第4金属层)对应的多个虚拟金属3中的多个虚拟金属3等间距排列，相邻两个虚拟金属3之间的排布间距为第四间距。第四层金属层24(即为电感器件1下方的第3金属层)对应的多个虚拟金属3等间距排列，相邻两个虚拟金属3之间的排布间距为第三间距。第三间距等于第四间距。
请参阅图9，图9是图1所示电感器件布线架构10在第六实施例中的部分结构示意图。本实施例中与前述实施例相同的大部分技术内容不再赘述。
在第六实施例中，电感器件1排布在第一层金属层21。电感器件1下方的第二层金属层22和第三层金属层23对应的虚拟金属3的排布面积在远离电感器件1的方向上递增。第四层金属层24、第五层金属层25及第六层金属层26对应的虚拟金属3的排布面积在远离电感器件1的方向上递增。
第四层金属层24(即为电感器件1下方的第3金属层)对应的虚拟金属3的排布面积等于第三层金属层23(即为电感器件1下方的第2金属层)对应的虚拟金属3的排布面积。第六层金属层26(即为电感器件1下方的第5金属层)、第七层金属层27(即为电感器件1下方的第6金属层)、第八层金属层28(即为电感器件1下方的第7金属层)及第九层金属层29(即为电感器件1下方的第8金属层)对应的虚拟金属3的排布面积相等。
请参阅图10，图10是图1所示电感器件布线架构10在第七实施例中的结构示意图。本实施例中与前述实施例相同的大部分技术内容不再赘述。
在第七实施例中，电感器件1排布在第一层金属层21。电感器件1下方的第三层金属层23和第四层金属层24对应的虚拟金属3的排布面积在远离电感器件1的方向上递增。
第三层金属层23(即为电感器件1下方的第2金属层)对应的虚拟金属3的排布面积小于第二层金属层22(即为电感器件1下方的第1金属层)对应的虚拟金属3的排布面积。第三层金属层23(即为电感器件1下方的第2金属层)对应的多个虚拟金属3中相邻的两 个虚拟金属3之间的排布间距为第二间距S7。第二层金属层22(即为电感器件1下方的第1金属层)对应的多个虚拟金属3中相邻的两个虚拟金属3之间的排布间距为第一间距S6。第一间距S6等于第二间距S7。
第五层金属层25(即为电感器件1下方的第4金属层)对应的虚拟金属3的排布面积等于第四层金属层24(即为电感器件1下方的第3金属层)对应的虚拟金属3的排布面积。第五层金属层25(即为电感器件1下方的第4金属层)对应的多个虚拟金属3中的相邻两个虚拟金属3之间的排布间距等于第四层金属层24(即为电感器件1下方的第3金属层)对应的多个虚拟金属3中的相邻两个虚拟金属3之间的排布间距。
请参阅图11，图11是图1所示电感器件布线架构10在第八实施例中的结构示意图。本实施例中与前述实施例相同的大部分技术内容不再赘述。
在第八实施例中，电感器件1排布在第一层金属层21。电感器件1下方的第三层金属层23和第四层金属层24对应的虚拟金属3的排布面积在远离电感器件1的方向上递增。
第三层金属层23(即为电感器件1下方的第2金属层)对应的虚拟金属3的排布面积小于第二层金属层22(即为电感器件1下方的第1金属层)对应的虚拟金属3的排布面积。
第三层金属层23(即为电感器件1下方的第2金属层)对应的多个虚拟金属3中相邻的两个虚拟金属3之间的排布间距为第二间距S7。第二层金属层22(即为电感器件1下方的第1金属层)对应的多个虚拟金属3中相邻的两个虚拟金属3之间的排布间距为第一间距S6。第一间距S6小于第二间距S7。
第五层金属层25(即为电感器件1下方的第4金属层)对应的虚拟金属3的排布面积等于第四层金属层24(即为电感器件1下方的第3金属层)对应的虚拟金属3的排布面积。
第五层金属层25(即为电感器件1下方的第4金属层)对应的多个虚拟金属3中的相邻两个虚拟金属3之间的排布间距、等于第四层金属层24(即为电感器件1下方的第3金属层)对应的多个虚拟金属3中的相邻两个虚拟金属3之间的排布间距。
请参阅图12，图12是图1所示电感器件布线架构10在第九实施例中的部分结构示意图。本实施例中与前述实施例相同的大部分技术内容不再赘述。
在第九实施例中，电感器件1排布在第一层金属层21。电感器件1下方的第三层金属层23和第四层金属层24对应虚拟金属3的排布面积在远离电感器件1的方向上递增。第五层金属层25和第六层金属层26对应虚拟金属3的排布面积在远离电感器件1的方向上递增。
第三层金属层23(即为电感器件1下方的第2金属层)对应的虚拟金属3的排布面积小于第二层金属层22(即为电感器件1下方的第1金属层)对应的虚拟金属3的排布面积。第五层金属层25(即为电感器件1下方的第4金属层)对应的虚拟金属3的排布面积小于第四层金属层24(即为电感器件1下方的第3金属层)对应的虚拟金属3的排布面积。
第三层金属层23(即为电感器件1下方的第2金属层)对应的多个虚拟金属3中的多个虚拟金属3等间距排列，相邻两个虚拟金属3之间的排布间距为第二间距。第三层金属层23(即为电感器件1下方的第2金属层)对应的多个虚拟金属3等间距排列，相邻两个虚拟金属3之间的排布间距为第一间距。第一间距等于第二间距。
第五层金属层25(即为电感器件1下方的第4金属层)对应的多个虚拟金属3等间距 排列，相邻两个虚拟金属3之间的排布间距为第四间距。第四层金属层24(即为电感器件1下方的第3金属层)对应的多个虚拟金属3等间距排列，相邻两个虚拟金属3之间的排布间距为第三间距。第三间距等于第四间距。
第六层金属层26(即为电感器件1下方的第5金属层)、第七层金属层27(即为电感器件1下方的第6金属层)、第八层金属层28(即为电感器件1下方的第7金属层)及第九层金属层29(即为电感器件1下方的第8金属层)对应的虚拟金属3的排布面积相等。
请参阅图13，图13是图1所示电感器件布线架构10在第十实施例中的部分结构示意图。本实施例中与前述实施例相同的大部分技术内容不再赘述。
第十实施例中，电感器件1排布在第一层金属层21。电感器件1下方的第二层金属层22和第三层金属层23对应的虚拟金属3的排布面积在远离电感器件1的方向上递增。第四层金属层24、第五层金属层25及第六层金属层26相邻设置，且在远离电感器件1的方向上，其对应的虚拟金属3的排布面积递增。
第二层金属层22(即为电感器件1下方的第1金属层)对应的虚拟金属3的排布面积与第一层金属层21(即为电感器件1所在金属层)对应的虚拟金属3的排布面积相等。第二层金属层22(即为电感器件1下方的第1金属层)对应的多个虚拟金属3中相邻的两个虚拟金属之间的排布间距，大于第一层金属层21(即为电感器件1所在金属层)对应的多个虚拟金属3中相邻的两个虚拟金属之间的排布间距。
第四层金属层24(即为电感器件1下方的第3金属层)对应的虚拟金属3的排布面积小于第三层金属层24(即为电感器件1下方的第2金属层)对应的虚拟金属3的排布面积。第四层金属层24(即为电感器件1下方的第3金属层)对应的多个虚拟金属3等间距排列，相邻两个虚拟金属3之间的排布间距为第三间距。第三层金属层24(即为电感器件1下方的第2金属层)对应的多个虚拟金属3等间距排列，相邻两个虚拟金属3之间的排布间距为第二间距。第二间距小于第三间距。
第六层金属层26(即为电感器件1下方的第5金属层)、第七层金属层27(即为电感器件1下方的第6金属层)、第八层金属层28(即为电感器件1下方的第7金属层)及第九层金属层29(即为电感器件1下方的第8金属层)对应的虚拟金属3的排布面积相等。在本申请中，前述第一实施例至第十实施例中对于电感器件1下方的多个虚拟金属3的排布关系做示意性说明，并不形成对电感器件1下方的多个虚拟金属3的排布关系(例如单层金属层2中的排布间距的关系、及多层金属层2之间的排布间距)的严格限定。例如，在前述第一实施例至第十实施例中，电感器件1下方的金属层2中的多个虚拟金属3也可以随机排布，或者呈其他排布规律。
进一步地，在本申请中，电感器件1可以有多种实现结构。例如，电感器件1可以为具有双端口的电感或者具有四端口的变压器(transformer)。电感器件1可排布于同一层金属层中；或者，电感器件1可以包括上电感和下电感，上电感和下电感排布于相邻的两层金属层中。
一种实现结构中，如图2所示，电感器件布线架构10中电感器件1为具有双端口的电感。
请参阅图14，图14是图1所示电感器件布线架构10的电感器件1的一种实现结构。 图14示意出电感器件布线架构10的电感器件1所在金属层的俯视图。
另一种实现结构中，电感器件布线架构10中电感器件1为具有双端口的螺旋电感。螺旋电感排布于同一层金属层中。螺旋电感的两个端口11之间形成180°。螺旋电感的主体结构排布于同一层金属层中。电感器件1所在金属层中还包括多个虚拟金属3。部分虚拟金属3围绕在螺旋电感的外周排布。部分虚拟金属3排布在螺旋电感所围绕出的中部空间中。图14中，电感器件1的布线区域通过电感器件1外周的虚线框示意。
请参阅图15，图15是图1所示电感器件布线架构10的电感器件1的另一种实现结构。图15示意出电感器件布线架构10的电感器件1所在金属层的俯视图。
再一种实现结构中，电感器件布线架构10中电感器件1为具有双端口的螺旋电感。螺旋电感的两个端口11之间形成90°。螺旋电感的主体结构排布于同一层金属层中。电感器件1所在金属层中还包括多个虚拟金属3。部分虚拟金属3围绕在螺旋电感的外周排布。部分虚拟金属3排布在螺旋电感所围绕出的中部空间中。图15中，电感器件1的布线区域通过电感器件1外周的虚线框示意。
请参阅图16，图16是图1所示电感器件布线架构10的电感器件1的再一种实现结构。图16示意出电感器件布线架构10的电感器件1所在金属层的俯视图。
再一种实现结构中，电感器件布线架构10中电感器件1为具有双端口的差分电感。差分电感的主体结构排布于同一层金属层中。电感器件1所在金属层中还包括多个虚拟金属3。部分虚拟金属3围绕在差分电感的外周排布。部分虚拟金属3排布在差分电感所围绕出的中部空间中。图16中，电感器件1的布线区域通过电感器件1外周的虚线框示意。
请参阅图17，图17是图1所示电感器件布线架构10的电感器件1的再一种实现结构。图17示意出电感器件布线架构10的电感器件1所在金属层的俯视图。
再一种实现结构中，电感器件布线架构10中电感器件1为具有双端口的方形电感。方形电感的主体结构排布于同一层金属层中。电感器件1所在金属层中还包括多个虚拟金属3。部分虚拟金属3围绕在方形电感的外周排布。部分虚拟金属3排布在方形电感所围绕出的中部空间中。图17中，电感器件1的布线区域通过电感器件1外周的虚线框示意。
本实现结构中，方形电感为差分电感。其他实现结构中，方形电感也可以为其他电感。其他实现结构中，电感也可以为其他形状的电感，例如圆形、多边形等，本申请对此不做严格限定。
请参阅图18，图18是图1所示电感器件布线架构10的电感器件1的再一种实现结构。图18示意出电感器件布线架构10的电感器件1所在金属层的俯视图。
再一种实现结构中，电感器件布线架构10中电感器件1为具有四端口的变压器。变压器中包括两个相互缠绕的线圈。每个线圈具有两个端口11。变压器的主体结构排布于同一层金属层中。电感器件1所在金属层中还包括多个虚拟金属3。部分虚拟金属3围绕在变压器的外周排布。部分虚拟金属3排布在变压器所围绕出的中部空间中。图18中，电感器件1的布线区域通过电感器件1外周的虚线框示意。
请参阅图19，图19是图1所示电感器件布线架构10的电感器件1的再一种实现结构。图19示意出电感器件1立体结构示意图。
再一种实现结构中，电感器件1可以包括上电感12和下电感13。上电感12和下电感 13排布于相邻的两层金属层中。其中，上电感12和下电感13可通过过孔中的导电材料14连接，使电感器件1作为多层金属串联电感(serial)使用。
本实现结构中，电感器件1的布线区域包括上电感12的最外圈走线的外边缘所围绕区域和下电感13的最外圈走线的外边缘所围绕区域。
可以理解的是，前述电感器件1的多种实现结构均应用于前述第一实施例至第十实施例所示的电感器件布线架构10中。
在本申请中，电感器件布线架构10中的电感器件1也可以更换成其他传输导线，而形成传输导线布线架构。传输导线可用于传输频率大于100兆赫兹的信号。例如，传输导线可以是用于传输射频信号的关键信号线。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (14)

  1. 一种电感器件布线架构，其特征在于，包括：
    电感器件及位于所述电感器件下方的多个虚拟金属；
    其中，所述多个虚拟金属排布在多层金属层中，所述多层金属层中每层金属层对应所述多个虚拟金属的部分虚拟金属，在远离所述电感器件的方向上，所述多层金属层中的至少两层金属层对应的虚拟金属的排布面积递增。
  2. 根据权利要求1所述的电感器件布线架构，其特征在于，所述多个虚拟金属呈阶梯状排布。
  3. 根据权利要求1或2所述的电感器件布线架构，其特征在于，在所述多层金属层中，彼此相邻设置的至少三层金属层对应的虚拟金属的排布面积在远离所述电感器件的方向上递增。
  4. 根据权利要求1至3中任一项所述的电感器件布线架构，其特征在于，所述电感器件下方的第i金属层对应的虚拟金属的排布面积等于第i-1金属层对应的虚拟金属的排布面积，所述第i金属层位于所述第i-1金属层远离所述电感器件的一侧，i为整数且大于或等于2。
  5. 根据权利要求4所述的电感器件布线架构，其特征在于，所述第i金属层对应的多个虚拟金属等间距排布，且相邻两个虚拟金属之间的排布间距为第i间距；所述第i-1金属层对应的多个虚拟金属等间距排布，且相邻两个虚拟金属之间的排布间距为第i-1间距；所述第i-1间距小于所述第i间距。
  6. 根据权利要求1至5中任一项所述的电感器件布线架构，其特征在于，所述电感器件下方的第j金属层对应的虚拟金属的排布面积小于第j-1金属层对应的虚拟金属的排布面积，所述第j金属层位于所述第j-1金属层远离所述电感器件的一侧，j为整数且大于或等于2。
  7. 根据权利要求6所述的电感器件布线架构，其特征在于，所述第j金属层对应的多个虚拟金属等间距排布，且相邻两个虚拟金属之间的排布间距为第j间距；所述第j-1金属层对应的多个虚拟金属等间距排布，且相邻两个虚拟金属之间的排布间距为第j-1间距；所述第j-1间距小于所述第j间距。
  8. 根据权利要求1至7中任一项所述的电感器件布线架构，其特征在于，在所述电感器件下方，每层所述金属层对应的虚拟金属的个数均为多个，且每层所述金属层对应的虚拟金属与相邻金属层对应的虚拟金属交叉排列。
  9. 根据权利要求1至5以及7中任一项所述的电感器件布线架构，其特征在于，在所述电感器件下方，每层所述金属层的所述虚拟金属的个数均为多个，且每层所述金属层对应的虚拟金属与相邻金属层对应的虚拟金属对齐排列。
  10. 根据权利要求1至7中任一项所述的电感器件布线架构，其特征在于，在所述电感器件下方，每层所述金属层对应的虚拟金属的个数均为多个，且一层或多层所述金属层对应的虚拟金属与相邻金属层对应的虚拟金属交叉排列，一层或多层所述金属层对应的虚拟金属与相邻金属层对应的虚拟金属对齐排列。
  11. 根据权利要求1至10中任一项所述的电感器件布线架构，其特征在于，所述电感器件为具有双端口的电感或者具有四端口的变压器。
  12. 根据权利要求1至11中任一项所述的电感器件布线架构，其特征在于，所述电感器件排布于同一层金属层中；或者，所述电感器件包括上电感和下电感，所述上电感和所述下电感排布于相邻的两层金属层中。
  13. 一种集成电路，其特征在于，包括权利要求1至12中任一项所述的电感器件布线架构。
  14. 一种通信设备，其特征在于，包括权利要求13所述的集成电路。
PCT/CN2019/080664 2019-03-29 2019-03-29 电感器件布线架构、集成电路及通信设备 Ceased WO2020199036A1 (zh)

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