WO2020211093A1 - 电容器及其制作方法 - Google Patents

电容器及其制作方法 Download PDF

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Publication number
WO2020211093A1
WO2020211093A1 PCT/CN2019/083533 CN2019083533W WO2020211093A1 WO 2020211093 A1 WO2020211093 A1 WO 2020211093A1 CN 2019083533 W CN2019083533 W CN 2019083533W WO 2020211093 A1 WO2020211093 A1 WO 2020211093A1
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Prior art keywords
layer
conductive layer
external electrode
conductive
wing
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PCT/CN2019/083533
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English (en)
French (fr)
Inventor
陆斌
沈健
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Priority to EP19924710.7A priority Critical patent/EP3780044B1/en
Priority to CN201980000563.1A priority patent/CN112119476B/zh
Priority to PCT/CN2019/083533 priority patent/WO2020211093A1/zh
Priority to US17/033,758 priority patent/US11469168B2/en
Publication of WO2020211093A1 publication Critical patent/WO2020211093A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/008—Selection of materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/33—Thin- or thick-film capacitors (thin- or thick-film circuits; capacitors without a potential-jump or surface barrier specially adapted for integrated circuits, details thereof, multistep manufacturing processes therefor)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/38—Multiple capacitors, i.e. structural combinations of fixed capacitors
    • H01G4/385—Single unit multiple capacitors, e.g. dual capacitor in one coil
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/682—Capacitors having no potential barriers having dielectrics comprising perovskite structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/696—Electrodes comprising multiple layers, e.g. comprising a barrier layer and a metal layer

Definitions

  • This application relates to the field of capacitors, and more specifically, to capacitors and methods of making them.
  • Capacitors can play the role of bypassing, filtering, decoupling, etc. in the circuit, and are an indispensable part of ensuring the normal operation of the circuit.
  • MLCC Multi-layer Ceramic Capacitors
  • the present application provides a capacitor and a manufacturing method thereof, which can manufacture a capacitor with a small volume and a high capacitance value density.
  • a capacitor which includes:
  • At least one multi-wing structure At least one multi-wing structure
  • a laminated structure covering the at least one multi-wing structure, the laminated structure comprising at least one dielectric layer and a plurality of conductive layers, the at least one dielectric layer and the multilayer conductive layer Forming a structure in which the conductive layer and the dielectric layer are adjacent to each other;
  • At least one first external electrode the first external electrode electrically connected to a part of the conductive layer in the multilayer conductive layer;
  • At least one second external electrode is electrically connected to another part of the conductive layer in the multilayer conductive layer, and each conductive layer in the part of the conductive layer is adjacent to each other in the laminated structure
  • the conductive layer includes at least one conductive layer in the other part of the conductive layer.
  • the first external electrode is electrically connected to all odd-numbered conductive layers in the multilayer conductive layer
  • the second external electrode is electrically connected to all odd-numbered conductive layers in the multilayer conductive layer. Even number of conductive layers.
  • the multilayer conductive layer includes: a first conductive layer, and the first conductive layer is complementary to the multi-wing structure in shape.
  • the conductive layer and the dielectric layer other than the first conductive layer in the laminated structure are conformal to the multi-wing structure.
  • the capacitor further includes a filling structure that covers the laminated structure to fill the void formed by the laminated structure.
  • the filling structure is complementary in shape to the laminated structure.
  • the multi-wing structure is formed of a material with a resistivity less than a threshold, or the surface of the multi-wing structure is formed with a heavily doped conductive layer with a resistivity less than the threshold.
  • the conductive layer closest to the multi-wing structure in the laminated structure is electrically connected to the first external electrode, and the multi-wing structure is electrically connected to the second external electrode;
  • the conductive layer closest to the multi-wing structure in the laminated structure is electrically connected to the second external electrode, and the multi-wing structure is electrically connected to the first external electrode.
  • the multi-wing structure includes N shafts and M wings, wherein the N shafts extend in a first direction, and the M wings are side walls from the N shafts.
  • M is an integer greater than or equal to 2
  • N is a positive integer.
  • the M wings are formed of a first material
  • the area connecting the wings of the N shafts is formed of the first material
  • the N shafts are connected to the first material.
  • the area outside the area of the wing is formed of a second material different from the first material.
  • the first wing and the N shafts of the M wings are formed of a third material, and the wings of the M wings other than the first wing are formed by the A fourth material different from the third material is formed.
  • the first wing is located above the remaining wings of the M wings.
  • the capacitor further includes: a substrate disposed under the multi-wing structure.
  • the capacitor further includes:
  • the isolation ring is located on the outer side of the at least one multi-wing structure, and the isolation ring is disposed in the laminated structure and extends from the upper surface of the laminated structure along the first direction into or through the laminated structure.
  • Layer structure to isolate the stacked structure into a first area and a second area, and the first external electrode and/or the second external electrode are only electrically connected to the stacked structure located in the first area connection.
  • the multi-wing structure extends from the upper surface of the substrate into the substrate along the first direction.
  • the stacked structure extends from the upper surface of the substrate into the substrate along the first direction.
  • the substrate is a substrate with a resistivity less than a threshold
  • the first external electrode is disposed under the substrate
  • the second external electrode is disposed on the multi-wing structure.
  • the capacitor further includes: an electrode layer disposed above the multi-wing structure, the electrode layer includes at least one first conductive area and at least one second conductive area that are separated from each other, so The first conductive area forms the first external electrode, and the second conductive area forms the second external electrode.
  • the first external electrode and/or the second external electrode are electrically connected to the conductive layer in the multilayer conductive layer through an interconnection structure.
  • the interconnection structure includes at least one insulating layer and a conductive channel, and the conductive channel penetrates the at least one insulating layer to electrically connect the conductive layers in the multilayer conductive layer.
  • the conductive layer includes at least one of the following:
  • the dielectric layer includes at least one of the following:
  • Silicon oxide layer silicon nitride layer, silicon oxynitride layer, metal oxide layer, metal nitride layer and metal oxynitride layer.
  • a method for manufacturing a capacitor including:
  • a laminate structure is prepared on the surface of the at least one multi-wing structure, the laminate structure covers the multi-wing structure, the laminate structure includes at least one dielectric layer and a plurality of conductive layers, and the at least one dielectric layer
  • the layer and the multilayer conductive layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other;
  • each conductive layer of the part of the conductive layer in the laminated structure includes at least one conductive layer in the other part of the conductive layer.
  • the first external electrode is electrically connected to all odd-numbered conductive layers in the multilayer conductive layer
  • the second external electrode is electrically connected to all odd-numbered conductive layers in the multilayer conductive layer. Even number of conductive layers.
  • the preparing at least one multi-wing structure above the substrate includes:
  • a multilayer structure is prepared over the substrate, the multilayer structure includes at least two first material layers and at least one second material layer, and the at least two first material layers and the at least one second material layer form a A structure in which a material layer and a second material layer are adjacent to each other, the first material is different from the second material, and the first material layer is in direct contact with the substrate;
  • Preparing at least one first groove on the multilayer structure the first groove extending from the upper surface of the multilayer structure into the multilayer structure along a first direction;
  • a part of the second material layer exposed in the first trench is removed to form the at least one multi-wing structure.
  • the preparing at least one multi-wing structure above the substrate includes:
  • a multilayer structure is prepared over the substrate, the multilayer structure includes at least one fourth material layer and at least one fifth material layer, and the at least one fourth material layer and the at least one fifth material layer form a fourth material A structure in which a layer and a fifth material layer are adjacent to each other, the fourth material is different from the fifth material, and the fourth material layer is in direct contact with the substrate;
  • Preparing at least one first groove on the multilayer structure the first groove extending from the upper surface of the multilayer structure into the multilayer structure along a first direction;
  • At least one second trench is prepared on the first structure, and the second trench extends from the upper surface of the first structure into the multilayer structure along the first direction to expose the at least A fifth material layer, and the second groove is located outside the first groove;
  • the fifth material layer exposed in the second trench is removed to form the at least one multi-wing structure.
  • the multilayer conductive layer includes: a first conductive layer, and the first conductive layer is complementary to the multi-wing structure in shape.
  • the conductive layer and the dielectric layer other than the first conductive layer in the laminated structure are conformal to the multi-wing structure.
  • the method further includes:
  • a filling structure is prepared, and the filling structure covers the laminated structure to fill the voids formed by the laminated structure.
  • the filling structure is complementary in shape to the laminated structure.
  • the multi-wing structure is formed of a material with a resistivity less than a threshold, or the surface of the multi-wing structure is formed with a heavily doped conductive layer with a resistivity less than the threshold.
  • the conductive layer closest to the multi-wing structure in the laminated structure is electrically connected to the first external electrode, and the multi-wing structure is electrically connected to the second external electrode;
  • the conductive layer closest to the multi-wing structure in the laminated structure is electrically connected to the second external electrode, and the multi-wing structure is electrically connected to the first external electrode.
  • the multi-wing structure includes N shafts and M wings, wherein the N shafts extend along the first direction, and the M wings extend from the N shafts.
  • the method further includes:
  • the isolation ring is located on the outer side of the at least one multi-wing structure, and the isolation ring is disposed in the laminated structure and extends from the upper surface of the laminated structure in the first direction Or pass through the laminated structure to isolate the laminated structure into a first region and a second region, and the first external electrode and/or the second external electrode are only connected to all the external electrodes located in the first region.
  • the laminated structure is electrically connected.
  • the multi-wing structure extends from the upper surface of the substrate into the substrate along the first direction.
  • the stacked structure extends from the upper surface of the substrate into the substrate along the first direction.
  • the preparing at least one first external electrode and at least one second external electrode includes:
  • An electrode layer is prepared above the laminated structure, the electrode layer includes at least one first conductive region and at least one second conductive region that are separated from each other, the first conductive region forms the first external electrode, and the second conductive region Two conductive regions form the second external electrode.
  • the substrate is a substrate with a resistivity less than a threshold
  • the preparing at least one first external electrode and at least one second external electrode includes:
  • the at least one second external electrode is prepared above the multi-wing structure.
  • the method further includes:
  • An interconnection structure is prepared so that the first external electrode and/or the second external electrode are electrically connected to the conductive layer in the multilayer conductive layer through the interconnection structure.
  • the interconnection structure includes at least one insulating layer and a conductive channel, and the conductive channel penetrates the at least one insulating layer to electrically connect the conductive layers in the multilayer conductive layer.
  • the multi-wing structure is used as the framework, and the laminated structure is arranged on the multi-wing structure, so that the surface area of the laminated structure can be increased, and a larger capacitance value can be obtained with a smaller device size. Therefore, it is possible to increase the capacitance density of a capacitor formed with a laminated structure. Furthermore, in the embodiments of the present application, a laminated structure in which conductive layers and dielectric layers are alternately stacked can make fuller use of the multi-wing structure as a skeleton to increase the surface area of the laminated structure, thereby further increasing the capacitance density of the capacitor .
  • Fig. 1 is a schematic structural diagram of a capacitor according to an embodiment of the present application.
  • Fig. 2 is a schematic diagram of the material of a multi-wing structure according to an embodiment of the application.
  • Figure 3 is a schematic diagram of another multi-wing structure according to an embodiment of the present application.
  • Fig. 4 is a schematic structural diagram of a multi-wing structure according to an embodiment of the present application.
  • Fig. 5 is a schematic structural diagram of another multi-wing structure according to an embodiment of the present application.
  • Fig. 6 is a schematic structural diagram of still another multi-wing structure according to an embodiment of the present application.
  • Fig. 7 is a schematic structural diagram of another capacitor according to an embodiment of the present application.
  • Fig. 8 is a schematic structural diagram of still another capacitor according to an embodiment of the present application.
  • Fig. 9 is a schematic structural diagram of still another capacitor according to an embodiment of the present application.
  • Fig. 10 is a schematic structural diagram of still another capacitor according to an embodiment of the present application.
  • Fig. 11 is a schematic structural diagram of still another capacitor according to an embodiment of the present application.
  • Fig. 12 is a schematic structural diagram of still another capacitor according to an embodiment of the present application.
  • Fig. 13 is a schematic structural diagram of still another capacitor according to an embodiment of the present application.
  • Fig. 14 is a schematic structural diagram of still another capacitor according to an embodiment of the present application.
  • Fig. 15 is a schematic top view of an isolation ring according to an embodiment of the present application.
  • Fig. 16 is a schematic flowchart of a method for manufacturing a capacitor according to an embodiment of the present application.
  • 17a to 17s are schematic diagrams of a manufacturing method of a capacitor according to an embodiment of the present application.
  • capacitors in the embodiments of the present application can perform functions such as bypassing, filtering, and decoupling in the circuit.
  • the capacitor described in the embodiments of the present application may be a 3D silicon capacitor, which is a new type of capacitor based on semiconductor wafer processing technology. Compared with traditional MLCC (Multilayer Ceramic Capacitors), 3D silicon capacitors have the advantages of small size, high precision, high stability, and long life.
  • the basic processing flow requires processing high-aspect-ratio deep holes (Via), trenches (Trench), pillars (Pillar), wall (Wall) and other 3D structures on the wafer or substrate first, and then in the 3D structure An insulating film and a low-resistivity conductive material are deposited on the surface to make the lower electrode, the dielectric layer and the upper electrode of the capacitor in sequence.
  • 3D silicon capacitors draw on the concept of multi-layer nesting in DRAM manufacturing, alternately deposit conductor and insulator materials on the surface of the 3D structure to make a structure of multiple capacitors stacked vertically, and then use different types on the front of the silicon substrate.
  • the connection method connects all capacitors in parallel, and finally forms a capacitor with a large capacitance.
  • the current capacitance density of wafer-level 3D capacitors is still limited.
  • this application proposes a new type of capacitor structure and manufacturing method, which can improve the capacitance density of the capacitor.
  • the capacitors in FIGS. 1 to 14 are only examples, and the number of multi-wing structures included in the capacitor is not limited to that shown in the capacitors in FIGS. 1 to 14 and can be determined according to actual needs.
  • the number of wings and the number of shafts included in the multi-wing structure are just examples, and the number of wings and the number of shafts included in the multi-wing structure are not limited to those shown in the capacitors in Figures 1 to 14, and can be based on actual needs. Flexible settings.
  • FIG. 1 is a possible structure diagram of a capacitor 100 according to an embodiment of the present application.
  • the capacitor 100 includes at least one multi-wing structure 110, a laminated structure 120, at least one first external electrode 130, and at least one second external electrode 140.
  • the laminated structure 120 covers the multi-wing structure 110, and the laminated structure 120 includes at least one dielectric layer and multiple conductive layers, and the at least one dielectric layer Layer and the multilayer conductive layer form a structure in which the conductive layer and the dielectric layer are adjacent to each other; the first external electrode 130 is electrically connected to a part of the conductive layer in the multilayer conductive layer; the second external electrode 140 is electrically connected to the multiple The other part of the conductive layer in the conductive layer, and each conductive layer of the part of the conductive layer in the laminated structure includes at least one conductive layer in the other part of the conductive layer.
  • two adjacent conductive layers in the multilayer conductive layer are electrically isolated by the dielectric layer.
  • the specific number of layers of the conductive layer and the dielectric layer can be flexibly configured according to actual needs, as long as the electrical isolation between two adjacent conductive layers in the multilayer conductive layer is satisfied.
  • the multi-wing structure is used as the skeleton, and the laminated structure is arranged on the multi-wing structure, so that the surface area of the laminated structure can be increased, and a larger device size can be obtained. Therefore, it is possible to increase the capacitance density of a capacitor formed with a laminated structure. Furthermore, in the embodiments of the present application, a laminated structure in which conductive layers and dielectric layers are alternately stacked can make fuller use of the multi-wing structure as a skeleton to increase the surface area of the laminated structure, thereby further increasing the capacitance density of the capacitor .
  • the multi-wing structure 110 is a skeleton, that is, the material selection of the multi-wing structure 110 can be more flexible, thereby simplifying the preparation process of the multi-wing structure 110.
  • the material of the multi-wing structure 110 is a conductive material
  • the multi-wing structure 110 can also be used as an electrode plate of the capacitor 100.
  • the multi-wing structure 110 is formed of a material with a resistivity less than a threshold, or the surface of the multi-wing structure 110 is formed with a heavily doped conductive layer with a resistivity less than the threshold.
  • the multi-wing structure 110 is formed of a material with a resistivity less than a threshold, which can ensure that the multi-wing structure 110 is conductive, that is, it can be used as an electrode plate of the capacitor 100.
  • the conductive layer closest to the multi-wing structure 110 in the laminated structure 120 is electrically connected to the first external electrode 130, and the multi-wing structure 110 is electrically connected to the second external electrode 140.
  • the conductive layer closest to the multi-wing structure 110 in the laminated structure 120 is electrically connected to the second external electrode 140, and the multi-wing structure 110 is electrically connected to the first external electrode 130.
  • the first external electrode 130 or the second external electrode 140 may be electrically connected to part or all of the at least one multi-wing structure 110.
  • different multi-wing structures 110 may be electrically connected through a low-resistivity substrate, and different multi-wing structures 110 may also be electrically connected through a conductive sheet or a metal interconnection structure.
  • the laminated structure 120 is conformal to the multi-wing structure 110.
  • the laminated structure 120 may have the same or substantially the same outline as the multi-wing structure 110, so that the laminated structure 120 can cover the multi-wing structure 110 and the laminated structure. 120 contact area, thus, the laminated structure 120 can obtain a larger surface area based on the multi-wing structure 110, thereby increasing the capacitance density of the capacitor.
  • external electrodes in the embodiments of the present application may also be referred to as pads or external pads.
  • the material of the first external electrode 130 and the second external electrode 140 may be metal, such as copper, aluminum, or the like.
  • the first external electrode 130 and the second external electrode 140 may also include low resistivity Ti, TiN, Ta, TaN layers as adhesion layers and/or barrier layers; they may also include some metal layers on the surface of the external electrodes, for example Ni, Pd (palladium), Au, Sn (tin), Ag are used for subsequent wire bonding or welding processes.
  • the conductive layer includes at least one of the following:
  • the material of the conductive layer in the laminated structure 120 may be heavily doped polysilicon, metal silicide (silicide), carbon, conductive polymers, metals such as Al, Cu, Ni, and tantalum nitride (TaN). , Titanium nitride (TiN), titanium aluminum nitride (TiAlN), tantalum silicon nitride (TaSiN), tantalum carbon nitride (TaCN) and other low-resistivity compounds, or a combination of the above materials, and a laminated structure.
  • the specific conductive material and layer thickness can be adjusted according to the capacitance, frequency characteristics, loss and other requirements of the capacitor.
  • the conductive layer in the laminated structure 120 may also include some other conductive materials, which is not limited in the embodiment of the present application.
  • the dielectric layer includes at least one of the following:
  • Silicon oxide layer silicon nitride layer, silicon oxynitride layer, metal oxide layer, metal nitride layer and metal oxynitride layer.
  • the material of the dielectric layer in the laminated structure 120 may be silicon oxide, silicon nitride, silicon oxynitride, metal oxide, metal nitride, or metal oxynitride.
  • SiO 2 , SiN, SiON, or high-k materials including aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, Y 2 O 3 , La 2 O 3 , HfSiO 4 , LaAlO 3 , SrTiO 3 , LaLuO 3 and so on.
  • the dielectric layer in the laminated structure 120 can be one layer or multiple laminated layers, and can be one material or a combination or mixture of multiple materials.
  • the specific insulating material and layer thickness can be adjusted according to the capacitance, frequency characteristics, loss and other requirements of the capacitor.
  • the dielectric layer in the stacked structure 120 may also include some other insulating materials, which is not limited in the embodiment of the present application.
  • the multi-wing structure 110 includes N shafts and M wings, wherein the N shafts extend along the first direction, and the M wings are side walls from the N shafts.
  • M is an integer greater than or equal to 2
  • N is a positive integer.
  • the M wings are formed of a first material 11, the area connecting the wings among the N shafts is formed by the first material 11, and among the N axes, except for connecting the wings The area outside the area is formed of a second material 12 different from the first material 11.
  • the first material 11 or the second material 12 may be silicon (including monocrystalline silicon, polycrystalline silicon, and amorphous silicon), silicon oxide, nitride or carbide, silicon-containing glass (including undoped silicon) Undoped Silicon Glass (USG), boro-silicate glass (BSG), phospho-silicate glass (PSG), boro-phospho-silicate glass (BPSG), aluminum ( Al), copper (Cu), nickel (Ni) and other metals, or metal nitrides, carbides, carbon, organic polymers, or a combination or laminated structure of the foregoing materials.
  • silicon-containing glass including undoped silicon
  • Undoped Silicon Glass USG
  • BSG boro-silicate glass
  • PSG phospho-silicate glass
  • BPSG boro-phospho-silicate glass
  • Al aluminum
  • Cu copper
  • Ni nickel
  • metal nitrides carbides, carbon, organic polymers, or a combination or laminated structure of the foregoing materials.
  • the second material 12 can be selectively removed. Specifically, in the same corrosion or etching environment, the difference in the corrosion (or etching) rate of the first material 11 and the second material 12 is greater than 5 times.
  • the first material 11 may be silicon
  • the second material 12 may be silicon oxide.
  • the silicon oxide can be removed with a hydrofluoric acid solution or gas and the silicon can be retained.
  • the first material 11 may be silicon oxide
  • the second material 12 may be silicon, using KOH or NaOH or Tetramethylammonium Hydroxide (TMAH) solution, or xenon difluoride (XeF 2 ) gas, The silicon can be removed while the silicon oxide remains.
  • TMAH Tetramethylammonium Hydroxide
  • XeF 2 xenon difluoride
  • the first material 11 may be silicon doped with concentrated boron
  • the second material 12 is silicon with a low or no doping concentration.
  • KOH or NaOH or TMAH solution can be used to remove the low or low doping concentration quickly. There is no doped silicon, while the dense boron-doped silicon is retained.
  • the first wing and the N shafts of the M wings are formed of a third material 13, and the wings of the M wings except the first wing are formed by the third wing.
  • a fourth material 14 different from the material 13 is formed.
  • the first wing is located above the remaining wings of the M wings.
  • the third material 13 or the fourth material 14 may be silicon (including monocrystalline silicon, polycrystalline silicon, and amorphous silicon), silicon oxide, nitride or carbide, silicon-containing glass (including USG, BSG) , PSG, BPSG), aluminum (Al), copper (Cu), nickel (Ni) and other metals, or metal nitrides, carbides, carbon, organic polymers, or a combination or laminate structure of the above materials.
  • the third material 13 and the fourth material 14 may also be the same.
  • the multi-wing structure 110 may be a variety of structures.
  • the capacitor 100 further includes: a filling structure 150 that covers the laminated structure 120 to fill the cavity formed by the laminated structure 120 Or gap.
  • the filling structure 150 is complementary to the laminated structure 120 in shape.
  • the filling structure 150 can be structurally complementary to the laminated structure 120, and the combination of the two can form a structure without voids or cavities inside, which improves the structural integrity and mechanical stability of the capacitor.
  • the material of the filling structure 150 may be a conductive material or some other materials.
  • the filling structure 150 can also be used as an electrode plate of the capacitor 100.
  • the stacked structure 120 includes two conductive layers and two dielectric layers, such as the conductive layer 121 and the conductive layer 122 shown in FIG. 7, and the dielectric layer 123 And dielectric layer 124.
  • the stacked structure 120 includes two conductive layers and two dielectric layers, such as the conductive layer 121 and the conductive layer 122 shown in FIG. 7, and the dielectric layer 123 And dielectric layer 124.
  • the conductive layer 121 is in direct contact with the multi-wing structure 110, that is, the conductive layer 121 is disposed on the surface of the multi-wing structure 110 and covers the multi-wing structure 110; the conductive layer 122 is disposed on the surface of the conductive layer 121 Above; the dielectric layer 123 is disposed between the conductive layer 121 and the conductive layer 122 to electrically isolate the conductive layer 121 and the conductive layer 122; the dielectric layer 124 is disposed between the conductive layer 122 and the filling structure 150 to separate the conductive layer 122 and The filling structure 150 is electrically isolated.
  • the first external electrode 130 is electrically connected to the conductive layer 121 and the filling structure 150, and the second external electrode 140 is electrically connected to the conductive layer 122.
  • the order of the at least one dielectric layer may be as follows: on the multi-wing structure, the distance from the multi-wing structure is ascending or descending.
  • the order of the multilayer conductive layer can also be: on the multi-wing structure, the distance from the multi-wing structure is ascending or descending.
  • the sequence of the at least one dielectric layer and the multi-layer conductive layer in the embodiment of the present application is described by taking the order of the distance from the multi-wing structure to the multi-wing structure from small to large as an example.
  • each conductive layer of the part of the conductive layer adjacent to the conductive layer in the laminated structure 120 includes at least one conductive layer of the other part of the conductive layer. Therefore, for different first external electrodes 130 and second external electrodes 140, the stacked structure 120 can form capacitors with different capacitances.
  • the capacitor 100 includes two first external electrodes and two second external electrodes
  • the two first external electrodes are respectively denoted as the first external electrode A and the first external electrode B
  • the two second external electrodes Denoted as the second external electrode C and the second external electrode D respectively
  • the laminated structure includes 5 conductive layers and 4 dielectric layers.
  • the 5 conductive layers are respectively denoted as conductive layer 1, conductive layer 2, and conductive layer 3.
  • Conductive layer 4 and Conductive layer 5 are denoted as dielectric layer 1, dielectric layer 2, dielectric layer 3, and dielectric layer 4, respectively.
  • first external electrode A is electrically connected to the conductive layer 1 and the conductive layer 3
  • first external electrode B is electrically connected to the conductive layer 1
  • second external electrode C is electrically connected
  • the second external electrode D is also electrically connected to the conductive layer 2 and the conductive layer 4.
  • the conductive Layer 1 and the conductive layer 2 form a capacitor 1
  • the capacitance value is denoted as C1
  • the conductive layer 2 and the conductive layer 3 form a capacitor 2
  • the capacitance value is denoted as C2
  • the conductive layer 3 and the conductive layer 4 form a capacitor 3
  • the capacitance The value is denoted as C3, capacitor 1
  • capacitor 2 and capacitor 3 are connected in parallel
  • the capacitor corresponding to D, the conductive layer 1 and the conductive layer 2 form a capacitor 1, the capacitance value is denoted as C1, the conductive layer 2 and the conductive layer 3 form a capacitor 2, the capacitance value is denoted as C2, the conductive layer 3 and the conductive layer Layer 4 forms a capacitor 3, the capacitance value is denoted as C3, the conductive layer 4 and the
  • the capacitors corresponding to the first external electrode A and the second external electrode D can also form a similar series-parallel structure, and the capacitors corresponding to the first external electrode B and the second external electrode C can also be similar.
  • the series-parallel structure will not be repeated here. Therefore, the stacked structure 120 can form capacitors with different capacitances.
  • first external electrode A is electrically connected to the conductive layer 1 and the conductive layer 5
  • first external electrode B is electrically connected to the conductive layer 3 and the conductive layer 5
  • second external electrode C is electrically connected to the conductive layer 2 and
  • the conductive layer 4 and the second external electrode D are also electrically connected to the conductive layer 4.
  • the conductive layer 1 and the conductive layer 2 form a capacitor 1
  • the capacitance is denoted as C1
  • the conductive layer 2 and the conductive layer 4 form a capacitor 2
  • the capacitance is denoted as C2
  • the capacitor 1 and the capacitor 2 are in parallel
  • the conductive layer 3 and the conductive layer 4 form a capacitor 3
  • the capacitance value is denoted as C3
  • the conductive layer 4 and the conductive layer 5 form
  • each first external electrode 130 in the at least one first external electrode 130 is electrically connected to all odd-numbered conductive layers in the multilayer conductive layer; each second external electrode in the at least one second external electrode 140 The electrode 140 is electrically connected to all even-numbered conductive layers in the multilayer conductive layer.
  • the capacitor 100 includes two first external electrodes and two second external electrodes
  • the two first external electrodes are respectively denoted as the first external electrode A and the first external electrode B
  • the two second external electrodes Denoted as the second external electrode C and the second external electrode D respectively
  • the laminated structure includes 5 conductive layers and 4 dielectric layers.
  • the 5 conductive layers are respectively denoted as conductive layer 1, conductive layer 2, and conductive layer 3.
  • Conductive layer 4 and Conductive layer 5 are denoted as dielectric layer 1, dielectric layer 2, dielectric layer 3, and dielectric layer 4, respectively.
  • the first external electrode A is electrically connected to the conductive layer 1, the conductive layer 3 and the conductive layer 5, and the first external electrode B is electrically connected to the conductive layer 1, the conductive layer 3 and the conductive layer 5, the second The external electrode C is electrically connected to the conductive layer 2 and the conductive layer 4, and the second external electrode D is also electrically connected to the conductive layer 2 and the conductive layer 4, so the first external electrode A corresponds to the second external electrode C
  • the conductive layer 1 and the conductive layer 2 form a capacitor 1, the capacitance value is denoted as C1, the conductive layer 2 and the conductive layer 3 form a capacitor 2, the capacitance value is denoted as C2, the conductive layer 3 and the conductive layer 4 A capacitor 3 is formed, the capacitance value is denoted as C3, the conductive layer 4 and the conductive layer 5 form a capacitor 4, and the capacitance value is denoted as C4.
  • the capacitor 100 further includes: a substrate 160 disposed under the multi-wing structure 120.
  • the first direction may be a direction perpendicular to the substrate 160.
  • Figure 1 Figure 2, Figure 3 and Figure 7.
  • the substrate 160 may be a silicon wafer, including monocrystalline silicon, polycrystalline silicon, and amorphous silicon.
  • the substrate 160 may also be other semiconductor substrates, including semiconductor-on-insulator (SOI) wafers, silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), etc.
  • SOI semiconductor-on-insulator
  • SiC silicon carbide
  • GaN gallium nitride
  • GaAs gallium arsenide
  • III -A compound semiconductor wafer of group V elements or a glass substrate; or an organic polymer substrate; or a substrate with an epitaxial layer, an oxide layer, or a doped layer on the surface.
  • the thickness of the substrate 160 can also be flexibly set according to actual needs. For example, when the thickness of the substrate 160 is too thick to meet the requirements, the substrate 160 can be Perform thinning treatment. Even the substrate 160 can be completely removed.
  • FIGS. 1, 2, 3, and 7 are cross sections along the longitudinal direction of the substrate.
  • the first external electrode 130 and/or the second external electrode 140 are electrically connected to the conductive layer in the multilayer conductive layer through the interconnection structure 170.
  • the interconnect structure 170 includes at least one insulating layer 171 and a conductive channel 172, and the conductive channel 172 penetrates the at least one insulating layer 171 to electrically connect the conductive layers in the multilayer conductive layer.
  • the interconnection structure 170 is disposed above the filling structure 150.
  • the at least one insulating layer 171 may also be referred to as an intermetal dielectric layer (IMD) or an interlayer dielectric layer (ILD).
  • IMD intermetal dielectric layer
  • ILD interlayer dielectric layer
  • the material of the at least one insulating layer 171 may be an organic polymer material, including polyimide, Parylene, benzocyclobutene (BCB), etc.; or some Inorganic materials, including spin-on glass (SOG), undoped silicon glass (USG), boro-silicate glass (BSG), phospho-silicate glass (PSG) ), boro-phospho-silicate glass (BPSG), silicon oxide synthesized from Tetraethyl Orthosilicate (TEOS), silicon oxide, nitride, ceramic; it can also be made of the above materials Combination or stacking.
  • organic polymer material including polyimide, Parylene, benzocyclobutene (BCB), etc.
  • Inorganic materials including spin-on glass (SOG), undoped silicon glass (USG), boro-silicate glass (BSG), phospho-silicate glass (PSG) ), boro-phospho-silicate glass (BPSG), silicon oxide synthesized from Tetraethyl Ortho
  • the material of the conductive channel 172 may be made of a low-resistivity conductive material, such as heavily doped polysilicon, tungsten, Ti, TiN, Ta, TaN.
  • the shape and number of the conductive channels 172 may be specifically determined according to the manufacturing process of the capacitor 100, which is not limited in the embodiment of the present application.
  • the stacked structure 120 includes two conductive layers and one dielectric layer, such as the conductive layer 121 and the conductive layer 122 as shown in FIG. 1, and the dielectric layer 123.
  • the conductive layer 121 is in direct contact with the multi-wing structure 110, that is, the conductive layer 121 is disposed on the surface of the multi-wing structure 110 and covers the multi-wing structure 110; the conductive layer 122 is disposed on the surface of the conductive layer 121 Above; the dielectric layer 123 is disposed between the conductive layer 121 and the conductive layer 122 to electrically isolate the conductive layer 121 and the conductive layer 122.
  • the at least one first external electrode 130 and the at least one second external electrode 140 are disposed above the multi-wing structure 110.
  • the capacitor 100 further includes: an electrode layer disposed above the multi-wing structure 110, and the electrode layer includes at least one first conductive region and at least one second conductive region that are separated from each other, the first conductive region The first external electrode 130 is formed, and the second conductive area forms the second external electrode 140, as shown in FIG. 1. That is, the at least one first external electrode 130 and the at least one second external electrode 140 can be formed by one etching, which reduces the etching steps.
  • the electrode layer is disposed above the interconnect structure 170, the first external electrode 130 is electrically connected to the conductive layer 121 through the conductive channel 172, and the second external electrode 140 The conductive channel 172 is electrically connected to the conductive layer 122.
  • the multilayer conductive layer includes: a first conductive layer, and the first conductive layer is complementary to the multi-wing structure 110 in shape.
  • the cavity or gap formed in the laminated structure 120 can be filled with the layer furthest from the multi-wing structure 110 in the multi-layer conductive layer to improve the structural integrity and mechanical stability of the capacitor.
  • the arrangement of the first conductive layer can fill the cavity or gap formed in the laminated structure 120, and the arrangement of the first conductive layer can improve the structural integrity and mechanical stability of the capacitor.
  • the conductive layer and the dielectric layer in the stacked structure 120 excluding the first conductive layer 125 are conformal to the multi-wing structure 120.
  • the stacked structure includes a conductive layer 121 and a conductive layer 122, and a dielectric layer 123, wherein the conductive layer 122 is the first conductive layer.
  • the conductive layer 121 is in direct contact with the multi-wing structure 110, that is, the conductive layer 121 is arranged on the surface of the multi-wing structure 110 and covers the multi-wing structure 110; the dielectric layer 123 is arranged on the upper surface of the conductive layer 121; the conductive layer 122 fills the stack A cavity or gap formed by the conductive layer 121 and the dielectric layer 123 in the layer structure 120, and the dielectric layer 123 is disposed between the conductive layer 121 and the conductive layer 122 to electrically isolate the conductive layer 121 and the conductive layer 122.
  • the first external electrode 130 is electrically connected to the conductive layer 121
  • the second external electrode 140 is electrically connected to the conductive layer 122.
  • the multi-wing structure 110 extends from the upper surface of the substrate 160 into the substrate 160 along the first direction.
  • the N axes in the multi-wing structure 110 extend from the upper surface of the substrate 160 into the substrate 160 along the first direction.
  • the mechanical stability of the multi-wing structure 110 can be increased.
  • the stacked structure 120 extends from the upper surface of the substrate 160 into the substrate 160 along the first direction.
  • the stacked structure 120 extends from the upper surface of the substrate 160 into the substrate 160 along the first direction.
  • the mechanical stability of the multi-wing structure 110 can be increased.
  • the surface area of each conductive layer in the laminated structure 120 can also be increased, thereby increasing the capacitance density.
  • the filling structure 150 also extends into the substrate 160.
  • the substrate 160 when the substrate 160 is a low-resistivity substrate, the first external electrode 130 is disposed under the substrate 160, and the second external electrode 140 is disposed on the Above the multi-wing structure 110.
  • the first external electrode 130 is disposed below the substrate 160
  • the second external electrode 140 is disposed above the multi-wing structure 110
  • the first external electrode 130 passes through the substrate 160.
  • the conductive layer 121 is electrically connected
  • the second external electrode 140 is electrically connected to the conductive layer 122 through the interconnection structure 170.
  • the first external electrode 130 is disposed below the substrate 160, the second external electrode 140 is disposed above the multi-wing structure 110, and the first external electrode 130 passes through the substrate 160.
  • 160 is electrically connected to the conductive layer 121, and the second external electrode 140 is electrically connected to the conductive layer 122 through the conductive filling structure 150.
  • the substrate 160 is a low resistivity substrate, it can also be shown in FIG. 11 or FIG.
  • the first external electrode 130 is disposed under the substrate 160, and the second external electrode 140 is disposed above the multi-wing structure 110, which will not be repeated here.
  • the capacitor 100 further includes:
  • the isolation ring 180 is located outside the at least one multi-wing structure 110, and the isolation ring 180 is disposed in the laminated structure 120, and extends from the upper surface of the laminated structure 120 along the first direction into or through the laminated structure.
  • the layer structure 120 is used to isolate the stacked structure 120 into a first area 10 and a second area 20, and the first external electrode 130 and/or the second external electrode 140 are only connected to the overlap located in the first area 10
  • the layer structure 120 is electrically connected.
  • the material of the spacer ring 180 can be an organic polymer material, including polyimide, Parylene, benzocyclobutene (BCB), etc.; it can also be some inorganic materials , Including SOG, USG, BSG, PSG, BPSG, silicon oxide synthesized by TEOS, silicon oxide, nitride, ceramic; it can also be a combination or stack of the above materials.
  • organic polymer material including polyimide, Parylene, benzocyclobutene (BCB), etc.
  • it can also be some inorganic materials , Including SOG, USG, BSG, PSG, BPSG, silicon oxide synthesized by TEOS, silicon oxide, nitride, ceramic; it can also be a combination or stack of the above materials.
  • the isolation ring 180 extends along the first direction into the laminated structure 120 located at the edge of the capacitor chip, thereby isolating the laminated structure 120 into a first region 10 and a second region 20
  • the second external electrode 140 is only electrically connected to the laminated structure 120 located in the first area 10.
  • the isolation ring 180 extends along the first direction through the laminated structure 120, thereby isolating the laminated structure 120 into a first region 10 and a second region 20.
  • the external electrode 130 is only electrically connected to the stacked structure 120 located in the first area 10
  • the second external electrode 140 is only electrically connected to the stacked structure 120 located in the first area 10.
  • the top view of the isolation ring 180 may be as shown in FIG. 15.
  • the arrangement of the isolation ring 180 can make the laminated structure 120 located in the second region 20 not constitute the electrode plate of the capacitor, thereby avoiding the problem of air breakdown between the laminated structure 120 and the substrate 160 at the edge of the capacitor .
  • the multi-wing structure is used as the framework, and the laminated structure is arranged on the multi-wing structure, so that the surface area of the laminated structure can be increased, and a larger capacitance value can be obtained with a smaller device size. Therefore, it is possible to increase the capacitance density of a capacitor formed with a laminated structure. Furthermore, in the embodiments of the present application, a laminated structure in which conductive layers and dielectric layers are alternately stacked can make fuller use of the multi-wing structure as a skeleton to increase the surface area of the laminated structure, thereby further increasing the capacitance density of the capacitor .
  • the capacitors of the embodiments of the present application are described above, and the method for preparing the capacitors of the embodiments of the present application is described below.
  • the method for preparing a capacitor of the embodiment of the present application can prepare the capacitor of the foregoing embodiment of the present application, and the following embodiments and related descriptions in the foregoing embodiments may refer to each other.
  • FIG. 16 is a schematic flowchart of a method for manufacturing a capacitor in an embodiment of the present application, but these steps or operations are only examples, and the embodiment of the present application may also perform other operations or variations of each operation in FIG. 16.
  • FIG. 16 shows a schematic flowchart of a method 200 for manufacturing a capacitor according to an embodiment of the present application. As shown in FIG. 16, the manufacturing method 200 of the capacitor includes:
  • Step 210 preparing at least one multi-wing structure above the substrate
  • Step 220 Prepare a laminated structure on the surface of the at least one multi-wing structure, the laminated structure covering the multi-wing structure, the laminated structure including at least one dielectric layer and multiple conductive layers, the at least one dielectric layer and The multilayer conductive layer forms a structure in which the conductive layer and the dielectric layer are adjacent to each other;
  • Step 230 prepare at least one first external electrode and at least one second external electrode, wherein the first external electrode is electrically connected to a part of the conductive layer in the multilayer conductive layer, and the second external electrode is electrically connected to the multilayer conductive layer.
  • the other part of the conductive layer in the conductive layer, and each adjacent conductive layer of the part of the conductive layer in the laminated structure includes at least one conductive layer in the other part of the conductive layer.
  • the first external electrode 130 is electrically connected to all odd-numbered conductive layers in the multilayer conductive layer
  • the second external electrode 140 is electrically connected to all even-numbered conductive layers in the multilayer conductive layer.
  • the multi-wing structure 110 includes N shafts and M wings, wherein the N shafts extend along a first direction, and the M wings extend from the side walls of the N shafts to perpendicular to the first direction.
  • M is an integer greater than or equal to 2
  • N is a positive integer.
  • the M wings are formed by the first material 11, the area connecting the wings among the N shafts is formed by the first material 11, and the N shafts are not connected The area outside the area of the wing is formed by the second material 12 different from the first material 11.
  • the multi-wing structure 110 is shown in FIG. 17a.
  • the first material or the second material may be silicon (including single crystal silicon, polycrystalline silicon, amorphous silicon), silicon oxide, nitride or carbide, silicon-containing glass (including USG, BSG, PSG) , BPSG), aluminum (Al), copper (Cu), nickel (Ni) and other metals, or metal nitrides, carbides, carbon, organic polymers, or a combination or laminated structure of the above materials.
  • the second material can be selectively removed relative to the first material. Specifically, in the same corrosion or etching environment, the difference between the corrosion (or etching) rates of the first material and the second material is greater than 5 times.
  • the first material may be silicon
  • the second material may be silicon oxide.
  • the silicon oxide can be removed with a hydrofluoric acid solution or gas and the silicon can be retained.
  • the first material may be silicon oxide
  • the second material may be silicon.
  • KOH or NaOH or TMAH solution, or xenon difluoride (XeF 2 ) gas silicon can be removed while silicon oxide is retained.
  • the first material can be silicon doped with concentrated boron
  • the second material is silicon with a low or no doping concentration.
  • KOH or NaOH or TMAH solution can quickly remove low or no doping. Impurity silicon, while retaining dense boron-doped silicon.
  • the first wing of the M wings and the N shafts are formed of a third material 13, and the first wing of the M wings is The outer wings are formed of a fourth material 14 different from the third material 13.
  • the multi-wing structure 110 is shown in FIG. 17b.
  • the third material or the fourth material may be silicon (including single crystal silicon, polycrystalline silicon, and amorphous silicon), silicon oxide, nitride or carbide, silicon-containing glass (including USG, BSG, PSG) , BPSG), aluminum (Al), copper (Cu), nickel (Ni) and other metals, or metal nitrides, carbides, carbon, organic polymers, or a combination or laminated structure of the above materials.
  • the third material and the fourth material may also be the same.
  • the multi-wing structure 110 as shown in FIG. 17a can be prepared in the following manner:
  • a multilayer structure is prepared over the substrate, the multilayer structure includes at least two first material layers and at least one second material layer, the at least two first material layers and the at least one second material layer form the first material layer A structure adjacent to the second material layer, the first material is different from the second material, and the first material layer is in direct contact with the substrate;
  • Preparing at least one first trench on the multilayer structure the first trench extending from the upper surface of the multilayer structure into the multilayer structure along a first direction;
  • a part of the second material layer exposed in the first trench is removed to form the at least one multi-wing structure.
  • the first material layer 11, the second material layer 12, the first material layer 11, the second material layer 12, the first material layer 11, and the second material layer 12 are sequentially deposited on the substrate 160 using a CVD process. And the first material layer 11 to form the multilayer structure above the substrate 160, as shown in FIG. 17c.
  • the first material 11 is polysilicon heavily doped with boron
  • the second material 12 is BSG.
  • the thickness of the first material layer 11 and the second material layer 12 can be adjusted according to the capacitance, frequency characteristics, loss and other requirements of the capacitor.
  • a layer of photoresist is spin-coated on the upper surface of the multilayer structure as shown in FIG. 17c, a number of photoresist gaps are opened after exposure and development, and the dry etching process is used to remove the photoresist that is not covered by the photoresist.
  • the dry etching process is used to remove the photoresist that is not covered by the photoresist.
  • four first trenches 41 are formed, and the photoresist is removed, as shown in FIG. 17d.
  • the first groove 41 is used as a release hole, and a hydrofluoric acid solution or gaseous hydrofluoric acid is passed into the first groove 41.
  • a hydrofluoric acid solution or gaseous hydrofluoric acid is passed into the first groove 41.
  • part of the second material layer (BSG) exposed in the first trench 41 is removed to form three multi-wing structures 110, as shown in FIG. 17e.
  • the multi-wing structure 110 as shown in FIG. 17b can be prepared in the following manner:
  • a multilayer structure is prepared over the substrate, the multilayer structure includes at least one fourth material layer and at least one fifth material layer, and the at least one fourth material layer and the at least one fifth material layer form the fourth material layer and the first material layer.
  • Preparing at least one first trench on the multilayer structure the first trench extending from the upper surface of the multilayer structure into the multilayer structure along a first direction;
  • At least one second trench is prepared on the first structure, and the second trench extends from the upper surface of the first structure into the multilayer structure along the first direction to expose the at least one fifth material layer , And the second groove is located outside the first groove;
  • the fifth material layer exposed in the second trench is removed to form the at least one multi-wing structure.
  • the fifth material can be selectively removed. Specifically, in the same corrosion or etching environment, the difference in the corrosion (or etching) rate of the fourth material and the fifth material is greater than 5 times.
  • the fourth material layer 14, the fifth material layer 15, the fourth material layer 14, the fifth material layer 15, the fourth material layer 14, and the fifth material layer 15 are sequentially deposited on the substrate 160 using a CVD process.
  • the fourth material 14 is polysilicon heavily doped with boron
  • the fifth material 15 is BSG.
  • the thickness of the fourth material layer 14 and the fifth material layer 15 can be adjusted according to the capacitance, frequency characteristics, loss and other requirements of the capacitor.
  • a layer of photoresist is spin-coated on the upper surface of the multilayer structure as shown in FIG. 17f. After exposure and development, a number of photoresist gaps are opened, and the dry etching process is used to remove the photoresist that is not covered by the photoresist. In a multilayer structure, three first trenches 41 are formed, and the photoresist is removed, as shown in FIG. 17g.
  • a third material 13 is deposited on the upper surface of the multilayer structure and the inner surface of the first trench 41 to form the first structure, as shown in FIG. 17h.
  • a layer of photoresist is spin-coated on the upper surface of the first structure, and several photoresist gaps are opened after exposure and development, and the dry etching process is used to remove
  • the first structure covered by photoresist forms four second trenches 42 and the at least one fifth material layer is exposed in the second trenches 42; finally, the photoresist is removed, as shown in FIG. 17i.
  • the second groove 42 is used as a release hole, and a hydrofluoric acid solution or gaseous hydrofluoric acid is passed into the second groove 42 as The etchant removes all the fifth material layer (BSG) exposed in the second trench to form three multi-wing structures 110, as shown in FIG. 17j.
  • BSG fifth material layer
  • the deposition method of the multilayer structure can use spin coating, spray coating, thermal oxidation, epitaxy, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), epitaxial growth, etc. Craft.
  • PVD physical vapor deposition
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • epitaxial growth etc. Craft.
  • the stacked structure 120 can be formed on the substrate 160 by using various processes such as thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (Chemical Vapor Deposition, CVD) and so on.
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • the laminated structure 120 can be prepared in the following manner:
  • the laminated structure 120 includes two conductive layers and a dielectric layer.
  • the two conductive layers are denoted as conductive layer 121 and conductive layer 122, and one dielectric layer is denoted
  • a conductive layer 121, a dielectric layer 123, and a conductive layer 122 are sequentially deposited on the multi-wing structure 110 as shown in FIG. 17b using an ALD process, as shown in FIG. 17k.
  • the method 200 further includes:
  • a filling structure 150 is prepared, and the filling structure 150 covers the laminated structure 120 to fill the void formed by the laminated structure 120.
  • the filling structure 150 is complementary to the laminated structure 120 in shape.
  • a sixth material is filled above the stacked structure 120 by using an LPCVD process to form the filling structure 150, as shown in FIG. 17l.
  • the sixth material may be a conductive material or other materials.
  • the method 200 further includes:
  • the interconnect structure 170 is prepared so that the first external electrode 130 and/or the second external electrode 140 are electrically connected to the conductive layer in the multilayer conductive layer through the interconnect structure 170.
  • the interconnect structure 170 includes at least one insulating layer 171 and a conductive channel 172, and the conductive channel 172 penetrates the at least one insulating layer 171 to electrically connect the conductive layers in the multilayer conductive layer.
  • the deposition method of the at least one insulating layer 171 includes spin coating, spray coating, physical vapor deposition (PVD) or chemical vapor deposition (CVD).
  • the deposition method of the conductive channel 172 includes PVD, Metal-organic Chemical Vapor Deposition (MOCVD), and ALD.
  • photolithography processing is performed on the filling structure 150 to form at least one window structure 50 and expose the conductive layer 121 in the stacked structure 110, as shown in FIG. 17m;
  • An insulating material is deposited on the upper surface of the filling structure 150 and the at least one window structure 50 to form an insulating layer 171, and the insulating layer 171 is subjected to photolithography processing to form two via structures 51, respectively exposing the conductive layer 121 And a conductive layer 122, as shown in FIG. 17n; a conductive material is deposited in the via structure 51 to form a conductive channel 172, thereby forming the interconnect structure 170, as shown in FIG. 17o.
  • an electrode layer may be prepared above the laminated structure 120, and the electrode layer includes at least one first conductive region and at least one second conductive region that are separated from each other, and the first conductive region forms the The first external electrode 130, and the second conductive area forms the second external electrode 140.
  • the electrode layer deposition method includes PVD, electroplating, and electroless plating.
  • the electrode layer is deposited on the upper surface of the interconnect structure 170, and the electrode layer is subjected to photolithography processing to obtain at least one first conductive region and at least one first conductive region separated from each other. Two conductive regions, the first conductive region forms the first external electrode 130, and the second conductive region forms the second external electrode 140, thereby preparing the capacitor 100 as shown in FIG. 1.
  • the multi-wing structure 110 extends from the upper surface of the substrate 160 into the substrate 160 along the first direction.
  • the axis of the multi-wing structure 110 extends into the substrate 160 along the first direction, so that the capacitor as shown in FIG. 9 can be prepared.
  • the stacked structure 120 extends from the upper surface of the substrate 160 into the substrate 160 along the first direction.
  • the conductive layer 121, the conductive layer 122, and the dielectric layer 123 in the stacked structure 120 extend from the upper surface of the substrate 160 into the substrate 160 along the first direction, and the filling structure 150 also extends into the substrate 160.
  • the substrate 160 is a low-resistivity substrate
  • the above step 230 specifically includes: preparing the at least one first external electrode 130 under the substrate 160, and placing the at least one external electrode 130 on the multi-wing structure The at least one second external electrode 140 is prepared above.
  • an electrode material is deposited on the lower surface of the substrate 160 to form the first external electrode 130, and an electrode material is deposited on the upper surface of the filling structure 150 to form the second external electrode 140,
  • the capacitor shown in FIG. 11 or FIG. 12 is prepared.
  • the deposition methods of the first external electrode 130 and the second external electrode 140 include PVD, electroplating, and electroless plating.
  • the multilayer conductive layer includes: a first conductive layer, and the first conductive layer is complementary to the multi-wing structure 110 in shape.
  • the conductive layer and the dielectric layer in the stacked structure 120 excluding the first conductive layer are conformal to the multi-wing structure 110.
  • the multi-wing structure 110 is formed of a material with a resistivity less than a threshold, or the surface of the multi-wing structure 110 is formed with a heavily doped conductive layer with a resistivity less than the threshold.
  • the conductive layer closest to the multi-wing structure 110 in the laminated structure 120 is electrically connected to the first external electrode 130, and the multi-wing structure 110 is electrically connected to the second external electrode 140.
  • the conductive layer closest to the multi-wing structure 110 in the laminated structure 120 is electrically connected to the second external electrode 140, and the multi-wing structure 110 is electrically connected to the first external electrode 130.
  • the method also includes:
  • the isolation ring 180 is located outside the at least one multi-wing structure 110, and the isolation ring 180 is disposed in the laminated structure 120 and extends from the upper surface of the laminated structure 120 in the first direction Into or penetrate the laminated structure 120 to isolate the laminated structure 120 into a first area 10 and a second area 20.
  • the first external electrode 130 and/or the second external electrode 140 are only connected to the first area 10 of the laminated structure 120 is electrically connected.
  • a structure as shown in FIG. 17p can be prepared, and then photolithography is performed on the filling structure 150 to form a window structure 50 and expose the conductive layer 121 in the laminated structure 120, as shown in FIG. Shown at 17q.
  • an insulating material is deposited on the upper surface of the filling structure 150 and the at least one window structure 50 to form the insulating layer 171 and the isolation ring 180 in the interconnect structure 170, as shown in FIG. 17r.
  • the insulating layer 171 is subjected to photolithography processing to form two via structures 51 to respectively expose the conductive layer 121 and the conductive layer 122 in the laminated structure 120, as shown in FIG. 17s.
  • an electrode material is deposited on the upper surface of the insulating layer 171 and in the through hole structure 51, and photolithography is performed to prepare a capacitor as shown in FIG. 13.
  • the isolation ring 180 extends along the first direction into the laminated structure 120 located at the edge of the capacitor chip, thereby isolating the laminated structure 120 into a first area 10 and a second area 20.
  • the two external electrodes 140 are only electrically connected to the laminated structure 120 located in the first region 10.
  • the filling structure 150 is subjected to photolithography processing to form a window structure 50 and a ring-shaped trench 60, in which the conductive layer in the laminated structure 120 is exposed. 121.
  • the substrate 160 is exposed in the annular groove 60.
  • an insulating material is deposited on the upper surface of the filling structure 150, in the at least one window structure 50, and in the annular trench 60 to form the insulating layer 171 and the isolation ring 180 in the interconnect structure 170.
  • a photolithography process is performed on the insulating layer 171 to form two via structures 51 to respectively expose the conductive layer 121 and the conductive layer 122 in the laminated structure 120.
  • an electrode material is deposited on the upper surface of the insulating layer 171 and in the through hole structure 51, and photolithographic processing is performed to prepare a capacitor as shown in FIG. 14.
  • the capacitance value of the capacitor can be increased by preparing the multi-wing structure.
  • FIG. 1 a capacitor as shown in FIG. 1 is fabricated in the first embodiment.
  • FIG. 7 a capacitor as shown in FIG. 7 was fabricated.
  • the capacitor manufacturing method in the first and second embodiments can also be used to manufacture capacitors as shown in Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13, and Figure 14, but only in the electrode layer
  • the substrate, the multi-wing structure, the laminated structure and the setting of the isolation ring For the sake of brevity, it will not be repeated here.
  • Step 1 Choose a silicon wafer as the substrate. Using a CVD process, a stacked structure of structural material 1-sacrificial material-structural material 1-sacrificial material-structural material 1-sacrificial material is deposited on the substrate.
  • the structural material 1 is polysilicon heavily doped with boron, and the sacrificial material is BSG.
  • Step 2 Spin-coating a layer of photoresist on the surface of the laminated structure, open a number of gaps in the photoresist after exposure and development, and then use a dry etching process to remove the film structure not covered by the photoresist to form a trench 1. Finally, the photoresist is removed.
  • Step 3 Use the CVD process to fill the trench 1 with polysilicon heavily doped with boron as the structural material 2.
  • Step 4 Spin-coating a layer of photoresist on the surface of the structural material 2, open several photoresist gaps after exposure and development, and then use a dry etching process to remove the film structure not covered by the photoresist to form a trench 2. Finally, the photoresist is removed.
  • Step 5 Use trench 2 as a release hole, use hydrofluoric acid solution or gaseous hydrofluoric acid as an etchant to remove BSG, and obtain a multi-wing structure composed of polysilicon. It should be noted that since the projections of the trench 1 and the trench 2 on the surface of the substrate can be varied, there are also various possibilities for the three-dimensional shape of the wing-like structure.
  • Step 6 Using the ALD process, deposit a layer of TiN on the surface of the multi-wing structure as the first electrode plate of the capacitor; then deposit a layer of alumina as the dielectric layer; finally deposit a layer of TiN as the second electrode plate.
  • Step 7 Using Low Pressure Chemical Vapor Deposition (LPCVD) process to deposit silicon oxide as a filling material to fill and cover the entire multi-wing structure.
  • LPCVD Low Pressure Chemical Vapor Deposition
  • Step 8 Spin-coating a layer of photoresist on the surface of the filling material, open a photoresist gap after exposure and development, and then use a dry etching process to remove the second conductive layer and dielectric layer in the gap, exposing the first capacitor Conductive layer.
  • Step 9 Use the PECVD process to deposit a layer of USG as an insulating material.
  • Step 10 Spin-coating a layer of photoresist on the surface of the USG, open two photoresist gaps after exposure and development, and then use a hydrofluoric acid solution to remove the USG and silicon oxide in the gaps.
  • the two notches respectively expose the first conductive layer and the second conductive layer.
  • Step 11 Use the PVD process to deposit a layer of Al.
  • Two pads (electrodes) of Al are formed by photolithography. One of the pads is connected to the first conductive layer, and the other pad is connected to the second conductive layer.
  • Step 1 Choose a silicon wafer as the substrate. Using the CVD process, a stacked structure of structural material-sacrificial material-structural material-sacrificial material-structural material-sacrificial material is deposited on the substrate.
  • the structural material is amorphous silicon
  • the sacrificial material is TEOS.
  • Step 2 Spin-coating a layer of photoresist on the surface of the laminated structure, open a number of gaps in the photoresist after exposure and development, and then use a dry etching process to remove the film structure not covered by the photoresist to form a trench . Finally, the photoresist is removed.
  • Step 3 Use the groove as the release hole, use the hydrofluoric acid solution or gaseous hydrofluoric acid as the etchant of TEOS, by controlling the corrosion rate and time, retaining part of the TEOS, the multi-wing structure shown in the figure below is obtained.
  • Step 4 Using the ALD process, deposit a layer of TiN on the surface of the multi-wing structure as the first electrode plate of the capacitor; deposit a layer of alumina as the first dielectric layer; deposit a layer of TiN as the second electrode plate; deposit a layer of oxide Aluminum is used as the second dielectric layer; finally, the LPCVD process is used to fill the remaining voids with heavily doped polysilicon as the third electrode plate.
  • Step 5 Use a two-step photolithography process to open two notches to expose the first electrode plate and the second electrode plate respectively, as shown in the figure.
  • Step 6 Using a plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) process to deposit a layer of silicon oxide as an interlayer dielectric layer.
  • PECVD plasma enhanced chemical vapor deposition
  • Step 7 Using a photolithography process, open several through holes to expose the first electrode plate, the second electrode plate, and the third electrode plate respectively.
  • Step 8 Use the PVD process to deposit a layer of Ti as an adhesion layer and a layer of TiN as a barrier layer in the through hole; then use the MOCVD process to fill the through hole with tungsten to form a conductive channel. Finally, the surface flattening process is used to grind the excess metal off the surface.
  • Step 9 Deposit a layer of Ti, a layer of TiN, and a layer of Al by PVD process; finally, two pads are formed by photolithography. One of the pads is connected to the first electrode plate and the third electrode plate through a conductive channel, and the other pad is connected to the second electrode plate through a conductive channel.

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Abstract

本申请提供一种电容器及其制作方法，能够制备小体积、高容值密度的电容器。该电容器包括：至少一个多翼结构；叠层结构，该叠层结构包覆该至少一个多翼结构，该叠层结构包括至少一层电介质层和多层导电层，该至少一层电介质层和该多层导电层形成导电层与电介质层彼此相邻的结构；至少一个第一外接电极，该第一外接电极电连接至该多层导电层中的一部分导电层；至少一个第二外接电极，该第二外接电极电连接至该多层导电层中的另一部分导电层，该一部分导电层中的每个导电层在该叠层结构中相邻的导电层包括有该另一部分导电层中的至少一个导电层。

Description

电容器及其制作方法 技术领域
本申请涉及电容器领域，并且更具体地，涉及电容器及其制作方法。
背景技术
电容器在电路中可以起到旁路、滤波、去耦等作用，是保证电路正常运转的不可或缺的一部分。随着现代电子系统不断向多功能、高集成、低功耗、微型化发展，传统的多层陶瓷电容(Multi-layer Ceramic Capacitors，MLCC)已经难以满足应用端日益严苛的小体积、高容量的需求。如何制备小体积、高容量的电容器，成为一个亟待解决的技术问题。
发明内容
本申请提供一种电容器及其制作方法，能够制备小体积、高容值密度的电容器。
第一方面，提供了一种电容器，该电容器包括：
至少一个多翼结构；
叠层结构，所述叠层结构包覆所述至少一个多翼结构，所述叠层结构包括至少一层电介质层和多层导电层，所述至少一层电介质层和所述多层导电层形成导电层与电介质层彼此相邻的结构；
至少一个第一外接电极，所述第一外接电极电连接至所述多层导电层中的一部分导电层；
至少一个第二外接电极，所述第二外接电极电连接至所述多层导电层中的另一部分导电层，所述一部分导电层中的每个导电层在所述叠层结构中相邻的导电层包括有所述另一部分导电层中的至少一个导电层。
在一些可能的实现方式中，所述第一外接电极电连接至所述多层导电层中的所有奇数层导电层，以及所述第二外接电极电连接至所述多层导电层中的所有偶数层导电层。
在一些可能的实现方式中，所述多层导电层包括：第一导电层，所述第一导电层在外形上与所述多翼结构互补。
在一些可能的实现方式中，所述叠层结构中除所述第一导电层之外的导 电层和电介质层与所述多翼结构共形。
在一些可能的实现方式中，所述电容器还包括：填充结构，所述填充结构包覆所述叠层结构，以填充所述叠层结构形成的空隙。
在一些可能的实现方式中，所述填充结构在外形上与所述叠层结构互补。
在一些可能的实现方式中，所述多翼结构由电阻率小于阈值的材料形成，或者，所述多翼结构的表面形成有重掺杂的电阻率小于阈值的导电层。
在一些可能的实现方式中，
所述叠层结构中距离所述多翼结构最近的导电层电连接所述第一外接电极，以及所述多翼结构电连接所述第二外接电极；或者
所述叠层结构中距离所述多翼结构最近的导电层电连接所述第二外接电极，以及所述多翼结构电连接所述第一外接电极。
在一些可能的实现方式中，所述多翼结构包括N个轴和M个翼，其中，所述N个轴延着第一方向延伸，所述M个翼为从所述N个轴的侧壁向垂直于所述第一方向的方向延伸形成的凸起结构，M为大于或者等于2的整数，N为正整数。
在一些可能的实现方式中，所述M个翼由第一材料形成，所述N个轴中连接所述翼的区域由所述第一材料形成，以及所述N个轴中除连接所述翼的区域之外的区域由与所述第一材料不同的第二材料形成。
在一些可能的实现方式中，所述M个翼中的第一翼和所述N个轴由第三材料形成，所述M个翼中除所述第一翼之外的翼由与所述第三材料不同的第四材料形成。
在一些可能的实现方式中，所述第一翼位于所述M个翼中其余翼的上方。
在一些可能的实现方式中，所述电容器还包括：衬底，设置于所述多翼结构的下方。
在一些可能的实现方式中，所述电容器还包括：
隔离环，位于所述至少一个多翼结构的外侧，且所述隔离环设置于所述叠层结构中，并自所述叠层结构的上表面沿着第一方向延伸进入或者贯穿所述叠层结构，以将所述叠层结构隔离为第一区域和第二区域，所述第一外接电极和/或所述第二外接电极仅与位于所述第一区域的所述叠层结构电连接。
在一些可能的实现方式中，所述多翼结构自所述衬底的上表面沿着第一 方向延伸进入所述衬底。
在一些可能的实现方式中，所述叠层结构自所述衬底的上表面沿着第一方向延伸进入所述衬底。
在一些可能的实现方式中，所述衬底为电阻率小于阈值的衬底，所述第一外接电极设置于所述衬底的下方，所述第二外接电极设置于所述多翼结构的上方。
在一些可能的实现方式中，所述电容器还包括：电极层，设置于所述多翼结构的上方，所述电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，所述第一导电区域形成所述第一外接电极，所述第二导电区域形成所述第二外接电极。
在一些可能的实现方式中，所述第一外接电极和/或所述第二外接电极通过互联结构电连接至所述多层导电层中的导电层。
在一些可能的实现方式中，所述互联结构包括至少一个绝缘层和导电通道，所述导电通道贯穿所述至少一个绝缘层，以电连接所述多层导电层中的导电层。
在一些可能的实现方式中，所述导电层包括以下中的至少一层：
重掺杂多晶硅层，金属硅化物层，碳层，导电聚合物层，铝层，铜层，镍层，氮化钽层，氮化钛层，氮化铝钛层，氮化硅钽层，氮化碳钽层。
在一些可能的实现方式中，所述电介质层包括以下中的至少一层：
硅的氧化物层，硅的氮化物层，硅的氮氧化物层，金属的氧化物层，金属的氮化物层和金属的氮氧化物层。
第二方面，提供了一种电容器的制作方法，包括：
在衬底上方制备至少一个多翼结构；
在所述至少一个多翼结构表面制备叠层结构，所述叠层结构包覆所述多翼结构，所述叠层结构包括至少一层电介质层和多层导电层，所述至少一层电介质层和所述多层导电层形成导电层与电介质层彼此相邻的结构；
制备至少一个第一外接电极和至少一个第二外接电极，其中，所述第一外接电极电连接至所述多层导电层中的一部分导电层，所述第二外接电极电连接至所述多层导电层中的另一部分导电层，所述一部分导电层中的每个导电层在所述叠层结构中相邻的导电层包括有所述另一部分导电层中的至少一个导电层。
在一些可能的实现方式中，所述第一外接电极电连接至所述多层导电层中的所有奇数层导电层，以及所述第二外接电极电连接至所述多层导电层中的所有偶数层导电层。
在一些可能的实现方式中，所述在衬底上方制备至少一个多翼结构，包括：
在衬底上方制备多层结构，所述多层结构包括至少两个第一材料层和至少一个第二材料层，所述至少两个第一材料层和所述至少一个第二材料层形成第一材料层与第二材料层彼此相邻的结构，所述第一材料与所述第二材料不同，以及所述第一材料层与所述衬底直接接触；
在所述多层结构上制备至少一个第一沟槽，所述第一沟槽自所述多层结构的上表面沿着第一方向延伸进入所述多层结构；
去除所述第一沟槽中露出的部分第二材料层，以形成所述至少一个多翼结构。
在一些可能的实现方式中，所述在衬底上方制备至少一个多翼结构，包括：
在衬底上方制备多层结构，所述多层结构包括至少一个第四材料层和至少一个第五材料层，所述至少一个第四材料层和所述至少一个第五材料层形成第四材料层与第五材料层彼此相邻的结构，所述第四材料与所述第五材料不同，所述第四材料层与所述衬底直接接触；
在所述多层结构上制备至少一个第一沟槽，所述第一沟槽自所述多层结构的上表面沿着第一方向延伸进入所述多层结构；
在所述多层结构的上方和所述至少一个第一沟槽内沉积第三材料，以形成第一结构；
在所述第一结构上制备至少一个第二沟槽，所述第二沟槽自所述第一结构的上表面沿着所述第一方向延伸进入所述多层结构，以露出所述至少一层第五材料层，且所述第二沟槽位于所述第一沟槽的外侧；
去除所述第二沟槽中露出的第五材料层，以形成所述至少一个多翼结构。
在一些可能的实现方式中，所述多层导电层包括：第一导电层，所述第一导电层在外形上与所述多翼结构互补。
在一些可能的实现方式中，所述叠层结构中除所述第一导电层之外的导电层和电介质层与所述多翼结构共形。
在一些可能的实现方式中，所述方法还包括：
制备填充结构，所述填充结构包覆所述叠层结构，以填充所述叠层结构形成的空隙。
在一些可能的实现方式中，所述填充结构在外形上与所述叠层结构互补。
在一些可能的实现方式中，所述多翼结构由电阻率小于阈值的材料形成，或者，所述多翼结构的表面形成有重掺杂的电阻率小于阈值的导电层。
在一些可能的实现方式中，
所述叠层结构中距离所述多翼结构最近的导电层电连接所述第一外接电极，以及所述多翼结构电连接所述第二外接电极；或者
所述叠层结构中距离所述多翼结构最近的导电层电连接所述第二外接电极，以及所述多翼结构电连接所述第一外接电极。
在一些可能的实现方式中，所述多翼结构包括N个轴和M个翼，其中，所述N个轴延着所述第一方向延伸，所述M个翼为从所述N个轴的侧壁向垂直于所述第一方向的方向延伸形成的凸起结构，M为大于或者等于2的整数，N为正整数。
在一些可能的实现方式中，所述方法还包括：
制备隔离环，所述隔离环位于所述至少一个多翼结构的外侧，且所述隔离环设置于所述叠层结构中，并自所述叠层结构的上表面沿着第一方向延伸进入或者贯穿所述叠层结构，以将所述叠层结构隔离为第一区域和第二区域，所述第一外接电极和/或所述第二外接电极仅与位于所述第一区域的所述叠层结构电连接。
在一些可能的实现方式中，所述多翼结构自所述衬底的上表面沿着第一方向延伸进入所述衬底。
在一些可能的实现方式中，所述叠层结构自所述衬底的上表面沿着第一方向延伸进入所述衬底。
在一些可能的实现方式中，所述制备至少一个第一外接电极和至少一个第二外接电极，包括：
在所述叠层结构上方制备电极层，所述电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，所述第一导电区域形成所述第一外接电极，所述第二导电区域形成所述第二外接电极。
在一些可能的实现方式中，所述衬底为电阻率小于阈值的衬底；
所述制备至少一个第一外接电极和至少一个第二外接电极，包括：
在所述衬底下方制备所述至少一个第一外接电极，以及
在所述多翼结构的上方制备所述至少一个第二外接电极。
在一些可能的实现方式中，所述方法还包括：
制备互联结构，以使所述第一外接电极和/或所述第二外接电极通过所述互联结构电连接至所述多层导电层中的导电层。
在一些可能的实现方式中，所述互联结构包括至少一个绝缘层和导电通道，所述导电通道贯穿所述至少一个绝缘层，以电连接所述多层导电层中的导电层。
因此，在本申请实施例中，以多翼结构为骨架，在多翼结构上设置叠层结构，从而可以增加叠层结构的表面积，能够在较小器件尺寸的情况下得到较大的电容值，从而能够提高以叠层结构形成的电容器的容值密度。进一步地，在本申请实施例中，采用导电层与电介质层交替堆叠的叠层结构，能够更加充分的利用多翼结构作为骨架来增加叠层结构的表面积，从而能够进一步提高电容器的容值密度。
附图说明
图1是根据本申请实施例的一种电容器的示意性结构图。
图2是根据本申请实施例的一种多翼结构的材料示意图。
图3是根据本申请实施例的另一种多翼结构的材料示意图。
图4是根据本申请实施例的一种多翼结构的示意性结构图。
图5是根据本申请实施例的另一种多翼结构的示意性结构图。
图6是根据本申请实施例的再一种多翼结构的示意性结构图。
图7是根据本申请实施例的又一种电容器的示意性结构图。
图8是根据本申请实施例的再一种电容器的示意性结构图。
图9是根据本申请实施例的再一种电容器的示意性结构图。
图10是根据本申请实施例的再一种电容器的示意性结构图。
图11是根据本申请实施例的再一种电容器的示意性结构图。
图12是根据本申请实施例的再一种电容器的示意性结构图。
图13是根据本申请实施例的再一种电容器的示意性结构图。
图14是根据本申请实施例的再一种电容器的示意性结构图。
图15是根据本申请实施例的隔离环的示意性俯视图。
图16是根据本申请实施例的一种电容器的制作方法的示意性流程图。
图17a至图17s是本申请实施例的一种电容器的制作方法的示意图。
具体实施方式
下面将结合附图，对本申请实施例中的技术方案进行描述。
应理解，本申请实施例的电容器在电路中可以起到旁路、滤波、去耦等作用。
本申请实施例所述的电容器可以是3D硅电容器，3D硅电容器是一种基于半导体晶圆加工技术的新型电容器。与传统的MLCC(多层陶瓷电容)相比，3D硅电容器具有小尺寸、高精度、高稳定性、长寿命等优点。其基本的加工流程需要先在晶圆或衬底上加工出高深宽比的深孔(Via)、沟槽(Trench)、柱状(Pillar)、墙状(Wall)等3D结构，接着在3D结构表面沉积绝缘薄膜和低电阻率导电材料依次制作电容的下电极、电介质层和上电极。
现阶段的3D硅电容器，借鉴DRAM制造中的一些多层嵌套的概念，在3D结构表面交替沉积导体和绝缘体材料，以此制作多个电容纵向堆叠的结构，再在硅衬底正面用不同的连接方式将所有电容并联，最后形成一个大容值的电容器。然而，目前晶圆级3D电容器的容值密度仍然有限。
在此背景下，本申请提出了一种新型的电容器的结构和制作方法，可以提高电容器的容值密度。
以下，结合图1至图14，详细介绍本申请实施例的电容器。
应理解，图1至图14中的电容器仅仅只是示例，电容器所包括的多翼结构的数量并不局限于图1至图14中的电容器所示，可以根据实际需要确定。同时多翼结构所包括的翼的数量以及轴的数量仅仅只是示例，多翼结构所包括的翼的数量以及轴的数量并不局限于图1至图14中的电容器所示，可以根据实际需要灵活设置。
需要说明的是，为便于理解，在以下示出的实施例中，对于不同实施例中示出的结构中，相同的结构采用相同的附图标记，并且为了简洁，省略对相同结构的详细说明。
图1是本申请一个实施例的电容器100的一种可能的结构图。如图1所示，该电容器100包括至少一个多翼结构110、叠层结构120、至少一个第 一外接电极130、至少一个第二外接电极140。
具体地，如图1所示，在该电容器100中，该叠层结构120包覆该多翼结构110，该叠层结构120包括至少一层电介质层和多层导电层，该至少一层电介质层和该多层导电层形成导电层与电介质层彼此相邻的结构；该第一外接电极130电连接至该多层导电层中的一部分导电层；该第二外接电极140电连接至该多层导电层中的另一部分导电层，该一部分导电层中的每个导电层在该叠层结构中相邻的导电层包括有该另一部分导电层中的至少一个导电层。
即在本申请实施例中，该多层导电层中相邻的两个导电层通过电介质层电隔离。导电层和电介质层的具体层数可以根据实际需要灵活配置，只需满足该多层导电层中相邻的两个导电层之间电隔离。
需要说明的是，在本申请实施例中，以多翼结构为骨架，在多翼结构上设置叠层结构，从而可以增加叠层结构的表面积，能够在较小器件尺寸的情况下得到较大的电容值，从而能够提高以叠层结构形成的电容器的容值密度。进一步地，在本申请实施例中，采用导电层与电介质层交替堆叠的叠层结构，能够更加充分的利用多翼结构作为骨架来增加叠层结构的表面积，从而能够进一步提高电容器的容值密度。
在本申请实施例中，多翼结构110为骨架，即多翼结构110的材料选择可以更为灵活，从而简化多翼结构110的制备流程。例如，在该多翼结构110的材料为导电材料的情况下，该多翼结构110也可以作为该电容器100的一个电极板。
可选地，在本申请实施例中，该多翼结构110由电阻率小于阈值的材料形成，或者，该多翼结构110的表面形成有重掺杂的电阻率小于阈值的导电层。
需要说明的是，该多翼结构110由电阻率小于阈值的材料形成，可以保证该多翼结构110导电，即可以作为电容器100的一个电极板。
例如，该叠层结构120中距离该多翼结构110最近的导电层电连接该第一外接电极130，以及该多翼结构110电连接该第二外接电极140。
又例如，该叠层结构120中距离该多翼结构110最近的导电层电连接该第二外接电极140，以及该多翼结构110电连接该第一外接电极130。
可选地，该第外接电极130或者该第二外接电极140可以电连接该至少 一个多翼结构110中的部分或者全部多翼结构110。
可选地，不同的多翼结构110之间可以通过低电阻率衬底电连接，不同的多翼结构110之间也可以通过导电片或者金属互联结构电连接。
可选地，该叠层结构120与该多翼结构110共形。例如，如图1所示，该叠层结构120可以与该多翼结构110具有相同或者大致相同的外形轮廓，以使该叠层结构120可以包覆该多翼结构110上与该叠层结构120接触的区域，从而，该叠层结构120可以基于该多翼结构110得到更大的表面积，进而提高电容器的容值密度。
应理解，本申请实施例中外接电极也可以称之为焊盘或者外接焊盘。
可选地，该第一外接电极130和该第二外接电极140的材料可以是金属，例如铜、铝等。该第一外接电极130和该第二外接电极140还可以包含低电阻率的Ti，TiN，Ta，TaN层作为黏附层和/或阻挡层；还可能包含位于外接电极表面的一些金属层，例如Ni、Pd(钯)、Au、Sn(锡)、Ag，用于后续打线或焊接工艺。
可选地，本申请实施例中，该导电层包括以下中的至少一层：
重掺杂多晶硅层，金属硅化物层，碳层，导电聚合物层，铝层，铜层，镍层，氮化钽层，氮化钛层，氮化铝钛层，氮化硅钽层，氮化碳钽层。
也就是说，该叠层结构120中的导电层的材料可以是重掺杂多晶硅，金属硅化物(silicide)，碳，导电的聚合物，Al、Cu、Ni等金属，氮化钽(TaN)、氮化钛(TiN)、氮化铝钛(TiAlN)、氮化硅钽(TaSiN)、氮化碳钽(TaCN)等低电阻率化合物，或者上述材料的组合、叠层结构。具体导电材料和层厚可根据电容器的容值、频率特性、损耗等需求来调整。当然，该叠层结构120中的导电层还可以包括一些其他的导电材料，本申请实施例对此不作限定。
可选地，本申请实施例中，该电介质层包括以下中的至少一层：
硅的氧化物层，硅的氮化物层，硅的氮氧化物层，金属的氧化物层，金属的氮化物层和金属的氮氧化物层。
也就是说，该叠层结构120中的电介质层的材料可以是硅的氧化物，硅的氮化物，硅的氮氧化物，金属的氧化物，金属的氮化物，金属的氮氧化物。例如SiO 2，SiN，SiON，或者高介电常数(high-k)材料，包括氧化铝，氧化铪，氧化锆，氧化钛，Y 2O 3，La 2O 3，HfSiO 4，LaAlO 3，SrTiO 3，LaLuO 3等。该叠层结构120中的电介质层可以是一层或包含多个叠层，可以是一种 材料或多种材料的组合、混合。具体绝缘材料和层厚可根据电容器的容值、频率特性、损耗等需求来调整。当然，该叠层结构120中的电介质层还可以包括一些其他的绝缘材料，本申请实施例对此不作限定。
可选地，在本申请实施例中，该多翼结构110包括N个轴和M个翼，其中，该N个轴延着第一方向延伸，该M个翼为从该N个轴的侧壁向垂直于该第一方向的方向延伸形成的凸起结构，M为大于或者等于2的整数，N为正整数。
可选地，如图2所示，该M个翼由第一材料11形成，该N个轴中连接该翼的区域由该第一材料11形成，以及该N个轴中除连接该翼的区域之外的区域由与该第一材料11不同的第二材料12形成。
可选地，该第一材料11或该第二材料12可以是硅(包括单晶硅、多晶硅、不定形硅)，硅的氧化物、氮化物或碳化物、含硅玻璃(包括未掺杂硅玻璃(Undoped Silicon Glass，USG)、硼硅玻璃(boro-silicate glass，BSG)、磷硅玻璃(phospho-silicateglass，PSG)、硼磷硅玻璃(boro-phospho-silicateglass，BPSG))，铝(Al)、铜(Cu)、镍(Ni)等金属，或金属氮化物、碳化物，碳，有机聚合物，或者上述材料的组合或叠层结构。
需要理解的是，相对于该第一材料11，该第二材料12可以被选择性去除。具体地，在同一腐蚀或刻蚀环境，该第一材料11和该第二材料12的腐蚀(或刻蚀)速率的差异大于5倍。
例如，第一材料11可以是硅，第二材料12可以是氧化硅，用氢氟酸溶液或气体可以去除氧化硅并保留硅。
再例如，第一材料11可以是氧化硅，第二材料12可以是硅，用KOH或NaOH或四甲基氢氧化铵(Tetramethylammonium Hydroxide，TMAH)溶液，或二氟化氙(XeF 2)气体，可以去除硅而保留氧化硅。
再例如，第一材料11可以是浓硼掺杂的硅，第二材料12是掺杂浓度低或没有掺杂的硅，用KOH或NaOH或TMAH溶液，可以较为快速地去除掺杂浓度低或没有掺杂的硅，而保留浓硼掺杂的硅。
可选地，如图3所示，该M个翼中的第一翼和该N个轴由第三材料13形成，该M个翼中除该第一翼之外的翼由与该第三材料13不同的第四材料14形成。
可选地，该第一翼位于该M个翼中其余翼的上方。
可选地，该第三材料13或该第四材料14可以是硅(包括单晶硅、多晶硅、不定形硅)，硅的氧化物、氮化物或碳化物、含硅玻璃(包括USG、BSG、PSG、BPSG)，铝(Al)、铜(Cu)、镍(Ni)等金属，或金属氮化物、碳化物，碳，有机聚合物，或者上述材料的组合或叠层结构。
可选地，该第三材料13与该第四材料14也可以相同。
在本申请实施例中，M和N的具体数值可以根据实际需要灵活配置。
假设M＝4，N＝1，如图1所示，多翼结构110可以包括4个翼和1个轴。需要说明的是，M＝4，N＝1仅仅只是示例，在本申请实施例中，M可以是大于或者等于2的整数，例如5，10等，N也可以是大于或者等于2的整数，例如，N＝3，4等，本申请实施例对比不作限定。
可选地，在本申请实施例中，该多翼结构110可以是多种结构。例如，在如图4所示的多翼结构110中，M＝4，N＝1。又例如，在如图5和图6所示的多翼结构110中，M＝4，N＝3。
可选地，在本申请实施例中，如图1所示，该电容器100还包括：填充结构150，该填充结构150包覆该叠层结构120，以填充该叠层结构120形成的空腔或者空隙。
可选地，该填充结构150在外形上与该叠层结构120互补。例如，如图1所示，该填充结构150可以与该叠层结构120在结构上互补，两者组合可以形成一个内部无空隙或者空腔的结构，提升电容器的结构完整性和机械稳定性。
需要说明的是，该填充结构150的材料可以是导电材料，也可以是一些其他的材料。
可选地，在该填充结构150的材料为导电材料的情况下，该填充结构150也可以作为该电容器100的一个电极板。
例如，如图7所示，假设该填充结构150导电，该叠层结构120包括2层导电层和2层电介质层，如图7中示出的导电层121和导电层122，以及电介质层123和电介质层124。具体地，如图7所示，导电层121与多翼结构110直接接触，即导电层121设置于多翼结构110的表面，并且包覆多翼结构110；导电层122设置于导电层121的上方；电介质层123设置于导电层121与导电层122之间，以将导电层121与导电层122电隔离；电介质层124设置于导电层122与填充结构150之间，以将导电层122与填充结构150 电隔离。该第一外接电极130电连接导电层121和填充结构150，该第二外接电极140电连接导电层122。
需要说明的是，在该叠层结构中，该至少一层电介质层的顺序可以是：在多翼结构上，与多翼结构的距离从小到大或者从大到小的顺序。同理，该多层导电层的顺序也可以是：在多翼结构上，与多翼结构的距离从小到大或者从大到小的顺序。为了便于描述，在本申请实施例中该至少一层电介质层和该多层导电层的顺序以在多翼结构上与多翼结构的距离从小到大的顺序为例进行说明。
需要说明的是，在本申请实施例中，由于该第一外接电极130电连接至该多层导电层中的一部分导电层；该第二外接电极140电连接至该多层导电层中的另一部分导电层，该一部分导电层中的每个导电层在该叠层结构120中相邻的导电层包括有该另一部分导电层中的至少一个导电层。因此，针对不同的第一外接电极130和第二外接电极140，该叠层结构120可以形成具有不同容值的电容器。
作为一个示例，假设该电容器100包括2个第一外接电极和2个第二外接电极，2个第一外接电极分别记为第一外接电极A和第一外接电极B，2个第二外接电极分别记为第二外接电极C和第二外接电极D，以及该叠层结构包括5层导电层和4层电介质层，5层导电层依次分别记为导电层1、导电层2、导电层3、导电层4和导电层5，4层电介质层依次分别记为电介质层1、电介质层2、电介质层3和电介质层4。
若该第一外接电极A电连接该导电层1和该导电层3，该第一外接电极B电连接该导电层1、该导电层3和该导电层5，该第二外接电极C电连接该导电层2和该导电层4，该第二外接电极D也电连接该导电层2和该导电层4，则针对该第一外接电极A与该第二外接电极C对应的电容器，该导电层1与该导电层2形成电容器1，容值记为C1，该导电层2与该导电层3形成电容器2，容值记为C2，该导电层3与该导电层4形成电容器3，容值记为C3，电容器1、电容器2和电容器3并联，其等效电容i的容值记为Ci，则Ci＝C1+C2+C3；则针对该第一外接电极B与该第二外接电极D对应的电容器，该导电层1与该导电层2形成电容器1，容值记为C1，该导电层2与该导电层3形成电容器2，容值记为C2，该导电层3与该导电层4形成电容器3，容值记为C3，该导电层4与该导电层5形成电容器4，容值记为C4， 电容器1、电容器2、电容器3和电容器4并联，其等效电容j的容值记为Cj，则Cj＝C1+C2+C3+C4。当然，针对该第一外接电极A与该第二外接电极D对应的电容器也可以形成类似的串并联结构，针对该第一外接电极B与该第二外接电极C对应的电容器也可以形成类似的串并联结构，在此不再赘述。因此，该叠层结构120可以形成具有不同容值的电容器。
若该第一外接电极A电连接该导电层1和该导电层5，该第一外接电极B电连接该导电层3和该导电层5，该第二外接电极C电连接该导电层2和该导电层4，该第二外接电极D也电连接该导电层4，则针对该第一外接电极A与该第二外接电极C对应的电容器，该导电层1与该导电层2形成电容器1，容值记为C1，该导电层2与该导电层4形成电容器2，容值记为C2，电容器1和电容器2并联，其等效电容i的容值记为Ci，则Ci＝C1+C2；则针对该第一外接电极B与该第二外接电极D对应的电容器，该导电层3与该导电层4形成电容器3，容值记为C3，该导电层4与该导电层5形成电容器4，容值记为C4，电容器3和电容器4并联，其等效电容j的容值记为Cj，则Cj＝C3+C4。因此，该叠层结构120可以形成具有不同容值的电容器。
可选地，该至少一个第一外接电极130中每个第一外接电极130电连接至该多层导电层中的所有奇数层导电层；该至少一个第二外接电极140中每个第二外接电极140电连接至该多层导电层中的所有偶数层导电层。从而可以充分发挥叠层结构增加电容器的容值密度的效果。
作为一个示例，假设该电容器100包括2个第一外接电极和2个第二外接电极，2个第一外接电极分别记为第一外接电极A和第一外接电极B，2个第二外接电极分别记为第二外接电极C和第二外接电极D，以及该叠层结构包括5层导电层和4层电介质层，5层导电层依次分别记为导电层1、导电层2、导电层3、导电层4和导电层5，4层电介质层依次分别记为电介质层1、电介质层2、电介质层3和电介质层4。
若该第一外接电极A电连接该导电层1、该导电层3和该导电层5，该第一外接电极B电连接该导电层1、该导电层3和该导电层5，该第二外接电极C电连接该导电层2和该导电层4，该第二外接电极D也电连接该导电层2和该导电层4，则针对该第一外接电极A与该第二外接电极C对应的电容器，该导电层1与该导电层2形成电容器1，容值记为C1，该导电层2与该导电层3形成电容器2，容值记为C2，该导电层3与该导电层4形成电容 器3，容值记为C3，该导电层4与该导电层5形成电容器4，容值记为C4，电容器1、电容器2、电容器3和电容器4并联，其等效电容i的容值记为Ci，则Ci＝C1+C2+C3+C4；则针对该第一外接电极B与该第二外接电极D对应的电容器，该导电层1与该导电层2形成电容器1，容值记为C1，该导电层2与该导电层3形成电容器2，容值记为C2，该导电层3与该导电层4形成电容器3，容值记为C3，该导电层4与该导电层5形成电容器4，容值记为C4，电容器1、电容器2、电容器3和电容器4并联，其等效电容j的容值记为Cj，则Cj＝C1+C2+C3+C4。
可选地，本申请实施例中，该电容器100还包括：衬底160，设置于该多翼结构120的下方。
在本申请实施例中，该第一方向可以是垂直于该衬底160的方向。例如，如图1、图2、图3和图7所示。
可选地，在本申请实施例中，该衬底160可以为硅晶圆，包括单晶硅、多晶硅、不定形硅。该衬底160也可以是别的半导体衬底，包括绝缘体上半导体(Silicon-On-Insulator，SOI)晶圆，碳化硅(SiC)、氮化镓(GaN)、砷化镓(GaAs)等III-V族元素的化合物半导体晶圆；或者是玻璃衬底；或者是有机聚合物衬底；或者表面包含外延层、氧化层、掺杂层的衬底。
需要注意的是，在本申请实施例中，该衬底160的厚度也可以根据实际需要灵活设置，例如，在该衬底160的厚度因太厚而不能满足需求时，可以对该衬底160进行减薄处理。甚至可以将该衬底160完全去除。
需要说明的是，上述图1、图2、图3和图7中是沿着衬底纵向的截面。
可选地，在本申请实施例中，该第一外接电极130和/或该第二外接电极140通过互联结构170电连接至该多层导电层中的导电层。
可选地，该互联结构170包括至少一个绝缘层171和导电通道172，该导电通道172贯穿该至少一个绝缘层171，以电连接该多层导电层中的导电层。具体如图1所示，该互联结构170设置于该填充结构150的上方。
需要说明的是，该至少一个绝缘层171也可以称之为金属间介质层(IMD)或者层间介质层(ILD)。
可选地，该至少一个绝缘层171的材料可以是有机的聚合物材料，包括聚酰亚胺(Polyimide)，帕里纶(Parylene)，苯并环丁烯(BCB)等；也可以是一些无机材料，包括旋转涂布玻璃(Spin on glass，SOG)，未掺杂硅玻 璃(Undoped Silicon Glass，USG)，硼硅玻璃(boro-silicate glass，BSG)，磷硅玻璃(phospho-silicateglass，PSG)，硼磷硅玻璃(boro-phospho-silicateglass，BPSG)，由四乙氧基硅烷(Tetraethyl Orthosilicate，TEOS)合成的硅氧化物，硅的氧化物、氮化物，陶瓷；还可以是上述材料的组合或者叠层。
可选地，该导电通道172的材料可以由低电阻率导电材料构成，例如重掺杂多晶硅，钨，Ti，TiN，Ta，TaN。
应理解，该导电通道172的形状和数量可以根据该电容器100的制作工艺具体确定，本申请实施例对此不作限定。
可选地，在本申请实施例中，假设该叠层结构120包括2层导电层和1层电介质层，如图1中示出的导电层121和导电层122，以及电介质层123。具体地，如图1所示，导电层121与多翼结构110直接接触，即导电层121设置于多翼结构110的表面，并且包覆多翼结构110；导电层122设置于导电层121的上方；电介质层123设置于导电层121与导电层122之间，以将导电层121与导电层122电隔离。
可选地，在一些实施例中，该至少一个第一外接电极130和该至少一个第二外接电极140设置于该多翼结构110的上方。可选地，该电容器100还包括：电极层，设置于该多翼结构110的上方，且该电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，该第一导电区域形成该第一外接电极130，该第二导电区域形成该第二外接电极140，具体如图1所示。也即，该至少一个第一外接电极130和该至少一个第二外接电极140可以通过一次刻蚀形成，减少了刻蚀步骤。
具体地，如图1和图7所示，该电极层设置于该互联结构170的上方，该第一外接电极130通过该导电通道172电连接至该导电层121，该第二外接电极140通过该导电通道172电连接至该导电层122。
可选地，在一些实施例中，该多层导电层包括：第一导电层，该第一导电层在外形上与该多翼结构110互补。
即可以由该多层导电层中距离多翼结构110最远的一层填充该叠层结构120内形成的空腔或者空隙，以提升电容器的结构完整性和机械稳定性。
需要说明的是，该第一导电层的设置可以填充该叠层结构120内形成的空腔或者空隙，以及该第一导电层的设置可以提升电容器的结构完整性和机械稳定性。
可选地，该叠层结构120中除该第一导电层125之外的导电层和电介质层与该多翼结构120共形。
具体地，如图8所示，该叠层结构包括导电层121和导电层122，以及电介质层123，其中，导电层122为该第一导电层。导电层121与多翼结构110直接接触，即导电层121设置于多翼结构110的表面，并且包覆多翼结构110；电介质层123设置于导电层121的上表面；导电层122填充该叠层结构120内导电层121和电介质层123形成的空腔或者空隙，并且电介质层123设置于导电层121与导电层122之间，以将导电层121与导电层122电隔离。该第一外接电极130电连接导电层121，该第二外接电极140电连接导电层122。
应理解，除了叠层结构120和填充结构150的设置不同外，图8和图1的其他设置相同，为了简洁，不再赘述。
可选地，在一些实施例中，该多翼结构110自该衬底160的上表面沿着第一方向延伸进入该衬底160。
例如，如图9所示，该多翼结构110中的该N个轴自该衬底160的上表面沿着该第一方向延伸进入该衬底160。从而，可以增加多翼结构110的机械稳定性。
应理解，除了该多翼结构110的设置不同外，图9和图1的其他设置相同，为了简洁，不再赘述。
可选地，在一些实施例中，该叠层结构120自该衬底160的上表面沿着第一方向延伸进入该衬底160。
例如，如图10所示，该叠层结构120自该衬底160的上表面沿着第一方向延伸进入该衬底160。可以增加多翼结构110的机械稳定性。进一步地，也可以增加该叠层结构120中各个导电层的表面积，从而，增大容值密度。
需要说明的是，在该叠层结构120延伸进入该衬底160的情况下，该填充结构150也延伸进入该衬底160。
应理解，除了该叠层结构120的设置不同外，图10和图1的其他设置相同，为了简洁，不再赘述。
可选地，在本申请实施例中，在该衬底160为低电阻率衬底的情况下，该第一外接电极130设置于该衬底160的下方，该第二外接电极140设置于该多翼结构110的上方。
例如，如图11所示，该第一外接电极130设置于该衬底160的下方，该第二外接电极140设置于该多翼结构110的上方，该第一外接电极130通过该衬底160电连接导电层121，该第二外接电极140通过互联结构170电连接至导电层122。
又例如，如图12所示，该第一外接电极130设置于该衬底160的下方，该第二外接电极140设置于该多翼结构110的上方，该第一外接电极130通过该衬底160电连接导电层121，该第二外接电极140通过导电的填充结构150电连接至导电层122。
需要说明的是，在图1、图7、图8、图9和图10所示的电容器100中，若该衬底160为低电阻率衬底的情况下，也可以如图11或者图12一样，将该第一外接电极130设置于该衬底160的下方，以及将该第二外接电极140设置于该多翼结构110的上方，在此不再赘述。
可选地，在本申请实施例中，该电容器100还包括：
隔离环180，位于该至少一个多翼结构110的外侧，且该隔离环180设置于该叠层结构120中，并自该叠层结构120的上表面沿着第一方向延伸进入或者贯穿该叠层结构120，以将该叠层结构120隔离为第一区域10和第二区域20，且该第一外接电极130和/或该第二外接电极140仅与位于该第一区域10的该叠层结构120电连接。
可选地，该隔离环180的材料可以是有机的聚合物材料，包括聚酰亚胺(Polyimide)，帕里纶(Parylene)，苯并环丁烯(BCB)等；也可以是一些无机材料，包括SOG，USG，BSG，PSG，BPSG，由TEOS合成的硅氧化物，硅的氧化物、氮化物，陶瓷；还可以是上述材料的组合或者叠层。
例如，如图13所示，该隔离环180沿着该第一方向延伸进入位于电容芯片边缘的叠层结构120内，从而，将该叠层结构120隔离为第一区域10和第二区域20，该第二外接电极140仅与位于该第一区域10的该叠层结构120电连接。
又例如，如图14所示，该隔离环180沿着该第一方向延伸贯穿该叠层结构120，从而，将该叠层结构120隔离为第一区域10和第二区域20，该第一外接电极130仅与位于该第一区域10的该叠层结构120电连接，该第二外接电极140仅与位于该第一区域10的该叠层结构120电连接。
具体地，该隔离环180的俯视图可以如图15所示。
需要说明的是，在电容器100或者电容芯片的边缘位置，由于空气的绝缘能力不足，叠层结构120与衬底160之间极易发生空气击穿，从而导致电容器的性能下降。隔离环180的设置，可以使得位于第二区域20的叠层结构120不构成电容器的电极板，从而，避免了电容器的边缘位置处叠层结构120与衬底160之间发生空气击穿的问题。
因此，在本申请实施例中，以多翼结构为骨架，在多翼结构上设置叠层结构，从而可以增加叠层结构的表面积，能够在较小器件尺寸的情况下得到较大的电容值，从而能够提高以叠层结构形成的电容器的容值密度。进一步地，在本申请实施例中，采用导电层与电介质层交替堆叠的叠层结构，能够更加充分的利用多翼结构作为骨架来增加叠层结构的表面积，从而能够进一步提高电容器的容值密度。
以上描述了本申请实施例的电容器，下面描述本申请实施例的制备电容器的方法。本申请实施例的制备电容器的方法可以制备前述本申请实施例的电容器，下述实施例和前述实施例中的相关描述可以相互参考。
以下，结合图16，详细介绍本申请实施例的电容器的制作方法。
应理解，图16是本申请实施例的电容器的制作方法的示意性流程图，但这些步骤或操作仅是示例，本申请实施例还可以执行其他操作或者图16中的各个操作的变形。
图16示出了根据本申请实施例的电容器的制作方法200的示意性流程图。如图16所示，该电容器的制作方法200包括：
步骤210，在衬底上方制备至少一个多翼结构；
步骤220，在该至少一个多翼结构表面制备叠层结构，该叠层结构包覆该多翼结构，该叠层结构包括至少一层电介质层和多层导电层，该至少一层电介质层和该多层导电层形成导电层与电介质层彼此相邻的结构；
步骤230，制备至少一个第一外接电极和至少一个第二外接电极，其中，该第一外接电极电连接至该多层导电层中的一部分导电层，该第二外接电极电连接至该多层导电层中的另一部分导电层，该一部分导电层中的每个导电层在该叠层结构中相邻的导电层包括有该另一部分导电层中的至少一个导电层。
可选地，该第一外接电极130电连接至该多层导电层中的所有奇数层导电层，以及该第二外接电极140电连接至该多层导电层中的所有偶数层导电 层。
可选地，该多翼结构110包括N个轴和M个翼，其中，该N个轴延着第一方向延伸，该M个翼为从该N个轴的侧壁向垂直于该第一方向的方向延伸形成的凸起结构，M为大于或者等于2的整数，N为正整数。
可选地，在该多翼结构110中，该M个翼由该第一材料11形成，该N个轴中连接该翼的区域由该第一材料11形成，以及该N个轴中除连接该翼的区域之外的区域由与该第一材料11不同的该第二材料12形成。例如，在M＝4，N＝1，该多翼结构110如图17a所示。
可选地，该第一材料或该第二材料可以是硅(包括单晶硅、多晶硅、不定形硅)，硅的氧化物、氮化物或碳化物、含硅玻璃(包括USG、BSG、PSG、BPSG)，铝(Al)、铜(Cu)、镍(Ni)等金属，或金属氮化物、碳化物，碳，有机聚合物，或者上述材料的组合或叠层结构。
需要理解的是，相对于该第一材料，该第二材料可以被选择性去除。具体地，在同一腐蚀或刻蚀环境，该第一材料和该第二材料的腐蚀(或刻蚀)速率的差异大于5倍。
例如，第一材料可以是硅，第二材料可以是氧化硅，用氢氟酸溶液或气体可以去除氧化硅并保留硅。
再例如，第一材料可以是氧化硅，第二材料可以是硅，用KOH或NaOH或TMAH溶液，或二氟化氙(XeF 2)气体，可以去除硅而保留氧化硅。
再例如，第一材料可以是浓硼掺杂的硅，第二材料是掺杂浓度低或没有掺杂的硅，用KOH或NaOH或TMAH溶液，可以较为快速地去除掺杂浓度低或没有掺杂的硅，而保留浓硼掺杂的硅。
可选地，如图17b所示，在该多翼结构110中，该M个翼中的第一翼和该N个轴由第三材料13形成，该M个翼中除该第一翼之外的翼由与该第三材料13不同的第四材料14形成。例如，在M＝4，N＝1，该多翼结构110如图17b所示。
可选地，该第三材料或该第四材料可以是硅(包括单晶硅、多晶硅、不定形硅)，硅的氧化物、氮化物或碳化物、含硅玻璃(包括USG、BSG、PSG、BPSG)，铝(Al)、铜(Cu)、镍(Ni)等金属，或金属氮化物、碳化物，碳，有机聚合物，或者上述材料的组合或叠层结构。
可选地，该第三材料与该第四材料也可以相同。
可选地，可以通过如下方式制备如图17a所示的多翼结构110：
在衬底上方制备多层结构，该多层结构包括至少两个第一材料层和至少一个第二材料层，该至少两个第一材料层和该至少一个第二材料层形成第一材料层与第二材料层彼此相邻的结构，该第一材料与该第二材料不同，以及该第一材料层与该衬底直接接触；
在该多层结构上制备至少一个第一沟槽，该第一沟槽自该多层结构的上表面沿着第一方向延伸进入该多层结构；
去除该第一沟槽中露出的部分第二材料层，以形成该至少一个多翼结构。
具体地，首先，利用CVD工艺在衬底160上依次沉积第一材料层11、第二材料层12、第一材料层11、第二材料层12、第一材料层11、第二材料层12和第一材料层11，以在该衬底160的上方形成该多层结构，如图17c所示。例如，该第一材料11为重掺硼的多晶硅，该第二材料12为BSG。具体第一材料层11和第二材料层12的厚度可根据电容器的容值、频率特性、损耗等需求来调整。
接着，在如图17c所示的多层结构的上表面旋涂一层光刻胶，曝光、显影之后打开若干光刻胶的缺口，利用干法刻蚀工艺去除未被光刻胶覆盖的该多层结构，形成4个第一沟槽41，去除光刻胶，如图17d所示。
最后，在如图17d所示的结构中，假设该第二材料为BSG，以该第一沟槽41为释放孔，在该第一沟槽41内通入氢氟酸溶液或气态氢氟酸作为腐蚀剂，去除该第一沟槽41中露出的部分第二材料层(BSG)，以形成3个多翼结构110，如图17e所示。
可选地，可以通过如下方式制备如图17b所示的多翼结构110：
在衬底上方制备多层结构，该多层结构包括至少一个第四材料层和至少一个第五材料层，该至少一个第四材料层和该至少一个第五材料层形成第四材料层与第五材料层彼此相邻的结构，该第四材料与该第五材料不同，该第四材料层与该衬底直接接触；
在该多层结构上制备至少一个第一沟槽，该第一沟槽自该多层结构的上表面沿着第一方向延伸进入该多层结构；
在该多层结构的上方和该至少一个第一沟槽内沉积第三材料，以形成第一结构；
在该第一结构上制备至少一个第二沟槽，该第二沟槽自该第一结构的上 表面沿着该第一方向延伸进入该多层结构，以露出该至少一层第五材料层，且该第二沟槽位于该第一沟槽的外侧；
去除该第二沟槽中露出的第五材料层，以形成该至少一个多翼结构。
需要理解的是，相对于该第四材料，该第五材料可以被选择性去除。具体地，在同一腐蚀或刻蚀环境，该第四材料和该第五材料的腐蚀(或刻蚀)速率的差异大于5倍。
具体地，首先，利用CVD工艺在衬底160上依次沉积第四材料层14、第五材料层15、第四材料层14、第五材料层15、第四材料层14和第五材料层15，以在该衬底160的上方形成该多层结构，如图17f所示。例如，该第四材料14为重掺硼的多晶硅，该第五材料15为BSG。具体第四材料层14和第五材料层15的厚度可根据电容器的容值、频率特性、损耗等需求来调整。
接着，在如图17f所示的多层结构的上表面旋涂一层光刻胶，曝光、显影之后打开若干光刻胶的缺口，利用干法刻蚀工艺去除未被光刻胶覆盖的该多层结构，形成3个第一沟槽41，去除光刻胶，如图17g所示。
然后，在该多层结构上表面和该第一沟槽41内表面沉积第三材料13，以形成该第一结构，如图17h所示。
再然后，在如图17h所示的结构中，在该第一结构的上表面旋涂一层光刻胶，曝光、显影之后打开若干光刻胶的缺口，利用干法刻蚀工艺去除未被光刻胶覆盖的该第一结构，形成4个第二沟槽42，且在该第二沟槽42内露出该至少一个第五材料层；最后，去除光刻胶，如图17i所示。
最后，在如图17i所示的结构中，假设该牺牲材料为BSG，以该第二沟槽42为释放孔，在该第二沟槽42内通入氢氟酸溶液或气态氢氟酸作为腐蚀剂，去除该第二沟槽中露出的全部第五材料层(BSG)，以形成3个多翼结构110，如图17j所示。
可选地，该多层结构的沉积方式，可以使用旋涂、喷涂、热氧化、外延、物理气相沉积(PVD)、化学气相沉积(CVD)、原子层沉积(ALD)、外延生长等多种工艺。
可选地，可以使用热氧化法、原子层沉积(Atomic layer deposition，ALD)、化学气相沉积(Chemical Vapor Deposition，CVD)等多种工艺在该衬底160上形成该叠层结构120。
具体地，可以通过如下方式制备该叠层结构120：
以如图17b所示的多翼结构110为例，假设该叠层结构120包括2层导电层和1层电介质层，2层导电层记为导电层121和导电层122，1层电介质层记为电介质层123，利用ALD工艺在如图17b所示的多翼结构110上依次沉积导电层121、电介质层123和导电层122，如图17k所示。
可选地，该方法200还包括：
制备填充结构150，所述填充结构150包覆所述叠层结构120，以填充所述叠层结构120形成的空隙。
例如，所述填充结构150在外形上与所述叠层结构120互补。
具体地，在如图17k所示的结构中，利用LPCVD工艺，在叠层结构120的上方填充第六材料，以形成该填充结构150，如图17l所示。
可选地，该第六材料可以是导电材料，也可以是其他的材料。
可选地，在一些实施例中，该方法200还包括：
制备互联结构170，以使该第一外接电极130和/或该第二外接电极140通过该互联结构170电连接至该多层导电层中的导电层。
可选地，该互联结构170包括至少一个绝缘层171和导电通道172，该导电通道172贯穿该至少一个绝缘层171，以电连接该多层导电层中的导电层。
可选地，该至少一个绝缘层171的沉积方法包括旋涂、喷涂或者物理气相沉积(PVD)或化学气相沉积(CVD)。
可选地，该导电通道172的沉积方法包括PVD、金属有机化合物化学气相沉淀(Metal-organic Chemical Vapor Deposition，MOCVD)、ALD。
具体地，在如图17l所示的结构中，对该填充结构150进行光刻处理，以形成至少一个窗口结构50，并露出该叠层结构110中的导电层121，如图17m所示；在该填充结构150上表面和该至少一个窗口结构50内沉积绝缘材料，以形成绝缘层171，并对该绝缘层171进行光刻处理，以形成两个通孔结构51，分别露出导电层121和导电层122，如图17n所示；在通孔结构51内沉积导电材料，以形成导电通道172，进而形成该互联结构170，如图17o所示。
可选地，在一些实施例中，可以在该叠层结构120上方制备电极层，该电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，该 第一导电区域形成该第一外接电极130，该第二导电区域形成该第二外接电极140。
可选地，该电极层的沉积方法包括PVD、电镀、化镀。
具体地，在如图17o所示的结构中，在该互联结构170上表面沉积该电极层，并对该电极层进行光刻处理，以得到相互分离的至少一个第一导电区域和至少一个第二导电区域，该第一导电区域形成该第一外接电极130，该第二导电区域形成该第二外接电极140，从而制备如图1所示的电容器100。
可选地，在一些实施例中，该多翼结构110自该衬底160的上表面沿着第一方向延伸进入该衬底160。例如，该多翼结构110中的轴沿着该第一方向延伸进入该衬底160，从而可以制备如图9所示的电容器。
在一些可能的实现方式中，该叠层结构120自该衬底160的上表面沿着第一方向延伸进入该衬底160。例如，该叠层结构120中的导电层121、导电层122和电介质层123自该衬底160的上表面沿着第一方向延伸进入该衬底160，并且，该填充结构150也延伸进入该衬底160，从而可以制备如图10所示的电容器。
可选地，在一些实施例中，该衬底160为低电阻率衬底，上述步骤230具体包括：在该衬底160下方制备该至少一个第一外接电极130，以及在该多翼结构的上方制备该至少一个第二外接电极140。
具体地，在如图17l所示的结构中，在衬底160下表面沉积电极材料，以形成第一外接电极130，以及在填充结构150的上表面沉积电极材料以形成第二外接电极140，从而制备如图11或图12所示的电容器。
可选地，该第一外接电极130和该第二外接电极140的沉积方法包括PVD、电镀、化镀。
可选地，在一些实施例中，该多层导电层包括：第一导电层，该第一导电层在外形上与该多翼结构110互补。该叠层结构120中除该第一导电层之外的导电层和电介质层与该多翼结构110共形。从而，基于上述步骤210至230可以制备如图8所示的电容器。
可选地，在一些实施例中，该多翼结构110由电阻率小于阈值的材料形成，或者，该多翼结构110的表面形成有重掺杂的电阻率小于阈值的导电层。
例如，该叠层结构120中距离该多翼结构110最近的导电层电连接该第一外接电极130，以及该多翼结构110电连接该第二外接电极140。
又例如，该叠层结构120中距离该多翼结构110最近的导电层电连接该第二外接电极140，以及该多翼结构110电连接该第一外接电极130。
在一些可能的实现方式中，该方法还包括：
制备隔离环180，该隔离环180位于该至少一个多翼结构110的外侧，且该隔离环180设置于该叠层结构120中，并自该叠层结构120的上表面沿着第一方向延伸进入或者贯穿该叠层结构120，以将该叠层结构120隔离为第一区域10和第二区域20，该第一外接电极130和/或该第二外接电极140仅与位于该第一区域10的该叠层结构120电连接。
具体地，在步骤220中可以制备如图17p所示的结构，然后，对该填充结构150进行光刻处理，以形成一个窗口结构50，并露出叠层结构120中的导电层121，如图17q所示。然后，在该填充结构150上表面和该至少一个窗口结构50内沉积绝缘材料，以形成互联结构170中的该绝缘层171和隔离环180，如图17r所示。再然后，对该绝缘层171进行光刻处理，以形成两个通孔结构51，以分别露出叠层结构120中的导电层121和导电层122，如图17s所示。再然后，在该绝缘层171的上表面、通孔结构51内沉积电极材料，并进行光刻处理，以制备如图13所示的电容器。
需要说明的是，该隔离环180沿着该第一方向延伸进入位于电容芯片边缘的叠层结构120内，从而，将该叠层结构120隔离为第一区域10和第二区域20，该第二外接电极140仅与位于该第一区域10的该叠层结构120电连接。
具体地，在如图17l所示的结构中，对该填充结构150进行光刻处理，以形成一个窗口结构50和环状沟槽60，该窗口结构50中露出叠层结构120中的导电层121，该环状沟槽60内露出衬底160。然后，在该填充结构150上表面、该至少一个窗口结构50内和环状沟槽60内沉积绝缘材料，以形成该互联结构170中的绝缘层171和隔离环180。再然后，对该绝缘层171进行光刻处理，以形成两个通孔结构51，以分别露出叠层结构120中的导电层121和导电层122。再然后，在该绝缘层171的上表面、通孔结构51内沉积电极材料，并进行光刻处理，以制备如图14所示的电容器。
因此，在本申请实施例提供的电容器的制作方法中，通过制备多翼结构的方式，可以增大电容器的电容值。
下面结合两个具体地实施例对本申请的电容器的制作方法作进一步说 明。为了便于理解，在该实施例一中制作如图1所示的电容器。在该实施例二中制作如图7所示的电容器。当然，利用该实施例一和实施例二中的电容器的制作方法还可以制作如图8、图9、图10、图11、图12、图13和图14所示的电容器，只是在电极层、衬底、多翼结构、叠层结构和隔离环的设置等部分有所区别，为了简洁，在此不再赘述。
实施例一
步骤一：选取硅晶圆作为衬底。利用CVD工艺，在衬底上沉积结构材料1-牺牲材料-结构材料1-牺牲材料-结构材料1-牺牲材料的叠层结构。其中结构材料1为重掺硼的多晶硅，牺牲材料为BSG。
步骤二：在叠层结构表面旋涂一层光刻胶，曝光、显影后打开若干光刻胶的缺口，然后利用干法刻蚀工艺去除未被光刻胶覆盖的膜层结构，形成沟槽1。最后去除光刻胶。
步骤三：利用CVD工艺，在沟槽1内部填充重掺硼的多晶硅，作为结构材料2。
步骤四：在结构材料2表面旋涂一层光刻胶，曝光、显影后打开若干光刻胶的缺口，然后利用干法刻蚀工艺去除未被光刻胶覆盖的膜层结构，形成沟槽2。最后去除光刻胶。
步骤五：将沟槽2作为释放孔，使用氢氟酸溶液或气态氢氟酸作为腐蚀剂，去除BSG，得到由多晶硅组成的多翼状结构。需要注意的是，由于沟槽1和沟槽2在衬底表面的投影可以多种多样，所以翼状结构的三维形态也有多种可能。
步骤六：利用ALD工艺，在多翼状结构表面沉积一层TiN，作为电容的第一极板；接着沉积一层氧化铝作为电介质层；最后沉积一层TiN作为第二极板。
步骤七：利用低压力化学气相沉积法(Low Pressure Chemical Vapor Deposition，LPCVD)工艺，沉积氧化硅作为填充材料，填充、包覆整个多翼结构。
步骤八：在填充材料表面旋涂一层光刻胶，曝光、显影后打开一个光刻胶的缺口，然后利用干法刻蚀工艺去除缺口内的第二导电层及电介质层，露出电容第一导电层。
步骤九：利用PECVD工艺，沉积一层USG作为绝缘材料。
步骤十：在USG表面旋涂一层光刻胶，曝光、显影后打开2个光刻胶的缺口，然后利用氢氟酸溶液去除缺口内的USG和氧化硅。两个缺口分别露出第一导电层和第二导电层。
步骤十一：利用PVD工艺，沉积一层Al。利用光刻形成Al的两个焊盘(电极)。其中一个焊盘连接第一导电层，另一个焊盘连接第二导电层。
实施例二
步骤一：选取硅晶圆作为衬底。利用CVD工艺，在衬底上沉积结构材料-牺牲材料-结构材料-牺牲材料-结构材料-牺牲材料的叠层结构。其中结构材料为不定形硅，牺牲材料为TEOS。
步骤二：在叠层结构表面旋涂一层光刻胶，曝光、显影后打开若干光刻胶的缺口，然后利用干法刻蚀工艺去除未被光刻胶覆盖的膜层结构，形成沟槽。最后去除光刻胶。
步骤三：将沟槽作为释放孔，使用氢氟酸溶液或气态氢氟酸作为TEOS的腐蚀剂，通过控制腐蚀速率和时间，保留部分TEOS，得到下图所示的多翼结构。
步骤四：利用ALD工艺，在多翼状结构表面沉积一层TiN，作为电容的第一极板；沉积一层氧化铝作为第一电介质层；沉积一层TiN作为第二极板；沉积一层氧化铝作为第二电介质层；最后，利用LPCVD工艺，将剩余空隙填满重掺杂多晶硅，作为第三极板。
步骤五：利用两步光刻工艺，打开两个缺口，分别露出第一极板和第二极板，如图所示。
步骤六：利用等离子体增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)工艺，沉积一层氧化硅作为层间介质层。
步骤七：利用光刻工艺，打开若干通孔，分别露出第一极板、第二极板、第三极板。
步骤八：利用PVD工艺，在通孔内沉积一层Ti作为黏附层，一层TiN作为阻挡层；再利用MOCVD工艺，将通孔填满钨，形成导电通道。最后利用表面平坦化工艺，磨去表面多余的金属。
步骤九：利用PVD工艺沉积一层Ti，一层TiN，一层Al；最后利用光刻形成两个焊盘。其中一个焊盘通过导电通道连接第一极板、第三极板，另一个焊盘通过导电通道连接第二极板。
本领域普通技术人员可以意识到，以上结合附图详细描述了本申请的优选实施方式，但是，本申请并不限于上述实施方式中的具体细节，在本申请的技术构思范围内，可以对本申请的技术方案进行多种简单变型，这些简单变型均属于本申请的保护范围。
另外需要说明的是，在上述具体实施方式中所描述的各个具体技术特征，在不矛盾的情况下，可以通过任何合适的方式进行组合，为了避免不必要的重复，本申请对各种可能的组合方式不再另行说明。
此外，本申请的各种不同的实施方式之间也可以进行任意组合，只要其不违背本申请的思想，其同样应当视为本申请所申请的内容。

Claims (40)

  1. 一种电容器，其特征在于，所述电容器包括：
    至少一个多翼结构；
    叠层结构，所述叠层结构包覆所述至少一个多翼结构，所述叠层结构包括至少一层电介质层和多层导电层，所述至少一层电介质层和所述多层导电层形成导电层与电介质层彼此相邻的结构；
    至少一个第一外接电极，所述第一外接电极电连接至所述多层导电层中的一部分导电层；
    至少一个第二外接电极，所述第二外接电极电连接至所述多层导电层中的另一部分导电层，所述一部分导电层中的每个导电层在所述叠层结构中相邻的导电层包括有所述另一部分导电层中的至少一个导电层。
  2. 根据权利要求1所述的电容器，其特征在于，所述第一外接电极电连接至所述多层导电层中的所有奇数层导电层，以及所述第二外接电极电连接至所述多层导电层中的所有偶数层导电层。
  3. 根据权利要求1或2所述的电容器，其特征在于，所述多层导电层包括：第一导电层，所述第一导电层在外形上与所述多翼结构互补。
  4. 根据权利要求3所述的电容器，其特征在于，所述叠层结构中除所述第一导电层之外的导电层和电介质层与所述多翼结构共形。
  5. 根据权利要求1或2所述的电容器，其特征在于，所述电容器还包括：填充结构，所述填充结构包覆所述叠层结构，以填充所述叠层结构形成的空隙。
  6. 根据权利要求5所述的电容器，其特征在于，所述填充结构在外形上与所述叠层结构互补。
  7. 根据权利要求1至6中任一项所述的电容器，其特征在于，所述多翼结构由电阻率小于阈值的材料形成，或者，所述多翼结构的表面形成有重掺杂的电阻率小于阈值的导电层。
  8. 根据权利要求7所述的电容器，其特征在于，
    所述叠层结构中距离所述多翼结构最近的导电层电连接所述第一外接电极，以及所述多翼结构电连接所述第二外接电极；或者
    所述叠层结构中距离所述多翼结构最近的导电层电连接所述第二外接电极，以及所述多翼结构电连接所述第一外接电极。
  9. 根据权利要求1至8中任一项所述的电容器，其特征在于，所述多翼结构包括N个轴和M个翼，其中，所述N个轴延着第一方向延伸，所述M个翼为从所述N个轴的侧壁向垂直于所述第一方向的方向延伸形成的凸起结构，M为大于或者等于2的整数，N为正整数。
  10. 根据权利要求9所述的电容器，其特征在于，所述M个翼由第一材料形成，所述N个轴中连接所述翼的区域由所述第一材料形成，以及所述N个轴中除连接所述翼的区域之外的区域由与所述第一材料不同的第二材料形成。
  11. 根据权利要求9所述的电容器，其特征在于，所述M个翼中的第一翼和所述N个轴由第三材料形成，所述M个翼中除所述第一翼之外的翼由与所述第三材料不同的第四材料形成。
  12. 根据权利要求11所述的电容器，其特征在于，所述第一翼位于所述M个翼中其余翼的上方。
  13. 根据权利要求1至12中任一项所述的电容器，其特征在于，所述电容器还包括：衬底，设置于所述多翼结构的下方。
  14. 根据权利要求13所述的电容器，其特征在于，所述电容器还包括：
    隔离环，位于所述至少一个多翼结构的外侧，且所述隔离环设置于所述叠层结构中，并自所述叠层结构的上表面沿着第一方向延伸进入或者贯穿所述叠层结构，以将所述叠层结构隔离为第一区域和第二区域，所述第一外接电极和/或所述第二外接电极仅与位于所述第一区域的所述叠层结构电连接。
  15. 根据权利要求13或14所述的电容器，其特征在于，所述多翼结构自所述衬底的上表面沿着第一方向延伸进入所述衬底。
  16. 根据权利要求13至15中任一项所述的电容器，其特征在于，所述叠层结构自所述衬底的上表面沿着第一方向延伸进入所述衬底。
  17. 根据权利要求13至16中任一项所述的电容器，其特征在于，所述衬底为电阻率小于阈值的衬底，所述第一外接电极设置于所述衬底的下方，所述第二外接电极设置于所述多翼结构的上方。
  18. 根据权利要求1至16中任一项所述的电容器，其特征在于，所述电容器还包括：电极层，设置于所述多翼结构的上方，所述电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，所述第一导电区域形成所述第一外接电极，所述第二导电区域形成所述第二外接电极。
  19. 根据权利要求1至18中任一项所述的电容器，其特征在于，所述第一外接电极和/或所述第二外接电极通过互联结构电连接至所述多层导电层中的导电层。
  20. 根据权利要求19所述的电容器，其特征在于，所述互联结构包括至少一个绝缘层和导电通道，所述导电通道贯穿所述至少一个绝缘层，以电连接所述多层导电层中的导电层。
  21. 根据权利要求1至20中任一项所述的电容器，其特征在于，所述导电层包括以下中的至少一层：
    重掺杂多晶硅层，金属硅化物层，碳层，导电聚合物层，铝层，铜层，镍层，氮化钽层，氮化钛层，氮化铝钛层，氮化硅钽层，氮化碳钽层。
  22. 根据权利要求1至21中任一项所述的电容器，其特征在于，所述电介质层包括以下中的至少一层：
    硅的氧化物层，硅的氮化物层，硅的氮氧化物层，金属的氧化物层，金属的氮化物层和金属的氮氧化物层。
  23. 一种电容器的制作方法，其特征在于，包括：
    在衬底上方制备至少一个多翼结构；
    在所述至少一个多翼结构表面制备叠层结构，所述叠层结构包覆所述多翼结构，所述叠层结构包括至少一层电介质层和多层导电层，所述至少一层电介质层和所述多层导电层形成导电层与电介质层彼此相邻的结构；
    制备至少一个第一外接电极和至少一个第二外接电极，其中，所述第一外接电极电连接至所述多层导电层中的一部分导电层，所述第二外接电极电连接至所述多层导电层中的另一部分导电层，所述一部分导电层中的每个导电层在所述叠层结构中相邻的导电层包括有所述另一部分导电层中的至少一个导电层。
  24. 根据权利要求23所述的方法，其特征在于，所述第一外接电极电连接至所述多层导电层中的所有奇数层导电层，以及所述第二外接电极电连接至所述多层导电层中的所有偶数层导电层。
  25. 根据权利要求23或24所述的方法，其特征在于，所述在衬底上方制备至少一个多翼结构，包括：
    在衬底上方制备多层结构，所述多层结构包括至少两个第一材料层和至少一个第二材料层，所述至少两个第一材料层和所述至少一个第二材料层形 成第一材料层与第二材料层彼此相邻的结构，所述第一材料与所述第二材料不同，以及所述第一材料层与所述衬底直接接触；
    在所述多层结构上制备至少一个第一沟槽，所述第一沟槽自所述多层结构的上表面沿着第一方向延伸进入所述多层结构；
    去除所述第一沟槽中露出的部分第二材料层，以形成所述至少一个多翼结构。
  26. 根据权利要求23或24所述的方法，其特征在于，所述在衬底上方制备至少一个多翼结构，包括：
    在衬底上方制备多层结构，所述多层结构包括至少一个第四材料层和至少一个第五材料层，所述至少一个第四材料层和所述至少一个第五材料层形成第四材料层与第五材料层彼此相邻的结构，所述第四材料与所述第五材料不同，所述第四材料层与所述衬底直接接触；
    在所述多层结构上制备至少一个第一沟槽，所述第一沟槽自所述多层结构的上表面沿着第一方向延伸进入所述多层结构；
    在所述多层结构的上方和所述至少一个第一沟槽内沉积第三材料，以形成第一结构；
    在所述第一结构上制备至少一个第二沟槽，所述第二沟槽自所述第一结构的上表面沿着所述第一方向延伸进入所述多层结构，以露出所述至少一层第五材料层，且所述第二沟槽位于所述第一沟槽的外侧；
    去除所述第二沟槽中露出的第五材料层，以形成所述至少一个多翼结构。
  27. 根据权利要求23至26中任一项所述的方法，其特征在于，所述多层导电层包括：第一导电层，所述第一导电层在外形上与所述多翼结构互补。
  28. 根据权利要求27所述的方法，其特征在于，所述叠层结构中除所述第一导电层之外的导电层和电介质层与所述多翼结构共形。
  29. 根据权利要求23至26中任一项所述的方法，其特征在于，所述方法还包括：
    制备填充结构，所述填充结构包覆所述叠层结构，以填充所述叠层结构形成的空隙。
  30. 根据权利要求29所述的方法，其特征在于，所述填充结构在外形上与所述叠层结构互补。
  31. 根据权利要求23至30中任一项所述的方法，其特征在于，所述多 翼结构由电阻率小于阈值的材料形成，或者，所述多翼结构的表面形成有重掺杂的电阻率小于阈值的导电层。
  32. 根据权利要求31所述的方法，其特征在于，
    所述叠层结构中距离所述多翼结构最近的导电层电连接所述第一外接电极，以及所述多翼结构电连接所述第二外接电极；或者
    所述叠层结构中距离所述多翼结构最近的导电层电连接所述第二外接电极，以及所述多翼结构电连接所述第一外接电极。
  33. 根据权利要求23至32中任一项所述的方法，其特征在于，所述多翼结构包括N个轴和M个翼，其中，所述N个轴延着所述第一方向延伸，所述M个翼为从所述N个轴的侧壁向垂直于所述第一方向的方向延伸形成的凸起结构，M为大于或者等于2的整数，N为正整数。
  34. 根据权利要求23至33中任一项所述的方法，其特征在于，所述方法还包括：
    制备隔离环，所述隔离环位于所述至少一个多翼结构的外侧，且所述隔离环设置于所述叠层结构中，并自所述叠层结构的上表面沿着第一方向延伸进入或者贯穿所述叠层结构，以将所述叠层结构隔离为第一区域和第二区域，所述第一外接电极和/或所述第二外接电极仅与位于所述第一区域的所述叠层结构电连接。
  35. 根据权利要求23至34中任一项所述的方法，其特征在于，所述多翼结构自所述衬底的上表面沿着第一方向延伸进入所述衬底。
  36. 根据权利要求23至35中任一项所述的方法，其特征在于，所述叠层结构自所述衬底的上表面沿着第一方向延伸进入所述衬底。
  37. 根据权利要求23至36中任一项所述的方法，其特征在于，所述制备至少一个第一外接电极和至少一个第二外接电极，包括：
    在所述叠层结构上方制备电极层，所述电极层包括相互分离的至少一个第一导电区域和至少一个第二导电区域，所述第一导电区域形成所述第一外接电极，所述第二导电区域形成所述第二外接电极。
  38. 根据权利要求23至36中任一项所述的方法，其特征在于，所述衬底为电阻率小于阈值的衬底；
    所述制备至少一个第一外接电极和至少一个第二外接电极，包括：
    在所述衬底下方制备所述至少一个第一外接电极，以及
    在所述多翼结构的上方制备所述至少一个第二外接电极。
  39. 根据权利要求23至38中任一项所述的方法，其特征在于，所述方法还包括：
    制备互联结构，以使所述第一外接电极和/或所述第二外接电极通过所述互联结构电连接至所述多层导电层中的导电层。
  40. 根据权利要求39所述的方法，其特征在于，所述互联结构包括至少一个绝缘层和导电通道，所述导电通道贯穿所述至少一个绝缘层，以电连接所述多层导电层中的导电层。
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