WO2020215293A1 - 一种供电电路和供电控制方法 - Google Patents

一种供电电路和供电控制方法 Download PDF

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Publication number
WO2020215293A1
WO2020215293A1 PCT/CN2019/084403 CN2019084403W WO2020215293A1 WO 2020215293 A1 WO2020215293 A1 WO 2020215293A1 CN 2019084403 W CN2019084403 W CN 2019084403W WO 2020215293 A1 WO2020215293 A1 WO 2020215293A1
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Prior art keywords
voltage conversion
conversion circuit
switch
voltage
circuit
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/084403
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English (en)
French (fr)
Inventor
邹鹏
黄伯宁
吴建权
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to EP19925755.1A priority Critical patent/EP3952090A4/en
Priority to PCT/CN2019/084403 priority patent/WO2020215293A1/zh
Priority to CN201980091012.0A priority patent/CN113366748B/zh
Publication of WO2020215293A1 publication Critical patent/WO2020215293A1/zh
Priority to US17/451,986 priority patent/US11757362B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/008—Plural converter units for generating at two or more independent and non-parallel outputs, e.g. systems with plural point of load switching regulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1582—Buck-boost converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/007—Plural converter units in cascade
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1584—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H01F17/0006—Printed inductances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H01F17/0006—Printed inductances
    • H01F2017/0053—Printed inductances with means to reduce eddy currents
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00—Fixed inductances of the signal type
    • H01F17/0006—Printed inductances
    • H01F2017/0066—Printed inductances with a magnetic layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F3/00—Cores, Yokes, or armatures
    • H01F3/10—Composite arrangements of magnetic circuits
    • H01F3/14—Constrictions; Gaps, e.g. air-gaps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0043—Converters switched with a phase shift, i.e. interleaved
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from DC input or output
    • H02M1/15—Arrangements for reducing ripples from DC input or output using active elements
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the embodiments of the present application relate to the field of circuit technology, and in particular, to a power supply circuit and a power supply control method.
  • the power supply architecture of a current system includes multiple buck converters, through which a battery or a given input voltage can be converted into a required voltage to supply power to the load module.
  • the voltage converter can be between the input voltage (battery) and the load module (for example, the central processing unit (CPU) physical core and the graphics processing unit (GPU) physical core, etc.) Complete point-to-point voltage conversion and power supply.
  • the load module for example, the central processing unit (CPU) physical core and the graphics processing unit (GPU) physical core, etc.
  • the number of voltage converters has an increasing trend, and each voltage converter circuit needs to be designed according to the maximum peak current of the load (even if the current in a typical working scenario is much smaller than the peak current ).
  • the printed circuit board (PCB) area of the power supply is proportional to the maximum current, with the demand for system performance improvement, the peak current and the number of power supply circuits will increase, and the area of the power supply PCB solution will continue to increase.
  • the area of a system (such as a smart phone) is usually fixed or limited, so the continuous increase in the area of the required power supply will pose a huge challenge to the system solution.
  • the embodiments of the present application provide a power supply circuit and a power supply control method, which can reduce the board area of an overall power supply solution, have a high power density, and improve the power supply efficiency of the system.
  • a power supply circuit includes: one or more first-level voltage conversion circuits and one or more second-level voltage conversion circuits; wherein the first-level voltage conversion The input terminal of the circuit is coupled to the power supply; the first-stage voltage conversion circuit is used to convert the first voltage received at its input terminal into a second voltage and output from the output terminal of the first-stage voltage conversion circuit.
  • the second voltage is less than the first voltage, the second voltage is greater than or equal to 0.6V, and less than or equal to 1.3V; the input terminal of the second stage voltage conversion circuit is coupled to the output terminal of the first stage voltage conversion circuit, the first The second-level voltage conversion circuit is used to convert the above-mentioned second voltage into a third voltage and provide the third voltage to the load.
  • the third voltage is less than the second voltage; the switching frequency of the second-level voltage conversion circuit is greater than or equal to 30Mhz. Based on this scheme, in the power supply circuit composed of the first-level voltage conversion circuit and the second-level voltage conversion circuit, the second-level voltage conversion circuit only needs to further convert the voltage in the low-voltage range of 0.6V-1.3V.
  • a high-frequency switch greater than 30MHz is used, which greatly reduces the space requirement of the power supply circuit. Even when multiple second-stage voltage conversion circuits can share the first-stage voltage conversion circuit, the space requirement of the power supply circuit of the embodiment of the present invention is further reduced. Therefore, the board area of the power supply circuit is greatly reduced, the power density is greatly improved, and the power supply efficiency is improved.
  • each first-level voltage conversion circuit can supply power to one or more second-level voltage conversion circuits, and then the second-level voltage conversion circuit supplies power to the load.
  • the power supply provided by the embodiment of the present invention The circuit forms a tree structure.
  • the second-level voltage conversion circuit includes an inductor, a capacitor, a first switch, and a second switch, and the first end of the first switch is connected to the second switch.
  • the second terminal of the first switch is connected to the first terminal of the inductor and the first terminal of the second switch.
  • the control terminal of the first switch is used to input the first control signal; the second terminal of the inductor It is the output terminal of the second-level voltage conversion circuit, the second terminal of the inductor is connected to the first terminal of the capacitor, the second terminal of the capacitor and the second terminal of the second switch are grounded; the control terminal of the second switch is used to input the second control Signal; wherein, the switching frequency of the first switch and the second switch is greater than or equal to 30Mhz.
  • the inductance density of the foregoing inductor is greater than or equal to 10nH/mm 2 , and the inductance density of the inductor is greater than or equal to 40nH/mm 3 , and the coil DC impedance of the inductor is less than or equal to 30m ⁇ .
  • the inductance per unit area per square millimeter
  • the inductance per unit volume per cubic millimeter
  • the inductance per unit area and unit volume of the first inductor has been greatly improved compared to the inductance in the prior art. Therefore, when the inductance is the same, the area and volume of the first inductor are both larger. small. Based on this solution, the footprint and volume of the inductors under the above specifications are small, which makes the power supply circuit more integrated. And when the inductor works at high frequency, the loss of the second-stage voltage conversion circuit is reduced, which improves the power supply efficiency of the second-stage voltage conversion circuit.
  • the foregoing inductor is a thin film inductor
  • the thin film inductor includes: a magnetic core including a first magnetic film and a second magnetic film; and a first magnetic film
  • the conductor is located in the accommodation cavity
  • the insulating spacer film is arranged on both sides of the conductor and is located between the first magnetic film and the second magnetic film
  • the insulating spacer film and the first magnetic film In contact with the second magnetic film
  • both the first magnetic film and the second magnetic film include a multilayer magnetic sub-film and a multilayer insulating sub-film
  • in the first magnetic film the magnetic sub-films and the insulator sub-films are alternately arranged
  • in the second magnetic film The magnetic sub-film and the insulating sub-film are arranged alternately; the surface of the first magnetic film in contact with the insulating spacer film exposes the multilayer magnetic sub-film
  • the second-level voltage conversion circuit includes an inductor, a capacitor, a third switch, a fourth switch, a fifth switch, and a sixth switch.
  • the first terminal of the three switches is connected to the output terminal of the first-stage voltage conversion circuit, the second terminal of the third switch is connected to the first terminal of the fourth switch, and the control terminal of the third switch is used to input the third control signal;
  • the fourth switch The second end of the fifth switch is connected to the first end of the inductor and the first end of the fifth switch, the control end of the fourth switch is used to input the first bias voltage;
  • the second end of the fifth switch is connected to the first end of the sixth switch
  • the control terminal of the fifth switch is used to input the second bias voltage;
  • the second terminal of the inductor is the output terminal of the second-level voltage conversion circuit, the second terminal of the inductor is connected to the first terminal of the capacitor, and the second terminal of the capacitor And the second end of the sixth switch are grounded;
  • the peak power of the first-stage voltage conversion circuit is less than the sum of the peak powers of one or more second-stage voltage conversion circuits connected to it . Based on this solution, over-design of the first-level voltage conversion circuit can be avoided, and the board area of the first-level power supply circuit can be further reduced, and the power density of the power supply circuit can be improved.
  • the foregoing first-stage voltage conversion circuit is a switched capacitor voltage converter circuit, a switched capacitor voltage converter circuit with a variable conversion ratio, and a buck DC-DC converter circuit, multi-level step-down converter circuit, transformer-isolated step-down converter circuit, mixed switch inductor and switch capacitor combined voltage converter circuit, or resonant switched capacitor voltage converter circuit. Based on this solution, the conversion efficiency of the first-stage voltage conversion circuit is relatively high, and the power supply efficiency is further improved.
  • the foregoing second-stage voltage conversion circuit is integrated with the foregoing load. Based on this solution, the power supply circuit has a higher degree of integration and a higher power density.
  • the step-down conversion of the second-level voltage conversion circuit can be realized by controlling the on and off of the first switch and the second switch.
  • a second aspect of the embodiments of the present application provides a power supply control method, which is applied to a power supply system.
  • the power supply system includes the power supply circuit in any one of the above-mentioned first aspect implementations, and the power supply circuit connected to the first-stage voltage conversion circuit.
  • the available power of the first-stage voltage conversion circuit is the maximum output power of the first-stage voltage conversion circuit minus the used power, and the used power is the same as the first-stage power
  • the maximum output power of the first-stage voltage conversion circuit can be preset. Based on this solution, the available power of the first-stage voltage conversion circuit can be determined according to the sum of the maximum output power of the first-stage voltage conversion circuit and the current output power of the second-stage voltage conversion circuit.
  • the foregoing method further includes: the main controller determines each first-stage voltage The first reference delay time corresponding to the conversion circuit; the first reference delay time is the delay time corresponding to each first-stage voltage conversion circuit when the ripple amplitude of the first voltage is the smallest; according to the first reference delay time, adjust The conduction time of each first-stage voltage conversion circuit. Based on this solution, the switch tubes of the multiple first-stage voltage conversion circuits can be staggered (staggered and turned on), thereby reducing voltage ripple.
  • the foregoing method further includes: the main controller determines and The second reference delay time corresponding to each second-level voltage conversion circuit connected to the first-level voltage conversion circuit; the second reference delay time is when the ripple amplitude of the second voltage is the smallest, each second-level voltage conversion The delay time corresponding to the circuit; according to the second reference delay time, the on-time of each second-stage voltage conversion circuit is adjusted. Based on this solution, the switch tubes of multiple second-stage voltage conversion circuits are staggered (staggered and turned on), thereby reducing voltage ripple.
  • the power supply system further includes a delay circuit, and the main controller determines the first reference delay time corresponding to each first-stage voltage conversion circuit, Including: the main controller configures the delay time of the switch on or off in each first-stage voltage conversion circuit according to the system reference clock and the delay circuit, and determines the first reference delay time. Based on this solution, the reference delay time can be determined by the delay circuit, so that the voltage ripple is minimized.
  • the above-mentioned main controller determines the second reference delay time corresponding to each second-stage voltage conversion circuit connected to the first-stage voltage conversion circuit , Including: the main controller configures the on or off delay time of the switch in each second-stage voltage conversion circuit according to the system reference clock and the delay circuit, and determines the second reference delay time. Based on this solution, the reference delay time can be determined by the delay circuit, so that the voltage ripple is minimized.
  • the foregoing method further includes: if the load starts a high-performance service, the main controller increases the output voltage of the first-stage voltage conversion circuit; Working in a low power consumption state, the main controller reduces the output voltage of the first-stage voltage conversion circuit. Based on this solution, the output voltage of the first conversion circuit can be adjusted when the load is running different services, so as to meet service requirements in different situations and improve power supply efficiency.
  • the foregoing method further includes: the master controller obtains the current output power of the second-stage voltage conversion circuit from the first slave controller; The sum of the current output power of one or more second-level voltage conversion circuits connected to the first-level voltage conversion circuit is greater than the maximum output power of the first-level voltage conversion circuit, and the main controller sends alarm information to the operating system. Based on this solution, when the power exceeds an abnormal situation, alarm information can be sent to handle the abnormal situation.
  • a third aspect of the embodiments of the present application provides an integrated circuit system, characterized in that the integrated circuit system includes a first chip and a second chip, the first chip includes a first-level voltage conversion circuit, and the second chip includes The second-level voltage conversion circuit; wherein, the input terminal of the first-level voltage conversion circuit is coupled to the power supply; the first-level voltage conversion circuit is used to convert the first voltage received at its input terminal into a second voltage, and Output from the output terminal of the first-level voltage conversion circuit, the second voltage is less than the first voltage, the second voltage is greater than or equal to 0.6V, and less than or equal to 1.3V; the input terminal of the second-level voltage conversion circuit is Is coupled to the output terminal of the first-stage voltage conversion circuit, and the second-stage voltage conversion circuit is used to convert the second voltage into a third voltage and provide the third voltage to the load, the third voltage being smaller than the second voltage Voltage; the switching frequency of the second-stage voltage conversion circuit is greater than or equal to 30Mhz.
  • the power supply voltage can be reduced to 0.6V-1.3V through the first chip, and the 0.6V-1.3V voltage can be used as the input voltage of the second chip, due to the second-level voltage conversion in the second chip
  • the circuit uses a high-frequency switch greater than 30MHz, which can greatly reduce the space requirement of the second chip.
  • the space requirement of the integrated circuit system of the embodiment of the present invention is further reduced. Therefore, the board area of the integrated circuit system is greatly reduced, the power density is greatly improved, and the power supply efficiency is improved.
  • the second chip is a processor chip
  • the first chip is a power chip that provides power to the processor chip.
  • the second-level voltage conversion circuit can be integrated in the processor chip, and the first chip can provide power for the processor chip.
  • a fourth aspect of the embodiments of the present application provides a computer storage medium having computer program code stored in the computer storage medium, and when the computer program code runs on a processor, the processor executes the second aspect Or the power supply control method described in any of the possible implementations of the second aspect.
  • the processor may be a CPU
  • the master controller and the slave controller may be other processors, digital logic modules, or a certain functional module in the CPU.
  • the fifth aspect of the embodiments of the present application provides a computer program product that stores computer software instructions executed by the above-mentioned processor, and the computer software instructions include a program for executing the solution described in the above-mentioned aspect.
  • the sixth aspect of the embodiments of the present application provides a device that exists in the form of a chip product.
  • the structure of the device includes a processor and a memory.
  • the memory is used to couple with the processor and store the necessary programs of the device. Instructions and data, the processor is used to execute the program instructions stored in the memory, so that the device executes the function of the power supply control device in the above method.
  • a seventh aspect of the embodiments of the present application provides a terminal.
  • the terminal includes a processor and the power supply circuit described in the first aspect or any of the possible implementations of the first aspect, and the processor is configured to execute the second aspect. Or the power supply control method described in any of the possible implementations of the second aspect.
  • Figure 1 is a schematic diagram of a power supply scheme provided by the prior art
  • FIG. 2 is a schematic structural diagram of a power supply circuit provided by an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of another power supply circuit provided by an embodiment of the application.
  • FIG. 4 is a circuit diagram of a second-stage voltage conversion circuit provided by an embodiment of the application.
  • FIG. 5 is an equivalent circuit diagram of a second-stage voltage conversion circuit provided by an embodiment of the application.
  • FIG. 6 is a schematic structural diagram of a thin film inductor provided by an embodiment of the application.
  • FIG. 7 is a schematic diagram 1 of a specific structure of a thin film inductor provided by an embodiment of this application.
  • FIG. 8 is a second schematic diagram of a specific structure of a thin film inductor provided by an embodiment of the application.
  • FIG. 9 is a circuit diagram of another second-stage voltage conversion circuit provided by an embodiment of the application.
  • FIG. 10 is a schematic structural diagram of another power supply circuit provided by an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of another power supply circuit provided by an embodiment of the application.
  • FIG. 12 is a schematic structural diagram of another power supply circuit provided by an embodiment of the application.
  • FIG. 13 is a schematic structural diagram of a power supply system provided by an embodiment of the application.
  • FIG. 14 is a schematic flowchart of a power supply control method provided by an embodiment of this application.
  • 15 is a schematic flowchart of another power supply control method provided by an embodiment of the application.
  • 16 is a schematic flowchart of another power supply control method provided by an embodiment of the application.
  • FIG. 17 is a schematic structural diagram of a terminal device provided by an embodiment of this application.
  • At least one of a, b, or c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.
  • an embodiment of the present application provides a power supply circuit, which can reduce the board area of the overall power supply solution, has a higher power density, and improves the system performance. Power supply efficiency.
  • the embodiments of the present application also provide a power supply circuit, which can be applied to terminal equipment.
  • the terminal device can be a mobile phone, a tablet computer, a notebook computer, a netbook, etc.
  • the specific form of the terminal device applied by the power supply circuit is not particularly limited.
  • the power supply circuit 20 includes: one or more first-stage voltage conversion circuits 21 and one or more second-stage voltage conversion circuits 22.
  • the input terminal of the first-stage voltage conversion circuit 21 is coupled to the power source, and the input terminal of the second-stage voltage conversion circuit 22 is coupled to the output terminal of the first-stage voltage conversion circuit 21.
  • the first-stage voltage conversion circuit 21 is used to convert the first voltage received at its input terminal into a second voltage and output it from the output terminal of the first-stage voltage conversion circuit 21.
  • the second voltage is less than the first voltage.
  • the second voltage is greater than or equal to 0.6V and less than or equal to 1.3V.
  • the second-stage voltage conversion circuit 22 is used to convert the second voltage into a third voltage and provide the third voltage to the load, the third voltage being smaller than the second voltage.
  • the switching frequency of the second-stage voltage conversion circuit 22 is greater than or equal to 30Mhz.
  • the power supply voltage in the wireless terminal device (usually the battery voltage in the wireless terminal device) is usually about 4.5V.
  • the power supply circuit 20 of the embodiment of the present invention adopts a two-stage voltage conversion circuit. First, the voltage is initially reduced to between 0.6V-1.3V through the first-stage voltage conversion circuit 21. Then, the voltage is stepped down again by the second-stage voltage conversion circuit 22.
  • the input voltage of the second-level voltage conversion circuit 22 is only between 0.6V and 1.3V, when the power supply voltage of the load in the wireless terminal device is low (for example, when the processor chip of the wireless terminal adopts 5nm, 7nm and other advanced Complementary Metal Oxide Semiconductor (CMOS) process, the power supply voltage can be reduced to about 0.6V), because the smaller the voltage difference between the input voltage and the output voltage, the higher the conversion efficiency, therefore, through the second level of voltage After the conversion circuit has stepped down, the conversion efficiency of the second-stage voltage conversion circuit 22 is higher.
  • CMOS Complementary Metal Oxide Semiconductor
  • the second-level voltage conversion circuit can use two The switch tube realizes the step-down. Compared with the use of four switch tubes to step-down, due to the reduced number of switches, the circuit integration is higher, and the switching loss is greatly reduced.
  • the second-stage voltage conversion circuit 22 may adopt a high-frequency switch circuit design, or have a higher switching tube operating frequency, such as 30Mhz. It is understandable that the lower the operating frequency of the switching tube, the smaller the loss of the switching tube, and the higher the efficiency, but it may not meet the transient performance of load jump, and the ripple current is larger, which has a greater impact on the battery. . Therefore, after considering factors such as efficiency and transient performance of load jumps, the frequency of the switching tube in the second-stage voltage conversion circuit 22 in the embodiment of the present application may be greater than or equal to 30 MHz.
  • the circuit The occupied board area will also be larger.
  • the design of the high-frequency switching circuit adopted by the second-level voltage conversion circuit 22 can meet the transient performance requirements of load jump and reduce the number of energy storage components such as capacitors, so the circuit footprint is greatly reduced. Therefore, when the operating frequency of the switching tube in the second-stage voltage conversion circuit is higher than the operating frequency of the switching tube in the low-frequency switching circuit in the prior art, the power density of the circuit is significantly improved compared with the existing low-frequency switching circuit. The degree is higher, and the board area is greatly reduced.
  • each first-stage voltage conversion circuit 21 described above is coupled to a power source.
  • One first-level voltage conversion circuit 21 can supply power to one or more second-level voltage conversion circuits 22, and the input end of each second-level voltage conversion circuit 22 is connected to the output end of the first-level voltage conversion circuit 21.
  • the power supply circuit 20 includes two first-level voltage conversion circuits 21 and two second-level voltage conversion circuits 22, and the input end of each second-level voltage conversion circuit 22 is connected to a first-level The output terminal of the voltage conversion circuit 21.
  • the embodiment of the present application does not limit the specific number of the first-level voltage conversion circuit 21 and the second-level voltage conversion circuit 22, and FIG. 3 is only an exemplary illustration.
  • the number and connection mode of the first-level voltage conversion circuits 21 and the second-level voltage conversion circuits 22 can be configured according to parameters such as the power supply requirements of the load and the load position. It is understandable that the third voltage output by the power supply circuit 20 can be used for the central processing unit (CPU), graphics processing unit (GPU), artificial intelligence (AI) in FIG. 3 Loads such as processors, memory (memory), solid-state drives (SSD) and image processors (Image Processor) are powered. Wherein, the CPU, GPU, and AI processor may be multi-core processors.
  • the first-level voltage conversion circuit 21 supplies power to M second-level voltage conversion circuits 22, M is greater than or equal to 1, that is, the input terminals of the M second-level voltage conversion circuits 22 are converted to the first-level voltage
  • M is greater than or equal to 1
  • the input terminals of the M second-level voltage conversion circuits 22 are converted to the first-level voltage
  • the output terminal of the circuit 21 is connected, and the peak power of the first-stage voltage conversion circuit 21 may be less than the sum of the peak power of the M second-stage voltage conversion circuits 22 connected to it. It is understandable that since all the loads of the wireless terminal equipment will not work in the peak state at the same time, the peak power of the first-stage voltage conversion circuit 21 in the power supply circuit 20 can be less than that of all the second-stage voltage conversion circuits 22 connected to it. The sum of the peak power can avoid over-design of the first-stage voltage conversion circuit 21.
  • the peak power of the first-stage voltage conversion circuit 21 is designed to be less than the sum of the peak powers of all the second-stage voltage conversion circuits 22 connected to it, compared with the point-to-point voltage conversion in the prior art, and each voltage The converter circuit is designed according to the maximum peak current of the load, which can reduce the board area of the voltage conversion circuit and further increase the power density of the power supply circuit.
  • the sum of the peak power of the second-level voltage conversion circuit is 60W, and the actual application
  • the power of medium wireless terminal equipment is generally about 3W-4W, so the peak power of the first-stage voltage conversion circuit can be designed to be less than the sum of the peak power of all second-stage voltage conversion circuits connected to it.
  • the peak power of the first-stage voltage conversion circuit 21 can be designed to be 20% of the sum of the peak power of all the second-stage voltage conversion circuits 22 connected to it.
  • the embodiment of the present application does not limit the specific value of the peak power of the first-stage voltage conversion circuit, and is only an exemplary description here.
  • the above-mentioned first-stage voltage conversion circuit 21 may adopt an efficient direct current to direct current (DCDC) voltage converter circuit to implement voltage conversion.
  • DCDC direct current to direct current
  • switched capacitor voltage converter circuits switched capacitor voltage converter circuits with variable conversion ratios
  • step-down DC-DC converter circuits multi-level step-down converter circuits
  • transformer-isolated step-down converter circuits transformer-isolated step-down converter circuits
  • hybrid Switched inductor and switched capacitor combined voltage converter circuit or resonant switched capacitor voltage converter circuit, etc.
  • the embodiment of the present application does not limit the specific circuit structure of the first-stage voltage conversion circuit 21.
  • the first-stage voltage conversion circuit 21 can be a closed-loop controlled regulated rectifier circuit. At this time, the output voltage (second voltage) of the first-stage voltage conversion circuit 21 is constant, and the input voltage (first voltage The change of) has no effect on the output voltage.
  • the first-stage voltage conversion circuit 21 may also be an open-loop controlled step-down conversion, and the output voltage (second voltage) relative to the input voltage (first voltage) may be implemented according to a fixed transformation ratio. Not limited.
  • the input power of the first-stage voltage conversion circuit 21 may be of various types and a wide range of voltage ranges, for example, a single battery with a voltage range of 2.8V-4.5V, or three batteries connected in series, whose voltage The range may be 8.4V-13.5V, or a fixed input provided by the upper-level system power supply, etc., which is not limited in the embodiment of the present application.
  • the above-mentioned second-stage voltage conversion circuit 22 may adopt the step-down circuit shown in FIG. 4.
  • the second-level voltage conversion circuit 22 includes: a first inductor L1, a first capacitor C1, a first switch Q1, and a second switch Q2.
  • the first terminal (a) of the first switch Q1 is the first The input terminal Vin of the secondary voltage conversion circuit 22, the second terminal (b) of the first switch Q1 is connected to the first terminal of the first inductor L1 and the first terminal (a) of the second switch Q2, the control of the first switch Q1 Terminal (c) is used to input the first control signal; the second terminal of the first inductor L1 is the output terminal Vout of the second-level voltage conversion circuit 22, and the second terminal of the first inductor L1 is connected to the first capacitor C1. Terminal, the second terminal of the first capacitor C1 and the second terminal (b) of the second switch Q2 are grounded; the control terminal (c) of the second switch Q2 is used to input the second control signal.
  • the switching frequency of the first switch Q1 and the second switch Q2 in the second-stage voltage conversion circuit 22 may be greater than or equal to 30 MHz.
  • the high switching frequency in this application can not only meet the transient performance of load jump, and make the circuit more integrated; but for the same inductance, the higher the switching frequency High, the shorter the on-time of the switch tube, the smaller the ripple current in the circuit, so the loss of the circuit will be smaller.
  • the first switch Q1 in the second-stage voltage conversion circuit 22 when the first switch Q1 in the second-stage voltage conversion circuit 22 is turned on, the second switch Q2 is turned off, and when the second switch Q2 is turned on, the first switch Q1 is turned off.
  • the first switch Q1 if the first switch Q1 is turned on when the first control signal is at a high level, and the second switch Q2 is turned off when the second control signal is at a low level, the first control signal and the second control signal can be a pair Reverse pulse signal.
  • the first switch Q1 When the first switch Q1 is turned on, the energy storage first inductor L1 is magnetized, and the current flowing through the first inductor L1 increases linearly, while charging the first capacitor C1 to provide energy to the load R.
  • the equivalent circuit is shown in the figure As shown in (a) in 5; in this case, the first inductor L1 and the load R are connected in series to the input terminal Vin, and the output voltage Vout is the voltage across the load. Since the first inductor L1 and the load R are divided in series, the output voltage Vout Must be less than the input voltage Vin.
  • the first switch Q1 When the first switch Q1 is turned off, the energy storage first inductor L1 is discharged through the second switch Q2, and the current of the first inductor L1 decreases linearly.
  • first switch Q1 and second switch Q2 may be Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET).
  • MOSFET Metal-Oxide-Semiconductor Field Effect Transistor
  • the first switch Q1 and the second switch Q2 may both be NMOS transistors, or the first switch Q1 and the second switch Q2 may also be PMOS transistors, or the first switch Q1 and the second switch Q2 may also be One is a PMOS transistor and the other is an NMOS transistor, which is not limited in the embodiment of the present application.
  • R in FIG. 4 represents the load of the wireless terminal device. In practical applications, the load of the wireless terminal device may be a circuit module with a specific function. The embodiment of the present application does not limit the specific form of the load of the wireless terminal device. Only R is used as an example.
  • the embodiment of the application provides an inductor.
  • the switching frequency of the first switch and the second switch is greater than or equal to 30Mhz
  • the inductance density is greater than or equal to 10 nH/mm 2
  • the inductance density is greater than or It is equal to 40nH/mm 3
  • the DC impedance of the inductor's coil is less than or equal to 30m ⁇ .
  • the inductance per unit area is greater than or equal to 10 nH
  • the inductance per unit volume is greater than or equal to 40 nH. That is, the inductance per unit area and unit volume of the first inductor has been greatly improved compared to the inductance in the prior art. Therefore, when the inductance is the same, the area and volume of the first inductor are both larger. small. Therefore, the second-stage voltage conversion circuit 22 using the first inductor L1 has a smaller footprint and a smaller volume, and the circuit has a higher degree of integration.
  • the first inductor has a larger inductance when the first switch and the second switch work at high frequencies, so the ripple circuit in the circuit is small, and the DC impedance of the inductor is also small, so the loss of the inductor is small, The power supply efficiency of the second-stage voltage conversion circuit is higher.
  • the thin film inductor 01 includes at least one magnetic core 10 and A conductor 20 in a magnetic core 10.
  • Each magnetic core 10 includes a first magnetic film 101 and a second magnetic film 102 disposed oppositely.
  • the aforementioned conductor 20 is located in the containing cavity 21.
  • the thin film inductor 01 also includes an insulating spacer film 30. The insulating spacer film 30 is disposed on both sides of the conductor 20 and located in the gap between the first magnetic film 101 and the second magnetic film 102.
  • the lower surface and the upper surface of the insulating spacer film 30 are in contact with the first magnetic film 101 and the second magnetic film 102, respectively.
  • the above-mentioned first magnetic film 101 and second magnetic film 102 each include a multilayer magnetic sub-film 120 and a multilayer insulating sub-film 121.
  • the magnetic sub-film 120 and the insulator sub-film 121 in the first magnetic film 101 are alternately arranged.
  • the magnetic sub-film 120 and the insulator sub-film 121 in the second magnetic film 102 are alternately arranged.
  • FIG. 8 it is a schematic diagram of the inclined surface of the first magnetic film 101 in contact with the insulating spacer film 30.
  • the surface of the first magnetic film 101 in contact with the insulating spacer film 30 can expose the first magnetic film 101 The multilayer magnetic sub-film 120 and the multilayer insulating sub-film 121. And/or, the surface of the second magnetic film 102 in contact with the insulating spacer film 30 exposes the multilayer magnetic sub-film 120 and the multilayer insulating sub-film 121 in the second magnetic film 102.
  • the eddy current at the insulating spacer film can be on the surface where the first magnetic film contacts the insulating spacer film, and/or the surface where the second magnetic film contacts the insulating spacer film , Intersect with the exposed multilayer magnetic sub-film and multilayer insulator sub-film.
  • the eddy current at the insulating spacer film is divided into a plurality of sub-eddy currents by each layer of magnetic sub-film at the position where the plane where the eddy current is located intersects with each layer of magnetic sub-film, and each sub-eddy current enters a layer of magnetic sub-film.
  • each sub-eddy current can be confined in a layer of magnetic sub-film, so as to reduce the eddy current loss. Therefore, after the second-level voltage conversion circuit 22 adopts the thin film inductor, the second-level voltage conversion circuit 22 can be more integrated, and when the switches in the second-level voltage conversion circuit 22 work at high frequencies, As a result, the impedance of the first inductor in the second-stage voltage conversion circuit 22 is smaller, and the loss is lower.
  • the second-level voltage conversion circuit 22 adopts the step-down circuit shown in FIG. 4, which occupies a small board area and has a high degree of integration. It is relatively high, and when the switching frequency of the first switch and the second switch is greater than or equal to 30Mhz, the loss of the circuit is ensured to be low, and the power supply efficiency of the second-stage voltage conversion circuit 22 is improved.
  • the above-mentioned second-stage voltage conversion circuit 22 may adopt the step-down circuit shown in FIG. 9.
  • the step-down circuit includes: a second inductor L2, a second capacitor C2, a third switch Q3, a fourth switch Q4, a fifth switch Q5, and a sixth switch Q6.
  • the first terminal (a) of the third switch Q3 is the input terminal of the second-stage voltage conversion circuit 22
  • the first terminal (a) of the third switch Q3 is connected to the output terminal of the first-stage voltage conversion circuit 21, and the third switch Q3
  • the second terminal (b) of the fourth switch Q4 is connected to the first terminal (a), and the control terminal (c) of the third switch Q3 is used to input a third control signal.
  • the second terminal (b) of the fourth switch Q4 is connected to the first terminal (a) of the second inductor L2 and the first terminal (a) of the fifth switch Q5, and the control terminal (c) of the fourth switch Q4 is used to input the first bias The voltage V bias1 .
  • the second terminal (b) of the fifth switch Q5 is connected to the first terminal (a) of the sixth switch Q6, and the control terminal (c) of the fifth switch Q5 is used to input the second bias voltage V bias2 .
  • the second terminal of the second inductor L2 is the output terminal of the second-stage voltage conversion circuit 22, and the second terminal of the second inductor L2 is connected to the first terminal of the second capacitor C2.
  • the second end of the second capacitor C2 and the second end (b) of the sixth switch Q6 are grounded.
  • the control terminal (c) of the sixth switch Q6 is used to input the fourth control signal.
  • the first bias voltage V bias1 and the second bias voltage V bias2 may be preset bias voltages, so that the gates of the fourth switch Q4 and the fifth switch Q5 are maintained at a fixed voltage value.
  • the third switch Q3 and the fourth switch Q4 are PMOS transistors, and the fifth switch Q5 and the sixth switch Q6 are NMOS transistors.
  • the fourth switch Q4 is also turned on.
  • the fifth switch Q5 is turned on.
  • Both the fifth switch Q5 and the sixth switch Q6 are turned off; when the third switch Q3 is turned off, the fourth switch Q4 is also turned off. At this time, the fifth switch Q5 and the sixth switch Q6 are both turned on.
  • the above-mentioned third switch Q3, fourth switch Q4, fifth switch Q5, and sixth switch Q6 may be NMOS transistors or PMOS transistors.
  • the embodiment of the present application does not limit this, and only needs to satisfy When the third switch Q3 and the fourth switch Q4 are turned on, the fifth switch Q5 and the sixth switch Q6 are turned off; when the third switch Q3 and the fourth switch Q4 are turned off, the fifth switch Q5 and the sixth switch Q6 are turned on.
  • the third switch Q3 and the fourth switch Q4 may both be PMOS transistors, and the fifth switch Q5 and the sixth switch Q6 may be NMOS transistors.
  • R in FIG. 9 represents the load of the wireless terminal device. In practical applications, the load of the wireless terminal device may be a circuit module with a specific function. The embodiment of the present application does not limit the specific form of the load of the wireless terminal device. Only R is used as an example.
  • the second inductor in the circuit can be the inductor shown in FIGS. 6-8, so that the first switch and the second switch
  • the switching frequency is greater than or equal to 30Mhz, it is ensured that the area and volume of the inductor are small, the loss of the inductor is low, and the power supply efficiency of the second-stage voltage conversion circuit 22 is high.
  • the step-down circuit of FIG. 4 uses two switching tubes, and the step-down circuit of FIG. 9 uses four switching tubes, the second-stage voltage conversion circuit 22 uses the step-down circuit shown in FIG. 4, Compared with the step-down circuit shown in FIG. 9, the output voltage of the first-stage voltage conversion circuit 21 is lower and the conversion efficiency is higher. Moreover, the number of switching tubes required for the step-down circuit shown in FIG. 4 is less, so the integration level is higher.
  • the second-stage voltage conversion circuit 22 in the power supply circuit 20 can be integrated with the load.
  • the second-level voltage conversion circuit 22 may be integrated with a system-on-chip (SoC) to supply power to the system-on-chip.
  • SoC system-on-chip
  • the system-on-chip may include CPU, GPU, AI processor and memory.
  • the first-level voltage conversion circuit 21 and the second-level voltage conversion circuit 22 may be different chips.
  • the first chip includes the first-level voltage conversion circuit 21, and the second chip includes the second-level voltage conversion circuit 22, and the second chip may be a processor chip integrated with the second-level voltage conversion circuit.
  • multiple second-stage voltage conversion circuits 22 may be used for different loads (for example, CPU, GPU). , AI processor and memory) power supply.
  • the second-level voltage conversion circuit 22 provided by the present application is a high-frequency switching circuit with a small area and volume. Therefore, the second-level voltage conversion circuit 22 can be integrated with the load it supplies, so that the integration of the power supply circuit is improved. High, greater power density.
  • the first-level voltage conversion circuit 21 in the power supply circuit 20 may be integrated with the second-level voltage conversion circuit 22 in an integrated circuit (IC).
  • IC integrated circuit
  • the processor chip of the network device can adopt advanced CMOS processes such as 5nm, 7nm, etc., its power supply voltage can be reduced to about 0.6V, and the low-voltage bus architecture (0.6V-1.3V voltage bus architecture of the embodiment of the application) ), can effectively improve the conversion efficiency of the circuit, and the power supply efficiency is high. Moreover, by combining high-frequency switching technology, the area and volume of the power supply solution can be further reduced, and the power density has been greatly improved compared with the prior art.
  • the power supply circuit provided by the embodiment of the application supplies power to the load through a two-stage voltage conversion circuit.
  • the first-stage voltage conversion circuit can convert the power supply voltage into an output voltage of about 1.1V (0.6V-1.3V), which is used as The input of the second-level voltage conversion circuit and the high-frequency second-level voltage conversion circuit step down to supply power to the load, which can improve the conversion efficiency of the second-level voltage conversion circuit when the supply voltage of the load is low. Since the second-stage voltage conversion circuit 22 is a high-frequency switching circuit, its operating frequency is much higher than that of the traditional power supply circuit, so it can meet the transient performance requirements of load jump while greatly reducing the power supply circuit's footprint area.
  • the present application can design the peak power of the first-stage voltage conversion circuit 21 to be less than all the one or more second-stage voltage converter circuits connected to it.
  • the sum of the peak power of the first-level voltage conversion circuit 22 can avoid circuit over-design, further reduce the board area of the power supply circuit, and increase the power density of the power supply circuit.
  • the embodiment of the present application also provides an integrated circuit system, the integrated circuit system includes a first chip and a second chip, the first chip includes the above-mentioned first-level voltage conversion circuit 21, and the second chip includes the above-mentioned second-level voltage conversion Circuit 22.
  • the second chip in the integrated circuit system may be a processor chip, and the first chip is a power chip that provides power to the processor chip.
  • the second chip may be a processor chip integrated with the second-level voltage conversion circuit 22, and the first-level voltage conversion circuit 21 of the first chip may supply power to the second chip. It is understandable that for the relevant description of the first-stage voltage conversion circuit 21 and the second-stage voltage conversion circuit 22, reference may be made to the content in the above-mentioned embodiment, which will not be repeated here.
  • the embodiment of the present application also provides a power supply control method, which is applied to the power supply system shown in FIG. 13, and the power supply system includes the power supply circuit 20 shown in FIG. 7, a main controller connected to the first-stage voltage conversion circuit 21, and The first slave controller connected to the second-stage voltage conversion circuit 22 and the second slave controller connected to the load are connected by a control bus between the master controller, the first slave controller and the second slave controller.
  • the power supply control method may include steps S1401-S1403.
  • the second slave controller Before the load starts the service, the second slave controller sends power request information to the master controller.
  • the power request information is used to request the available power of the first-stage voltage conversion circuit 21.
  • the available power is the maximum output power of the first-stage voltage conversion circuit minus the sum of the current output power of all second-stage voltage conversion circuits 22 connected to the first-stage voltage conversion circuit 21.
  • the maximum output power of the first-stage voltage conversion circuit can be preset.
  • the second-stage voltage conversion circuit 22 for supplying power to the load connected to the second slave controller is connected to the first-stage voltage conversion circuit 21. Since the peak power of the first-stage voltage conversion circuit 21 in the embodiment of the present application is less than the sum of the peak powers of all the second-stage voltage conversion circuits 22 connected to it, the second-stage voltage conversion circuit 22 is changing from the first-stage voltage Before the conversion circuit 21 draws current to supply power to the load, it may first request the available power of the first-stage voltage conversion circuit 21.
  • the second slave controller receives the power response message sent by the master controller.
  • the power response message carries the available power of the first-stage voltage conversion circuit 21.
  • step S1403 may be executed.
  • the second slave controller waits for the first time period, and then sends the power request information to the master controller again.
  • the available power of the first-stage voltage conversion circuit 21 when the available power of the first-stage voltage conversion circuit 21 is not enough to support the start of the load, it may wait for the first period of time before sending the power request information to the main controller again until the available power of the first-stage voltage conversion circuit 21 It is greater than or equal to the power required to start the load, and then start the load.
  • the maximum power limitation mechanism of steps S1401-S1403 can be used to stagger multiple peak services, thereby reducing the energy lost in the internal resistance of the power supply and improving the efficiency of the power supply system.
  • the embodiment of the present application also provides a power supply control method. As shown in FIG. 15, after the above steps S1401-S1403, the method further includes steps S1404-S1405. S1401-S1403 are not shown in FIG.
  • the master controller obtains the current output power of the second-stage voltage conversion circuit from the first slave controller.
  • the master controller may obtain the current output power of the second-stage voltage conversion circuit 22 connected to each first slave controller from the first slave controller.
  • the main controller sends an alarm to the operating system information.
  • the maximum output power of the first-stage voltage conversion circuit 21 is greater than or equal to the sum of the output powers of all second-stage voltage conversion circuits 22 connected to it.
  • the sum of the current output power of one or more second-level voltage conversion circuits 22 connected to the first-level voltage conversion circuit 21 may be greater than the maximum of the first-level voltage conversion circuit 21.
  • the main controller sends an alarm message to the operating system, and the operating system can use a preset power management strategy to deal with the situation where the power exceeds the abnormality.
  • the power supply control method provided by the embodiments of the present application can stagger multiple peak services by limiting the maximum power mechanism, reduce the energy lost in the internal resistance of the power supply, and improve the efficiency of the power supply system. And when the sum of the output power of the plurality of second-stage voltage conversion circuits 22 connected to the first-stage voltage conversion circuit 21 is higher than the maximum output power of the first-stage voltage conversion circuit 21, an alarm message can be sent.
  • the embodiment of the present application also provides a power supply control method, which is applied to the power supply system shown in FIG. 13, and the power supply system further includes a delay circuit. As shown in Fig. 16, the power supply control method further includes steps S1601-S1605.
  • the main controller determines the first reference delay time corresponding to each first-level voltage conversion circuit.
  • the first reference delay time is the delay time corresponding to each first-stage voltage conversion circuit 21 when the ripple amplitude of the first voltage is the smallest. It is understandable that the first reference delay time may be obtained according to an algorithm obtained through training, and the embodiment of the present application does not limit the specific method for obtaining the first reference delay time.
  • the switch tubes of multiple first-stage voltage conversion circuits 21 are turned on at the same time, a large transient current will be generated, resulting in a large voltage ripple of the power supply. Therefore, the power supply voltage (first voltage When the ripple amplitude of) is the smallest, the delay time corresponding to each first-stage voltage conversion circuit 21 causes the switching tubes of the multiple first-stage voltage conversion circuits 21 to be out of phase (staggered to conduct), thereby reducing the voltage ripple.
  • the algorithm obtained by the above training may include: the main controller configures the delay time for the switch tube in each first-stage voltage conversion circuit 21 to close or open according to the system reference clock and the delay circuit, and determine the ripple of the first voltage.
  • the delay time corresponding to the first-stage voltage conversion circuit 21 is the first reference delay time.
  • the foregoing delay circuit may be a Delay Lock Loop or a module with similar functions, and a delay line may be configured in each second-stage voltage conversion circuit 22.
  • the main controller adjusts the conduction time of each first-stage voltage conversion circuit.
  • each first-stage voltage conversion circuit can be adjusted according to the first reference delay time determined in step S1601, so that the switch between the multiple first-stage voltage conversion circuits 21 included in the power supply system
  • the tube conduction time is staggered to reduce the power supply voltage ripple. For example, when multiple loads are started, if the second-level voltage conversion circuit 22 that supplies power to the multiple load modules is connected to the multiple first-level voltage conversion circuits 21, the multiple first-level voltage conversion circuits 21 can be connected according to the first reference delay time.
  • the stage voltage conversion circuit 21 staggers the conduction time of the switch tubes to reduce the power supply voltage ripple.
  • the main controller determines the second reference delay time corresponding to each second-level voltage conversion circuit connected to the first-level voltage conversion circuit.
  • the second reference delay time is the delay time corresponding to each second-stage voltage conversion circuit 22 when the ripple amplitude of the second voltage is the smallest.
  • the first-stage voltage conversion circuit supplies power to multiple second-stage voltage conversion circuits, that is, when the input terminals of the multiple second-stage voltage conversion circuits 22 are connected to the output terminals of the first-stage voltage conversion circuit 21, If multiple switch tubes of the second-stage voltage conversion circuit 22 are turned on at the same time, a large transient current will be generated, resulting in a large voltage ripple in the output voltage of the first-stage voltage conversion circuit 21.
  • a training algorithm can be used to determine when the ripple amplitude of the output voltage (second voltage) of the first-stage voltage conversion circuit 21 is the smallest, and the delay time corresponding to each second-stage voltage conversion circuit 22 is such that multiple second-stage The switch tubes of the voltage conversion circuit 22 are out of phase (staggered to conduct), thereby reducing voltage ripple.
  • the main controller can configure the switch on or off delay time of each second-stage voltage conversion circuit 22 according to the system reference clock and delay circuit, and determine that when the ripple amplitude of the second voltage is the smallest, the second The delay time corresponding to the stage voltage conversion circuit 22 is the second reference delay time.
  • the main controller adjusts the conduction time of each second-stage voltage conversion circuit.
  • the conduction time of multiple second-level voltage conversion circuits connected to one first-level voltage conversion circuit can be adjusted according to the second reference delay time determined in step S1603, so that the multiple second-level voltage conversion circuits
  • the switch tubes of the circuit 22 are turned on at staggered times, reducing the voltage ripple of the output voltage of the first-stage voltage conversion circuit 21, and improving the power supply efficiency of the power supply system.
  • the second-level voltage conversion circuit 22 may be used according to the second reference delay time.
  • the stage voltage conversion circuit 22 has a staggered turn-on time of the switches, reducing the power supply voltage ripple.
  • the main controller increases the output voltage of the first-stage voltage conversion circuit; if the load is working in a low-power state, the main controller reduces the output voltage of the first-stage voltage conversion circuit The output voltage.
  • the output voltage of the first-stage voltage conversion circuit 21 can be reduced to improve the efficiency of the second-stage voltage conversion circuit 22, and the power supply efficiency is relatively high.
  • the output voltage of the first-stage voltage conversion circuit 21 can be increased to allow the load to run high-performance services normally, so that the output voltage of the first conversion circuit can be adjusted when the load is running different services , To meet business needs in different situations.
  • the power supply control method provided by the embodiment of the present application can stagger the conduction time of the switch tubes of multiple first-level voltage conversion circuits 21, and connect multiple second-level voltage conversion circuits of the same first-level voltage conversion circuit 21
  • the switch tube 22 turns on time staggered, thereby reducing the power supply voltage ripple.
  • the output voltage of the first-stage voltage conversion circuit 21 is increased, and in a low power consumption state, the output voltage of the first-stage voltage conversion circuit 21 is reduced, so that the power supply efficiency of the power supply system is higher.
  • An embodiment of the present application also provides a terminal device, which includes the power supply circuit 20 described above.
  • the terminal device may further include a power management chip 1701, and a power supply bus or power supply network connected to the power management chip 1701.
  • the power management chip 1701 can communicate to the rest of the terminal device through the power bus, such as radio frequency module, memory, hard disk, camera and imaging processing module, and input /Output (I/O) interface, human-computer interaction device (human interactive device), etc. provide working voltage.
  • I/O input /Output
  • the foregoing terminal device further includes a processor 1702 and a data bus (Data bus) connected to the processor 1702.
  • the processor 1702 includes a power supply circuit 20.
  • the processor 1702 can provide operating voltages to the remaining components in the terminal device, such as the aforementioned radio frequency transceiver, memory, hard disk, camera and image processor, input/output interface, human-computer interaction equipment, etc., through the data bus.
  • the processor 1702 may be any one of SoC, CPU, and GPU.
  • the foregoing terminal device has the same technical effect as the power supply circuit 20 provided in the foregoing embodiment, and will not be repeated here.
  • the embodiment of the present application also provides a computer storage medium in which computer program codes are stored.
  • the processor is caused to execute S1401-S1403 in FIG. 14 or FIG. 15 S1404-S1405 in Figure 16, or S1601-S1605 in Figure 16.
  • the processor may be a CPU, and the master controller and the slave controller may be other processors, digital logic modules, or a certain functional module of the CPU, which is not limited in the embodiment of the present application.
  • the terminal device includes a hardware structure and/or software module corresponding to each function.
  • the terminal device includes a hardware structure and/or software module corresponding to each function.
  • the steps of the method or algorithm described in conjunction with the disclosure of this application can be implemented in a hardware manner, or implemented in a manner in which a processor executes software instructions.
  • Software instructions can be composed of corresponding software modules, which can be stored in random access memory (Random Access Memory, RAM), flash memory, erasable programmable read-only memory (Erasable Programmable ROM, EPROM), and electrically erasable Programming read-only memory (Electrically EPROM, EEPROM), register, hard disk, mobile hard disk, CD-ROM or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor, so that the processor can read information from the storage medium and can write information to the storage medium.
  • the storage medium may also be an integral part of the processor.
  • the processor and the storage medium may be located in the ASIC.
  • the ASIC may be located in the core network interface device.
  • the processor and the storage medium may also exist as discrete components in the core network interface device.
  • the functions described in this application can be implemented by hardware, software, firmware or any combination thereof. When implemented by software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on the computer-readable medium.
  • the computer-readable medium includes a computer storage medium and a communication medium, where the communication medium includes any medium that facilitates the transfer of a computer program from one place to another.
  • the storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer.

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Abstract

本申请实施例公开了一种供电电路和供电控制方法，涉及电路技术领域，解决了现有技术电源占板面积较大的问题。具体方案为：供电电路包括一个或多个第一级电压转换电路和一个或多个第二级电压转换电路；第一级电压转换电路的输入端被耦合至电源；第一级电压转换电路用于将输入端接收到的第一电压转换为第二电压，第二电压小于第一电压，第二电压大于或等于0.6V，且小于或等于1.3V；第二级电压转换电路的输入端被耦合至第一级电压转换电路的输出端，第二级电压转换电路用于将第二电压转换为第三电压，并将第三电压提供给负载，第三电压小于第二电压；第二级电压转换电路的开关频率大于或等于30Mhz。

Description

一种供电电路和供电控制方法 技术领域
本申请实施例涉及电路技术领域，尤其涉及一种供电电路和供电控制方法。
背景技术
目前系统(例如，智能手机)的供电架构包括多个电压转换器(buck converter)，通过该多个电压转换器可以将电池或给定的输入电压转换为需要的电压，为负载模块供电。
如图1所示，电压转换器可以在输入电压(电池)和负载模块(例如，中央处理器(Central Processing Unit，CPU)物理核和图形处理器(Graphics Processing Unit，GPU)物理核等)间完成点到点的电压转换和供电。为了精细化电源管理，提高系统能效，电压转换器的路数有越来越多的趋势，同时每一路电压转换器电路需要按负载的最大峰值电流设计(即使典型工作场景的电流远小于峰值电流)。由于电源的印制电路板(Printed Circuit Board，PCB)面积与最大电流成正比，而随着系统性能提升的需求，峰值电流和电源路数都会增长，电源PCB方案面积也会不断加大，而系统(如智能手机)的面积通常是固定或受限的，因此需要的电源占板面积不断增加会对系统方案造成巨大挑战。
发明内容
本申请实施例提供一种供电电路和供电控制方法，能够减小整体电源方案的占板面积，功率密度较高，提高了系统的供电效率。
为达到上述目的，本申请实施例采用如下技术方案：
本申请实施例的第一方面，提供一种供电电路，该供电电路包括：一个或多个第一级电压转换电路和一个或多个第二级电压转换电路；其中，该第一级电压转换电路的输入端被耦合至电源；该第一级电压转换电路用于将其输入端接收到的第一电压转换为第二电压，并从该第一级电压转换电路的输出端输出，该第二电压小于上述第一电压，第二电压大于或等于0.6V，且小于或等于1.3V；该第二级电压转换电路的输入端被耦合至上述第一级电压转换电路的输出端，该第二级电压转换电路用于将上述第二电压转换为第三电压，并将该第三电压提供给负载，第三电压小于第二电压；第二级电压转换电路的开关频率大于或等于30Mhz。基于本方案，在由第一级电压转换电路和第二级电压转换电路组成的供电电路中，第二级电压转换电路只需要将0.6V-1.3V这样的低压范围内的电压进行进一步转化，而且还使用了大于30MHz的高频开关，这极大地减小了供电电路对空间的需求。甚至，在多个第二级电压转换电路能够共享第一级电压转换电路的情况下，本发明实施例的供电电路的空间需求被进一步的缩小了。因此，供电电路的占板面积被大大降低，功率密度得到大幅提升，供电效率得到提高。
结合第一方面，在一种可能的实现方式中，上述一个第一级电压转换电路为一个或多个第二级电压转换电路供电时，每个第二级电压转换电路的输入端连接该第一级 电压转换电路的输出端。基于本方案，每个第一级电压转换电路能够为一个或多个第二级电压转换电路供电，然后第二级电压转换电路再向负载供电，用这种方式，本发明实施例提供的供电电路就形成了一种树型结构，通过不同的第一级电压转换电路和第二级电压转换电路的组合，能够实现对多种负载的供电的精细化管理，提高供电效率。
结合第一方面和上述可能的实现方式，在另一种可能的实现方式中，上述第二级电压转换电路包括电感、电容、第一开关和第二开关，第一开关的第一端连接第一级电压转换电路的输出端，第一开关的第二端连接电感的第一端和第二开关的第一端，第一开关的控制端用于输入第一控制信号；电感的第二端为第二级电压转换电路的输出端，电感的第二端连接电容的第一端，电容的第二端和第二开关的第二端接地；第二开关的控制端用于输入第二控制信号；其中，第一开关和第二开关的开关频率大于或等于30Mhz。基于本方案，通过两个开关管工作在高频，能够在满足负载跳变的瞬态性能要求的同时，大大减小供电电路的占板面积。
结合第一方面和上述可能的实现方式，在另一种可能的实现方式中，当第一开关和第二开关的开关频率大于或等于30Mhz时，上述电感的电感量密度大于或等于10nH/mm 2，且电感的电感量密度大于或等于40nH/mm 3，且电感的线圈直流阻抗小于或等于30mΩ。可以理解的，该第一电感在电路工作在高频时，单位面积(每平方毫米)的电感量大于或等于10nH，且单位体积(每立方毫米)的电感量大于或等于40nH。即该第一电感在单位面积和单位体积的电感量相对于现有技术中的电感有了很大的提升，因此在电感量相同的情况下，该第一电感的占板面积和体积均较小。基于本方案，上述规格下的电感的占板面积和体积较小，从而使得供电电路的集成度更高。而且当电感工作在高频时，第二级电压转换电路的损耗降低，这提高了第二级电压转换电路的供电效率。
结合第一方面和上述可能的实现方式，在另一种可能的实现方式中，上述电感为薄膜电感，该薄膜电感包括：磁芯，包括第一磁膜和第二磁膜；第一磁膜与第二磁膜之间具有容纳腔；导体，位于容纳腔内；绝缘间隔膜，设置于导体两侧，且位于第一磁膜和第二磁膜之间；绝缘间隔膜与第一磁膜和第二磁膜相接触；第一磁膜和第二磁膜均包括多层磁性子膜和多层绝缘子膜；第一磁膜中，磁性子膜和绝缘子膜交替设置；第二磁膜中，磁性子膜和绝缘子膜交替设置；第一磁膜与绝缘间隔膜相接触的表面，暴露出第一磁膜中多层磁性子膜和多层绝缘子膜；和/或，第二磁膜与绝缘间隔膜相接触的表面，暴露出第二磁膜中多层磁性子膜和多层绝缘子膜。基于本方案，使得电路的集成度更高，而且在第二级电压转换电路工作在高频时，使得高频开关电路(第二级电压转换电路)中的第一电感的阻抗较小，损耗较低。
结合第一方面和上述可能的实现方式，在另一种可能的实现方式中，上述第二级电压转换电路包括电感、电容、第三开关、第四开关、第五开关和第六开关，第三开关的第一端连接第一级电压转换电路的输出端，第三开关的第二端连接第四开关的第一端，第三开关的控制端用于输入第三控制信号；第四开关的第二端连接电感的第一端和所述第五开关的第一端，第四开关的控制端用于输入第一偏置电压；第五开关的第二端连接第六开关的第一端，第五开关的控制端用于输入第二偏置电压；电感的第 二端为第二级电压转换电路的输出端，电感的第二端连接电容的第一端，电容的第二端和第六开关的第二端接地；第六开关的控制端用于输入第四控制信号。基于本方案，相对于现有技术能够减小供电电路的占板面积，功率密度有了大幅提升，供电效率较高。
结合第一方面和上述可能的实现方式，在另一种可能的实现方式中，第一级电压转换电路的峰值功率小于所有与其连接的一个或多个第二级电压转换电路的峰值功率之和。基于本方案，能够避免第一级电压转换电路过设计，且进一步减小该第一级供电电路的占板面积，提高供电电路的功率密度。
结合第一方面和上述可能的实现方式，在另一种可能的实现方式中，上述第一级电压转换电路为开关电容电压转换器电路、转换比可变的开关电容电压转换器电路、降压DC-DC转换器电路、多电平降压转换器电路、变压器隔离的降压转换器电路、混合的开关电感和开关电容结合的电压转换器电路，或者谐振开关电容电压转换器电路。基于本方案，该第一级电压转换电路的转换效率较高，进一步提高供电效率。
结合第一方面和上述可能的实现方式，在另一种可能的实现方式中，上述第二级电压转换电路与上述负载集成在一起。基于本方案，供电电路的集成度更高，功率密度更大。
结合第一方面和上述可能的实现方式，在另一种可能的实现方式中，当上述第一开关导通时，上述第二开关关断，且，当上述第二开关导通时，上述第一开关关断。基于本方案，能够通过控制第一开关和第二开关的通断，实现第二级电压转换电路的降压转换。
本申请实施例的第二方面，提供一种供电控制方法，应用于电源系统，该电源系统包括上述第一方面的任一种实现方式中的供电电路、与上述第一级电压转换电路连接的主控制器、与上述第二级电压转换电路连接的第一从控制器，以及与上述负载连接的第二从控制器，主控制器、第一从控制器和第二从控制器之间通过控制总线连接，该供电控制方法包括：当负载启动时，第二从控制器向主控制器发送功率请求信息，该功率请求信息用于请求第一级电压转换电路的可用功率；第二从控制器接收主控制器发送的功率响应消息，该功率响应消息中携带第一级电压转换电路的可用功率；若第一级电压转换电路的可用功率小于负载启动所需功率，第二从控制器等待第一时长后，再次向主控制器发送所述功率请求信息。基于本方案，通过限制最大功率机制，将多个峰值业务错开，从而减小电源内阻上损失的能量，提高了电源系统的效率。
结合第二方面，在一种可能的实现方式中，上述第一级电压转换电路的可用功率为第一级电压转换电路的最大输出功率减去已用功率，该已用功率为与第一级电压转换电路连接的一个或多个第二级电压转换电路的当前输出功率之和。示例性的，该第一级电压转换电路的最大输出功率可以预设值。基于本方案，可以根据第一级电压转换电路的最大输出功率，以及第二级电压转换电路的当前输出功率之和，确定第一级电压转换电路的可用功率。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，若上述供电电路包括多个第一级电压转换电路，上述方法还包括：主控制器确定每个第一级电压转换电路对应的第一基准延迟时间；该第一基准延迟时间为第一电压的纹波幅度最小 时，每个第一级电压转换电路对应的延迟时间；根据所述第一基准延迟时间，调整每个第一级电压转电路的导通时间。基于本方案，可以使得多个第一级电压转换电路的开关管错相(错开导通)，从而减小电压纹波。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，若上述第一级电压转换电路为多个第二级电压转换电路供电，上述方法还包括：主控制器确定与第一级电压转换电路连接的每个第二级电压转换电路对应的第二基准延迟时间；该第二基准延迟时间为所述第二电压的纹波幅度最小时，每个第二级电压转换电路对应的延迟时间；根据所述第二基准延迟时间，调整所述每个第二级电压转换电路的导通时间。基于本方案，使得多个第二级电压转换电路的开关管错相(错开导通)，从而减小电压纹波。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，上述电源系统还包括延迟电路，上述主控制器确定每个第一级电压转换电路对应的第一基准延迟时间，包括：主控制器根据系统参考时钟和延迟电路，配置每个第一级电压转换电路中开关闭合或断开的延迟时间，确定第一基准延迟时间。基于本方案，能够通过延迟电路确定基准延迟时间，使得电压的纹波最小。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，上述主控制器确定与第一级电压转换电路连接的每个第二级电压转换电路对应的第二基准延迟时间，包括：主控制器根据系统参考时钟和延迟电路，配置该每个第二级电压转换电路中开关闭合或断开的延迟时间，确定第二基准延迟时间。基于本方案，能够通过延迟电路确定基准延迟时间，使得电压的纹波最小。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，上述方法还包括：若负载启动高性能业务，主控制器增大第一级电压转换电路的输出电压；若负载工作在低功耗状态，主控制器减小第一级电压转换电路的输出电压。基于本方案，能够在负载运行不同业务时，对第一转换电路的输出电压进行调整，满足不同情况时的业务需求，提高供电效率。
结合第二方面和上述可能的实现方式，在另一种可能的实现方式中，上述方法还包括：主控制器从第一从控制器获取第二级电压转换电路的当前输出功率；若与第一级电压转换电路连接的一个或多个第二级电压转换电路的当前输出功率之和，大于第一级电压转换电路的最大输出功率，主控制器向操作系统发送告警信息。基于本方案，能够在功率超出的异常情况时，发送告警信息以处理该异常情况。
本申请实施例的第三方面，提供一种集成电路系统，其特征在于，该集成电路系统包括第一芯片和第二芯片，该第一芯片包括第一级电压转换电路，该第二芯片包括第二级电压转换电路；其中，该第一级电压转换电路的输入端被耦合至电源；该第一级电压转换电路用于将其输入端接收到的第一电压转换为第二电压，并从该第一级电压转换电路的输出端输出，该第二电压小于第一电压，该第二电压大于或等于0.6V，且小于或等于1.3V；上述第二级电压转换电路的输入端被耦合至上述第一级电压转换电路的输出端，该第二级电压转换电路用于将上述第二电压转换为第三电压，并将该第三电压提供给负载，该第三电压小于第二电压；该第二级电压转换电路的开关频率大于或等于30Mhz。基于本方案，可以通过第一芯片可以将电源电压降为0.6V-1.3V， 并将该0.6V-1.3V的电压作为第二芯片的输入电压，由于第二芯片中的第二级电压转换电路使用了大于30MHz的高频开关，可以极大地减小了第二芯片对空间的需求。而且，在第一级电压转换电路可以为多个第二级电压转换电路提供输入电压的情况下，本发明实施例的集成电路系统的空间需求被进一步的缩小了。因此，该集成电路系统的占板面积被大大降低，功率密度得到大幅提升，供电效率得到提高。
结合第三方面，在一种可能的实现方式中，上述第二芯片为处理器芯片，上述第一芯片为向该处理器芯片提供电力的电源芯片。基于本方案，可以将第二级电压转换电路集成在处理器芯片中，第一芯片可以为该处理器芯片提供电力。
本申请实施例的第四方面，提供一种计算机存储介质，所述计算机存储介质中存储有计算机程序代码，当所述计算机程序代码在处理器上运行时，使得所述处理器执行第二方面或第二方面的可能的实现方式中任一所述的供电控制方法。示例性的，该处理器可以为CPU，主控制器和从控制可以为其它处理器，数字逻辑模块，或者CPU中的某一个功能模块。
本申请实施例的第五方面，提供了一种计算机程序产品，该程序产品储存有上述处理器执行的计算机软件指令，该计算机软件指令包含用于执行上述方面所述方案的程序。
本申请实施例的第六方面，提供了一种装置，该装置以芯片的产品形态存在，该装置的结构中包括处理器和存储器，该存储器用于与处理器耦合，保存该装置必要的程序指令和数据，该处理器用于执行存储器中存储的程序指令，使得该装置执行上述方法中供电控制装置的功能。
本申请实施例的第七方面，提供一种终端，该终端包括处理器和上述第一方面或第一方面的可能的实现方式中任一所述的供电电路，处理器用于执行上述第二方面或第二方面的可能的实现方式中任一所述的供电控制方法。
附图说明
图1为现有技术提供的一种供电方案的示意图；
图2为本申请实施例提供的一种供电电路的结构示意图；
图3为本申请实施例提供的另一种供电电路的结构示意图；
图4为本申请实施例提供的一种第二级电压转换电路的电路图；
图5为本申请实施例提供的一种第二级电压转换电路的等效电路图；
图6为本申请实施例提供的一种薄膜电感的结构示意图；
图7为本申请实施例提供的一种薄膜电感的具体结构示意图一；
图8为本申请实施例提供的一种薄膜电感的具体结构示意图二；
图9为本申请实施例提供的另一种第二级电压转换电路的电路图；
图10为本申请实施例提供的另一种供电电路的结构示意图；
图11为本申请实施例提供的另一种供电电路的结构示意图；
图12为本申请实施例提供的另一种供电电路的结构示意图；
图13为本申请实施例提供的一种电源系统的结构示意图；
图14为本申请实施例提供的一种供电控制方法的流程示意图；
图15为本申请实施例提供的另一种供电控制方法的流程示意图；
图16为本申请实施例提供的另一种供电控制方法的流程示意图；
图17为本申请实施例提供的一种终端设备的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c或a-b-c，其中a、b和c可以是单个，也可以是多个。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
为了解决现有技术随着系统性能提升，电源占板面积较大的问题，本申请实施例提供一种供电电路，能够减小整体电源方案的占板面积，功率密度较高，提高了系统的供电效率。
本申请实施例还提供一种供电电路，该供电电路可以应用于终端设备中。该终端设备可以为手机、平板电脑、笔记本电脑、上网本等设备。本申请实施例中对于该供电电路应用的终端设备的具体形式不做特殊限制。
如图2所示，该供电电路20包括：一个或多个第一级电压转换电路21和一个或多个第二级电压转换电路22。第一级电压转换电路21的输入端被耦合至电源，第二级电压转换电路22的输入端被耦合至第一级电压转换电路21的输出端。
第一级电压转换电路21，用于将其输入端接收到的第一电压转换为第二电压，并从第一级电压转换电路21的输出端输出，该第二电压小于第一电压，该第二电压大于或等于0.6V，且小于或等于1.3V。
第二级电压转换电路22，用于将第二电压转换为第三电压，并将第三电压提供给负载，该第三电压小于第二电压。第二级电压转换电路22的开关频率大于或等于30Mhz。
以无线终端设备为例说明。在无线终端设备中的电源电压(在无线终端设备中通常为电池电压)通常为4.5V左右。本发明实施例的供电电路20采用两级电压转换电路，首先通过第一级电压转换电路21将电压初步降低到0.6V-1.3V之间。然后再通过第二级电压转换电路22再次降压。由于第二级电压转换电路22的输入电压仅在0.6V-1.3V之间，因此在无线终端设备中负载的供电电压较低时(例如，在无线终端的处理器芯片采用5nm、7nm等先进互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)制程，其供电电压可以降低到0.6V左右)，由于输入电压和输出电压的压差越小转换效率越高，因此，通过该第二级电压转换电路降压后，第二级电压转换电路22的转换效率较高。而且由于一个开关管的耐压值为1V左右，因此 通过第一级电压转换电路将输入电压降为1.1V左右的电压(0.6V-1.3V)后，第二级电压转换电路可以采用两个开关管实现降压，与采用四个开关管降压相比，由于开关数量减小，电路的集成度更高，开关损耗也大大降低。
示例性的，第二级电压转换电路22可以采用高频开关电路的设计，或者说具有更高的开关管工作频率，比如30Mhz。可以理解的，由于开关管的工作频率越低，开关管的损耗越小，效率越高，但可能不能满足负载跳变的瞬态性能，而且纹波电流较大，对电池的干扰影响越大。因此，考虑了效率和负载跳变的瞬态性能等因素后，本申请实施例中的第二级电压转换电路22中的开关管的频率可以大于或等于30Mhz。
可以理解的，采用低频开关电路(开关频率通常小于5Mhz)时，由于负载瞬态性能要求越高时，负载瞬态的电流变化越大，电路中需要更多的电容组件进行储能，那么电路的占板面积也将越大。而本申请通过第二级电压转换电路22采用高频开关电路的设计，能够满足负载跳变的瞬态性能要求，减少电容等储能元件的数量，因此电路的占板面积大大减小。故当第二级电压转换电路中的开关管工作频率高于现有技术中的低频开关电路中开关管的工作频率时，电路的功率密度较现有的低频开关电路有了显著的提升，集成度更高，占板面积大大减小。
示例性的，上述每个第一级电压转换电路21的输入端被耦合至电源。一个第一级电压转换电路21可以给一个或多个第二级电压转换电路22供电，每个第二级电压转换电路22的输入端连接该第一级电压转换电路21的输出端。例如，如图3所示，该供电电路20包括2个第一级电压转换电路21和2个第二级电压转换电路22，每个第二级电压转换电路22的输入端连接一个第一级电压转换电路21的输出端。本申请实施例对于第一级电压转换电路21和第二级电压转换电路22的具体数量并不进行限定，图3仅是示例性说明。实际应用中，可以根据负载的供电需求、负载位置等参数配置第一级电压转换电路21和第二级电压转换电路22的数量和连接方式。可以理解的，供电电路20输出的第三电压可以用于为图3中的中央处理器(central processing unit，CPU)、图形处理器(Graphics Processing Unit，GPU)、人工智能(Artificial Intelligence，AI)处理器、内存(memory)、固态硬盘(solid-state drive，SSD)和图像处理器(Image Processor)等负载供电。其中，该CPU、GPU和AI处理器可以为多核处理器。
示例性的，若第一级电压转换电路21给M个第二级电压转换电路22供电，M大于或等于1，即M个第二级电压转换电路22的输入端与该第一级电压转换电路21的输出端连接，该第一级电压转换电路21的峰值功率可以小于与其连接的M个第二级电压转换电路22的峰值功率之和。可以理解的，由于无线终端设备的所有负载不会同时工作在峰值状态，因此上述供电电路20中的第一级电压转换电路21的峰值功率可以小于与其连接的所有第二级电压转换电路22的峰值功率之和，从而能够避免第一级电压转换电路21过设计。而且由于峰值电流越大，电路中的电感的体积和面积越大，当输出电压一定时，峰值功率也越大，则电路的占板面积也会越大，即电路的占板面积与峰值功率成正比。因此，将第一级电压转换电路21的峰值功率设计为小于所有与其连接的第二级电压转换电路22的峰值功率之和，相比于现有技术中点对点的电压转换，并将每一路电压转换器电路按负载的最大峰值电流设计，能够减小电压转换电路的占板面积，进一步提高供电电路的功率密度。例如，以第二级电压转换电路的输出 电压为0.6V、第二级电压转换电路的峰值电流之和为100A为例，该第二级电压转换电路的峰值功率之和为60W，而实际应用中无线终端设备(例如，手机)的功率一般为3W-4W左右，因此第一级电压转换电路的峰值功率可以设计为小于与其连接的所有第二级电压转换电路的峰值功率之和即可。例如，该第一级电压转换电路21的峰值功率可以设计为与其连接的所有第二级电压转换电路22的峰值功率之和的20％。本申请实施例对于第一级电压转换电路的峰值功率的具体数值并不进行限定，在此仅是示例性说明。
示例性的，上述第一级电压转换电路21可以采用高效的直流变直流(Direct Current Direct Current，DCDC)电压转换器电路实现电压的转换。例如，开关电容电压转换器电路、转换比可变的开关电容电压转换器电路、降压DC-DC转换器电路、多电平降压转换器电路、变压器隔离的降压转换器电路、混合的开关电感和开关电容结合的电压转换器电路，或者谐振开关电容电压转换器电路等。本申请实施例对于第一级电压转换电路21的具体电路结构并不进行限定。
需要说明的是，第一级电压转换电路21可以为闭环控制的稳压整流电路，此时，第一级电压转换电路21的输出电压(第二电压)是恒定的，输入电压(第一电压)的变化对输出电压没有影响。或者，该第一级电压转换电路21也可以为开环控制的降压转换，输出电压(第二电压)相对输入电压(第一电压)可以按照固定变比实现，本申请实施例对此并不进行限定。
示例性的，第一级电压转换电路21的输入电源可以是多种类型和宽范围的电压范围，例如，电压范围可以为2.8V-4.5V的单电池，或者，串联的三节电池，其电压范围可以为8.4V-13.5V，或上一级系统电源提供的固定的输入等，本申请实施例对此并不进行限定。
一种实现方式中，上述第二级电压转换电路22可以采用图4所示的降压电路。如图4所示，该第二级电压转换电路22包括：第一电感L1、第一电容C1、第一开关Q1和第二开关Q2，第一开关Q1的第一端(a)为该第二级电压转换电路22的输入端Vin，第一开关Q1的第二端(b)连接第一电感L1的第一端和第二开关Q2的第一端(a)，第一开关Q1的控制端(c)用于输入第一控制信号；第一电感L1的第二端为该第二级电压转换电路22的输出端Vout，第一电感L1的第二端连接第一电容C1的第一端，第一电容C1的第二端和第二开关Q2的第二端(b)接地；第二开关Q2的控制端(c)用于输入第二控制信号。
示例性的，该第二级电压转换电路22中的第一开关Q1和第二开关Q2的开关频率可以大于或等于30Mhz。相比于现有技术中的开关频率通常小于5Mhz，本申请中的高开关频率不仅能够满足负载跳变的瞬态性能，使电路的集成度更高；而且对于同样的电感，由于开关频率越高，开关管的导通时间越短，电路中的纹波电流越小，因此电路的损耗也将越小。
示例性的，该第二级电压转换电路22中的第一开关Q1导通时，第二开关Q2关断，且，当第二开关Q2导通时，第一开关Q1关断。例如，若该第一开关Q1在第一控制信号为高电平时导通，第二开关Q2在第二控制信号为低电平时关断，该第一控制信号和第二控制信号可以采用一对反向的脉冲信号。当第一开关Q1导通时，储能 第一电感L1被充磁，流经第一电感L1的电流线性增加，同时给第一电容C1充电，给负载R提供能量，其等效电路如图5中的(a)所示；该情况下第一电感L1和负载R串联到输入端Vin，输出电压Vout为负载两端电压，由于第一电感L1和负载R串联分压，那么输出电压Vout必定小于输入电压Vin。当第一开关Q1关断时，储能第一电感L1通过第二开关Q2放电，第一电感L1电流线性减少，其等效电路如图5中的(b)所示；该情况下第一电感L1储存的能量向负载R释放，而第一电感L1的电压小于输入电压，因此负载R两端的输出电压也小于输入电压Vin。通过第一开关Q1和第二开关Q2的导通和关闭，使得输出电压Vout小于输入电压Vin。示例性的，可以通过控制第一开关Q1和第二开关Q2的导通和关闭的时间比，调整输出电压的大小。
需要说明的是，上述第一开关Q1和第二开关Q2可以为金属氧化物半导体场效应晶体管(Metal-Oxide-Semiconductor Field Effect Transistor，MOSFET)。例如，该第一开关Q1和第二开关Q2可以均为NMOS管，或者，第一开关Q1和第二开关Q2也可以为均为PMOS管，或者，第一开关Q1和第二开关Q2也可以一个为PMOS管，一个为NMOS管，本申请实施例对此并不仅限定。图4中的R表示无线终端设备的负载，实际应用中，无线终端设备的负载可以为一个具体功能的电路模块，本本申请实施例对于无线终端设备的负载的具体形式并不进行限定，在此仅以R进行示例性说明。
示例性的，为了实现第一开关和第二开关工作在高频(大于或等于30Mhz)时，第二级电压转换电路22中第一电感的占板面积和体积较小，并且第一电感的损耗较低，本申请实施例提供了一种电感，该电感在第一开关和第二开关的开关频率大于或等于30Mhz时，电感量密度大于或等于10nH/mm 2，且电感量密度大于或等于40nH/mm 3，且电感的线圈直流阻抗小于或等于30mΩ。可以理解的，该第一电感在电路工作在高频时，单位面积(每平方毫米)的电感量大于或等于10nH，且单位体积(每立方毫米)的电感量大于或等于40nH。即该第一电感在单位面积和单位体积的电感量相对于现有技术中的电感有了很大的提升，因此在电感量相同的情况下，该第一电感的占板面积和体积均较小。故采用了该第一电感L1的第二级电压转换电路22的占板面积和体积均较小，电路的集成度更高。而且该第一电感在第一开关和第二开关工作在高频时的电感量较大，因此电路中的纹波电路较小，而且电感的直流阻抗也较小，因此电感的损耗较小，使得第二级电压转换电路的供电效率较高。
一种实现方式中，为了实现上述第一电感的高集成度和低损耗，本申请实施例提供一种薄膜电感01，如图6所示，该薄膜电感01包括至少一个磁芯10和位于每个磁芯10内的导体20。每个磁芯10包括相对设置的第一磁膜101和第二磁膜102。第一磁膜101与第二磁膜102之间具有容纳腔21。上述导体20位于容纳腔21内。该薄膜电感01还包括绝缘间隔薄膜30。该绝缘间隔膜30设置于上述导体20两侧，且位于第一磁膜101与第二磁膜102之间的间隙(gap)内。上述绝缘间隔膜30的下表面、上表面分别与第一磁膜101和第二磁膜102相接触。如图7所示，上述第一磁膜101和第二磁膜102均包括多层磁性子膜120和多层绝缘子膜121。第一磁膜101中的磁性子膜120和绝缘子膜121交替设置。第二磁膜102中的磁性子膜120和绝缘子膜121交替设置。如图8所示，为第一磁膜101与绝缘间隔膜30相接触的倾斜表面的示意图，该第一磁膜101与绝缘间隔膜30相接触的表面，可以暴露出第一磁膜101中多层磁性 子膜120和多层绝缘子膜121。和/或，第二磁膜102与绝缘间隔膜30相接触的表面，暴露出第二磁膜102中多层磁性子膜120和多层绝缘子膜121。
结合图6-图8所示的薄膜电感，绝缘间隔膜处的涡流，能够在第一磁膜与绝缘间隔膜相接触的表面，和/或，第二磁膜与绝缘间隔膜相接触的表面，与暴露出的多层磁性子膜和多层绝缘子膜相交。从而使得绝缘间隔膜处的涡流，在该涡流所在的平面与各层磁性子膜相交的位置，被各层磁性子膜分隔成多个子涡流，且每个子涡流进入到一层磁性子膜中。从而使得每个子涡流能够被局限于一层磁性子膜中，达到降低涡流损耗的目的。因此，在第二级电压转换电路22采用该薄膜电感后，能够使第二级电压转换电路22的集成度更高，而且在该第二级电压转换电路22中的开关工作在高频时，使得第二级电压转换电路22中第一电感的阻抗较小，损耗较低。
可以理解的，在第二级电压转换电路22的输入电压为0.6V-1.3V时，该第二级电压转换电路22采用图4所示的降压电路，其占板面积较小，集成度较高，并且能够在第一开关和第二开关的开关频率大于或等于30Mhz时，确保电路的损耗较低，提高了第二级电压转换电路22的供电效率。
另一种实现方式中，上述第二级电压转换电路22可以采用图9所示的降压电路。如图9所示，该降压电路包括：第二电感L2、第二电容C2、第三开关Q3、第四开关Q4、第五开关Q5和第六开关Q6。第三开关Q3的第一端(a)为第二级电压转换电路22的输入端，第三开关Q3的第一端(a)连接第一级电压转换电路21的输出端，第三开关Q3的第二端(b)连接第四开关Q4的第一端(a)，第三开关Q3的控制端(c)用于输入第三控制信号。第四开关Q4的第二端(b)连接第二电感L2的第一端和第五开关Q5的第一端(a)，第四开关Q4的控制端(c)用于输入第一偏置电压V bias1。第五开关Q5的第二端(b)连接第六开关Q6的第一端(a)，第五开关Q5的控制端(c)用于输入第二偏置电压V bias2。第二电感L2的第二端为第二级电压转换电路22的输出端，第二电感L2的第二端连接第二电容C2的第一端。第二电容C2的第二端和第六开关Q6的第二端(b)接地。第六开关Q6的控制端(c)用于输入第四控制信号。
示例性的，上述第一偏置电压V bias1和第二偏置电压V bias2可以为预设偏置电压，使得第四开关Q4和第五开关Q5的栅极保持在一个固定的电压值。若第三开关Q3和第四开关Q4为PMOS管，第五开关Q5和第六开关Q6为NMOS管，当第三开关Q3导通时，第四开关Q4也导通，此时第五开关Q5和第六开关Q6均截止；当第三开关Q3截止时，第四开关Q4也截止，此时第五开关Q5和第六开关Q6均导通。
需要说明的是，上述第三开关Q3、第四开关Q4、第五开关Q5和第六开关Q6可以为NMOS管，也可以为PMOS管，本申请实施例对此并不进行限定，只需满足第三开关Q3和第四开关Q4导通时，第五开关Q5和第六开关Q6截止；第三开关Q3和第四开关Q4截止时，第五开关Q5和第六开关Q6导通即可。例如，该第三开关Q3和第四开关Q4可以均为PMOS管，第五开关Q5和第六开关Q6均为NMOS管。图9中的R表示无线终端设备的负载，实际应用中，无线终端设备的负载可以为一个具体功能的电路模块，本申请实施例对于无线终端设备的负载的具体形式并不进行限定，在此仅以R进行示例性说明。
可以理解的，该第二级电压转换电路22采用图9所示的降压电路时，电路中的第二电感可以采用图6-图8所示的电感，从而在第一开关和第二开关的开关频率大于或等于30Mhz时，确保电感的面积和体积较小，电感的损耗较低，第二级电压转换电路22的供电效率较高。需要说明的是，由于图4的降压电路采用了两个开关管，图9的降压电路采用了四个开关管，故第二级电压转换电路22采用图4所示的降压电路，较采用图9所示的降压电路，第一级电压转换电路21的输出电压低，转换效率较高。而且采用图4所示的降压电路需要的开关管数量较少，因此集成度更高。
一种实现方式中，供电电路20中的第二级电压转换电路22可以与负载集成在一起。示例性的，如图10所示，可以将第二级电压转换电路22与系统级芯片(System on Chip，SoC)集成在一起，用于为该系统级芯片供电。该系统级芯片可以包括CPU、GPU、AI处理器和内存等。在该实现方式中，第一级电压转换电路21和第二级电压转换电路22可以为不同的芯片。例如，第一芯片中包括第一级电压转换电路21，第二芯片中包括第二级电压转换电路22，该第二芯片可以为集成了第二级电压转换电路的处理器芯片。
示例性的，如图11所示，由于不同负载的电压需求不同，为了精细化电源管理，提高供电效率，可以采用多个第二级电压转换电路22分别为不同的负载(例如，CPU、GPU、AI处理器和内存)供电。而且本申请提供的第二级电压转换电路22为高频开关电路，其面积和体积很小，因此可以将第二级电压转换电路22与其供电的负载集成在一起，使得供电电路的集成度更高，功率密度更大。
一种实现方式中，如图12所示，供电电路20中的第一级电压转换电路21可以与第二级电压转换电路22集成在一个集成电路(Integrated Circuit，IC)中。
可以理解的，由于网络设备的处理器芯片可以采用5nm、7nm等先进CMOS制程，其供电电压可以降低到0.6V左右，采用本申请实施例的低压总线架构(0.6V-1.3V的电压总线架构)，能够有效的提高电路的转换效率，供电效率较高。而且通过结合高频开关技术，能够进一步减小电源方案的面积和体积，功率密度较现有技术有了大幅提升。
本申请实施例提供的供电电路，通过两级电压转换电路为负载供电，其中，第一级电压转换电路可以将电源电压转换为1.1V左右(0.6V-1.3V)的输出电压，将其作为第二级电压转换电路的输入，并通过高频的第二级电压转换电路降压后为负载供电，能够在负载的供电电压较低时，提高第二级电压转换电路的转换效率。由于第二级电压转换电路22为高频开关电路，其工作频率远高于传统电源电路的工作频率，因此能够在满足负载跳变的瞬态性能要求的同时，大大减小供电电路的占板面积。而且与现有技术中每一路电压转换器电路需要按负载的最大峰值电流设计相比，本申请可以将第一级电压转换电路21的峰值功率设计为小于所有与其连接的一个或多个第二级电压转换电路22的峰值功率之和，从而能够避免电路过设计，且进一步减小供电电路的占板面积，提高供电电路的功率密度。
本申请实施例还提供一种集成电路系统，该集成电路系统包括第一芯片和第二芯片，该第一芯片包括上述第一级电压转换电路21，该第二芯片包括上述第二级电压转换电路22。
示例性的，该集成电路系统中的第二芯片可以为处理器芯片，该第一芯片为向该处理器芯片提供电力的电源芯片。例如，该第二芯片可以为集成了第二级电压转换电路22的处理器芯片，第一芯片的第一级电压转换电路21可以为该第二芯片供电。可以理解的，关于该第一级电压转换电路21和第二级电压转换电路22的相关描述可以参考上述实施例中的内容，在此不再赘述。
本申请实施例还提供一种供电控制方法，应用于图13所示的电源系统，该电源系统包括图7所示的供电电路20、与第一级电压转换电路21连接的主控制器、与第二级电压转换电路22连接的第一从控制器，以及与负载连接的第二从控制器，主控制器、第一从控制器和第二从控制器之间通过控制总线连接。如图14所示，该供电控制方法可以包括步骤S1401-S1403。
S1401、负载启动业务前，第二从控制器向主控制器发送功率请求信息。
该功率请求信息用于请求第一级电压转换电路21的可用功率。该可用功率为第一级电压转换电路的最大输出功率减去与第一级电压转换电路21连接的全部第二级电压转换电路22的当前输出功率之和。示例性的，该第一级电压转换电路的最大输出功率可以预设值。
示例性的，为第二从控制器连接的负载供电的第二级电压转换电路22与第一级电压转换电路21连接。由于，本申请实施例中第一级电压转换电路21的峰值功率小于与其连接的所有第二级电压转换电路22的峰值功率之和，因此，第二级电压转换电路22在从第一级电压转换电路21抽取电流为负载供电前，可以先请求第一级电压转换电路21的可用功率。
S1402、第二从控制器接收主控制器发送的功率响应消息。
该功率响应消息中携带第一级电压转换电路21的可用功率。
若第一级电压转换电路21的可用功率大于或等于负载启动所需功率，确定负载启动时可以从第一级电压转换电路21抽取电流为负载供电。若第一级电压转换电路21的可用功率小于负载启动所需功率，确定当前第一转换电路的输出功率较大，不足以再为该负载启动供电，可以执行步骤S1403。
S1403、若第一级电压转换电路的可用功率小于负载启动所需功率，第二从控制器等待第一时长后，再次向主控制器发送功率请求信息。
示例性的，在第一级电压转换电路21的可用功率不足以支撑负载启动时，可以等待第一时长后，再次向主控制器发送功率请求信息，直至第一级电压转换电路21的可用功率大于或等于负载启动所需功率，再启动负载。
可以理解的，由于本申请实施例中第一级电压转换电路21的峰值功率小于与其连接的所有第二级电压转换电路22的峰值功率之和，因此，在第一级电压转换电路21的输出功率有限的情况下，可以通过步骤S1401-S1403的限制最大功率机制，将多个峰值业务错开，从而减小电源内阻上损失的能量，提高了电源系统的效率。
本申请实施例还提供一种供电控制方法，如图15在上述步骤S1401-S1403之后，还包括步骤S1404-S1405，图15中未示出S1401-S1403。
S1404、主控制器从第一从控制器获取第二级电压转换电路的当前输出功率。
示例性的，主控制器可以从第一从控制器获取与每个第一从控制器连接的第二级 电压转换电路22的当前输出功率。
S1405、若与第一级电压转换电路连接的一个或多个第二级电压转换电路的当前输出功率之和，大于该第一级电压转换电路的最大输出功率，主控制器向操作系统发送告警信息。
示例性的，基于步骤S1401-S1403的限制最大功率机制，一般情况下，第一级电压转换电路21的最大输出功率大于或等于与其连接的所有第二级电压转换电路22的输出功率之和。但若负载短路或出现其他异常情况时，与第一级电压转换电路21连接的一个或多个第二级电压转换电路22的当前输出功率之和可能会大于第一级电压转换电路21的最大输出功率，此时，主控制器向操作系统发送告警信息，操作系统可以采用预设的电源管理策略来处理该功率超出异常的情况。
本申请实施例提供的供电控制方法，通过限制最大功率机制，能够将多个峰值业务错开，减小电源内阻上损失的能量，提高了电源系统的效率。并且能够在与第一级电压转换电路21连接的多个第二级电压转换电路22的输出功率之和高于该第一级电压转换电路21的最大输出功率时，发送告警信息。
本申请实施例还提供一种供电控制方法，应用于图13所示的电源系统，该电源系统还包括延迟电路。如图16所示，该供电控制方法还包括步骤S1601-S1605。
S1601、若供电电路包括多个第一级电压转换电路，主控制器确定每个第一级电压转换电路对应的第一基准延迟时间。
该第一基准延迟时间为第一电压的纹波幅度最小时，每个第一级电压转换电路21对应的延迟时间。可以理解的，该第一基准延迟时间可以根据训练得到的算法来获得，本申请实施例对于第一基准延迟时间的具体获取方法并不进行限定。
示例性的，如果多个第一级电压转换电路21的开关管同时开启，将产生极大的瞬态电流，导致电源有很大的电压纹波，因此，可以通过确定电源电压(第一电压)的纹波幅度最小时，每个第一级电压转换电路21对应的延迟时间，使得多个第一级电压转换电路21的开关管错相(错开导通)，从而减小电压纹波。
示例性的，上述训练得到的算法可以包括：主控制器根据系统参考时钟和延迟电路，配置每个第一级电压转换电路21中开关管闭合或断开的延迟时间，确定第一电压的纹波幅度最小时，第一级电压转换电路21对应的延迟时间为第一基准延迟时间。
示例性的，上述延迟电路可以为Delay Lock Loop或类似功能的模块，可以实现在每个第二级电压转换电路22中配置延迟线。
S1602、根据第一基准延迟时间，主控制器调整每个第一级电压转换电路的导通时间。
可以理解的，可以根据上述步骤S1601确定的第一基准延迟时间，调整每个第一级电压转换电路的导通时间，使得电源系统中包括的多个第一级电压转换电路21之间的开关管导通的时间错开，减小电源电压纹波。例如，当多个负载启动时，若为该多个负载模块供电的第二级电压转换电路22连接多个第一级电压转换电路21，可以根据该第一基准延迟时间将该多个第一级电压转换电路21开关管导通的时间错开，减小电源电压纹波。
S1603、若第一级电压转换电路为多个第二级电压转换电路供电，主控制器确定与 第一级电压转换电路连接的每个第二级电压转换电路对应的第二基准延迟时间。
该第二基准延迟时间为第二电压的纹波幅度最小时，每个第二级电压转换电路22对应的延迟时间。
示例性的，当第一级电压转换电路为多个第二级电压转换电路供电时，即多个第二级电压转换电路22的输入端与第一级电压转换电路21的输出端连接时，如果多个第二级电压转换电路22的开关管同时导通，将产生极大的瞬态电流，导致第一级电压转换电路21的输出电压有很大的电压纹波。因此，可以通过训练算法，确定第一级电压转换电路21的输出电压(第二电压)的纹波幅度最小时，每个第二级电压转换电路22对应的延迟时间，使得多个第二级电压转换电路22的开关管错相(错开导通)，从而减小电压纹波。
示例性的，主控制器可以根据系统参考时钟和延迟电路，配置每个第二级电压转换电路22中开关管闭合或断开的延迟时间，确定第二电压的纹波幅度最小时，第二级电压转换电路22对应的延迟时间为第二基准延迟时间。
S1604、根据第二基准延迟时间，主控制器调整每个第二级电压转换电路的导通时间。
可以理解的，可以根据上述步骤S1603确定的第二基准延迟时间，调整与一个第一级电压转换电路连接的多个第二级电压转换电路的导通时间，使得该多个第二级电压转换电路22的开关管导通的时间错开，减小第一级电压转换电路21输出电压的电压纹波，提高电源系统的供电效率。例如，当多个负载启动时，若为该多个负载模块供电的第二级电压转换电路22连接同一个第一级电压转换电路21，可以根据该第二基准延迟时间将该多个第二级电压转换电路22开关管导通的时间错开，减小电源电压纹波。
(可选的)S1605、若负载启动高性能业务，主控制器增大第一级电压转换电路的输出电压；若负载工作在低功耗状态，主控制器减小第一级电压转换电路的输出电压。
示例性的，当负载运行低功耗业务时，可以将第一级电压转换电路21的输出电压降低，以提高第二级电压转换电路22的效率，供电效率较高。当负载运行高性能业务时，可以将第一级电压转换电路21的输出电压提高，以供负载正常运行高性能业务，从而能够在负载运行不同业务时，对第一转换电路的输出电压进行调整，满足不同情况时的业务需求。
本申请实施例提供的供电控制方法，能够将多个第一级电压转换电路21的开关管导通时间错开，并且将连接同一个第一级电压转换电路21的多个第二级电压转换电路22的开关管导通的时间错开，从而减小电源电压纹波。而且通过在高性能业务，增大第一级电压转换电路21的输出电压，在低功耗状态，减小第一级电压转换电路21的输出电压，使得电源系统的供电效率更高。
本申请实施例还提供一种终端设备，该终端设备包括上述供电电路20。
可选的，如图17所示，该终端设备还可以包括电源管理芯片1701，以及与电源管理芯片1701相连接的电源总线(power supply bus)或电源供电网络。电源管理芯片1701可以通过电源总线向该终端设备中的其余部件，例如，射频收发器(radio frequency module)、内存(memory)、硬盘、相机(Camera)与图像处理器(imaging processing  module)、输入/输出(I/O)接口、人机交互设备(human interactive device)等提供工作电压。
示例性的，上述终端设备还包括处理器1702，以及与处理器1702相连接的数据总线(Data bus)。该处理器1702包括供电电路20。处理器1702可以通过数据总线向该终端设备中的其余部件，例如，上述射频收发器、内存、硬盘、相机与图像处理器、输入/输出接口、人机交互设备等提供工作电压。该处理器1702可以为SoC、CPU、GPU中的任意一种。
上述终端设备和前述实施例提供的供电电路20技术效果相同，在此不再赘述。
本申请实施例还提供一种计算机存储介质，该计算机存储介质中存储有计算机程序代码，当计算机程序代码在处理器上运行时，使得该处理器执行图14中的S1401-S1403、或图15中的S1404-S1405、或图16中的S1601-S1605。示例性的，该处理器可以为CPU，而主控制器和从控制器可以为其他处理器、数字逻辑模块，或者CPU中的某一个功能模块，本申请实施例对此并不进行限定。
可以理解的是，终端设备为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的模块及算法步骤，本申请能够以硬件和计算机软件的结合形式来实现。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
结合本申请公开内容所描述的方法或者算法的步骤可以硬件的方式来实现，也可以是由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器(Random Access Memory，RAM)、闪存、可擦除可编程只读存储器(Erasable Programmable ROM，EPROM)、电可擦可编程只读存储器(Electrically EPROM，EEPROM)、寄存器、硬盘、移动硬盘、只读光盘(CD-ROM)或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。另外，该ASIC可以位于核心网接口设备中。当然，处理器和存储介质也可以作为分立组件存在于核心网接口设备中。
本领域技术人员应该可以意识到，在上述一个或多个示例中，本申请所描述的功能可以用硬件、软件、固件或它们的任意组合来实现。当使用软件实现时，可以将这些功能存储在计算机可读介质中或者作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是通用或专用计算机能够存取的任何可用介质。
以上所述的具体实施方式，对本申请的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本申请的具体实施方式而已，并不用于限定本申请的保护范围，凡在本申请的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本申请的保护范围之内。

Claims (11)

  1. 一种供电电路，其特征在于，所述供电电路包括：一个或多个第一级电压转换电路和一个或多个第二级电压转换电路；其中，
    所述第一级电压转换电路的输入端被耦合至电源；所述第一级电压转换电路用于将所述输入端接收到的第一电压转换为第二电压，并从所述第一级电压转换电路的输出端输出，所述第二电压小于所述第一电压，所述第二电压大于或等于0.6V，且小于或等于1.3V；
    所述第二级电压转换电路的输入端被耦合至所述第一级电压转换电路的输出端，所述第二级电压转换电路用于将所述第二电压转换为第三电压，并将所述第三电压提供给负载，所述第三电压小于所述第二电压；所述第二级电压转换电路的开关频率大于或等于30Mhz。
  2. 根据权利要求1所述的供电电路，其特征在于，一个第一级电压转换电路为一个或多个第二级电压转换电路供电时，每个第二级电压转换电路的输入端连接该第一级电压转换电路的输出端。
  3. 根据权利要求2所述的供电电路，其特征在于，所述第二级电压转换电路包括电感、电容、第一开关和第二开关，所述第一开关的第一端连接所述第一级电压转换电路的输出端，所述第一开关的第二端连接所述电感的第一端和所述第二开关的第一端，所述第一开关的控制端用于输入第一控制信号；所述电感的第二端为所述第二级电压转换电路的输出端，所述电感的第二端连接所述电容的第一端，所述电容的第二端和所述第二开关的第二端接地；所述第二开关的控制端用于输入第二控制信号；其中，所述第一开关和所述第二开关的开关频率大于或等于30Mhz。
  4. 根据权利要求3所述的供电电路，其特征在于，当所述第一开关和所述第二开关的开关频率大于或等于30Mhz时，所述电感的电感量密度大于或等于10nH/mm 2，且所述电感的电感量密度大于或等于40nH/mm 3，且所述电感的线圈直流阻抗小于或等于30mΩ。
  5. 根据权利要求3或4所述的供电电路，其特征在于，所述电感为薄膜电感，所述薄膜电感包括：磁芯，包括第一磁膜和第二磁膜；所述第一磁膜与所述第二磁膜之间具有容纳腔；
    导体，位于所述容纳腔内；
    绝缘间隔膜，设置于所述导体两侧，且位于所述第一磁膜和所述第二磁膜之间；所述绝缘间隔膜与所述第一磁膜和第二磁膜相接触；
    所述第一磁膜和所述第二磁膜均包括多层磁性子膜和多层绝缘子膜；
    所述第一磁膜中，所述磁性子膜和所述绝缘子膜交替设置；
    所述第二磁膜中，所述磁性子膜和所述绝缘子膜交替设置；
    所述第一磁膜与所述绝缘间隔膜相接触的表面，暴露出所述第一磁膜中多层磁性子膜和多层绝缘子膜；
    和/或，
    所述第二磁膜与所述绝缘间隔膜相接触的表面，暴露出所述第二磁膜中多层磁性子膜和多层绝缘子膜。
  6. 根据权利要求1-5任一项所述的供电电路，其特征在于，所述第一级电压转换电路的峰值功率小于所有与其连接的一个或多个第二级电压转换电路的峰值功率之和。
  7. 根据权利要求1-6任一项所述的供电电路，其特征在于，所述第一级电压转换电路为开关电容电压转换器电路、转换比可变的开关电容电压转换器电路、降压DC-DC转换器电路、多电平降压转换器电路、变压器隔离的降压转换器电路、混合的开关电感和开关电容结合的电压转换器电路，或者谐振开关电容电压转换器电路。
  8. 根据权利要求1-7任一项所述的供电电路，其特征在于，所述第二级电压转换电路与所述负载集成在一起。
  9. 根据权利要求3所述的供电电路，其特征在于，当所述第一开关导通时，所述第二开关关断，且，当所述第二开关导通时，所述第一开关关断。
  10. 一种集成电路系统，其特征在于，所述集成电路系统包括第一芯片和第二芯片，所述第一芯片包括第一级电压转换电路，所述第二芯片包括第二级电压转换电路；其中，
    所述第一级电压转换电路的输入端被耦合至电源；所述第一级电压转换电路用于将所述输入端接收到的第一电压转换为第二电压，并从所述第一级电压转换电路的输出端输出，所述第二电压小于所述第一电压，所述第二电压大于或等于0.6V，且小于或等于1.3V；
    所述第二级电压转换电路的输入端被耦合至所述第一级电压转换电路的输出端，所述第二级电压转换电路用于将所述第二电压转换为第三电压，并将所述第三电压提供给负载，所述第三电压小于所述第二电压；所述第二级电压转换电路的开关频率大于或等于30Mhz。
  11. 如权利要求10所述的集成电路系统，其特征在于，所述第二芯片为处理器芯片，所述第一芯片为向所述处理器芯片提供电力的电源芯片。
PCT/CN2019/084403 2019-04-25 2019-04-25 一种供电电路和供电控制方法 Ceased WO2020215293A1 (zh)

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