WO2020215732A1 - 信号处理方法、装置及系统 - Google Patents

信号处理方法、装置及系统 Download PDF

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Publication number
WO2020215732A1
WO2020215732A1 PCT/CN2019/123584 CN2019123584W WO2020215732A1 WO 2020215732 A1 WO2020215732 A1 WO 2020215732A1 CN 2019123584 W CN2019123584 W CN 2019123584W WO 2020215732 A1 WO2020215732 A1 WO 2020215732A1
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Prior art keywords
module
power amplifier
signal
outphasing
load modulation
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PCT/CN2019/123584
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English (en)
French (fr)
Inventor
任志雄
欧阳涛
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to EP19925642.1A priority Critical patent/EP3944496B1/en
Publication of WO2020215732A1 publication Critical patent/WO2020215732A1/zh
Priority to US17/508,080 priority patent/US12289081B2/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0277—Selecting one or more amplifiers from a plurality of amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0294—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using vector summing of two or more constant amplitude phase-modulated signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/432—Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier

Definitions

  • the embodiments of the present application relate to the field of signal processing, and in particular, to a signal processing method, device, and system.
  • the signal bandwidth has been expanded from 20MHz in 802.11g to 160MHz in 802.11ac
  • the modulation signal has been upgraded from Orthogonal Frequency Division Multiplexing (OFDM) 64-QAM (Quadrature Amplitude Modulation) to OFDM 256-QAM, and the corresponding rate has been increased from 54Mbps to 3.5Gbps
  • OFDM Orthogonal Frequency Division Multiplexing
  • the signal bandwidth has been expanded from the 4th Generation mobile communication technology (4G) Long Term Evolution (LTE) 20MHz to the 5th generation mobile communication technology (the 5th generation mobile communication technology).
  • the corresponding rate has increased from 100Mbps to above 1Gbps; in the coaxial cable access (Data Over Cable Service Interface Specifications, DOCSIS) technology, the signal bandwidth has been expanded from 860MHz in DOCSIS 1.0 to 1GHz in DOCSIS 3.1 The modulation signal is increased from single-carrier 64/256-QAM to OFDM 4096-QAM, and the corresponding rate is increased from 38Mbps to 10Gbps.
  • DOCSIS Data Over Cable Service Interface Specifications
  • the signals in current common communication systems have the characteristics of large bandwidth and high-order QAM modulation.
  • signals with large bandwidth and high-order QAM modulation will lead to the peak-to-average ratio of the signal.
  • -to-Average-Ratio, PAR increase.
  • the functional modules in the communication link need to work in the fallback area according to PAR.
  • PA Power Amplifier
  • PA Power Amplifier
  • the PA In the face of the current signal bandwidth expansion, the PA is required to have higher linearity, and the change of PAR makes the PA fall back to a lower level.
  • the efficiency area of the system leads to system energy loss and temperature rise, which in turn requires an increase in complex cooling system design. Therefore, how to design a high-efficiency PA to meet the current transmission requirements of large bandwidth and high PAR signals has become an urgent problem to be solved.
  • the corresponding back-off zone is 6dB.
  • the prior art usually adopts methods such as increasing the number of auxiliary amplifiers in the Doherty power amplifier.
  • this method will greatly increase the size of the power amplifier while improving the efficiency of the back-off zone.
  • the present application provides a signal processing method, device and system, which can effectively improve the efficiency of the fallback area.
  • an embodiment of the present application provides a signal processing system.
  • the system includes: n-channel load modulation modules and a synthesis module; wherein the n-channel load modulation modules are connected in parallel, and the output end of each load modulation module is connected to the synthesis module.
  • the input terminals of the modules are connected, and n is an integer greater than 1, wherein the synthesis module receives n signals output by the n load modulation modules through the input terminal, and synthesizes the n signals; and, n loads
  • the modulation module includes a main power amplifier module and (n-1) auxiliary power amplifier modules, wherein the auxiliary power amplifier module is turned on when the power value of the signal received at the input of the load modulation module is greater than the first threshold; wherein,
  • the main power amplifier module includes two out-of-phase Outphasing power amplifier units, and each auxiliary power amplifier module includes two Outphasing power amplifier arrays or one digital polarized Digital Polar power amplifier array.
  • the present application provides a system that does not require the number of auxiliary amplifiers, but can effectively improve the efficiency of the back-off zone, especially the efficiency of the deep back-off zone.
  • the Outpahsing power amplifier unit includes a Digital Outphasing power amplifier array. That is to say, each of the two channels of Outphasing power amplifier unit includes a Digital Outphasing power amplifier array, where each Digital Outphasing array includes two or more Outphasing power amplifiers. Therefore, when the main power amplifying module is turned on, the number of outphasing power amplifiers in the main power amplifying module is further controlled to improve the efficiency of the fallback zone.
  • the main power amplifier module further includes a synthesis unit, the output ends of the two Outphasing power amplifier units are respectively connected to the input end of the synthesis unit, and the output end of the synthesis unit is connected to the input end of the synthesis module
  • the synthesis unit may be used to receive the two-channel signals output by the two-channel Outphasing power amplifying unit through the input terminal, and perform synthesis processing on the two-channel signals; wherein the synthesis unit and the synthesis module are composed of transformers.
  • the device size is reduced, and the system can be integrated on the chip through the CMOS process.
  • the first synthesis unit is a Chireix synthesizer
  • the second synthesis unit is a Doherty synthesizer
  • the embodiments of the present application provide a signal processing method, which can be applied to the signal processing system described in the first aspect.
  • the method includes: receiving signals through n-channel load modulation modules connected in parallel; Value, turn on one or more of the n-channel load modulation modules; among them, if the power value is less than or equal to the first threshold, turn on one of the n-channel load modulation modules; if the power value is greater than the first threshold A threshold value, turn on at least one auxiliary power amplifier module of one main power amplifier module and (n-1) load modulation module; wherein, the main power amplifier module includes two outphasing power amplifier units, and the auxiliary power amplifier The module includes two Outphasing power amplifier arrays or a digital polarized Digital Polar power amplifier array.
  • the step of turning on one or more of the n-channel load modulation modules includes: if the amplitude value of the signal is less than or equal to the second threshold, turning on the main Power amplification module; if the amplitude value of the signal is greater than the second threshold, turn on at least one auxiliary power amplification module.
  • the step of turning on at least one auxiliary power amplifier module of one main power amplifier module and (n-1) load modulation module includes: if the amplitude value of the signal meets the requirements of Outphasing power amplifier array or Digital The trigger condition of one or more power amplifiers in the Polar power amplifier array turns on one or more power amplifiers.
  • the step of turning on one or more load modulation modules among the n-channel load modulation modules includes: if the phase value of the signal is greater than or equal to the third threshold, turning on the main Power amplifying module; if the phase value of the signal is less than the third threshold, turn on at least one auxiliary power amplifying module; wherein the phase value is obtained after outphasing the signal.
  • the step of turning on at least one auxiliary power amplifier module of one main power amplifier module and (n-1) load modulation module includes: if the phase value of the signal satisfies Outphasing power amplifier array or Digital The trigger condition of one or more power amplifiers in the Polar power amplifier array turns on one or more power amplifiers.
  • an embodiment of the present application provides a signal processing device, including: a control module for controlling n-channel load modulation modules connected in parallel to receive signals; and the control module may be further configured to turn on n-channels based on the power value of the signal One or more load modulation modules in the load modulation module; among them, if the power value is less than or equal to the first threshold, then one of the n-channel load modulation modules is turned on; if the power value is greater than the first threshold, turn on At least one auxiliary power amplifier module of one main power amplifier module and (n-1) load modulation module; wherein, the main power amplifier module includes two outphasing power amplifier units, and the auxiliary power amplifier module includes two outphasing power amplifier units.
  • control module is further configured to: if the amplitude value of the signal is less than or equal to the second threshold, turn on the main power amplifier module; if the amplitude of the signal is greater than the second threshold, turn on at least one auxiliary power Amplify the module.
  • control module is further configured to: if the amplitude value of the signal meets the trigger condition of one or more power amplifiers in the Outphasing power amplifier array or the Digital Polar power amplifier array, turn on one or more power Amplifier.
  • control module is further configured to: if the phase value of the signal is greater than or equal to the third threshold, turn on the main power amplification module; if the phase value of the signal is less than the third threshold, turn on at least one auxiliary power Amplification module; among them, the phase value is obtained after outphasing the signal.
  • control module is further configured to: if the phase value of the signal meets the trigger condition of one or more power amplifiers in the Outphasing power amplifier array or the Digital Polar power amplifier array, turn on one or more power Amplifier.
  • embodiments of the present application provide a computer-readable medium for storing a computer program, the computer program including instructions for executing the second aspect or any possible implementation of the second aspect.
  • an embodiment of the present application provides a computer program, which includes instructions for executing the second aspect or any possible implementation of the second aspect.
  • an embodiment of the present application provides a chip, which includes a processing circuit and transceiver pins.
  • the transceiver pin and the processor communicate with each other through an internal connection path, and the processor executes the method in the second aspect or any one of the possible implementations of the second aspect to control the receiving pin to receive signals, and Control the sending pin to send signals.
  • Fig. 1 is a schematic diagram showing the structure of a power amplifier by way of example
  • Fig. 2 is an exemplary efficiency curve
  • Fig. 3 is a schematic structural diagram of a power amplifier shown by way of example
  • FIG. 4 is one of the structural schematic diagrams of a signal processing system provided by an embodiment of the present application.
  • FIG. 5 is one of the flowcharts of a signal processing method provided by an embodiment of the present application.
  • FIG. 6 is one of the schematic diagrams of a polarization scheme provided by an embodiment of the present application.
  • FIG. 7 is one of the schematic diagrams of a polarization scheme provided by an embodiment of the present application.
  • FIG. 8 is a spectrum diagram of a signal provided by an embodiment of the present application.
  • Figures 9(a)-9(d) are the load impedance change curves of Outphasing PA in an embodiment of the present application.
  • FIG. 10 is an efficiency curve diagram of the system provided by an embodiment of the present application.
  • FIG. 11 is one of the structural schematic diagrams of a signal processing system provided by an embodiment of the present application.
  • FIG. 12 is one of the flowcharts of a signal processing method provided by an embodiment of the present application.
  • Figure 13 is an efficiency curve diagram of a system provided by an embodiment of the present application.
  • FIG. 14 is one of the structural schematic diagrams of a signal processing system provided by an embodiment of the present application.
  • FIG. 15 is one of the structural schematic diagrams of a signal processing system provided by an embodiment of the present application.
  • FIG. 16 is one of the schematic structural diagrams of a signal processing device provided by an embodiment of the present application.
  • first and second in the description and claims of the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order of objects.
  • first target object and the second target object are used to distinguish different target objects, rather than to describe the specific order of the target objects.
  • words such as “exemplary” or “for example” are used as examples, illustrations, or illustrations. Any embodiment or design solution described as “exemplary” or “for example” in the embodiments of the present application should not be construed as being more preferable or advantageous than other embodiments or design solutions. To be precise, words such as “exemplary” or “for example” are used to present related concepts in a specific manner.
  • multiple means two or more.
  • multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.
  • Figure 1 is a schematic diagram of a power amplifier structure in the prior art.
  • Figure 1 is a schematic diagram of a power amplifier structure in the prior art.
  • the power amplifier has a multi-channel analog Doherty PA structure, which includes a main power amplifier 110 and two auxiliary power amplifiers, namely: an auxiliary power amplifier 120 and an auxiliary power amplifier 130.
  • the main power amplifier includes a power amplifier 111 and a power amplifier 112, which are two out-of-phase (outphasing) power amplifiers.
  • the two auxiliary amplifiers also include an input signal separation unit, an output signal synthesizer, etc. (not labeled in the figure).
  • the Doherty PA structure its working principle is: when the input signal (or can be described as the power of the input signal) is small (the input signal can be defined as being small, if the power of the input signal is less than the preset Threshold, the input signal is a smaller signal, otherwise it is a larger signal), the auxiliary power amplifier (such as the two auxiliary power amplifiers 120 and 130 in FIG. 1) is in a non-working state, and the main power amplifier is in a working state. That is, referring to FIG.
  • the PA works in the Outphasing mode, that is, the main power amplifier 110 is in the working state to amplify the input signal, and its efficiency curve forms the first back-off zone ( Namely T1 ⁇ T2).
  • the auxiliary power amplifier is turned on when the input signal is large (at the same time, the main power amplifier is still in working state, that is, when the input signal is large, the main and auxiliary power amplifiers are in working state).
  • the auxiliary amplifiers 120 and 130 are gradually turned on.
  • the auxiliary power amplifier 120 and the auxiliary power amplifier 130 form a Doherty load modulation with the main power amplifier, and the efficiency curves form the second and third Fallback area.
  • the size of the back-off zone is determined by the number of auxiliary amplifiers. That is, in the amplifier structure including two auxiliary power amplifiers shown in Figure 1, the main power of Outphasing Two new fallback points are added to the amplifier. If you want to continue to increase the back-off point (that is, increase the size of the back-off zone, or it can be understood as improving the efficiency of the back-off zone), you need to add the number of auxiliary amplifiers and the corresponding impedance transformation transmission line, resulting in the structure of the output synthesizer More complex, the separation of the corresponding input signal also becomes more complicated, which will reduce the overall PA gain and efficiency.
  • FIG. 3 is a schematic diagram of another power amplifier in the prior art.
  • Figure 3 is a schematic diagram of another power amplifier in the prior art.
  • the power amplifier 200 combines the traditional analog Doherty PA and the digital polarized PA (Digital Polar) two structures.
  • the auxiliary power amplifier in the Doherty PA is replaced with the Digital Polar PA (i.e. 220 in the figure). ), and the main power amplifier is still a traditional analog PA (210 in the figure).
  • the auxiliary power amplifiers are all turned off, and only the main power amplifier 210, that is, the analog PA, is in working state.
  • the PA in the Digital Polar (ie auxiliary power amplifier 220) power amplifier array is gradually turned on. At this time, Doherty load modulation is formed between the main and auxiliary PAs.
  • the corresponding back-off zone size is 6dB, which is the same size as the back-off zone that can be achieved by the traditional two-way analog Doherty PA.
  • the power amplifier shown in Figure 3 can also By adopting the asymmetric Doherty structure, the efficiency of the fallback area is further improved, that is, the size of the fallback area is increased.
  • the problem in asymmetric Doherty PA is that if a larger back-off zone is to be achieved, for example, a deep back-off zone (that is, above 12dB), the power of the auxiliary power amplifier must be at least equal to that of the main power amplifier. 3 times the size, therefore, the size of the auxiliary power amplifier will be relatively increased (larger increase). Therefore, in practical applications, it is difficult to improve the efficiency of the deep back-off zone of the PA.
  • this application proposes a signal Processing system.
  • the system does not need to increase the number of additional auxiliary amplifiers, and can effectively improve the efficiency of the fallback zone, thereby achieving a deep fallback zone.
  • Fig. 4 is a schematic diagram of the structure of the signal processing system in an embodiment of the application, and in Fig. 4:
  • the signal processing system 300 includes a digital signal processing (DSP) module 310, two parallel load modulation modules, where the two load modulation modules include a main power amplifier module 320, an auxiliary power amplifier module 330, and signal processing
  • DSP digital signal processing
  • the system 300 also includes a synthesis module 340 and a feedback module 350.
  • the output ends of the DSP module 310 in the signal processing system 300 are respectively connected to the input ends of two load modulation modules (that is, the main power amplifier module 320 and the auxiliary power amplifier module 330).
  • the input ends of the synthesis module 340 are respectively connected to the output ends of two load modulation modules (that is, the main power amplifier module 320 and the auxiliary power amplifier module 330).
  • the output terminal of the synthesis module 340 is connected to the input terminal of the feedback module 350, and the output terminal of the feedback module 350 is connected to the input terminal of the DSP module 310, thereby forming a feedback loop.
  • the feedback loop can be used to recover the PA output signal, and feedback the collected signal to the DSP module for processing such as distortion, mismatch and other undesirable factors.
  • the specific processing method of the feedback loop can refer to the technical solution in the prior art embodiment , This application will not repeat it.
  • the main power amplifier module 320 includes two Outphasing power amplifiers (that is, the Outphasing power amplifier 321 and the Outphasing power amplifier 322 in the figure) connected in parallel, and a combining unit 323.
  • the synthesis unit 323 may be a low isolation Chireix synthesizer, which is composed of an inductor and a capacitor. In other embodiments, the synthesizer may also be another low isolation synthesizer, which is not limited in this application.
  • the DSP module (for example, the DSP module 310) may be a DSP processor or a module composed of multiple main functional units of DSP processing.
  • the auxiliary power amplifier module 330 includes a digital Polar power amplifier array, that is, the auxiliary power amplifier can be quantified as an array composed of multiple (ie, two or more) polarized power amplifiers.
  • the synthesis module 340 includes but is not limited to: a transmission line 341 and a synthesizer 342.
  • the transmission line 341 may be a ⁇ /4 transmission line used for impedance transformation of Doherty load modulation.
  • the synthesizer 342 may be a Doherty synthesizer.
  • FIG. 5 is a flowchart of a signal processing method in an embodiment of the application. The method is applied to the signal processing system shown in FIG. 4, and the method includes:
  • Step 101 Receive a signal through a load modulation module connected in parallel.
  • the DSP module performs digital signal processing on signals (to distinguish other signals, such as output signals, etc., in this embodiment and the following embodiments, the signals are collectively referred to as input signals). Subsequently, the DSP sends the processed input signal through the output terminal to the input terminal of the two-way load modulation module.
  • the signals input to the two load modulation modules include: two Outphasing PA input signals S 1 and S 2 , and Digital Polar PA input signal S 3 and control signals A 1 ⁇ A n .
  • the load modulation modules can form a Doherty PA structure, that is, the load modulation modules in this application can work in the Doherty load modulation mode.
  • the load modulation modules in this application can work in the Doherty load modulation mode.
  • the main power amplifier is turned on, and the auxiliary power amplifier is turned off; when the input signal is large, the main power amplifier and the auxiliary power amplifier are turned on at the same time .
  • the amplitude threshold can be set, and the DSP can determine the size of the input signal based on the amplitude threshold, and determine the corresponding For the processing method of the input signal.
  • the DSP converts the input signal S in into two signals S 1 and S 2 , and outputs them to the main power amplifier module, so that The main power amplifier module is in working state, and step 102 is entered.
  • the DSP converts the input signal into: the input signal S 3 , the control A 1 -A n , and the two signals S 1 and S 2 .
  • the input signal S 3 the control signal A 1 ⁇ A n for amplifying the secondary power module is active, and proceeds to step 103, wherein the control signal A 1 ⁇ A n open auxiliary amplifier array of power amplifying modules comprising Refer to step 103 for the manner of one or more power amplifiers.
  • the input signal S in can be expressed as:
  • A(t) is the amplitude modulation signal, It is a phase modulation signal, and ⁇ is the carrier frequency.
  • DSP can obtain the amplitude value of the input signal based on the envelope value of the input signal, and determine the power of the input signal based on the amplitude value (that is, if the amplitude value is less than or equal to the amplitude threshold, the input signal is a smaller signal , The corresponding power is also smaller, and vice versa is a larger input signal).
  • the DSP module performs Outphasing processing on the signal, and the separated two signals S 1 and S 2 are expressed as:
  • the DSP module 310 outputs the two-channel two-channel signal S 1 and S 2 to the main power amplifier module to turn on the two outphasing power amplifiers in the main power amplifier module 320.
  • the DSP module 310 detects that the input signal is relatively large, the DSP module 310 performs Outphasing processing on the signal to obtain two signals S 1 and S 2 for turning on the main power amplifier module. And, DSP blocks, 310 pairs of signal polarization treatment, so as to obtain a power amplification module for turning on the auxiliary input signal and the control signal S 3 A 1 ⁇ A n.
  • DSP blocks, 310 pairs of signal polarization treatment so as to obtain a power amplification module for turning on the auxiliary input signal and the control signal S 3 A 1 ⁇ A n.
  • phase threshold DSP blocks, 310 can be Outphasing (processing procedure described above with reference) to an input signal S in, and to give The phase value ⁇ (t) ⁇ [0 ⁇ /2] related to the amplitude information.
  • the smaller the amplitude of the input signal the larger the value of ⁇ (t)
  • the larger the amplitude of the input signal the smaller the value of ⁇ (t).
  • the control signal A 1 ⁇ A n auxiliary control power amplifier module comprising amplifier array 330 Digital Polar Polar PA in turn, since the amplitude and ⁇ (t) correlation, it is possible to ⁇ (t) directly Converted into control signals A 1 to A n .
  • the larger the amplitude the smaller the value of ⁇ (t).
  • the polarized signals A 1 ⁇ A n and S 3 are output, and after the Outphasing transformation S 1 and S 2 , that is, the two Outphasing power amplifiers 321 and 322 and one or more Polar power amplifiers in the Digital Polar power amplifier array are in working state.
  • Step 102 If the power value is less than or equal to the first threshold, turn on one main power amplifier module in the load modulation module.
  • the DSP module 310 may determine the power of the input signal based on the amplitude value of the input signal or may be based on the phase value of the input signal after the Ohtphasing transformation. That is, when the amplitude value is less than or equal to the amplitude threshold, or the transformed phase value is greater than or equal to the phase threshold, it can be determined that the input signal is a small signal, that is, the power value of the input signal is less than or equal to the power threshold. If the amplitude value is greater than the amplitude threshold, or the transformed phase value is less than the phase threshold, it can be determined that the input signal is a larger signal, that is, the power value of the input signal is greater than the power threshold.
  • the DSP determines that the input signal is a small signal, then, as described above, the DSP performs Outphasing transformation on the input signal to obtain two signals S 1 and S 2 , and outputs S 1 to the main power
  • the Outphasng power amplifier will amplify the two signals separately. And output the processed signal to the Chireix synthesizer 323 in the main power amplifier module 320.
  • the Chireix synthesizer outputs the synthesized signal to the synthesis module 340.
  • the signal is transmitted to the Doherty synthesizer 342 via the transmission line 341, the Doherty synthesizer 342 processes the signal and outputs it through the output terminal, and the feedback loop collects the output signal of the Doherty synthesizer 342 and feeds it back to the DSP module 310.
  • Step 103 If the power value is greater than the first threshold, turn on the main power amplifying module and the auxiliary power amplifying module.
  • the DSP module 310 may perform Ohtphasing transformation on the input signal to obtain two signals S 1 and S 2 , and Output S 1 to the Outphasing power amplifier 321 in the main power amplifier module 320, and output S 2 to the Outphasing power amplifier 322 in the main power amplifier module 320 to turn on the two Outphasing amplifiers.
  • the two signals are amplified and processed, and the processed signal is output to the Chireix synthesizer 323 in the main power amplification module 320.
  • the DSP module 310 performs polarization processing on the input signal to obtain the input signal S 3 and the control signals A 1 ⁇ A n .
  • the DSP module 310 stores trigger conditions of one or more power amplifiers in the Digital Polar power amplifier array.
  • the DSP module 310 can determine whether the trigger condition of the Polar power amplifier is satisfied based on the magnitude of the amplitude value, and if so, send a control signal to the Polar power amplifier that meets the trigger condition.
  • the trigger condition of the Polar PA 331 in the Digital Polar amplifier array is: when the amplitude value reaches the amplitude value 1 (this value can be set according to actual needs, this application does not limit it), Polar PA 331 is turned on.
  • the trigger condition of Polar PA 331 is that the amplitude value reaches the amplitude value 2
  • the trigger condition of Polar PA 333 (not shown in the figure) is that the amplitude value reaches the amplitude value 3.
  • the DSP module 310 when the DSP module 310 detects that the amplitude value of the input signal reaches the amplitude value 1, it outputs the control signal A 1 to control the Polar PA 331 to turn on, and amplify the input signal S 3 . If the DSP module 310 detects that the amplitude value of the input signal reaches the amplitude value 2, it outputs control signals A 1 and A 2 to control Polar PA 331 and Polar PA 332 to turn on. If the DSP module 310 detects that the amplitude value of the input signal reaches the amplitude value 3, it will output control signals A 1 , A 2 , and A 3 to control Polar PA 331, Polar PA 332 and Polar PA 333 to turn on.
  • the DSP module 310 may determine whether the trigger condition of the Polar power amplifier is satisfied based on the magnitude of the phase value of the signal after the Outphasing transformation, and if so, send a control signal to the Polar power amplifier that meets the trigger condition .
  • Polar PA 331 in Digital Polar the trigger condition is: when the phase value reaches phase value 1 (this value can be set according to actual needs, this application is not limited), Polar PA 331 is turned on.
  • Polar power amplifier 2 The trigger condition is that the phase value reaches phase value 2, and the trigger condition of Polar PA 333 is that the phase value reaches phase value 3.
  • the DSP module 310 detects that the phase value of the input signal after the Ohtphasing transformation reaches the phase value At 1, the control signal A 1 is output to control the Polar power amplifier 1 to turn on, and the input signal S 3 is amplified. If the DSP module 310 detects that the phase value of the input signal reaches the phase value 2, it outputs the control signal A 1 , A 2 , to control Polar Polar PA 331 and Polar PA 332 to turn on. If the DSP module 310 detects that the phase value of the input signal reaches the phase value 3, it outputs control signals A 1 , A 2 , A 3 , and Control Polar PA 331, Polar PA 332 and Polar PA 333 to turn on.
  • Figure 8 shows the frequency spectrum of the amplitude signal processed by different polarization methods.
  • the bandwidth extension of the amplitude signal after complete polarization is larger, and the partial polarization scheme can significantly reduce the bandwidth extension effect. For example, taking the power value equal to -140dB/Hz as a reference and using partial polarization, the extended bandwidth of the amplitude signal can be reduced from 580MHz to 360MHz. Therefore, this application can effectively reduce the bandwidth expansion effect by performing polarization processing on part of the signal.
  • Figures 9(a) to 9(d) show the load impedance change curves of the Outphasing PA in this embodiment.
  • Figure 9(a) shows the load impedance transformation curve with only the Outphasing PA turned on, that is, without Doherty load modulation (that is, as shown in Figure 9(a)), the load impedance of the two Outphasing PAs varies with ⁇ (t), due to the Chireix compensation network, there are two points where the imaginary part of the impedance is equal to zero.
  • Figure 9(b) shows the load impedance transformation curve of the Outphasing PA and Polar PA 331.
  • Fig. 10 shows an efficiency curve based on ideal model simulation (including ideal voltage source, current source, ideal transmission line, etc.) using the technical solution in this embodiment.
  • the PAR of the input signal is 21dB
  • the peak output power of the system is required to reach 30dBm, and the corresponding average power is 9dBm.
  • the states of A 1 , A 2 , and A 3 need to be dynamically controlled to achieve 21dB deep return. Improved exit efficiency.
  • the PAR of the input signal is 18dB
  • the peak output power is required to reach 30dBm
  • the corresponding average power is 12dBm.
  • the states of A 1 and A 2 need to be dynamically controlled to improve the efficiency of the 18dB deep fallback zone.
  • the PAR of the input signal is 15 dB
  • the peak output power is required to reach 30 dBm, and the corresponding average power is 15 dBm.
  • the state of A 1 needs to be dynamically controlled to improve the efficiency of the 15 dB deep fallback zone. If the PAR of the input signal is 9dB, only the Outphasing PA amplifier can work, or the Chireix compensation network can be modified to reduce the fallback area of the Outphasing PA, while controlling the states of A 1 , A 2 , and A 3 to achieve 9dB return Improved exit efficiency.
  • this application can achieve high-efficiency transmission of different PAR signals through flexible control.
  • this application can control the number of Digital Polar PAs to be turned on to meet the high efficiency requirements in different PAR signal scenarios.
  • FIG. 11 is a schematic structural diagram of the signal processing system in an embodiment of the application, and in FIG. 11:
  • the signal processing system 400 includes a DSP module 410 and two parallel load modulation modules.
  • the two load modulation modules include a main power amplifier module 420 and an auxiliary power amplifier module 430.
  • the signal processing system 400 also includes a synthesis module 440 and a feedback module. Module 450.
  • the output ends of the DSP module 410 in the signal processing system 400 are respectively connected to the input ends of two load modulation modules (that is, the main power amplifier module 420 and the auxiliary power amplifier module 430).
  • the input ends of the synthesis module 440 are respectively connected to the output ends of the two load modulation modules (that is, the main power amplifier module 420 and the auxiliary power amplifier module 430).
  • the output terminal of the synthesis module 440 is connected to the input terminal of the feedback module 450, and the output terminal of the feedback module 450 is connected to the input terminal of the DSP module 410, thereby forming a feedback loop.
  • the main power amplifier module 420 includes two Outphasing power amplifier arrays connected in parallel (ie, the Outphasing power amplifier array 421 and the Outphasing power amplifier array 422 in the figure, wherein each Outphasing power amplifier array includes Two or more Outphasing power amplifiers, and, it should be noted that the Outphasing amplifiers in the two Outphasing power amplifier arrays are set in pairs, for example: Outphasing PA 421a and Outphasing power amplifier arrays in Outphasing power amplifier array 421 Outphasing PA 422a in 422 is paired, that is, control signal A 11 can be used to control Outphasing PA 421a and Outphasing PA 422a), that is, the main power amplifier in Doherty PA is quantized as an array composed of multiple Outphasing amplifiers.
  • the main power amplification module 420 further includes a combining unit 423.
  • the synthesizing unit 423 may be a Chireix synthesizer with low isolation, which is composed of an inductor and a capacitor.
  • the synthesizer may also be another low isolation synthesizer, which is not limited in this application.
  • the auxiliary power amplifier module 430 includes a Digital Polar power amplifier array, that is, the auxiliary power amplifier can be quantified as an array composed of multiple (ie, two or more) polarized power amplifiers.
  • the synthesis module 440 includes a transmission line 441 and a synthesizer 442.
  • FIG. 12 shows a signal processing method in an embodiment of this application. The method is applied to the signal processing system shown in FIG. 11, and the method includes:
  • Step 201 Receive a signal through a load modulation module connected in parallel.
  • the DSP module performs digital signal processing on signals (to distinguish other signals, such as output signals, etc., in this embodiment and the following embodiments, the signals are collectively referred to as input signals). Subsequently, the DSP sends the processed input signal through the output terminal to the input terminal of the two-way load modulation module.
  • the signals input to the two load modulation modules include: two Outphasing PA input signals S 1 , S 2 , and control signals A 11 ⁇ A 1n , and Digital Polar PA input signals S 3 and Control signals A 21 ⁇ A 2n .
  • the load modulation modules can form a Doherty PA structure, that is, the load modulation modules in this application can work in the Doherty load modulation mode.
  • the load modulation modules in this application can work in the Doherty load modulation mode.
  • the main power amplifier is turned on, and the auxiliary power amplifier is turned off; when the input signal is large, the main power amplifier and the auxiliary power amplifier are turned on at the same time .
  • the DSP when the input signal is large, the DSP also determines whether the trigger condition of each Digital Polar power amplifier in the auxiliary power amplifier module 430 is satisfied based on the amplitude value or the phase value after Outphasing transformation. If yes, output S 3 and the corresponding control signal A 2n .
  • Step 202 If the power value is less than or equal to the first threshold, turn on one or more pairs of Outphasing power amplifiers in the Outphasing power amplifier array.
  • the DSP module 410 may be further based on the stored Outphasing power amplifier
  • the trigger condition of each pair of Outphasing power amplifier in the array determines the Outphasing power amplifier to be turned on.
  • the trigger condition of Outphasing PA 421a and Outphasing PA 422a is that the amplitude value of the input signal reaches the amplitude value 1
  • the trigger condition of Outphasing PA 421b and Outphasing PA 422b is that the amplitude value of the input signal reaches the amplitude value 2.
  • the DSP module 410 outputs two signals S 1 , S 2 and a control signal A 11 to turn on the Outphasing PA 421a and the Outphasing PA 422a.
  • the DSP module 410 outputs two signals S 1 , S 2 and control signals A 11 and A 12 to turn on Outphasing PA 421a, Outphasing PA 422a, Outphasing PA 421b, and Outphasing PA 422b.
  • step 102 Other details are similar to step 102, and will not be repeated here.
  • Step 203 If the power value is greater than the first threshold, turn on all the Outphasing power amplifiers in the Outphasing power amplifier array and one or more Polar power amplifiers in the Digital Polar power amplifier array.
  • the DSP module 410 may perform Ohtphasing transformation on the input signal to obtain two signals S 1 and S 2 , DSP The module 410 outputs S 1 , S 2 and the control signals A 1 ⁇ A 1n to the main power amplifier module 420 to turn on all the Outphasing power amplifiers in the Outphasing power amplifier array.
  • the Outphasng power amplifier will amplify the two signals separately, and output the processed signals to the Chireix synthesizer 423 in the main power amplifier module 420.
  • the DSP module 410 performs polarization processing on the input signal to obtain the input signal S 3 and the control signals A 21 ⁇ A 2n .
  • the DSP module 410 stores the trigger conditions of one or more power amplifiers in the Digital Polar power amplifier array.
  • the DSP module 410 can determine the Polar power amplifier to be turned on based on the amplitude value of the input signal or the phase value after Outphasing transformation and the trigger condition, and output corresponding control signals A 2n and S 3 .
  • step 103 Other details are similar to step 103, and will not be repeated here.
  • Figure 13 shows the efficiency curve based on ideal model simulation (including ideal voltage source, current source, ideal transmission line, etc.) using the technical solution in this embodiment. Among them, Ouphasing PA is quantized to 4-bit, and Polar PA is quantized to 3. -bit. Referring to FIG. 13, FIG. 13, FIG.
  • FIG. 14 is a schematic structural diagram of another signal processing system in an embodiment of the application.
  • the system includes: a DSP module 510, a main power amplifier module 520 in a Doherty load modulation mode, Auxiliary power amplification module 530, synthesis module 540, and feedback module 550.
  • the main power amplifier module 520 in the load modulation module may include two digital outphasing power amplifier arrays
  • the auxiliary power amplifier module 530 may include two digital outphasing power amplifier arrays.
  • the main power amplifier module 520 and the auxiliary power amplifier module 530 can implement the Doherty load modulation mode, that is, when the input signal is small, the main power amplifier module is turned on, and when the input signal is large, the main power amplifier module and the auxiliary power amplifier are turned on Module.
  • the DSP module can turn on two or more Outphasing power amplifiers in the main power amplifier module based on the trigger condition of each Outphasing power amplifier in the main power amplifier module.
  • the DSP module 510 can turn on all the Outphasing power amplifiers included in the main power amplifier module, and based on the trigger conditions of each pair of Outphasing amplifiers included in the auxiliary power amplifier module, turn on a pair or more Outphasing power amplifier in auxiliary power amplifier module.
  • the DSP module 510 can turn on all the Outphasing power amplifiers included in the main power amplifier module, and based on the trigger conditions of each pair of Outphasing amplifiers included in the auxiliary power amplifier module, turn on a pair or more Outphasing power amplifier in auxiliary power amplifier module.
  • FIG. 15 is a schematic structural diagram of a signal processing system in an embodiment of the application.
  • the system includes: a DSP module 610, a main power amplifier module 620 in a Doherty load modulation mode, and an auxiliary The power amplification module 630, the synthesis module 640, and the feedback module 650.
  • the main power amplifier module 620 also includes a Chireix synthesizer 621
  • the synthesis module 640 can be a Doherty synthesizer, where the Chireix synthesizer 621 and the Doherty synthesizer 640 use transformers to implement Chireix Outphasing and Doherty active loads Modulate and reduce the size of the system to achieve on-chip integration through CMOS technology. It should be noted that the structure in this embodiment can be applied to any of the systems shown in FIG. 4, or FIG. 11 and FIG. 14.
  • the main power module and/or the auxiliary power module including the Outphasing power amplifier or the Outphasing power amplifier array may adopt a Chireix synthesizer composed of a transformer, and the Doherty synthesizer also adopts a transformer structure.
  • the main power amplifier module in the Doherty load modulation mode may also be a Digital Polar array
  • the auxiliary power amplifier module may also be a traditional Outphasing power amplifier or a Digital Outphasing array.
  • the working mode of the system can refer to the above-mentioned embodiment, which is not repeated here.
  • the signal processing system may include n-channel load modulation modules, and n is an integer greater than 1, for example, Can include 3 load modulation modules.
  • the n-channel load modulation module includes a main power amplifier module and (n-1) auxiliary power amplifier modules.
  • each module in the multi-channel Doherty structure is similar to those described in the embodiments of this application, that is, the main power amplifier module can implement the Outphasing mode, and the (n-1) auxiliary power amplifier module can implement the Digital Outphasing mode and/or Digital Polar mode, in which the auxiliary power amplifier module is in a non-working state when the input signal is small, that is, the auxiliary power amplifier module is only turned on when the input signal is large.
  • the more the number of auxiliary power amplification modules in the system the higher the efficiency of the back-off zone and the greater the depth of the back-off zone.
  • the signal processing apparatus includes hardware structures and/or software modules corresponding to each function.
  • the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed by hardware or computer software-driven hardware depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.
  • the embodiment of the present application may divide the signal processing apparatus into functional modules according to the foregoing method examples.
  • each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module.
  • the above-mentioned integrated modules can be implemented in the form of hardware or software functional modules. It should be noted that the division of modules in the embodiments of the present application is illustrative, and is only a logical function division, and there may be other division methods in actual implementation.
  • FIG. 16 shows a possible structural schematic diagram of the signal processing apparatus 700 involved in the above-mentioned embodiment.
  • the signal processing device may include: a control module 710, which is used to control the parallel-connected n-channel load modulation module to receive a signal; wherein, the control module 710 may be further configured to be based on the power value of the signal , Turn on one or more load modulation modules among the n-channel load modulation modules.
  • the embodiments of the present application also provide a computer-readable storage medium, the computer-readable storage medium stores a computer program, the computer program includes at least one piece of code, the at least one piece of code can be executed by the signal processing device to The control signal processing device is used to implement the above method embodiments.
  • the embodiments of the present application also provide a computer program, which is used to implement the foregoing method embodiments when the computer program is executed by the signal processing apparatus.
  • the program may be stored in whole or in part on a storage medium packaged with the processor, or may be stored in part or in a memory not packaged with the processor.
  • an embodiment of the present application further provides a processor, which is configured to implement the foregoing method embodiment.
  • the aforementioned processor may be a chip.
  • the steps of the method or algorithm described in combination with the disclosure of the embodiments of the present application may be implemented in a hardware manner, or may be implemented in a manner in which a processor executes software instructions.
  • Software instructions can be composed of corresponding software modules, which can be stored in random access memory (Random Access Memory, RAM), flash memory, read-only memory (Read Only Memory, ROM), and erasable programmable read-only memory ( Erasable Programmable ROM (EPROM), Electrically Erasable Programmable Read-Only Memory (Electrically EPROM, EEPROM), register, hard disk, mobile hard disk, CD-ROM or any other form of storage medium known in the art.
  • RAM Random Access Memory
  • ROM read-only memory
  • EPROM Erasable Programmable ROM
  • EPROM Electrically Erasable Programmable Read-Only Memory
  • register hard disk, mobile hard disk, CD-ROM or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor, so that the processor can read information from the storage medium and can write information to the storage medium.
  • the storage medium may also be an integral part of the processor.
  • the processor and the storage medium may be located in the ASIC.
  • the ASIC may be located in a network device.
  • the processor and storage medium can also exist as discrete components in the network device.
  • the functions described in the embodiments of the present application may be implemented by hardware, software, firmware, or any combination thereof. When implemented by software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on the computer-readable medium.
  • the computer-readable medium includes a computer storage medium and a communication medium, where the communication medium includes any medium that facilitates the transfer of a computer program from one place to another.
  • the storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer.

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Abstract

本申请实施例提供了一种信号处理方法、装置及系统，该系统包括n路负载调制模块、以及合成模块；其中，所述n路负载调制模块并联，并且，每路所述负载调制模块的输出端与所述合成模块的输入端相连，n为大于1的整数；以及，所述n路负载调制模块中包括一路主功率放大模块和（n-1）路辅功率放大模块，其中，所述辅功率放大模块在所述负载调制模块的输入端接收到的信号的功率值大于第一阈值时开启；其中，所述主功率放大模块包括两个Outphasing功率放大单元，以及，每路所述辅功率放大模块包括两个Outphasing功率放大器阵列或一个Digital Polar功率放大器阵列。从而提供了一种可有效提升回退区效率，尤其可实现深回退区效率的提升的系统。

Description

信号处理方法、装置及系统
本申请要求于2019年04月25日提交中国专利局、申请号为201910340782.6、申请名称为“信号处理方法、装置及系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及信号处理领域，尤其涉及一种信号处理方法、装置及系统。
背景技术
为了满足人们日益增长的网络速率要求，扩大信号带宽和增加频谱利用率是两种最常用的手段，例如：在无线WiFi技术中，信号带宽已经从802.11g中的20MHz扩大为802.11ac中的160MHz，并且，调制信号从正交频分复用(Orthogonal Frequency Division Multiplexing，OFDM)的64-QAM(Quadrature Amplitude Modulation，正交振幅调制)提升至OFDM 256-QAM，对应速率从54Mbps提升至3.5Gbps；在移动通信技术中，信号带宽已从第四代移动通信技术(the 4th Generation mobile communication technology，4G)长期演进(Long Term Evolution，LTE)的20MHz扩大为第五代移动通信技术(the 5th generation mobile networks，5G)的100MHz，对应速率从100Mbps提升至1Gbps以上；在同轴有线接入(Data Over Cable Service Interface Specifications，DOCSIS)技术中，信号带宽已经从DOCSIS 1.0的860MHz扩大为DOCSIS 3.1的1GHz，调制信号从单载波64/256-QAM提升至OFDM 4096-QAM，对应速率从38Mbps提升至10Gbps。
综上所述，目前常见的通信系统中的信号均具有大带宽、高阶QAM调制的特点，但是，通常情况下，大带宽、高阶QAM调制的信号将会导致信号的峰均比(Peak-to-Average-Ratio，PAR)的增加。为了保证信号的无损传输，通信链路中的功能模块需要根据PAR工作于回退区。
功率放大器(Power Amplifier,PA)作为通信链路中的核心功能模块之一，面对目前信号的带宽的扩展，要求PA具有更高的线性度，而PAR的变大会使PA回退至更低的效率区域，导致系统能量损耗，温度升高，进而需要增加复杂的散热系统设计。所以，如何设计高效率的PA，以满足目前的大带宽、高PAR信号的传输需求，成为亟需解决的问题。
在已有技术的Doherty功率放大器、Class-G功率放大器等结构中，对应的回退区为6dB大小。为提升回退区效率，已有技术通常采用增加Doherty功率放大器中的辅放大器路数等方式。但是，该种方式在提升回退区效率的同时，将会大幅度增加功率放大器的尺寸。
发明内容
本申请提供一种信号处理方法、装置及系统，能够有效提升回退区效率。
为达到上述目的，本申请采用如下技术方案：
第一方面，本申请实施例提供一种信号处理系统，该系统包括：n路负载调制模块、以及合成模块；其中，n路负载调制模块并联，并且，每路负载调制模块的输出端与合成模块的输入端相连，n为大于1的整数，其中，合成模块通过所述输入端接收所述n个负载调制模块输出的n路信号，并对n路信号进行合成处理；以及，n路负载调制模块中包括一路主功率放大模块和(n-1)路辅功率放大模块，其中，辅功率放大模块在负载调制模块的输入端接收到的信号的功率值大于第一阈值时开启；其中，主功率放大模块包括两个异相Outphasing功率放大单元，以及，每路辅功率放大模块包括两个Outphasing功率放大器阵列或一个数字极化Digital Polar功率放大器阵列。
通过上述方式，本申请提供了一种不需要辅放大器路数，但可有效提升回退区效率，尤其可实现深回退区效率的提升的系统。
在一种可能的实现方式中，其中，Outpahsing功率放大单元包括一个Digital Outphasing功率放大器阵列。也就是说，两路中的每一路Outphasing功率放大单元包括一个Digital Outphasing功率放大器阵列，其中，每个Digital Outphasing阵列中包括两个或两个以上Outphasing功率放大器。从而在主功率放大模块开启时，进一步通过控制主功率放大模块中的Outphasing功率放大器的开启数量，以提升回退区效率。
在一种可能的实现方式中，两个Outphasing功率放大单元并联。
在一种可能的实现方式中，主功率放大模块还包括合成单元，两路Outphasing功率放大单元的输出端分别与合成单元的输入端相连，以及，合成单元的输出端与合成模块的输入端相连，合成单元可用于通过所述输入端接收所述两路Outphasing功率放大单元输出的两路信号，并对所述两路信号进行合成处理；其中，合成单元与合成模块由变压器构成。
通过上述方式，实现了器件尺寸的减小，并可通过CMOS工艺，将系统在片上集成。
在一种可能的实现方式中，其中，第一合成单元为Chireix合成器，第二合成单元为多赫蒂Doherty合成器。
通过上述方式，实现了Chireix Outphasing与Doherty负载调制的结合。
第二方面，本申请实施例提供一种信号处理方法，该方法可应用于第一方面所述的信号处理系统中，该方法包括：通过并联的n路负载调制模块接收信号；基于信号的功率值，开启n路负载调制模块中的一路或一路以上负载调制模块；其中，若功率值小于或等于第一阈值，则开启n路负载调制模块中的一路主功率放大模块；若功率值大于第一阈值，则开启一路主功率放大模块和(n-1)路负载调制模块中的至少一路辅功率放大模块；其中，主功率放大模块包括两个异相Outphasing功率放大单元，以及，辅功率放大模块包括两个Outphasing功率放大器阵列或一个数字极化Digital Polar功率放大器阵列。
在一种可能的实现方式中，基于信号的功率值，开启n路负载调制模块中的一路或一路以上负载调制模块的步骤，包括：若信号的幅度值小于或等于第二阈值，则开启主功率放大模块；若信号的幅度值大于第二阈值，则开启至少一路辅功率放大模块。
在一种可能的实现方式中，开启一路主功率放大模块和(n-1)路负载调制模块中的至少一路辅功率放大模块的步骤，包括：若信号的幅度值满足Outphasing功率放大器阵列或Digital Polar功率放大器阵列中的一个或一个以上功率放大器的触发条件，则开启一个或一个以上功率放大器。
在一种可能的实现方式中，基于信号的功率值，开启n路负载调制模块中的一路或一路以上负载调制模块的步骤，包括：若信号的相位值大于或等于第三阈值，则开启主功率放大模块；若信号的相位值小于第三阈值，则开启至少一路辅功率放大模块；其中，相位值为将信号进行Outphasing变换后得到的。
在一种可能的实现方式中，开启一路主功率放大模块和(n-1)路负载调制模块中的至少一路辅功率放大模块的步骤，包括：若信号的相位值满足Outphasing功率放大器阵列或Digital Polar功率放大器阵列中的一个或一个以上功率放大器的触发条件，则开启一个或一个以上功率放大器。
第三方面，本申请实施例提供一种信号处理装置，包括：控制模块，用于控制并联的n路负载调制模块接收信号；以及，控制模块可以进一步用于基于信号的功率值，开启n路负载调制模块中的一路或一路以上负载调制模块；其中，若功率值小于或等于第一阈值，则开启n路负载调制模块中的一路主功率放大模块；若功率值大于第一阈值，则开启一路主功率放大模块和(n-1)路负载调制模块中的至少一路辅功率放大模块；其中，主功率放大模块包括两个异相Outphasing功率放大单元，以及，辅功率放大模块包括两个Outphasing功率放大器阵列或一个数字极化Digital Polar功率放大器阵列。
在一种可能的实现方式中，控制模块进一步用于：若信号的幅度值小于或等于第二阈值，则开启主功率放大模块；若信号的幅度值大于第二阈值，则开启至少一路辅功率放大模块。
在一种可能的实现方式中，控制模块进一步用于：若信号的幅度值满足Outphasing功率放大器阵列或Digital Polar功率放大器阵列中的一个或一个以上功率放大器的触发条件，则开启一个或一个以上功率放大器。
在一种可能的实现方式中，控制模块进一步用于：若信号的相位值大于或等于第三阈值，则开启主功率放大模块；若信号的相位值小于第三阈值，则开启至少一路辅功率 放大模块；其中，相位值为将信号进行Outphasing变换后得到的。
在一种可能的实现方式中，控制模块进一步用于：若信号的相位值满足Outphasing功率放大器阵列或Digital Polar功率放大器阵列中的一个或一个以上功率放大器的触发条件，则开启一个或一个以上功率放大器。
第四方面，本申请实施例提供了一种计算机可读介质，用于存储计算机程序，该计算机程序包括用于执行第二方面或第二方面的任意可能的实现方式中的方法的指令。
第五方面，本申请实施例提供了一种计算机程序，该计算机程序包括用于执行第二方面或第二方面的任意可能的实现方式中的方法的指令。
第六方面，本申请实施例提供了一种芯片，该芯片包括处理电路、收发管脚。其中，该收发管脚、和该处理器通过内部连接通路互相通信，该处理器执行第二方面或第二方面的任一种可能的实现方式中的方法，以控制接收管脚接收信号，以控制发送管脚发送信号。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是示例性示出的一种功率放大器结构示意图；
图2是示例性示出的效率曲线；
图3是示例性示出的一种功率放大器结构示意图；
图4是本申请实施例提供的一种信号处理系统的结构示意图之一；
图5是本申请实施例提供的一种信号处理方法的流程图之一；
图6是本申请实施例提供的一种极化方案的示意图之一；
图7是本申请实施例提供的一种极化方案的示意图之一；
图8是本申请实施例提供的信号的频谱图；
图9(a)～9(d)是本申请实施例中的Outphasing PA的负载阻抗变化曲线；
图10是本申请实施例提供的系统的效率曲线图；
图11是本申请实施例提供的一种信号处理系统的结构示意图之一；
图12是本申请实施例提供的一种信号处理方法的流程图之一；
图13是本申请实施例提供的系统的效率曲线图；
图14是本申请实施例提供的一种信号处理系统的结构示意图之一；
图15是本申请实施例提供的一种信号处理系统的结构示意图之一；
图16是本申请实施例提供的一种信号处理装置的结构示意图之一。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本文中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。
本申请实施例的说明书和权利要求书中的术语“第一”和“第二”等是用于区别不同的对象，而不是用于描述对象的特定顺序。例如，第一目标对象和第二目标对象等是用于区别不同的目标对象，而不是用于描述目标对象的特定顺序。
在本申请实施例中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
在本申请实施例的描述中，除非另有说明，“多个”的含义是指两个或两个以上。例如，多个处理单元是指两个或两个以上的处理单元；多个系统是指两个或两个以上的系统。
为了使本领域人员更好地理解本申请实施例中的技术方案，首先对已有技术进行介绍。
如图1所示为已有技术中的一种功率放大器结构的示意图。在图1中:
该功率放大器为多路模拟多赫蒂(Doherty)PA结构，其中包括主功率放大器110，以及两路辅功率放大器，分别为：辅功率放大器120、辅功率放大器130。
主功率放大器包括功率放大器111及功率放大器112，为两路异相(Outphasing)功率放大器。
两路辅放大器，还包括输入信号分离单元、输出信号合成器等(图中未标号)。
需要说明的是，在Doherty PA结构中，其工作原理为：在输入信号(或者可描述为输入信号的功率)较小时(输入信号较小的界定方式可以为，若输入信号的功率小于预设阈值，则输入信号为较小的信号，否则为较大信号)，辅功率放大器(例如图1中的两路辅功率放大器120和130)处于非工作状态，而主功率放大器处于工作状态。即，参照图1，此时，PA工作于Outphasing模式，即主功率放大器110处于工作状态，以对输入信号进行放大处理，其效率曲线形成如图2中所示的第一个回退区(即T1～T2)。在Doherty PA中，辅功率放大器在输入信号较大时开启(同时，主功率放大器仍然处于工作状态，即，输入信号较大时，主辅功率放大器均处于工作状态)。仍参照图1，随着输入信号变大，逐渐开启辅放大器120和130，此时，辅功率放大器120和辅功率放大器130与主功率放大器形成Doherty负载调制，效率曲线形成第二、第三个回退区。
在如图1所示的功率放大器结构中，回退区的大小由辅放大器的路数决定，即，在 图1所示的包含两路辅功率放大器的放大器结构中，则可在Outphasing主功率放大器的基础上新增两个回退点。而如果要继续增加回退点(即增加回退区大小，或者可以理解为提升回退区的效率)，则需要新增辅放大器的路数和对应的阻抗变换传输线，导致输出合成器的结构更为复杂，对应输入信号的分离也变得更加复杂，从而会降低整体PA的增益和效率。
如图3所示为已有技术中的另一种功率放大器的结构示意图。在图3中：
该功率放大器200中结合了传统的模拟Doherty PA和数字极化(Digital Polar)PA两种结构，其中，该已有技术中将Doherty PA中的辅功率放大器替换为Digital Polar PA(即图中220)，而主功率放大器依然是传统的模拟PA(即图中210)。基于Doherty PA的工作原理，在输入信号较小时，辅功率放大器全部关闭，仅主功率放大器210，即模拟PA处于工作状态。随着输入信号变大，逐渐开启Digital Polar(即辅功率放大器220)功率放大器阵列中的PA。此时，主辅两路PA之间形成Doherty负载调制。
基于图3所示的功率放大器结构，其所对应的回退区大小为6dB，即与传统的两路模拟Doherty PA所能达到的回退区大小相同，如图3所示的功率放大器还可以通过采用不对称Doherty结构，以进一步提高回退区的效率，即，增加回退区大小。但是，不对称Doherty PA中存在的问题为：若要达到较大的回退区，例如，实现深回退区(即12dB以上)，则辅功率放大器的功率至少要达到主功率放大器的功率的3倍大小，因此，辅功率放大器的尺寸则会相对增加(增加的幅度较大)，因此，在实际应用中，很难实现PA的深回退区的效率的提升。
综上，针对已有技术中存在的在提升回退区效率的同时，将会大幅度增加功率放大器的尺寸，从而增加工艺难度，进而无法实现深回退区的问题，本申请提出一种信号处理系统，该系统通过结合Outphasing与Doherty两种负载调制方式，在不需要增加额外辅放大器路数的同时，能有效提升回退区效率，进而实现深回退区。
如图4所示为本申请实施例中的信号处理系统的结构示意图，在图4中：
信号处理系统300包括数字信号处理(Digital Signal Processing，DSP)模块310、并联的两路负载调制模块，其中，两路负载调制模块包括主功率放大模块320、辅功率放大模块330，以及，信号处理系统300还包括合成模块340、反馈模块350。
参照图4，信号处理系统300中的DSP模块310的输出端分别与两路负载调制模块(即主功率放大模块320与辅功率放大模块330)的输入端相连接。以及，合成模块340的输入端分别与两路负载调制模块(即主功率放大模块320与辅功率放大模块330)的输出端相连接。以及，合成模块340的输出端连接反馈模块350的输入端，反馈模块350的输出端连接DSP模块310的输入端，从而形成反馈回路。反馈回路可用于PA输出信号的回采，并将采集的信号反馈至DSP模块进行失真、失配等不理想因素的校准等处理，反馈回路的具体处理方式可参照已有技术实施例中的技术方案，本申请不再赘述。
可选地，在本申请中，主功率放大模块320包括并联的两个Outphasing功率放大器(即图中的Outphasing功率放大器321和Outphasing功率放大器322)，以及合成单元323。可选地，合成单元323可以为低隔离度的Chireix合成器，由电感和电容组成。在 其它实施例中，合成器也可以为其它低隔离度的合成器，本申请对此不做限定。
DSP模块(例如DSP模块310)可以就是DSP处理器或者多个DSP处理的主要功能单元组合成的模块。
以及，辅功率放大模块330包括Digital Polar功率放大器阵列，即，辅功率放大器可量化为由多个(即两个或两个以上)极化功率放大器组成的阵列。
可选地，在本申请中，合成模块340包括但不限于：传输线341及合成器342。可选地，传输线341可以为λ/4传输线，用于Doherty负载调制的阻抗变换。可选地，在本申请中，合成器342可以为Doherty合成器。
结合图4，如图5所示为本申请实施例中的一种信号处理方法的流程图，该方法应用于如图4所示的信号处理系统中，方法包括：
步骤101，通过并联的负载调制模块接收信号。
具体的，在本申请的实施例中，DSP模块对信号(为区分其它的例如输出的信号等，在本实施例及下面的实施例中，将该信号统称为输入信号)进行数字信号处理，随后，DSP将处理后的输入信号通过输出端发送至两路负载调制模块的输入端。如图4所示，其中，输入两路负载调制模块的信号包括：两路Outphasing PA的输入信号S 1和S 2，以及Digital Polar PA的输入信号S 3和控制信号A 1～A n。
可选地，在本申请中，负载调制模块可构成Doherty PA结构，即，本申请中的负载调制模块之间可工作于Doherty负载调制模式。具体的，基于上文所述的Doherty PA的工作原理，即，在输入信号较小时，主功率放大器开启，而辅功率放大器关闭；在输入信号较大时，主功率放大器与辅功率放大器同时开启。
在本申请中，确定输入信号的大小的方式可包括两种，其一为：在本申请中，可设置幅度阈值，DSP可基于幅度阈值，判断输入信号的大小，并基于判断结果，确定对应于输入信号的处理方式。
具体的，参照图6，即，当输入信号的幅度小于或等于幅度阈值A th时，DSP将输入信号S in转换为两路信号S 1和S 2，并输出至主功率放大模块，从而使主功率放大模块处于工作状态，并进入步骤102。当输入信号的幅度值大于幅度阈值A th时，DSP将输入信号转换为：输入信号S 3、控制A 1～A n、以及两路信号S 1和S 2。其中，输入信号S 3、控制信号A 1～A n用于使辅功率放大模块处于工作状态，并进入步骤103，其中，控制信号A 1～A n开启辅功率放大模块中包括的功率放大器阵列中的一个或一个以上功率放大器的方式可参照步骤103。
举例说明：输入信号S in可表示为：
Figure PCTCN2019123584-appb-000001
其中A(t)为调幅信号，
Figure PCTCN2019123584-appb-000002
为调相信号，ω为载波频率。
DSP可基于输入信号的包络值，获取输入信号的幅度值大小，并基于幅度值大小，判定输入信号的功率大小(即，若幅度值小于或等于幅度阈值，则输入信号为较小的信号，对应的功率也较小，反之则为较大的输入信号)。
可选地，若DSP检测到输入信号较小，则，DSP模块对信号进行Outphasing处理，获得分离后的两路信号S 1和S 2表示为：
Figure PCTCN2019123584-appb-000003
Figure PCTCN2019123584-appb-000004
其中，A 0＝max(abs(A(t)))，θ(t)＝arccos(0.5*A(t)/A 0)，其中，θ(t)为相位值。
DSP模块310将两路两路信号S 1和S 2输出至主功率放大模块，以开启主功率放大模块320中的两路Outphasing功率放大器。
可选地，若DSP模块310检测到输入信号较大，则，DSP模块310对信号进行Outphasing处理，从而获得用于开启主功率放大模块的两路信号S 1和S 2。以及，DSP模块310对信号进行极化处理，从而获得用于开启辅功率放大模块的输入信号S 3和控制信号A 1～A n。DSP模块310对输入信号进行极化处理的具体细节可参照已有技术中的技术方案，本申请不再赘述。
在本申请中，确定输入信号的大小的另一种方式为：在本申请中，可设置相位阈值，DSP模块310可对输入信号S in进行Outphasing处理(处理过程可参照上文)，得到与幅度信息相关的相位值θ(t)∈[0π/2]。其中，输入信号的幅度越小，θ(t)值越大，反之，输入信号的幅度越大，则θ(t)值越小。
随着输入信号幅度的增加，控制信号A 1～A n控制辅功率放大模块330包括的Digital Polar放大器阵列中的Polar PA开启，由于幅度和θ(t)相关，所以可以将θ(t)直接转换为控制信号A 1～A n。如图7所示，幅度越大，θ(t)值越小，当θ(t)低于相位阈值θ th时，输出极化后的信号A 1～A n和S 3，以及Outphasing变换后的S 1和S 2，即，两路Outphasing功率放大器321和322与Digital Polar功率放大器阵列中的一个或一个以上Polar功率放大器均处于工作状态。
步骤102，若功率值小于或等于第一阈值，则开启负载调制模块中的一路主功率放大模块。
具体的，在本申请中，如上文所述，DSP模块310可基于输入信号的幅度值或可基于输入信号经Ouhtphasing变换后的相位值，判定输入信号的功率大小。即，幅度值小于或等于幅度阈值，或变换后的相位值大于或等于相位阈值时，可确定输入信号为较小信号，即，输入信号的功率值小于或等于功率阈值。若幅度值大于幅度阈值，或变换后的相位值小于相位阈值时，可确定输入信号为较大信号，即，输入信号的功率值大于功率阈值。
因此，在本申请中，若DSP确定输入信号为较小信号，则，如上文所述，DSP将输入信号进行Outphasing变换，得到两路信号S 1和S 2，并将S 1输出至主功率放大模块320中的Outphasing功率放大器321，以及，将S 2输出至主功率放大模块320中的Outphasing功率放大器322，以开启两路Outphasing放大器，Outphasng功率放大器将会分别对两路信号进行放大处理，并将处理后的信号输出至主功率放大模块320中的Chireix合成器323中。
随后，Chireix合成器将合成处理后的信号输出至合成模块340。信号经由传输线341传输至Doherty合成器342中，Doherty合成器342对信号进行处理，并通过输出端输出，以及，反馈回路采集Doherty合成器342的输出信号并反馈至DSP模块310。
步骤103，若功率值大于第一阈值，则开启主功率放大模块和辅功率放大模块。
仍参照图4，若DSP模块310确定输入信号为较大信号，则，如上文所述，可选地，DSP模块310可将输入信号进行Ouhtphasing变换，得到两路信号S 1和S 2，并将S 1输出至主功率放大模块320中的Outphasing功率放大器321，以及，将S 2输出至主功率放大模块320中的Outphasing功率放大器322，以开启两路Outphasing放大器，Outphasng功率放大器将会分别对两路信号进行放大处理，并将处理后的信号输出至主功率放大模块320中的Chireix合成器323中。以及，DSP模块310将输入信号进行极化处理，以获取输入信号S 3以及控制信号A 1～A n。
可选地，在本申请中，DSP模块310中存储Digital Polar功率放大器阵列中的一个或一个以上功率放大器的触发条件。
可选地，在本申请中，DSP模块310可基于幅度值的大小，判定是否满足Polar功率放大器的触发条件，若是，则向满足触发条件的Polar功率放大器发送控制信号。举例说明：Digital Polar放大器阵列中的Polar PA 331的触发条件为：当幅度值达到幅度值1(该值可根据实际需求进行设置，本申请不做限定)时，Polar PA 331开启。Polar PA 331的触发条件为幅度值达到幅度值2，Polar PA 333(图中未示出)的触发条件为幅度值达到幅度值3。则，在本申请中，DSP模块310在监测到输入信号的幅度值达到幅度值1时，则输出控制信号A 1，以控制Polar PA 331开启，并对输入信号S 3进行放大处理。若DSP模块310在监测到输入信号的幅度值达到幅度值2时，则输出控制信号A 1、A 2，以控制Polar PA 331和Polar PA 332开启。若DSP模块310在监测到输入信号的幅度值达到幅度值3时，则输出控制信号A 1、A 2、A 3，以控制Polar PA 331、Polar PA 332和Polar PA 333开启。
可选地，在本申请中，DSP模块310可基于经Outphasing变换后的信号的相位值的大小，判定是否满足Polar功率放大器的触发条件，若是，则向满足触发条件的Polar功率放大器发送控制信号。举例说明：Digital Polar中的Polar PA 331(的触发条件为：当相位值达到相位值1(该值可根据实际需求进行设置，本申请不做限定)时，Polar PA 331开启。Polar功率放大器2的触发条件为相位值达到相位值2，Polar PA 333的触发条件为相位值达到相位值3。则，在本申请中，DSP模块310在监测到Ouhtphasing变换后的输入信号的相位值达到相位值1时，则输出控制信号A 1，以控制Polar功率放大器1开启，并对输入信号S 3进行放大处理。若DSP模块310在监测到输入信号的相位值达到相位值2时，则输出控制信号A 1、A 2，以控制Polar Polar PA 331和Polar PA 332开启。若DSP模块310在监测到输入信号的相位值达到相位值3时，则输出控制信号A 1、A 2、A 3，以控制Polar PA 331、Polar PA 332和Polar PA 333开启。
相较于传统的极化方案，本申请仅需要对输入信号中的部分信号(即超过阈值的部分)作极化处理，如图8所示为不同极化方式处理后幅度信号的频谱图，完整极化后的幅度信号带宽扩展较大，而部分极化的方案，可以明显降低带宽扩展效果。例如，以取功率值等于-140dB/Hz作为参考，采用部分极化后，可以将幅度信号的扩展带宽从580MHz降至360MHz。因此，本申请通过对部分信号进行极化处理，从而可以有效降低带宽扩展效应。
如图9(a)～9(d)所示为本实施例中的Outphasing PA的负载阻抗变化曲线。其中， 图9(a)所示为仅开启Outphasing PA的负载阻抗变换曲线，即，在没有Doherty负载调制情况下(即图9(a)中所示)，两路Outphasing PA的负载阻抗随θ(t)的变化情况，由于Chireix补偿网络的作用，存在两个阻抗虚部等于零的点。图9(b)为开启Outphasing PA与Polar PA 331的负载阻抗变换曲线，由于Doherty负载调制效应的作用，此时两路Outphasing PA的负载阻抗会下降，在史密斯(Smith)圆图上左移；图9(c)为开启Outphasing PA、以及控制信号A 1、A 2开启Polar PA 331与Polar PA 332的负载阻抗变换曲线；图9(d)为开启Outphasing PA、以及控制信号A 1、A 2、A 3开启Polar PA 331、Polar PA 332与Polar PA 333的负载阻抗变换曲线。显然，随着Polar PA开启数量的增加，负载阻抗逐渐下降。
综上所述，由于Doherty负载调制效应，Outphasing PA的负载阻抗会相应下降，而且随着Polar PA开启数量的增加，Outphasing PA的负载阻抗越小，对应的输出功率越大。因此，本申请可通过控制Polar PA的开启数量，以调整输出功率的大小，从而适应不同的PAPR场景。举例说明：如图10所示为应用本实施例中的技术方案基于理想模型仿真(包括理想电压源、电流源、理想传输线等)效率曲线。参照图10，在n＝3时(即DSP模块310输出控制信号A 1、A 2、A 3，开启对应的Polar功率放大器)，在20.9dB回退区域依然可以获得很高的效率值，其中Outphasing的回退区域由Chireix补偿单元决定，此实施例中为9.2dB。
需要说明的是，如果输入信号的PAR为21dB，要求系统的峰值输出功率达到30dBm，对应的平均功率为9dBm，此时需要动态控制A 1、A 2、A 3的状态，以实现21dB深回退区效率的提升。如果输入信号的PAR为18dB，则要求峰值输出功率达到30dBm，对应的平均功率为12dBm，此时需要动态控制A 1、A 2的状态，以实现18dB深回退区效率的提升。如果输入信号的PAR为15dB，则要求峰值输出功率达到30dBm，对应的平均功率为15dBm，此时需要动态控制A 1的状态，以实现15dB深回退区效率的提升。如果输入送信号的PAR为9dB，则可以仅Outphasing PA放大器工作，也可以通过修改Chireix补偿网络，减小Outphasing PA的回退区，同时控制A 1、A 2、A 3的状态，实现9dB回退区效率的提升。
综上所述，本申请可通过灵活控制，实现不同PAR信号的高效率发射。也就是说，本申请可通过控制Digital Polar PA的开启数量，以满足不同PAR信号场景下的高效率要求。
如图11所示为本申请实施例中的信号处理系统的结构示意图，在图11中：
信号处理系统400包括DSP模块410、并联的两路负载调制模块，其中，两路负载调制模块包括主功率放大模块420、辅功率放大模块430，以及，信号处理系统400还包括合成模块440、反馈模块450。
参照图11，信号处理系统400中的DSP模块410的输出端分别与两路负载调制模块(即主功率放大模块420与辅功率放大模块430)的输入端相连接。以及，合成模块440的输入端分别与两路负载调制模块(即主功率放大模块420与辅功率放大模块430)的输出端相连接。以及，合成模块440的输出端连接反馈模块450的输入端，反馈模块450 的输出端连接DSP模块410的输入端，从而形成反馈回路。
可选地，在本申请中，主功率放大模块420包括并联的两个Outphasing功率放大阵列(即图中的Outphasing功率放大器阵列421和Outphasing功率放大器阵列422，其中，每个Outphasing功率放大器阵列中包括两个或两个以上Outphasing功率放大器，并且，需要说明的是，两路Outphasing功率放大器阵列中的Outphasing放大器为成对设置，举例说明：Outphasing功率放大器阵列421中的Outphasing PA 421a以及Outphasing功率放大器阵列422中的Outphasing PA 422a成对，即，控制信号A 11可用于控制Outphasing PA 421a以及Outphasing PA 422a)，即，Doherty PA中的主功率放大器量化为由多个Outphasing放大器组成的阵列。
可选地，在本申请中，主功率放大模块420还包括合成单元423。可选地，合成单元423可以为低隔离度的Chireix合成器，由电感和电容组成。在其它实施例中，合成器也可以为其它低隔离度的合成器，本申请对此不做限定。
以及，辅功率放大模块430包括Digital Polar功率放大器阵列，即，辅功率放大器可量化为由多个(即两个或两个以上)极化功率放大器组成的阵列。
以及，在本申请的实施例中，合成模块440包括传输线441及合成器442。
结合图11，如图12所示为本申请实施例中的一种信号处理方法，该方法应用于如图11所示的信号处理系统中，方法包括：
步骤201，通过并联的负载调制模块接收信号。
具体的，在本申请的实施例中，DSP模块对信号(为区分其它的例如输出的信号等，在本实施例及下面的实施例中，将该信号统称为输入信号)进行数字信号处理，随后，DSP将处理后的输入信号通过输出端发送至两路负载调制模块的输入端。如图11所示，其中，输入两路负载调制模块的信号包括：两路Outphasing PA的输入信号S 1、S 2、和控制信号A 11～A 1n，以及Digital Polar PA的输入信号S 3和控制信号A 21～A 2n。
可选地，在本申请中，负载调制模块可构成Doherty PA结构，即，本申请中的负载调制模块之间可工作于Doherty负载调制模式。具体的，基于上文所述的Doherty PA的工作原理，即，在输入信号较小时，主功率放大器开启，而辅功率放大器关闭；在输入信号较大时，主功率放大器与辅功率放大器同时开启。
在本申请中，确定输入信号的大小的方式可包括两种，具体可参照步骤101中的细节，此处不赘述。
与步骤101类似，在本实施例中，当输入信号较大时，DSP同样基于幅度值或经过Outphasing变换后的相位值，判定是否满足辅功率放大模块430中各个Digital Polar功率放大器的触发条件。若是，则输出S 3及对应的控制信号A 2n。
步骤202，若功率值小于或等于第一阈值，则开启Outphasing功率放大器阵列中的一对或一对以上Outphasing功率放大器。
可选地，在本申请中，在输入信号较小(即输入信号的幅度值小于或等于幅度阈值或经过Outphasing变换后的相位值大于)时，DSP模块410可进一步基于已存储的Outphasing功率放大器阵列中各对Outphasing功率放大器的触发条件，确定所要开启的Outphasing功率放大器。举例说明：Outphasing PA 421a与Outphasing PA 422a的触发条 件为输入信号的幅度值达到幅度值1，Outphasing PA 421b与Outphasing PA 422b的触发条件为输入信号的幅度值达到幅度值2。则，当输入信号的幅度值达到幅度值1时，DSP模块410输出两路信号S 1、S 2以及控制信号A 11，以开启Outphasing PA 421a与Outphasing PA 422a。当输入信号的幅度值达到幅度值2时，DSP模块410输出两路信号S 1、S 2以及控制信号A 11、A 12，以开启Outphasing PA 421a、Outphasing PA 422a、Outphasing PA 421b、与Outphasing PA 422b。
其它细节与步骤102类似，此处不赘述。
步骤203，若功率值大于第一阈值，则开启Outphasing功率放大器阵列中的所有Outphasing功率放大器以及Digital Polar功率放大器阵列中的一个或一个以上Polar功率放大器。
仍参照图11，若DSP模块410确定输入信号为较大信号，则，如上文所述，可选地，DSP模块410可将输入信号进行Ouhtphasing变换，得到两路信号S 1和S 2，DSP模块410将S 1、S 2以及控制信号A 1～A 1n输出至主功率放大模块420，以开启Outphasing功率放大器阵列中的所有Outphasing功率放大器。Outphasng功率放大器将会分别对两路信号进行放大处理，并将处理后的信号输出至主功率放大模块420中的Chireix合成器423中。以及，DSP模块410将输入信号进行极化处理，以获取输入信号S 3以及控制信号A 21～A 2n。
可选地，在本申请中，DSP模块410中存储Digital Polar功率放大器阵列中的一个或一个以上功率放大器的触发条件。DSP模块410可基于输入信号的幅度值或经过Outphasing变换后的相位值以及触发条件，确定所要开启的Polar功率放大器，并输出相应的控制信号A 2n和S 3。
其他细节与步骤103类似，此处不赘述。
如图13所示为应用本实施例中的技术方案基于理想模型仿真(包括理想电压源、电流源、理想传输线等)的效率曲线，其中，Ouphasing PA量化成4-bit，Polar PA量化成3-bit。参照图13，在图3中示出开启多种数量组合的功率放大器对应的效率曲线，其中包括在仅开启Outphasing功率放大器(即仅开启主功率放大器模块420)中的控制信号A 11所控制的Outphasing功率放大器开启时对应效率曲线；开启Outphasing功率放大器中的控制信号A 11、A 12所控制的Outphasing功率放大器开启时对应效率曲线；开启Outphasing功率放大器中的控制信号A 11、A 12、A 13所控制的Outphasing功率放大器开启时对应效率曲线；开启Outphasing功率放大器中的控制信号A 11、A 12、A 13、A 14所控制的Outphasing功率放大器开启时对应效率曲线；开启主功率放大模块中的所有Outphasing功率放大器以及开启Digital Polar功率放大器阵列中的控制信号A 21所控制的Polar功率放大器时对应效率曲线；开启主功率放大模块中的所有Outphasing功率放大器以及开启Digital Polar功率放大器阵列中的控制信号A 21、A 22所控制的Polar功率放大器时对应效率曲线；以及，开启主功率放大模块中的所有Outphasing功率放大器以及开启Digital Polar功率放大器阵列中的所有Polar功率放大器时对应效率曲线；显然，在33dB回退区域(即开启所有功率放大器时)系统依然可以获得很高的效率值，从而进一步提高了回退区效率。
可选地，如图14所示为本申请实施例中的另一种信号处理系统的结构示意图，在图14中，系统包括：DSP模块510、处于Doherty负载调制模式的主功率放大模块520、辅功率放大模块530、合成模块540以及反馈模块550。其中，负载调制模块中的主功率放大模块520可以包括两路Digital Outphasing功率放大器阵列，辅功率放大模块530可包括两路Digital Outphasing功率放大器阵列。其中，主功率放大模块520与辅功率放大模块530可实现Doherty负载调制模式，即，在输入信号较小时，开启主功率放大模块，在输入信号较大时，开启主功率放大模块和辅功率放大模块。可选地，在输入信号较小时，DSP模块可基于主功率放大模块中的各个Outphasing功率放大器的触发条件，开启主功率放大模块中的两个或两个以上Outphasing功率放大器。以及，在输入信号较大时，DSP模块510可开启主功率放大模块中包括的全部Outphasing功率放大器，并基于辅功率放大模块中包含的每对Outphasing放大器的触发条件，开启一对或一对以上辅功率放大模块中的Outphasing功率放大器。具体细节可参照上述实施例，此处不赘述。
可选地，如图15所示为本申请实施例中的有一种信号处理系统的结构示意图，在图15中，系统包括：DSP模块610、处于Doherty负载调制模式的主功率放大模块620、辅功率放大模块630、合成模块640以及反馈模块650。可选地，主功率放大模块620中还包括Chireix合成器621，合成模块640可以为Doherty合成器，其中，Chireix合成器621与Doherty合成器640采用变压器，以实现Chireix Outphasing与Doherty的有源负载调制，并且，减小系统的尺寸，以通过CMOS工艺实现片上集成。需要说明的是，该实施例中的结构可应用于如图4、或图11以及图14所示的任一种系统中。即，包括Outphasing功率放大器或Outphasing功率放大器阵列的主功率模块和/或辅功率模块中可采用由变压器构成的Chireix合成器，并且，Doherty合成器同样采用变压器结构。
可选地，在本申请中，处于Doherty负载调制模式的主功率放大模块也可以为Digital Polar阵列，以及，辅功率放大模块以及为传统Outphasing功率放大器或Digital Outphasing阵列。系统的工作方式可参照上述实施例，此处不赘述。
需要说明的是，在本申请中仅以两路Doherty结构为例进行介绍，可选的，在本申请中，信号处理系统中可包括n路负载调制模块，n为大于1的整数，例如，可以包括3路负载调制模块。其中，n路负载调制模块中包括一路主功率放大模块，以及(n-1)路辅功率放大模块。多路Doherty结构中各个模块的功能与本申请实施例中的所述的类似，即，主功率放大模块可实现Outphasing模式，(n-1)路辅功率放大模块可实现Digital Outphasing模式和/或Digital Polar模式，其中，辅功率放大模块在输入信号较小时处于非工作状态，即，辅功率放大模块仅在输入信号较大时开启。在本申请中，系统中存在的辅功率放大模块的路数越多，则回退区的效率越高，回退区深度越大。但是，考虑到系统复杂度的限制，通常可采用n＝2的两路负载调制结构，以在可实现工艺的目标下，达到深回退区。
上述主要从各个网元之间交互的角度对本申请实施例提供的方案进行了介绍。可以理解的是，信号处理装置为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，本申请实施例能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
本申请实施例可以根据上述方法示例对信号处理装置进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
在采用对应各个功能划分各个功能模块的情况下，在采用对应各个功能划分各个功能模块的情况下，图16示出了上述实施例中所涉及的信号处理装置700的一种可能的结构示意图，如图16所示，信号处理装置可以包括：控制模块710，该模块用于控制并联的n路负载调制模块接收信号；其中，所述控制模块710还可以进一步用于基于所述信号的功率值，开启所述n路负载调制模块中的一路或一路以上负载调制模块。
其中，上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
基于相同的技术构思，本申请实施例还提供一种计算机可读存储介质，该计算机可读存储介质存储有计算机程序，该计算机程序包含至少一段代码，该至少一段代码可由信号处理装置执行，以控制信号处理装置用以实现上述方法实施例。
基于相同的技术构思，本申请实施例还提供一种计算机程序，当该计算机程序被信号处理装置执行时，用以实现上述方法实施例。
所述程序可以全部或者部分存储在与处理器封装在一起的存储介质上，也可以部分或者全部存储在不与处理器封装在一起的存储器上。
基于相同的技术构思，本申请实施例还提供一种处理器，该处理器用以实现上述方法实施例。上述处理器可以为芯片。
结合本申请实施例公开内容所描述的方法或者算法的步骤可以硬件的方式来实现，也可以是由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器(Random Access Memory，RAM)、闪存、只读存储器(Read Only Memory，ROM)、可擦除可编程只读存储器(Erasable Programmable ROM，EPROM)、电可擦可编程只读存储器(Electrically EPROM，EEPROM)、寄存器、硬盘、移动硬盘、只读光盘(CD-ROM)或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。另外，该ASIC可以位于网络设备中。当然，处理器和存储介 质也可以作为分立组件存在于网络设备中。
本领域技术人员应该可以意识到，在上述一个或多个示例中，本申请实施例所描述的功能可以用硬件、软件、固件或它们的任意组合来实现。当使用软件实现时，可以将这些功能存储在计算机可读介质中或者作为计算机可读介质上的一个或多个指令或代码进行传输。计算机可读介质包括计算机存储介质和通信介质，其中通信介质包括便于从一个地方向另一个地方传送计算机程序的任何介质。存储介质可以是通用或专用计算机能够存取的任何可用介质。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (16)

  1. 一种信号处理系统，其特征在于，包括n路负载调制模块、以及合成模块；
    其中，所述n路负载调制模块并联，并且，每路所述负载调制模块的输出端与所述合成模块的输入端相连，n为大于1的整数，其中，所述合成模块通过所述输入端接收所述n个负载调制模块输出的n路信号，并对所述n路信号进行合成处理；
    以及，所述n路负载调制模块中包括一路主功率放大模块和(n-1)路辅功率放大模块，其中，所述辅功率放大模块在所述负载调制模块的输入端接收到的信号的功率值大于第一阈值时开启；
    其中，所述主功率放大模块包括两个异相Outphasing功率放大单元，以及，每路所述辅功率放大模块包括两个Outphasing功率放大器阵列或一个数字极化Digital Polar功率放大器阵列；
  2. 根据权利要求1所述的系统，其特征在于，其中，所述Outpahsing功率放大单元包括一个数字异相Digital Outphasing功率放大器阵列。
  3. 根据权利要求1或2所述的系统，其特征在于，所述两个Outphasing功率放大单元并联。
  4. 根据权利要求1至3任一项所述的系统，其特征在于，所述主功率放大模块还包括合成单元，所述两路Outphasing功率放大单元的输出端分别与所述合成单元的输入端相连，以及，所述合成单元的输出端与所述合成模块的输入端相连，所述合成单元用于通过所述输入端接收所述两路Outphasing功率放大单元输出的两路信号，并对所述两路信号进行合成处理；
    其中，所述合成单元与所述合成模块由变压器构成。
  5. 根据权利要求4所述的系统，其特征在于，其中，所述合成单元为希莱克斯Chireix合成器，所述合成模块为多赫蒂Doherty合成器。
  6. 一种信号处理方法，其特征在于，包括：
    通过并联的n路负载调制模块接收信号；
    基于所述信号的功率值，开启所述n路负载调制模块中的一路或一路以上负载调制模块；
    其中，若所述功率值小于或等于第一阈值，则开启所述n路负载调制模块中的一路主功率放大模块；
    若所述功率值大于所述第一阈值，则开启所述一路主功率放大模块和(n-1)路负载调制模块中的至少一路辅功率放大模块；
    其中，所述主功率放大模块包括两个异相Outphasing功率放大单元，以及，所述辅 功率放大模块包括两个Outphasing功率放大器阵列或一个数字极化Digital Polar功率放大器阵列。
  7. 根据权利要求6所述的方法，其特征在于，所述基于所述信号的功率值，开启所述n路负载调制模块中的一路或一路以上负载调制模块的步骤，包括：
    若所述信号的幅度值小于或等于第二阈值，则开启所述主功率放大模块；
    若所述信号的幅度值大于所述第二阈值，则开启所述至少一路辅功率放大模块。
  8. 根据权利要求6或7所述的方法，其特征在于，所述开启所述一路主功率放大模块和(n-1)路负载调制模块中的至少一路辅功率放大模块的步骤，包括：
    若所述信号的幅度值满足所述Outphasing功率放大器阵列或所述Digital Polar功率放大器阵列中的一个或一个以上功率放大器的触发条件，则开启所述一个或一个以上功率放大器。
  9. 根据权利要求6所述的方法，其特征在于，所述基于所述信号的功率值，开启所述n路负载调制模块中的一路或一路以上负载调制模块的步骤，包括：
    若所述信号的相位值大于或等于第三阈值，则开启所述主功率放大模块；
    若所述信号的相位值小于所述第三阈值，则开启所述至少一路辅功率放大模块；
    其中，所述相位值为将所述信号进行Outphasing变换后得到的。
  10. 根据权利要求9所述的方法，其特征在于，所述开启所述一路主功率放大模块和(n-1)路负载调制模块中的至少一路辅功率放大模块的步骤，包括：
    若所述信号的相位值满足所述Outphasing功率放大器阵列或所述Digital Polar功率放大器阵列中的一个或一个以上功率放大器的触发条件，则开启所述一个或一个以上功率放大器。
  11. 一种信号处理装置，其特征在于，包括：
    控制模块，用于控制并联的n路负载调制模块接收信号；
    所述控制模块进一步用于基于所述信号的功率值，开启所述n路负载调制模块中的一路或一路以上负载调制模块；
    其中，若所述功率值小于或等于第一阈值，则开启所述n路负载调制模块中的一路主功率放大模块；
    若所述功率值大于所述第一阈值，则开启所述一路主功率放大模块和(n-1)路负载调制模块中的至少一路辅功率放大模块；
    其中，所述主功率放大模块包括两个异相Outphasing功率放大单元，以及，所述辅功率放大模块包括两个Outphasing功率放大器阵列或一个数字极化Digital Polar功率放大器阵列。
  12. 根据权利要求11所述的装置，其特征在于，所述控制模块进一步用于：
    若所述信号的幅度值小于或等于第二阈值，则开启所述主功率放大模块；
    若所述信号的幅度值大于所述第二阈值，则开启所述至少一路辅功率放大模块。
  13. 根据权利要11或12所述的装置，其特征在于，所述控制模块进一步用于：
    若所述信号的幅度值满足所述Outphasing功率放大器阵列或所述Digital Polar功率放大器阵列中的一个或一个以上功率放大器的触发条件，则开启所述一个或一个以上功率放大器。
  14. 根据权利要求11所述的装置，其特征在于，所述控制模块进一步用于：
    若所述信号的相位值大于或等于第三阈值，则开启所述主功率放大模块；
    若所述信号的相位值小于所述第三阈值，则开启所述至少一路辅功率放大模块；
    其中，所述相位值为将所述信号进行Outphasing变换后得到的。
  15. 根据权利要求14所述的装置，其特征在于，所述控制模块进一步用于：
    若所述信号的相位值满足所述Outphasing功率放大器阵列或所述Digital Polar功率放大器阵列中的一个或一个以上功率放大器的触发条件，则开启所述一个或一个以上功率放大器。
  16. 一种芯片，所述处理电路、收发管脚；其中，所述收发管脚、和该处理器通过内部连接通路互相通信，所述处理电路用于如权利要求6-10任一项所述的方法。
PCT/CN2019/123584 2019-04-25 2019-12-06 信号处理方法、装置及系统 Ceased WO2020215732A1 (zh)

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