WO2020238824A1 - 一种逆变电路、逆变器及光伏发电系统 - Google Patents

一种逆变电路、逆变器及光伏发电系统 Download PDF

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Publication number
WO2020238824A1
WO2020238824A1 PCT/CN2020/091982 CN2020091982W WO2020238824A1 WO 2020238824 A1 WO2020238824 A1 WO 2020238824A1 CN 2020091982 W CN2020091982 W CN 2020091982W WO 2020238824 A1 WO2020238824 A1 WO 2020238824A1
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WO
WIPO (PCT)
Prior art keywords
capacitor
inverter
switching tube
inductor
csy2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/091982
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English (en)
French (fr)
Inventor
王德臣
石鹏
马征
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to EP20813181.3A priority Critical patent/EP3958455B1/en
Publication of WO2020238824A1 publication Critical patent/WO2020238824A1/zh
Priority to US17/536,624 priority patent/US12034380B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/34—Snubber circuits
    • H02M1/346—Passive non-dissipative snubbers
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from AC input or output
    • H02M1/126—Arrangements for reducing harmonics from AC input or output using passive filters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H02M1/34—Snubber circuits
    • H02M1/348—Passive dissipative snubbers
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/56—Power conversion systems, e.g. maximum power point trackers

Definitions

  • This application relates to the technical field of voltage conversion, in particular to an inverter circuit, an inverter and a photovoltaic power generation system.
  • a photovoltaic power generation system includes photovoltaic components, inverters, transformers, cables and other components.
  • the inverter is the core component of photovoltaic power generation system energy conversion, which converts the DC power output by the photovoltaic components into AC power available to the grid. effect.
  • inverters are also widely used in other systems that need to convert direct current into alternating current.
  • the HERIC topology includes a first vertical bridge and a second vertical bridge, wherein both ends of the first vertical bridge are connected to the first switching tube and the second switching tube, and the second vertical bridge
  • the third switch tube and the fourth switch tube are respectively connected to the two ends.
  • the first switch tube and the fourth switch tube are closed.
  • the first switch tube and the fourth switch tube are closed.
  • the switching tubes are disconnected at the same time.
  • the disconnection speed of the first switching tube and the fourth switching tube cannot be kept exactly the same.
  • the disconnecting speed of the fourth switching tube is faster than that of the first switching tube.
  • the voltage on the first vertical bridge and the second vertical bridge will rise, and after the first switch tube is turned off, the voltage will fall again, and resonance will occur in the process.
  • EMC electromagnetic compatibility
  • the embodiments of the present application provide an inverter circuit, an inverter, and a photovoltaic power generation system.
  • the scheme of adding a jumper capacitor to the bus bar at the connection point of the vertical bridge and the horizontal bridge in the HERIC topology can prevent the power circuit from working normally due to switching Resonance problems caused by differences in turn-off speeds.
  • the first aspect of the present application provides an inverter circuit, including: a bus, a first vertical bridge, a second vertical bridge, a horizontal bridge, and a filter, wherein a capacitor bank is provided on the bus, and the bus is connected in parallel with a DC power supply.
  • the capacitor group includes a first capacitor and a second capacitor arranged in series, wherein the first capacitor is arranged on the side where the bus bar is connected to the positive electrode of the DC power supply, and the second capacitor is arranged on the bus bar connected to the negative electrode of the DC power supply On one side, the first capacitor and the second capacitor are used to be charged by the DC power supply to provide a DC voltage to the first vertical bridge, the second vertical bridge, and the horizontal bridge; the bus bar and the first vertical bridge In parallel, the first vertical bridge is connected in parallel with the second vertical bridge, the first vertical bridge includes a first switching tube and a second switching tube connected in series, and the second vertical bridge includes a third switching tube and a fourth switching tube connected in series , The two ends of the horizontal bridge are respectively connected to the first vertical bridge and the second vertical bridge; the filter is connected in parallel on the horizontal bridge, the filter is connected to the AC power grid, and the horizontal bridge is used to pass the filter to the AC power supply; the inverter circuit further includes: a third capacitor connected between the bus bar and the first
  • the third capacitor and the fourth capacitor are connected between the first vertical bridge and the bus bar, and between the second vertical bridge and the bus bar, so that the first When the first switching tube and the fourth switching tube are disconnected, the third capacitor can stabilize the voltage difference caused by the different disconnection speeds of the two switching tubes, thereby preventing the occurrence of resonance and effectively preventing EMC problems caused by resonance. .
  • the fourth capacitor can stabilize the voltage difference caused by the different disconnection speeds of the two switching tubes, thereby stabilizing the voltage in the negative half cycle of the DC to AC conversion. Prevent the occurrence of resonance phenomenon.
  • At least one inductor is arranged in series on the line where the third capacitor is located, and/or at least one inductor is arranged in series on the line where the fourth capacitor is located.
  • At least one inductor connected in series with the third capacitor and/or in series with the fourth capacitor can protect the third capacitor and or the fourth capacitor during charging and discharging.
  • At least one resistor is connected in series on the line where the third capacitor is located, and/or at least one resistor is connected in series on the line where the fourth capacitor is located.
  • At least one resistor connected in series to the third capacitor, and/or in series to the fourth capacitor, during the charging and discharging process, the resistor can pass the charge and discharge current to the third capacitor and or the fourth capacitor. Play a protective role.
  • At least one inductor and at least one resistor are arranged in series on the line where the third capacitor is located, and/or at least one resistor is arranged in series on the line where the fourth capacitor is located Inductance and at least one resistance.
  • At least one resistor and at least one inductor are connected in series to the third capacitor, and/or at least one inductor is connected in series to the fourth capacitor.
  • the capacitor and or the fourth capacitor play a protective role.
  • connection point between the line where the third capacitor is located and the bus bar, and the line where the fourth capacitor is located and The connection points of the bus bar are all arranged between the first capacitor and the second capacitor.
  • the third capacitor and the fourth capacitor are both connected across the first capacitor and the second capacitor on the bus, so that the first capacitor and the third capacitor form a parallel circuit, and the second capacitor and the fourth capacitor form a parallel circuit. Circuit, so that when the first switching tube and the fourth switching tube are closed, the voltage of the third capacitor is equal to the voltage of the first capacitor, and the voltage of the bus bar, the first vertical bridge and the second vertical bridge is increased during the positive half cycle of the inverter output. When the second switching tube and the third switching tube are closed, the voltage of the fourth capacitor is equal to the voltage of the second capacitor, and the voltage on the bus, the first vertical bridge and the second vertical bridge is in the negative half cycle of the inverter output.
  • the voltage of the first capacitor causes the circuit to pass through the third capacitor, the first inductor, the AC power grid, and the second capacitor in sequence.
  • the inductor, the fourth capacitor and the second capacitor are respectively charged with 1/2 bus voltage.
  • connection point between the line where the third capacitor is located and the bus bar, and the line where the fourth capacitor is located and The connection points of the bus bar are not arranged between the first capacitor and the second capacitor.
  • connection point between the line where the third capacitor is located and the bus bar and the connection point between the line where the fourth capacitor is located and the bus bar are both set between the first capacitor and the DC power source; or, the line where the third capacitor is located and the bus
  • the connection point of the bus bar and the connection point between the line where the fourth capacitor is located and the bus bar are both set between the second capacitor and the DC power supply; or, the connection point between the line where the third capacitor is located and the bus bar is set between the first capacitor and the DC power supply
  • connection point between the line where the fourth capacitor is located and the bus bar is set between the second capacitor and the DC power supply; or, the connection point between the line where the third capacitor is located and the bus bar is set between the second capacitor and the DC power supply.
  • the connection point between the line where the four capacitors are located and the bus bar is arranged between the first capacitor and the DC power supply.
  • the third The capacitor can absorb voltage fluctuations, thereby stabilizing the circuit.
  • the fourth capacitor can absorb the voltage fluctuations, thereby stabilizing the circuit. Therefore, it can effectively prevent resonance problems due to different switching speeds.
  • connection point between the line where the third capacitor is located and the bus bar and the line where the fourth capacitor is located Among the connection points with the bus bar, only one connection point is arranged between the first capacitor and the second capacitor.
  • the connection point between the third capacitor and the bus bar may be set between the first capacitor and the second capacitor
  • the connection point between the line where the fourth capacitor is located and the bus bar may be set between the first capacitor and the DC power source or the second capacitor.
  • connection point between the fourth capacitor and the bus bar can be set between the first capacitor and the second capacitor, and the connection point between the line where the third capacitor is located and the bus bar is set at the first Between the capacitor and the DC power source or between the second capacitor and the DC power source.
  • one of the third capacitor or the fourth capacitor is connected across the first capacitor and the second capacitor, and the other is connected across the capacitor bank and the DC power supply, so that the first switch tube and the second capacitor
  • the third capacitor can absorb voltage fluctuations at the moment the four switch tubes are disconnected, thereby stabilizing the circuit.
  • the fourth capacitor can absorb voltage fluctuations Therefore, it can effectively prevent resonance problems due to different switching speeds, but it will bring certain circuit losses.
  • the filter in a seventh possible implementation manner, includes a first inductor and a second inductor, and the cross bridge includes a freewheeling switch group , Wherein the first inductor is connected between the first vertical bridge and the AC power grid, the second inductor is connected between the AC power grid and the second vertical bridge, and the freewheeling switch group is connected in parallel with the first inductor And the second inductor.
  • the inverter circuit further includes a fifth capacitor connected in parallel between the first inductor and the second inductor, and the fifth capacitor is used to stabilize the voltage of the filter.
  • the freewheeling switch group includes a fifth switch tube and a sixth switch tube connected in series, wherein the fifth switch tube and the The sixth switch tube can be a MOS tube or an IGBT device,
  • the fifth switching tube and the sixth switching tube are controlled to control the circuit from the on phase to the freewheeling phase, so that the excited first inductor and the second inductor are connected to the AC grid.
  • the inverter circuit provided by the embodiment of the present application can connect capacitors to the busbars on the first vertical bridge and the second vertical bridge, so that the first switching tube is disconnected from the fourth switching tube during the operation of the HERIC topology, or During the disconnection process of the second switch tube and the third switch tube, the capacitor connected to the bus bar can stabilize the voltage fluctuation caused by the different disconnection speed of the switch tube, and inhibit the switching speed of the power circuit due to the switch opening and closing under normal operation.
  • the resonance problem caused by the difference thereby solving the EMC-related problems caused by this resonance.
  • a second aspect of the present application provides an inverter, including a control unit and an inverter power unit, the control unit is used to control the operation of the inverter power unit, wherein the inverter power unit includes the first aspect or the first aspect described above.
  • the inverter circuit described in any possible implementation manner is described in any possible implementation manner.
  • the inverter circuit in the inverter provided by the embodiment of the present application can connect capacitors to the busbars on the first vertical bridge and the second vertical bridge, so that during the operation of the HERIC topology, the first switch and the fourth switch When the second switching tube is disconnected from the third switching tube, the capacitor connected to the bus bar can stabilize the voltage fluctuation caused by the different disconnection speed of the switching tube, and inhibit the normal operation of the power circuit.
  • the resonance problem caused by the difference in the switching speed of switching on and off has solved the EMC-related problems caused by this resonance.
  • a third aspect of the present application provides a photovoltaic power generation system, including: a photovoltaic panel, an inverter, and an AC power grid; the photovoltaic panel is connected to the inverter, the inverter is connected to the AC power grid; the photovoltaic panel is used to connect Light energy is converted into direct current; the inverter includes the inverter circuit as described in the first aspect or any one of the possible implementations of the first aspect, for converting the direct current into alternating current; the alternating current grid is used to transmit the Alternating current.
  • the inverter realizes the conversion of direct current to alternating current, wherein the inverter circuit in the inverter can be connected to the busbar by connecting capacitors on the first vertical bridge and the second vertical bridge.
  • Figure 1 shows the HERIC topology of an inverter circuit in the prior art
  • FIG. 2 is a circuit diagram of an implementation manner of an inverter circuit in an embodiment of the application
  • FIG. 3 is a circuit diagram of another implementation of the inverter circuit in the embodiment of the application.
  • FIG. 5 is a circuit diagram of another implementation of the inverter circuit in the embodiment of the application.
  • FIG. 6 is a circuit diagram of another implementation manner of the inverter circuit in the embodiment of the application.
  • FIG. 7 is a circuit diagram of another implementation manner of the inverter circuit in the embodiment of the application.
  • FIG. 8 is a circuit diagram of another implementation manner of the inverter circuit in the embodiment of the application.
  • FIG. 9 is a circuit diagram of another implementation manner of the inverter circuit in the embodiment of the application.
  • FIG. 10 is a circuit diagram of another implementation manner of the inverter circuit in the embodiment of the application.
  • FIG. 11 is a circuit diagram of another implementation manner of the inverter circuit in the embodiment of the application.
  • FIG. 12 is a circuit diagram of another implementation manner of the inverter circuit in the embodiment of the application.
  • FIG. 13 is a circuit diagram of another implementation manner of the inverter circuit in the embodiment of the application.
  • FIG. 14 is a schematic structural diagram of an inverter in an embodiment of the application.
  • FIG. 15 is a schematic structural diagram of a photovoltaic power generation system in an embodiment of the application.
  • 16 is a circuit diagram of another implementation manner of the inverter circuit in the embodiment of the application.
  • FIG. 17 is a circuit diagram of another implementation of the inverter circuit in the embodiment of the application.
  • Inverter is a device that converts direct current into alternating current.
  • a photovoltaic power generation system includes photovoltaic components, inverters, transformers, cables and other components.
  • the inverter is the core component of the energy conversion of the photovoltaic power generation system, which converts the DC power output by the photovoltaic components into AC power available to the grid. The role of.
  • inverters are also widely used in other systems that need to convert direct current into alternating current.
  • the HERIC topology includes a first vertical bridge 10 and a second vertical bridge 20, wherein two ends of the first vertical bridge 10 are respectively connected with a first switching tube T1 and a second switching tube T2, The two ends of the second vertical bridge 20 are respectively connected to the third switching tube T3 and the fourth switching tube T4. During the first half of the inverter output, the first switching tube T1 and the fourth switching tube T4 are closed.
  • the first switching tube T1 and the fourth switching tube T4 are turned off at the same time.
  • the opening speeds of the first switching tube T1 and the fourth switching tube T4 cannot be kept exactly the same, for example, the fourth switching tube T4
  • the opening speed is faster than that of the first switching tube T1.
  • the voltage on the bus bar, the first vertical bridge 10 and the second vertical bridge 20 will increase.
  • the voltage will fall again. This process There will be resonance phenomenon. This affects the ability of equipment and systems to work normally in their electromagnetic environment and does not cause electromagnetic compatibility (EMC) to anything in the environment, causing EMC conduction and radiation test results to exceed the standard.
  • EMC electromagnetic compatibility
  • the embodiment of the present application provides an inverter circuit, by adding a jumper capacitor to the bus at the connection point of the vertical bridge and the horizontal bridge of the HERIC topology, to prevent the power circuit from being switched off under normal operation. Resonance problem caused by the difference in breaking speed.
  • the inverter circuits and inverters provided in the embodiments of the present application can be photovoltaic inverters used in photovoltaic power generation systems, or they can be applied to other circuits or devices that need to convert direct current to alternating current. Therefore, the embodiments of the present application are not limited.
  • the embodiments of the present application take a photovoltaic inverter as an example to describe in detail the inverter provided in the embodiments of the present application.
  • the inverter circuit provided by the embodiment of the present application is based on the HERIC topology in the prior art, and specifically includes: a bus bar, a first vertical bridge 10, a second vertical bridge 20, a horizontal bridge, and A filter, wherein a capacitor group is provided on the bus bar, the bus bar is connected in parallel with the DC power supply, the capacitor group includes a first capacitor Cs1 and a second capacitor Cs2 arranged in series, wherein the first capacitor Cs1 is connected to the positive electrode of the DC power supply DC+ connection, the second capacitor Cs2 is connected to the negative electrode DC- of the DC power supply, and the first capacitor Cs1 and the second capacitor Cs2 are used to be charged by the DC power supply to charge the first vertical bridge 10 and the second vertical bridge 10
  • the bridge 20 and the cross bridge provide DC voltage.
  • the bus bar is connected in parallel with the first vertical bridge 10, the first vertical bridge 10 is connected in parallel with the second vertical bridge 20, and the first vertical bridge 10 includes a first switching tube T1, a second switching tube T2 connected in series, and The line of the first switching tube T1 and the second switching tube T2, the second vertical bridge 20 includes a third switching tube T3, a fourth switching tube T4 connected in series, and connecting the third switching tube T3 and the fourth switching tube T4
  • the two ends of the horizontal bridge are respectively connected to the first vertical bridge 10 and the second vertical bridge 20.
  • the horizontal bridge includes a connection point A, a connection point B, a connection point C, and a connection point in sequence.
  • the circuit structure of D wherein the connection point A is the connection point between the cross bridge and the first bridge arm 10, and the connection point D is the connection point between the cross bridge and the second bridge arm 20.
  • first vertical bridge 10 and the second vertical bridge 20 are not limited to the above-mentioned structures, but may also be related deformed topological structures.
  • first vertical bridge 10 or the second vertical bridge 20 has two The above switch tube;
  • the horizontal bridge is also not limited to the above-mentioned structure, but may also be a related deformed topological structure, such as a topological structure including the partial structure of the above-mentioned horizontal bridge, which is not limited in the embodiment of the present application.
  • the source of the first switching tube T1 is connected to the drain of the second switching tube T2 through a wire
  • the drain of the first switching tube T1 is connected to the first capacitor Cs1 through a wire
  • the second switching tube T2 The source of is connected to the second capacitor Cs2 through a wire.
  • the first switching tube T1, the second switching tube T2, the third switching tube T3, and the fourth switching tube T4 can be MOS tubes, IGBTs, or other semiconductor devices that function as switches.
  • the embodiment is not limited.
  • each switch Diodes and capacitors can also be connected in parallel on the tubes respectively.
  • the first switching tube T1, the second switching tube T2, the third switching tube T3, and the fourth switching tube T4 can be connected in parallel with a capacitor C1, a capacitor C2, and
  • the capacitor C3 and the capacitor C4 when the switch tube is a MOS tube can be a gallium nitride MOS tube or a silicon carbide MOS tube.
  • the first capacitor Cs1 or the second capacitor Cs2 can be realized by one capacitor or by multiple capacitive devices.
  • the embodiments of the application are not limited.
  • the filter is connected in parallel on the cross bridge, the filter is connected to the AC power grid AC, and the cross bridge is used to supply power to the AC power grid AC through the filter.
  • the filter specifically includes a circuit structure that sequentially passes through connection point B, connection point E, connection point F, and connection point C.
  • the filter is connected in parallel to the cross bridge through connection point B and connection point C. Point E and connection point F are connected to the AC grid AC.
  • the filter includes a first inductor L1 and a second inductor L2, and the cross bridge includes a freewheeling switch group, wherein,
  • the first inductor L1 is connected between the first vertical bridge 10 and the AC power grid AC
  • the second inductor L2 is connected between the AC power grid AC connection and the second vertical bridge 20
  • the freewheeling switch group is connected in parallel with the first vertical bridge.
  • the connection point E and the connection point F are connected to the AC grid AC.
  • the first inductor L1 and the second inductor L2 are used when the first switching tube T1 and the fourth switching tube T4, or the second switching tube T2 and the third switching tube T3 are closed by the DC Power excitation;
  • the freewheeling switch group is used to close when the first switching tube T1 is disconnected from the fourth switching tube T4, or when the second switching tube T2 is disconnected from the third switching tube T3, so that the The first inductor L1 and the second inductor L2 supply power to the output.
  • the freewheeling switch group includes a fifth switch tube T5 and a sixth switch tube T6 connected in series, wherein,
  • the fifth switch tube T5 is used to keep closed
  • the sixth switching tube T6 is used to close when the first switching tube T1 is disconnected from the fourth switching tube T4, or when the second switching tube T2 is disconnected from the third switching tube T3, so that The first inductor L1 and the second inductor L2 supply power to the output.
  • the inverter further includes a fifth capacitor Cx1.
  • the fifth capacitor Cx1 is connected in parallel between the first inductor L1 and the second inductor L2 through a connection point E and a connection point F.
  • the fifth capacitor Cx1 is used for The voltage of the cross bridge is stabilized so that the cross bridge outputs a stable voltage to the AC power grid AC.
  • the fifth switching tube T5 and the sixth switching tube T6 are MOS tubes, and the MOS tubes may be MOS tubes, IGBTs, or other semiconductor devices that function as switches, which are not limited in the embodiment of the present application.
  • the fifth switching tube T5 and the sixth switching tube T6 are MOS tubes
  • the fifth switching tube T5 and the sixth switching tube T6 are MOS tubes, and diodes can be connected in parallel respectively.
  • the MOS tube can be a gallium nitride MOS tube or a silicon carbide MOS tube.
  • the topology structure on which the inverter circuit in the embodiment of the present application is based may also be a related modified topology structure of the HERIC topology, which is not limited by the embodiment of the present application.
  • the DC power supply charges the first capacitor Cs1 and the second capacitor Cs2 in the bus.
  • the first switching tube T1 and the fourth switching tube T4 are closed.
  • the first capacitor Cs1 releases the voltage through the positive electrode DC+ of the bus, and the current passes through the first switching tube T1 and the first inductor in turn L1, the second inductor L2, and the fourth switch tube T4 finally flow to the negative pole DC- of the bus bar, thus completing the loop.
  • the first inductor L1 and the second inductor L2 are charged to realize the first inductor L1 and the second inductor L1. Excitation of the inductor L2.
  • the first switching tube T1 is disconnected from the fourth switching tube T4, and the freewheeling switch group is closed.
  • the specific closing method of the freewheeling switch group is: the fifth switching tube T5 Always keep the closed state, when the freewheeling switch group needs to be changed from open to closed, the sixth switch tube T6 is opened and closed to realize the closing of the freewheeling switch group; the first inductor L1 and the second inductor L2 discharge , The current forms a loop between the AC power grid AC, the first inductor L1, the freewheeling switch group, and the second inductor L2, so that in the freewheeling phase, the first inductor L1 and the second inductor L2 continuously charge the AC power grid AC, thereby In the positive half cycle of alternating current, the horizontal bridge supplies power to the output.
  • the second switching tube T2 and the third switching tube T3 are closed.
  • the second capacitor Cs2 releases the voltage through the negative pole of the bus bar, and the current passes through the second switching tube T2 and the first switching tube in turn.
  • the inductor L1, the second inductor L2, and the third switch tube T3 finally flow to the positive electrode DC+ of the bus bar, thus completing the loop.
  • the first inductor L1 and the second inductor L2 are charged to realize the first inductor L1 and the second inductor L1. Excitation of the inductor L2.
  • the second switching tube T2 In the freewheeling phase of the negative half cycle of the inverter output, the second switching tube T2 is disconnected from the third switching tube T3, and the freewheeling switch group is closed.
  • the specific closing method of the freewheeling switch group is: the fifth switching tube T5 Always keep the closed state, when the freewheeling switch group needs to be changed from open to closed, the sixth switch tube T6 is opened and closed to realize the closing of the freewheeling switch group; the first inductor L1 and the second inductor L2 discharge , The current forms a loop between the AC power grid AC, the first inductor L1, the freewheeling switch group, and the second inductor L2, so that in the freewheeling phase, the first inductor L1 and the second inductor L2 continuously charge the AC power grid AC, thereby In the negative half cycle of alternating current, the horizontal bridge supplies power to the output.
  • the inverter circuit of the HERIC topology converts the DC power output by the DC power supply into AC power, thereby providing AC power to the AC power grid.
  • the speed at which the first switching tube T1 is turned off cannot be synchronized with the speed at which the fourth switching tube T4 is turned off, for example, The fourth switching tube T4 is turned off faster than the first switching tube T1.
  • the bus, the first vertical bridge 10 and the second The voltage of the vertical bridge 20 will be pulled up to the positive voltage of the bus.
  • the voltage of the bus, the first vertical bridge 10 and the second vertical bridge 20 will return to the bus midpoint voltage.
  • the inverter circuit provided by the embodiment of the present application is connected across the third capacitor Csy1 and the fourth capacitor Csy2 on the basis of the existing HERIC topology.
  • the third capacitor Csy1 is connected between the bus bar and the first vertical bridge 10, wherein the connection point H of the third capacitor Csy1 and the first vertical bridge 10 is located at the Between the first switch tube T1 and the second switch tube T2;
  • the fourth capacitor Csy2 is connected between the bus bar and the second vertical bridge 20, wherein the connection point J of the fourth capacitor Csy2 and the second vertical bridge 20 is located between the third switch tube T3 and the fourth switch tube Between T4;
  • the third capacitor Csy1 is used to stabilize the voltages of the bus bar, the first vertical bridge 10 and the second vertical bridge 20 when the first switching tube T1 and the fourth switching tube T4 are disconnected;
  • the fourth capacitor Csy2 is used to stabilize the voltage of the bus bar, the first vertical bridge 10 and the second vertical bridge 20 when the second switching tube T2 and the third switching tube T3 are disconnected.
  • connection point G between the third capacitor Csy1 and the bus bar is set between the first capacitor Cs1 and the second capacitor Cs2, and the third capacitor Csy1 is connected to the first vertical bridge 10 through the connection point H; the fourth capacitor Csy2
  • connection point I with the bus bar is arranged between the first capacitor Cs1 and the second capacitor Cs2, and the fourth capacitor Csy2 is connected to the second vertical bridge 20 through the connection point J.
  • the first switching tube T1 and the fourth switching tube T4 are closed.
  • the first capacitor Cs1 and the third capacitor Csy1 form a parallel equivalent circuit.
  • the capacitor Cs1 charges the third capacitor Csy1, and the voltages of the first capacitor Cs1 and the third capacitor Csy1 are equal.
  • the first capacitor Cs1 and the second capacitor Cs2 constitute a voltage divider circuit of the DC power supply, at this time, the voltages of the first capacitor Cs1 and the second capacitor Cs2 are respectively equal to 1/2 of the bus voltage, that is, 1/2 of the bus voltage. Therefore, At this time, the voltage of the third capacitor Csy1 is also equal to 1/2 bus voltage.
  • the first switching tube T1 is disconnected from the fourth switching tube T4. If the fourth switching tube T4 is disconnected faster than the first switching tube T1, when the When the four switching tube T4 is disconnected and the first switching tube T1 is not yet disconnected, the third capacitor Csy1 can be further charged by the capacitor of the positive voltage of the bus, thereby preventing fluctuations caused by the voltage rise; if the fourth switching tube T4 is disconnected The speed is slower than the disconnection speed of the first switching tube T1. When the first switching tube T1 is disconnected and the fourth switching tube T4 is not disconnected, the 1/2 bus voltage output by the third capacitor Csy1 can be stabilized.
  • the second switching tube T2 and the third switching tube T3 are closed.
  • the second capacitor Cs2 and the fourth capacitor Csy2 form a parallel equivalent circuit, and the second capacitor Cs2 is directed to the fourth The capacitor Csy2 is charged, and the voltages of the second capacitor Cs2 and the fourth capacitor Csy2 are equal.
  • the first capacitor Cs1 and the second capacitor Cs2 constitute a voltage divider circuit of the DC power supply, at this time, the voltages of the first capacitor Cs1 and the second capacitor Cs2 are respectively equal to 1/2 of the bus voltage, that is, 1/2 of the bus voltage.
  • the voltage of the fourth capacitor Csy2 is also equal to 1/2 bus voltage.
  • the second switching tube T2 is disconnected from the third switching tube T3. If the third switching tube T3 is disconnected faster than the second switching tube T2, when the When the third switch tube T3 is disconnected and the second switch tube T2 is not disconnected, the fourth capacitor Csy2 can be further charged by the capacitor of the positive voltage of the bus, thereby preventing the fluctuation caused by the voltage increase; if the third switch tube T3 is disconnected The speed is slower than the disconnection speed of the second switching tube T2.
  • the 1/2 bus voltage output by the fourth capacitor Csy2 can be stabilized. Prevents fluctuations on the bus bar, the first vertical bridge 10 and the second vertical bridge 20 due to voltage rise; thereby effectively preventing the disconnection of the second switching tube T2 and the third switching tube T3 during the operation of the HERIC topology inverter Different speeds cause resonance problems.
  • the difference between the positive half cycle and the negative half cycle of the inverter output is that in the positive half cycle, the first capacitor Cs1 is charged by the positive electrode DC+ of the DC power supply, and the third capacitor Csy1 is charged with 1/2 of the positive bus voltage.
  • the second capacitor Cs2 is charged by the negative electrode DC- of the direct current power supply, and the fourth capacitor Csy2 is charged with 1/2 bus negative voltage.
  • the third capacitor Csy1 and the fourth capacitor Csy2 are connected across the bus bar at the position between the first capacitor Cs1 and the second capacitor Cs2, so that the first capacitor Cs1 and The third capacitor Csy1 forms a parallel circuit, and the second capacitor Cs2 and the fourth capacitor Csy2 form a parallel circuit, so that when the first switch tube T1 and the fourth switch tube T4 are closed, the voltage of the third capacitor Csy1 is equal to the voltage of the first capacitor Cs1 In the positive half cycle of the inverter output, the voltage of the bus bar, the first vertical bridge 10 and the second vertical bridge 20 is stabilized; when the second switch tube T2 and the third switch tube T3 are closed, the voltage of the fourth capacitor Csy2 The voltage equal to the second capacitor Cs2 stabilizes the voltage of the bus bar, the first vertical bridge 10 and the second vertical bridge 20 during the negative half cycle of the inverter output, thereby preventing the occurrence of resonance problems.
  • the voltage of the first capacitor Cs1 causes the circuit to pass through the third capacitor Csy1 and the first inductor in sequence.
  • L1 AC power grid AC, second inductor L2, fourth capacitor Csy2, and second capacitor Cs2.
  • the third capacitor Csy1 and the fourth capacitor Csy2 are charged with 1/2 bus voltage respectively, when the first switch tube T1 and When the fourth switching tube T4 is closed, or the second switching tube T2 and the third switching tube T3 are closed, due to the voltage discharged by the third capacitor Csy1 or the voltage discharged by the fourth capacitor Csy2 and the first capacitor Cs1 or the second capacitor Cs2
  • the voltage values are equal, and they are all 1/2 bus voltage, so the loss of the circuit is small. Therefore, the first implementation in the embodiments of the present application can not only effectively prevent resonance problems due to different switching speeds, but also effectively reduce circuit losses.
  • the first embodiment is the most preferred embodiment.
  • the third capacitor Csy1 or the fourth capacitor Csy2 can be realized by one capacitor, or can be realized by multiple capacitive devices.
  • the embodiments of the application are not limited.
  • connection point G between the third capacitor Csy1 and the bus bar and the connection point I between the fourth capacitor Csy2 and the bus bar and the bus bar are only the first implementation manner provided by the embodiment of the present application, which is optional Ground, according to the location of the connection point, different working modes can be used to stabilize the voltage of the bus bar, the first vertical bridge 10 and the second vertical bridge 20. It also includes:
  • connection point between the line where the third capacitor is located and the bus bar and the connection point between the line where the fourth capacitor is located and the bus bar are both set between the capacitor bank and the DC power supply.
  • connection point between the line where the third capacitor is located and the bus bar and the connection point between the line where the fourth capacitor is located and the bus bar are not set between the first capacitor and the second capacitor.
  • connection point between the line where the third capacitor is located and the bus bar and the connection point between the line where the fourth capacitor is located and the bus bar only one connection point is set between the first capacitor and the second capacitor.
  • the third capacitor Csy1 and the fourth capacitor Csy2 are both connected across the first capacitor Cs1 on the bus bar and the positive pole of the DC power supply.
  • connection point G between the third capacitor Csy1 and the bus bar is set between the first capacitor Cs1 and the positive pole of the DC power supply, and the third capacitor Csy1 is connected to the first capacitor Cs1.
  • the vertical bridge 10 is connected through a connection point H; the connection point I between the fourth capacitor Csy2 and the bus bar is arranged between the first capacitor Cs1 and the positive electrode of the DC power supply, and the fourth capacitor Csy2 and the second vertical bridge 20 are connected through the connection point J.
  • the first switching tube T1 and the fourth switching tube T4 are closed. At this time, the current starts from the first capacitor Cs1 and passes through the first switching tube T1 and the first switching tube T1. Inductor L1, AC grid AC, second inductance L2, fourth switching tube T4 and second capacitor Cs2; in the freewheeling phase of the positive half cycle of the inverter output, the first switching tube T1 and the fourth switching tube T4 are disconnected, if The speed at which the fourth switching tube T4 is turned off is different from the speed at which the first switching tube T1 is turned off.
  • the generated positive bus voltage charges the third capacitor Csy1, so that the third capacitor Csy1 can absorb the bus, the first vertical bridge 10 and
  • the increased voltage on the second vertical bridge 20 eliminates fluctuations caused by the increase in voltage, thereby effectively preventing resonance problems due to the different disconnection speeds of the first switch and the fourth switch during the operation of the HERIC topology inverter circuit.
  • the second switching tube T2 and the third switching tube T3 are closed.
  • the current starts from the second capacitor Cs2 and passes through the second switching tube T2, the first inductor L1, and the AC power grid in turn AC, the second inductor L2, the third switching tube T3 and the first capacitor Cs1;
  • the second switching tube T2 is disconnected from the third switching tube T3, if the second switching tube T2 The disconnection speed is different from the disconnection speed of the third switch tube T3.
  • the generated negative voltage of the bus bar charges the fourth capacitor Csy2, so that the fourth capacitor Csy2 can absorb the bus bar, the first vertical bridge 10 and the second vertical bridge 20.
  • the above voltage change eliminates the fluctuations caused by the voltage change, thereby effectively preventing the resonance problem caused by the different disconnection speeds of the second switch and the third switch during the operation of the HERIC topology inverter circuit.
  • the third capacitor Csy1 and the fourth capacitor Csy2 are connected across the positive position of the bus voltage, so that the first switch transistor T1 and the fourth switch transistor T4 are disconnected.
  • the third capacitor Csy1 can absorb voltage fluctuations, thereby stabilizing the circuit.
  • the fourth capacitor Csy2 can absorb the voltage fluctuations, thereby Stabilize the circuit.
  • the voltage of the first capacitor Cs1 causes the circuit to pass through the third capacitor Csy1 and the fourth capacitor in sequence Csy2 flows through the entire loop.
  • the third capacitor Csy1 and the fourth capacitor Csy2 are respectively charged with a bus voltage.
  • the first switching tube T1 and the fourth switching tube T4 are closed, or the second switching tube T2 and the third switching tube are closed.
  • the tube T3 is closed, the voltage discharged by the third capacitor Csy1 or the voltage discharged by the fourth capacitor Csy2 is greater than the voltage discharged by the first capacitor Cs1 or the second capacitor Cs2 (as mentioned above, the first capacitor Cs1 and the second capacitor Cs2 In the voltage divider circuit composed, the voltages of the first capacitor Cs1 and the second capacitor Cs2 are respectively equal to 1/2 bus voltage), so when the first switching tube T1 and the fourth switching tube T4 are closed, or the second switching tube T2 and the When the three-switch tube T3 is closed, the third capacitor Csy1 or the fourth capacitor Csy2 needs to discharge an extra voltage, and this process will cause external loss of the circuit. Therefore, the second implementation manner in the embodiments of the present application can effectively
  • the third capacitor Csy1 and the fourth capacitor Csy2 are both connected across the second capacitor Cs2 on the bus bar and the negative pole of the DC power supply.
  • connection point G between the third capacitor Csy1 and the bus bar is set between the second capacitor Cs2 and the negative electrode of the DC power supply, and the third capacitor Csy1 is connected to the first vertical
  • the bridge 10 is connected through the connection point H; the connection point I between the fourth capacitor Csy2 and the bus is arranged between the second capacitor Cs2 and the negative electrode of the DC power supply, and the fourth capacitor Csy2 is connected to the second vertical bridge 20 through the connection point J.
  • the first switching tube T1 and the fourth switching tube T4 are closed. At this time, the current starts from the first capacitor Cs1 and passes through the first switching tube T1 and the first switching tube T1. Inductor L1, AC grid AC, second inductance L2, fourth switching tube T4 and second capacitor Cs2; in the freewheeling phase of the positive half cycle of the inverter output, the first switching tube T1 and the fourth switching tube T4 are disconnected, if The speed at which the fourth switching tube T4 is turned off is different from the speed at which the first switching tube T1 is turned off.
  • the generated positive bus voltage charges the third capacitor Csy1, so that the third capacitor Csy1 can absorb the bus, the first vertical bridge 10 and
  • the increased voltage on the second vertical bridge 20 eliminates fluctuations caused by the increase in voltage, thereby effectively preventing resonance problems due to the different disconnection speeds of the first switch and the fourth switch during the operation of the HERIC topology inverter circuit.
  • the second switching tube T2 and the third switching tube T3 are closed.
  • the current starts from the second capacitor Cs2 and passes through the second switching tube T2, the first inductor L1, and the AC power grid in turn AC, the second inductor L2, the third switching tube T3 and the first capacitor Cs1;
  • the second switching tube T2 is disconnected from the third switching tube T3, if the second switching tube T2 The disconnection speed is different from the disconnection speed of the third switch tube T3.
  • the generated negative voltage of the bus bar charges the fourth capacitor Csy2, so that the fourth capacitor Csy2 can absorb the bus bar, the first vertical bridge 10 and the second vertical bridge 20.
  • the above voltage change eliminates the fluctuations caused by the voltage change, thereby effectively preventing the resonance problem caused by the different disconnection speeds of the second switch and the third switch during the operation of the HERIC topology inverter circuit.
  • the third capacitor Csy1 and the fourth capacitor Csy2 are connected across the negative bus voltage, so that the first switch transistor T1 and the fourth switch transistor T4 are disconnected.
  • the third capacitor Csy1 can absorb voltage fluctuations, thereby stabilizing the circuit.
  • the fourth capacitor Csy2 can absorb the voltage fluctuations, thereby Stabilize the circuit.
  • the voltage of the first capacitor Cs1 causes the circuit to pass through the third capacitor Csy1 and the fourth capacitor in sequence Csy2 flows through the entire loop.
  • the third capacitor Csy1 and the fourth capacitor Csy2 are respectively charged with a bus voltage.
  • the voltage discharged by the third capacitor Csy1 or the voltage discharged by the fourth capacitor Csy2 is greater than the voltage discharged by the first capacitor Cs1 or the second capacitor Cs2 (as mentioned above, the first capacitor Cs1 and the second capacitor Cs2 In the voltage divider circuit composed, the voltages of the first capacitor Cs1 and the second capacitor Cs2 are respectively equal to 1/2 bus voltage), so when the first switching tube T1 and the fourth switching tube T4 are closed, or the second switching tube T2 and the When the three-switch tube T3 is closed, the third capacitor Csy1 or the fourth capacitor Csy2 needs to discharge an extra voltage, and this process will cause external loss of the circuit.
  • the third implementation manner in the embodiments of the present application can effectively prevent the resonance problem due to different switching speeds, but will cause certain circuit losses; the third implementation manner of the present application is equivalent to the above-mentioned second implementation manner.
  • the difference is that in the second embodiment, the third capacitor Csy1 and the fourth capacitor Csy2 are connected across the voltage positive position of the bus bar. In the second embodiment, the third capacitor Csy1 and the fourth capacitor Csy2 are connected across the bus bar. The voltage is negative, so the third embodiment can be used as an alternative to the second embodiment.
  • the third capacitor Csy1 is connected across the midpoint of the bus, and the fourth capacitor Csy2 is connected across the positive bus;
  • the fourth capacitor Csy2 is connected across the midpoint of the bus, and the third capacitor Csy1 is connected across the positive bus;
  • the fourth capacitor Csy2 is connected across the midpoint of the bus, and the third capacitor Csy1 is connected across the negative of the bus;
  • the ninth embodiment the third capacitor Csy1 is connected across the negative bus bar, and the fourth capacitor Csy2 is connected across the positive bus bar.
  • connection scheme and working principle of the jump mode of the third capacitor Csy1 and the fourth capacitor Csy2 can be referred to the first to third embodiments above, and the difference lies only in the jump mode.
  • the permutation and combination are different, so I won't repeat them here.
  • an impedance network may be connected in series to the third capacitor Csy1 and the fourth capacitor Csy2, thereby During the charging process of the capacitor Csy1 and the fourth capacitor Csy2, the stability of the charging of the third capacitor Csy1 and the fourth capacitor Csy2 is maintained.
  • the impedance network includes at least one inductor and/or at least one resistor connected in series. For ease of understanding, different situations of the impedance network will be specifically described below in conjunction with the drawings.
  • FIG. 5 is based on the first implementation manner of the embodiment of the present application, the third capacitor Csy1 and the fourth capacitor Csy2 are respectively arranged in series with an inductor Ls1 and an inductor Ls2, where, The inductor Ls1 is connected in series with the third capacitor Csy1, and the inductor Ls2 is connected in series with the fourth capacitor Csy2.
  • the inductor Ls1 and the inductor Ls2 can share the current charged in the third capacitor Csy1 and the fourth capacitor Csy2 during the charging process of the third capacitor Csy1 and the fourth capacitor Csy2, thereby avoiding the third capacitor Csy1 and the fourth capacitor Csy2.
  • the third capacitor Csy1 and the fourth capacitor Csy2 are damaged due to the instantaneous overcharge of the fourth capacitor Csy2.
  • the inductor Ls1 and the inductor Ls2 can release the charged electricity, and slowly charge the third capacitor Csy1 and the fourth capacitor Csy2, so as to ensure that the large current does not affect the third capacitor. While the capacitor Csy1 and the fourth capacitor Csy2 are damaged, the excess current is not wasted.
  • FIG. 6 is based on the first implementation of the embodiment of the present application, a resistor Rs1 and a resistor Rs2 are respectively arranged in series on the third capacitor Csy1 and the fourth capacitor Csy2. , Wherein the resistor Rs1 is connected in series with the third capacitor Csy1, and the resistor Rs2 is connected in series with the fourth capacitor Csy2.
  • the resistor Rs1 and the resistor Rs2 connected in series between the third capacitor Csy1 and the fourth capacitor Csy2 can transfer the extra electric energy It is converted to protect the third capacitor Csy1 and the fourth capacitor Csy2, and prevent the third capacitor Csy1 and the fourth capacitor Csy2 from being damaged due to high power charging.
  • FIG. 7 is based on the first implementation manner of the embodiment of the present application, and an inductor Ls1 and an inductor Ls2 are respectively arranged in series on the third capacitor Csy1 and the fourth capacitor Csy2.
  • the inductor Ls1 and the inductor Ls2 can share the current charged by the third capacitor Csy1 and the fourth capacitor Csy2 during the charging process of the third capacitor Csy1 and the fourth capacitor Csy2, thereby avoiding the third capacitor Csy1 and the fourth capacitor Csy2.
  • the third capacitor Csy1 and the fourth capacitor Csy2 are damaged due to the instantaneous overcharge of the fourth capacitor Csy2.
  • the resistor Rs1 and the resistor Rs2 connected in series can convert the extra electrical energy, thereby further protecting the third capacitor Csy1 and the fourth capacitor Csy2 prevent the third capacitor Csy1 and the fourth capacitor Csy2 from being damaged due to high power charging.
  • FIG. 8 is based on the second implementation manner of the embodiment of the present application, the third capacitor Csy1 and the fourth capacitor Csy2 are respectively provided in series with an inductor Ls1 and an inductor Ls2, where, The inductor Ls1 is connected in series with the third capacitor Csy1, and the inductor Ls2 is connected in series with the fourth capacitor Csy2.
  • the inductor Ls1 and the inductor Ls2 can share the current charged in the third capacitor Csy1 and the fourth capacitor Csy2 during the charging process of the third capacitor Csy1 and the fourth capacitor Csy2, thereby avoiding the third capacitor Csy1 and the fourth capacitor Csy2.
  • the third capacitor Csy1 and the fourth capacitor Csy2 are damaged due to the instantaneous overcharge of the fourth capacitor Csy2.
  • the inductor Ls1 and the inductor Ls2 can release the charged electricity, and slowly charge the third capacitor Csy1 and the fourth capacitor Csy2, so as to ensure that the large current does not affect the third capacitor. While the capacitor Csy1 and the fourth capacitor Csy2 are damaged, the excess current is not wasted.
  • FIG. 9 is based on the second implementation manner of the embodiment of the present application, a resistor Rs1 and a resistor Rs2 are respectively arranged in series on the third capacitor Csy1 and the fourth capacitor Csy2. , Wherein the resistor Rs1 is connected in series with the third capacitor Csy1, and the resistor Rs2 is connected in series with the fourth capacitor Csy2.
  • the resistor Rs1 and the resistor Rs2 connected in series between the third capacitor Csy1 and the fourth capacitor Csy2 can transfer the extra electric energy It is converted to protect the third capacitor Csy1 and the fourth capacitor Csy2, and prevent the third capacitor Csy1 and the fourth capacitor Csy2 from being damaged due to high power charging.
  • FIG. 10 is based on the second implementation manner of the embodiment of the present application, and the third capacitor Csy1 and the fourth capacitor Csy2 are respectively provided in series with an inductor Ls1 and an inductor Ls2 , The resistor Rs1 and the resistor Rs2, wherein the inductor Ls1 and the resistor Rs1 are connected in series with the third capacitor Csy1, and the inductor Ls2 and the resistor Rs2 are connected in series with the fourth capacitor Csy2.
  • the inductor Ls1 and the inductor Ls2 can share the current charged in the third capacitor Csy1 and the fourth capacitor Csy2 during the charging process of the third capacitor Csy1 and the fourth capacitor Csy2, thereby avoiding the third capacitor Csy1 and the fourth capacitor Csy2.
  • the third capacitor Csy1 and the fourth capacitor Csy2 are damaged due to the instantaneous overcharge of the fourth capacitor Csy2.
  • the resistor Rs1 and the resistor Rs2 connected in series can convert the extra electrical energy, thereby further protecting the third capacitor Csy1 and the fourth capacitor Csy2 prevent the third capacitor Csy1 and the fourth capacitor Csy2 from being damaged due to high power charging.
  • FIG. 11 is based on the third implementation manner of the embodiment of the present application, and the third capacitor Csy1 and the fourth capacitor Csy2 are respectively provided in series with an inductor Ls1 and an inductor Ls2, where, The inductor Ls1 is connected in series with the third capacitor Csy1, and the inductor Ls2 is connected in series with the fourth capacitor Csy2.
  • the inductor Ls1 and the inductor Ls2 can share the current charged by the third capacitor Csy1 and the fourth capacitor Csy2 during the charging process of the third capacitor Csy1 and the fourth capacitor Csy2, thereby avoiding the third capacitor Csy1 and the fourth capacitor Csy2.
  • the third capacitor Csy1 and the fourth capacitor Csy2 are damaged due to the instantaneous overcharge of the fourth capacitor Csy2.
  • the inductor Ls1 and the inductor Ls2 can release the charged electricity, and slowly charge the third capacitor Csy1 and the fourth capacitor Csy2, so as to ensure that the large current does not affect the third capacitor. While the capacitor Csy1 and the fourth capacitor Csy2 are damaged, the excess current is not wasted.
  • FIG. 12 is based on the third implementation manner of the embodiment of the present application, a resistor Rs1 and a resistor Rs2 are respectively arranged in series on the third capacitor Csy1 and the fourth capacitor Csy2 , Wherein the resistor Rs1 is connected in series with the third capacitor Csy1, and the resistor Rs2 is connected in series with the fourth capacitor Csy2.
  • the resistor Rs1 and the resistor Rs2 connected in series between the third capacitor Csy1 and the fourth capacitor Csy2 can transfer the extra electric energy It is converted to protect the third capacitor Csy1 and the fourth capacitor Csy2, and prevent the third capacitor Csy1 and the fourth capacitor Csy2 from being damaged due to high power charging.
  • FIG. 13 is based on the third implementation manner of the embodiment of the present application, the third capacitor Csy1 and the fourth capacitor Csy2 are respectively provided in series with an inductor Ls1 and an inductor Ls2 , The resistor Rs1 and the resistor Rs2, wherein the inductor Ls1 and the resistor Rs1 are connected in series with the third capacitor Csy1, and the inductor Ls2 and the resistor Rs2 are connected in series with the fourth capacitor Csy2.
  • the inductor Ls1 and the inductor Ls2 can share the current charged in the third capacitor Csy1 and the fourth capacitor Csy2 during the charging process of the third capacitor Csy1 and the fourth capacitor Csy2, thereby avoiding the third capacitor Csy1 and the fourth capacitor Csy2.
  • the third capacitor Csy1 and the fourth capacitor Csy2 are damaged due to the instantaneous overcharge of the fourth capacitor Csy2.
  • the resistor Rs1 and the resistor Rs2 connected in series can convert the extra electrical energy, thereby further protecting the third capacitor Csy1 and the fourth capacitor Csy2 prevent the third capacitor Csy1 and the fourth capacitor Csy2 from being damaged due to high power charging.
  • an impedance network may also be provided in the third capacitor Csy1 and the fourth capacitor Csy2.
  • an impedance network may also be provided in the third capacitor Csy1 and the fourth capacitor Csy2.
  • the impedance network can protect the third capacitor Csy1 and the fourth capacitor Csy2 and prevent the third capacitor Csy1 and the fourth capacitor Csy2 from being damaged during the charging process.
  • the existence of the impedance network also Will reduce the third capacitor Csy1 and the fourth capacitor Csy2, thereby affecting the protection of the third capacitor Csy1 and the fourth capacitor Csy2 against resonance problems during the switching process of the switch tube to a certain extent. Therefore, the user can choose according to the actual use Whether to increase the impedance network, and the number of capacitors and inductors specifically set in the impedance network.
  • an embodiment of the present application also provides an inverter.
  • the inverter includes a control unit 1401 and an inverter power unit 1402.
  • the control unit is used to control the operation of the inverter power unit.
  • the inverter power unit 1402 includes the inverter circuit described in any of the foregoing embodiments, which can be understood by referring to the description of the foregoing inverter circuit; the control unit 1401 may include a control chip and a circuit structure for realizing the function of the control chip.
  • the operation of the control unit 1401 and the inverter power unit 1402 may include the control unit 1401 controlling the opening and closing of each switch tube of the inverter circuit in the inverter power unit 1402.
  • an embodiment of the present application also provides a photovoltaic power generation system, including: a photovoltaic panel 1501, an inverter 1502, and an AC power grid 1503; the photovoltaic panel 1501 is connected to the inverter 1502, and the inverter 1502 Connected to the AC power grid 1503; the photovoltaic panel 1501 is used to convert light energy into direct current; the inverter 1502 includes the inverter circuit described in any one of the above embodiments, and is used to convert the direct current to alternating current; The grid 1503 is used to transmit the alternating current.
  • the inverter converts the DC power generated by the photovoltaic panel through solar power generation into AC power and merges it into the AC power grid, so that solar energy can be used.
  • the inverter circuit included in the inverter is any one of the implementations described above.
  • the inverter circuit described in the example can be understood by referring to the description of the aforementioned inverter circuit.
  • the inverter circuit can not only convert alternating current into direct current, but also avoid EMC problems caused by resonance.

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  • Inverter Devices (AREA)

Abstract

本申请公开了一种逆变电路，可以应用于逆变器，例如光伏逆变器中，本申请实施例还提供了一种逆变器和光伏发电系统，其中，该逆变器和该光伏发电系统中的逆变器均包含本申请所公开的逆变电路；基于HERIC拓扑逆变电路结构，该逆变电路通过在第一竖桥和第二竖桥上分别对母线跨接第三电容和第四电容，使得在逆变电路在由开启阶段向续流阶段转化的过程中，第三电容和第四电容能够稳定HERIC拓扑中因开关管关断速度不同而产生的电压波动，从而防止因电压波动而产生的谐振问题，从而解决了谐振干扰的问题，对于设备和系统在其电磁环境中能正常工作且不对环境中任何事物构成不能承受的电磁骚扰的能力(electro magnetic compatibility,EMC),能够满足EMC相关标准的要求。

Description

一种逆变电路、逆变器及光伏发电系统
本申请要求于2019年5月31日提交中国专利局、申请号为201910469584.X、发明名称为“一种逆变电路、逆变器及光伏发电系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电压变换技术领域，具体涉及一种逆变电路、逆变器及光伏发电系统。
背景技术
作为一种可再生清洁能源，光伏发电产业在近年来得到迅猛发展。一个光伏发电系统包括光伏组件、逆变器、变压器和线缆等多个部件，其中逆变器是光伏发电系统能量转换的核心部件，起到了将光伏组件输出的直流电转换为电网可用的交流电的作用。同时，逆变器在其余各种需要将直流电转化为交流电的系统中也广泛使用。
Highly efficient reliable inverter concept，HERIC，是一种高效可靠的逆变器概念，基于该概念所产生的HERIC拓扑由于其自身的低成本的特性在光伏逆变器产品中得到广泛的应用，如图1所示，现有技术中，在HERIC拓扑中包括第一竖桥和第二竖桥，其中，第一竖桥的两端分别连接有第一开关管和第二开关管，第二竖桥的两端分别连接有第三开关管和第四开关管，在逆变输出的上半周，第一开关管和第四开关管闭合，在进入续流阶段，此时，第一开关管和第四开关管同时断开，用于实际工作中，第一开关管和第四开关管的断开速度不能保持完全一致，例如第四开关管的断开速度较第一开关管快，此时母线、第一竖桥和第二竖桥上的电压会升高，待第一开关管关闭后，电压又会回落，此过程中会产生谐振现象。从而影响设备和系统在其电磁环境中能正常工作且不对环境中任何事物构成不能承受的电磁骚扰的能力(electro magnetic compatibility,EMC)，造成EMC的传导、辐射测试项目结果超标。
因此，对于现有技术中的HERIC拓扑还有待于改进。
发明内容
本申请实施例提供一种逆变电路、逆变器及光伏发电系统，可以通过在HERIC拓扑竖桥与横桥连接点位置对母线加跨接电容的方案，来抑制功率电路正常工作下因为开关关断速度差异引起的谐振问题。
本申请第一方面提供一种逆变电路，包括：母线、第一竖桥、第二竖桥、横桥及滤波器，其中，该母线上设置有电容组，该母线与直流电源并联，该电容组包括串联设置的第一电容和第二电容，其中，该第一电容设置在该母线与该直流电源的正极连接的一侧，该第二电容设置在该母线与该直流电源的负极连接的一侧，该第一电容及该第二电容用于被该直流电源充电，以向该第一竖桥、该第二竖桥和该横桥提供直流电压；该母线与该第一 竖桥并联，该第一竖桥与该第二竖桥并联，该第一竖桥包括串联的第一开关管和第二开关管，该第二竖桥包括串联的第三开关管和第四开关管，该横桥的两端分别与该第一竖桥和该第二竖桥连接；该滤波器并联在该横桥上，该滤波器与交流电网连接，该横桥用于通过该滤波器向交流电网供电；该逆变电路还包括：第三电容，该第三电容连接在该母线与该第一竖桥之间，其中，该第三电容与该第一竖桥的连接点位于该第一开关管与该第二开关管之间；第四电容，该第四电容连接在该母线与该第二竖桥之间，其中，该第四电容与该第二竖桥的连接点位于该第三开关管与该第四开关管之间。其中，该第一开关管、该第二开关管、该第三开关管及该第四开关管可以为MOS管或IGBT器。
本实施例中，通过在现有HERIC拓扑逆变电路的基础上，在第一竖桥与母线之间，以及第二竖桥与母线之间跨接第三电容和第四电容，从而使得第一开关管和第四开关管断开的过程中，第三电容能够稳定由于两开关管断开速度不同所产生的电压差，从而杜绝谐振现象的发生，有效杜绝因谐振现象而导致的EMC问题。同理，在第二开关管和第三开关管断开的过程中，第四电容能够稳定由于两开关管断开速度不同所产生的电压差，从而在直流电转交流电的负半周期稳定电压，杜绝谐振现象的发生。
结合上述第一方面，在第一种可能的实现方式中，该第三电容所在线路上串联设置有至少一个电感，和/或，该第四电容所在线路上串联设置有至少一个电感。
本实施例中，串联在第三电容，和/或，串联在第四电容上的至少一个电感，在充放电的过程中能够对第三电容和或第四电容起到保护的作用。
结合上述第一方面，在第二种可能的实现方式中，该第三电容所在线路上串联设置有至少一个电阻，和/或，该第四电容所在线路上串联设置有至少一个电阻。
本实施例中，串联在第三电容，和/或，串联在第四电容上的至少一个电阻，在充放电的过程中，该电阻能够通过充放电流，对第三电容和或第四电容起到保护的作用。
结合上述第一方面，在第三种可能的实现方式中，该第三电容所在线路上串联设置有至少一个电感及至少一个电阻，和/或，该第四电容所在线路上串联设置有至少一个电感及至少一个电阻。
本实施例中，串联在第三电容，和/或，串联在第四电容上的至少一个电阻及至少一个电感，在充放电的过程中，串联的电阻和电感能够通过协同工作，对第三电容和或第四电容起到保护的作用。
结合上述第一方面及第一方面第一至第三种可能的实现方式，在第四种可能的实现方式中，该第三电容所在线路与该母线的连接点以及该第四电容所在线路与该母线的连接点，均设置在该第一电容和该第二电容之间。
本实施例中，第三电容和第四电容均跨接在母线上的第一电容和第二电容之间，使得第一电容和第三电容构成并联电路，第二电容和第四电容构成并联电路，从而使得第一开关管和第四开关管闭合时，第三电容的电压等于第一电容的电压，在逆变输出正半周期对母线、第一竖桥和第二竖桥的电压起到了稳定的作用；第二开关管和第三开关管闭合时，第四电容的电压等于第二电容的电压，在逆变输出负半周期对母线、第一竖桥和第二竖桥的电压起到了稳定的作用，从而防止谐振问题的发生。进一步地，当第一开关管、第二开 关管、第三开关管及第四开关管全部断开时，第一电容的电压使得电路依次途径第三电容、第一电感、交流电网、第二电感、第四电容及第二电容，此时，第三电容和第四电容分别被充上1/2母线电压，当第一开关管与第四开关管闭合，或者第二开关管与第三开关管闭合时，由于第三电容放出的电压或第四电容放出的电压与第一电容或第二电容放出的电压值相等，均为1/2母线电压，因此电路的损耗较小，因此不仅能够有效防止因开关速度不同产生谐振问题，还能够有效降低电路损耗。
结合上述第一方面及第一方面第一至第三种可能的实现方式，在第五种可能的实现方式中，该第三电容所在线路与该母线的连接点以及该第四电容所在线路与该母线的连接点，均不设置在该第一电容和该第二电容之间。具体地，可以是第三电容所在线路与该母线的连接点以及该第四电容所在线路与该母线的连接点均设置在第一电容与直流电源之间；或者，第三电容所在线路与该母线的连接点以及该第四电容所在线路与该母线的连接点均设置在第二电容与直流电源之间；或者，第三电容所在线路与该母线的连接点设置在第一电容与直流电源之间，第四电容所在线路与该母线的连接点设置在第二电容与直流电源之间；或者，第三电容所在线路与该母线的连接点设置在第二电容与直流电源之间，第四电容所在线路与该母线的连接点设置在第一电容与直流电源之间。
本实施例中，通过将第三电容和第四电容的跨接点均不设置在该第一电容和该第二电容之间，在第一开关管和第四开关管断开的瞬间，第三电容能够吸收电压波动，从而对电路起到稳定的作用，同样地，在第二开关管和第三开关管断开的瞬间，第四电容能够吸收电压波动，从而对电路起到稳定的作用。因此能够有效防止因开关速度不同产生谐振问题。
结合上述第一方面及第一方面第一至第三种可能的实现方式，在第六种可能的实现方式中，在该第三电容所在线路与该母线的连接点以及该第四电容所在线路与该母线的连接点中，仅有一个连接点设置在该第一电容与该第二电容之间。具体地，可以为第三电容与该母线的连接点设置在第一电容与该第二电容之间，该第四电容所在线路与该母线的连接点设置在第一电容与直流电源之间或第二电容与直流电源之间；或者，可以为第四电容与该母线的连接点设置在第一电容与该第二电容之间，该第三电容所在线路与该母线的连接点设置在第一电容与直流电源之间或第二电容与直流电源之间。
本实施例中，通过将第三电容或第四电容中的一个跨接在第一电容和第二电容之间，另一个跨接在电容组与直流电源之间，使得第一开关管和第四开关管断开的瞬间，第三电容能够吸收电压波动，从而对电路起到稳定的作用，同样地，在第二开关管和第三开关管断开的瞬间，第四电容能够吸收电压波动，因此能够有效防止因开关速度不同产生谐振问题，但是会带来一定的电路损耗。
结合上述第一方面及第一方面第一至第六种可能的实现方式，在第七种可能的实现方式中，该滤波器包括第一电感及第二电感，该横桥包括续流开关组，其中，该第一电感连接在该第一竖桥与该交流电网之间，该第二电感连接在该交流电网与该第二竖桥之间，该续流开关组并联在该第一电感及该第二电感之间。
本实施例中，可选地，该逆变电路还包括第五电容，该第五电容并联在该第一电感与该第二电感之间，该第五电容用于稳定该滤波器的电压。
结合上述第一方面第七种可能的实现方式，在第八种可能的实现方式中，该续流开关组包括串联的第五开关管和第六开关管，其中，该第五开关管及该第六开关管可以为MOS管或IGBT器，
本实施例中，通过控制第五开关管及该第六开关管来控制电路由开启阶段进入到续流阶段，使得被励磁的第一电感和第二电感向交流电网并网。
从以上技术方案可以看出，本申请实施例具有以下优点：
本申请实施例提供的逆变电路可以通过在第一竖桥和第二竖桥上对母线跨接电容，从而使得HERIC拓扑工作过程中，在第一开关管与第四开关管断开，或者第二开关管与第三开关管在断开的过程中，跨接在母线上的电容能够稳定由于开关管断开速度不同所产生的电压浮动，抑制功率电路正常工作下因为开关开通关断速度差异引起的谐振问题，从而解决了此谐振带来的EMC相关问题。
本申请第二方面提供一种逆变器，包括控制单元和逆变功率单元，该控制单元用于控制该逆变功率单元的工作，其中，该逆变功率单元包括如上述第一方面或第一方面任意一种可能的实现方式所述的逆变电路。
从以上技术方案可以看出，本申请实施例具有以下优点：
本申请实施例提供的逆变器中的逆变电路可以通过在第一竖桥和第二竖桥上对母线跨接电容，从而使得HERIC拓扑工作过程中，在第一开关管与第四开关管断开，或者第二开关管与第三开关管在断开的过程中，跨接在母线上的电容能够稳定由于开关管断开速度不同所产生的电压浮动，抑制功率电路正常工作下因为开关开通关断速度差异引起的谐振问题，从而解决了此谐振带来的EMC相关问题。
本申请第三方面提供一种光伏发电系统，包括：光伏板、逆变器和交流电网；该光伏板与该逆变器相连，该逆变器与该交流电网相连；该光伏板用于将光能转化为直流电；该逆变器包括如上述第一方面或第一方面任意一种可能的实现方式所述的逆变电路，用于将该直流电转换为交流电；该交流电网用于传输该交流电。
从以上技术方案可以看出，本申请实施例具有以下优点：
本申请实施例提供的光伏发电系统中，逆变器实现直流电到交流电的转化，其中，该逆变器中的逆变电路可以通过在第一竖桥和第二竖桥上对母线跨接电容，从而使得HERIC拓扑工作过程中，在第一开关管与第四开关管断开，或者第二开关管与第三开关管在断开的过程中，跨接在母线上的电容能够稳定由于开关管断开速度不同所产生的电压浮动，抑制功率电路正常工作下因为开关开通关断速度差异引起的谐振问题，从而解决了此谐振带来的EMC相关问题。
附图说明
图1为现有技术中逆变电路的HERIC拓扑结构；
图2为本申请实施例中逆变电路的一种实施方式的电路图；
图3为本申请实施例中逆变电路的另一种实施方式的电路图；
图4为本申请实施例中逆变电路的另一种实施方式的电路图；
图5为本申请实施例中逆变电路的另一种实施方式的电路图；
图6为本申请实施例中逆变电路的另一种实施方式的电路图；
图7为本申请实施例中逆变电路的另一种实施方式的电路图；
图8为本申请实施例中逆变电路的另一种实施方式的电路图；
图9为本申请实施例中逆变电路的另一种实施方式的电路图；
图10为本申请实施例中逆变电路的另一种实施方式的电路图；
图11为本申请实施例中逆变电路的另一种实施方式的电路图；
图12为本申请实施例中逆变电路的另一种实施方式的电路图；
图13为本申请实施例中逆变电路的另一种实施方式的电路图；
图14为本申请实施例中逆变器的结构示意图；
图15为本申请实施例中光伏发电系统的结构示意图；
图16为本申请实施例中逆变电路的另一种实施方式的电路图；
图17为本申请实施例中逆变电路的另一种实施方式的电路图。
具体实施方式
下面结合附图，对本申请的实施例进行描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。本领域普通技术人员可知，随着技术的发展和新场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
逆变器是一种将直流电转化为交流电的装置，随着光伏发电产业在近年来得到迅猛发展。一个光伏发电系统包括光伏组件、逆变器、变压器和线缆等多个部件，其中，逆变器是光伏发电系统能量转换的核心部件，起到了将光伏组件输出的直流电转换为电网可用的交流电的作用。同时，逆变器在其余各种需要将直流电转化为交流电的系统中也广泛使用。
Highly efficient reliable inverter concept，HERIC，是一种高效可靠的逆变器概念，基于该概念所产生的HERIC拓扑由于其自身的低成本的特性在光伏逆变器产品中得到广泛的应用，如图1所示，现有技术中，在HERIC拓扑中包括第一竖桥10和第二竖桥20，其中，第一竖桥10的两端分别连接有第一开关管T1和第二开关管T2，第二竖桥20的两端分别连接有第三开关管T3和第四开关管T4，在逆变输出的上半周，第一开关管T1和第四开关管T4闭合，在进入续流阶段，此时，第一开关管T1和第四开关管T4同时断开，用于实际工作中，第一开关管T1和第四开关管T4的断开速度不能保持完全一致，例如第四 开关管T4的断开速度较第一开关管T1快，此时母线、第一竖桥10和第二竖桥20上的电压会升高，待第一开关管T1关闭后，电压又会回落，此过程中会产生谐振现象。从而影响设备和系统在其电磁环境中能正常工作且不对环境中任何事物构成不能承受的电磁骚扰的能力(electro magnetic compatibility,EMC)，造成EMC的传导、辐射测试项目结果超标。
因此，为了解决上述问题，本申请实施例提供一种逆变电路，通过在HERIC拓扑的竖桥与横桥连接点位置对母线加跨接电容的方案，来抑制功率电路正常工作下因为开关关断速度差异引起的谐振问题。
需要说明的是，本申请实施例所提供的逆变电路及逆变器可以是用于光伏发电系统的光伏逆变器，也可以是应用于其他需要将直流电转化为交流电的电路或装置，对此，本申请实施例并不进行限定，为便于理解，本申请实施例以光伏逆变器为例，对本申请实施例所提供的逆变器做详细说明。
以下结合附图，对本申请实施例所提供的逆变电路进行具体说明。
请参阅图1，如图1所示，本申请实施例所提供的逆变电路基于现有技术中的HERIC拓扑，具体包括：母线、第一竖桥10、第二竖桥20、横桥及滤波器，其中，该母线上设置有电容组，该母线与直流电源并联，该电容组包括串联设置的第一电容Cs1和第二电容Cs2，其中，该第一电容Cs1与该直流电源的正极DC+连接，该第二电容Cs2与该直流电源的负极DC-连接，该第一电容Cs1及该第二电容Cs2用于被该直流电源充电，以向该第一竖桥10、该第二竖桥20和该横桥提供直流电压。
该母线与该第一竖桥10并联，该第一竖桥10与该第二竖桥20并联，该第一竖桥10的包括串联的第一开关管T1、第二开关管T2以及连接该第一开关管T1和该第二开关管T2的线路，该第二竖桥20包括串联的第三开关管T3、第四开关管T4以及连接该第三开关管T3和该第四开关管T4的线路，该横桥的两端分别与该第一竖桥10和该第二竖桥20连接，具体地，该横桥具体包括依次经过连接点A、连接点B、连接点C及连接点D的电路结构，其中，所述连接点A为横桥与第一桥臂10的连接点，连接点D为横桥与第二桥臂20的连接点。
需要说明的是，该第一竖桥10及该第二竖桥20不仅限于上述结构，还可以是相关的变形拓扑结构，例如，该第一竖桥10或第二竖桥20上具备两个以上的开关管；该横桥同样不仅限与上述结构，还可以是相关的变形拓扑结构，例如包括上述横桥部分结构的拓扑结构，对此本申请实施例并不进行限定。
进一步地，该第一开关管T1的源极通过导线与第二开关管T2的漏极连接，该第一开关管T1的漏极通过导线与该第一电容Cs1连接，该第二开关管T2的源极通过导线与该第二电容Cs2连接。
具体地，该第一开关管T1、该第二开关管T2、该第三开关管T3及该第四开关管T4可以为MOS管、IGBT器或其他起开关作用的半导体器件，对此本申请实施例并不进行限定，作为一种可选的方式，当第一开关管T1、该第二开关管T2、该第三开关管T3及该第四开关管T4为MOS管时，每个开关管上还可以分别并联有二极管和电容，具体地，第一开关管T1、该第二开关管T2、该第三开关管T3及该第四开关管T4可以分别并联有电容C1、电容C2、电容C3及电容C4，当开关管为MOS管时，该MOS管可以为氮化镓MOS管或碳化硅MOS管。
需要说明的是，上述第一电容Cs1和第二电容Cs2在实际物理实现过程中，第一电容Cs1或第二电容Cs2可以通过一个电容来实现，也可以通过多个电容器件来实现，对此本申请实施例并不进行限定。
该滤波器并联在该横桥上，该滤波器与交流电网AC连接，该横桥用于通过该滤波器向交流电网AC供电。该滤波器具体包括依次经过连接点B、连接点E、连接点F及连接点C的电路结构，其中，该滤波器通过连接点B和连接点C并联在横桥上，该滤波器通过连接点E和连接点F与交流电网AC连接。
具体地，该滤波器包括第一电感L1及第二电感L2，该横桥包括续流开关组，其中，
该第一电感L1连接在该第一竖桥10与交流电网AC之间，该第二电感L2连接在交流电网AC连接与第二竖桥20之间，该续流开关组并联在该第一电感L1及该第二电感L2之间，其中，第一电感L1通过连接点B与横桥连接，第二电感L2通过连接点C与横桥连接，第一电感L1和第二电感L2分别通过连接点E和连接点F与交流电网AC连接。
该第一电感L1及该第二电感L2用于，当该第一开关管T1与该第四开关管T4，或者，该第二开关管T2与该第三开关管T3闭合时，被该直流电源励磁；
该续流开关组用于，当该第一开关管T1与该第四开关管T4断开时，或者，该第二开关管T2与该第三开关管T3断开时，闭合，以使得该第一电感L1及该第二电感L2向该输出供电。
进一步地，该续流开关组包括串联的第五开关管T5和第六开关管T6，其中，
该第五开关管T5用于保持闭合，
该第六开关管T6用于，当该第一开关管T1与该第四开关管T4断开时，或者，该第二开关管T2与该第三开关管T3断开时，闭合，以使得该第一电感L1及该第二电感L2向输出供电。
进一步地，该逆变器还包括第五电容Cx1，该第五电容Cx1通过连接点E及连接点F并联在该第一电感L1与该第二电感L2之间，该第五电容Cx1用于稳定该横桥的电压，使得该横桥向交流电网AC输出稳定的电压。
可选地，该第五开关管T5及该第六开关管T6为MOS管，该MOS管可以为MOS管、IGBT器或其他起开关作用的半导体器件，对此本申请实施例并不进行限定，作为一种可选的方式，当该第五开关管T5及该第六开关管T6为MOS管时，第五开关管T5及该第六开关管T6为MOS管上还可以分别并联有二极管和电容C5及C6，该MOS管可以为氮化镓MOS管或碳化硅MOS管。
需要说明的是，本申请实施例中的逆变电路所基于的拓扑结构除了上述的HERIC拓扑外，还可以是HERIC拓扑的相关变形拓扑结构，对此，本申请实施例并不进行限定。
具体工作时，由于母线与直流电源并联，直流电源向母线中的第一电容Cs1和第二电容Cs2充电。
在逆变输出正半周期的开启阶段，第一开关管T1与第四开关管T4闭合，此时，第一电容Cs1通过母线正极DC+释放电压，电流依次经过第一开关管T1、第一电感L1、第二电感L2及第四开关管T4，最终流向母线负极DC-，从而走完该回路，在此过程中，第一电感L1和第二电感L2被充电，实现第一电感L1和第二电感L2的励磁。
在逆变输出正半周期的续流阶段，第一开关管T1与第四开关管T4断开，续流开关组闭合，其中，续流开关组具体闭合的实现方式为：第五开关管T5一直保持闭合状态，当续流 开关组需要由断开变为闭合时，第六开关管T6有断开变为闭合，以实现续流开关组的闭合；第一电感L1和第二电感L2放电，电流在交流电网AC、第一电感L1、续流开关组、第二电感L2之间形成回路，从而在续流阶段，第一电感L1和第二电感L2持续地向交流电网AC充电，从而实现在交流电的正半周期，所述横桥向所述输出供电。
在逆变输出负半周期的开启阶段，第二开关管T2与第三开关管T3闭合，此时，第二电容Cs2通过母线负极DC-释放电压，电流依次经过第二开关管T2、第一电感L1、第二电感L2及第三开关管T3，最终流向母线正极DC+，从而走完该回路，在此过程中，第一电感L1和第二电感L2被充电，实现第一电感L1和第二电感L2的励磁。
在逆变输出负半周期的续流阶段，第二开关管T2与第三开关管T3断开，续流开关组闭合，其中，续流开关组具体闭合的实现方式为：第五开关管T5一直保持闭合状态，当续流开关组需要由断开变为闭合时，第六开关管T6有断开变为闭合，以实现续流开关组的闭合；第一电感L1和第二电感L2放电，电流在交流电网AC、第一电感L1、续流开关组、第二电感L2之间形成回路，从而在续流阶段，第一电感L1和第二电感L2持续地向交流电网AC充电，从而实现在交流电的负半周期，所述横桥向所述输出供电。
在上述工作过程，实现了HERIC拓扑的逆变电路将直流电源的输出的直流电转化为交流电，从而向交流电网AC供电的过程。
然而，在上述出正半周期或出负半周期由开启阶段转化为续流阶段的过程中，第一开关管T1断开的速度无法与第四开关管T4断开的速度保持同步，例如，第四开关管T4断开的速度比第一开关管T1断开的速度快，当第四开关管T4断开而第一开关管T1尚未断开时，母线、第一竖桥10及第二竖桥20的电压会被拉升至母线正电压，待第一开关管T1关闭后，母线、第一竖桥10及第二竖桥20的电压又会回到母线中点电压，在此过程中，电压浮动的现象会引起谐振现象的发生，导致影响整个设备和系统在其电磁环境中能正常工作且不对环境中任何事物构成不能承受的电磁骚扰的能力(electro magnetic compatibility，EMC)，从而造成EMC的传导、辐射测试项目结果超标。同理，在第二开关管T2和第三开关管T3断开的过程中，也面临同样的问题。
为了克服上述问题，本申请实施例所提供的逆变电路在现有HERIC拓扑的基础上跨接了第三电容Csy1和第四电容Csy2。
请参阅图2，如图2所示，该第三电容Csy1连接在该母线与该第一竖桥10之间，其中，该第三电容Csy1与该第一竖桥10的连接点H位于该第一开关管T1与该第二开关管T2之间；
该第四电容Csy2连接在该母线与该第二竖桥20之间，其中，该第四电容Csy2与该第二竖桥20的连接点J位于该第三开关管T3与该第四开关管T4之间；
该第三电容Csy1用于，当该第一开关管T1和该第四开关管T4断开时，稳定该母线、该第一竖桥10及该第二竖桥20的电压；
该第四电容Csy2用于，当该第二开关管T2和该第三开关管T3断开时，稳定该母线、该第一竖桥10及该第二竖桥20的电压。
如图2所示，第三电容Csy1与母线的连接点G设置在第一电容Cs1和第二电容Cs2之间，第三电容Csy1与第一竖桥10通过连接点H连接；第四电容Csy2与母线的连接点I设置在第一 电容Cs1和第二电容Cs2之间，第四电容Csy2与第二竖桥20通过连接点J连接。
本实施例中，在逆变输出正半周期的开启阶段，第一开关管T1与第四开关管T4闭合，此时，第一电容Cs1与第三电容Csy1构成并联的等效电路，第一电容Cs1向第三电容Csy1充电，且第一电容Cs1与第三电容Csy1的电压相等。由于第一电容Cs1和第二电容Cs2构成直流电源的分压电路，此时，第一电容Cs1和第二电容Cs2的电压分别等于母线电压的1/2，既1/2母线电压，因此，此时第三电容Csy1的电压也等于1/2母线电压。在逆变输出正半周期的续流阶段，第一开关管T1与第四开关管T4断开，若第四开关管T4断开的速度比第一开关管T1断开的速度快，当第四开关管T4断开而第一开关管T1尚未断开时，第三电容Csy1能够被母线正电压的电容进一步充电，从而杜绝由于电压升高导致的波动；若第四开关管T4断开的速度比第一开关管T1断开的速度慢，当第一开关管T1断开而第四开关管T4尚未断开时，第三电容Csy1所输出的1/2母线电压能够起到稳定作用，防止母线、第一竖桥10和第二竖桥20上由于电压升高导致的波动；从而有效防止了HERIC拓扑逆变电路工作过程中因第一开关管T1和第四开关管T4的断开速度不同产生谐振问题。
在逆变输出负半周期的开启阶段，第二开关管T2与第三开关管T3闭合，此时，第二电容Cs2与第四电容Csy2构成并联的等效电路，第二电容Cs2向第四电容Csy2充电，且第二电容Cs2与第四电容Csy2的电压相等。由于第一电容Cs1和第二电容Cs2构成直流电源的分压电路，此时，第一电容Cs1和第二电容Cs2的电压分别等于母线电压的1/2，既1/2母线电压，因此，此时第四电容Csy2的电压也等于1/2母线电压。在逆变输出负半周期的续流阶段，第二开关管T2与第三开关管T3断开，若第三开关管T3断开的速度比第二开关管T2断开的速度快，当第三开关管T3断开而第二开关管T2尚未断开时，第四电容Csy2能够被母线正电压的电容进一步充电，从而杜绝由于电压升高导致的波动；若第三开关管T3断开的速度比第二开关管T2断开的速度慢，当第二开关管T2断开而第三开关管T3尚未断开时，第四电容Csy2所输出的1/2母线电压能够起到稳定作用，防止母线、第一竖桥10和第二竖桥20上由于电压升高导致的波动；从而有效防止了HERIC拓扑逆变器工作过程中因第二开关管T2和第三开关管T3的断开速度不同产生谐振问题。
上述逆变输出正半周期和负半周期的区别在于，在正半周期，第一电容Cs1被直流电源的正极DC+充电，向第三电容Csy1充1/2母线正电压，在负半周期，第二电容Cs2被直流电源的负极DC-充电，向第四电容Csy2充1/2母线负电压。
需要说明的是，在上述第一种实施方式中，通过将第三电容Csy1和第四电容Csy2跨接在母线上第一电容Cs1和第二电容Cs2之间的位置，使得第一电容Cs1和第三电容Csy1构成并联电路，第二电容Cs2和第四电容Csy2构成并联电路，从而使得第一开关管T1和第四开关管T4闭合时，第三电容Csy1的电压等于第一电容Cs1的电压，在逆变输出正半周期对母线、第一竖桥10和第二竖桥20的电压起到了稳定的作用；第二开关管T2和第三开关管T3闭合时，第四电容Csy2的电压等于第二电容Cs2的电压，在逆变输出负半周期对母线、第一竖桥10和第二竖桥20的电压起到了稳定的作用，从而防止谐振问题的发生。进一步地，当第一开关管T1、第二开关管T2、第三开关管T3及第四开关管T4全部断开时，第一电容Cs1的电压使得电路依次途径第三电容Csy1、第一电感L1、交流电网AC、第二电感L2、第四电容Csy2及 第二电容Cs2，此时，第三电容Csy1和第四电容Csy2分别被充上1/2母线电压，当第一开关管T1与第四开关管T4闭合，或者第二开关管T2与第三开关管T3闭合时，由于第三电容Csy1放出的电压或第四电容Csy2放出的电压与第一电容Cs1或第二电容Cs2放出的电压值相等，均为1/2母线电压，因此电路的损耗较小，因此，本申请实施例中的第一种实施方式不仅能够有效防止因开关速度不同产生谐振问题，还能够有效降低电路损耗，第一种实施方式为最优选的实施方式。
需要说明的是，上述第三电容Csy1和第四电容Csy2在实际物理实现过程中，第三电容Csy1或第四电容Csy2可以通过一个电容来实现，也可以通过多个电容器件来实现，对此本申请实施例并不进行限定。
需要进一步说明的是，上述第三电容Csy1与母线的连接点G以及第四电容Csy2与母线的连接点I与母线连接的方式，只是本申请实施例所提供的第一种实施方式，可选地，根据该连接点所在位置的不同，还可以采用不同的工作方式稳定该母线、该第一竖桥10及该第二竖桥20的电压。具体还包括：
1、该第三电容所在线路与该母线的连接点以及该第四电容所在线路与该母线的连接点，均设置在该电容组与该直流电源之间。
2、该第三电容所在线路与该母线的连接点以及该第四电容所在线路与该母线的连接点，均不设置在该第一电容和该第二电容之间。
3、在该第三电容所在线路与该母线的连接点以及该第四电容所在线路与该母线的连接点中，仅有一个连接点设置在该第一电容与该第二电容之间。
为便于理解，以下结合附图，对本申请实施例中第三电容Csy1和第四电容Csy2在逆变电路中各种不同的连接情况做详细说明。
一、第三电容Csy1和第四电容Csy2均跨接在母线上的第一电容Cs1和直流电源正极之间。
请参阅图3，如图3所示，在第二种实施方式中，第三电容Csy1与母线的连接点G设置在的第一电容Cs1和直流电源正极之间，第三电容Csy1与第一竖桥10通过连接点H连接；第四电容Csy2与母线的连接点I设置在第一电容Cs1和直流电源正极之间，第四电容Csy2与第二竖桥20通过连接点J连接。
本实施例中，在逆变输出正半周期的开启阶段，第一开关管T1与第四开关管T4闭合，此时，电流从第一电容Cs1出发，依次经过第一开关管T1、第一电感L1、交流电网AC、第二电感L2、第四开关管T4及第二电容Cs2；在逆变输出正半周期的续流阶段，第一开关管T1与第四开关管T4断开，若第四开关管T4断开的速度与第一开关管T1断开的速度不同，所产生的母线正电压向第三电容Csy1充电，从而使得第三电容Csy1能够吸收母线、第一竖桥10和第二竖桥20上升高的电压，杜绝了由于电压升高导致的波动，从而有效防止了HERIC拓扑逆变电路工作过程中因第一开关和第四开关的断开速度不同产生谐振问题。
在逆变输出负半周期的开启阶段，第二开关管T2与第三开关管T3闭合，此时，电流从第二电容Cs2出发，依次经过第二开关管T2、第一电感L1、交流电网AC、第二电感L2、第三开关管T3及第一电容Cs1；在逆变输出负半周期的续流阶段，第二开关管T2与第三开关管T3 断开，若第二开关管T2断开的速度与第三开关管T3断开的速度不同，所产生的母线负电压向第四电容Csy2充电，从而使得第四电容Csy2能够吸收母线、第一竖桥10和第二竖桥20上的电压变化，杜绝了由于电压变化导致的波动，从而有效防止了HERIC拓扑逆变电路工作过程中因第二开关和第三开关的断开速度不同产生谐振问题。
需要说明的是，在上述第二种实施方式中，通过将第三电容Csy1和第四电容Csy2跨接在母线电压正的位置，从而使得第一开关管T1和第四开关管T4断开的瞬间，第三电容Csy1能够吸收电压波动，从而对电路起到稳定的作用，同样地，在第二开关管T2和第三开关管T3断开的瞬间，第四电容Csy2能够吸收电压波动，从而对电路起到稳定的作用。进一步地，当第一开关管T1、第二开关管T2、第三开关管T3及第四开关管T4全部断开时，第一电容Cs1的电压使得电路依次途径第三电容Csy1和第四电容Csy2流经整个回路，此时，第三电容Csy1和第四电容Csy2分别被充上一个母线电压，当第一开关管T1与第四开关管T4闭合，或者第二开关管T2与第三开关管T3闭合时，由于第三电容Csy1放出的电压或第四电容Csy2放出的电压大于第一电容Cs1或第二电容Cs2放出的电压值(如前所述，第一电容Cs1与第二电容Cs2组成的分压电路中，第一电容Cs1和第二电容Cs2的电压分别等于1/2母线电压)，因此当第一开关管T1与第四开关管T4闭合，或者第二开关管T2与第三开关管T3闭合时，第三电容Csy1或第四电容Csy2需要放出额外多出的电压，此过程会造成电路的外损耗。因此，本申请实施例中的第二种实施方式能够有效防止因开关速度不同产生谐振问题，但是会带来一定的电路损耗，因此第二种实施方式可以作为一种候选的实施方式。
二、第三电容Csy1和第四电容Csy2均跨接在母线上的第二电容Cs2和直流电源负极之间。
请参阅图4，如图4所示，在第三种实施方式中，第三电容Csy1与母线的连接点G设置在第二电容Cs2和直流电源负极之间，第三电容Csy1与第一竖桥10通过连接点H连接；第四电容Csy2与母线的连接点I设置在第二电容Cs2和直流电源负极之间，第四电容Csy2与第二竖桥20通过连接点J连接。
本实施例中，在逆变输出正半周期的开启阶段，第一开关管T1与第四开关管T4闭合，此时，电流从第一电容Cs1出发，依次经过第一开关管T1、第一电感L1、交流电网AC、第二电感L2、第四开关管T4及第二电容Cs2；在逆变输出正半周期的续流阶段，第一开关管T1与第四开关管T4断开，若第四开关管T4断开的速度与第一开关管T1断开的速度不同，所产生的母线正电压向第三电容Csy1充电，从而使得第三电容Csy1能够吸收母线、第一竖桥10和第二竖桥20上升高的电压，杜绝了由于电压升高导致的波动，从而有效防止了HERIC拓扑逆变电路工作过程中因第一开关和第四开关的断开速度不同产生谐振问题。
在逆变输出负半周期的开启阶段，第二开关管T2与第三开关管T3闭合，此时，电流从第二电容Cs2出发，依次经过第二开关管T2、第一电感L1、交流电网AC、第二电感L2、第三开关管T3及第一电容Cs1；在逆变输出负半周期的续流阶段，第二开关管T2与第三开关管T3断开，若第二开关管T2断开的速度与第三开关管T3断开的速度不同，所产生的母线负电压向第四电容Csy2充电，从而使得第四电容Csy2能够吸收母线、第一竖桥10和第二竖桥20上的电压变化，杜绝了由于电压变化导致的波动，从而有效防止了HERIC拓扑逆变电路工作过 程中因第二开关和第三开关的断开速度不同产生谐振问题。
需要说明的是，在上述第三种实施方式中，通过将第三电容Csy1和第四电容Csy2跨接在母线电压负的位置，从而使得第一开关管T1和第四开关管T4断开的瞬间，第三电容Csy1能够吸收电压波动，从而对电路起到稳定的作用，同样地，在第二开关管T2和第三开关管T3断开的瞬间，第四电容Csy2能够吸收电压波动，从而对电路起到稳定的作用。进一步地，当第一开关管T1、第二开关管T2、第三开关管T3及第四开关管T4全部断开时，第一电容Cs1的电压使得电路依次途径第三电容Csy1和第四电容Csy2流经整个回路，此时，第三电容Csy1和第四电容Csy2分别被充上一个母线电压，当第一开关管T1与第四开关管T4闭合，或者第二开关管T2与第三开关管T3闭合时，由于第三电容Csy1放出的电压或第四电容Csy2放出的电压大于第一电容Cs1或第二电容Cs2放出的电压值(如前所述，第一电容Cs1与第二电容Cs2组成的分压电路中，第一电容Cs1和第二电容Cs2的电压分别等于1/2母线电压)，因此当第一开关管T1与第四开关管T4闭合，或者第二开关管T2与第三开关管T3闭合时，第三电容Csy1或第四电容Csy2需要放出额外多出的电压，此过程会造成电路的外损耗。因此，本申请实施例中的第三种实施方式能够有效防止因开关速度不同产生谐振问题，但是会带来一定的电路损耗；本申请第三种实施方式与上述第二种实施方式等效，区别在于在第二种实施方式中，第三电容Csy1和第四电容Csy2跨接在母线的电压正位置，在第二种实施方式中，第三电容Csy1和第四电容Csy2跨接在母线的电压负位置，因此第三种实施方式可以作为上述第二种实施方式的替换方案。
上述介绍了本申请实施例中，在HERIC拓扑逆变电路基础上改进的三个方案，分别为：第一种实施方式：在第一电容Cs1和第二电容Cs2之间(即母线中点)跨接第三电容Csy1和第四电容Csy2；第二种实施方式：在第一电容Cs1与直流电源正极之间(即母线正)跨接第三电容Csy1和第四电容Csy2；第三种实施方式：在第二电容Cs2与直流电源负极之间(即母线负)跨接第三电容Csy1和第四电容Csy2。可选地，基于上述方式进行排列组合，还可以包括以下实现方式：
第四种实施方式：第三电容Csy1跨接在母线中点，第四电容Csy2跨接在母线正；
第五种实施方式：请参阅图16，如图16所示，第三电容Csy1跨接在母线中点，第四电容Csy2跨接在母线负；
第六种实施方式：第四电容Csy2跨接在母线中点，第三电容Csy1跨接在母线正；
第七种实施方式：第四电容Csy2跨接在母线中点，第三电容Csy1跨接在母线负；
第八种实施方式：请参阅图17，如图17所示，第三电容Csy1跨接在母线正，第四电容Csy2跨接在母线负；
第九种实施方式：第三电容Csy1跨接在母线负，第四电容Csy2跨接在母线正。
在上述第四至第九种实施方式中，第三电容Csy1及第四电容Csy2的跨接方式的连接方案和工作原理可参阅上述第一至第三种实施方式，区别仅仅在于跨接方式的排列组合不同，因此此处不再赘述。
需要说明的是，在上述任意一种实施例中，为了保护第三电容Csy1和第四电容Csy2充电的稳定性，可以在第三电容Csy1和第四电容Csy2上串联阻抗网络，从而在第三电容Csy1 和第四电容Csy2充电的过程中，保持第三电容Csy1和第四电容Csy2充电的稳定性，具体地，该阻抗网络包括串联的至少一个电感，和/或，至少一个电阻。为便于理解，以下结合附图对阻抗网络的不同情况做具体的说明。
请参阅图5，如图5所示，图5为在本申请实施例第一种实施方式的基础上，在第三电容Csy1和第四电容Csy2上分别串联设置电感Ls1和电感Ls2，其中，电感Ls1与第三电容Csy1串联，电感Ls2与第四电容Csy2串联。
本实施例中，电感Ls1和电感Ls2能够在第三电容Csy1和第四电容Csy2被充电的过程中，分担第三电容Csy1和第四电容Csy2被充入的电流，从而避免第三电容Csy1和第四电容Csy2因瞬时过大电量的充电而导致第三电容Csy1和第四电容Csy2发生损坏。当向第三电容Csy1和第四电容Csy2的充电结束时，电感Ls1和电感Ls2可以释放被充入的电量，缓慢向第三电容Csy1和第四电容Csy2充电，从而在确保大电流不对第三电容Csy1和第四电容Csy2造成损坏的同时，不对过剩的电流造成浪费。
进一步地，请参阅图6，如图6所示，图6为在本申请实施例第一种实施方式的基础上，在第三电容Csy1和第四电容Csy2上分别串联设置电阻Rs1及电阻Rs2，其中，电阻Rs1与第三电容Csy1串联，电阻Rs2与第四电容Csy2串联。
本实施例中，当第三电容Csy1和第四电容Csy2被充电的过程中，若所充电流过大，第三电容Csy1和第四电容Csy2所串联的电阻Rs1及电阻Rs2能够将额外的电能转化掉，从而保护第三电容Csy1和第四电容Csy2，防止第三电容Csy1和第四电容Csy2因大电量充电发生损坏。
进一步地，请参阅图7，如图7所示，图7为在本申请实施例第一种实施方式的基础上，在第三电容Csy1和第四电容Csy2上分别串联设置电感Ls1、电感Ls2、电阻Rs1及电阻Rs2，其中，电感Ls1及电阻Rs1与第三电容Csy1串联，电感Ls2及电阻Rs2与第四电容Csy2串联。
本实施例中，电感Ls1和电感Ls2能够在第三电容Csy1和第四电容Csy2被充电的过程中，分担第三电容Csy1和第四电容Csy2被充入的电流，从而避免第三电容Csy1和第四电容Csy2因瞬时过大电量的充电而导致第三电容Csy1和第四电容Csy2发生损坏，进一步地，所串联的电阻Rs1及电阻Rs2能够将额外的电能转化掉，从而进一步保护第三电容Csy1和第四电容Csy2，防止第三电容Csy1和第四电容Csy2因大电量充电发生损坏。
请参阅图8，如图8所示，图8为在本申请实施例第二种实施方式的基础上，在第三电容Csy1和第四电容Csy2上分别串联设置电感Ls1和电感Ls2，其中，电感Ls1与第三电容Csy1串联，电感Ls2与第四电容Csy2串联。
本实施例中，电感Ls1和电感Ls2能够在第三电容Csy1和第四电容Csy2被充电的过程中，分担第三电容Csy1和第四电容Csy2被充入的电流，从而避免第三电容Csy1和第四电容Csy2因瞬时过大电量的充电而导致第三电容Csy1和第四电容Csy2发生损坏。当向第三电容Csy1和第四电容Csy2的充电结束时，电感Ls1和电感Ls2可以释放被充入的电量，缓慢向第三电容Csy1和第四电容Csy2充电，从而在确保大电流不对第三电容Csy1和第四电容Csy2造成损坏的同时，不对过剩的电流造成浪费。
进一步地，请参阅图9，如图9所示，图9为在本申请实施例第二种实施方式的基础上， 在第三电容Csy1和第四电容Csy2上分别串联设置电阻Rs1及电阻Rs2，其中，电阻Rs1与第三电容Csy1串联，电阻Rs2与第四电容Csy2串联。
本实施例中，当第三电容Csy1和第四电容Csy2被充电的过程中，若所充电流过大，第三电容Csy1和第四电容Csy2所串联的电阻Rs1及电阻Rs2能够将额外的电能转化掉，从而保护第三电容Csy1和第四电容Csy2，防止第三电容Csy1和第四电容Csy2因大电量充电发生损坏。
进一步地，请参阅图10，如图10所示，图10为在本申请实施例第二种实施方式的基础上，在第三电容Csy1和第四电容Csy2上分别串联设置电感Ls1、电感Ls2、电阻Rs1及电阻Rs2，其中，电感Ls1及电阻Rs1与第三电容Csy1串联，电感Ls2及电阻Rs2与第四电容Csy2串联。
本实施例中，电感Ls1和电感Ls2能够在第三电容Csy1和第四电容Csy2被充电的过程中，分担第三电容Csy1和第四电容Csy2被充入的电流，从而避免第三电容Csy1和第四电容Csy2因瞬时过大电量的充电而导致第三电容Csy1和第四电容Csy2发生损坏，进一步地，所串联的电阻Rs1及电阻Rs2能够将额外的电能转化掉，从而进一步保护第三电容Csy1和第四电容Csy2，防止第三电容Csy1和第四电容Csy2因大电量充电发生损坏。
请参阅图11，如图11所示，图11为在本申请实施例第三种实施方式的基础上，在第三电容Csy1和第四电容Csy2上分别串联设置电感Ls1和电感Ls2，其中，电感Ls1与第三电容Csy1串联，电感Ls2与第四电容Csy2串联。
本实施例中，电感Ls1和电感Ls2能够在第三电容Csy1和第四电容Csy2被充电的过程中，分担第三电容Csy1和第四电容Csy2被充入的电流，从而避免第三电容Csy1和第四电容Csy2因瞬时过大电量的充电而导致第三电容Csy1和第四电容Csy2发生损坏。当向第三电容Csy1和第四电容Csy2的充电结束时，电感Ls1和电感Ls2可以释放被充入的电量，缓慢向第三电容Csy1和第四电容Csy2充电，从而在确保大电流不对第三电容Csy1和第四电容Csy2造成损坏的同时，不对过剩的电流造成浪费。
进一步地，请参阅图12，如图12所示，图12为在本申请实施例第三种实施方式的基础上，在第三电容Csy1和第四电容Csy2上分别串联设置电阻Rs1及电阻Rs2，其中，电阻Rs1与第三电容Csy1串联，电阻Rs2与第四电容Csy2串联。
本实施例中，当第三电容Csy1和第四电容Csy2被充电的过程中，若所充电流过大，第三电容Csy1和第四电容Csy2所串联的电阻Rs1及电阻Rs2能够将额外的电能转化掉，从而保护第三电容Csy1和第四电容Csy2，防止第三电容Csy1和第四电容Csy2因大电量充电发生损坏。
进一步地，请参阅图13，如图13所示，图13为在本申请实施例第三种实施方式的基础上，在第三电容Csy1和第四电容Csy2上分别串联设置电感Ls1、电感Ls2、电阻Rs1及电阻Rs2，其中，电感Ls1及电阻Rs1与第三电容Csy1串联，电感Ls2及电阻Rs2与第四电容Csy2串联。
本实施例中，电感Ls1和电感Ls2能够在第三电容Csy1和第四电容Csy2被充电的过程中，分担第三电容Csy1和第四电容Csy2被充入的电流，从而避免第三电容Csy1和第四电容Csy2因瞬时过大电量的充电而导致第三电容Csy1和第四电容Csy2发生损坏，进一步地，所串联的电阻Rs1及电阻Rs2能够将额外的电能转化掉，从而进一步保护第三电容Csy1和第四 电容Csy2，防止第三电容Csy1和第四电容Csy2因大电量充电发生损坏。
进一步地，在上述第四至第九种实施方式的基础上，也可以在第三电容Csy1及第四电容Csy2中设置阻抗网络，具体的设置方式可参阅上述第一至第三种实施方式，区别仅仅在于跨接方式的排列组合不同，因此此处不再赘述。
需要说明的是，当上述设置了阻抗网络时，阻抗网络可以保护第三电容Csy1和第四电容Csy2，防止第三电容Csy1和第四电容Csy2在充电过程中损坏，同时，阻抗网络的存在也会降低第三电容Csy1和第四电容Csy2，从而一定程度上影响第三电容Csy1和第四电容Csy2在开关管断开过程中对于谐振问题的保护情况，因此，用户可根据实际使用情况，选择是否增加阻抗网络，以及阻抗网络中，具体设置的电容电感数量。
如图14所示，本申请实施例还提供一种逆变器，该逆变器包括控制单元1401及逆变功率单元1402，该控制单元用于控制该逆变功率单元的工作，其中，该逆变功率单元1402包括上述任意一种实施方式所述的逆变电路，可以参阅前述逆变电路的描述进行理解；该控制单元1401可以包括控制芯片及用于实现该控制芯片功能的电路结构。其中，该控制单元1401逆变功率单元1402的工作，可以包括，控制单元1401控制逆变功率单元1402中逆变电路的各个开关管的开闭。
如图15所示，本申请实施例还提供一种光伏发电系统，包括：光伏板1501、逆变器1502和交流电网1503；该光伏板1501与该逆变器1502相连，该逆变器1502与该交流电网1503相连；该光伏板1501用于将光能转化为直流电；该逆变器1502包括上述任意一种实施例所述的逆变电路，用于将该直流电转换为交流电；该交流电网1503用于传输该交流电。
本实施例中，逆变器将光伏板通过太阳能发电产生的直流电转化为交流电并入交流电网，从而使得太阳能得以利用，其中，该逆变器中所包含的逆变电路为述任意一种实施例所述的逆变电路，可以参阅前述逆变电路的描述进行理解，该逆变电路不仅能够将交流电转化为直流电，还可以避免因谐振现象带来的EMC问题。
以上对本申请实施例所提供的逆变电路、逆变器及光伏发电系统进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (11)

  1. 一种逆变电路，其特征在于，包括：母线、第一竖桥、第二竖桥、横桥及滤波器，其中，所述母线上设置有电容组，所述母线与直流电源并联，所述电容组包括串联设置的第一电容和第二电容；
    所述母线与所述第一竖桥并联，所述第一竖桥与所述第二竖桥并联，所述第一竖桥包括串联的第一开关管和第二开关管，所述第二竖桥包括串联的第三开关管和第四开关管，所述横桥的两端分别与所述第一竖桥和所述第二竖桥连接；
    所述滤波器并联在所述横桥上，所述滤波器与交流电网连接，所述横桥用于通过所述滤波器向交流电网供电；
    所述逆变电路还包括：
    第三电容，所述第三电容连接在所述母线与所述第一竖桥之间，其中，所述第三电容所在线路与所述第一竖桥的连接点位于所述第一开关管与所述第二开关管之间；
    第四电容，所述第四电容连接在所述母线与所述第二竖桥之间，其中，所述第四电容所在线路与所述第二竖桥的连接点位于所述第三开关管与所述第四开关管之间。
  2. 根据权利要求1所述的逆变电路，其特征在于，所述第三电容所在线路上串联设置有至少一个电感，和/或，所述第四电容所在线路上串联设置有至少一个电感。
  3. 根据权利要求1所述的逆变电路，其特征在于，所述第三电容所在线路上串联设置有至少一个电阻，和/或，所述第四电容所在线路上串联设置有至少一个电阻。
  4. 根据权利要求1所述的逆变电路，其特征在于，所述第三电容所在线路上串联设置有至少一个电感及至少一个电阻，和/或，所述第四电容所在线路上串联设置有至少一个电感及至少一个电阻。
  5. 根据权利要求1至4任一所述的逆变电路，其特征在于，所述第三电容所在线路与所述母线的连接点以及所述第四电容所在线路与所述母线的连接点，均设置在所述第一电容和所述第二电容之间。
  6. 根据权利要求1至4任一所述的逆变电路，其特征在于，所述第三电容所在线路与所述母线的连接点以及所述第四电容所在线路与所述母线的连接点，均不设置在所述第一电容和所述第二电容之间。
  7. 根据权利要求1至4任一所述的逆变电路，其特征在于，在所述第三电容所在线路与所述母线的连接点以及所述第四电容所在线路与所述母线的连接点中，仅有一个连接点设置在所述第一电容与所述第二电容之间。
  8. 根据权利要求1至7任一所述的逆变电路，其特征在于，所述滤波器包括第一电感及第二电感，所述横桥包括续流开关组，其中，
    所述第一电感连接在所述第一竖桥与所述交流电网之间，所述第二电感连接在所述交流电网与所述第二竖桥之间，所述续流开关组并联在所述第一电感及所述第二电感之间。
  9. 根据权利要求8所述的逆变电路，其特征在于，所述续流开关组包括串联的第五开关管和第六开关管。
  10. 一种逆变器，其特征在于，包括控制单元和逆变功率单元，所述控制单元用于控 制所述逆变功率单元的工作，其中，所述逆变功率单元包括如权利要求1-9任一所述的逆变电路。
  11. 一种光伏发电系统，其特征在于，包括：
    光伏板、逆变器和交流电网；
    所述光伏板与所述逆变器相连，所述逆变器与所述交流电网相连；
    所述光伏板用于将光能转化为直流电；
    所述逆变器包括上述权利要求1-9任一所述的逆变电路，用于将所述直流电转换为交流电；
    所述交流电网用于传输所述交流电。
PCT/CN2020/091982 2019-05-31 2020-05-25 一种逆变电路、逆变器及光伏发电系统 Ceased WO2020238824A1 (zh)

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