WO2021017719A1 - 一种信息处理方法、物理机和pcie设备 - Google Patents

一种信息处理方法、物理机和pcie设备 Download PDF

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Publication number
WO2021017719A1
WO2021017719A1 PCT/CN2020/098722 CN2020098722W WO2021017719A1 WO 2021017719 A1 WO2021017719 A1 WO 2021017719A1 CN 2020098722 W CN2020098722 W CN 2020098722W WO 2021017719 A1 WO2021017719 A1 WO 2021017719A1
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WIPO (PCT)
Prior art keywords
driver
pcie device
dma
dirty
dma address
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Ceased
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PCT/CN2020/098722
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English (en)
French (fr)
Inventor
欧阳长春
曹水
项子豪
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to EP20846569.0A priority Critical patent/EP3992790B1/en
Publication of WO2021017719A1 publication Critical patent/WO2021017719A1/zh
Priority to US17/205,090 priority patent/US12117947B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G06F2009/4557—Distribution of virtual machine instances; Migration and load balancing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G06F2009/45583—Memory management, e.g. access or allocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Definitions

  • This application relates to the computer field, in particular to an information processing method, a physical machine and a PCIE device.
  • a virtual machine manager with the function of managing virtual machines is installed on a physical machine, and VMM manages one or more virtual machine VMs, and operations can be run on each VM System (operating system, OS) and various applications.
  • the hardware of a physical machine mainly includes: some hardware related to running virtual machines, such as central processing unit (CPU), memory, hard disk, etc., and some are not directly used to run virtual machines, but are used to perform some specific services , And hardware with relatively independent functions, such as peripheral component interconnection express (PCIE) devices (such as network card adapters, graphics cards, etc.) in physical machines.
  • PCIE peripheral component interconnection express
  • Single-root I/O virtualization is a kind of input/output (I/O) virtualization technology, which can virtualize multiple devices on a PCIE device.
  • a virtual PCIE adapter is called a virtual function (VF).
  • the VF can perform DMA (direct memory access) operations with the physical host memory to realize data interaction between the PCIE device and the VM.
  • DMA direct memory access
  • the virtual machine hot migration can be realized through the host.
  • the virtual machine hot migration technology refers to the transfer of the virtual machine from one host to another through the hot migration.
  • the hot migration process can include host pairing. The standard dirty of the data to be migrated, and the migration of the dirty data.
  • the VF can directly perform DMA operations with the physical machine memory, that is, the VF can directly transfer data to the physical machine memory corresponding to the DMA address.
  • this part of the data also needs to be migrated.
  • the host cannot obtain the DMA address of the physical machine memory where the data to be migrated is located, and during the hot migration process, the host cannot realize the dirty and hot of this part of the data. migrate.
  • the PCIE device records the DMA address and sends the DMA address to the PF driver in the host, so that the host can obtain the DMA address, and perform marking and hot migration according to the DMA address.
  • this application provides an information processing method that is applied to a physical machine, the physical machine is provided with a fast peripheral component interconnection standard PCIE device, and the physical machine is running including the first virtual machine VM.
  • At least one virtual machine VM, a physical function PF driver for managing the PCIE device, and a virtual machine manager VMM the method includes: during the hot migration process of the first VM, the PCIE device receives and sends to all The message of the first VM; the PCIE device determines the direct memory access DMA address corresponding to the first VM based on the message; the PCIE device transfers the DMA address to the PF driver; the PF The driver generates a dirty bit used to indicate the DMA address; the PF driver writes the dirty bit into a dirty bitmap so that the VMM can obtain it, and the dirty bitmap is used to store the first VM The address of the data to be migrated during the hot migration process.
  • the PCIE device records the DMA address, and sends the DMA address to the PF driver in the host, so that the host can obtain the DMA address, and perform dirty and hot migration according to the DMA address.
  • the DMA address corresponding to the virtual machine VM can It changes in real time (that is, the DMA address that the VM has permission to use may change dynamically), and the VMM needs to obtain the DMA address corresponding to the virtual machine VM in real time, which will cause the CPU overhead of the physical machine to be excessive.
  • the PCIE device can know the change of the DMA address corresponding to the VM (the VF driver corresponding to the VM will send the DMA address corresponding to the VM to the PCIE device). Therefore, the PCIE device can directly send the DMA address to the host, reducing the CPU of the physical machine Overhead.
  • the PCIE device transferring the DMA address to the PF driver includes: the PCIE device writes the DMA address into the buffer of the receiving queue of the PF driver buffer; The PCIE device sends a first interrupt to the PF driver, and the first interrupt is used to instruct the PF driver to read the buffer of the receive queue.
  • the PCIE device transferring the DMA address to the PF driver includes: the PCIE device writes the DMA address into a mailbox; The PF driver sends a second interrupt, and the second interrupt is used to instruct the PF driver to read the mailbox to obtain the DMA address.
  • the corresponding DMA address needs to be occupied by the VMM.
  • the PCIE device sends the DMA address to the PF driver of the host through the receiving queue and the mailbox. Because the size of the buffer of the receiving queue is controllable, and the cache buffer of the mailbox The size is controllable, and the memory occupied by the buffers on the receiving queue is discrete, and there is no need to occupy a large block of continuous memory in the CPU.
  • the determination by the PCIE device of the direct memory access DMA address corresponding to the first VM based on the message includes: the PCIE device from the first VM based on the message N DMA addresses are obtained from L DMA addresses corresponding to a VM, where the L DMA addresses and the N DMA addresses belong to the same group of memory pages, and N is less than L; correspondingly, the PCIE device
  • the transferring the DMA address to the PF driver includes: the PCIE device transferring the N DMA addresses to the PF driver.
  • the data processing unit after determining the L DMA addresses corresponding to the message, the data processing unit will filter the L DMA addresses. Under the premise that each memory page corresponds to at least one DMA address, only N DMA addresses are reserved. address. That is, it is guaranteed that the filtered DMA address can also indicate all memory pages corresponding to the DMA address before filtering, which saves resource occupation.
  • the PCIE device further includes at least one virtual function VF, and in the hot migration of the first VM, the first VM and the first of the at least one VF Corresponding to VF, the method further includes: the PF driver sends the function identifier of the first virtual function VF to the PCIE device; the PCIE device determines the first VM according to the function identifier of the first VF. In this way, the PCIE device can learn that the first VM needs to perform hot migration, and then after receiving the message sent to the first VM, it sends the DMA address corresponding to the first VM to the PF driver in the host.
  • the dirty bitmap includes a first dirty bitmap and a second dirty bitmap, the first dirty bitmap is writable, and the second dirty bitmap is readable,
  • the PF driver writing the dirty bit bit into the dirty bitmap includes: the PF driver writing the dirty bit bit into the first dirty bitmap; the PF driver writing the first dirty bitmap It is changed to be readable, so that the VMM obtains the written dirty bit from the first dirty bitmap.
  • the method further includes: the PF driver changes the second dirty bitmap to Writable so that the PF drive can write information. In this way, the maximum concurrency of read and write access to dirty bitmaps can be ensured through the mechanism of reading and writing double dirty bitmaps.
  • the method further includes: the PF driver clears the first dirty bit. Dirty bitmap.
  • this application provides an information processing method applied to a PCIE device, the PCIE device is set in a physical machine, and the physical machine runs a host and at least one virtual machine VM including a first virtual machine VM.
  • the host includes a physical function PF driver for managing the PCIE device, and the method includes: receiving a message sent to the first VM during the hot migration process of the first VM; The message determines the direct memory access DMA address corresponding to the first VM; the DMA address is passed to the PF driver for processing by the host.
  • the transferring the DMA address to the PF driver includes: writing the DMA address into the buffer buffer of the receiving queue of the PF driver; and sending to the PF driver The first interrupt is used to instruct the PF driver to receive the buffer of the receiving queue.
  • the transferring the DMA address to the PF driver includes:
  • the determining the direct memory access DMA address corresponding to the first VM based on the message includes:
  • N DMA addresses are obtained from the L DMA addresses corresponding to the first VM based on the message, where the L DMA addresses and the N DMA addresses belong to the same group of memory pages, and N is less than L;
  • the transferring the DMA address to the PF driver includes:
  • the N DMA addresses are transferred to the PF driver.
  • the PCIE device further includes at least one virtual function VF, and in the hot migration of the first VM, the first VM and the first of the at least one VF Corresponding to VF, the method further includes:
  • the PCIE device determines the first VM according to the function identifier of the first VF.
  • the present application provides an information processing method, the method is applied to a PF driver, the PF driver runs on a physical machine, and the physical machine is provided with a standard PCIE device for quick peripheral component interconnection, and the physical machine At least one virtual machine VM including the first virtual machine VM and a virtual machine manager VMM are also running, and the method includes:
  • the dirty bit is written into a dirty bitmap so that the VMM can obtain the dirty bitmap, and the dirty bitmap is used to store the address of the data that needs to be migrated in the hot migration process of the first VM.
  • the receiving the DMA address transferred by the PCIE device includes:
  • the buffer of the receiving queue is read according to the first interrupt, and the DMA address is written in the buffer.
  • the PF driver receiving the DMA address transferred by the PCIE device includes:
  • the mailbox is read according to the second interrupt to obtain the DMA address, and the DMA address is written in the mailbox.
  • the PCIE device further includes at least one virtual function VF, and in the hot migration of the first VM, the first VM and the first of the at least one VF Corresponding to VF, the method further includes:
  • the dirty bitmap includes a first dirty bitmap and a second dirty bitmap, the first dirty bitmap is writable, and the second dirty bitmap is readable, Writing the dirty bits into the dirty bitmap includes:
  • the first dirty bitmap is changed to be readable, so that the VMM obtains the written dirty bit from the first dirty bitmap.
  • the method further includes: changing the second dirty bitmap to be writable in order to write information.
  • the method further includes:
  • the present application provides a physical machine that is provided with a PCIE device that is a standard PCIE device for quick peripheral component interconnection. At least one virtual machine VM including the first virtual machine VM is running in the physical machine. Manage the physical function PF driver of the PCIE device and the virtual machine manager VMM, where,
  • the PCIE device is configured to receive a message sent to the first VM, determine the direct memory access DMA address corresponding to the first VM based on the message, and set The DMA address is transferred to the PF driver;
  • the PF driver is used to generate a dirty bit used to indicate the DMA address; write the dirty bit to a dirty bitmap so that the VMM can obtain it, and the dirty bitmap is used to save the first VM
  • the hot migration process requires the address of the data to be migrated.
  • the PCIE device is specifically used for:
  • the DMA address is written into the buffer buffer of the receive queue of the PF driver, and a first interrupt is sent to the PF driver, where the first interrupt is used to instruct the PF driver to read the buffer of the receive queue.
  • the PCIE device is specifically used for:
  • the DMA address is written into a mailbox, and a second interrupt is sent to the PF driver.
  • the second interrupt is used to instruct the PF driver to read the mailbox to obtain the DMA address.
  • the PCIE device is specifically used for:
  • N DMA addresses are obtained from the L DMA addresses corresponding to the first VM based on the message, where the L DMA addresses and the N DMA addresses belong to the same group of memory pages, and N is less than L;
  • the N DMA addresses are transferred to the PF driver.
  • the PCIE device further includes at least one virtual function VF, and in the hot migration of the first VM, the first VM and the first of the at least one VF Corresponding to VF, the PF driver is further used to: send the function identifier of the first virtual function VF to the PCIE device;
  • the PCIE device is further configured to: determine the first VM according to the function identifier of the first VF.
  • the dirty bitmap includes a first dirty bitmap and a second dirty bitmap, the first dirty bitmap is writable, and the second dirty bitmap is readable,
  • the PF driver is specifically used for:
  • the first dirty bitmap is changed to be readable, so that the VMM obtains the written dirty bit from the first dirty bitmap.
  • the PF driver is further used to: change the second dirty bitmap to be writable, so that the PF driver can write information.
  • the PF driver is further used to: clear the first dirty bitmap.
  • the present application provides a PCIE device that is a standard PCIE device for quick peripheral component interconnection.
  • the PCIE device is set in a physical machine, and the physical machine runs a host and at least one virtual machine VM including a first virtual machine VM.
  • the host includes a physical function PF driver for managing the PCIE device, and the PCIE device includes:
  • a transceiver module configured to receive a message sent to the first VM during the hot migration process of the first VM
  • a processing module configured to determine a direct memory access DMA address corresponding to the first VM based on the message
  • the transceiver module is also used to transfer the DMA address to the PF driver for processing by the host.
  • the transceiver module is specifically used for:
  • the transceiver module is specifically used for:
  • the processing module is further configured to obtain N DMA addresses from the L DMA addresses corresponding to the first VM based on the message, where the L The DMA address and the N DMA addresses belong to the same group of memory pages, and N is less than L;
  • the transceiver module is specifically used for:
  • the N DMA addresses are transferred to the PF driver.
  • the PCIE device further includes at least one virtual function VF.
  • the transceiver module is further configured to receive the function identifier of the first VF sent by the PF driver;
  • the processing module is further configured to determine the first VM according to the function identifier of the first VF.
  • the present application provides a host, the host runs on a physical machine, the physical machine is provided with a fast peripheral component interconnection standard PCIE device, and the physical machine also runs the first virtual machine VM including the At least one virtual machine VM and virtual machine manager VMM, including:
  • a transceiver module configured to receive a DMA address transferred by the PCIE device during the hot migration process of the first VM, where the DMA address corresponds to the first VM, and generate a dirty bit for indicating the DMA address Bit
  • the processing module is configured to write the dirty bits into a dirty bitmap so that the VMM can obtain the dirty bitmap, and the dirty bitmap is used to store the address of the data that needs to be migrated during the hot migration process of the first VM.
  • the transceiver module is specifically configured to receive the first interrupt sent by the PCIE device, and read the buffer of the receiving queue according to the first interrupt, and the buffer writes some The DMA address.
  • the transceiver module is specifically configured to receive a second interrupt sent by the PCIE device, and read a mailbox according to the second interrupt to obtain the DMA address, and the mailbox The DMA address is written.
  • the PCIE device further includes at least one virtual function VF, and in the hot migration of the first VM, the first VM and the first of the at least one VF Corresponding to the VF, the transceiver module is further configured to send the function identifier of the first virtual function VF to the PCIE device, so that the PCIE device determines the first VM according to the function identifier of the first VF.
  • the dirty bitmap includes a first dirty bitmap and a second dirty bitmap, the first dirty bitmap is writable, and the second dirty bitmap is readable,
  • the processing module is also used for:
  • the dirty bit is written into the first dirty bitmap, and the first dirty bitmap is changed to be readable, so that the VMM obtains the written dirty bit from the first dirty bitmap Bits.
  • the processing module is further configured to change the second dirty bitmap to be writable so as to write information.
  • the processing module is further configured to clear the first dirty bitmap.
  • this application provides a communication device, including: a processor, a memory, and a PCIE device;
  • the processor is configured to run a PF driver based on the code in the memory
  • this application provides a communication device, including: a processor and a memory;
  • the processor and the memory are electrically connected;
  • the processor is configured to execute the method according to any one of the foregoing third aspects based on the code in the memory.
  • the present application provides an information processing method, including: during the hot migration process of the virtual machine to be migrated, a PCIE device receives a message corresponding to the VF to be migrated, where the VF to be migrated is a VF among the multiple VFs
  • the PCIE device determines the direct memory access DMA address according to the message; and the PCIE device sends the DMA address to the PF driver.
  • the PCIE device records the DMA address, and sends the DMA address to the PF driver in the host, so that the host can obtain the DMA address, and perform dirty and hot migration according to the DMA address.
  • the PCIE device records the DMA address, and sends the DMA address to the PF driver in the host, so that the host can obtain the DMA address, and perform dirty and hot migration according to the DMA address.
  • FIG. 1 is a schematic diagram of an application architecture provided by an embodiment of the present invention.
  • Figure 2 is a schematic diagram of a migration architecture for virtual machine hot migration
  • FIG. 3a is a schematic flowchart of an information processing method provided by an embodiment of this application.
  • FIG. 3b is a schematic diagram of a flow of DMA address transfer according to an embodiment of the application.
  • FIG. 5a is a schematic diagram of reading and writing a dirty bitmap provided in an embodiment of the application.
  • FIG. 5b is a schematic diagram of reading and writing a dirty bitmap provided in an embodiment of the application.
  • FIG. 6 is a schematic structural diagram of a physical machine provided by an embodiment of this application.
  • FIG. 7 is a schematic structural diagram of a PCIE device with a fast peripheral component interconnection standard provided by an embodiment of the application;
  • FIG. 8 is a schematic structural diagram of a host provided by an embodiment of this application.
  • FIG. 9 is a schematic diagram of an embodiment of a physical machine in an embodiment of this application.
  • Fig. 1 is a schematic diagram of an application architecture provided by an embodiment of the present invention.
  • the embodiment of the present invention can be applied to a physical machine 100, where the physical machine 100 can run a host 110, a peripheral component interconnection express (PCIE) device 120, and at least one virtual machine (VM) (That is, the virtual machines VM1 ⁇ VM3 shown in Figure 1.
  • PCIE peripheral component interconnection express
  • VM virtual machine
  • the number of virtual machines is not a limit to the embodiment of this solution. In actual applications, it can be adjusted at any time according to the needs. This is only listed here for convenience of explanation. Three virtual machines).
  • the host 110 runs a VMM 111, and the VMM 111 can manage one or more virtual machine VMs, and each virtual machine VM can run an operating system and various applications running on the operating system. It should be understood that, in some scenarios, the virtual machine manager VMM in this embodiment may implement part or all of the functions of a virtual machine monitor (VMM).
  • VMM virtual machine monitor
  • the virtual machine manager VMM can be implemented by a custom logic chip, which is responsible for the management and control of the virtual machine, including the completion of the monitoring and modification of the attributes and status of the virtual machine, the creation, migration, and power-on of the virtual machine And power off operations.
  • the host 110 also includes hardware related to running a virtual machine VM, such as a central processing unit (CPU) and at least one computer-readable storage medium memory (hard disk, memory, etc.).
  • a virtual machine VM such as a central processing unit (CPU) and at least one computer-readable storage medium memory (hard disk, memory, etc.).
  • the host 110 may also include a communication unit, an input unit, a display unit, and so on.
  • the host 110 may be connected to a PCIE device 120, which is a hardware device that supports the single-root input and output virtualization SR-IOV standard.
  • the PCIE device 120 includes at least one physical function (PF) and at least one virtual function VF.
  • FIG. 1 only shows one PF and three VFs (VF1, VF2, and VF3).
  • both PF and VF are configured with a unique function number function id.
  • Each PF or VF corresponds to a virtual machine VM, and the corresponding relationship between the function id of the PF or VF and the virtual machine VM may be stored in the management unit 121 and the data processing unit 122 of the PCIE device 120.
  • the data processing unit 122 may specifically be an L2vSwitch virtual switch.
  • the host 110 also runs a PF driver that manages the PCIE device 120 (the PF driver can directly access all resources of the PF, and is responsible for configuring and managing all VFs).
  • Each virtual machine VM runs a VF driver to manage its corresponding VF .
  • the binding relationship between each virtual machine and VF is not unchangeable. In this embodiment, it is only to illustrate the one-to-one correspondence between each virtual machine VM and each VF, for example, VM1 corresponds to VF1.
  • Each virtual machine VM can directly perform network I/O data interaction with its corresponding one or more VFs based on DMA operations, without VMM, which not only reduces the I/O performance overhead in VMM, but also ensures the performance of each VM I/O throughput efficiency.
  • the virtual machine VM sends and receives data messages from the VF, it can be combined with the input/output memory management unit (IOMMU) technology provided by the CPU to achieve complete independence of sending and receiving, and the data messages are written into the DMA in the VF During the process of the physical machine memory corresponding to the address, the VMM 111 cannot perceive it.
  • IOMMU input/output memory management unit
  • the VF driver of each virtual machine VM can obtain the DMA address that the virtual machine VM has permission to use, where the DMA address is the memory address of the memory of the physical machine.
  • the VF driver can send the DMA address to the data processing unit 122 through the corresponding VF. Therefore, the data processing unit 122 can save the correspondence between each virtual machine VM and the DMA address.
  • the correspondence between each virtual machine VM and the DMA address The relationship can be understood as the DMA address that each VM has permission to use.
  • the VF can write the message into the memory of the physical machine corresponding to the DMA address that the VM has permission to use.
  • the VF driver of the virtual machine VM1 is connected to VF1
  • the VF driver of the virtual machine VM1 obtains the DMA address that the virtual machine VM1 has permission to use, and transfers the DMA address that the virtual machine VM1 has permission to use to the data processing unit 122 through VF1, correspondingly Yes
  • the data processing unit 122 may save the DMA address that the virtual machine VM1 has permission to use.
  • the data processing unit 122 also maintains the corresponding relationship between each VF and VM.
  • the data processing unit 122 in the PCIE device 120 receives a message (the source of the message can be the external network or the VM in the physical machine), it can be determined according to the destination address of the message to be sent to VM, and based on the correspondence between VF and VM, determine the VF corresponding to the VM, so as to transfer the message to the corresponding VF, and then the VF can initiate a DMA operation based on the correspondence between the VM and the DMA address, and write the message In the memory of the physical machine corresponding to the DMA address that the VM has the authority to use, correspondingly, the VM can obtain the message from the memory of the physical machine corresponding to the DMA address that the VM has the authority to use.
  • FIG. 2 is a schematic diagram of a migration architecture for virtual machine hot migration.
  • the running state of the virtual machine 201 can be migrated to other virtual machines 202 on the same physical machine or Migrate to virtual machines 211, 212, and 213 on other physical machines.
  • the physical machine can be a server that provides various cloud services.
  • the server After the server is virtualized, it can easily realize the hot migration of the virtual machine VM, and the key of the virtual machine VM hot migration is the memory migration.
  • the migration of the virtual machine VM memory can be divided into three stages:
  • Iterative pre-copy stage After the virtual machine VM migration process is started, it is still running on the source server, and the virtual machine VM business is not interrupted. First, the host copies all the memory of the virtual machine VM to the destination server, and then the host copies the virtual machine The memory data changed in the VM is marked dirty, and the dirty memory data is copied to the destination server repeatedly. After iterating until the memory that needs to be copied is less than a certain threshold, it enters the shutdown copy phase.
  • steps implemented by the host may be implemented by the VMM in the host.
  • Recovery phase the destination virtual machine VM completes the recovery processing before running, starts the destination virtual machine VM, and the entire migration process is completed.
  • the VF can directly perform DMA operations with the physical machine memory, that is, the VF can directly transfer data to the physical machine memory corresponding to the DMA address.
  • this Part of the data also needs to be migrated.
  • the host cannot obtain the DMA address of the physical machine memory where the data to be migrated is located, and during the hot migration process, the host cannot achieve the dirty and hot marking of this part of the data. migrate.
  • this application provides an information processing method, which is applied to a physical machine, the physical machine is provided with a fast peripheral component interconnection standard PCIE device, and the physical machine runs including a first virtual At least one virtual machine VM including the machine VM, the physical function PF driver used to manage the PCIE device, and the virtual machine manager VMM, refer to FIG. 3a, which is a flow of an information processing method provided by an embodiment of the application Schematic. As shown in Figure 3, the information processing method provided in this embodiment includes:
  • the PCIE device receives a packet sent to the first VM.
  • the VF driver can send the DMA address that the corresponding virtual machine VM has permission to use to the PCIE device (in other words, the DMA address corresponding to the VM).
  • the data processing unit in the PCIE device can receive the DMA address sent by the above-mentioned VF.
  • the PCIE device can save the correspondence between each virtual machine VM and the DMA address. Since the PCIE device also saves the correspondence between the VF and each virtual machine VM, the PCIE device can save the correspondence between the VF and the DMA address. Correspondence.
  • the PCIE device may maintain multiple function tables, each function table corresponds to a VF, and the function table records the correspondence between the VF, the virtual machine VM, and the DMA address.
  • both the management unit and the data processing unit of the PCIE device may maintain the above function table.
  • the PF driver of the host may initialize the communication channel with the management unit in the PCIE device, that is, apply for channel resources for communication between the PF driver and the management unit.
  • the PF driver can apply for memory resources of multiple receive queues (RQ), and serve as a data transmission link with the data processing unit in the PCIE device.
  • the receiving queue RQ may include multiple elements, and each element may correspond to a buffer.
  • the PF driver may pre-configure the number of elements included in the receiving queue RQ and the size of the buffer corresponding to each element.
  • each of the foregoing multiple receiving queues RQ may uniquely correspond to a queue identifier.
  • the PF driver may deliver the function id of the VF to be migrated and the queue id of a receiving queue RQ to the management unit.
  • the management unit may determine the corresponding VF according to the received VF identifier, and determine that the VM corresponding to the VF is the VM that requires hot migration (the first VM), and mark the dirty state of the memory of the VF as the dirty state of memory required, And, bind the VF with the queue identifier of the received receiving queue RQ.
  • the management unit may determine the corresponding function table according to the function id of the VF, mark a field in the function table as requiring memory mark dirty, and save the corresponding receiving queue RQ queue in the function table Logo.
  • the function id of the VF can be used to distinguish different VFs.
  • the function id can be composed of a bus number and a device number, which is not limited in this application.
  • the PF driver can communicate with the PCIE device through the doorbell and mailbox mechanism. Specifically, the PF driver can apply for the mailbox cache and doorbell register for the PCIE device to implement the PF driver and the PCIE device.
  • the communication between the PCIE devices is to configure a mailbox cache and a doorbell register in the PF to implement a mechanism similar to "doorbell". If the PCIE device has a message to send, then the data is directly sent to the mailbox buffer in PF, and the second interrupt is sent to the PF driver. After the PF driver receives the second interrupt, it can read the mailbox buffer corresponding to the second interrupt .
  • the PCIE device may receive the function identifier of the first virtual function VF sent by the host, and determine the first VM according to the function identifier of the first VF.
  • the PCIE device may receive a message sent to the first VM, and the message may be sent by an external network, or sent by a VM other than the first VM on the physical machine.
  • the PCIE device determines a direct memory access DMA address corresponding to the first VM based on the message.
  • the data processing unit in the PCIE device may determine that the destination VM to be sent is the first VM according to the destination address in the message, and based on the VM and The corresponding relationship of the VF is to determine the VF corresponding to the first VM, and then read the status flag of the VF. Specifically, the corresponding field indicating the dirty status of the VF memory can be found in the function table corresponding to the VF. If the VF is not in the memory mark dirty state, the data processing unit in the PCIE device can normally pass the message to the receiving queue corresponding to the VF.
  • the data processing unit in the PCIE device reads the status flag of the VF and determines that the VF is in the dirty state of the memory, it obtains the corresponding DMA address from the function table.
  • the data processing unit may obtain N DMA addresses from the L DMA addresses corresponding to the first VM based on the message, where the L DMA addresses and the N DMA addresses belong to the same group of memory pages, and N is less than L.
  • the data processing unit may determine in the function table that the first VM corresponds to L DMA addresses, and L is a positive integer greater than or equal to 2.
  • the virtual machine VM reads and writes memory in units of memory pages.
  • the same memory page can correspond to multiple DMA addresses, and one DMA address corresponds to one memory page.
  • the L DMA addresses determined by the data processing unit may be DMA addresses on N memory pages, where N is a positive integer less than L.
  • the data processing unit may determine N DMA addresses corresponding to N memory pages, where each memory page of the N memory pages corresponds to at least one DMA address among the N DMA addresses.
  • the data processing unit determines that the DMA address corresponding to the message is ⁇ address 1, address 2, address 3, address 4, address 5, address 6, address 7, address 8, address 9, address 10, address 11, address 12, Address 13, address 14, address 15 ⁇ , where,
  • ⁇ Address 1, Address 2, Address 3 ⁇ is the DMA address on memory page 1;
  • Address 5 ⁇ is the DMA address on memory page 2;
  • ⁇ Address 6, Address 7, Address 8 ⁇ is the DMA address on memory page 3;
  • the data processing unit may determine N DMA addresses corresponding to the 4 memory pages, where each memory page of the 4 memory pages corresponds to at least one DMA address among the N DMA addresses.
  • the data processing unit can determine the 4 DMA addresses corresponding to 4 memory pages: ⁇ address 1, address 4, address 6, address 9 ⁇ , where memory page 1 corresponds to address 1, memory page 2 corresponds to address 4, memory Page 3 corresponds to address 6, and memory page 4 corresponds to address 9.
  • the number of DMA addresses corresponding to a memory page may be greater than 1.
  • the data processing unit may determine 5 DMA addresses corresponding to 4 memory pages: ⁇ address 1, address 2, address 4, address 6 , Address 9 ⁇ , where memory page 1 corresponds to address 1 and address 2, memory page 2 corresponds to address 4, memory page 3 corresponds to address 6, and memory page 4 corresponds to address 9.
  • the data processing unit after determining the L DMA addresses corresponding to the message, the data processing unit will filter the L DMA addresses. Under the premise that each memory page corresponds to at least one DMA address, only N DMA addresses are reserved. address. That is, it is guaranteed that the filtered DMA address can also indicate all memory pages corresponding to the DMA address before filtering, which saves resources.
  • the PCIE device transfers the DMA address to the PF driver.
  • the data processing unit can find the identifier of the receiving queue RQ bound to the VF in the function table corresponding to the VF, and write the DMA address into a buffer buffer of the receiving queue corresponding to the identifier of the receiving queue RQ in.
  • the data processing unit may determine multiple DMA addresses corresponding to the message.
  • a memory page may correspond to multiple DMA addresses, due to the memory hot migration In the process, migration is performed in units of memory pages. Therefore, if the data processing unit determines that there are multiple DMA addresses belonging to the same memory page in the multiple DMAs corresponding to the message, it can only send to the PF driver A DMA address among multiple DMA addresses in the same memory page.
  • the data processing unit determines that there are multiple DMA addresses in the same memory page in the multiple DMAs corresponding to the message, it can only write one of the multiple DMA addresses belonging to the same memory page into the DMA address
  • the receiving queue identifier corresponds to a buffer of the receiving queue RQ.
  • the data processing unit may send a first interrupt to the PF driver, and the first interrupt is used to instruct the PF driver to receive the buffer.
  • the data processing unit may send a first interrupt to the PF driver when determining that at least one of the following preset conditions is satisfied, where the preset conditions may include:
  • the buffer is full of DMA addresses.
  • the timeout period is up;
  • the VF to be migrated is not in the memory mark dirty state.
  • the data processing unit can write the DMA address in a buffer in the receiving queue RQ, and the data processing unit can determine in real time whether the determined buffer has been filled with the DMA address, and after judging that the buffer has been written After the DMA address is full, send a first interrupt to the PF driver to instruct the PF driver to receive the buffer of the receiving queue.
  • the data processing unit may determine a buffer among multiple buffer buffers in the receiving queue and write the DMA address.
  • the data processing unit may start timing when the first write operation is performed, and when it reaches the preset At time, send a first interrupt to the PF driver to instruct the PF driver to receive the buffer of the receiving queue.
  • the data processing unit can monitor the memory mark dirty state of the VF to be migrated in the function table corresponding to the VF to be migrated in real time, and if the memory mark dirty state is that the memory mark dirty state is not required, the first interrupt is sent to the PF driver To instruct the PF driver to receive the buffer of the receiving queue.
  • the data processing unit may determine a buffer among multiple buffer buffers in the receiving queue and write the DMA address.
  • the data processing unit may determine in real time whether the determined buffer has been filled with the DMA address, and at the same time, Start timing when the first write operation is performed, and monitor the dirty state of the memory of the VF to be migrated in the function table corresponding to the VF to be migrated in real time.
  • the data processing unit may send the first interrupt to the PF driver after determining that the buffer is full of the DMA address; or, the data processing unit may send the first interrupt to the PF driver when the buffer is not full of the DMA address, but when the preset time is reached , Send the first interrupt to the PF driver; or, the data processing unit can send the first interrupt to the PF driver when the buffer is not full with the DMA address, but it is determined that the VF to be migrated is not in the memory mark dirty state; or, the data processing unit can When the buffer is not full of the DMA address and the preset time is not reached, but it is determined that the VF to be migrated is not in the memory mark dirty state, the first interrupt is sent to the PF driver. Wherein, the first interrupt may instruct the PF driver to receive the buffer of the receiving queue.
  • the data processing unit may determine multiple DMA addresses corresponding to the message.
  • a memory page may correspond to multiple DMA addresses, due to the memory hot migration In the process, migration is performed in units of memory pages. Therefore, if the data processing unit determines that there are multiple DMA addresses belonging to the same memory page in the multiple DMAs corresponding to the message, it can only send to the PF driver A DMA address among multiple DMA addresses in the same memory page. That is, if the data processing unit determines that there are multiple DMA addresses in the same memory page in the multiple DMAs corresponding to the message, it can only write one of the multiple DMA addresses belonging to the same memory page into the DMA address In the mailbox.
  • the data processing unit may send a second interrupt to the PF driver.
  • the second interrupt is used to instruct the PF driver to read the mailbox to obtain the DMA address.
  • the data processing unit may send a second interrupt to the PF driver when determining that at least one of the following preset conditions is satisfied, where the preset conditions may include:
  • the mailbox is full of DMA addresses.
  • the timeout period is up;
  • the VF to be migrated is not in the memory mark dirty state.
  • the data processing unit can write the DMA address in the mailbox, and the data processing unit can determine in real time whether the mailbox has been filled with the DMA address, and after judging that the mailbox is filled with the DMA address, send it to the PF
  • the driver sends a second interrupt to instruct the PF driver to read the mailbox to obtain the DMA address.
  • the data processing unit can write the DMA address in the mailbox, the data processing unit can start timing when the first write operation is performed, and when the preset time is reached, send a second interrupt to the PF driver, To instruct the PF driver to read the mailbox to obtain the DMA address.
  • the data processing unit can monitor the memory status of the VF to be migrated in the function table corresponding to the VF to be migrated in real time, and if the memory status is that the memory status is not required to be dirty, it sends a second interrupt to the PF driver To instruct the PF driver to read the mailbox to obtain the DMA address.
  • the data processing unit can write a DMA address in the mailbox, and the data processing unit can determine in real time whether the mailbox has been filled with the DMA address, and at the same time, start timing when the first write operation is performed, and Monitor the dirty state of the memory of the VF to be migrated in the function table corresponding to the VF to be migrated in real time.
  • the data processing unit may send a second interrupt to the PF driver after judging that the mailbox is full of the DMA address; or, the data processing unit may not write the DMA address in the mailbox, but when it reaches the preset At time, send a second interrupt to the PF driver; or, the data processing unit can send a second interrupt to the PF driver when the mailbox is not full of DMA addresses, but it is determined that the VF to be migrated is not in the memory mark dirty state; or, data The processing unit may send a second interrupt to the PF driver when the mailbox is not filled with the DMA address and the preset time is not reached, but it is determined that the VF to be migrated is not in the memory mark dirty state. Wherein, the second interrupt may instruct the PF driver to read the mailbox to obtain the DMA address.
  • the PF driver generates a dirty bit used to indicate the DMA address.
  • the PF driver may generate dirty bits for indicating the DMA address.
  • the PF driver writes the dirty bits into a dirty bitmap so that the VMM can obtain the dirty bitmap, where the dirty bitmap is used to store the address of the data that needs to be migrated during the hot migration process of the first VM.
  • the dirty bit can be written into the dirty bitmap so that the VMM can obtain it, where the dirty bitmap is used for Save the address of the data to be migrated during the hot migration process of the first VM.
  • the VMM can obtain the dirty bitmap, and perform memory hot migration based on the dirty bitmap.
  • the PF driver of the host can read the mailbox and obtain the DMA address written in the mailbox, and then the PF driver can convert the DMA address into dirty bits and write them into the dirty bitmap ,
  • the VMM of the physical machine can obtain the dirty bitmap, and perform memory hot migration according to the dirty bitmap.
  • VMM performs memory hot migration according to the dirty bits in the dirty bitmap can refer to the implementation in the prior art, which will not be repeated here.
  • the PCIE device records the DMA address and sends the DMA address to the PF driver in the host, so that the host can obtain the DMA address, and perform dirty and hot migration according to the DMA address.
  • the DMA address corresponding to the virtual machine VM can It changes in real time (that is, the DMA address that the VM has permission to use may change dynamically), and the VMM needs to obtain the DMA address corresponding to the virtual machine VM in real time, which will cause the CPU overhead of the physical machine to be excessive.
  • the PCIE device can know the change of the DMA address corresponding to the VM (the VF driver corresponding to the VM will send the DMA address corresponding to the VM to the PCIE device). Therefore, the PCIE device can directly send the DMA address to the host, reducing the CPU of the physical machine Overhead.
  • VMM occupies a large block of continuous memory in the CPU.
  • the PCIE device sends the DMA address to the PF driver of the host through the receiving queue and the mailbox. Because the size of the buffer in the receiving queue is controllable, and the cache of the mailbox The size of the buffer is controllable, and the memory occupied by the buffers on the receiving queue is discrete, and there is no need to occupy a large block of continuous memory in the CPU.
  • Figure 3b is a schematic flow diagram of a DMA address transfer provided by an embodiment of the application.
  • the data processing unit can determine the The VF corresponding to the first VM, and the function table corresponding to the VF, where the function table records the dirty state of the VF as the dirty state required, and the DMA address ⁇ DMA_1, DMA_2, DMA_3 ⁇ corresponding to the first VM and the bound Receiving queue ID: receiving queue 1.
  • the data processing unit can select receive queue 1 from the multiple receive queues corresponding to multiple PF drivers, and write the DMA address ⁇ DMA_1, DMA_2, DMA_3 ⁇ corresponding to the first VM to one of the buffers (buffer1), correspondingly,
  • the PF driver can obtain the DMA address ⁇ DMA_1, DMA_2, DMA_3 ⁇ corresponding to the first VM from the buffer1 in the receiving queue 1.
  • the embodiment of the present application provides an information processing method, including: during the hot migration process of the virtual machine to be migrated, a PCIE device receives a message corresponding to the VF to be migrated, and the VF to be migrated is among the multiple VFs
  • the PCIE device determines the direct memory access DMA address according to the message; and, the PCIE device sends the DMA address to the PF driver.
  • the PCIE device records the DMA address, and sends the DMA address to the PF driver in the host, so that the host can obtain the DMA address, and perform dirty and hot migration according to the DMA address.
  • FIG. 4 is a schematic flowchart of another information processing method provided by an embodiment of this application.
  • the information processing method provided in this embodiment can be applied to a PF driver, which runs on a physical machine, and the physical machine is provided with a quick peripheral component interconnection standard PCIE device, and the physical machine also runs a first virtual machine VM At least one virtual machine VM and a virtual machine manager VMM included therein, the information processing method specifically includes:
  • step 303 For how the PF driver receives the DMA address transferred by the PCIE device, refer to the description of step 303 in the embodiment corresponding to FIG. 3, which is not repeated here.
  • the PF driver generates a dirty bit corresponding to the DMA address.
  • the PF driver writes the dirty bits into a dirty bitmap so that the VMM can obtain the dirty bitmap.
  • the dirty bitmap is used to store the address of the data that needs to be migrated during the hot migration process of the first VM.
  • the dirty bitmap may include a first dirty bitmap and a second dirty bitmap.
  • the PF driver can maintain two dirty bitmaps (the first dirty bitmap and the second dirty bitmap), where the read and write attributes of the first dirty bitmap are writable, and the second dirty bitmap Read and write attributes are readable.
  • the PF driver may write the dirty bit into the first dirty bitmap.
  • Figure 5a is a schematic diagram of reading and writing a dirty bitmap provided in an embodiment of this application.
  • the read and write attributes of the first dirty bitmap are writable.
  • the PF driver obtains the DMA address transferred by the PCIE device, it can generate the dirty bit corresponding to the DMA address, and write the dirty bit into the first dirty bitmap.
  • the VMM may periodically call the state synchronization sync interface to obtain the dirty bit in the dirty bitmap whose read and write attributes are readable.
  • the aforementioned state synchronization sync interface can be configured in advance.
  • the state synchronization sync interface may be an interface function used to implement the receiving function, and the code for receiving state synchronization can be executed by calling the interface function.
  • you can set the interface name for the state synchronization sync interface for example, configure the function name for the function.
  • step 1 the read-write attribute of the first dirty bitmap is writable, and the readable attribute of the second dirty bitmap is readable.
  • the VMM can call the synchronous sync interface. To read the dirty bit in the second dirty bitmap.
  • the PF driver can set the read and write attributes of the first dirty bitmap from writable to readable as shown in step 2 in Figure 5a, and set The read-write attribute of the second dirty bitmap is set from readable to writable, and the second dirty bitmap is cleared.
  • step 3 after the PF driver changes the writable attribute of the first dirty bitmap to readable, the VMM can obtain the dirty bitmap. Bit bit.
  • step 3 after the VMM obtains the dirty bits in the first dirty bitmap, the PF driver can change the read and write attributes of the first dirty bitmap from readable to writable, and change the The read-write attribute changes from writable to readable.
  • the VMM can obtain the dirty bit in the second dirty bitmap.
  • Figure 5a only shows that in step 1, the PF driver writes the first dirty bitmap into the first dirty bitmap.
  • the PF driver can receive the DMA address sent by the PCIE device in real time. , And write the dirty bit corresponding to the generated DMA address into the dirty bitmap whose read/write attribute is writable.
  • Figure 5b is a schematic diagram of reading and writing a dirty bitmap provided in an embodiment of the application.
  • the PF driver can receive the PCIE device in real time. And write the dirty bit corresponding to the generated DMA address into the second dirty bitmap.
  • the PF driver can receive the DMA address sent by the PCIE device in real time, and generate the dirty bit corresponding to the DMA address, and write it into the second dirty bitmap.
  • the PF driver can receive the DMA address sent by the PCIE device in real time, and generate the dirty bit corresponding to the DMA address, and write it into the first dirty bitmap.
  • FIG. 5a and FIG. 5b are only an illustration, and do not constitute a limitation to the embodiment of the present application.
  • the PF driver can apply for two dirty bitmap buffers, one of which has a read-write attribute as a write attribute and the other has a read attribute.
  • the mechanism of reading and writing double dirty bitmaps ensures that the dirty bitmap is Maximum concurrency of read and write access.
  • FIG. 6 is a schematic structural diagram of a physical machine provided by an embodiment of the application.
  • the physical machine 600 is provided with a quick peripheral component interconnection standard PCIE device 601, and the physical machine 600
  • At least one virtual machine VM including the first virtual machine VM604, a physical function PF driver 602 for managing the PCIE device 601, and a virtual machine manager VMM 603 are running in it, where:
  • the PCIE device 601 is configured to receive a message sent to the first VM, and determine the direct memory access DMA address corresponding to the first VM based on the message, Pass the DMA address to the PF driver;
  • the PF driver 602 is used to generate the dirty bit used to indicate the DMA address; write the dirty bit to the dirty bitmap so that the VMM 603 can obtain it, and the dirty bitmap is used to save the first The address of the data to be migrated during the hot migration process of the VM.
  • the PCIE device 601 is specifically used for:
  • the DMA address is written into the buffer buffer of the receive queue of the PF driver, and a first interrupt is sent to the PF driver, where the first interrupt is used to instruct the PF driver to read the buffer of the receive queue.
  • the PCIE device 601 is specifically used for:
  • the DMA address is written into a mailbox, and a second interrupt is sent to the PF driver.
  • the second interrupt is used to instruct the PF driver to read the mailbox to obtain the DMA address.
  • the PCIE device 601 is specifically used for:
  • N DMA addresses are obtained from the L DMA addresses corresponding to the first VM based on the message, where the L DMA addresses and the N DMA addresses belong to the same group of memory pages, and N is less than L;
  • the N DMA addresses are transferred to the PF driver.
  • the PCIE device 601 further includes at least one virtual function VF.
  • the PF driver is further used to: send the function identifier of the first virtual function VF to the PCIE device;
  • the PCIE device 601 is further configured to: determine the first VM according to the function identifier of the first VF.
  • the dirty bitmap includes a first dirty bitmap and a second dirty bitmap, the first dirty bitmap is writable, and the second dirty bitmap is readable, so
  • the PF driver 602 is specifically used for:
  • the first dirty bitmap is changed to be readable, so that the VMM obtains the written dirty bit from the first dirty bitmap.
  • the PF driver 602 is further used to: change the second dirty bitmap to be writable, so that the PF driver can write information.
  • the PF driver 602 is further used to: clear the first dirty bitmap.
  • FIG. 7 is a schematic structural diagram of a standard PCIE device for quick peripheral component interconnection provided by an embodiment of the application.
  • the PCIE device 700 is set in the physical machine, so The physical machine runs with a host and at least one virtual machine VM including a first virtual machine VM, the host includes a physical function PF driver for managing the PCIE device, and the PCIE device includes:
  • the transceiver module 701 is configured to receive a message sent to the first VM during the hot migration process of the first VM;
  • the processing module 702 is configured to determine the direct memory access DMA address corresponding to the first VM based on the message;
  • the transceiver module 701 is also used to transfer the DMA address to the PF driver for processing by the host.
  • the transceiver module 701 is specifically configured to:
  • the transceiver module 701 is specifically configured to:
  • the processing module 702 is further configured to obtain N DMA addresses from the L DMA addresses corresponding to the first VM based on the message, where the L The DMA address and the N DMA addresses belong to the same group of memory pages, and N is less than L;
  • the transceiver module is specifically used for:
  • the N DMA addresses are transferred to the PF driver.
  • the PCIE device 700 further includes at least one virtual function VF.
  • the transceiver module 701 is further configured to receive the function identifier of the first VF sent by the PF driver;
  • the processing module 702 is further configured to determine the first VM according to the function identifier of the first VF.
  • FIG. 8 is a schematic structural diagram of a host provided by an embodiment of the application.
  • the host 800 runs on a physical machine, and the physical machine is provided with a shortcut peripheral component interconnection standard PCIE device, the physical machine also runs at least one virtual machine VM including the first virtual machine VM and a virtual machine manager VMM, and the host 800 includes:
  • the transceiver module 801 is configured to receive the DMA address transferred by the PCIE device during the hot migration process of the first VM, where the DMA address corresponds to the first VM, and generate a dirty address indicating the DMA address. Bit
  • the processing module 802 is configured to write the dirty bits into a dirty bitmap so that the VMM can obtain the dirty bitmap, and the dirty bitmap is used to store the address of the data that needs to be migrated during the hot migration process of the first VM.
  • the transceiver module 801 is specifically configured to receive the first interrupt sent by the PCIE device, read the buffer of the receiving queue according to the first interrupt, and the buffer writes something The DMA address.
  • the transceiver module 801 is specifically configured to receive a second interrupt sent by the PCIE device, and read a mailbox according to the second interrupt to obtain the DMA address.
  • the DMA address is written.
  • the PCIE device 800 further includes at least one virtual function VF.
  • the transceiver module 801 is further configured to send the function identifier of the first virtual function VF to the PCIE device, so that the PCIE device determines the first VM according to the function identifier of the first VF.
  • the dirty bitmap includes a first dirty bitmap and a second dirty bitmap, the first dirty bitmap is writable, and the second dirty bitmap is readable, so
  • the processing module 802 is also used for:
  • the dirty bit is written into the first dirty bitmap, and the first dirty bitmap is changed to be readable, so that the VMM obtains the written dirty bit from the first dirty bitmap Bits.
  • the processing module 802 is further configured to change the second dirty bitmap to be writable, so as to write information.
  • the processing module 802 is further configured to clear the first dirty bitmap.
  • FIG. 9 is a schematic diagram of an embodiment of a physical machine 900 in an embodiment of the present application, and the specific device form thereof is not limited in the embodiment of the present application.
  • the physical machine 900 may have relatively large differences due to different configurations or performances, and may include one or more processors 901 and a memory 902, and the memory 902 stores programs or data.
  • the memory 902 may be volatile storage or non-volatile storage.
  • the processor 901 is one or more central processing units (CPU), and the CPU may be a single-core CPU or a multi-core CPU.
  • the processor 901 may communicate with the memory 902, and execute a series of instructions in the memory 902 on the physical machine 900.
  • the physical machine 900 also includes a PCIE device 903.
  • the physical machine 900 may also include one or more power supplies; one or more input and output interfaces, which can be used to connect a display, a mouse, a keyboard, a touch screen device or a sensor Equipment, etc.
  • the input and output interfaces are optional components, which may or may not exist, and are not limited here.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are merely illustrative, for example, the division of units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or integrated. To another system, or some features can be ignored, or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • each unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the above-mentioned integrated unit can be implemented in the form of hardware or software functional unit.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solution of this application essentially or the part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , Including several instructions to make a computer device (which may be a personal computer, server, or other network device, etc.) execute all or part of the steps of the method described in the embodiment of FIG. 2 of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (read-only memory, ROM), random access memory (random access memory, RAM), magnetic disk or optical disk and other media that can store program code .

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Abstract

本申请实施例公开了一种信息处理方法、物理机和PCIE设备，使得主机可以获取到DMA地址，并根据DMA地址进行标脏和热迁移。其中，信息处理方法包括：在所述待迁移虚拟机的热迁移过程中，PCIE设备接收待迁移VF对应的报文，所述待迁移VF为所述多个VF中的VF；PCIE设备根据所述报文确定直接内存访问DMA地址；以及，PCIE设备向所述PF驱动发送所述DMA地址。

Description

一种信息处理方法、物理机和PCIE设备
本申请要求于2019年07月31日提交中国国家知识产权局、申请号为201910703910.9、发明名称为“一种信息处理方法、物理机和PCIE设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机领域，尤其涉及一种信息处理方法、物理机和PCIE设备。
背景技术
在典型的虚拟机应用架构中，一台物理机上安装具有管理虚拟机功能的虚拟机管理器(virtual machine manager,VMM)，由VMM管理一个或多个虚拟机VM，每个VM上可以运行操作系统(operating system，OS)以及各种应用。物理机的硬件主要包括：一部分跟运行虚拟机相关的硬件，例如中央处理器(central processing unit，CPU)、内存、硬盘等，以及一部分不直接用于运行虚拟机，而用于执行一些特定业务，且功能相对独立的硬件，例如物理机内的快捷外围部件互连标准(peripheral component interconnection express，PCIE)设备(如网卡适配器、显卡等)。
单根I/O虚拟化(single-root I/O virtualization，SR-IOV)是一种输入输出(input/output，I/O)虚拟化技术，该技术可以在一个PCIE设备上虚拟化出多个虚拟的PCIE适配器，称之为虚拟功能(virtual function，VF)，VF能够通过与物理主机内存进行DMA(direct memory access，直接内存访问)操作，实现PCIE设备与VM之间的数据交互。
物理机在实现虚拟化后，可以通过主机实现虚拟机热迁移，虚拟机热迁移技术是指通过热迁移将虚拟机从一台主机中转移到另一台主机中，热迁移过程可以包括主机对要迁移的数据的标脏，以及标脏数据的迁移。
VF能够直接与物理机内存进行DMA操作，即VF可以直接将数据传递到DMA地址对应的物理机内存中，在VM的热迁移过程中，这部分数据也需要进行迁移。然而，由于VF不需要通过主机就可以完成DMA操作，主机无法获取到这部分需要迁移的数据所在物理机内存的DMA地址，进而在热迁移过程中，主机无法实现这部分数据的标脏和热迁移。
发明内容
本申请提供了一种信息处理方法，由PCIE设备记录DMA地址，并将该DMA地址发送到主机中的PF驱动，使得主机可以获取到DMA地址，并根据DMA地址进行标脏和热迁移。
第一方面，本申请提供了一种信息处理方法，应用于物理机，所述物理机设置有快捷外围部件互连标准PCIE设备，所述物理机中运行有包括第一虚拟机VM在内的至少一个虚拟机VM、用于管理所述PCIE设备的物理功能PF驱动以及虚拟机管理器VMM，所述方法包括：在所述第一VM的热迁移过程中，所述PCIE设备接收发送给所述第一VM的报文；所述PCIE设备基于所述报文确定所述第一VM对应的直接内存访问DMA地址；所述PCIE设备将所述DMA地址传递给所述PF驱动；所述PF驱动生成用于指示所述DMA地址的脏位比特； 所述PF驱动将所述脏位比特写入脏位图，以便所述VMM获取，所述脏位图用于保存所述第一VM的热迁移过程需要迁移的数据所在的地址。
通过上述方式，由PCIE设备记录DMA地址，并将该DMA地址发送到主机中的PF驱动，使得主机可以获取到DMA地址，并根据DMA地址进行标脏和热迁移。
另一方面，比起由VMM不经过PCIE设备而直接获取到虚拟机VM对应的DMA地址，然后监测该DMA地址对应的内存空间是否有修改内存动作的方案，由于虚拟机VM对应的DMA地址可以是实时变化的(即VM有权限使用的DMA地址可能是动态变化的)，而VMM需要实时获取虚拟机VM对应的DMA地址，会导致物理机的CPU开销过大，本申请实施例中，由于PCIE设备可以知道VM对应的DMA地址的变化(VM对应的VF驱动会将VM对应的DMA地址发送到PCIE设备)，因此，PCIE设备可以直接将DMA地址发送到主机，减小了物理机的CPU开销。
在第一方面的一种可选设计中，所述PCIE设备将所述DMA地址传递给所述PF驱动，包括：所述PCIE设备将所述DMA地址写入所述PF驱动的接收队列的缓存buffer；所述PCIE设备向所述PF驱动发送第一中断，所述第一中断用于指示所述PF驱动读取所述接收队列的buffer。
在第一方面的一种可选设计中，所述PCIE设备将所述DMA地址传递给所述PF驱动，包括：所述PCIE设备将所述DMA地址写入邮箱mailbox；所述PCIE设备向所述PF驱动发送第二中断，所述第二中断用于指示所述PF驱动读取所述mailbox以获取所述DMA地址。
这样，比起由VMM不经过PCIE设备而直接获取到虚拟机VM对应的DMA地址，然后监测该DMA地址对应的内存空间，当有修改内存动作时标记对应的DMA地址的方案中，需要VMM占用CPU中大块的连续内存，本申请实施例中，PCIE设备通过接收队列以及邮箱mailbox的方式向主机的PF驱动发送DMA地址，由于接收队列的buffer的大小可控，以及邮箱mailbox的缓存buffer的大小可控，且接收队列上的buffer之间占用的内存是离散的，不需要占用CPU中大块的连续内存。
在第一方面的一种可选设计中，所述PCIE设备基于所述报文确定所述第一VM对应的直接内存访问DMA地址，包括：所述PCIE设备基于所述报文从所述第一VM对应的L个DMA地址中得到N个DMA地址，其中，所述L个DMA地址和所述N个DMA地址归属相同的一组内存页，且N小于L；相应的，所述PCIE设备将所述DMA地址传递给所述PF驱动，包括：所述PCIE设备将所述N个DMA地址传递给所述PF驱动。
本申请实施例中，数据处理单元在确定报文对应的L个DMA地址之后，会对L个DMA地址进行筛选，在保证每个内存页对应至少一个DMA地址的前提下，仅保留N个DMA地址。也就是保障筛选后的DMA地址也能指示的筛选前的DMA地址对应的所有内存页，节省了资源占用。
在第一方面的一种可选设计中，所述PCIE设备还包括至少一个虚拟功能VF，在所述第一VM的热迁移中，所述第一VM与所述至少一个VF中的第一VF对应，所述方法还包括：所述PF驱动向所述PCIE设备发送第一虚拟功能VF的功能标识；所述PCIE设备根据所述第一VF的功能标识确定所述第一VM。这样，PCIE设备可以获知第一VM是需要进行热迁移 的，进而在接收到发送给第一VM的报文后，将第一VM对应的DMA地址发送到主机中的PF驱动。
在第一方面的一种可选设计中，所述脏位图包括第一脏位图和第二脏位图，所述第一脏位图可写，所述第二脏位图可读，所述PF驱动将所述脏位比特写入脏位图，包括：所述PF驱动将所述脏位比特写入所述第一脏位图；所述PF驱动将所述第一脏位图更改为可读，以便所述VMM从所述第一脏位图中获取写入的所述脏位比特。
在第一方面的一种可选设计中，所述PF驱动将所述第一脏位图更改为可读后，所述方法还包括：所述PF驱动将所述第二脏位图更改为可写，以便所述PF驱动写入信息。这样，可以通过读写双脏位图的机制保证了对脏位图读写访问的最大并发性。
在第一方面的一种可选设计中，所述VMM从所述第一脏位图中获取写入的所述脏位比特之后，所述方法还包括：所述PF驱动清空所述第一脏位图。
第二方面，本申请提供了一种信息处理方法，应用于PCIE设备，所述PCIE设备设置于物理机，所述物理机运行有主机和包括第一虚拟机VM在内的至少一个虚拟机VM，所述主机包括用于管理所述PCIE设备的物理功能PF驱动，所述方法包括：在所述第一VM的热迁移过程中，接收发送给所述第一VM的报文；基于所述报文确定所述第一VM对应的直接内存访问DMA地址；将所述DMA地址传递给所述PF驱动，以便所述主机处理。
在第二方面的一种可选设计中，所述将DMA地址传递给所述PF驱动，包括：将所述DMA地址写入所述PF驱动的接收队列的缓存buffer；向所述PF驱动发送第一中断，所述第一中断用于指示所述PF驱动接收所述接收队列的buffer。
在第二方面的一种可选设计中，所述将DMA地址传递给所述PF驱动，包括：
将所述DMA地址写入邮箱mailbox；
向所述PF驱动发送第二中断，所述第二中断用于指示所述PF驱动读取所述mailbox以获取所述DMA地址。
在第二方面的一种可选设计中，所述基于所述报文确定所述第一VM对应的直接内存访问DMA地址，包括：
基于所述报文从所述第一VM对应的L个DMA地址中得到N个DMA地址，其中，所述L个DMA地址和所述N个DMA地址归属相同的一组内存页，且N小于L；
相应的，所述将所述DMA地址传递给所述PF驱动，包括：
将所述N个DMA地址传递给所述PF驱动。
在第二方面的一种可选设计中，所述PCIE设备还包括至少一个虚拟功能VF，在所述第一VM的热迁移中，所述第一VM与所述至少一个VF中的第一VF对应，所述方法还包括：
接收所述PF驱动发送的第一VF的功能标识；
所述PCIE设备根据所述第一VF的功能标识确定所述第一VM。
第三方面，本申请提供了一种信息处理方法，所述方法应用于PF驱动，所述PF驱动运行于物理机，所述物理机设置有快捷外围部件互连标准PCIE设备，所述物理机还运行有第一虚拟机VM在内的至少一个虚拟机VM以及虚拟机管理器VMM，所述方法包括：
在所述第一VM的热迁移过程中，接收所述PCIE设备传递的DMA地址，所述DMA地址对应于所述第一VM；
生成用于指示所述DMA地址的脏位比特；
将所述脏位比特写入脏位图，以便所述VMM获取，所述脏位图用于保存所述第一VM的热迁移过程需要迁移的数据所在的地址。
在第三方面的一种可选设计中，所述接收所述PCIE设备传递的DMA地址，包括：
接收所述PCIE设备发送的第一中断；
根据所述第一中断读取接收队列的buffer，所述buffer写有所述DMA地址。
在第三方面的一种可选设计中，所述PF驱动接收所述PCIE设备传递的DMA地址，包括：
接收所述PCIE设备发送的第二中断；
根据所述第二中断读取mailbox以获取所述DMA地址，所述mailbox写有所述DMA地址。
在第三方面的一种可选设计中，所述PCIE设备还包括至少一个虚拟功能VF，在所述第一VM的热迁移中，所述第一VM与所述至少一个VF中的第一VF对应，所述方法还包括：
向所述PCIE设备发送第一虚拟功能VF的功能标识，以便所述PCIE设备根据所述第一VF的功能标识确定所述第一VM。
在第三方面的一种可选设计中，所述脏位图包括第一脏位图和第二脏位图，所述第一脏位图可写，所述第二脏位图可读，将所述脏位比特写入脏位图，包括：
将所述脏位比特写入所述第一脏位图；
将所述第一脏位图更改为可读，以便所述VMM从所述第一脏位图中获取写入的所述脏位比特。
在第三方面的一种可选设计中，将所述第一脏位图更改为可读后，所述方法还包括：将所述第二脏位图更改为可写，以便写入信息。
在第三方面的一种可选设计中，所述VMM从所述第一脏位图中获取写入的所述脏位比特之后，所述方法还包括：
清空所述第一脏位图。
第四方面，本申请提供了一种物理机，物理机设置有快捷外围部件互连标准PCIE设备，所述物理机中运行有包括第一虚拟机VM在内的至少一个虚拟机VM、用于管理所述PCIE设备的物理功能PF驱动以及虚拟机管理器VMM，其中，
在所述第一VM的热迁移过程中，所述PCIE设备用于接收发送给所述第一VM的报文，基于所述报文确定所述第一VM对应的直接内存访问DMA地址，将所述DMA地址传递给所述PF驱动；
所述PF驱动用于生成用于指示所述DMA地址的脏位比特；将所述脏位比特写入脏位图，以便所述VMM获取，所述脏位图用于保存所述第一VM的热迁移过程需要迁移的数据所在的地址。
在第四方面的一种可选设计中，所述PCIE设备，具体用于：
将所述DMA地址写入所述PF驱动的接收队列的缓存buffer，向所述PF驱动发送第一中断，所述第一中断用于指示所述PF驱动读取所述接收队列的buffer。
在第四方面的一种可选设计中，所述PCIE设备，具体用于：
将所述DMA地址写入邮箱mailbox，向所述PF驱动发送第二中断，所述第二中断用于指示所述PF驱动读取所述mailbox以获取所述DMA地址。
在第四方面的一种可选设计中，所述PCIE设备，具体用于：
基于所述报文从所述第一VM对应的L个DMA地址中得到N个DMA地址，其中，所述L个DMA地址和所述N个DMA地址归属相同的一组内存页，且N小于L；
将所述N个DMA地址传递给所述PF驱动。
在第四方面的一种可选设计中，所述PCIE设备还包括至少一个虚拟功能VF，在所述第一VM的热迁移中，所述第一VM与所述至少一个VF中的第一VF对应，所述PF驱动，还用于：向所述PCIE设备发送第一虚拟功能VF的功能标识；
所述PCIE设备，还用于：根据所述第一VF的功能标识确定所述第一VM。
在第四方面的一种可选设计中，所述脏位图包括第一脏位图和第二脏位图，所述第一脏位图可写，所述第二脏位图可读，所述PF驱动，具体用于：
将所述脏位比特写入所述第一脏位图；
将所述第一脏位图更改为可读，以便所述VMM从所述第一脏位图中获取写入的所述脏位比特。
在第四方面的一种可选设计中，所述PF驱动，还用于：将所述第二脏位图更改为可写，以便所述PF驱动写入信息。
在第四方面的一种可选设计中，所述PF驱动，还用于：清空所述第一脏位图。
第五方面，本申请提供了一种快捷外围部件互连标准PCIE设备，所述PCIE设备设置于物理机，所述物理机运行有主机和包括第一虚拟机VM在内的至少一个虚拟机VM，所述主机包括用于管理所述PCIE设备的物理功能PF驱动，所述PCIE设备包括：
收发模块，用于在所述第一VM的热迁移过程中，接收发送给所述第一VM的报文；
处理模块，用于基于所述报文确定所述第一VM对应的直接内存访问DMA地址；
所述收发模块，还用于将所述DMA地址传递给所述PF驱动，以便所述主机处理。
在第五方面的一种可选设计中，所述收发模块，具体用于：
将所述DMA地址写入所述PF驱动的接收队列的缓存buffer；
向所述PF驱动发送第一中断，所述第一中断用于指示所述PF驱动接收所述接收队列的buffer。
在第五方面的一种可选设计中，所述收发模块，具体用于：
将所述DMA地址写入邮箱mailbox；
向所述PF驱动发送第二中断，所述第二中断用于指示所述PF驱动读取所述mailbox以获取所述DMA地址。
在第五方面的一种可选设计中，所述处理模块，还用于基于所述报文从所述第一VM对 应的L个DMA地址中得到N个DMA地址，其中，所述L个DMA地址和所述N个DMA地址归属相同的一组内存页，且N小于L；
所述收发模块，具体用于：
将所述N个DMA地址传递给所述PF驱动。
在第五方面的一种可选设计中，所述PCIE设备还包括至少一个虚拟功能VF，在所述第一VM的热迁移中，所述第一VM与所述至少一个VF中的第一VF对应，所述收发模块，还用于接收所述PF驱动发送的第一VF的功能标识；
所述处理模块，还用于根据所述第一VF的功能标识确定所述第一VM。
第六方面，本申请提供了一种主机，所述主机运行于物理机，所述物理机设置有快捷外围部件互连标准PCIE设备，所述物理机还运行有第一虚拟机VM在内的至少一个虚拟机VM以及虚拟机管理器VMM，包括：
收发模块，用于在所述第一VM的热迁移过程中，接收所述PCIE设备传递的DMA地址，所述DMA地址对应于所述第一VM，生成用于指示所述DMA地址的脏位比特；
处理模块，用于将所述脏位比特写入脏位图，以便所述VMM获取，所述脏位图用于保存所述第一VM的热迁移过程需要迁移的数据所在的地址。
在第六方面的一种可选设计中，所述收发模块，具体用于接收所述PCIE设备发送的第一中断，根据所述第一中断读取接收队列的buffer，所述buffer写有所述DMA地址。
在第六方面的一种可选设计中，所述收发模块，具体用于接收所述PCIE设备发送的第二中断，根据所述第二中断读取mailbox以获取所述DMA地址，所述mailbox写有所述DMA地址。
在第六方面的一种可选设计中，所述PCIE设备还包括至少一个虚拟功能VF，在所述第一VM的热迁移中，所述第一VM与所述至少一个VF中的第一VF对应，所述收发模块，还用于向所述PCIE设备发送第一虚拟功能VF的功能标识，以便所述PCIE设备根据所述第一VF的功能标识确定所述第一VM。
在第六方面的一种可选设计中，所述脏位图包括第一脏位图和第二脏位图，所述第一脏位图可写，所述第二脏位图可读，所述处理模块，还用于：
将所述脏位比特写入所述第一脏位图，将所述第一脏位图更改为可读，以便所述VMM从所述第一脏位图中获取写入的所述脏位比特。
在第六方面的一种可选设计中，所述处理模块，还用于将所述第二脏位图更改为可写，以便写入信息。
在第六方面的一种可选设计中，所述处理模块，还用于清空所述第一脏位图。
第七方面，本申请提供了一种通信设备，包括：处理器、存储器和PCIE设备；
所述处理器、所述存储器和所述PCIE设备之间电连接；
所述处理器用于基于所述存储器中的代码运行PF驱动；
并通过所述PF驱动和所述PCIE设备执行上述第一方面任一所述的方法。
第八方面，本申请提供了一种通信设备，包括：处理器和存储器；
所述处理器和所述存储器电连接；
所述处理器用于基于所述存储器中的代码执行上述第三方面任一项所述的方法。
从以上技术方案可以看出，本申请实施例具有以下优点：
本申请提供了一种信息处理方法，包括：在所述待迁移虚拟机的热迁移过程中，PCIE设备接收待迁移VF对应的报文，所述待迁移VF为所述多个VF中的VF；PCIE设备根据所述报文确定直接内存访问DMA地址；以及，PCIE设备向所述PF驱动发送所述DMA地址。通过上述方式，由PCIE设备记录DMA地址，并将该DMA地址发送到主机中的PF驱动，使得主机可以获取到DMA地址，并根据DMA地址进行标脏和热迁移。通过上述方式，由PCIE设备记录DMA地址，并将该DMA地址发送到主机中的PF驱动，使得主机可以获取到DMA地址，并根据DMA地址进行标脏和热迁移。
附图说明
图1为本发明实施例提供的一种应用架构的示意图；
图2为虚拟机热迁移的一种迁移架构示意图；
图3a为本申请实施例提供的一种信息处理方法的流程示意图；
图3b为本申请实施例提供的一种DMA地址传递的流程示意图；
图4为本申请实施例提供的另一种信息处理方法的流程示意图；
图5a为本申请实施例中提供的一种脏位图读写示意图；
图5b为本申请实施例中提供的一种脏位图读写示意图；
图6为本申请实施例提供的一种物理机的结构示意图；
图7为本申请实施例提供的一种快捷外围部件互连标准PCIE设备的结构示意图路；
图8为本申请实施例提供的一种主机的结构示意图；
图9为本申请实施例中一种物理机的一个实施例示意图。
具体实施方式
下面结合附图，对本申请的实施例进行描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。本领域普通技术人员可知，随着技术的发展和新场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或模块的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或模块，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或模块。在本申请中出现的对步骤进行的命名或者编号，并不意味着必须按照命名或者编号所指示的时间/逻辑先后顺序执行方法流程中的步骤，已经命名或者编号的流程步骤可以根据要实现的技术目的变更执行次序，只要能达到相同或者相类似的技术效果 即可。
为了便于实施例的描述，下面先简单介绍一下本发明实施例的应用场景。参见图1，图1为本发明实施例提供的一种应用架构的示意图。本发明实施例可以应用在物理机100中，其中，物理机100可以运行有主机110、快捷外围部件互连标准(peripheral component interconnection express，PCIE)设备120和至少一个虚拟机(virtual machine，VM)(即图1中示出的虚拟机VM1～VM3，需要注意的是，虚拟机的数量不作为对本方案实施例的限制，实际应用中可以随时根据需求作出调整，这里只是为了方便说明才列举了三个虚拟机)。
该主机110上运行有VMM 111，该VMM 111可以管理一个或多个虚拟机VM，每个虚拟机VM上可以运行操作系统以及运行在操作系统上的各种应用。需要理解的是，在一些场景中，本实施例中的虚拟机管理器VMM可以实现虚拟机监控器(virtual machine monitor，VMM)的一部分或全部功能。
在具体实现过程中，虚拟机管理器VMM可以由定制的逻辑芯片实现，其负责虚拟机的管理和控制，包括完成虚拟机的属性和状态的监控和修改，虚拟机的创建、迁移、上电和下电等操作。
尽管图1中未示出，该主机110还包括跟运行虚拟机VM相关的硬件，例如中央处理器(central processing unit，CPU)及至少一个计算机可读存储介质的存储器(硬盘、内存等)。除此之外，该主机110还可以包括通信单元、输入单元、显示单元等。
主机110可以与PCIE设备120连接，该PCIE设备120为一个支持单根输入输出虚拟化SR-IOV标准的硬件设备。PCIE设备120包括至少一个物理功能(physical function，PF)以及至少一个虚拟功能VF，图1中为了方便描述，仅示出了一个PF与三个VF(VF1、VF2和VF3)。其中，PF和VF都配置有唯一的功能号function id。每个PF或VF与一个虚拟机VM相对应，PF或VF的功能号function id与虚拟机VM的对应关系可以保存在PCIE设备120的管理单元121和数据处理单元122中。其中，该数据处理单元122具体可以是L2vSwitch虚拟交换机。
主机110上还运行有管理PCIE设备120的PF驱动(所述PF驱动可以直接访问PF的所有资源，并负责配置和管理所有VF)，每个虚拟机VM运行有VF驱动来管理各自对应的VF。需要注意的是，每个虚拟机与VF的绑定关系并不是不能改变的，本实施例中仅是为了说明每个虚拟机VM与每个VF的一一对应关系，如VM1对应VF1。
每个虚拟机VM可以基于DMA操作与其对应的一个或多个VF直接进行网络I/O的数据交互，无需通过VMM，既降低了VMM中的I/O性能开销，又保证了每个VM的I/O吞吐效率。具体的，虚拟机VM从VF收发数据报文时，可以结合CPU提供的输入输出存储管理单元(input/output memory management unit，IOMMU)技术，实现收发完全独立，在VF将数据报文写入DMA地址对应的物理机内存的过程中，VMM 111并不能感知。
本申请实施例中，每个虚拟机VM的VF驱动可以获取虚拟机VM有权限使用的DMA地址，其中，DMA地址为物理机内存的内存地址。VF驱动可以将DMA地址通过对应的VF发送到数据处理单元122，因此，数据处理单元122可以保存各个虚拟机VM与DMA地址的对应关系，需要说明的是，各个虚拟机VM与DMA地址的对应关系可以理解为各个VM有权限使用的DMA 地址。VF在通过DMA操作将报文发送给VM的过程中，可以将报文写入到VM有权限使用的DMA地址对应的物理机内存中。例如：虚拟机VM1的VF驱动与VF1相连，虚拟机VM1的VF驱动获取虚拟机VM1有权限使用的DMA地址，并将虚拟机VM1有权限使用的DMA地址通过VF1传递到数据处理单元122，相应的，数据处理单元122可以保存虚拟机VM1有权限使用的DMA地址。
此外，数据处理单元122还维护有各个VF与VM的对应关系。当PCIE设备120中的数据处理单元122接收到报文时(该报文的来源可以是外网，也可以是物理机中的VM)，可以根据该报文的目的地址确定要需要发送到的VM，并基于VF与VM的对应关系，确定该VM对应的VF，从而将该报文传递到对应的VF，进而VF可以基于VM与DMA地址的对应关系发起DMA操作，将该报文写入该VM有权限使用的DMA地址对应的物理机内存中，相应的，VM可以从有权限使用的DMA地址对应的物理机内存中获取报文。
需要说明的是，以上所述的设备种类及连接方式仅为举例，本发明对此不作限制。
在一种应用场景中，某一VM需要维护时，通常可以将VM的运行状态完整地保存下来并恢复到另一个平台上，即可以进行虚拟机热迁移。例如，参照图2，图2为虚拟机热迁移的一种迁移架构示意图，当图2中虚拟机201需要维护时，可以将虚拟机201的运行状态迁移到同一物理机上的其他虚拟机202或者迁移到其他物理机上的虚拟机211、212、213上。
在实际场景中，物理机可以是提供各种云服务的服务器。
服务器在实现虚拟化后，可以方便地实现虚拟机VM的热迁移，而虚拟机VM热迁移的关键就是内存的迁移，通常虚拟机VM内存的迁移可为三个阶段:
1、迭代预拷贝阶段:虚拟机VM迁移过程启动后，其依然运行在源服务器上，虚拟机VM业务不中断，首先主机把虚拟机VM的全部内存复制到目的服务器上，然后主机将虚拟机VM中变化的内存数据进行标脏，并向目的服务器不停的迭代复制标脏后的内存数据。当迭代到需要复制的内存小到一定的门限后，进入停机拷贝阶段。
需要说明的是，上述主机实现的步骤可以有主机中的VMM实现。
2、停机拷贝阶段:虚拟机VM停机，业务中断，拷贝虚拟机VM的残余内存数据。
3、恢复阶段：目的虚拟机VM完成运行前的恢复处理，启动目的虚拟机VM，整个迁移过程完成。
可见，在VM热迁移过程中，要迁移的数据需要主机完成标脏和迁移。
然而，在使用SR-IOV技术的场景下，由于VF能够直接与物理机内存进行DMA操作，即VF可以直接将数据传递到DMA地址对应的物理机内存中，在VM的热迁移过程中，这部分数据也需要迁移。然而，由于VF不需要通过主机就可以完成DMA操作，因此，主机无法获取到需要迁移的数据所在物理机内存的DMA地址，进而在热迁移过程中，主机无法实现这部分数据的标脏和热迁移。
为了解决上述问题，本申请提供了一种信息处理方法，该信息处理方法应用于物理机，所述物理机设置有快捷外围部件互连标准PCIE设备，所述物理机中运行有包括第一虚拟机 VM在内的至少一个虚拟机VM、用于管理所述PCIE设备的物理功能PF驱动以及虚拟机管理器VMM，参照图3a，图3a为本申请实施例提供的一种信息处理方法的流程示意图。如图3中示出的那样，本实施例提供的信息处理方法，包括：
301、在所述第一VM的热迁移过程中，所述PCIE设备接收发送给所述第一VM的报文。
本申请实施例中，在DMA的配置阶段，VF驱动可以向PCIE设备发送对应的虚拟机VM有权限使用的DMA地址(换一种表述方式，VM对应的DMA地址)。PCIE设备中的数据处理单元可以接收到上述VF发送的DMA地址。相应的，PCIE设备可以保存各个虚拟机VM与DMA地址之间的对应关系，由于PCIE设备中还保存有VF与各个虚拟机VM的对应关系，因此，PCIE设备可以保存VF与DMA地址之间的对应关系。
在一种实施例中，PCIE设备可以维护多个function表，每个function表对应一个VF，该function表中记录了VF、虚拟机VM以及DMA地址之间的对应关系。可选地，本申请实施例中，PCIE设备的管理单元和数据处理单元都可以维护上述function表。
本申请实施例中，在进行虚拟机热迁移之前，主机的PF驱动可以初始化与PCIE设备中管理单元的通信通道，即申请PF驱动与管理单元之间通信的通道资源。
可选的，在一种实施例中，PF驱动可以申请多个接收队列RQ(receive queue)的内存资源，并作为与PCIE设备中数据处理单元的数据传输链路。具体的，接收队列RQ可以包括多个元素，每个元素可以对应一个buffer，可选地，PF驱动可以预先配置接收队列RQ中包括的元素的数量，以及每个元素对应的buffer的大小。
需要说明的是，上述多个接收队列RQ中的每个接收队列RQ可以唯一对应一个队列标识。
本申请实施例中，PF驱动可以向管理单元下发待迁移VF的功能标识function id以及一个接收队列RQ的队列标识。进而，管理单元可以根据接收到的VF标识确定对应的VF，并确定该VF对应的VM为需要热迁移的VM(第一VM)，将该VF的内存标脏状态标注为需要内存标脏，且，将该VF与接收到的接收队列RQ的队列标识进行绑定。具体的，管理单元可以根据该VF的功能标识function id确定对应的function表，并在该function表中的一个字段标注为需要内存标脏，并在该function表中保存对应的接收队列RQ的队列标识。
需要说明的是，VF的功能标识function id可以用来区分不同的VF，在这里，功能标识function id可以由总线号和设备编号组成，本申请并不限定。
可选的，在一种实施例中，PF驱动可以和PCIE设备通过门铃和邮箱mailbox机制进行通信，具体的，PF驱动可以为PCIE设备申请mailbox缓存和门铃door bell寄存器来实现PF驱动和PCIE设备之间的通信，即在PF中为PCIE设备配置一个mailbox缓存和一个door bell寄存器，实现一种类似“敲门铃”的机制。若PCIE设备有报文需要发送，那么将数据直接发送给PF中的mailbox缓存，并向PF驱动发送第二中断，PF驱动接收到第二中断后，可以读取该第二中断对应的mailbox缓存。
本申请实施例中，PCIE设备可以接收到主机发送的第一虚拟功能VF的功能标识，并根据所述第一VF的功能标识确定所述第一VM。
本申请实施例中，PCIE设备可以接收发送给所述第一VM的报文，该报文可以是由外网发送的，或者是物理机上除第一VM之外的其他VM发送的。
302、所述PCIE设备基于所述报文确定所述第一VM对应的直接内存访问DMA地址。
本申请实施例中，PCIE设备中的数据处理单元在收到发送给所述第一VM的报文后，可以根据报文中的目的地址确定发送的目的VM为第一VM，并基于VM和VF的对应关系，确定第一VM对应的VF，之后读取该VF的状态标记，具体的，可以在该VF对应的function表中查找对应的用于指示VF内存标脏状态的字段。若该VF没有处于内存标脏状态，PCIE设备中的数据处理单元可以将报文正常传递到VF对应的接收队列。
本申请实施例中，若PCIE设备中的数据处理单元读取该VF的状态标记，并确定该VF处于内存标脏状态，则从function表中获取相应的DMA地址。
可选的，在一种实施例中，数据处理单元可以基于所述报文从所述第一VM对应的L个DMA地址中得到N个DMA地址，其中，所述L个DMA地址和所述N个DMA地址归属相同的一组内存页，且N小于L。
本申请实施例中，数据处理单元可以在function表中确定第一VM对应有L个DMA地址，L为大于或等于2的正整数。
虚拟机VM是以内存页为单位进行内存的读写的，同一个内存页可以对应有多个DMA地址，而一个DMA地址对应一个内存页。
本申请实施例中，数据处理单元确定的L个DMA地址可以为N个内存页上的DMA地址，其中，N为小于L的正整数。
本申请实施例中，数据处理的单元可以确定N个内存页对应的N个DMA地址，其中，所述N个内存页中的每个内存页对应N个DMA地址中的至少一个DMA地址。
例如，数据处理单元确定报文对应的DMA地址为{地址1，地址2，地址3，地址4，地址5，地址6，地址7，地址8，地址9，地址10，地址11，地址12，地址13，地址14，地址15}，其中，
{地址1，地址2，地址3}为内存页1上的DMA地址；
{地址4，地址5}为内存页2上的DMA地址；
{地址6，地址7，地址8}为内存页3上的DMA地址；
{地址9，地址10，地址11，地址12，地址13，地址14，地址15}为内存页4上的DMA地址。
此时，15个DMA地址为4个内存页上的DMA地址。
数据处理的单元可以确定4个内存页对应的N个DMA地址，其中，4个内存页中的每个内存页对应N个DMA地址中的至少一个DMA地址。
例如，数据处理的单元可以确定4个内存页对应的4个DMA地址：{地址1，地址4，地址6，地址9}，其中，内存页1对应地址1，内存页2对应地址4，内存页3对应地址6，内存页4对应地址9。
在一种实施例中，内存页对应的DMA地址的数量可以大于1，例如，数据处理的单元可以确定4个内存页对应的5个DMA地址：{地址1，地址2，地址4，地址6，地址9}，其中，内存页1对应地址1和地址2，内存页2对应地址4，内存页3对应地址6，内存页4对应地址9。
本申请实施例中，数据处理单元在确定报文对应的L个DMA地址之后，会对L个DMA地址进行筛选，在保证每个内存页对应至少一个DMA地址的前提下，仅保留N个DMA地址。也就是保障筛选后的DMA地址也能指示的筛选前的DMA地址对应的所有内存页，节省了资源占。
303、所述PCIE设备将所述DMA地址传递给所述PF驱动。
本申请实施例中，数据处理单元可以在该VF对应的function表中查找到该VF绑定的接收队列RQ的标识，并将DMA地址写入接收队列RQ的标识对应的接收队列的一个缓存buffer中。
可选地，在一种实施例中，数据处理单元可以确定与该报文对应的多个DMA地址，对于虚拟机VM而言，一个内存页可能对应多个DMA地址，由于在进行内存热迁移的过程中，是以内存页为单位进行迁移的，因此，若数据处理单元确定与该报文对应的多个DMA中存在属于同一内存页内的多个DMA地址，则可以只向PF驱动发送在同一内存页内的多个DMA地址中的一个DMA地址。即，若数据处理单元确定与该报文对应的多个DMA中存在在同一内存页内的多个DMA地址，则可以只将属于同一内存页内的多个DMA地址中的一个DMA地址写入接收队列标识对应的接收队列RQ的一个缓存buffer中。
本申请实施例中，数据处理单元在将确定的DMA地址写入接收队列的缓存buffer之后，可以向PF驱动发送第一中断，该第一中断用于指示所述PF驱动接收所述buffer。
可选地，在一种实施例中，数据处理单元可以在判断满足如下预设条件中的至少一种时，向PF驱动发送第一中断，其中，预设条件可以包括：
1、buffer已写满DMA地址。
2、超时时间到；
3、待迁移VF不处于内存标脏状态。
在一种实施例中，数据处理单元可以在接收队列RQ中的一个buffer中写入DMA地址，数据处理单元可以实时判断该确定出的buffer是否已经写满DMA地址，并在判断出buffer已写满DMA地址之后，向PF驱动发送第一中断，来指示所述PF驱动接收所述接收队列的buffer。
在一种实施例中，数据处理单元可以在接收队列的多个缓存buffer中确定一个buffer，并写入DMA地址，数据处理单元可以在进行第一次写入操作时开始计时，当到达预设时间时，向PF驱动发送第一中断，来指示所述PF驱动接收所述接收队列的buffer。
在一种实施例中，数据处理单元可以实时监测待迁移VF对应的function表中待迁移VF的内存标脏状态，若内存标脏状态为不需要内存标脏，则向PF驱动发送第一中断，来指示所述PF驱动接收所述接收队列的buffer。
在一种实施例中，数据处理单元可以在接收队列的多个缓存buffer中确定一个buffer，并写入DMA地址，数据处理单元可以实时判断该确定出的buffer是否已经写满DMA地址，同时，在进行第一次写入操作时开始计时，以及实时监测待迁移VF对应的function表中待迁移VF的内存标脏状态。
本申请实施例中，数据处理单元可以在判断出buffer已写满DMA地址之后，向PF驱 动发送第一中断；或，数据处理单元可以在buffer未写满DMA地址，但当到达预设时间时，向PF驱动发送第一中断；或，数据处理单元可以在buffer未写满DMA地址，但确定待迁移VF不处于内存标脏状态时，向PF驱动发送第一中断；或，数据处理单元可以在buffer未写满DMA地址，且未到达预设时间，但确定待迁移VF不处于内存标脏状态时，向PF驱动发送第一中断。其中，第一中断可以指示所述PF驱动接收所述接收队列的buffer。
可选地，在一种实施例中，数据处理单元可以确定与该报文对应的多个DMA地址，对于虚拟机VM而言，一个内存页可能对应多个DMA地址，由于在进行内存热迁移的过程中，是以内存页为单位进行迁移的，因此，若数据处理单元确定与该报文对应的多个DMA中存在属于同一内存页内的多个DMA地址，则可以只向PF驱动发送在同一内存页内的多个DMA地址中的一个DMA地址。即，若数据处理单元确定与该报文对应的多个DMA中存在在同一内存页内的多个DMA地址，则可以只将属于同一内存页内的多个DMA地址中的一个DMA地址写入邮箱mailbox中。
本申请实施例中，数据处理单元在将确定的DMA地址写入邮箱mailbox之后，可以向PF驱动发送第二中断，该第二中断用于指示所述PF驱动读取所述mailbox以获取所述DMA地址。
可选地，在一种实施例中，数据处理单元可以在判断满足如下预设条件中的至少一种时，向PF驱动发送第二中断，其中，预设条件可以包括：
1、邮箱mailbox已写满DMA地址。
2、超时时间到；
3、待迁移VF不处于内存标脏状态。
在一种实施例中，数据处理单元可以在邮箱mailbox写入DMA地址，数据处理单元可以实时判断该邮箱mailbox是否已经写满DMA地址，并在判断出邮箱mailbox已写满DMA地址之后，向PF驱动发送第二中断，来指示所述PF驱动读取所述mailbox以获取所述DMA地址。
在一种实施例中，数据处理单元可以在邮箱mailbox写入DMA地址，数据处理单元可以在进行第一次写入操作时开始计时，当到达预设时间时，向PF驱动发送第二中断，来指示所述PF驱动读取所述mailbox以获取所述DMA地址。
在一种实施例中，数据处理单元可以实时监测待迁移VF对应的function表中待迁移VF的内存标脏状态，若内存标脏状态为不需要内存标脏，则向PF驱动发送第二中断，来指示所述PF驱动读取所述mailbox以获取所述DMA地址。
在一种实施例中，数据处理单元可以在邮箱mailbox写入DMA地址，数据处理单元可以实时判断该邮箱mailbox是否已经写满DMA地址，同时，在进行第一次写入操作时开始计时，以及实时监测待迁移VF对应的function表中待迁移VF的内存标脏状态。
本申请实施例中，数据处理单元可以在判断出邮箱mailbox已写满DMA地址之后，向PF驱动发送第二中断；或，数据处理单元可以在邮箱mailbox未写满DMA地址，但当到达预设时间时，向PF驱动发送第二中断；或，数据处理单元可以在邮箱mailbox未写满DMA地址，但确定待迁移VF不处于内存标脏状态时，向PF驱动发送第二中断；或，数据处理 单元可以在邮箱mailbox未写满DMA地址，且未到达预设时间，但确定待迁移VF不处于内存标脏状态时，向PF驱动发送第二中断。其中，第二中断可以指示所述PF驱动读取所述mailbox以获取所述DMA地址。
304、所述PF驱动生成用于指示所述DMA地址的脏位比特。
本申请实施例中，PF驱动在获取到DMA地址后，可以生成用于指示DMA地址的脏位比特。
305、所述PF驱动将所述脏位比特写入脏位图，以便所述VMM获取，所述脏位图用于保存所述第一VM的热迁移过程需要迁移的数据所在的地址。
本申请实施例中，PF驱动生成用于指示所述DMA地址的脏位比特后，可以将所述脏位比特写入脏位图，以便所述VMM获取，其中，所述脏位图用于保存所述第一VM的热迁移过程需要迁移的数据所在的地址。相应的，VMM可以获取脏位图，并根据脏位图中的脏位比特进行内存热迁移。
可选地，在一种实施例中，主机的PF驱动可以读取邮箱mailbox并获取邮箱mailbox中写入的DMA地址，然后PF驱动可以将DMA地址转换成标脏比特并写入脏位图中，物理机的VMM可以获取脏位图，并根据脏位图中的脏位比特进行内存热迁移。
需要说明的是，关于VMM如何根据脏位图中的脏位比特进行内存热迁移可以参照现有技术中的实现方式，这里不再赘述。
本申请实施例中，一方面，由PCIE设备记录DMA地址，并将该DMA地址发送到主机中的PF驱动，使得主机可以获取到DMA地址，并根据DMA地址进行标脏和热迁移。
另一方面，比起由VMM不经过PCIE设备而直接获取到虚拟机VM对应的DMA地址，然后监测该DMA地址对应的内存空间是否有修改内存动作的方案，由于虚拟机VM对应的DMA地址可以是实时变化的(即VM有权限使用的DMA地址可能是动态变化的)，而VMM需要实时获取虚拟机VM对应的DMA地址，会导致物理机的CPU开销过大，本申请实施例中，由于PCIE设备可以知道VM对应的DMA地址的变化(VM对应的VF驱动会将VM对应的DMA地址发送到PCIE设备)，因此，PCIE设备可以直接将DMA地址发送到主机，减小了物理机的CPU开销。
另一方面，比起由VMM不经过PCIE设备而直接获取到虚拟机VM对应的DMA地址，然后监测该DMA地址对应的内存空间，当有修改内存动作时标记对应的DMA地址的方案中，需要VMM占用CPU中大块的连续内存，本申请实施例中，PCIE设备通过接收队列以及邮箱mailbox的方式向主机的PF驱动发送DMA地址，由于接收队列的buffer的大小可控，以及邮箱mailbox的缓存buffer的大小可控，且接收队列上的buffer之间占用的内存是离散的，不需要占用CPU中大块的连续内存。
参照图3b，图3b为本申请实施例提供的一种DMA地址传递的流程示意图，如图3b中示出的那样，数据处理单元在接收到发送给第一VM的报文之后，可以确定该第一VM对应的VF，以及VF对应的function表，其中，function表记录了该VF的标脏状态为需要标脏，以及第一VM对应的DMA地址{DMA_1,DMA_2,DMA_3}和绑定的接收队列ID：接收队列1。
数据处理单元可以从多个PF驱动对应的多个接收队列中选择接收队列1，并将第一VM 对应的DMA地址{DMA_1,DMA_2,DMA_3}写入其中的一个buffer(buffer1)，相应的，PF驱动可以从接收队列1中的buffer1中获取到第一VM对应的DMA地址{DMA_1,DMA_2,DMA_3}。
本申请实施例提供了一种信息处理方法，包括：在所述待迁移虚拟机的热迁移过程中，PCIE设备接收待迁移VF对应的报文，所述待迁移VF为所述多个VF中的VF；PCIE设备根据所述报文确定直接内存访问DMA地址；以及，PCIE设备向所述PF驱动发送所述DMA地址。通过上述方式，由PCIE设备记录DMA地址，并将该DMA地址发送到主机中的PF驱动，使得主机可以获取到DMA地址，并根据DMA地址进行标脏和热迁移。
参照图4，图4为本申请实施例提供的另一种信息处理方法的流程示意图。本实施例提供的信息处理方法可以应用于PF驱动，所述PF驱动运行于物理机，所述物理机设置有快捷外围部件互连标准PCIE设备，所述物理机还运行有第一虚拟机VM在内的至少一个虚拟机VM以及虚拟机管理器VMM，所述信息处理方法具体包括：
401、在所述第一VM的热迁移过程中，接收所述PCIE设备传递的DMA地址，所述DMA地址对应于所述第一VM。
关于PF驱动如何接收所述PCIE设备传递的DMA地址可参照图3对应的实施例中的步骤303的描述，这里不再赘述。
402、所述PF驱动生成所述DMA地址对应的脏位比特。
需要说明的是，关于PF驱动如何生成所述DMA地址对应的脏位比特可以参照现有技术中的实现方式，这里不再赘述。
403、PF驱动将所述脏位比特写入脏位图，以便所述VMM获取，所述脏位图用于保存所述第一VM的热迁移过程需要迁移的数据所在的地址。
本申请实施例中，所述脏位图可以包括第一脏位图和第二脏位图。
本申请实施例中，PF驱动可以维护两个脏位图(第一脏位图和第二脏位图)，其中，第一脏位图的读写属性为可写，第二脏位图的读写属性为可读。
相应的，PF驱动在生成所述DMA地址对应的脏位比特之后，可以将所述脏位比特写入所述第一脏位图。
参照图5a，图5a为本申请实施例中提供的一种脏位图读写示意图，如图5a中示出的那样，在step 1阶段，第一脏位图的读写属性为可写，此时，若PF驱动获取到PCIE设备传递的DMA地址，则可以生成所述DMA地址对应的脏位比特，并将所述脏位比特写入第一脏位图。
本申请实施例中，VMM可以定时调用状态同步sync接口，来获取读写属性为可读的脏位图中的脏位比特。
需要说明的是，可以预先配置前述状态同步sync接口。在具体实现中，状态同步sync接口可以是用于实现接收功能的接口函数，通过调用该接口函数可以执行接收状态同步的代码。在配置状态同步sync接口时，可以为状态同步sync接口设置接口名称，例如为函数配置函数名。
如图5a中示出的那样，在step 1阶段，第一脏位图的读写属性为可写，第二脏位图 的可读属性为可读，此时，VMM可以调用同步sync接口，来读取第二脏位图中的脏位比特。
在VMM读取第二脏位图中的脏位比特之后，如图5a中示出的step 2阶段，PF驱动可以将第一脏位图的读写属性由可写设置为可读，以及将第二脏位图的读写属性由可读设置为可写，并清空第二脏位图。
本申请实施例中，如图5a中示出的，在step 3阶段，PF驱动将第一脏位图的可写属性变为可读之后，VMM可以获取所述第一脏位图中的脏位比特。在step 3阶段，VMM获取所述第一脏位图中的脏位比特之后，PF驱动可以将第一脏位图的读写属性由可读变为可写，以及将第二脏位图的读写属性由可写变为可读。相应的，在下一阶段，VMM可以获取第二脏位图中的脏位比特。
需要说明的是，图5a中仅仅示出了在step 1阶段，PF驱动将第一脏位图写入第一脏位图，在实际应用中，PF驱动可以实时接收到PCIE设备发送的DMA地址，并将生成DMA地址对应的脏位比特，写入到读写属性为可写的脏位图中。
示例性的，参照图5b，图5b为本申请实施例中提供的一种脏位图读写示意图，如图5b中示出的那样，在step 2阶段，PF驱动可以实时接收到PCIE设备发送的DMA地址，并将生成DMA地址对应的脏位比特，写入到第二脏位图中。
在step 3阶段，PF驱动可以实时接收到PCIE设备发送的DMA地址，并将生成DMA地址对应的脏位比特，写入到第二脏位图中。
在step 4阶段，PF驱动可以实时接收到PCIE设备发送的DMA地址，并将生成DMA地址对应的脏位比特，写入到第一脏位图中。
需要说明的是，图5a和图5b仅为一种示意，并不构成对本申请实施例的限定。
本申请实施例中，PF驱动可以申请两个脏位图buffer，其中一个buffer的读写属性为写属性，另一个buffer为读属性，通过读写双脏位图的机制保证了对脏位图读写访问的最大并发性。
参照图6，图6为本申请实施例提供的一种物理机的结构示意图，如图6中示出的那样，物理机600设置有快捷外围部件互连标准PCIE设备601，所述物理机600中运行有包括第一虚拟机VM604在内的至少一个虚拟机VM、用于管理所述PCIE设备601的物理功能PF驱动602以及虚拟机管理器VMM 603，其中，
在所述第一VM的热迁移过程中，所述PCIE设备601用于接收发送给所述第一VM的报文，基于所述报文确定所述第一VM对应的直接内存访问DMA地址，将所述DMA地址传递给所述PF驱动；
所述PF驱动602用于生成用于指示所述DMA地址的脏位比特；将所述脏位比特写入脏位图，以便所述VMM 603获取，所述脏位图用于保存所述第一VM的热迁移过程需要迁移的数据所在的地址。
可选的，在一种实施例中，所述PCIE设备601，具体用于：
将所述DMA地址写入所述PF驱动的接收队列的缓存buffer，向所述PF驱动发送第一中断，所述第一中断用于指示所述PF驱动读取所述接收队列的buffer。
可选的，在一种实施例中，所述PCIE设备601，具体用于：
将所述DMA地址写入邮箱mailbox，向所述PF驱动发送第二中断，所述第二中断用于指示所述PF驱动读取所述mailbox以获取所述DMA地址。
可选的，在一种实施例中，所述PCIE设备601，具体用于：
基于所述报文从所述第一VM对应的L个DMA地址中得到N个DMA地址，其中，所述L个DMA地址和所述N个DMA地址归属相同的一组内存页，且N小于L；
将所述N个DMA地址传递给所述PF驱动。
可选的，在一种实施例中，所述PCIE设备601还包括至少一个虚拟功能VF，在所述第一VM的热迁移中，所述第一VM与所述至少一个VF中的第一VF对应，所述PF驱动，还用于：向所述PCIE设备发送第一虚拟功能VF的功能标识；
所述PCIE设备601，还用于：根据所述第一VF的功能标识确定所述第一VM。
可选的，在一种实施例中，所述脏位图包括第一脏位图和第二脏位图，所述第一脏位图可写，所述第二脏位图可读，所述PF驱动602，具体用于：
将所述脏位比特写入所述第一脏位图；
将所述第一脏位图更改为可读，以便所述VMM从所述第一脏位图中获取写入的所述脏位比特。
可选的，在一种实施例中，所述PF驱动602，还用于：将所述第二脏位图更改为可写，以便所述PF驱动写入信息。
可选的，在一种实施例中，所述PF驱动602，还用于：清空所述第一脏位图。
参照图7，图7为本申请实施例提供的一种快捷外围部件互连标准PCIE设备的结构示意图路，如图7中示出的那样，所述PCIE设备700设置于所述物理机，所述物理机运行有主机和包括第一虚拟机VM在内的至少一个虚拟机VM，所述主机包括用于管理所述PCIE设备的物理功能PF驱动，所述PCIE设备包括：
收发模块701，用于在所述第一VM的热迁移过程中，接收发送给所述第一VM的报文；
处理模块702，用于基于所述报文确定所述第一VM对应的直接内存访问DMA地址；
所述收发模块701，还用于将所述DMA地址传递给所述PF驱动，以便所述主机处理。
可选的，在一种实施例中，所述收发模块701，具体用于：
将所述DMA地址写入所述PF驱动的接收队列的缓存buffer；
向所述PF驱动发送第一中断，所述第一中断用于指示所述PF驱动接收所述接收队列的buffer。
可选的，在一种实施例中，所述收发模块701，具体用于：
将所述DMA地址写入邮箱mailbox；
向所述PF驱动发送第二中断，所述第二中断用于指示所述PF驱动读取所述mailbox以获取所述DMA地址。
可选的，在一种实施例中，所述处理模块702，还用于基于所述报文从所述第一VM对应的L个DMA地址中得到N个DMA地址，其中，所述L个DMA地址和所述N个DMA地址归 属相同的一组内存页，且N小于L；
所述收发模块，具体用于：
将所述N个DMA地址传递给所述PF驱动。
可选的，在一种实施例中，所述PCIE设备700还包括至少一个虚拟功能VF，在所述第一VM的热迁移中，所述第一VM与所述至少一个VF中的第一VF对应，所述收发模块701，还用于接收所述PF驱动发送的第一VF的功能标识；
所述处理模块702，还用于根据所述第一VF的功能标识确定所述第一VM。
参照图8，图8为本申请实施例提供的一种主机的结构示意图，如图8中示出的那样，所述主机800运行于物理机，所述物理机设置有快捷外围部件互连标准PCIE设备，所述物理机还运行有第一虚拟机VM在内的至少一个虚拟机VM以及虚拟机管理器VMM，所述主机800，包括：
收发模块801，用于在所述第一VM的热迁移过程中，接收所述PCIE设备传递的DMA地址，所述DMA地址对应于所述第一VM，生成用于指示所述DMA地址的脏位比特；
处理模块802，用于将所述脏位比特写入脏位图，以便所述VMM获取，所述脏位图用于保存所述第一VM的热迁移过程需要迁移的数据所在的地址。
可选的，在一种实施例中，所述收发模块801，具体用于接收所述PCIE设备发送的第一中断，根据所述第一中断读取接收队列的buffer，所述buffer写有所述DMA地址。
可选的，在一种实施例中，所述收发模块801，具体用于接收所述PCIE设备发送的第二中断，根据所述第二中断读取mailbox以获取所述DMA地址，所述mailbox写有所述DMA地址。
可选的，在一种实施例中，所述PCIE设备800还包括至少一个虚拟功能VF，在所述第一VM的热迁移中，所述第一VM与所述至少一个VF中的第一VF对应，所述收发模块801，还用于向所述PCIE设备发送第一虚拟功能VF的功能标识，以便所述PCIE设备根据所述第一VF的功能标识确定所述第一VM。
可选的，在一种实施例中，所述脏位图包括第一脏位图和第二脏位图，所述第一脏位图可写，所述第二脏位图可读，所述处理模块802，还用于：
将所述脏位比特写入所述第一脏位图，将所述第一脏位图更改为可读，以便所述VMM从所述第一脏位图中获取写入的所述脏位比特。
可选的，在一种实施例中，所述处理模块802，还用于将所述第二脏位图更改为可写，以便写入信息。
可选的，在一种实施例中，所述处理模块802，还用于清空所述第一脏位图。
请参阅图9，图9为本申请实施例中一种物理机900的一个实施例示意图，本申请实施例中对其具体设备形态不做限定。
该物理机900可因配置或性能不同而产生比较大的差异，可以包括一个或一个以上处理器901和存储器902，该存储器902中存储有程序或数据。
其中，存储器902可以是易失性存储或非易失性存储。可选地，处理器901是一个或多个中央处理器(central processing unit，CPU)，该CPU可以是单核CPU，也可以是多核CPU。处理器901可以与存储器902通信，在物理机900上执行存储器902中的一系列指令。
该物理机900还包括PCIE设备903。
可选地，尽管图9中未示出，物理机900还可以包括一个或一个以上电源；一个或一个以上输入输出接口，输入输出接口可以用于连接显示器、鼠标、键盘、触摸屏设备或传感设备等，输入输出接口为可选部件，可以存在也可以不存在，此处不做限定。
本实施例中物理机900中的处理器901和PCIE设备903所执行的流程可以参考前述方法实施例中描述的方法流程，此处不加赘述。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者其他网络设备等)执行本申请图2实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (35)

  1. 一种信息处理方法，其特征在于，应用于物理机，所述物理机设置有快捷外围部件互连标准PCIE设备，所述物理机中运行有包括第一虚拟机VM在内的至少一个虚拟机VM、用于管理所述PCIE设备的物理功能PF驱动以及虚拟机管理器VMM，所述方法包括：
    在所述第一VM的热迁移过程中，所述PCIE设备接收发送给所述第一VM的报文；
    所述PCIE设备基于所述报文确定所述第一VM对应的直接内存访问DMA地址；
    所述PCIE设备将所述DMA地址传递给所述PF驱动；
    所述PF驱动生成用于指示所述DMA地址的脏位比特；
    所述PF驱动将所述脏位比特写入脏位图，以便所述VMM获取，所述脏位图用于保存所述第一VM的热迁移过程需要迁移的数据所在的地址。
  2. 根据权利要求1所述的方法，其特征在于，所述PCIE设备将所述DMA地址传递给所述PF驱动，包括：
    所述PCIE设备将所述DMA地址写入所述PF驱动的接收队列的缓存buffer；
    所述PCIE设备向所述PF驱动发送第一中断，所述第一中断用于指示所述PF驱动读取所述接收队列的buffer。
  3. 根据权利要求1所述的方法，其特征在于，所述PCIE设备将所述DMA地址传递给所述PF驱动，包括：
    所述PCIE设备将所述DMA地址写入邮箱mailbox；
    所述PCIE设备向所述PF驱动发送第二中断，所述第二中断用于指示所述PF驱动读取所述mailbox以获取所述DMA地址。
  4. 根据权利要求1至3任一所述的方法，其特征在于，所述PCIE设备基于所述报文确定所述第一VM对应的直接内存访问DMA地址，包括：
    所述PCIE设备基于所述报文从所述第一VM对应的L个DMA地址中得到N个DMA地址，其中，所述L个DMA地址和所述N个DMA地址归属相同的一组内存页，且N小于L；
    相应的，所述PCIE设备将所述DMA地址传递给所述PF驱动，包括：
    所述PCIE设备将所述N个DMA地址传递给所述PF驱动。
  5. 根据权利要求1至4任一所述的方法，其特征在于，所述PCIE设备还包括至少一个虚拟功能VF，在所述第一VM的热迁移中，所述第一VM与所述至少一个VF中的第一VF对应，所述方法还包括：
    所述PF驱动向所述PCIE设备发送第一虚拟功能VF的功能标识；
    所述PCIE设备根据所述第一VF的功能标识确定所述第一VM。
  6. 根据权利要求1至5任一所述的方法，其特征在于，所述脏位图包括第一脏位图和第二脏位图，所述第一脏位图可写，所述第二脏位图可读，所述PF驱动将所述脏位比特写入脏位图，包括：
    所述PF驱动将所述脏位比特写入所述第一脏位图；
    所述PF驱动将所述第一脏位图更改为可读，以便所述VMM从所述第一脏位图中获取写入的所述脏位比特。
  7. 根据权利要求6所述的方法，其特征在于，所述PF驱动将所述第一脏位图更改为可读后，所述方法还包括：所述PF驱动将所述第二脏位图更改为可写，以便所述PF驱动写入信息。
  8. 根据权利要求6或7所述的方法，其特征在于，所述VMM从所述第一脏位图中获取写入的所述脏位比特之后，所述方法还包括：
    所述PF驱动清空所述第一脏位图。
  9. 一种信息处理方法，其特征在于，应用于PCIE设备，所述PCIE设备设置于物理机，所述物理机运行有主机和包括第一虚拟机VM在内的至少一个虚拟机VM，所述主机包括用于管理所述PCIE设备的物理功能PF驱动，所述方法包括：
    在所述第一VM的热迁移过程中，接收发送给所述第一VM的报文；
    基于所述报文确定所述第一VM对应的直接内存访问DMA地址；
    将所述DMA地址传递给所述PF驱动，以便所述主机处理。
  10. 根据权利要求9所述的方法，其特征在于，所述将DMA地址传递给所述PF驱动，包括：
    将所述DMA地址写入所述PF驱动的接收队列的缓存buffer；
    向所述PF驱动发送第一中断，所述第一中断用于指示所述PF驱动接收所述接收队列的buffer。
  11. 根据权利要求9所述的方法，其特征在于，所述将DMA地址传递给所述PF驱动，包括：
    将所述DMA地址写入邮箱mailbox；
    向所述PF驱动发送第二中断，所述第二中断用于指示所述PF驱动读取所述mailbox以获取所述DMA地址。
  12. 根据权利要求9至11任一所述的方法，其特征在于，所述基于所述报文确定所述第一VM对应的直接内存访问DMA地址，包括：
    基于所述报文从所述第一VM对应的L个DMA地址中得到N个DMA地址，其中，所述L个DMA地址和所述N个DMA地址归属相同的一组内存页，且N小于L；
    相应的，所述将所述DMA地址传递给所述PF驱动，包括：
    将所述N个DMA地址传递给所述PF驱动。
  13. 根据权利要求9至12任一所述的方法，其特征在于，所述PCIE设备还包括至少一个虚拟功能VF，在所述第一VM的热迁移中，所述第一VM与所述至少一个VF中的第一VF对应，所述方法还包括：
    接收所述PF驱动发送的第一VF的功能标识；
    所述PCIE设备根据所述第一VF的功能标识确定所述第一VM。
  14. 一种信息处理方法，其特征在于，所述方法应用于PF驱动，所述PF驱动运行于物理机，所述物理机设置有快捷外围部件互连标准PCIE设备，所述物理机还运行有第一虚拟机VM在内的至少一个虚拟机VM以及虚拟机管理器VMM，所述方法包括：
    在所述第一VM的热迁移过程中，接收所述PCIE设备传递的DMA地址，所述DMA地址 对应于所述第一VM；
    生成用于指示所述DMA地址的脏位比特；
    将所述脏位比特写入脏位图，以便所述VMM获取，所述脏位图用于保存所述第一VM的热迁移过程需要迁移的数据所在的地址。
  15. 根据权利要求14所述的方法，其特征在于，所述接收所述PCIE设备传递的DMA地址，包括：
    接收所述PCIE设备发送的第一中断；
    根据所述第一中断读取接收队列的buffer，所述buffer写有所述DMA地址。
  16. 根据权利要求14所述的方法，其特征在于，所述PF驱动接收所述PCIE设备传递的DMA地址，包括：
    接收所述PCIE设备发送的第二中断；
    根据所述第二中断读取mailbox以获取所述DMA地址，所述mailbox写有所述DMA地址。
  17. 根据权利要求14至16任一所述的方法，其特征在于，所述PCIE设备还包括至少一个虚拟功能VF，在所述第一VM的热迁移中，所述第一VM与所述至少一个VF中的第一VF对应，所述方法还包括：
    向所述PCIE设备发送第一虚拟功能VF的功能标识，以便所述PCIE设备根据所述第一VF的功能标识确定所述第一VM。
  18. 根据权利要求14至17任一所述的方法，其特征在于，所述脏位图包括第一脏位图和第二脏位图，所述第一脏位图可写，所述第二脏位图可读，将所述脏位比特写入脏位图，包括：
    将所述脏位比特写入所述第一脏位图；
    将所述第一脏位图更改为可读，以便所述VMM从所述第一脏位图中获取写入的所述脏位比特。
  19. 根据权利要求18所述的方法，其特征在于，将所述第一脏位图更改为可读后，所述方法还包括：将所述第二脏位图更改为可写，以便写入信息。
  20. 根据权利要求18或19所述的方法，其特征在于，所述VMM从所述第一脏位图中获取写入的所述脏位比特之后，所述方法还包括：
    清空所述第一脏位图。
  21. 一种物理机，其特征在于，所述物理机设置有快捷外围部件互连标准PCIE设备，所述物理机中运行有包括第一虚拟机VM在内的至少一个虚拟机VM、用于管理所述PCIE设备的物理功能PF驱动以及虚拟机管理器VMM，其中，
    在所述第一VM的热迁移过程中，所述PCIE设备用于接收发送给所述第一VM的报文，基于所述报文确定所述第一VM对应的直接内存访问DMA地址，将所述DMA地址传递给所述PF驱动；
    所述PF驱动用于生成用于指示所述DMA地址的脏位比特；将所述脏位比特写入脏位图，以便所述VMM获取，所述脏位图用于保存所述第一VM的热迁移过程需要迁移的数据所在的 地址。
  22. 根据权利要求21所述的物理机，其特征在于，所述PCIE设备，具体用于：
    将所述DMA地址写入所述PF驱动的接收队列的缓存buffer，向所述PF驱动发送第一中断，所述第一中断用于指示所述PF驱动读取所述接收队列的buffer。
  23. 根据权利要求21所述的物理机，其特征在于，所述PCIE设备，具体用于：
    将所述DMA地址写入邮箱mailbox，向所述PF驱动发送第二中断，所述第二中断用于指示所述PF驱动读取所述mailbox以获取所述DMA地址。
  24. 根据权利要求21至23任一所述的物理机，其特征在于，所述PCIE设备，具体用于：
    基于所述报文从所述第一VM对应的L个DMA地址中得到N个DMA地址，其中，所述L个DMA地址和所述N个DMA地址归属相同的一组内存页，且N小于L；
    将所述N个DMA地址传递给所述PF驱动。
  25. 根据权利要求21至24任一所述的物理机，其特征在于，所述PCIE设备还包括至少一个虚拟功能VF，在所述第一VM的热迁移中，所述第一VM与所述至少一个VF中的第一VF对应，所述PF驱动，还用于：向所述PCIE设备发送第一虚拟功能VF的功能标识；
    所述PCIE设备，还用于：根据所述第一VF的功能标识确定所述第一VM。
  26. 根据权利要求21至25任一所述的物理机，其特征在于，所述脏位图包括第一脏位图和第二脏位图，所述第一脏位图可写，所述第二脏位图可读，所述PF驱动，具体用于：
    将所述脏位比特写入所述第一脏位图；
    将所述第一脏位图更改为可读，以便所述VMM从所述第一脏位图中获取写入的所述脏位比特。
  27. 根据权利要求26所述的物理机，其特征在于，所述PF驱动，还用于：将所述第二脏位图更改为可写，以便所述PF驱动写入信息。
  28. 根据权利要求26或27所述的物理机，其特征在于，所述PF驱动，还用于：清空所述第一脏位图。
  29. 一种快捷外围部件互连标准PCIE设备，其特征在于，所述PCIE设备设置于物理机，所述物理机运行有主机和包括第一虚拟机VM在内的至少一个虚拟机VM，所述主机包括用于管理所述PCIE设备的物理功能PF驱动，所述PCIE设备包括：
    收发模块，用于在所述第一VM的热迁移过程中，接收发送给所述第一VM的报文；
    处理模块，用于基于所述报文确定所述第一VM对应的直接内存访问DMA地址；
    所述收发模块，还用于将所述DMA地址传递给所述PF驱动，以便所述主机处理。
  30. 根据权利要求29所述的PCIE设备，其特征在于，所述收发模块，具体用于：
    将所述DMA地址写入所述PF驱动的接收队列的缓存buffer；
    向所述PF驱动发送第一中断，所述第一中断用于指示所述PF驱动接收所述接收队列的buffer。
  31. 根据权利要求29所述的PCIE设备，其特征在于，所述收发模块，具体用于：
    将所述DMA地址写入邮箱mailbox；
    向所述PF驱动发送第二中断，所述第二中断用于指示所述PF驱动读取所述mailbox以获取所述DMA地址。
  32. 根据权利要求29至31任一所述的PCIE设备，其特征在于，所述处理模块，还用于基于所述报文从所述第一VM对应的L个DMA地址中得到N个DMA地址，其中，所述L个DMA地址和所述N个DMA地址归属相同的一组内存页，且N小于L；
    所述收发模块，具体用于：
    将所述N个DMA地址传递给所述PF驱动。
  33. 根据权利要求29至32任一所述的PCIE设备，其特征在于，所述PCIE设备还包括至少一个虚拟功能VF，在所述第一VM的热迁移中，所述第一VM与所述至少一个VF中的第一VF对应，所述收发模块，还用于接收所述PF驱动发送的第一VF的功能标识；
    所述处理模块，还用于根据所述第一VF的功能标识确定所述第一VM。
  34. 一种通信设备，其特征在于，包括：处理器、存储器和PCIE设备；
    所述处理器、所述存储器和所述PCIE设备之间电连接；
    所述处理器用于基于所述存储器中的代码运行PF驱动；
    以使得所述PF驱动和所述PCIE设备执行如权利要求1至8中任一项所述的方法。
  35. 一种通信设备，其特征在于，包括：处理器和存储器；
    所述处理器和所述存储器电连接；
    所述处理器用于基于所述存储器中的代码执行如权利要求14至20中任一项所述的方法。
PCT/CN2020/098722 2019-07-31 2020-06-29 一种信息处理方法、物理机和pcie设备 Ceased WO2021017719A1 (zh)

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