WO2021036786A1 - 电子组件及电子设备 - Google Patents

电子组件及电子设备 Download PDF

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Publication number
WO2021036786A1
WO2021036786A1 PCT/CN2020/108530 CN2020108530W WO2021036786A1 WO 2021036786 A1 WO2021036786 A1 WO 2021036786A1 CN 2020108530 W CN2020108530 W CN 2020108530W WO 2021036786 A1 WO2021036786 A1 WO 2021036786A1
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WIPO (PCT)
Prior art keywords
temperature solder
solder layer
electronic component
pad
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/108530
Other languages
English (en)
French (fr)
Inventor
周洋
龙浩晖
叶润清
方建平
王竹秋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to EP20856813.9A priority Critical patent/EP4016613B1/en
Priority to CN202090000371.9U priority patent/CN216958013U/zh
Publication of WO2021036786A1 publication Critical patent/WO2021036786A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3465—Application of solder
    • H05K3/3485—Application of solder paste, slurry or powder
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
    • H—ELECTRICITY
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
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    • H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
    • H10W72/01223—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in liquid form, e.g. by dispensing droplets or by screen printing
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    • H10W72/01231—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition
    • H10W72/01233—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01235—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating
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    • H10W72/01251—Changing the shapes of bumps
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    • H10W72/01257—Changing the shapes of bumps by reflowing
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    • H10W72/07236—Soldering or alloying
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    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07253—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in shapes
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
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    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H10W72/07338—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy hardening the adhesive by curing, e.g. thermosetting
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/225—Bumps having a filler embedded in a matrix
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/231—Shapes
    • H10W72/232—Plan-view shape, i.e. in top view
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
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    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/253—Materials not comprising solid metals or solid metalloids, e.g. polymers or ceramics
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
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    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
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    • H10W74/00—Encapsulations, e.g. protective coatings
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    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
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Definitions

  • This application relates to the field of electronic technology, in particular to an electronic component and an electronic device.
  • the embodiments of the present application provide an electronic component and an electronic device, which are used to solve the problem of low bonding stability between electronic components.
  • an electronic component including: a first electronic component having at least one first pad on a first active surface; a second electronic component having at least one first pad on a second active surface Two pads, the second active surface and the first active surface are arranged oppositely; at least one first welding portion, one first welding portion is located between one first pad and one second pad, and the first welding portion Bonding with the first pad and the second pad on both sides thereof;
  • the first soldering portion includes a high-temperature solder layer and a low-temperature solder layer; the high-temperature solder layer is arranged close to the first pad and is bonded to the first pad;
  • the low temperature solder layer is arranged close to the second pad and is bonded to the second pad; wherein the melting point of the low temperature solder layer is lower than the melting point of the high temperature solder layer, and the material constituting the low temperature solder layer is partly the same as the material constituting the high temperature solder layer , So that the low-temperature solder layer is bonded to the high-
  • the high-temperature solder layer is bonded to the first pad, and a high-strength IMC is formed on the bonding interface, and the low-temperature solder layer and the high-temperature solder layer are bonded through atomic diffusion bonding. No IMC will be formed in the process.
  • the stability of bonding between the first electronic device and the first welding part can be improved, thereby improving the stability of the electronic component.
  • the electronic component further includes at least one second soldering portion; the second soldering portion is arranged on the side of the first soldering portion close to the second pad and is bonded to the second pad; the melting point of the low-temperature solder layer is lower than the first soldering portion The melting point of the second welding part, and the material constituting the low temperature solder layer is partly the same as the material constituting the second welding part, so that the low temperature solder layer is bonded to the second welding part through atomic diffusion.
  • the second soldering part is bonded to the second pad, and a high-strength IMC is formed on the bonding interface, and the low-temperature solder layer and the second soldering part are bonded through atomic diffusion bonding.
  • No IMC will be formed in the process of integration. The stability of the bonding between the second electronic device and the second welding part can be improved, thereby improving the stability of the electronic component.
  • the bonding interface between the high-temperature solder layer and the low-temperature solder layer is a plane; the material constituting the high-temperature solder layer is a simple metal.
  • the high-temperature solder layer can be formed by an electroplating process, and the process is simple.
  • the bonding interface between the high-temperature solder layer and the low-temperature solder layer is a curved surface centered on the side where the first pad is located; the material constituting the high-temperature solder layer is a metal alloy.
  • the material requirements for the high-temperature solder layer are relatively low, and the commonly used high-temperature solders on the market can be used.
  • the orthographic projection of the first pad on the first electronic component is located within the orthographic projection of the second pad on the first electronic component.
  • the facing area of the first pad and the second pad is larger, and the bonding effect is better.
  • the thickness of the low-temperature solder layer is 50-100um.
  • the thickness of the low-temperature solder layer is too thin, it will affect the bonding effect between the low-temperature solder layer and the high-temperature solder layer and the second soldering part.
  • the thickness of the low-temperature solder layer is too thick, it is not conducive to the preparation of solder paste through the steel mesh. .
  • the thickness of the high-temperature solder layer or the second soldering portion is 10-100um.
  • the stress on the first welding part and the second welding part is relatively large at a position within 10um from the first pad and the second pad.
  • the thickness of the first welding part and the second welding part is too large, it is not conducive to the preparation by brushing the solder paste through the steel mesh.
  • the second welding portion is a micro bump provided on the second pad.
  • the electronic components provided in the embodiments of the present application are also suitable for bonding of BGA devices.
  • the electronic component further includes an underfill adhesive layer located between the first electronic component and the second electronic component; the underfill adhesive layer is bonded to the first active surface and the second active surface respectively, and surrounds At the periphery of the first welding part and the second welding part, and adhering to the first welding part and the second welding part.
  • the underfill layer is bonded to the first welding part and the second welding part, and the first welding part and the second welding part can be bonded together.
  • the first welding part and the second welding part can be bonded together.
  • a method for manufacturing an electronic component includes a first electronic component and a second electronic component; the first electronic component has at least one first pad on the first active surface; the second There is at least one second pad on the second active surface of the electronic component, and the second active surface is arranged opposite to the first active surface; the preparation method of the electronic component includes: A high-temperature solder layer bonded to the first pad is formed on the pad; low-temperature solder is placed between the high-temperature solder layer and the second pad; the low-temperature solder is bonded to the high-temperature solder layer and the second pad through atomic diffusion bonding, respectively , Forming a low-temperature solder layer; the bonded high-temperature solder layer and low-temperature solder layer are used as the first soldering part to bond the first electronic component and the second electronic component; wherein the melting point of the low-temperature solder layer is lower than that of the high-temperature solder The melting point of the layer, and the material constitu
  • placing low-temperature solder between the high-temperature solder layer and the second pad includes: placing low-temperature solder on the high-temperature solder layer.
  • placing low-temperature solder between the high-temperature solder layer and the second bonding pad includes: placing low-temperature solder on the second bonding pad.
  • the method for preparing the electronic component further includes: aligning and attaching the first electronic component and the second electronic component , So that the low temperature solder is attached to the high temperature solder layer and the second pad respectively.
  • the method for preparing the electronic component further includes: forming a second pad on each second pad of the second electronic component.
  • the disk is bonded by atomic diffusion, including: bonding the low-temperature solder to the second welding part by atomic diffusion.
  • the material constituting the second welding portion is a metal alloy
  • forming a second welding portion bonded to the second pad on each second pad of the second electronic component includes: A second high-temperature solder is placed on each second pad of the device; the second high-temperature solder is bonded to the second pad to form a second welding part bonded to the second pad.
  • placing low-temperature solder between the high-temperature solder layer and the second bonding pad includes: placing low-temperature solder on the second soldering part.
  • the method for preparing the electronic component further includes: aligning the first electronic component and the second electronic component to make the low-temperature solder separate It is bonded to the high-temperature solder layer and the second soldering part.
  • an electronic device including the electronic component of any one of the first aspects.
  • FIG. 1 is a schematic structural diagram of an electronic device provided by an embodiment of this application.
  • 2a is a schematic structural diagram of an electronic component provided by an embodiment of this application.
  • 2b is a schematic structural diagram of another electronic component provided by an embodiment of the application.
  • Fig. 3a is a schematic cross-sectional view along the A-A' direction in Fig. 2a according to an embodiment of the application;
  • 3b is a schematic diagram of the bonding structure of the first electronic component and the second electronic component in the related art
  • FIG. 4 is a force distribution diagram of a first welding portion of an electronic component provided by an embodiment of the application.
  • FIG. 5 is another schematic cross-sectional view along the A-A' direction in FIG. 2a provided by an embodiment of the application;
  • 6a-6g are schematic diagrams of the size relationship between the first pad and the second pad provided by an embodiment of the application.
  • FIGS. 7a-7f are schematic diagrams of the shape of a first pad provided by an embodiment of the application.
  • FIG. 8a is a flowchart of a bonding process of a first electronic component and a second electronic component provided by an embodiment of the application;
  • 8b is a flowchart of another bonding process of a first electronic component and a second electronic component provided by an embodiment of the application;
  • 9a-9h are schematic diagrams of a bonding process of an electronic component provided by an embodiment of the application.
  • 10a-10c are schematic diagrams of a bonding interface between a high-temperature solder layer and a low-temperature solder layer provided by an embodiment of the application;
  • 11a-11d are schematic diagrams of the side surface of a low-temperature solder layer provided by an embodiment of the application.
  • FIG. 12 is a flowchart of another electronic component bonding process provided by an embodiment of the application.
  • 13a-13d are schematic diagrams of another bonding process of an electronic component provided by an embodiment of the application.
  • FIG. 14 is a force distribution diagram of a first welding part and a second welding part of an electronic component provided by an embodiment of the application;
  • FIG. 15 is another schematic cross-sectional view along the line A-A′ in FIG. 2a according to an embodiment of the application;
  • FIG. 16 is another schematic cross-sectional view along the line A-A′ in FIG. 2a according to an embodiment of the application;
  • FIG. 17a is a flowchart of another electronic component bonding process provided by an embodiment of the application.
  • 17b-17c are schematic diagrams of another electronic component bonding process provided by an embodiment of the application.
  • FIG. 18 is another schematic cross-sectional view along the A-A′ direction in FIG. 2a provided by an embodiment of the application; FIG.
  • Fig. 19 is another schematic cross-sectional view along the A-A' direction in Fig. 2a provided by an embodiment of the application.
  • the embodiment of the present application provides an electronic device.
  • the electronic device can be a terminal device with a display interface such as a mobile phone, a TV, a monitor, a tablet computer, a car computer, or a smart display wearable device such as a smart watch, a smart bracelet, or a communication device such as a server, a memory, and a base station, or For smart cars, etc.
  • the embodiments of the present application do not impose special restrictions on the specific form of the above-mentioned electronic equipment. For the convenience of description, the following embodiments all take the electronic device as a mobile phone as an example for description.
  • the electronic device 1 mainly includes a display module 2, a middle frame 3, a casing (also called a battery cover, a rear casing) 4 and a cover 5.
  • the display module 2 has a light-emitting side where the display screen can be seen and a back surface opposite to the above-mentioned light-emitting side.
  • the back of the display module 2 is close to the middle frame 3, and the cover plate 5 is arranged on the light-emitting side of the display module 2.
  • the above-mentioned display module 2 includes a display panel (DP).
  • the display module 2 is a liquid crystal display module.
  • the above-mentioned display screen is a liquid crystal display (LCD).
  • the display module 2 also includes a backlight unit (BLU) located on the back of the liquid crystal display screen (away from the side surface of the LCD for displaying images).
  • BLU backlight unit
  • the backlight module can provide a light source to the liquid crystal display, so that each sub-pixel in the liquid crystal display can emit light to realize image display.
  • the display module 2 is an organic light emitting diode display module.
  • the above-mentioned display screen is an organic light emitting diode (OLED) display screen. Since each sub-pixel in the OLED display screen is provided with an electroluminescent layer, the OLED display screen can realize self-luminescence after receiving the working voltage. In this case, there is no need to provide the above-mentioned backlight module in the display module 2 with the OLED display screen.
  • the cover plate 5 is located on the side of the display module 2 away from the middle frame 3, and the cover plate 5 may be, for example, cover glass (CG), which may have certain toughness.
  • CG cover glass
  • the middle frame 3 is located between the display module 2 and the housing 4, and the surface of the middle frame 3 away from the display module 2 is used to install internal components such as batteries, printed circuit boards (PCB), cameras, antennas, etc. . After the casing 4 and the middle frame 3 are closed, the above-mentioned internal elements are located between the casing 4 and the middle frame 3.
  • internal components such as batteries, printed circuit boards (PCB), cameras, antennas, etc.
  • the above-mentioned electronic device 1 also includes a main board arranged on the PCB.
  • the PCB is used to carry the main board and is bonded to the main board to realize the control of the main board to the components in the electronic device 1.
  • the motherboard for example, may be a central processing unit (CPU).
  • the bonding stability between the motherboard and the PCB plays a vital role in the performance of the electronic device 1. For example, the bonding position of the motherboard and the PCB is broken, causing the signal of the motherboard and the PCB to be interrupted, thereby causing the electronic device 1 to be damaged.
  • a fingerprint module for fingerprint identification is bonded to a flexible printed circuit (FPC), and FPC is bonded to a PCB to achieve The fingerprint recognition function of the electronic device 1.
  • FPC flexible printed circuit
  • PCB to achieve The fingerprint recognition function of the electronic device 1.
  • SOC system-on-chip
  • SIP system-in-a-package
  • LGA land grid array
  • BGA ball grid array
  • an embodiment of the present application provides an electronic component 100, including: a first electronic component 10 and a second electronic component 20.
  • the first electronic component 10 and the second electronic component 20 may be any component with an electrical signal transmission function in the electronic device 1, for example, may be a connector, an electronic transformer, a relay, a laser device, a PCB, an FPC, Integrated circuits (or chips), packaged devices, biometric identification modules, processors, memories, power modules, etc.
  • the first electronic component 10 is a PCB
  • the second electronic component 20 is a processor.
  • the first electronic component 10 can be bonded with other second electronic components 20 in addition to being bonded to the processor.
  • the shape and size of the first pad 11 bonded to different second electronic components 20 may be different.
  • the processor may be an LGA device, that is, it is bonded to the PCB through a pad.
  • the processor may also be a BGA device, that is, bonded to the PCB through solder balls.
  • the first electronic component 10 and the second electronic component 20 are both die.
  • the size of the first electronic component 10 and the second electronic component 20 are equal, and therefore, the first electronic component 10 and the second electronic component 20 are bonded one to one.
  • the first active surface a of the first electronic component 10 has at least one first pad 11, and the first electronic component 10 is shown in FIG. 3a.
  • the first active surface a has a plurality of first pads 11 as an example for description.
  • the active surface of the electronic component refers to the side where the electronic component is provided with pads and is electrically connected to other devices through the pads to realize signal interaction.
  • the material of the first pad 11 and the second pad 21 is a simple metal such as copper (Cu).
  • the electronic component 100 further includes at least one first soldering portion 30, a first soldering portion 30 is located between a first pad 11 and a second pad 21, and the first soldering portion 30 is The first pad 11 and the second pad 21 on both sides thereof are bonded.
  • Bonding refers to a process in which two homogenous or heterogeneous materials are surface treated and directly combined under certain conditions to achieve electrical or mechanical interconnection between the two materials.
  • the bonding effect can be achieved through a welding process, for example.
  • the number of the first welding portion 30 is related to the number of the first pad 11 and the second pad 21, and each group of the first pad 11 and the second pad 21 disposed oppositely are bonded by a first welding portion 30 .
  • the first soldering portion 30 includes a high temperature solder layer 31 and a low temperature solder layer 32.
  • the high temperature solder layer 31 is disposed close to the first pad 11, and the high temperature solder layer 31 is bonded to the first pad 11.
  • the low-temperature solder layer 32 is disposed close to the second pad 21, and the low-temperature solder layer 32 is bonded to the second pad 21.
  • the bonding process between the low-temperature solder layer 32 and the second pad 21 in a possible embodiment, after the high-temperature solder layer 31 bonded to the first pad 11 is formed on the first pad 11, Low temperature solder is placed on the high temperature solder layer 31. Then, the first electronic component 10 and the second electronic component 20 are aligned and bonded so that the low-temperature solder is located between the high-temperature solder layer 31 and the second pad 21. Finally, the low-temperature solder is bonded to the high-temperature solder layer 31 and the second pad 21 by atomic diffusion bonding to form a low-temperature solder layer 32 that is bonded to the second pad 21 and the high-temperature solder layer 31, respectively. The bonded high-temperature solder layer 31 and low-temperature solder layer 32 serve as the first soldering portion 30 to bond the first electronic component 10 and the second electronic component 20 together.
  • the bonding process of the low temperature solder layer 32 and the second pad 21 in another possible embodiment, after the high temperature solder layer 31 bonded to the first pad 11 is formed on the first pad 11, then Low temperature solder is placed on the second pad 21. Then, the first electronic component 10 and the second electronic component 20 are aligned and bonded so that the low-temperature solder is located between the high-temperature solder layer 31 and the second pad 21. Finally, the low-temperature solder is bonded to the high-temperature solder layer 31 and the second pad 21 by atomic diffusion bonding to form a low-temperature solder layer 32 that is bonded to the second pad 21 and the high-temperature solder layer 31, respectively.
  • the bonded high-temperature solder layer 31 and low-temperature solder layer 32 serve as the aforementioned first soldering portion 30 to bond the first electronic component 10 and the second electronic component 20 together.
  • the difference from the bonding process of the low-temperature solder layer 32 and the second pad 21 in the foregoing embodiment is that the low-temperature solder is placed on the second pad 21.
  • the low-temperature solder layer 32 may be directly contact-bonded with the second pad 21, or may be bonded through other components.
  • the melting point of the low temperature solder layer 32 is lower than the melting point of the high temperature solder layer 31, and the material constituting the low temperature solder layer 32 is partly the same as the material constituting the high temperature solder layer 31, so that the low temperature solder layer 32 is bonded to the high temperature solder layer 31 through atomic diffusion .
  • the melting point of the low-temperature solder layer 32 is lower than that of the high-temperature solder layer 31, but the range of the melting point of the low-temperature solder layer 32 is not limited.
  • the melting point of the low-temperature solder layer 32 can be as low as possible under the condition that the bonding reliability meets the requirements.
  • the material of the high-temperature solder layer 31 may be a metal alloy, and the material of the high-temperature solder layer 31 may also be a simple metal.
  • the material constituting the low-temperature solder layer 32 is the same as the material constituting the high-temperature solder layer 31. It can be understood that when the material of the high-temperature material layer 31 is a metal alloy, the material constituting the low-temperature solder layer 32 is the same as that of the high-temperature solder layer 31. The main material of the material is the same, but the mixed materials are different.
  • the material of the high temperature solder layer 31 is tin alloy.
  • the material of the high-temperature solder layer 31 is the main material tin (Sn) doped with metals such as silver (Ag), antimony (Sb), lead (Pb), and the material of the low-temperature solder layer 32 is the main material tin (Sn) doped with bismuth ( Bi), indium (In), cadmium (Cd) and other metals.
  • the main body material in the material of the high temperature solder layer 31 and the main body material in the material of the low temperature solder layer 32 are the same, and the mixed materials are different.
  • the material constituting the low-temperature solder layer 32 is the same as the material constituting the high-temperature solder layer 31. It can also be understood that when the material of the high-temperature material layer 31 is a simple metal, the material of the low-temperature solder layer 32 is the main material constituting the high-temperature solder layer. The metal element of the material layer 31 is mixed with other metal materials in the main body material.
  • the material of the high temperature solder layer 31 is silver, and the material of the low temperature solder layer 32 is the main material.
  • the silver is mixed with copper, tin, nickel (Ni), zinc (Zn), Boron (B) (e.g. BAg40CuZnSnNi).
  • the coefficient of thermal expansion (CTE) and elastic modulus of the materials of the high-temperature solder layer 31 and the low-temperature solder layer 32 are (modulus) are similar.
  • CTE coefficient of thermal expansion
  • elastic modulus elastic modulus
  • a high-temperature solder layer 31 is provided between the low-temperature solder layer 32 and the first pad 11 to directly bond the high-temperature solder layer 31 and the first pad 11. Since the elongation rate of high-temperature solder is higher than that of low-temperature solder, high-temperature solder is not as brittle as low-temperature solder and is not easy to break. Based on this, the strength of the intermetallic compound (IMC) formed when the high-temperature solder layer 31 is bonded to the first pad 11 is higher than that of the low-temperature solder layer 32 directly bonded to the first pad 11 as shown in FIG. 3b. The strength of the IMC formed in time.
  • IMC intermetallic compound
  • the low-temperature solder layer 32 is partially the same as the material constituting the high-temperature solder layer 31, the low-temperature solder layer 32 and the high-temperature solder layer 31 are bonded through atomic diffusion to achieve the low-temperature solder layer. 32 is bonded to the high temperature solder layer 31. Therefore, the low-temperature solder layer 32 and the high-temperature solder layer 31 will not form an IMC during the bonding process, and the low-temperature solder layer 32 and the high-temperature solder layer 31 have high stability after bonding.
  • a low-strength bond is formed on the bonding interface IMC.
  • the high-temperature solder layer 31 is bonded to the first pad 11
  • a high-strength IMC is formed on the bonding interface
  • the low-temperature solder layer 32 and the high-temperature solder layer 31 are bonded by atomic diffusion bonding , IMC will not be formed during the bonding process.
  • the stability of bonding between the first electronic device 10 and the first welding part 30 can be improved, thereby improving the stability of the electronic assembly 100.
  • the stress analysis shows that when the electronic component 100 is subjected to external forces (such as impact, drop, vibration), the first soldering portion 30 contacts the first pad 11 and the second pad 21.
  • the force at the edge of (the black square in Figure 4) is greater.
  • the high-temperature solder layer 31 is located at a position where the stress is greater. Since the reliability of high-temperature solder is higher than that of low-temperature solder, the structure of the first soldering portion 30 provided by the embodiment of the present application is that the low-temperature solder layer 32 is directly located at a position where the stress is greater than that of FIG. The stability of bonding between the first electronic device 10 and the first welding part 30 can be further improved.
  • the electronic assembly 100 includes: a first electronic component 10, a second electronic component 20, at least one first welding part 30, and at least one second welding part 40.
  • the first active surface a of the first electronic component 10 and the second active surface b of the second electronic component 20 are arranged opposite to each other, and the first pad 11 on the first electronic component 10 is on the first electronic component
  • the orthographic projection on 10 overlaps the orthographic projection of the second pad 21 on the second electronic component 20 on the first electronic component 10.
  • the overlap here may be, as shown in FIG. 5, the first pad 11 and the second pad 21 have the same size and are arranged opposite each other. As shown in FIG. 6a, from the top view, the orthographic projection of the first pad 11 and the orthographic projection of the second pad 21 overlap.
  • the overlap here can also be that, as shown in FIG. 6b, the first pad 11 and the second pad 21 have the same size but are arranged in a staggered position. As shown in FIG. 6c, from the top view, the orthographic projection of the first pad 11 and the orthographic projection of the second pad 21 have an intersection, and the first pad 11 and the second pad 21 have a one-to-one correspondence.
  • the overlap here can also be that, as shown in FIG. 6d, the size of the first pad 11 is smaller than the size of the second pad 21. As shown in FIG. 6e, from the top view, the orthographic projection of the first pad 11 is located within the orthographic projection of the second pad 21.
  • the overlap here can also be that, as shown in FIG. 6f, the size of the first pad 11 is larger than the size of the second pad 21. As shown in FIG. 6g, from the top view, the orthographic projection of the second pad 21 is located within the orthographic projection of the first pad 11.
  • first pad 11 and the second pad 21 are not limited, and they may be closed patterns of any shape.
  • the shape of the first pad 11 and the second pad 21 may be the same or different.
  • the shape of the first pad 11 may be a circle as shown in FIG. 7a, or an ellipse as shown in FIG. 7b, or as shown in FIG.
  • the triangle in 7c is either a rectangle as shown in Fig. 7d, or a square as shown in Fig. 6a, or a regular pattern such as a pentagon as shown in Fig. 7e.
  • the shape of the first pad 11 may be an irregular pattern as shown in FIG. 7f.
  • a first soldering portion 30 and a second soldering portion 40 are provided between the correspondingly provided first pad 11 and the second soldering pad 21.
  • the second welding part 40 is arranged close to the second pad 21.
  • the first soldering part 30 includes a high temperature solder layer 31 and a low temperature solder layer 32.
  • the high-temperature solder layer 31 is disposed close to the first pad 11 and is bonded to the first pad 11.
  • the low-temperature solder layer 32 is disposed close to the second welding part 40 and is bonded to the second welding part 40.
  • the second welding part 40 is also bonded to the second pad 21.
  • the melting point of the low-temperature solder layer 32 is lower than the melting point of the high-temperature solder layer 31 and the second soldering portion 40.
  • the material constituting the low-temperature solder layer is partly the same as the material constituting the high-temperature solder layer 31 so that the low-temperature solder layer 32 is bonded to the high-temperature solder layer 31 by atomic diffusion.
  • the material constituting the low-temperature solder layer is partly the same as the material constituting the second solder portion 40, so that the low-temperature solder layer 32 is bonded to the second solder portion 40 through atomic diffusion.
  • the material constituting the high-temperature solder layer 31 and the material constituting the second solder portion 40 may be the same or different.
  • the process of preparing the high-temperature solder layer 31 is different according to the material selection of the high-temperature solder layer 31, and the bonding process of the high-temperature solder layer 31 and the first pad 11 is also different.
  • the combination of the high-temperature solder layer 31 and the low-temperature solder layer 32 is also different.
  • the shape of the welding interface is also different.
  • different materials will form different second welding parts 40.
  • the bonding process of the first electronic component 10 and the second electronic component 20 will be exemplified according to the material selection of the high-temperature solder layer 31 and the second soldering part 40.
  • the material of the high-temperature solder layer 31 and the second welding portion 40 is a metal alloy.
  • the bonding process of the first electronic component 10 and the second electronic component 20 is as follows:
  • a first high temperature solder G1 is placed on each first pad 11 of the first electronic component 10.
  • a steel mesh 50 is placed on the first electronic component 10, the opening 51 of the steel mesh 50 corresponds to the first pad 11, and the shielding portion 52 of the steel mesh 50 corresponds to the part between the adjacent first pads 11. . Then, the solder paste is applied to fill the opening 51 of the steel mesh 50 with the solder paste. Subsequently, the steel mesh 50 is removed to form the first high temperature solder G1 on the first pad 11.
  • step S11 is executed after step S10 is executed.
  • a reflow process is used to bond the first high temperature solder G1 to the first pad 11 to form the first high temperature that is bonded to the first pad 11 The solder layer 31.
  • the body material of the first high temperature solder G1 is different from the material of the first pad 11, for example, the body material of the first high temperature solder G1 is tin, the material of the first pad 11 is copper, and the first high temperature solder G1 An IMC is formed at the bonding interface with the first pad 11.
  • a second high temperature solder G2 is placed on each second pad 21 of the second electronic component 20.
  • the method of placing the second high temperature solder G2 on the second pad 21 may be the same as the method of placing the first high temperature solder G1 on the first pad 11, and step S10 may be referred to.
  • step S13 As shown in FIG. 9d, the second high temperature solder G2 is bonded to the second pad 21 to form the second soldering portion 40. As shown in Figure 8a, step S13 is executed after step S12 is executed.
  • the method of bonding the second high temperature solder G2 to the second pad 21 to form the second soldering portion 40 bonded to the second pad 21 may be the same as bonding the first high temperature solder G1 to the first pad 11
  • the method is the same, and you can refer to step S11.
  • steps S10 and S12 there is no sequence between steps S10 and S12 above. These two steps can be executed simultaneously within the same time period, or step S10 can be executed before step S12 is executed, or step S12 can be executed after step S10 is executed. Step S10 is executed after S12.
  • step S14 As shown in FIG. 9e, a low-temperature solder D is placed on the high-temperature solder layer 31. As shown in Figure 8a, step S14 is executed after step S11 is executed.
  • the method of placing the low-temperature solder D on the high-temperature solder layer 31 may be the same as the method of placing the first high-temperature solder G1 on the first pad 11 in step S10.
  • step S14' as shown in FIG. 9f, a low temperature solder D is formed on the second soldering portion 40. As shown in Figure 8b, step S14' is executed after step S13 is executed.
  • the first electronic component 10 and the second electronic component 20 are aligned and bonded.
  • the low-temperature solder D is bonded to the high-temperature solder layer 31 and the second solder portion 40, respectively.
  • step S14 a low-temperature solder D is placed on the high-temperature solder layer 31.
  • the first electronic component 10 and the second electronic component 20 are aligned and bonded, the first electronic component 10 is placed in the forward direction, and the second electronic component 20 is aligned with the first electronic component from above.
  • the device 10 is aligned and attached.
  • step S14' a low-temperature solder D is placed on the second soldering part 40.
  • the second electronic component 20 is placed in the forward direction, and the first electronic component 10 is connected to the second electronic component from above.
  • the device 20 is aligned and attached.
  • the low temperature solder D is located between the high temperature solder layer 31 and the second soldering portion 40 after the step S15 is performed.
  • the low temperature solder D Since the low temperature solder D is placed on the high temperature solder layer 31, it is not bonded to it. Therefore, taking the structure shown in FIG. 9h as an example, the second electronic component 20 with low-temperature solder D is used as a reference, and the first electronic component 10 without low-temperature solder D is placed from above and covered with the first electronic component 10 Two electronic components 20 are aligned and attached.
  • the low-temperature solder D can be prevented from being separated from the second solder 40 due to gravity, and the reliability of the bonding can be guaranteed.
  • the low-temperature solder D is bonded to the high-temperature solder layer 31 and the second solder portion 40 through atomic diffusion bonding, respectively, to form the low-temperature solder layer 32.
  • the bonded high-temperature solder layer 32 and low-temperature solder layer 31 serve as the first soldering portion 30, and the first soldering portion 30 and the second soldering portion 40 are bonded by atomic diffusion bonding, so that the first electronic component 10 and the second Two electronic components 20 are bonded.
  • the heating temperature is low when the low-temperature solder D is bonded to the high-temperature solder layer 31 and the second soldering portion 40
  • the first electronic component 10 and the second electronic component 20 are bonded with high-temperature solder, under a high-temperature environment, the first electronic component 10 and the second electronic component 20 Each will have different degrees of thermal deformation. However, since the first electronic component 10 and the second electronic component 20 are bonded together, the first electronic component 10 and the second electronic component 20 will be subjected to deformation pulling force from each other, resulting in the first electronic component 10 And the second electronic component 20 is warped and deformed.
  • the first high temperature solder G1 and the first pad 11 are bonded at a high temperature
  • the second high temperature solder G2 and the second pad 21 are also bonded at a high temperature.
  • the first high temperature solder G1 and the first pad 11 since the first high temperature solder G1 is bonded to the first pad 11, it is bonded on the surface of the first electronic component 10. There will be thermal deformation, which is within the bearing range of the first electronic component 10 and will not be subjected to the force of the second electronic component 20, so the probability of warping deformation is significantly reduced.
  • a high-temperature solder layer 31 may be formed on the first pad 11 first. After that, parts or films that are not resistant to high temperatures are formed.
  • the high-temperature solder layer 31 may be formed on the first pad 11 before the optical film is formed.
  • the second soldering part 40 and the first soldering part 30 may become different.
  • the shape of the bonding interface and the shape of the bonding interface between the high-temperature solder layer 31 and the low-temperature solder layer 32 in the first soldering portion 30 may have various forms. Therefore, in the embodiment of the present application, the first soldering portion 30 and the second soldering portion 30 are not combined.
  • the shape of the longitudinal section of the welding portion 40 and the shape of the bonding interface are defined.
  • the bonding interface between the second solder portion 40 and the low-temperature solder layer 32 has the same formation principle as the bonding interface between the high-temperature solder layer 31 and the low-temperature solder layer 32 in the first solder portion 30.
  • the shape of the bonding interface between the high temperature solder layer 31 and the low temperature solder layer 32 is taken as an example for illustration. It is understandable that since the high temperature solder layer 31 and the low temperature solder layer 32 are bonded by atomic diffusion, the shape of the bonding interface between the high temperature solder layer 31 and the low temperature solder layer 32 is the high temperature solder layer 31 and the first solder layer.
  • the high-temperature solder layer 31 and the first pad 11 are bonded through a soldering process.
  • the bonding interface c of 32 is a curved surface with a center recessed toward the side where the first pad 11 is located.
  • the high-temperature solder layer 31 and the first pad 11 are bonded through other processes.
  • the high-temperature solder layer 31 and the low-temperature solder layer 32 are bonded together.
  • the bonding interface c is a curved surface with a center that is convex away from the side where the first pad 11 is located.
  • the bonding interface c between the high temperature solder layer 31 and the low temperature solder layer 32 is a plane parallel to the first pad 11.
  • the shape of the side surface d of the low-temperature solder layer 32 intersecting the bonding interface c may also have various shapes.
  • the cross section of the low-temperature solder layer 32 in the direction (longitudinal) perpendicular to the first electronic component 10 may have various forms. Therefore, in the embodiment of the present application, the shape of the side surface d of the low-temperature solder layer 32 is not limited.
  • the side surface d of the low-temperature solder layer 32 is flat.
  • the angle between the side surface d of the low-temperature solder layer 32 and the first pad 11 is different.
  • the side surface d of the low-temperature solder layer 32 is a plane perpendicular to the first pad 11.
  • the side surface d of the low-temperature solder layer 32 is a plane whose angle with the first pad 11 is greater than 90°.
  • the side surface d of the low temperature solder layer 32 is a plane with an angle less than 90° with the first pad 11.
  • the side surface d of the low-temperature solder layer 32 is a curved surface that is recessed inward.
  • the side surface d of the low-temperature solder layer 32 is a convex curved surface.
  • the material of the high-temperature solder layer 31 is simple metal. As shown in FIG. 12, the bonding process of the first electronic component 10 and the second electronic component 20 is as follows:
  • a high-temperature solder layer 31 bonded to the first pad 11 is formed on the first pad 11 of the first electronic component 10 through an electroplating process.
  • the surface of the high-temperature solder layer 31 formed by the electroplating process away from the first pad 11 is a plane parallel to the first pad 11.
  • a second soldering portion 40 bonded to the second pad 21 is formed on the second pad 21 of the second electronic component 20 through an electroplating process.
  • the surface of the second welding portion 40 formed by the electroplating process away from the second pad 21 is a plane parallel to the second pad 21.
  • FIG. 13c takes the low-temperature solder D placed on the high-temperature solder layer 31 as an example for illustration.
  • the method of placing the low-temperature solder D on the high-temperature solder layer 31 or the second soldering portion 40 may be the same as the method of placing the first high-temperature solder G1 on the first pad 11 in step S10.
  • the low-temperature solder D is bonded to the high-temperature solder layer 31 and the second solder portion 40 through atomic diffusion bonding, respectively, to form a low-temperature solder layer 32.
  • the bonded high-temperature solder layer 31 and low-temperature solder layer 32 serve as the first soldering portion 30, and the first soldering portion 30 and the second soldering portion 40 are bonded by atomic diffusion bonding, so that the first electronic component 10 and the second electronic component The device 20 is bonded.
  • the bonding interface c between the high temperature solder layer 31 and the low temperature solder layer 32 is parallel to the first pad 11. Plane.
  • the bonding interface between the second soldering portion 40 and the low-temperature solder layer 32 is also a plane parallel to the first pad 11.
  • the edge position of the contact surface between the first soldering portion 30 and the first pad 11 and the second receives a relatively large force, which is a stress concentration area, and the middle area is a low stress area. Since the brittleness of high-temperature solder is less than that of low-temperature solder, the reliability of high-temperature solder is higher than that of low-temperature solder.
  • the high temperature solder layer 31 is located in the stress concentration area, avoiding the low temperature solder layer 32 being disposed in the stress concentration area to improve the first electronic component 10 and the second The stability of the bonding of electronic components 20.
  • the stress on the first soldering portion 30 and the second soldering portion 40 is relatively large at a position within 10 um from the first pad 11 and the second pad 21.
  • the thickness of the first welding part 30 and the second welding part 40 is too large, it is not conducive to the method of applying solder paste to the steel mesh.
  • the thickness of the high-temperature solder layer 31 and the second welding portion 40 is 10-100 um.
  • the thickness of the high temperature solder layer 31 and the second welding portion 40 is 20um, 30um, 40um, 50um, 60um, 70um, 80um, 90um.
  • the thickness of the component in the embodiment of the present application refers to the dimension of the component in a direction perpendicular to the first pad.
  • the thickness of the low-temperature solder layer 32 is 50-100 um.
  • the thickness of the low-temperature solder layer 32 is 60 um, 70 um, 80 um, and 90 um.
  • the force of the first soldering portion 30 and the second soldering portion 40 in the stress concentration area shown in FIG. 14 is about 40% greater than that of low stress.
  • the stress borne by the low-temperature solder layer 32 can be reduced by about 40%.
  • the electronic component further includes a first electronic component 10 and a second electronic component 20
  • An underfill 60 is provided.
  • the underfill layer 60 is adhered to the first active surface a of the first electronic component 10 and the second active surface b of the second electronic component 20 respectively, and the underfill layer 60 surrounds the first soldering portion 30 And the outer periphery of the second welding part 40, and adhere to the first welding part 30 and the second welding part 40.
  • the material of the underfill adhesive layer 60 may be a thermosetting adhesive.
  • the underfill layer 60 between the first electronic component 10 and the second electronic component 20 by filling the underfill layer 60 between the first electronic component 10 and the second electronic component 20, and the underfill layer 60 is bonded to the first soldering portion 30 and the second soldering portion 40,
  • the first welding part 30 and the second welding part 40 play a role of protection and stabilization, so as to further improve the bonding stability of the first electronic component 10 and the second electronic component 20.
  • the first soldering portion 30 and the second soldering portion 40 are composed of three layers of solder, and the thickness of the three layers of solder is not too thin, so that the first electronic component 10 and the second electronic component The gap between the devices 20 is relatively large. In this way, when the underfill adhesive layer 60 is formed, the resistance of the adhesive is small, and the fluidity of the adhesive is better. It can be ensured that the glue completely covers each solder joint formed by the first soldering portion 30 and the second soldering portion 40, thereby further improving the bonding stability of the first electronic component 10 and the second electronic component 20.
  • the second embodiment is different from the first embodiment in that: the first electronic component 10 is a PCB, and the second electronic component 20 is a BGA device.
  • the second soldering portion 40 is a micro bump provided on the second pad 21.
  • the second soldering portion 40 is a component of the second electronic component 20, and there is no step of forming the second soldering portion 40 when the first electronic component 10 and the second electronic component 20 are bonded.
  • micro bumps may be balls, bumps, etc.
  • the embodiment of the present application takes the second welding portion 40 as a solder ball as an example for illustration.
  • the bonding process of the first electronic component 10 and the second electronic component 20 is as follows:
  • step S30 may include: as shown in FIG. 9a, placing a first high temperature solder G1 on each first pad 11 of the first electronic component 10. As shown in FIG. 9b, the first high temperature solder G1 is bonded to the first pad 11 to form a high temperature solder layer 31.
  • step S30 may include: as shown in FIG. 13a, forming a high-temperature solder layer 31 bonded to the first pad 11 on the first pad 11 of the first electronic component 10 through an electroplating process.
  • a low-temperature solder D is placed on the high-temperature solder layer 31.
  • the low-temperature solder D is bonded to the high-temperature solder layer 31 and the second solder portion 40 through atomic diffusion bonding, respectively, to form a low-temperature solder layer 32 .
  • the first electronic component 10 and the second electronic component 20 are bonded.
  • the electronic component On the basis of the structure of the electronic component shown in FIG. 16, as shown in FIG. 19 (a cross-sectional view along the AA′ direction in FIG. 2a), the electronic component also includes a first electronic component 10 and a second electronic component 20. Between the underfill layer 60.
  • the underfill layer 60 is bonded to the first active surface a of the first electronic component 10 and the second active surface b of the second electronic component 20, respectively, and surrounds the first soldering portion 30 and the second soldering portion 40 and adhere to the first welding part 30 and the second welding part 40.

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Abstract

本申请提供一种电子组件及电子设备，涉及电子技术领域，用于解决电子元器件之间键合稳定性较低的问题。电子组件，包括：第一电子元器件，其第一有源面上具有至少一个第一焊盘；第二电子元器件，其第二有源面上具有至少一个第二焊盘，第二有源面与第一有源面相对设置；至少一个第一焊接部，一个第一焊接部位于一个第一焊盘和一个第二焊盘之间，且第一焊接部与位于其两侧的第一焊盘和第二焊盘键合；第一焊接部包括高温焊料层和低温焊料层；高温焊料层靠近第一焊盘设置，且与第一焊盘键合；低温焊料层靠近第二焊盘设置，且与第二焊盘键合；其中，低温焊料层的熔点低于高温焊料层的熔点，且构成低温焊料层的材料与构成高温焊料层的材料部分相同。

Description

电子组件及电子设备
本申请要求于2019年08月30日提交国家知识产权局、申请号为201910817423.5、申请名称为“电子组件及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子技术领域，尤其涉及一种电子组件及电子设备。
背景技术
随着电子技术的发展，电子设备不断向小型化、集成化、超薄化趋势发展，因此，对电子设备中的电子元器件键合工艺的要求越来越高。而电子设备中的电子元器件之间的键合效果，对电子设备的性能起到至关重要的作用。
在两个电子元器件键合时，如果采用熔融温度较高的高温焊料键合，会导致电子元器件翘曲或改变电子元器件性能，从而影响电子组件的可靠性。而如果采用键合温度较低的低温焊料键合，由于低温焊料脆性大，延展率低，使得低温焊料与电子元器件上的焊盘会形成强度较低的介面合金共化物(intermetallic compound，IMC)，导致电子元器件之间键合的可靠性较低。
因此，如何在不影响电子元器件性能的基础上，提高电子元器件之间键合的稳定性，成为本领域技术人员急需解决的技术问题。
发明内容
本申请实施例提供一种电子组件及电子设备，用于解决电子元器件之间键合稳定性较低的问题。
为达到上述目的，本实施例采用如下技术方案：
第一方面，提供一种电子组件，包括:第一电子元器件，其第一有源面上具有至少一个第一焊盘；第二电子元器件，其第二有源面上具有至少一个第二焊盘，第二有源面与第一有源面相对设置；至少一个第一焊接部，一个第一焊接部位于一个第一焊盘和一个第二焊盘之间，且第一焊接部与位于其两侧的第一焊盘和第二焊盘键合；第一焊接部包括高温焊料层和低温焊料层；高温焊料层靠近第一焊盘设置，且与第一焊盘键合；低温焊料层靠近第二焊盘设置，且与第二焊盘键合；其中，低温焊料层的熔点低于高温焊料层的熔点，且构成低温焊料层的材料与构成高温焊料层的材料部分相同，以使得低温焊料层通过原子扩散与高温焊料层键合。本申请实施例提供的电子组件中，高温焊料层与第一焊盘键合，键合界面上形成强度较高的IMC，并且低温焊料层和高温焊料层通过原子扩散键合，在键合的过程中不会形成IMC。可提高第一电子器件与第一焊接部键合的稳定性，从而提高电子组件的稳定性。
可选的，电子组件还包括至少一个第二焊接部；第二焊接部设置在第一焊接部靠近第二焊盘一侧，且与第二焊盘键合；低温焊料层的熔点低于第二焊接部的熔点，且构成低温焊料层的材料与构成第二焊接部的材料部分相同，以使得低温焊料层通过原 子扩散与第二焊接部键合。本申请实施例提供的电子组件中，第二焊接部与第二焊盘键合，键合界面上形成强度较高的IMC，并且低温焊料层和第二焊接部通过原子扩散键合，在键合的过程中不会形成IMC。可提高第二电子器件与第二焊接部键合的稳定性，从而提高电子组件的稳定性。
可选的，高温焊料层与低温焊料层的键合界面为平面；构成高温焊料层的材料为金属单质。可通过电镀工艺形成高温焊料层，工艺简单。
可选的，高温焊料层与低温焊料层的键合界面为中心向第一焊盘所在侧凹陷的曲面；构成高温焊料层的材料为金属合金。对高温焊料层的材料要求较低，可以使市面上常用的高温焊料。
可选的，第一焊盘在第一电子元器件上的正投影位于第二焊盘在第一电子元器件上的正投影内。这种结构下，第一焊盘和第二焊盘的正对面积较大，键合效果较好。
可选的，沿垂直于第一焊盘的方向，低温焊料层的厚度为50-100um。低温焊料层的厚度太薄时，会影响低温焊料层与高温焊料层和第二焊接部的键合效果，而低温焊料层的厚度太厚时，不利于通过钢网涂刷焊膏的方式制备。
可选的，沿垂直于第一焊盘的方向，高温焊料层或第二焊接部的厚度为10-100um。通过对电子组件进行跌落仿真分析，在距离第一焊盘和第二焊盘在10um以内的位置处，第一焊接部和第二焊接部受到的应力比较大。而第一焊接部和第二焊接部的厚度太大时，不利于通过钢网涂刷焊膏的方式制备。
可选的，第二焊接部为设置在第二焊盘上的微凸点。本申请实施例提供的电子组件也适用于BGA器件的键合。
可选的，电子组件还包括位于第一电子元器件和第二电子元器件之间的底部填充胶层；底部填充胶层与第一有源面和第二有源面分别粘接，且围绕在第一焊接部和第二焊接部的外围，并与第一焊接部和第二焊接部粘接。通过在第一电子元器件和第二电子元器件之间填充底部填充胶层，底部填充胶层与第一焊接部和第二焊接部粘接，可以对第一焊接部和第二焊接部起到保护和稳固作用，以进一步提高第一电子元器件和第二电子元器件键合的稳定性。
第二方面，提供一种电子组件的制备方法，电子组件包括第一电子元器件和第二电子元器件；第一电子元器件的第一有源面上具有至少一个第一焊盘；第二电子元器件的第二有源面上具有至少一个第二焊盘，第二有源面与第一有源面相对设置；电子组件的制备方法包括：在第一电子元器件的每一第一焊盘上形成与第一焊盘键合的高温焊料层；在高温焊料层与第二焊盘之间放置低温焊料；将低温焊料，与高温焊料层和第二焊盘分别通过原子扩散键合，形成低温焊料层；键合后的高温焊料层和低温焊料层作为第一焊接部，以使第一电子元器件和第二电子元器件键合；其中，低温焊料层的熔点低于高温焊料层的熔点，且构成低温焊料层的材料与构成高温焊料层的材料部分相同。
可选的，构成高温焊料层的材料为金属合金；在第一电子元器件的每一第一焊盘上形成与第一焊盘键合的高温焊料层，包括：在第一电子元器件的每一第一焊盘上放置第一高温焊料；将第一高温焊料与第一焊盘键合，以形成与第一焊盘键合的高温焊料层。
可选的，构成高温焊料层的材料为金属单质；在第一电子元器件的每一第一焊盘上形成与第一焊盘键合的高温焊料层，包括：通过电镀工艺，在第一电子元器件的第一焊盘上形成与第一焊盘键合的高温焊料层。可选的，在高温焊料层与第二焊盘之间放置低温焊料，包括：在高温焊料层上放置低温焊料。
可选的，在高温焊料层与第二焊盘之间放置低温焊料，包括：在第二焊盘上放置低温焊料。
可选的，在将低温焊料，与高温焊料层和第二焊盘分别通过原子扩散键合之前，电子组件的制备方法还包括：将第一电子元器件和第二电子元器件对位贴合，以使低温焊料分别与高温焊料层和第二焊盘贴合。
可选的，将低温焊料，与高温焊料层和第二焊盘分别通过原子扩散键合之前，电子组件的制备方法还包括：在第二电子元器件的每一第二焊盘上形成与第二焊盘键合的第二焊接部；低温焊料层的熔点低于第二焊接部的熔点，且构成低温焊料层的材料与构成第二焊接部的材料部分相同；将低温焊料与第二焊盘通过原子扩散键合，包括：将低温焊料与第二焊接部通过原子扩散键合。
可选的，构成第二焊接部的材料为金属合金；在第二电子元器件的每一第二焊盘上形成与第二焊盘键合的第二焊接部，包括：在第二电子元器件的每一第二焊盘上放置第二高温焊料；将第二高温焊料与第二焊盘键合，以形成与第二焊盘键合的第二焊接部。
可选的，构成第二焊接部的材料为金属单质；在第二电子元器件的每一第二焊盘上形成与第二焊盘键合的第二焊接部，包括：通过电镀工艺，在第二电子元器件的第二焊盘上形成与第二焊盘键合的第二焊接部。
可选的，在高温焊料层与第二焊盘之间放置低温焊料，包括：在第二焊接部上放置低温焊料。
可选的，在将低温焊料与第二焊接部通过原子扩散键合之前，电子组件的制备方法还包括：将第一电子元器件和第二电子元器件对位贴合，以使低温焊料分别与高温焊料层和第二焊接部贴合。
第三方面，提供一种电子设备，包括第一方面任一项的电子组件。
附图说明
图1为本申请实施例提供的一种电子设备的结构示意图；
图2a为本申请实施例提供的一种电子组件的结构示意图；
图2b为本申请实施例提供的另一种电子组件的结构示意图；
图3a为本申请实施例提供的一种沿图2a中A-A′向的剖视示意图；
图3b为相关技术中第一电子元器件和第二电子元器件的键合结构示意图；
图4为本申请实施例提供的一种电子组件的第一焊接部的受力分布图；
图5为本申请实施例提供的另一种沿图2a中A-A′向的剖视示意图；
图6a-图6g为本申请实施例提供的第一焊盘和第二焊盘的大小关系示意图；
图7a-图7f为本申请实施例提供的一种第一焊盘的形状示意图；
图8a为本申请实施例提供的一种第一电子元器件和第二电子元器件的键合过程的流程图；
图8b为本申请实施例提供的另一种第一电子元器件和第二电子元器件的键合过程的流程图；
图9a-图9h为本申请实施例提供的一种电子组件的键合过程的示意图；
图10a-图10c为本申请实施例提供的一种高温焊料层与低温焊料层的键合界面的示意图；
图11a-图11d为本申请实施例提供的一种低温焊料层的侧面的示意图；
图12为本申请实施例提供的另一种电子组件的键合过程的流程图；
图13a-图13d为本申请实施例提供的另一种电子组件的键合过程的示意图；
图14为本申请实施例提供的一种电子组件的第一焊接部和第二焊接部的受力分布图；
图15为本申请实施例提供的又一种沿图2a中A-A′向的剖视示意图；
图16为本申请实施例提供的又一种沿图2a中A-A′向的剖视示意图；
图17a为本申请实施例提供的又一种电子组件的键合过程的流程图；
图17b-图17c为本申请实施例提供的又一种电子组件的键合过程的示意图；
图18为本申请实施例提供的又一种沿图2a中A-A′向的剖视示意图；
图19为本申请实施例提供的又一种沿图2a中A-A′向的剖视示意图。
附图标记：
1-电子设备；2-显示模组；3-中框；4-壳体；5-盖板；100-电子组件；10-第一电子元器件；11-第一焊盘；20-第二电子元器件；21-第二焊盘；30-第一焊接部；31-高温焊料层；32-低温焊料层；40-第二焊接部；G1-第一高温焊料，G2-第二高温焊料；D-低温焊料；50-钢网；51-开口部；52-遮挡部；60-底部填充胶层。
具体实施方式
除非另作定义，本申请使用的技术术语或者科学术语应当为本领域技术人员所理解的通常意义。本申请说明书以及权利要求书中使用的术语“第一”、“第二”、“第三”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。由此，限定有“第一”、“第二”、“第三”的特征可以明示或者隐含地包括一个或者更多个该特征。在本申请实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
“左”、“右”、“上”以及“下”等方位术语是相对于附图中的部件示意放置的方位来定义的，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据部件所放置的方位的变化而相应地发生变化。
本申请实施例提供一种电子设备。该电子设备可以为手机、电视、显示器、平板电脑、车载电脑等具有显示界面的终端设备，或者为智能手表、智能手环等智能显示穿戴设备，或者为服务器、存储器、基站等通信设备，或者为智能汽车等。本申请实施例对上述电子设备的具体形式不做特殊限制。以下实施例为了方便说明，均是以电子设备为手机为例进行举例说明。
在此情况下，如图1所示，电子设备1主要包括显示模组2、中框3、壳体(或者称为电池盖、后壳)4以及盖板5。
显示模组2具有能够看到显示画面的出光侧和与上述出光侧相对设置的背面，显 示模组2的背面靠近中框3，盖板5设置在显示模组2的出光侧。
上述显示模组2，包括显示屏(display panel，DP)。
在本申请的一种可能的实施例中，显示模组2为液晶显示模组。在此情况下，上述显示屏为液晶显示屏(liquid crystal display，LCD)。基于此，显示模组2还包括位于液晶显示屏背面(远离LCD用于显示画面的一侧表面)的背光模组(back light unit，BLU)。
背光模组可以向液晶显示屏提供光源，以使得液晶显示屏中的各个亚像素(sub pixel)能够发光以实现图像显示。
或者，在本申请的另一种可能的实施例中，显示模组2为有机发光二极管显示模组。在此情况下，上述显示屏为有机发光二极管(organic light emitting diode，OLED)显示屏。由于OLED显示屏中每个亚像素内设置有电致发光层，所以可以使得OLED显示屏在接收到工作电压后，实现自发光。在此情况下，具有OLED显示屏的显示模组2中无需再设置上述背光模组。
盖板5位于显示模组2远离中框3一侧，盖板5例如可以是盖板玻璃(cover glass，CG)，该盖板玻璃可以具有一定的韧性。
中框3位于显示模组2和壳体4之间，中框3远离显示模组2的表面用于安装电池、印刷电路板(printed circuit board，PCB)、摄像头(camera)、天线等内部元件。壳体4与中框3盖合后，上述内部元件位于壳体4与中框3之间。
上述电子设备1还包括设置于PCB上的主板，PCB用于承载主板，并于主板键合，以实现主板对电子设备1中各部件的控制。主板，例如可以是中央处理器(central processing unit，CPU)。主板与PCB的键合稳定性，对电子设备1的性能起到至关重要的作用，例如主板与PCB键合位置处断裂，导致主板与PCB信号中断，从而导致电子设备1损坏。
当然，电子设备1中有多种电子元器件之间键合的地方，例如用于指纹识别的指纹模组与柔性电路板(flexible printed circuit，FPC)键合，FPC与PCB键合，以实现电子设备1的指纹识别功能。或者，例如，系统级芯片(system on chip，SOC)中的多种功能的芯片之间的键合，以完成系统级封装(system in a package，SIP)。或者，例如，SOC与PCB的键合、电源模块与PCB的键合、封装器件与PCB的键合等等。
其中，根据电子元器件中用于与其他器件键合的结构的不同，可将电子元器件分为栅格阵列封装(land grid array，LGA)器件和焊球阵列封装(ball grid array，BGA)器件。LGA器件通过焊盘与其他器件键合，BGA器件通过焊球与其他器件键合。
基于此，为了提高电子设备1中电子元器件之间的键合稳定性，从而保证电子设备1的性能。如图2a所示，本申请实施例提供一种电子组件100，包括:第一电子元器件10和第二电子元器件20。
此处，第一电子元器件10和第二电子元器件20可以是电子设备1中任意具有电信号传导功能的部件，例如，可以为连接器、电子变压器、继电器、激光器件、PCB、FPC、集成电路(或称为芯片)、封装器件、生物特征识别模组、处理器、存储器、电源模块等。
在一种可能的实施例中，如图2a所示，例如第一电子元器件10为PCB，第二电 子元器件20为处理器。在这种情况下，由于PCB的面积比较大，因此，第一电子元器件10除了可以与处理器键合外，还可以与其他第二电子元器件20键合。当然，与不同第二电子元器件20键合的第一焊盘11的形状和大小可以不同。其中，处理器可以是LGA器件，即，通过焊盘与PCB键合。处理器也可以是BGA器件，即，通过焊球与PCB键合。
在另一种可能的实施例中，如图2b所示，例如第一电子元器件10和第二电子元器件20均为裸芯片(die)。在这种情况下，第一电子元器件10和第二电子元器件20的大小相等，因此，第一电子元器件10和第二电子元器件20一对一键合。
如图3a(沿图2a中A-A′向的剖视图)所示，第一电子元器件10的第一有源面a上具有至少一个第一焊盘11，图3a中以第一电子元器件10的第一有源面a上具有多个第一焊盘11为例进行说明。
其中，电子元器件的有源面是指电子元器件设置有焊盘，且通过焊盘与其他器件电连接，以实现信号交互的一面。
第二电子元器件20的第二有源面b上具有至少一个第二焊盘21，第二电子元器件20的第二有源面b与第一电子元器件10的第一有源面a相对设置。
示例的，第一焊盘11和第二焊盘21的材料为铜(Cu)等金属单质。
如图3a所示，电子组件100还包括至少一个第一焊接部30，一个第一焊接部30位于一个第一焊盘11和一个第二焊盘21之间，且第一焊接部30与位于其两侧的第一焊盘11和第二焊盘21键合(bonding)。
键合，是指将两种同质或者异质材料结果表面处理，在一定条件下直接结合，使两者材料实现电学或机械互连的一种工艺。本申请实施例中，例如可以通过焊接工艺达到键合效果。第一焊接部30的数量，与第一焊盘11和第二焊盘21的数量相关，每一组相对设置的第一焊盘11和第二焊盘21通过一个第一焊接部30键合。
如图3a所示，第一焊接部30包括高温焊料层31和低温焊料层32。高温焊料层31靠近第一焊盘11设置，且高温焊料层31与第一焊盘11键合。低温焊料层32靠近第二焊盘21设置，且低温焊料层32与第二焊盘21键合。
关于低温焊料层32与第二焊盘21的键合过程，在一种可能的实施例中，在第一焊盘11上形成与第一焊盘11键合的高温焊料层31后，再在高温焊料层31上放置低温焊料。然后，将第一电子元器件10和第二电子元器件20对位贴合，以使低温焊料位于高温焊料层31与第二焊盘21之间。最后，将低温焊料，与高温焊料层31和第二焊盘21分别通过原子扩散键合，形成分别与第二焊盘21和高温焊料层31键合的低温焊料层32。键合后的高温焊料层31和低温焊料层32作为上述第一焊接部30，以使第一电子元器件10和第二电子元器件20键合。
关于低温焊料层32与第二焊盘21的键合过程，在另一种可能的实施例中，在第一焊盘11上形成与第一焊盘11键合的高温焊料层31后，再在第二焊盘21上放置低温焊料。然后，将第一电子元器件10和第二电子元器件20对位贴合，以使低温焊料位于高温焊料层31与第二焊盘21之间。最后，将低温焊料，与高温焊料层31和第二焊盘21分别通过原子扩散键合，形成分别与第二焊盘21和高温焊料层31键合的低温焊料层32。键合后的高温焊料层31和低温焊料层32作为上述第一焊接部30，以使第 一电子元器件10和第二电子元器件20键合。与前述实施例中低温焊料层32与第二焊盘21的键合过程，不同之处在于低温焊料放置在第二焊盘21上。
其中，低温焊料层32可以与第二焊盘21直接接触键合，也可以通过其他部件键合。
低温焊料层32的熔点低于高温焊料层31的熔点，且构成低温焊料层32的材料与构成高温焊料层31的材料部分相同，以使得低温焊料层32通过原子扩散与高温焊料层31键合。
本申请实施例中低温焊料层32的熔点相对于高温焊料层31的熔点较低，但对于低温焊料层32的熔点的范围，不做限定。在选取低温焊料层32的材料时，保证键合可靠性满足要求的情况下，使低温焊料层32的熔点尽可能的低即可。
其中，高温焊料层31的材料可以是金属合金，高温焊料层31的材料也可以是金属单质。
构成低温焊料层32的材料与构成高温焊料层31的材料部分相同，可以理解为，在高温材料层31的材料为金属合金的情况下，构成低温焊料层32的材料与构成高温焊料层31的材料的主体材料相同，参杂的材料不同。
例如，在一种可能的实施例中，高温焊料层31的材料为锡合金。高温焊料层31的材料为在主体材料锡(Sn)中掺杂银(Ag)、锑(Sb)、铅(Pb)等金属，低温焊料层32的材料为在主体材料锡中掺杂铋(Bi)、铟(In)、镉(Cd)等金属。高温焊料层31的材料中的主体材料和低温焊料层32的材料中的主体材料相同，参杂的材料不同。
构成低温焊料层32的材料与构成高温焊料层31的材料部分相同，也可以理解为，在高温材料层31的材料为金属单质的情况下，低温焊料层32的材料，其主体材料为构成高温材料层31的金属单质，在主体材料中还参杂有其他金属材料。
例如，在另一种可能的实施例中，高温焊料层31的材料为银单质，低温焊料层32的材料为主体材料银中参杂有铜、锡、镍(Ni)、锌(Zn)、硼(B)(例如BAg40CuZnSnNi)。
这样一来，由于构成低温焊料层32的材料与构成高温焊料层31的材料部分相同，因此高温焊料层31和低温焊料层32的材料的热膨胀系数(coefficient of thermal expansion，CTE)和弹性模量(modulus)均相近。在键合过程中，高温焊料层31和低温焊料层32中都包含的原子会发生扩散，使得高温焊料层31和低温焊料层32通过原子扩散键合。
基于本申请实施例提供的电子组件100，通过在低温焊料层32与第一焊盘11之间设置高温焊料层31，使高温焊料层31与第一焊盘11直接键合。由于高温焊料的延展率比低温焊料的延展率高，因此，高温焊料没有低温焊料脆性高，不易断裂。基于此，高温焊料层31与第一焊盘11键合时形成的介面合金共化物(intermetallic compound，IMC)的强度，高于图3b所示的低温焊料层32与第一焊盘11直接键合时形成的IMC的强度。
在此基础上，由于构成低温焊料层32的材料与构成高温焊料层31的材料部分相同，以使得低温焊料层32和高温焊料层31在键合的过程中，是通过原子扩散实现低 温焊料层32与高温焊料层31键合。因此，低温焊料层32和高温焊料层31在键合的过程中不会形成IMC，低温焊料层32和高温焊料层31键合后的稳定性较高。
因此，将第一电子元器件10与第二电子元器件20键合时，相比图3b所示的直接采用低温焊料层32与第一焊盘11键合，键合界面上形成强度低的IMC。本申请实施例提供的电子组件100中，高温焊料层31与第一焊盘11键合，键合界面上形成强度较高的IMC，并且低温焊料层32和高温焊料层31通过原子扩散键合，在键合的过程中不会形成IMC。可提高第一电子器件10与第一焊接部30键合的稳定性，从而提高电子组件100的稳定性。
此外，如图4所示，通过应力分析可知，电子组件100在受到外界作用力(例如撞击、跌落、震动)时，第一焊接部30与第一焊盘11和第二焊盘21接触面的边缘位置处(图4中黑色方块处)的受力较大。本申请实施例中，通过设置高温焊料层31后，使高温焊料层31位于受应力较大的位置处。由于高温焊料的可靠性比低温焊料的可靠性高，因此，相比图3b所示的直接使低温焊料层32位于受应力较大位置处，本申请实施例提供的第一焊接部30的结构可进一步提高第一电子器件10与第一焊接部30键合的稳定性。
以下，以几个详细的实施例对本申请实施例提供的电子组件100的结构进行详细说明。
实施例一
以第一电子元器件10为PCB，第二电子元器件20为LGA器件为例进行说明。
如图5(沿图2a中A-A′向的剖视图)所示，电子组件100包括：第一电子元器件10、第二电子元器件20、至少一个第一焊接部30以及至少一个第二焊接部40。
第一电子元器件10的第一有源面a和第二电子元器件20的第二有源面b相对设置，且第一电子元器件10上的第一焊盘11在第一电子元器件10上的正投影与第二电子元器件20上的第二焊盘21在第一电子元器件10上的正投影交叠。
其中，此处的交叠，可以是，如图5所示，第一焊盘11和第二焊盘21大小相同，且正对设置。如图6a所示，从俯视图上来看，第一焊盘11的正投影和第二焊盘21的正投影重合。
此处的交叠，也可以是，如图6b所示，第一焊盘11和第二焊盘21大小相同，但错位设置。如图6c所示，从俯视图上来看，第一焊盘11的正投影和第二焊盘21的正投影具有交集，且第一焊盘11和第二焊盘21是一一对应。
此处的交叠，还可以是，如图6d所示，第一焊盘11的尺寸小于第二焊盘21的尺寸。如图6e所示，从俯视图上来看，第一焊盘11的正投影位于第二焊盘21的正投影内。
此处的交叠，还可以是，如图6f所示，第一焊盘11的尺寸大于第二焊盘21的尺寸。如图6g所示，从俯视图上来看，第二焊盘21的正投影位于第一焊盘11的正投影内。
此外，不对第一焊盘11和第二焊盘21的形状做限定，可以是任意形状的封闭图形。第一焊盘11和第二焊盘21的形状可以相同，也可以不同。
以第一焊盘11为例，例如，在一些可能的实施例中，第一焊盘11的形状可以是 如图7a中的圆形，或者是如图7b中的椭圆形，或者是如图7c中的三角形，或者是如图7d中的长方形，或者是如图6a中的正方形，或者是如图7e中的五边形等规则图形。在另一些可能的实施例中，第一焊盘11的形状可以是如图7f中的不规则图形。
如图5所示，对应设置的第一焊盘11和第二焊盘21之间设置有第一焊接部30和第二焊接部40，第一焊接部30靠近第一焊盘11设置，第二焊接部40靠近第二焊盘21设置。
第一焊接部30包括高温焊料层31和低温焊料层32。高温焊料层31靠近第一焊盘11设置，且与第一焊盘11键合。低温焊料层32靠近第二焊接部40设置，且与第二焊接部40键合。第二焊接部40还与第二焊盘21键合。
其中，低温焊料层32的熔点低于高温焊料层31和第二焊接部40的熔点。构成低温焊料层的材料与构成高温焊料层31的材料部分相同，以使得低温焊料层32通过原子扩散与高温焊料层31键合。且构成低温焊料层的材料与构成第二焊接部40的材料部分相同，以使得低温焊料层32通过原子扩散与第二焊接部40键合。构成高温焊料层31的材料与构成第二焊接部40的材料可以相同，也可以不同。
可以理解的是，根据高温焊料层31的选材不同，制备高温焊料层31的工艺不同，高温焊料层31与第一焊盘11的键合工艺也不同，高温焊料层31与低温焊料层32的焊接界面的形状也不同。同理，不同的材料会形成不同的第二焊接部40。
以下，根据高温焊料层31和第二焊接部40的材料的选材不同，对第一电子元器件10和第二电子元器件20的键合过程进行举例示意。
在一种可能的实施例中，高温焊料层31和第二焊接部40的材料为金属合金，如图8a所示，第一电子元器件10和第二电子元器件20的键合过程如下：
S10、如图9a所示，在第一电子元器件10的每一第一焊盘11上放置第一高温焊料G1。
例如，首先，在第一电子元器件10上放置钢网50，钢网50的开口部51对应第一焊盘11，钢网50的遮挡部52对应相邻第一焊盘11之间的部分。然后，涂刷焊膏，使焊膏填充在钢网50的开口部51中。随后，去除钢网50，即可形成位于第一焊盘11上的第一高温焊料G1。
S11、如图9b所示，将第一高温焊料G1与第一焊盘11键合，以形成高温焊料层31。如图8a所示，步骤S11是在执行完步骤S10后执行的。
例如，根据第一高温焊料G1的回流温度曲线对应的温度，采用回流焊工艺，将第一高温焊料G1与第一焊盘11键合，以形成与第一焊盘11键合的第一高温焊料层31。
其中，在第一高温焊料G1的主体材料与第一焊盘11的材料不同时，例如，第一高温焊料G1的主体材料为锡，第一焊盘11的材料为铜，第一高温焊料G1与第一焊盘11的键合界面处会形成IMC。
S12、如图9c所示，在第二电子元器件20的每一第二焊盘21上放置第二高温焊料G2。
在第二焊盘21上放置第二高温焊料G2的方法，可以与在第一焊盘11上放置第一高温焊料G1的方法相同，可以参照步骤S10。
S13、如图9d所示，将第二高温焊料G2与第二焊盘21键合，以形成第二焊接部40。如图8a所示，步骤S13是在执行完步骤S12后执行的。
将第二高温焊料G2与第二焊盘21键合，以形成与第二焊盘21键合的第二焊接部40的方法，可以与将第一高温焊料G1与第一焊盘11键合的方法相同，可以参照步骤S11。
应当明白的是，上述步骤S10和步骤S12两者并没有先后顺序，可以是在同一时间段内同时执行这两个步骤，也可以是执行完步骤S10再执行步骤S12，还可以是执行完步骤S12后再执行步骤S10。
S14、如图9e所示，在高温焊料层31上放置低温焊料D。如图8a所示，步骤S14是在执行完步骤S11后执行的。
在高温焊料层31上放置低温焊料D的方法，可以与步骤S10中在第一焊盘11上放置第一高温焊料G1的方法相同。
或者，S14′、如图9f所示，在第二焊接部40上形成低温焊料D。如图8b所示，步骤S14′是在执行完步骤S13后执行的。
S15、如图9g所示，将第一电子元器件10和第二电子元器件20对位贴合。以使低温焊料D分别与高温焊料层31和第二焊接部40贴合。
其中，若执行步骤S14后，在高温焊料层31上放置了低温焊料D。如图9g所示，第一电子元器件10和第二电子元器件20对位贴合时，将第一电子元器件10正向放置好，第二电子元器件20从上方与第一电子元器件10对位贴合。
若执行步骤S14′后，在第二焊接部40上放置了低温焊料D。如图9h所示，第一电子元器件10和第二电子元器件20对位贴合时，将第二电子元器件20正向放置好，第一电子元器件10从上方与第二电子元器件20对位贴合。
此处，无论是执行上述步骤S14，还是执行上述步骤S14′，在执行步骤S15后低温焊料D是位于高温焊料层31和第二焊接部40之间的。
由于低温焊料D是放置在高温焊料层31上的，并未与其键合。因此，以图9h所示的结构为例，将放置有低温焊料D的第二电子元器件20作为基准，正向放置，未放置低温焊料D的第一电子元器件10从上方盖下来与第二电子元器件20对位贴合。可以避免低温焊料D因重力作用于第二焊接40部分离，保证键合的可靠性。
S16、如图5所示，将低温焊料D，与高温焊料层31和第二焊接部40分别通过原子扩散键合，形成低温焊料层32。
此时，键合后的高温焊料层32和低温焊料层31作为第一焊接部30，第一焊接部30和第二焊接部40通过原子扩散键合，以使第一电子元器件10和第二电子元器件20键合。
可以理解的是，由于低温焊料D的熔点低于高温焊料层31和第二焊接部40的熔点，因此，将低温焊料D与高温焊料层31和第二焊接部40键合时，加热温度低于步骤S11中第一高温焊料G1与第一焊盘11键合时的温度。也就是说，将低温焊料D与高温焊料层31和第二焊接部40键合时，低温焊料D会熔融，但高温焊料层31和第二焊接部40均未熔融。
需要说明的是，第一，现有技术中采用高温焊料将第一电子元器件10和第二电子 元器件20键合时，高温环境下，第一电子元器件10和第二电子元器件20各自会有不同程度的受热变形。而由于第一电子元器件10和第二电子元器件20又键合在一起，因此第一电子元器件10和第二电子元器件20会受到来自对方的形变拉力，导致第一电子元器件10和第二电子元器件20翘曲变形。
而本申请实施例中，虽然第一高温焊料G1与第一焊盘11是在高温下键合，第二高温焊料G2与第二焊盘21也是在高温下键合。但是，以第一高温焊料G1与第一焊盘11键合为例，由于第一高温焊料G1与第一焊盘11键合时，是在第一电子元器件10的表面键合，只是自身会有受热变形这在第一电子元器件10的承受范围内，不会受到第二电子元器件20的作用力，因此发生翘曲变形的概率明显降低。
此外，以第一电子元器件10为例，当第一电子元器件10的非有源面上具有不耐高温的部件或膜层时，可以先在第一焊盘11上形成高温焊料层31后，再形成不耐高温的部件或膜层。例如，第一电子元器件10为表面高光制程指纹模组时，由于光膜不耐高温，可以在第一焊盘11上形成高温焊料层31后，再在形成光膜。
第二，由于第一高温焊料G1、第二高温焊料G2以及低温焊料D三种焊料比例差异、回流曲线差异、浸润性差异等工艺因素，会导致第二焊接部40与第一焊接部30的键合界面的形状以及第一焊接部30中高温焊料层31与低温焊料层32的键合界面的形状会有多种形态，因此，本申请实施例中，不对第一焊接部30和第二焊接部40纵向截面的形状和键合界面的形状进行限定。
其中，第二焊接部40与低温焊料层32的键合界面与第一焊接部30中高温焊料层31与低温焊料层32的键合界面的形状的形成原理相同，以第一焊接部30中高温焊料层31与低温焊料层32的键合界面的形状为例进行举例说明。可以理解的是，由于高温焊料层31与低温焊料层32是通过原子扩散键合的，因此，高温焊料层31与低温焊料层32的键合界面的形状即为高温焊料层31与第一焊盘11键合后的形状。
基于此，在一种可能的实施方式中，高温焊料层31与第一焊盘11通过焊接工艺达到键合的效果，在此情况下，如图10a所示，高温焊料层31与低温焊料层32的键合界面c为中心向第一焊盘11所在侧凹陷的曲面。
在另一种可能的实施方式中，高温焊料层31与第一焊盘11通过其他工艺达到键合的效果，在此情况下，如图10b所示，高温焊料层31与低温焊料层32的键合界面c为中心向远离第一焊盘11所在侧凸起的曲面。或者，如图10c所示，高温焊料层31与低温焊料层32的键合界面c为与第一焊盘11平行的平面。
此外，因低温焊料D的放置量的不同和工艺的误差，低温焊料层32的与键合界面c相交的侧面d的形状也会有多种形态。也就是说，低温焊料层32的垂直于第一电子元器件10的方向(纵向)上的截面会有多种形态。因此，本申请实施例中，不对低温焊料层32的侧面d的形状进行限定。
以下，对的低温焊料层32的与键合界面c相交的侧面d的形状，进行举例说明。
在一种可能的实施方式中，如图10b所示，低温焊料层32的侧面d为平面。
其中，根据第一焊盘11和第二焊盘21相对大小的不同，低温焊料层32的侧面d与第一焊盘11的夹角不同。如图10b所示，第一焊盘11和第二焊盘21大小相等的情况下，低温焊料层32的侧面d为垂直于第一焊盘11的平面。如图11a所示，第一焊 盘11小于第二焊盘21的情况下，低温焊料层32的侧面d为与第一焊盘11的夹角大于90°的平面。如图11b所示，第一焊盘11大于第二焊盘21的情况下，低温焊料层32的侧面d为与第一焊盘11的夹角小于90°的平面。
在另一种可能的实施方式中，若低温焊料D的放置量较少，如图11c所示，低温焊料层32的侧面d为向内凹陷的曲面。
在另一种可能的实施方式中，若低温焊料D的放置量较多，如图11d所示，低温焊料层32的侧面d为向外凸起的曲面。
在另一种可能的实施例中，高温焊料层31的材料为金属单质。如图12所示，第一电子元器件10和第二电子元器件20的键合过程如下：
S20、如图13a所示，通过电镀工艺，在第一电子元器件10的第一焊盘11上形成与第一焊盘11键合的高温焊料层31。
其中，通过电镀工艺形成的高温焊料层31的远离第一焊盘11的表面(与低温焊料层32的键合界面c)为平行于第一焊盘11的平面。
S21、如图13b所示，通过电镀工艺，在第二电子元器件20的第二焊盘21上形成与第二焊盘21键合的第二焊接部40。
同理，通过电镀工艺形成的第二焊接部40的远离第二焊盘21的表面为平行于第二焊盘21的平面。
S22、在高温焊料层31或第二焊接部40上放置低温焊料D。图13c以在高温焊料层31上放置低温焊料D为例进行示意。
在高温焊料层31或第二焊接部40上放置低温焊料D的方法，可以与步骤S10中在第一焊盘11上放置第一高温焊料G1的方法相同。
S23、将第一电子元器件10和第二电子元器件20对位贴合。
S24、如图13d所示，将低温焊料D，与高温焊料层31和第二焊接部40分别通过原子扩散键合，形成低温焊料层32。键合后的高温焊料层31和低温焊料层32作为第一焊接部30，第一焊接部30和第二焊接部40通过原子扩散键合，以使第一电子元器件10和第二电子元器件20键合。
在此情况下，如图13d所示，第一电子元器件10和第二电子元器件20键合后，高温焊料层31与低温焊料层32的键合界面c为平行于第一焊盘11的平面。第二焊接部40与低温焊料层32的键合界面也为平行于第一焊盘11的平面。
低温焊料层32的侧面d的形状，可以参考上述关于图11a-图11d的描述。
在上述结构的基础上，如图14所示，电子组件在受到外界作用力(例如撞击、跌落、震动)时，第一焊接部30与第一焊盘11接触面的边缘位置处和第二焊接部40与第二焊盘21接触面的边缘位置处(图14中黑色方块处)的受力较大，为应力集中区，中间区域为低应力区。由于高温焊料的脆性比低温焊料的脆性小，即高温焊料的可靠性比低温焊料的可靠性高。因此，本申请实施例中，通过调整高温焊料层31的厚度，使高温焊料层31位于应力集中区，避免将低温焊料层32设置在应力集中区，以提高第一电子元器件10和第二电子元器件20键合的稳定性。
通过对电子组件100进行跌落仿真分析，在距离第一焊盘11和第二焊盘21在10um以内的位置处，第一焊接部30和第二焊接部40受到的应力比较大。而第一焊接部 30和第二焊接部40的厚度太大时，不利于通过钢网涂刷焊膏的方式制备。基于此，在本申请的一些实施例中，高温焊料层31和第二焊接部40的厚度为10-100um。例如，高温焊料层31和第二焊接部40的厚度为20um、30um、40um、50um、60um、70um、80um、90um。其中，本申请实施例中部件的厚度，是指部件沿垂直于第一焊盘的方向上的尺寸。
此外，由于低温焊料层32的厚度太薄时，会影响低温焊料层32与高温焊料层31和第二焊接部40的键合效果，而低温焊料层32的厚度太厚时，不利于通过钢网涂刷焊膏的方式制备。基于此，在本申请的一些实施例中，低温焊料层32的厚度为50-100um。例如，低温焊料层32的厚度为60um、70um、80um、90um。
通过对电子组件100进行跌落仿真分析得到，第一焊接部30和第二焊接部40在图14所示的应力集中区的受力比低应力去的受力要大40％左右。也就是说，本申请实施例提供的结构，低温焊料层32承受的应力可减少40％左右。从而可保证第一电子元器件10和第二电子元器件20键合的稳定性，以提高电子设备1的寿命。
在图5所示的电子组件的基础上，如图15(沿图2a中A-A′向的剖视图)所示，电子组件还包括位于第一电子元器件10和第二电子元器件20之间的底部填充胶层(underfill)60。底部填充胶层60与第一电子元器件10的第一有源面a和第二电子元器件20的第二有源面b分别粘接，且底部填充胶层60围绕在第一焊接部30和第二焊接部40的外围，并与第一焊接部30和第二焊接部40粘接。
其中，底部填充胶层60的材料可以为热固化胶。
此处，通过在第一电子元器件10和第二电子元器件20之间填充底部填充胶层60，且底部填充胶层60与第一焊接部30和第二焊接部40粘接，可以对第一焊接部30和第二焊接部40起到保护和稳固作用，以进一步提高第一电子元器件10和第二电子元器件20键合的稳定性。
此外，本实施例中，第一焊接部30和第二焊接部40是由三层焊料层构成，且三层焊料的厚度都不会太薄，使得第一电子元器件10和第二电子元器件20之间的间隙较大。这样一来，形成底部填充胶层60时，胶受到的阻力小，胶的流动性较好。可以确保胶完全包裹每个由第一焊接部30和第二焊接部40构成的焊点，从而进一步提高第一电子元器件10和第二电子元器件20键合的稳定性。
实施例二
实施例二与实施例一的不同在于：第一电子元器件10为PCB，第二电子元器件20为BGA器件。
如图16(沿图2a中A-A′向的剖视图)所示，第二焊接部40为设置在第二焊盘21上的微凸点。在这种情况下，第二焊接部40属于第二电子元器件20中的部件，在第一电子元器件10和第二电子元器件20键合时，没有形成第二焊接部40的步骤。
其中，微凸点可以是焊球(ball)，也可以是凸块(bump)等，本申请实施例以第二焊接部40为焊球为例进行示意。
基于此，如图17a所示，第一电子元器件10和第二电子元器件20的键合过程如下：
S30、在第一电子元器件10的每一第一焊盘11上形成与第一焊盘11键合的高温 焊料层31。
示例的，步骤S30可以包括：如图9a所示，在第一电子元器件10的每一第一焊盘11上放置第一高温焊料G1。如图9b所示，将第一高温焊料G1与第一焊盘11键合，以形成高温焊料层31。
另一种实例的，步骤S30可以包括：如图13a所示，通过电镀工艺，在第一电子元器件10的第一焊盘11上形成与第一焊盘11键合的高温焊料层31。
S31、如图9e和图13c所示，在高温焊料层31上放置低温焊料D。
S32、如图17b和图17c所示，将第一电子元器件10和第二电子元器件20对位贴合。
S33、如图16和图18(沿图2a中A-A′向的剖视图)所示，将低温焊料D，与高温焊料层31和第二焊接部40分别通过原子扩散键合，形成低温焊料层32。从而使第一电子元器件10和第二电子元器件20键合。
在图16所示的电子组件的结构的基础上，如图19(沿图2a中A-A′向的剖视图)所示，电子组件还包括位于第一电子元器件10和第二电子元器件20之间的底部填充胶层60。底部填充胶层60与第一电子元器件10的第一有源面a和第二电子元器件20的第二有源面b分别粘接，且围绕在第一焊接部30和第二焊接部40的外围，并与第一焊接部30和第二焊接部40粘接。
以上，仅为本申请的具体实施方式，但申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (12)

  1. 一种电子组件，其特征在于，包括:
    第一电子元器件，其第一有源面上具有至少一个第一焊盘；
    第二电子元器件，其第二有源面上具有至少一个第二焊盘，所述第二有源面与所述第一有源面相对设置；
    至少一个第一焊接部，一个所述第一焊接部位于一个所述第一焊盘和一个所述第二焊盘之间，且所述第一焊接部与位于其两侧的所述第一焊盘和所述第二焊盘键合；
    所述第一焊接部包括高温焊料层和低温焊料层；所述高温焊料层靠近所述第一焊盘设置，且与所述第一焊盘键合；所述低温焊料层靠近所述第二焊盘设置，且与所述第二焊盘键合；
    其中，所述低温焊料层的熔点低于所述高温焊料层的熔点，且构成所述低温焊料层的材料与构成所述高温焊料层的材料部分相同，以使得所述低温焊料层通过原子扩散与所述高温焊料层键合。
  2. 根据权利要求1所述的电子组件，其特征在于，所述电子组件还包括至少一个第二焊接部；
    所述第二焊接部设置在所述第一焊接部靠近所述第二焊盘一侧，且与所述第二焊盘键合；
    所述低温焊料层的熔点低于所述第二焊接部的熔点，且构成所述低温焊料层的材料与构成所述第二焊接部的材料部分相同，以使得所述低温焊料层通过原子扩散与所述第二焊接部键合。
  3. 根据权利要求1所述的电子组件，其特征在于，所述高温焊料层与所述低温焊料层的键合界面为平面；构成所述高温焊料层的材料为金属单质。
  4. 根据权利要求1所述的电子组件，其特征在于，所述高温焊料层与所述低温焊料层的键合界面为中心向所述第一焊盘所在侧凹陷的曲面；构成所述高温焊料层的材料为金属合金。
  5. 根据权利要求2所述的电子组件，其特征在于，所述第一焊盘在所述第一电子元器件上的正投影位于所述第二焊盘在所述第一电子元器件上的正投影内。
  6. 根据权利要求1所述的电子组件，其特征在于，沿垂直于所述第一焊盘的方向，所述低温焊料层的厚度为50-100um。
  7. 根据权利要求2所述的电子组件，其特征在于，沿垂直于所述第一焊盘的方向，所述高温焊料层或所述第二焊接部的厚度为10-100um。
  8. 根据权利要求2所述的电子组件，其特征在于，所述第二焊接部为设置在所述第二焊盘上的微凸点。
  9. 根据权利要求2所述的电子组件，其特征在于，所述电子组件还包括位于所述第一电子元器件和所述第二电子元器件之间的底部填充胶层；
    所述底部填充胶层与所述第一有源面和所述第二有源面分别粘接，且围绕在所述第一焊接部和所述第二焊接部的外围，并与所述第一焊接部和所述第二焊接部粘接。
  10. 一种电子组件的制备方法，其特征在于，所述电子组件包括第一电子元器件和第二电子元器件；所述第一电子元器件的第一有源面上具有至少一个第一焊盘；所 述第二电子元器件的第二有源面上具有至少一个第二焊盘，所述第二有源面与所述第一有源面相对设置；
    所述电子组件的制备方法包括：
    在所述第一电子元器件的每一所述第一焊盘上形成与所述第一焊盘键合的高温焊料层；
    在所述高温焊料层与所述第二焊盘之间放置低温焊料；
    将所述低温焊料，与所述高温焊料层和所述第二焊盘分别通过原子扩散键合，形成低温焊料层；键合后的所述高温焊料层和所述低温焊料层作为第一焊接部，以使所述第一电子元器件和所述第二电子元器件键合；
    其中，所述低温焊料层的熔点低于所述高温焊料层的熔点，且构成所述低温焊料层的材料与构成所述高温焊料层的材料部分相同。
  11. 根据权利要求10所述的电子组件的制备方法，其特征在于，将所述低温焊料，与所述高温焊料层和所述第二焊盘分别通过原子扩散键合之前，所述电子组件的制备方法还包括：
    在所述第二电子元器件的每一所述第二焊盘上形成与所述第二焊盘键合的第二焊接部；所述低温焊料层的熔点低于所述第二焊接部的熔点，且构成所述低温焊料层的材料与构成所述第二焊接部的材料部分相同；
    将所述低温焊料与所述第二焊盘通过原子扩散键合，包括：将所述低温焊料与所述第二焊接部通过原子扩散键合。
  12. 一种电子设备，其特征在于，包括权利要求1-9任一项所述的电子组件。
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