WO2021051232A1 - 功率放大电路、发射器以及网络设备 - Google Patents

功率放大电路、发射器以及网络设备 Download PDF

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Publication number
WO2021051232A1
WO2021051232A1 PCT/CN2019/105943 CN2019105943W WO2021051232A1 WO 2021051232 A1 WO2021051232 A1 WO 2021051232A1 CN 2019105943 W CN2019105943 W CN 2019105943W WO 2021051232 A1 WO2021051232 A1 WO 2021051232A1
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WIPO (PCT)
Prior art keywords
power
branch
circuit
power amplifier
power amplifying
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Ceased
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PCT/CN2019/105943
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English (en)
French (fr)
Inventor
孙捷
孙益军
索海雷
陈金虎
李松
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to EP19945716.9A priority Critical patent/EP4024704A4/en
Priority to PCT/CN2019/105943 priority patent/WO2021051232A1/zh
Priority to JP2022516707A priority patent/JP7490050B2/ja
Priority to CN201980100342.1A priority patent/CN114402527A/zh
Priority to KR1020227011442A priority patent/KR102725649B1/ko
Publication of WO2021051232A1 publication Critical patent/WO2021051232A1/zh
Priority to US17/695,065 priority patent/US12334877B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0288—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers using a main and one or several auxiliary peaking amplifiers whereby the load is connected to the main amplifier using an impedance inverter, e.g. Doherty amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/42—Modifications of amplifiers to extend the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
    • H03F3/602—Combinations of several amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/198—A hybrid coupler being used as coupling circuit between stages of an amplifier circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/204—A hybrid coupler being used at the output of an amplifier circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/222—A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/387—A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • This application relates to the field of communications, in particular to power amplifier circuits, transmitters and network equipment in the field of communications.
  • wireless communication systems have put forward higher and higher requirements for channel capacity and data transmission rate.
  • Current and future wireless communication systems require power amplifiers to have broadband and multi-band characteristics. They must take into account multiple frequency bands under the same communication standard, and they should also be compatible with different communication standards. Their working frequency bands are fragmented and their signal bandwidths are getting wider and wider.
  • the power amplifier is the main energy-consuming module of the transceiver, and its energy consumption accounts for a high proportion of the wireless communication system. Improving the efficiency of the power amplifier and reducing the energy consumption directly affects the heat dissipation of the system, and also affects the load capacity of the power supply. . Therefore, expanding the working bandwidth of the power amplifier and improving the working efficiency of the power amplifier are key technologies of the wireless communication system.
  • DHT Two-way Doherty
  • the use of 3 channels, 4 channels and other N channels of DHT can further expand the power back-off or generate multiple high-efficiency points, thereby further improving the efficiency of the power amplifier.
  • the N-channel DHT often has a relatively large impedance modulation of the power tube, and its working bandwidth is limited, and cannot be used in a high-power ultra-wideband power amplifier circuit.
  • This application provides a power amplifier circuit, a transmitter, and a network device, so that the power amplifier circuit has the characteristics of broadband and high efficiency.
  • an embodiment of the present application provides a power amplifying circuit.
  • the power amplifying circuit may include: N input terminals, N power amplifying branches, a combining circuit, and an output terminal.
  • the N input terminals are respectively connected to one of the N power amplification branches, each of the power amplification branches is connected to a synthesis circuit, and the synthesis circuit is also connected to the output terminal, and each input terminal is used for input An input signal.
  • N power amplifying branches and synthesis circuits are used for power amplifying and synthesizing N input signals, and generate an output signal.
  • the output terminal is used to output the output signal.
  • the N power amplifying branches include a first power amplifying branch and N-1 second power amplifying branches.
  • the first power amplifying branch works in a Class A, B or B working mode
  • the N-1 The second power amplifying branch works in a Class C working mode under different gate bias voltages.
  • the gate bias voltages of the N-1 second power amplifying branches decrease sequentially, and N is a positive integer greater than 2. .
  • N-1 second power amplifying branches work in a Class C working mode with different gate bias voltages, and N power amplifiers
  • the branches are turned on in sequence and reach saturation in turn, so multiple high-efficiency points can be generated under different power back-offs, and the back-off efficiency is improved, and since there is no load pulling between the N power amplification branches, impedance modulation The ratio is 1, so that the working bandwidth of the power amplifier circuit of the present application can be guaranteed, so that the power amplifier circuit has the characteristics of broadband and high efficiency.
  • each of the second power amplification branches includes a first port and two second ports, the first port is connected to an input end, and the two second ports are respectively connected to the composite Circuit connection.
  • Each second power amplification branch is used to perform power distribution and power amplification on one input signal, and generate two second signals, each of the two second signals is output through a second port To the synthesis circuit.
  • the two second signals have the same amplitude and a phase difference of 90 degrees.
  • the balanced power amplification characteristic can be realized through the second power amplification circuit.
  • each second power amplifying branch includes a power dividing circuit and two power amplifying sub-branches.
  • the through end and the coupling end of the power dividing circuit are respectively connected with a power amplifier sub-branch.
  • the two power amplifying sub-branches work in a Class C working mode under the same bias.
  • the impedance modulation ratio is all 1, which can ensure the bandwidth of the power amplification circuit of the present application to avoid bandwidth limitation.
  • the synthesis circuit includes N-1 couplers and N-1 impedance matching circuits.
  • An impedance matching circuit is arranged between two adjacent couplers of the N-1 couplers, and an impedance matching circuit is arranged between the output end of the power amplifier circuit and one coupler.
  • the isolation end of the first coupler of the N-1 couplers is connected to the output end of the first power amplifier branch, and the two balanced ends of each coupler of the N-1 couplers are respectively connected A second power amplifier branch.
  • the impedance matching circuit between two adjacent couplers is used to convert the characteristic impedance of the former coupler into the characteristic impedance of the latter coupler.
  • the characteristic impedance of each of the N-1 couplers is based on the optimal value of the power tubes in the first power amplifier branch and the second power amplifier branch in the Class B working mode The impedance is determined.
  • the characteristic impedance of the coupler in the synthesis circuit can be determined according to the optimal impedance of the power tube in the power amplifier branch, which can improve the performance of the power amplifier circuit of the present application.
  • the impedance matching circuit includes at least one of a low-pass filter circuit, a high-pass filter circuit, a resonance circuit, or a microstrip line.
  • the first power amplifying branch includes a power amplifier.
  • the first power amplifying branch includes a Doherty circuit
  • the input of the Doherty circuit is connected to the input of the power amplifying circuit
  • the output of the Doherty circuit is connected to the combining circuit.
  • the first power amplifying branch reaches the voltage and current saturation state before the second power amplifying branch reaches the voltage and current saturation state.
  • an embodiment of the present application provides a transmitter including the power amplifier circuit according to any one of the first aspect.
  • an embodiment of the present application provides a network device that includes a transceiver, a processor, and a memory, and the transceiver includes the power amplifier circuit according to any one of the first aspect.
  • the power amplifier circuit includes N input terminals, N power amplification branches, a synthesis circuit, and an output terminal, and the N input terminals and N power amplification branches are respectively One of the power amplifier branches is connected, each power amplifier branch is connected to the synthesis circuit, and the synthesis circuit is also connected to the output terminal.
  • Each input terminal is used to input an input signal
  • N power amplification branches and synthesis circuits are used for Perform power amplification on N input signals and generate an output signal.
  • the output terminal is used to output the output signal.
  • the N power amplification branches include a first power amplification branch and N-1 second power amplification branches.
  • the first power amplifying branch works in Class A and B or Class B working mode
  • N-1 second power amplifying branches work in Class C working mode under different gate bias voltages
  • N-1 second power amplifiers The gate bias voltages of the branches decrease sequentially, and N is a positive integer greater than 2. Since the N power amplification branches are turned on in sequence and reach saturation in turn, multiple high efficiency points can be generated under different power back-offs to improve the back-off efficiency, and because there is no load between the N power amplification branches Traction, so the impedance modulation ratio is 1, so that the working bandwidth of the power amplifier circuit of the present application can be guaranteed, so that the power amplifier circuit has the characteristics of broadband and high efficiency.
  • FIG. 1 is a schematic structural diagram of a power amplifier circuit provided by an embodiment of the application
  • FIG. 2 is a schematic structural diagram of another power amplifier circuit provided by an embodiment of the application.
  • FIG. 3 is a schematic structural diagram of another power amplifier circuit provided by an embodiment of the application.
  • FIG. 4 is a schematic structural diagram of another power amplifier circuit provided by an embodiment of the application.
  • FIG. 5 is a schematic structural diagram of a transmitter provided by an embodiment of the application.
  • FIG. 6 is a schematic structural diagram of a network device provided by an embodiment of this application.
  • At least one (item) refers to one or more, and “multiple” refers to two or more.
  • “And/or” is used to describe the association relationship of associated objects, indicating that there can be three types of relationships, for example, “A and/or B” can mean: only A, only B, and both A and B , Where A and B can be singular or plural.
  • the character “/” generally indicates that the associated objects before and after are in an “or” relationship.
  • the following at least one item (a) or similar expressions refers to any combination of these items, including any combination of a single item (a) or a plurality of items (a).
  • At least one of a, b, or c can mean: a, b, c, "a and b", “a and c", “b and c", or "a and b and c" ", where a, b, and c can be single or multiple.
  • the embodiments of the present application provide a power amplifier circuit, which has the characteristics of broadband and high efficiency, which can generate multiple high efficiency points under different power back-offs, improve the back-off efficiency, and guarantee each power
  • the impedance modulation ratio of the tube is 1, and its specific structure can be referred to the explanation of the following embodiments.
  • FIG. 1 is a schematic structural diagram of a power amplifier circuit provided by an embodiment of the application.
  • the power amplifier circuit may include: N input terminals, N power amplifier branches, a synthesis circuit 20, and an output. ⁇ 30.
  • the N input terminals are input_1, input_2, input_3, ..., input_N, respectively.
  • the N power amplifying branches are power amplifying branch 11, power amplifying branch 12, ..., power amplifying branch 1N.
  • the N input terminals are respectively connected to one power amplification branch of the N power amplification branches, each power amplification branch is connected to a synthesis circuit 20, and the synthesis circuit 20 is also connected to an output terminal.
  • input_1 is connected to power amplifying branch 11
  • input_2 is connected to power amplifying branch 12
  • input_3 is connected to power amplifying branch 13
  • input_N is connected to power
  • the amplifying branch 1N is connected, the output terminal of each power amplifying circuit is connected with the input terminal of the synthesis circuit 20, and the output terminal of the synthesis circuit is connected with the output terminal 30.
  • Each input terminal (input_1, input_2, input_3,..., input_N) is used to input an input signal.
  • the N power amplifying branches and the combining circuit 20 are used for power amplifying and combining N input signals and generating an output signal.
  • the output terminal 30 is used to output an output signal.
  • the N power amplifying branches include a first power amplifying branch and N-1 second power amplifying branches, and the first power amplifying branch works in a class A and B (AB) or B (B) working mode ,
  • the N-1 second power amplifying branch works in a class C (C) operating mode under different gate bias voltages, and the gate bias voltages of the N-1 second power amplifying branches decrease sequentially
  • N is a positive integer greater than 2.
  • the power amplifying branch 11 is the first power amplifying branch
  • the power amplifying branch 12 the power amplifying branch 13,...
  • the power amplifying branch 1N is the N-1 second power amplifying branch
  • the gate bias voltages of the power amplifying branch 12, the power amplifying branch 13,..., the power amplifying branch 1N are sequentially reduced.
  • the first power amplifying branch (power amplifying branch 11) includes an input terminal and an input terminal.
  • the input terminal of the power amplifying branch 11 is connected to input_1, and the power amplifying branch 11
  • the output terminal of is connected to the input terminal of the synthesis circuit 20.
  • each second power amplifying branch includes a first port and two second ports, the first The port is connected to one input terminal, and the two second ports are respectively connected to the synthesis circuit 20.
  • Each second power amplifying branch (power amplifying branch 12, power amplifying branch 13,..., power amplifying branch 1N) is used for power distribution and power amplifying of an input signal, and generates two second signals , Each of the two second signals is output to the synthesis circuit 20 through a second port.
  • the two second signals have the same amplitude and a phase difference of 90 degrees.
  • the power amplifier branch 12 includes a first port 121 and two second ports (122, 123), the first port 121 is connected to input_2, and the second port 122 and the second port 123 are respectively connected to the synthesis circuit 20 connections.
  • the power amplification branch 12 is used to perform power distribution and power amplification on the input signal input from input_2, and generate two second signals, and output the two second signals to the synthesis through the second port 122 and the second port 123 Circuit 20.
  • the power amplifier branch 13 includes a first port 131 and two second ports (132, 133), the first port 131 is connected to the input_3, and the second port 132 and the second port 133 are respectively connected to the synthesis circuit 20.
  • the power amplification branch 13 is used to perform power distribution and power amplification on the input signal input from input_3, and generate two second signals, and output the two second signals to the synthesis through the second port 132 and the second port 133 Circuit 20.
  • the power amplifier branch 1N includes a first port 1N1 and two second ports (1N2, 1N3). The first port 1N1 is connected to the input_N, and the second port 1N2 and the second port 1N3 are respectively connected to the combining circuit 20.
  • the power amplifier branch 1N is used to perform power distribution and power amplification on the input signal input from input_N, and generate two second signals, and output the two second signals to the synthesis through the second port 1N2 and the second port 1N3 Circuit 20.
  • the other second power amplifying branches adopt the same connection method as the power amplifying branch 12, the power amplifying branch 13 or the power amplifying branch 1N, which will not be illustrated here.
  • the synthesis circuit 20 is used for outputting the output of the above-mentioned power amplifier branch 11, the second port 122, the second port 123, the second port 132, the second port 133, ..., the second port 1N2, and the second port 1N3.
  • the signal undergoes power synthesis and is output through the output terminal 30.
  • the working principle of the power amplifying circuit in the embodiment of the present application is schematically explained. Since the power amplifying branch 11 is in the class A and B (AB) or B (B) working mode, the power amplifying branch 12, the power amplifying branch 13, and the «, the power amplifier branch 1N is in the C (C) working mode, and the grids of each second power amplifier branch (power amplifier branch 12, power amplifier branch 13,..., power amplifier branch 1N) The bias voltage is sequentially reduced, so that the power amplifying branch 11, the power amplifying branch 12, the power amplifying branch 12,..., The power amplifying branch 1N are sequentially turned on, and sequentially reach saturation.
  • the power amplifying branch 11 works, and the power amplifying branch 12, the power amplifying branch 13,..., and the power amplifying branch 1N are all in a closed state.
  • the power amplifying branch 11 reaches the saturation state, the power amplifying branch 12 is turned on, the power amplifying branches 13,..., and the power amplifying branch 1N are still in the closed state, and the power amplifying branch 11 remains in the saturated state.
  • the power amplifying branch 12 reaches the saturation state, the power amplifying branch 13 is turned on, the power amplifying branch 14,..., and the power amplifying branch 1N are still in the closed state, and the power amplifying branch 11 and the power amplifying branch 12 remain The saturation state remains unchanged.
  • the first power amplifying branch includes a power amplifier, and the power amplifier can be used as a main amplifier.
  • the first power amplifying branch includes a Doherty circuit, the input end of the Doherty circuit is connected to the input end (input_1) of the power amplifying circuit, and the output end of the Doherty circuit is connected to the synthesis circuit 20.
  • the aforementioned first power amplifying branch reaches the voltage and current saturation state, which is earlier than the second power amplifying branch reaching the voltage and current saturation state.
  • the power amplifier circuit of this embodiment includes N input terminals, N power amplifier branches, a synthesis circuit, and an output terminal.
  • the N input terminals are respectively connected to one of the N power amplifier branches.
  • a power amplifier branch is connected to the synthesis circuit, and the synthesis circuit is also connected to the output terminal.
  • Each input terminal is used to input an input signal.
  • N power amplifier branches and synthesis circuits are used to power amplify the N input signals, and Generate an output signal, and the output terminal is used to output the output signal.
  • N power amplification branches include a first power amplification branch and N-1 second power amplification branches.
  • the first power amplification branch works in A and B Class or Class B working mode
  • N-1 second power amplifying branch works under different gate bias voltage in Class C working mode
  • N-1 second power amplifying branch's gate bias voltage is reduced in turn Small
  • N is a positive integer greater than 2. Since the N power amplification branches are turned on in sequence and reach saturation in turn, it is possible to generate multiple high-efficiency points under different power back-offs, improve the back-off efficiency, and because there is no load between the N power amplification branches Traction, so the impedance modulation ratio is 1, so that the working bandwidth of the power amplifier circuit of the present application can be guaranteed, so that the power amplifier circuit has the characteristics of broadband and high efficiency.
  • the M input terminals in the power amplifier circuit of the embodiment of the present application may be connected to the output terminal of a power dividing circuit, and M (M is less than or equal to N) of the N input signals in the embodiment of the present application
  • the power dividing circuit divides the channel signal into two sub-channel signals, and the two sub-channel signals can be input to the other two input terminals of the power amplifier circuit in the embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another power amplifier circuit provided by an embodiment of the application. As shown in FIG. 2, this embodiment is based on the power amplifier circuit shown in FIG. 1, and each second power amplifier branch (The power amplifying branch 12, the power amplifying branch 13,..., the power amplifying branch 1N) may include a power dividing circuit and two power amplifying sub-branches. The amplifying sub-branches are connected, wherein the two power amplifying sub-branches work in a class C (C) working mode under the same bias.
  • C class C
  • Each power dividing circuit is used to distribute power to the input signal at the input terminal (input_2, input_3, ..., or input_N).
  • each power dividing circuit may be a coupler, for example, a 50 ohm coupler.
  • Each power amplifying sub-branch is used for power amplifying, and it can be a power amplifier.
  • the power amplifying branch 12 may include a power dividing circuit 124, a power amplifying sub-branch 125, and a power amplifying sub-branch 126, the input end of the power dividing circuit 124 is connected to input_2, and the isolated end of the power dividing circuit 124 Connect the load.
  • the through end 1241 of the power dividing circuit 124 is connected to the input end of the power amplifying sub-branch 125, and the coupling end 1242 of the power dividing circuit 124 is connected to the input end of the power amplifying sub-branch 126.
  • the output end of the power amplifying sub-branch 125 is connected to the second port 122, and the output end of the power amplifying sub-branch 126 is connected to the second port 123.
  • the power amplifying sub-branch 125 and the power amplifying sub-branch 126 can work in two power amplifiers in Class C (C) working mode under the same gate bias voltage, and the power amplifier can be used as the peak amplifier 1.
  • the input signal input from input_2 passes through the power dividing circuit 124 and is divided into two signals.
  • One of the two signals is output to the power amplifier sub-branch 125 through the through terminal 1241, and the other signal is output through the coupling terminal 1242.
  • the phase difference between the two signals is 90 degrees.
  • the two signals pass through the power amplifying sub-branch 125 and the power amplifying sub-branch 126 to output two second signals.
  • the two second signals have the same amplitude and a phase difference of 90 degrees.
  • the power amplifying branch 13 may include a power dividing circuit 134, a power amplifying sub-branch 135, and a power amplifying sub-branch 136.
  • the input end of the power dividing circuit 134 is connected to input_3, and the isolated end of the power dividing circuit 134 Connect the load.
  • the through end 1341 of the power dividing circuit 134 is connected to the input end of the power amplifying sub-branch 135, and the coupling end 1342 of the power dividing circuit 134 is connected to the input end of the power amplifying sub-branch 136.
  • the output end of the power amplifying sub-branch 135 is connected to the second port 132, and the output end of the power amplifying sub-branch 136 is connected to the second port 133.
  • the power amplifying sub-branch 135 and the power amplifying sub-branch 136 can work in two power amplifiers in a class C (C) working mode under the same gate bias voltage, and the power amplifier can be used as the peak amplifier 2.
  • the input signal input from input_3 passes through the power dividing circuit 134 and is divided into two signals, one of the two signals is output to the power amplifier sub-branch 135 through the through terminal 1341, and the other signal is output through the coupling terminal 1342 To the power amplifier sub-branch 136, the phase difference between the two signals is 90 degrees.
  • the two signals pass through the power amplifying sub-branch 135 and the power amplifying sub-branch 136 and then output two second signals.
  • the two second signals have the same amplitude and a phase difference of 90 degrees.
  • the power amplifying branch 1N may include a power dividing circuit 1N4, a power amplifying sub-branch 1N5, and a power amplifying sub-branch 1N6, the input terminal of the power dividing circuit 1N4 is connected to input_N, and the isolation terminal of the power dividing circuit 1N4 Connect the load.
  • the through terminal 1N41 of the power dividing circuit 1N4 is connected to the input terminal of the power amplifier sub-branch 1N5, and the coupling terminal 1N42 of the power dividing circuit 1N4 is connected to the input terminal of the power amplifier sub-branch 1N6.
  • the output end of the power amplifying sub-branch 1N5 is connected to the second port 1N2, and the output end of the power amplifying sub-branch 1N6 is connected to the second port 1N3.
  • the power amplifying sub-branch 1N5 and the power amplifying sub-branch 1N6 can work in two power amplifiers in a class C (C) working mode under the same gate bias voltage, and the power amplifier can be used as a peak amplifier (N-1).
  • the input signal input from input_N passes through the power dividing circuit 1N4 and is divided into two signals.
  • One of the two signals is output to the power amplifier sub-branch 1N5 through the through terminal 1N41, and the other signal is output through the coupling terminal 1N42.
  • the phase difference between the two signals is 90 degrees.
  • the two signals pass through the power amplifying sub-branch 1N5 and the power amplifying sub-branch 1N6 and then output two second signals.
  • the two second signals have the same amplitude and a phase difference of 90 degrees.
  • the other second power amplification branches adopt similar connection modes, which will not be illustrated here one by one.
  • the combining circuit 20 is used for power combining the signal output by the first power amplifying branch and the two second signals output by any one of the N-1 second power amplifying branches. Through the above-mentioned connection mode of each second power amplifying branch and the combining circuit, a balanced power amplifying characteristic can be realized.
  • the impedance modulation ratio is all 1, which can ensure the bandwidth of the power amplifying circuit of the present application to avoid bandwidth limitation.
  • FIG. 3 is a schematic structural diagram of another power amplifier circuit provided by an embodiment of the application.
  • the above-mentioned synthesis circuit 20 may include N-1 couplers (211, 212,..., 21(N-1)) and N-1 impedance matching circuits (221, 222,..., 22(N-1)).
  • An impedance matching circuit is arranged between two adjacent couplers of the N-1 couplers, and an impedance matching circuit is arranged between the output end of the power amplifier circuit and one coupler.
  • the isolated end of the first coupler of the N-1 couplers is connected to the output end of the first power amplifier branch, and the two balanced ends of each coupler of the N-1 couplers are connected to a second Power amplifier branch.
  • the isolation end of the coupler 211 is connected to the output end of the power amplifying branch 11, and one of the two balanced ends of the coupler 211 is connected to the second end of the power amplifying branch 12.
  • the port 122 is connected, and the other balanced end of the two balanced ends of the coupler 211 is connected to the second port 123 of the power amplifying branch 12.
  • the output terminal of the coupler 211 is connected to the isolation terminal of the coupler 212 through an impedance matching circuit 221.
  • One of the two balanced ends of the coupler 212 is connected to the second port 132 of the power amplifying branch 13, and the other of the two balanced ends of the coupler 212 is connected to the second port of the power amplifying branch 13 133 connections.
  • the output terminal of the coupler 212 is connected to the isolation terminal of the coupler 213 through an impedance matching circuit 222.
  • one of the two balanced ends of the coupler 21 (N-1) is connected to the second port 1N2 of the power amplifier branch 1N, and one of the two balanced ends of the coupler 21 (N-1)
  • the other balanced terminal is connected to the second port 1N3 of the power amplifying branch 1N.
  • the output terminal of the coupler 21 (N-1) is connected to the output terminal 30 through an impedance matching circuit 22 (N-1).
  • the coupler 211 is used for power synthesis of the signal output by the power amplifying branch 11 and the two second signals of the power amplifying branch 12, and the coupler 212 is used for the signal input from the isolated end of the coupler 212 and the power amplifying branch
  • the two second signals of 13 are combined for power,..., the coupler 21 (N-1) is used to input the signal from the isolated end of the coupler 21 (N-1), and the two second signals of the power amplifying branch 1N
  • the signal undergoes power synthesis.
  • the coupler 212 Since the signal input from the isolated end of the coupler 212 is the signal output by the coupler 211 after power combining the signal output by the power amplifier branch 11 and the two second signals of the power amplifier branch 12, in other words, the coupler 212 It is used to perform power synthesis on the signal of the power amplifying branch 11, the signal of the power amplifying branch 12, and the signal of the power amplifying branch 13.
  • the coupler 21 (N-1) is used for power combining the signal of the power amplifying branch 11, the signal of the power amplifying branch 12, the power amplifying branch 13,..., and the signal of the power amplifying branch 1N.
  • the impedance matching circuit between two adjacent couplers is used to convert the characteristic impedance of the former coupler into the characteristic impedance of the latter coupler.
  • the characteristic impedances of the aforementioned couplers may be Z 01 , Z 02 , ..., Z 0n-1, respectively .
  • the power amplifier branch 11 is connected to the isolated end of the coupler 211 with a characteristic impedance of Z 01.
  • the impedance matching circuit 221 is used to achieve matching from Z 01 to Z 02 .
  • the impedance matching circuit 222 is used to achieve matching from Z 02 to Z 03 ,..., the impedance matching circuit 22 (N-1) is used to achieve matching from Z 0n-1 to 50 ohms.
  • 50 is an example for illustration, and the embodiment of the present application is not limited thereto.
  • the characteristic impedance of each of the N-1 couplers is based on the maximum value of the power tube in the first power amplifying branch and the second power amplifying branch in the Class B (B) working mode.
  • the optimal impedance is determined. That is, the characteristic impedance of each coupler can be optimized according to the optimal impedance of the power tube in the first power amplifier branch and the second power amplifier branch in the Class B working mode to achieve optimal matching, so as to give full play to the implementation of this application. Example of the performance of the power amplifier circuit.
  • the characteristic impedance of the coupler 211 may be determined according to the optimal impedance of the power tubes in the power amplifying branch 11 and the power amplifying branch 12 in the B (B) working mode.
  • the optimal impedance can be determined using the following formula (1).
  • Ropt is the optimal impedance
  • Vdd is the drain bias voltage
  • Vknee is the knee voltage of the power tube
  • Psat is the saturated output power of the power tube.
  • any one of the foregoing impedance matching circuits may be at least one of a low-pass filter circuit, a high-pass filter circuit, a resonance circuit, or a microstrip line.
  • the characteristic impedance of the coupler in the synthesis circuit can be determined according to the optimal impedance of the power tube in the power amplifier branch, which can improve the performance of the power amplifier circuit of the present application.
  • N 3 as an example to illustrate the power amplifier circuit of the embodiment of the present application.
  • the three input terminals are input_1, input_2, and input_3.
  • the three power amplification branches are power amplification branch 11, power amplification branch 12, and power amplification branch 13, respectively.
  • the power amplifying branch 11 is a power amplifier, that is, as a main amplifier.
  • the power amplifying branch 12 includes a power dividing circuit 124, a power amplifying sub-branch 125, and a power amplifying sub-branch 126.
  • the power dividing circuit 124 is a coupler, which is used for power distribution, the power amplifying sub-branch 125 and the power amplifying
  • the sub-branch 126 is a power amplifier with the same gate bias voltage, and the two power amplifiers can be used as two peak amplifiers 1.
  • the power amplifier sub-branch 125 and the power amplifier sub-branch 126 are connected to the coupler 211, the output end of the coupler 211 is connected to the impedance matching circuit 221, and the output end of the impedance matching circuit 221 is connected to the isolation end of the coupler 212.
  • the power amplifying branch 13 includes a power dividing circuit 134, a power amplifying sub-branch 135, and a power amplifying sub-branch 136.
  • the power dividing circuit 134 is a coupler, which is used for power distribution, the power amplifying sub-branch 135 and the power amplifying
  • the sub-branch 136 is a power amplifier with the same gate bias voltage, and the two power amplifiers can be used as two peak amplifiers 2.
  • the power amplifying sub-branch 135 and the power amplifying sub-branch 136 are connected to the coupler 212, the output end of the coupler 212 is connected to the impedance matching circuit 222, and the output end of the impedance matching circuit 222 is connected to the output end.
  • the characteristic impedance of the power dividing circuit 124 and the power dividing circuit 134 may be 50 ohms, the characteristic impedance of the coupler 211 is Z 01 , and the characteristic impedance of the coupler 212 is Z 02 .
  • the main amplifier works in AB/B class, and only the main amplifier works until saturation.
  • the peak amplifier 1 is turned on, the peak amplifier 2 is still in the off state, and the main amplifier remains in the saturated state until the peak amplifier 1 reaches the saturated state.
  • the peak amplifier 1 reaches saturation, the peak amplifier 2 is turned on, and the main amplifier and the peak amplifier 1 remain saturated until the main amplifier, the peak amplifier 1, and the peak amplifier 2 all reach saturation.
  • BO1 log 10 ((Psat_Main+2 ⁇ Psat_Peak1)/(Psat_Main+2 ⁇ Psat_Peak1+2 ⁇ Psat_Peak2)) ⁇ -4.3dB
  • BO2 log 10 (Psat_Main/(Psat_Main+2 ⁇ Psat_Peak1+2 ⁇ Psat_Peak2)) ⁇ -8.45dB
  • Psat_Main represents the saturated output power of the main amplifier
  • Psat_Peak1 represents the saturated output power of the peak amplifier 1
  • Psat_Peak2 represents the saturated output power of the peak amplifier 2.
  • the power amplifier circuit of the three-way power amplifier branch of the embodiment of the present application can achieve an impedance modulation ratio of 1 under the same power back-off, which can fully expand the working bandwidth of the power amplifier circuit.
  • the working bandwidth of the power amplifier circuit of the application embodiment depends only on the working bandwidth of the power tube and the working bandwidth of the coupler.
  • FIG. 5 is a schematic structural diagram of a transmitter provided by an embodiment of this application. As shown in FIG. 5, the transmitter may include: the power amplifier circuit involved in any one of the above-mentioned FIGS. 1 to 4 of this application.
  • FIG. 6 is a schematic structural diagram of a network device provided by an embodiment of the application.
  • the network device includes a transceiver 61, a processor 62, and a memory 63.
  • the transceiver may include the above-mentioned FIGS. 1 to FIG. 4.
  • the power amplifier circuit involved in any of the embodiments. For its implementation principles and technical effects, please refer to the explanations of the foregoing embodiments, which will not be repeated here.
  • processors mentioned in the embodiments of the present application may be a central processing unit (Central Processing Unit, CPU), or other general-purpose processors, digital signal processors (Digital Signal Processors, DSPs), and application-specific integrated circuits (Central Processing Unit, CPU).
  • CPU Central Processing Unit
  • DSPs Digital Signal Processors
  • CPU Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • the general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like.
  • the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory can be read-only memory (Read-Only Memory, ROM), programmable read-only memory (Programmable ROM, PROM), erasable programmable read-only memory (Erasable PROM, EPROM), and electrically available Erase programmable read-only memory (Electrically EPROM, EEPROM) or flash memory.
  • the volatile memory may be random access memory (Random Access Memory, RAM), which is used as an external cache.
  • RAM static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous dynamic random access memory
  • DDR SDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • Enhanced SDRAM, ESDRAM Enhanced Synchronous Dynamic Random Access Memory
  • Synchronous Link Dynamic Random Access Memory Synchronous Link Dynamic Random Access Memory
  • DR RAM Direct Rambus RAM
  • the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component
  • the memory storage module

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Abstract

一种功率放大电路、发射器以及网络设备。功率放大电路包括：N个输入端、N个功率放大支路（11，12，13，…，1N）、一个合成电路（20）和一个输出端（30），N个输入端分别与N个功率放大支路（11，12，13，…，1N）中的一个功率放大支路连接，每个功率放大支路与合成电路（20）连接，合成电路（20）还与输出端（30）连接，每个输入端用于输入一个输入信号，N个功率放大支路（11，12，13，…，1N）和合成电路（20）用于对N个输入信号进行功率放大，并产生一个输出信号，输出端（30）用于输出输出信号，其中，N个功率放大支路（11，12，13，…，1N）包括一个第一功率放大支路（11）和N-1个第二功率放大支路（12，13，…，1N），第一功率放大支路（11）工作在甲乙类或乙类工作模式，N-1个第二功率放大支路（12，13，…，1N）工作在不同栅极偏置电压下的丙类工作模式，N-1个第二功率放大支路（12，13，…，1N）的栅极偏置电压依次减小，N为大于2的正整数。该功率放大电路具有宽带且高效率的特点。

Description

功率放大电路、发射器以及网络设备 技术领域
本申请涉及通信领域，尤其涉及通信领域中的功率放大电路、发射器以及网络设备。
背景技术
随着无线通信技术的飞速发展，无线通信系统对信道容量和数据传输速率提出了越来越高的要求。现在和未来的无线通信系统要求功率放大器具备宽带、多带特性，既要兼顾同一通信标准下的多个频段，还应兼容不同的通信标准，其工作频段零碎，且信号带宽也越来越宽。另外，功率放大器是收发信机的主要耗能模块，其能耗占据无线通信系统很高的比重，提升功率放大器的效率，降低能耗直接影响系统的散热问题，同时也影响电源的带载能力。所以，拓展功率放大器的工作带宽和提升功率放大器的工作效率，是无线通信系统的关键技术。
两路Doherty(DHT)基于有源负载调制机理，有效的提升功率放大电路的回退效率，已被广泛运用在移动基站中。采用3路，4路等N路DHT，可以进一步拓展功率回退或者产生多个高效率点，从而进一步提升功放效率。
然而，该N路DHT，往往由于功率管的阻抗调制比较大，其工作带宽受限，无法在大功率超宽带功率放大电路中运用。
发明内容
本申请提供一种功率放大电路、发射器以及网络设备，以使得功率放大电路具有宽带且高效率的特点。
第一方面，本申请实施例提供一种功率放大电路，其该功率放大电路可以包括：N个输入端、N个功率放大支路、一个合成电路和一个输出端。N个输入端分别与N个功率放大支路中的一个功率放大支路连接，每个所述功率放大支路与合成电路连接，合成电路还与该输出端连接，每个输入端用于输入一个输入信号。N个功率放大支路和合成电路用于对N个输入信号进行功率放大和合成，并产生一个输出信号。该输出端用于输出该输出信号。其中，该N个功率放大支路包括一个第一功率放大支路和N-1个第二功率放大支路，该第一功率放大支路工作在甲乙类或乙类工作模式，该N-1个第二功率放大支路工作在不同栅极偏置电压下的丙类工作模式，该N-1个第二功率放大支路的栅极偏置电压依次减小，N为大于2的正整数。
本实现方式，由于第一功率放大支路工作在甲乙类或乙类工作模式，N-1个第二功率放大支路工作在不同栅极偏置电压下的丙类工作模式，N个功率放大支路依次开启，并且依次达到饱和，所以可以实现在不同的功率回退下产生多个高效率点，提升回退效率，并且由于N个功率放大支路之间不存在负载牵引，所以阻抗调制比为1，从而可以保证本申请的功率放大电路的工作带宽，使得该功率放大电路具有宽带且高效率的特点。
在一种可能的设计中，每个所述第二功率放大支路包括一个第一端口和两个第二端口，该第一端口与一个输入端连接，该两个第二端口分别与该合成电路连接。每个第二功率放大支路用于对一个所述输入信号进行功率分配和功率放大，并产生两个第二信号，该两个第二信号中的每个第二信号通过一个第二端口输出至合成电路。其中，该两个第二信号的幅度相同，且相位相差90度。
本实现方式，通过第二功率放大电路可以实现平衡式功率放大特性。
在一种可能的设计中，每个第二功率放大支路包括一个功分电路和两个功率放大子支路。该功分电路的直通端和耦合端分别与一个功率放大子支路连接。其中，该两个功率放大子支路工作在相同偏置下的丙类工作模式。
本实现方式，第一功率放大支路和各个第二功率放大支路之间不存在负载牵引，因此阻抗调制比均为1，可以保证本申请的功率放大电路的带宽，以避免带宽受限。
在一种可能的设计中，该合成电路包括N-1个耦合器和N-1个阻抗匹配电路。该N-1个耦合器中的相邻两个耦合器之间设置有一个阻抗匹配电路，该功率放大电路的输出端与一个耦合器之间设置有一个阻抗匹配电路。该N-1个耦合器中的第一个耦合器的隔离端与该第一功率放大支路的输出端连接，该N-1个耦合器中的每个耦合器的两个平衡端分别连接一个第二功率放大支路。
在一种可能的设计中，相邻两个耦合器之间的阻抗匹配电路用于将相邻两个耦合器中的前一个耦合器的特征阻抗转换为后一个耦合器的特征阻抗。
在一种可能的设计中，N-1个耦合器中的每个耦合器的特征阻抗为根据第一功率放大支路和第二功率放大支路中功率管在乙类工作模式下的最优阻抗确定的。
本实现方式，合成电路中的耦合器的特征阻抗可以根据功率放大支路中的功率管的最优阻抗确定，可以提升本申请的功率放大电路的性能。
在一种可能的设计中，该阻抗匹配电路包括低通滤波电路、高通滤波电路、谐振电路或微带线中至少一项。
在一种可能的设计中，该第一功率放大支路包括功率放大器。
在一种可能的设计中，该第一功率放大支路包括Doherty电路，该Doherty电路的输入端与该功率放大电路的输入端连接，该Doherty电路的输出端与该合成电路连接。
在一种可能的设计中，该第一功率放大支路达到电压和电流饱和状态，早于该第二功率放大支路达到电压和电流饱和状态。
第二方面，本申请实施例提供一种发射器，包括如第一方面任一项所述的功率放大电路。
第二方面，本申请实施例提供一种网络设备，该网络设备包括收发器、处理器和存储器，该收发器包括如第一方面任一项所述的功率放大电路。
本申请的功率放大电路、发射器以及网络设备，该功率放大电路包括N个输入端、N个功率放大支路、一个合成电路和一个输出端，N个输入端分别与N个功率放大支路中的一个功率放大支路连接，每个功率放大支路与合成电路连接，合成电路还与输出端连接，每个输入端用于输入一个输入信号，N个功率放大支路和合成电路用于对N个输入信号进行功率放大，并产生一个输出信号，输出端用于输出输出信号，其中，N个功率放大支路包括一个第一功率放大支路和N-1个第二功率放大支路，第一功率 放大支路工作在甲乙类或乙类工作模式，N-1个第二功率放大支路工作在不同栅极偏置电压下的丙类工作模式，N-1个第二功率放大支路的栅极偏置电压依次减小，N为大于2的正整数。由于N个功率放大支路依次开启，且依次达到饱和，所以可以实现在不同的功率回退下产生多个高效率点，提升回退效率，并且由于N个功率放大支路之间不存在负载牵引，所以阻抗调制比为1，从而可以保证本申请的功率放大电路的工作带宽，使得该功率放大电路具有宽带且高效率的特点。
附图说明
图1为本申请实施例提供的一种功率放大电路的结构示意图；
图2为本申请实施例提供的另一种功率放大电路的结构示意图；
图3为本申请实施例提供的另一种功率放大电路的结构示意图；
图4为本申请实施例提供的另一种功率放大电路的结构示意图；
图5为本申请实施例提供的一种发射器的结构示意图；
图6为本申请实施例提供的一种网络设备的结构示意图。
具体实施方式
本申请的术语“第一”、“第二”等仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元。方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。在本申请实施例的描述中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请实施例中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
应当理解，在本申请中，“至少一个(项)”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系，例如，“A和/或B”可以表示：只存在A，只存在B以及同时存在A和B三种情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，“a和b”，“a和c”，“b和c”，或“a和b和c”，其中a，b，c可以是单个，也可以是多个。
本申请实施例提供一种功率放大电路，该功率放大电路具有宽带且高效率的特点，既能在不同的功率回退下产生多个高效率点，提升回退效率，又能保证每个功率管的阻抗调制比为1，其具体结构可以参见下述实施例的解释说明。
图1为本申请实施例提供的一种功率放大电路的结构示意图，如图1所示，该功率放大电路可以包括：N个输入端、N个功率放大支路、一个合成电路20和一个输出端30。
该N个输入端分别为输入_1、输入_2、输入_3、……、输入_N。N个功率放大支路分别为功率放大支路11、功率放大支路12、……、功率放大支路1N。
该N个输入端分别与N个功率放大支路中的一个功率放大支路连接，每个功率放大支路与合成电路20连接，合成电路20还与输出端连接。例如，如图1所示，输入_1与功率放大支路11连接，输入_2与功率放大支路12连接，输入_3与功率放大支路13连接，依此类推，输入_N与功率放大支路1N连接，每个功率放大电路的输出端与合成电路20的输入端连接，合成电路的输出端与输出端30连接。
每个输入端(输入_1、输入_2、输入_3、……、输入_N)用于输入一个输入信号。该N个功率放大支路和该合成电路20用于对N个输入信号进行功率放大和合成，并产生一个输出信号。该输出端30用于输出输出信号。
其中，N个功率放大支路包括一个第一功率放大支路和N-1个第二功率放大支路，该第一功率放大支路工作在甲乙(AB)类或乙(B)类工作模式，该N-1个第二功率放大支路工作在不同栅极偏置电压下的丙(C)类工作模式，该N-1个第二功率放大支路的栅极偏置电压依次减小，N为大于2的正整数。即如图1所示，功率放大支路11为第一功率放大支路，功率放大支路12、功率放大支路13、……、功率放大支路1N为该N-1个第二功率放大支路，且功率放大支路12、功率放大支路13、……、功率放大支路1N的栅极栅极偏置电压依次减小。
在一些实施例中，上述第一功率放大支路(功率放大支路11)包括一个输入端和一个输入端，该功率放大支路11的输入端与输入_1连接，该功率放大支路11的输出端与合成电路20的输入端连接。
在一些实施例中，每个第二功率放大支路(功率放大支路12、功率放大支路13、……、功率放大支路1N)包括一个第一端口和两个第二端口，第一端口与一个输入端连接，两个第二端口分别与合成电路20连接。每个第二功率放大支路(功率放大支路12、功率放大支路13、……、功率放大支路1N)用于对一个输入信号进行功率分配和功率放大，并产生两个第二信号，两个第二信号中的每个第二信号通过一个第二端口输出至合成电路20。其中，两个第二信号的幅度相同，且相位相差90度。
举例而言，功率放大支路12包括一个第一端口121和两个第二端口(122、123)，第一端口121与输入_2连接，第二端口122和第二端口123分别与合成电路20连接。功率放大支路12用于对从输入_2输入的输入信号进行功率分配和功率放大，并产生两个第二信号，通过第二端口122和第二端口123将两个第二信号输出给合成电路20。功率放大支路13包括一个第一端口131和两个第二端口(132、133)，第一端口131与输入_3连接，第二端口132和第二端口133分别与合成电路20连接。功率放大支路13用于对从输入_3输入的输入信号进行功率分配和功率放大，并产生两个第二信号，通过第二端口132和第二端口133将两个第二信号输出给合成电路20。功率放大支路1N包括一个第一端口1N1和两个第二端口(1N2、1N3)，第一端口1N1与输入_N连接，第二端口1N2和第二端口1N3分别与合成电路20连接。功率放大支路1N用于对从输入_N输入的输入信号进行功率分配和功率放大，并产生两个第二信号，通过第二端口1N2和第二端口1N3将两个第二信号输出给合成电路20。其他第二功率放大支路采用与功率放大支路12、功率放大支路13或功率放大支路1N相同的连接方 式，此处不一一举例说明。
合成电路20用于对上述功率放大支路11的输出端、第二端口122、第二端口123、第二端口132、第二端口133、……、第二端口1N2和第二端口1N3的输出信号进行功率合成，并通过输出端30输出。
对本申请实施例的功率放大电路的工作原理进行示意性解释说明，由于功率放大支路11在甲乙(AB)类或乙(B)类工作模式，功率放大支路12、功率放大支路13、……、功率放大支路1N在丙(C)类工作模式，且各个第二功率放大支路(功率放大支路12、功率放大支路13、……、功率放大支路1N)的栅极偏置电压依次减小，从而使得功率放大支路11、功率放大支路12、功率放大支路12、……、功率放大支路1N依次开启，并且依次达到饱和。例如，首先，功率放大支路11工作，功率放大支路12、功率放大支路13、……、以及功率放大支路1N均处于关闭状态。当功率放大支路11达到饱和状态后，功率放大支路12开启，功率放大支路13、……、以及功率放大支路1N仍处于关闭状态，功率放大支路11保持饱和状态不变。当功率放大支路12达到饱和状态后，功率放大支路13开启，功率放大支路14、……、以及功率放大支路1N仍处于关闭状态，功率放大支路11和功率放大支路12保持饱和状态不变。以此类推，直至各个功率放大支路(功率放大支路14、……、以及功率放大支路1N)均达到饱和状态，根据上述工作原理，会在不同的回退点产生高效率点，例如，共产生N个高效率点，从而提升功率回退效率和调制波效率。
一种可实现方式，该第一功率放大支路包括功率放大器，该功率放大器可以作为主放大器。另一种可实现方式，第一功率放大支路包括Doherty电路，该Doherty电路的输入端与功率放大电路的输入端(输入_1)连接，Doherty电路的输出端与合成电路20连接。
上述第一功率放大支路达到电压和电流饱和状态，早于第二功率放大支路达到电压和电流饱和状态。
本实施例的功率放大电路包括N个输入端、N个功率放大支路、一个合成电路和一个输出端，N个输入端分别与N个功率放大支路中的一个功率放大支路连接，每个功率放大支路与合成电路连接，合成电路还与输出端连接，每个输入端用于输入一个输入信号，N个功率放大支路和合成电路用于对N个输入信号进行功率放大，并产生一个输出信号，输出端用于输出输出信号，其中，N个功率放大支路包括一个第一功率放大支路和N-1个第二功率放大支路，第一功率放大支路工作在甲乙类或乙类工作模式，N-1个第二功率放大支路工作在不同栅极偏置电压下的丙类工作模式，N-1个第二功率放大支路的栅极偏置电压依次减小，N为大于2的正整数。由于N个功率放大支路依次开启，并且依次达到饱和，所以可以实现在不同的功率回退下产生多个高效率点，提升回退效率，并且由于N个功率放大支路之间不存在负载牵引，所以阻抗调制比为1，从而可以保证本申请的功率放大电路的工作带宽，使得该功率放大电路具有宽带且高效率的特点。
需要说明的是，本申请实施例的功率放大电路中的M个输入端可以连接在一个功分电路的输出端，本申请实施例的N个输入信号中的M(M小于或等于N)个输入信号可以是功分电路的M个输出信号。举例而言，发送信号为两通道信号，N＝3，M＝2， 则一个通道信号可以输入至本申请实施例的功率放大电路的一个输入端，另一个通道信号可以输入至功分电路，功分电路将该通道信号分为两个子通道信号，该两个子通道信号可以输入至本申请实施例的功率放大电路的另外两个输入端。
图2为本申请实施例提供的另一种功率放大电路的结构示意图，如图2所示，本实施例在图1所示的功率放大电路的基础上，每个第二功率放大支路(功率放大支路12、功率放大支路13、……、功率放大支路1N)可以包括一个功分电路和两个功率放大子支路，该功分电路的直通端和耦合端分别与一个功率放大子支路连接，其中，该两个功率放大子支路工作在相同偏置下的丙(C)类工作模式。
每一个功分电路用于对输入端(输入_2、输入_3、……、或者输入_N)的输入信号进行功率分配。示例性的，每一个功分电路可以是一个耦合器，例如，50欧姆的耦合器。每一个功率放大子支路用于进行功率放大，其可以是一个功率放大器。
示例性的，功率放大支路12可以包括功分电路124、功率放大子支路125和功率放大子支路126，功分电路124的输入端与输入_2连接，功分电路124的隔离端接负载。功分电路124的直通端1241与功率放大子支路125的输入端连接，功分电路124的耦合端1242与功率放大子支路126的输入端连接。功率放大子支路125的输出端与第二端口122连接，功率放大子支路126的输出端与第二端口123连接。功率放大子支路125和功率放大子支路126可以工作在相同栅极偏置电压下的丙(C)类工作模式的两个功率放大器，该功率放大器可以作为峰值放大器1。
从输入_2输入的输入信号经过该功分电路124，被分成两路信号，该两路信号中的一个信号通过直通端1241输出至功率放大子支路125，另一个信号通过耦合端1242输出至功率放大子支路126，该两路信号的相位差为90度。该两路信号通过功率放大子支路125和功率放大子支路126后输出两个第二信号，该两个第二信号的幅度相同，且相位相差90度。
示例性的，功率放大支路13可以包括功分电路134、功率放大子支路135和功率放大子支路136，功分电路134的输入端与输入_3连接，功分电路134的隔离端接负载。功分电路134的直通端1341与功率放大子支路135的输入端连接，功分电路134的耦合端1342与功率放大子支路136的输入端连接。功率放大子支路135的输出端与第二端口132连接，功率放大子支路136的输出端与第二端口133连接。功率放大子支路135和功率放大子支路136可以工作在相同栅极偏置电压下的丙(C)类工作模式的两个功率放大器，该功率放大器可以作为峰值放大器2。
从输入_3输入的输入信号经过该功分电路134，被分成两路信号，该两路信号中的一个信号通过直通端1341输出至功率放大子支路135，另一个信号通过耦合端1342输出至功率放大子支路136，该两路信号的相位差为90度。该两路信号通过功率放大子支路135和功率放大子支路136后输出两个第二信号，该两个第二信号的幅度相同，且相位相差90度。
示例性的，功率放大支路1N可以包括功分电路1N4、功率放大子支路1N5和功率放大子支路1N6，功分电路1N4的输入端与输入_N连接，功分电路1N4的隔离端接负载。功分电路1N4的直通端1N41与功率放大子支路1N5的输入端连接，功分电 路1N4的耦合端1N42与功率放大子支路1N6的输入端连接。功率放大子支路1N5的输出端与第二端口1N2连接，功率放大子支路1N6的输出端与第二端口1N3连接。功率放大子支路1N5和功率放大子支路1N6可以工作在相同栅极偏置电压下的丙(C)类工作模式的两个功率放大器，该功率放大器可以作为峰值放大器(N-1)。
从输入_N输入的输入信号经过该功分电路1N4，被分成两路信号，该两路信号中的一个信号通过直通端1N41输出至功率放大子支路1N5，另一个信号通过耦合端1N42输出至功率放大子支路1N6，该两路信号的相位差为90度。该两路信号通过功率放大子支路1N5和功率放大子支路1N6后输出两个第二信号，该两个第二信号的幅度相同，且相位相差90度。
其他第二功率放大支路采用类似的连接方式，此处不一一举例说明。
合成电路20用于对第一功率放大支路输出的信号和N-1个第二功率放大支路中任意一个第二功率放大支路输出的两个第二信号进行功率合成。通过上述各个第二功率放大支路的连接方式以及合成电路，可以实现平衡式功率放大特性。
本实施例的第一功率放大支路和各个第二功率放大支路之间不存在负载牵引，因此阻抗调制比均为1，可以保证本申请的功率放大电路的带宽，以避免带宽受限。
图3为本申请实施例提供的另一种功率放大电路的结构示意图，如图3所示，本实施例在图1或图2所示的功率放大电路的基础上，上述合成电路20可以包括N-1个耦合器(211、212、……、21(N-1))和N-1个阻抗匹配电路(221、222、……、22(N-1))。N-1个耦合器中的相邻两个耦合器之间设置有一个阻抗匹配电路，功率放大电路的输出端与一个耦合器之间设置有一个阻抗匹配电路。N-1个耦合器中的第一个耦合器的隔离端与第一功率放大支路的输出端连接，N-1个耦合器中的每个耦合器的两个平衡端分别连接一个第二功率放大支路。
参照图3对其连接结构进行解释说明，耦合器211的隔离端与功率放大支路11的输出端连接，耦合器211的两个平衡端中的一个平衡端与功率放大支路12的第二端口122连接，耦合器211的两个平衡端中的另一个平衡端与功率放大支路12的第二端口123连接。耦合器211的输出端通过阻抗匹配电路221连接至耦合器212的隔离端。
耦合器212的两个平衡端中的一个平衡端与功率放大支路13的第二端口132连接，耦合器212的两个平衡端中的另一个平衡端与功率放大支路13的第二端口133连接。耦合器212的输出端通过阻抗匹配电路222连接至耦合器213的隔离端。
依此类推，耦合器21(N-1)的两个平衡端中的一个平衡端与功率放大支路1N的第二端口1N2连接，耦合器21(N-1)的两个平衡端中的另一个平衡端与功率放大支路1N的第二端口1N3连接。耦合器21(N-1)的输出端通过阻抗匹配电路22(N-1)连接至输出端30。
耦合器211用于对功率放大支路11输出的信号和功率放大支路12的两个第二信号进行功率合成，耦合器212用于对耦合器212的隔离端输入的信号、功率放大支路13的两个第二信号进行功率合成，……，耦合器21(N-1)用于对耦合器21(N-1)的隔离端输入的信号、功率放大支路1N的两个第二信号进行功率合成。由于耦合器212的隔离端输入的信号为耦合器211对功率放大支路11输出的信号和功率放大支路12 的两个第二信号进行功率合成后输出的信号，所以，换言之，耦合器212用于对功率放大支路11的信号、功率放大支路12的信号以及功率放大支路13的信号进行功率合成。耦合器21(N-1)用于对功率放大支路11的信号、功率放大支路12的信号、功率放大支路13、……、以及功率放大支路1N的信号进行功率合成。
在一些实施例，相邻两个耦合器之间的阻抗匹配电路用于将相邻两个耦合器中的前一个耦合器的特征阻抗转换为后一个耦合器的特征阻抗。
上述耦合器(211、212、……、21(N-1))的特征阻抗可以分别为Z 01、Z 02、……、Z 0n-1。功率放大支路11连接在特征阻抗为Z 01的耦合器211的隔离端。阻抗匹配电路221用于实现Z 01至Z 02的匹配。阻抗匹配电路222用于实现Z 02至Z 03的匹配，……，阻抗匹配电路22(N-1)用于实现Z 0n-1至50欧姆的匹配。其中，50为举例说明，本申请实施例不以此作为限制。
在一些实施例中，N-1个耦合器中的每个耦合器的特征阻抗为根据第一功率放大支路和第二功率放大支路中功率管在乙(B)类工作模式下的最优阻抗确定的。即可以根据第一功率放大支路和第二功率放大支路中功率管在乙类工作模式下的最优阻抗优化每个耦合器的特征阻抗，以实现最优匹配，以充分发挥本申请实施例的功率放大电路的性能。
例如，可以根据功率放大支路11和功率放大支路12中功率管在乙(B)类工作模式下的最优阻抗确定耦合器211的特征阻抗。示例性的，最优阻抗可以采用如下公式(1)确定。
Ropt＝0.5*(Vdd-Vknee)^2/Psat      (1)
其中，Ropt为该最优阻抗，Vdd为漏极偏置电压，Vknee为功率管的膝值电压，Psat为功率管的饱和输出功率。
在一些实施例中，上述任意一个阻抗匹配电路可以是低通滤波电路、高通滤波电路、谐振电路或微带线中至少一项。
本实施例，合成电路中的耦合器的特征阻抗可以根据功率放大支路中的功率管的最优阻抗确定，可以提升本申请的功率放大电路的性能。
下面以N＝3为例对本申请实施例的功率放大电路进行举例说明。
图4为本申请实施例提供的另一种功率放大电路的结构示意图，如图4所示，该功率放大电路包括：3(N＝3)个输入端、3个功率放大支路、一个合成电路和一个输出端。
其中，3个输入端分别为输入_1、输入_2和输入_3。3个功率放大支路分别为功率放大支路11、功率放大支路12和功率放大支路13。功率放大支路11为功率放大器，即作为主放大器。功率放大支路12包括功分电路124、功率放大子支路125和功率放大子支路126，功分电路124为耦合器，该耦合器用于进行功率分配，功率放大子支路125和功率放大子支路126为栅极偏置电压相同的功率放大器，该两个功率放大器可以作为两个峰值放大器1。功率放大子支路125和功率放大子支路126与耦合器211连接，耦合器211的输出端与阻抗匹配电路221连接，阻抗匹配电路221的输出端与耦合器212的隔离端连接。功率放大支路13包括功分电路134、功率放大子支 路135和功率放大子支路136，功分电路134为耦合器，该耦合器用于进行功率分配，功率放大子支路135和功率放大子支路136为栅极偏置电压相同的功率放大器，该两个功率放大器可以作为两个峰值放大器2。功率放大子支路135和功率放大子支路136与耦合器212连接，耦合器212的输出端与阻抗匹配电路222连接，阻抗匹配电路222的输出端与输出端连接。
上述功分电路124和功分电路134的特征阻抗可以为50欧姆，耦合器211的特征阻抗为Z 01，耦合器212的特征阻抗为Z 02。
当小功率时，主放大器工作在AB/B类，仅主放大器工作，直到饱和。主放大器饱和后，随后峰值放大器1打开，峰值放大器2仍处于关闭状态，主放大器保持饱和状态，直到峰值放大器1达到饱和状态。当峰值放大器1达到饱和后，峰值放大器2打开，主放大器和峰值放大器1保持饱和状态，直到主放大器、峰值放大器1、峰值放大器2均达到饱和。
由于上述连接关系，使得主放大器与峰值放大器1之间不存在负载牵引，主放大器和峰值放大器1，与峰值放大器2之间不存在负载牵引。
主放大器在第1个高效率点处达到电流饱和，阻抗调制比LPR＝1。峰值放大器1在第2个高效率点处达到电流饱和，阻抗调制比LPR＝1，第3个高效率点出现在满功率处，此时峰值放大器2达到电流饱和。高效率点分别出现在满功率0dB、BO1dB和BO2dB。其BO1和BO2可以采用如下公式计算，假设Psat_Main:Psat_Peak1:Psat_Peak2＝1:0.8:2.2。
BO1＝log 10((Psat_Main+2×Psat_Peak1)/(Psat_Main+2×Psat_Peak1+2×Psat_Peak2))≈-4.3dB
BO2＝log 10(Psat_Main/(Psat_Main+2×Psat_Peak1+2×Psat_Peak2))≈-8.45dB
其中，Psat_Main表示主放大器的饱和输出功率，Psat_Peak1表示峰值放大器1的饱和输出功率，Psat_Peak2表示峰值放大器2的饱和输出功率。
本申请实施例的3路功率放大支路的功率放大电路，相较于3路Doherty，可以在相同的功率回退下，实现阻抗调制比为1，可以充分拓展功率放大电路的工作带宽，本申请实施例的功率放大电路的工作带宽仅取决于功率管的工作带宽和耦合器的工作带宽。
图5为本申请实施例提供的一种发射器的结构示意图，如图5所示，该发射器可以包括：本申请上述图1至图4任一实施例所涉及的功率放大电路。
其实现原理及技术效果可以参见上述实施例的解释说明，此处不再赘述。
图6为本申请实施例提供的一种网络设备的结构示意图，如图6所示，该网络设备包括收发器61、处理器62和存储器63，该收发器可以包括本申请上述图1至图4任一实施例所涉及的功率放大电路。其实现原理及技术效果可以参见上述实施例的解释说明，此处不再赘述。
应理解，本申请实施例中提及的处理器可以是中央处理单元(Central Processing  Unit，CPU)，还可以是其他通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
还应理解，本申请实施例中提及的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DR RAM)。
需要说明的是，当处理器为通用处理器、DSP、ASIC、FPGA或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件时，存储器(存储模块)集成在处理器中。
应注意，本文描述的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种功率放大电路，其特征在于，所述功率放大电路包括：
    N个输入端、N个功率放大支路、一个合成电路和一个输出端；
    所述N个输入端分别与所述N个功率放大支路中的一个功率放大支路连接，每个所述功率放大支路与所述合成电路连接，所述合成电路还与所述输出端连接；
    每个所述输入端用于输入一个输入信号；
    所述N个功率放大支路和所述合成电路用于对N个输入信号进行功率放大和合成，并产生一个输出信号；
    所述输出端用于输出所述输出信号；
    其中，所述N个功率放大支路包括一个第一功率放大支路和N-1个第二功率放大支路，所述第一功率放大支路工作在甲乙类或乙类工作模式，所述N-1个第二功率放大支路工作在不同栅极偏置电压下的丙类工作模式，所述N-1个第二功率放大支路的栅极偏置电压依次减小，N为大于2的正整数。
  2. 根据权利要求1所述的功率放大电路，其特征在于，每个所述第二功率放大支路包括一个第一端口和两个第二端口，所述第一端口与一个输入端连接，所述两个第二端口分别与所述合成电路连接；
    每个所述第二功率放大支路用于对一个所述输入信号进行功率分配和功率放大，并产生两个第二信号，所述两个第二信号中的每个第二信号通过一个所述第二端口输出至所述合成电路；
    其中，所述两个第二信号的幅度相同，且相位相差90度。
  3. 根据权利要求2所述的功率放大电路，其特征在于，每个所述第二功率放大支路包括一个功分电路和两个功率放大子支路；
    所述功分电路的直通端和耦合端分别与一个所述功率放大子支路连接；
    其中，所述两个功率放大子支路工作在相同偏置下的丙类工作模式。
  4. 根据权利要求1至3任一项所述的功率放大电路，其特征在于，所述合成电路包括N-1个耦合器和N-1个阻抗匹配电路；
    所述N-1个耦合器中的相邻两个耦合器之间设置有一个阻抗匹配电路，所述功率放大电路的输出端与一个耦合器之间设置有一个阻抗匹配电路；
    所述N-1个耦合器中的第一个耦合器的隔离端与所述第一功率放大支路的输出端连接，所述N-1个耦合器中的每个耦合器的两个平衡端分别连接一个所述第二功率放大支路。
  5. 根据权利要求4所述的功率放大电路，其特征在于，所述相邻两个耦合器之间的阻抗匹配电路用于将所述相邻两个耦合器中的前一个耦合器的特征阻抗转换为后一个耦合器的特征阻抗。
  6. 根据权利要求5所述的功率放大电路，其特征在于，所述N-1个耦合器中的每个耦合器的特征阻抗为根据所述第一功率放大支路和所述第二功率放大支路中功率管在乙类工作模式下的最优阻抗确定的。
  7. 根据权利要求4至6任一项所述的功率放大电路，其特征在于，所述阻抗匹配电路包括低通滤波电路、高通滤波电路、谐振电路或微带线中至少一项。
  8. 根据权利要求1至7任一项所述的功率放大电路，其特征在于，所述第一功率放大支路包括功率放大器。
  9. 根据权利要求1至7任一项所述的功率放大电路，其特征在于，所述第一功率放大支路包括Doherty电路，所述Doherty电路的输入端与所述功率放大电路的输入端连接，所述Doherty电路的输出端与所述合成电路连接。
  10. 根据权利要求1至9任一项所述的功率放大电路，其特征在于，所述第一功率放大支路达到电压和电流饱和状态，早于所述第二功率放大支路达到电压和电流饱和状态。
  11. 一种发射器，其特征在于，包括如权利要求1至10任一项所述的功率放大电路。
  12. 一种网络设备，其特征在于，所述网络设备包括收发器、处理器和存储器，所述收发器包括如权利要求1至10任一项所述的功率放大电路。
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