WO2021051826A1 - 唤醒电路、唤醒方法 - Google Patents

唤醒电路、唤醒方法 Download PDF

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Publication number
WO2021051826A1
WO2021051826A1 PCT/CN2020/089446 CN2020089446W WO2021051826A1 WO 2021051826 A1 WO2021051826 A1 WO 2021051826A1 CN 2020089446 W CN2020089446 W CN 2020089446W WO 2021051826 A1 WO2021051826 A1 WO 2021051826A1
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Prior art keywords
wake
signal
module
source
xor gate
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English (en)
French (fr)
Inventor
杨倩
姜新
施济杰
张腾
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ZTE Corp
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ZTE Corp
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Priority to EP20865173.7A priority Critical patent/EP3964899A4/en
Priority to US17/614,387 priority patent/US11848669B2/en
Publication of WO2021051826A1 publication Critical patent/WO2021051826A1/zh
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Program-control systems
    • G05B19/02—Program-control systems electric
    • G05B19/04—Program control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Program control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Program-control systems
    • G05B19/02—Program-control systems electric
    • G05B19/04—Program control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Program control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/17744—Structural details of routing resources for input/output signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines

Definitions

  • the present disclosure relates to the technical field of wake-up circuits, in particular to a wake-up circuit and a wake-up method.
  • Telematics BOX abbreviated as car T-BOX
  • the car networking system consists of four parts, the host, the car T-BOX, the mobile APP and the background system.
  • the host is mainly used for audio-visual entertainment in the car and vehicle information display;
  • the car T-BOX is mainly used for communicating with the background system/mobile phone APP to realize the vehicle information display and control of the mobile phone APP.
  • a background system such as the TSP background will send a control command to the vehicle T-BOX.
  • the vehicle T-BOX After the vehicle T-BOX obtains the control command, it sends a control message through the CAN bus and realizes the control message to the vehicle. Control, and finally feedback the operation result to the user's mobile phone APP; this function can help the user to remotely start the vehicle, turn on the air conditioner, and adjust the seat to a suitable position.
  • the main device of the wake-up signal detection in the existing vehicle-mounted T-BOX products is a wake-up circuit including a first comparator.
  • the first comparator is coupled to an input signal and is configured to compare the input signal with a first comparison value.
  • the wake-up circuit includes a second comparator coupled to the input signal and configured to compare the input signal with a second comparison value.
  • the wake-up circuit also includes an exclusive OR gate. The first input of the XOR gate is coupled to the output of the first comparator. The second input of the XOR gate is coupled to the output of the second comparator.
  • the wake-up circuit also includes a tunable charge pump, which is coupled to the output of the XOR gate and is configured to convert the signal from the XOR gate to a DC value to wake up the circuit being monitored; the solution of the wake-up circuit is for a wake-up source
  • a tunable charge pump which is coupled to the output of the XOR gate and is configured to convert the signal from the XOR gate to a DC value to wake up the circuit being monitored; the solution of the wake-up circuit is for a wake-up source
  • the number of comparators used is large, which makes the cost high, and the wake-up circuit can only detect one input signal as a wake-up source, and cannot detect when there are multiple wake-up sources.
  • the embodiments of the present disclosure provide a wake-up circuit and a wake-up method.
  • Several wake-up sources are accessed through one main control module, which reduces the cost of the wake-up circuit and is suitable for detection of multiple wake-up sources.
  • the embodiment of the present disclosure provides a wake-up circuit, including: a wake-up module, connected to a wake-up source, used to detect a wake-up signal sent by the wake-up source, and forward the wake-up signal to a main control module, the wake-up
  • the number of sources is more than one; the main control module is connected to the wake-up module and is used to receive the forwarded wake-up signal, and the number of the main control module is one.
  • the embodiment of the present disclosure also provides a wake-up method, including: using the wake-up circuit to wake up.
  • the embodiment of the present disclosure also provides a wake-up method, including: detecting a wake-up signal sent by the wake-up source, and forwarding the wake-up signal; and receiving the forwarded wake-up signal.
  • the embodiment of the present disclosure also provides a storage medium, the storage medium includes a stored program, wherein the above-mentioned method is executed when the program is running.
  • the embodiment of the present disclosure further provides a processor, the processor is configured to run a program, wherein the above-mentioned method is executed when the program is running.
  • FIG. 1 is a structural diagram of a wake-up circuit according to an embodiment of the disclosure
  • FIG. 2 is a structural diagram of another wake-up circuit according to an embodiment of the disclosure.
  • FIG. 3 is a structural diagram of another wake-up circuit according to an embodiment of the disclosure.
  • FIG. 4 is a structural diagram of another wake-up circuit according to an embodiment of the disclosure.
  • FIG. 5 is a flowchart of a wake-up method according to an embodiment of the disclosure.
  • FIG. 6 is a flowchart of a method for detecting a wake-up signal sent by the wake-up source according to an embodiment of the disclosure
  • FIG. 7 is a wake-up in the form of a pulse signal obtained by calculating the wake-up signal output from the output terminal of the wake-up source and the delayed signal formed after the wake-up signal is delayed by the delay module by the exclusive OR gate of the embodiment of the disclosure.
  • FIG. 8 is a flowchart of another method for detecting a wake-up signal sent by the wake-up source according to an embodiment of the disclosure
  • FIG. 9 is a structural diagram of a wake-up circuit according to an embodiment of the disclosure.
  • FIG. 10 is a coordinate diagram of the voltage curves of the input terminal and the output terminal of the XOR gate according to an embodiment of the disclosure.
  • FIG. 11 is a structural diagram of a wake-up circuit in Embodiment 1 of an embodiment of the disclosure.
  • FIG. 12 is a waveform diagram of voltage changes at the first input terminal A of the XOR gate, the second input terminal B of the XOR gate, and the output terminal Y of the XOR gate in the first embodiment of the disclosed embodiments;
  • FIG. 13 is a structural diagram of the wake-up circuit in the second embodiment of the embodiment of the disclosure.
  • the application scenarios of the wake-up circuit in the embodiment of the present disclosure include: a wake-up circuit of a vehicle-mounted T-BOX, products with multiple wake-up sources, etc., and its application prospects are broad.
  • a wake-up circuit including: a wake-up module 11, connected to a wake-up source, for detecting a wake-up signal sent by the wake-up source, and forwarding the wake-up signal
  • the number of the wake-up source is more than one
  • the main control module 12 is connected to the wake-up module for receiving the forwarded wake-up signal, and the number of the main control module is one.
  • the wake-up module detects the wake-up signal sent by the wake-up source, and forwards the wake-up signal to the main control module.
  • the number of the wake-up source is more than one; the main control module is connected to the main control module.
  • the wake-up module is connected to receive the forwarded wake-up signal, and the number of the main control module is one.
  • several wake-up sources can be accessed through one main control module, so that one main control module can receive the wake-up signals sent by multiple wake-up sources, which reduces the cost of the wake-up circuit and is suitable for multiple wake-up sources.
  • the detection solves the problem that the relatively large number of comparators used for one wake-up source in the related technology makes the cost high, and the wake-up circuit cannot perform detection when there are multiple wake-up sources.
  • the wake-up circuit further includes: an identification module 13, which is connected between the wake-up source connected to the wake-up module and the main control module, and is used for connecting The wake-up signal transmitted by the wake-up source is sent to the main control module for identification.
  • the wake-up signal can be identified by the main control module, and the wake-up signal transmitted by the wake-up source can be distinguished, and the source of the wake-up signal will not be confused.
  • the wake-up module corresponds to the wake-up source to which it is connected, and the wake-up source corresponds to the identification module to which it is connected.
  • the wake-up circuit further includes: a delay module 14, which is connected between the wake-up source connected to the wake-up module and the wake-up module, and is used to The wake-up signal transmitted by the wake-up source is delayed and transmitted to the main control module in the form of a pulse signal, and the wake-up module corresponds to the delay module connected to it one-to-one.
  • a delay module 14 which is connected between the wake-up source connected to the wake-up module and the wake-up module, and is used to The wake-up signal transmitted by the wake-up source is delayed and transmitted to the main control module in the form of a pulse signal, and the wake-up module corresponds to the delay module connected to it one-to-one.
  • each time a different wake-up module transmits the wake-up signal it can be transmitted to the main control module in the form of a pulse signal after the delay of the corresponding delay module, so that The main control module effectively receives the wake-up signal transmitted in the form of a pulse signal, and achieves the wake-up function of the wake-up signal more accurately.
  • the wake-up circuit further includes: an isolation module 15, which is connected between the wake-up module and the main control module, and is used to isolate the main control module For the backflow current transmitted by the wake-up module, the wake-up module has a one-to-one correspondence with the isolation module connected to it.
  • the use of the isolation module prevents the main control module from sending backflow current to the corresponding wake-up module to cause damage to the wake-up module.
  • the wake-up module is an XOR gate
  • the first input terminal of the XOR gate is connected to the output terminal of the wake-up source
  • the second input terminal of the XOR gate is connected to the delay
  • One end of the module is connected
  • the other end of the delay module is connected to the output end of the wake-up source
  • the output ends of all the XOR gates are connected to one pin of the main control module
  • the XOR gate It is used to calculate the wake-up signal output from the output terminal of the wake-up source and the delayed signal formed after the wake-up signal is delayed by the delay module, and then transmit the calculation to the main control module in the form of a pulse signal.
  • the main control module can recognize the wake-up signal and achieve the purpose of identifying several wake-up signals, so that there are multiple wake-up signals.
  • the source is awakened, the purpose of detecting several awakening signals transmitted by it can be performed, and the XOR gate is low in cost.
  • the main control module is an MCU, and the pin of the MCU connected to the output terminals of all the XOR gates is used to receive a wake-up signal transmitted in the form of a pulse signal; the MCU It also includes one-to-one corresponding pins to the identification module, one end of the identification module is connected to the corresponding pin of the MCU, and the other end of the identification module is connected to the output end of the corresponding wake-up source.
  • the main control module uses an MCU, which is a single-chip microcomputer, and is low in price.
  • One pin of the MCU is used to receive wake-up signals transmitted by several wake-up sources, and a main control module can be used to access several wake-up sources.
  • one main control module can receive the wake-up signals sent by multiple wake-up sources, which reduces the cost of the wake-up circuit and is suitable for detection of multiple wake-up sources.
  • the two ends of the identification module are respectively connected to the corresponding wake-up source and the corresponding MCU pin, so that the wake-up signal sent by the output terminal of the wake-up source can be transmitted to the corresponding MCU pin via the identification module, which is beneficial to the MCU Identify the wake-up source from which the wake-up signal is sent.
  • the identification module is a first resistor, and the first resistor is used to limit the current of the wake-up signal sent from the output terminal of the wake-up source to the corresponding pin of the MCU and then send it to all Identify in the MCU.
  • the signal sent to the MCU is identified after the current limit, so that the signal sent to the MCU is safer and more reliable.
  • the delay module is an RC delay circuit
  • the RC delay circuit includes a second resistor and a first capacitor; one end of the second resistor is connected to the output end of the wake-up source, so The other end of the second resistor and one pole of the first capacitor are connected to the second input end of the XOR gate, and the other pole of the first capacitor is grounded.
  • the isolation module is a diode, the anode of the diode is connected to the output terminal of the XOR gate, and the cathode of all the diodes is connected to a pin of the MCU.
  • connection manner of the diode can effectively prevent the MCU from sending backflow current to the corresponding wake-up module and causing damage to the XOR gate.
  • An embodiment of the present disclosure also provides a wake-up method, including: using the wake-up circuit to wake up.
  • the wake-up circuit includes: a wake-up module, connected to a wake-up source, for detecting a wake-up signal sent by the wake-up source, and forwarding the wake-up signal to the main control module, the number of the wake-up source is more than one
  • the main control module, connected to the wake-up module, is used to receive the forwarded wake-up signal, and the number of the main control module is one.
  • a wake-up method is also provided. As shown in FIG. 5, corresponding to the realization principle of the wake-up circuit, the method includes: step 101, detecting a wake-up signal sent by the wake-up source, and combining the wake-up signal Forward; Step 102, receive the forwarded wakeup signal.
  • the detecting the wake-up signal sent by the wake-up source includes: Step 201: The output terminal of the wake-up source outputs a wake-up signal; Step 202: The output wake-up signal Are respectively transmitted to the first input terminal of the XOR gate and the RC delay circuit; step 203: after the RC delay circuit delays the wake-up signal to form the delay signal, the XOR The door handles the wake-up signal output from the output terminal of the wake-up source and the delayed signal formed after the wake-up signal is delayed by the delay module to obtain a wake-up signal in the form of a pulse signal.
  • the XOR gate performs operations on the wake-up signal output from the output terminal of the wake-up source and the delayed signal formed after the wake-up signal is delayed by the delay module to obtain a pulse signal.
  • the wake-up signal in the form includes: step 301, before the outputted wake-up signal is respectively transmitted to the first input terminal of the XOR gate and the RC delay circuit, the first of the XOR gate The input terminal is the same as the input level of the second input terminal of the XOR gate, and the output terminal of the XOR gate outputs a low level; in step 302, the wake-up signals at the output are respectively transmitted to the XOR gate.
  • step 303 after the delay period, the input levels of the first input terminal of the XOR gate and the second input terminal of the XOR gate are the same,
  • the output terminal of the exclusive OR gate outputs a low level, thereby forming a wake-up signal in the form of a pulse signal.
  • the pin used by the MCU to receive the wake-up signal can only detect the rising edge of the wake-up signal. If the pin is directly connected to the output terminals of multiple wake-up sources, only one wake-up signal is recognized. The high level of the output terminal of the wake-up source that is received for the first time will maintain a continuous high level, so the next wake-up signal cannot be detected.
  • Forming a wake-up signal in the form of a pulse signal allows the pin to receive the previous wake-up signal with only one rising edge and convert it into a pulse signal, so that the MCU can recognize the wake-up signal.
  • the detecting the wake-up signal sent by the wake-up source further includes: Step 401: The wake-up signal output by the output terminal of the wake-up source also passes through the first resistance limit. After streaming, it is transmitted to the corresponding pin of the MCU; step 402: the MCU determines the wake-up signal transmitted by the corresponding wake-up source by transmitting to the pin of the corresponding MCU.
  • the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, of course, it can also be implemented by hardware, but in many cases the former is Better implementation.
  • the technical solution of the present disclosure essentially or the part that contributes to the existing technology can be embodied in the form of a software product, and the computer software product is stored in a storage medium (such as ROM/RAM, magnetic disk, The optical disc) includes several instructions to make a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) execute the methods described in the various embodiments of the present disclosure.
  • the wake-up circuit of this embodiment includes an MCU as the main control module, which is marked as D(N+1) in FIG. 9; N exclusive OR gates are marked as D1-DN; N identification modules, which are marked as identification module 1-identification module N in Figure 9; N delay modules, which are marked as delay module 1-delay module N on Figure 9; N isolation modules are marked as isolation module 1-isolation module path N in FIG. 9, where N is a positive integer, indicating the number of exclusive OR gates, delay modules, identification modules, and isolation modules.
  • the MCU in this embodiment is marked as D(N+1) in Figure 9 as the main control module of the wake-up circuit. Its main function is to use a separate pin WKUP to receive the wake-up signal.
  • each different wake-up The wake-up signal sent by the source is connected to the pins of different N MCUs.
  • the pins of these different N MCUs are marked as CHECK1-CHECKN in Figure 9; therefore, one of the wake-up signals is on the corresponding MCU pin.
  • the MCU can detect which wake-up source sends the wake-up signal; all the pins can be the GPIO pins of the MCU.
  • the XOR gate marked D1-DN in this embodiment mainly functions to change the wake-up signal sent by the wake-up source into a pulse signal.
  • the XOR gate (generally, the XOR gate function logic circuit device has 5 pins, There are also multiple pins, but the basic principle is the same) Among them, there are two XOR gate input pins as the first input terminal and the second input terminal, and one XOR gate output pin as the output terminal.
  • the delay module is mainly used to delay the wake-up signal of the input wake-up source, thereby making the two inputs of the exclusive OR gate
  • the level of the XOR gate is the same, and the XOR gate outputs a low level; when there is a wake-up signal, the levels of the two input terminals of the XOR gate are different during the delay time when the delay module is active. , So that the output terminal of the XOR gate is high.
  • the delay module fails, the levels of the two input terminals of the XOR gate are the same, so the output terminal of the XOR gate outputs low level, thus forming
  • the wake-up signal in the form of a pulse signal can be recognized by the MCU.
  • the identification module is an identification signal generated by the input wake-up signal, and the identification signal is input to the pins marked CHECK1-CHECKN of the MCU.
  • the one-to-one input is used for the MCU to identify the specific wake-up signal from Wake-up source; in this embodiment, the isolation module is to isolate the wake-up signal of the pin marked WKUP of multiple input MCUs, which can generally be a diode or other devices that can prevent current backflow.
  • the delay module uses an RC delay circuit including a second resistor and a first capacitor.
  • T2-T1 -R*C*Ln((E-V)/E) (1)
  • R is the resistance value of the second resistor, in ⁇
  • C is the capacitance value of the first capacitor, in F
  • E is the high-level voltage value input to the second input terminal of the XOR gate
  • V is the voltage value of the level reached during the charging of the first capacitor.
  • the capacitance of the second input terminal of the XOR gate is fully charged, and the level of the second input terminal of the XOR gate also becomes high. Therefore, at time T2, due to the input of the two input terminals of the XOR gate The levels are all high, so the output terminal of the XOR gate outputs a low level, thereby forming a pulse signal, which is convenient for the MCU to recognize the wake-up signal.
  • Each module in the embodiment of the present disclosure can be implemented in the form of hardware, software, or a combination, and can be a circuit of various forms, which will be described in detail below through specific implementations:
  • the wake-up signal sent by the wake-up source of this embodiment is: the pin MCU_3V3 outputting a 3.3V voltage of the external single-chip and the supply potential KL30 output by the external voltage source is the wake-up signal output by the comparator D3 POWER_LOW, because the supply potential KL30 is continuously decreasing during use, the voltage difference between the start supply potential KL30 and the 3.3V output pin MCU_3V3 is large, and the comparator D3 outputs a low level.
  • the comparator D3 When the supply potential KL30 voltage value drops to an alarm When the voltage value is lower than the voltage value of the pin MCU_3V3 that outputs the 3.3V voltage, the comparator D3 outputs a high level, that is, the wake-up signal POWER_LOW is a rising edge waveform from low to high.
  • the exclusive OR gate The voltage value of the first input terminal A of the XOR gate quickly becomes 1.8V, and the second input terminal B of the XOR gate is connected to an RC delay circuit composed of a second resistor R1 and a first capacitor C1.
  • the second resistor The resistance value of R1 is 100 ⁇
  • the capacitance value of the first capacitor C1 is 1000*1/1000000
  • the high-level voltage input to the second input terminal of the exclusive OR gate is 1.8V
  • the first capacitor is being charged
  • the voltage value of the reached level is 1.6V, so according to formula (1), the duration T of the delay period of the RC delay circuit is calculated as follows:
  • the general logic circuit MCU judges that the high level has a range, it reaches the lowest low voltage judged to be high level, and the XOR gate D1 can be judged to be high level, and the second input terminal of the XOR gate is delayed When it reaches 1.6V in 0.2197 seconds, the XOR gate D1 determines that the second input terminal of the XOR gate is high, so the wake-up signal POWER_DETEC signal is for the output terminal of the XOR gate to output 0V before being sent, and there is 0.2197 time after being sent Lower the output terminal of the XOR gate to a high level, and then let the output terminal of the XOR gate output 0V, specifically the first input terminal A of the XOR gate, the second input terminal B of the XOR gate and the XOR gate
  • the waveform of the voltage change at the output terminal Y is shown in Figure 12.
  • the first resistor of the identification module is marked as R2, and the XOR gate also has a power supply terminal marked VCC and GND and a grounded ground terminal.
  • the power supply terminal is output by the external single-chip microcomputer.
  • the pin MCU_3V3 is powered, the isolation module is a diode VT1, and the MCU is marked as D2.
  • the MCU pin WKUP and pin GPIO are used to receive the wake-up signal POWER_DETEC in the form of a pulse signal and the wake-up signal after current limitation. KL30_DET_GPIO.
  • the power supply terminal of the XOR gate and the output terminal Y of the XOR gate are both connected to one pole of the second capacitor C2, and the other pole of the second capacitor C2 is grounded.
  • the second capacitor C2 can play a filtering role.
  • the XOR gate is used to input the same wake-up signal to the two input terminals of the XOR gate, but an RC delay circuit is added to the second input terminal of the XOR gate, so that the XOR gate will produce signal inversion within a period of time , Which is to convert a rising edge signal of the wake-up signal into a pulse signal, so that the MCU can detect the wake-up signal, and the wake-up signal is connected to the MCU's pin GPIO to identify the specific wake-up source.
  • the wake-up circuit can be accurate and efficient , The wake-up signal is detected multiple times, the cost is very low, the layout area is small, and the use of diodes to isolate the wake-up signals generated by different wake-up sources makes the product reliability greatly improved.
  • the signal source MOV_DET is initially a high-level signal, and the signal source MOV_DET and the pin MCU_3V3 of the external single-chip microcomputer outputting 3.3V voltage are respectively connected to the collector of the triode switch VT2.
  • the signal source MOV_DET and the pin MCU_3V3 of the external single-chip microcomputer outputting 3.3V voltage are respectively connected to the collector of the triode switch VT2.
  • one end of the fourth resistor R4 is connected to the signal source MOV_DET
  • the other end of the fourth resistor R4 is connected to the voltage source VDD
  • the fourth resistor R4 is the pull-up resistor of the signal source MOV_DET, which is pulled up to the voltage
  • the level provided by the source VDD Generally, the level provided by the voltage source VDD is relatively high.
  • the third resistor R3 is connected to the emitter of the transistor switch VT2, and the other end of the third resistor R3 is grounded.
  • the third resistor R3 is a pull-down resistor.
  • the signal emitted by the emitter of the triode switch VT2 is used as the wake-up signal.
  • the emitter of the triode switch VT2 is connected to the first input terminal of the exclusive OR gate D1.
  • the exclusive OR gate D1 The first input terminal of the XOR gate and the second input terminal of the XOR gate D1 are both low level.
  • the transistor switch VT2 When the level value of the signal source MOV_DET becomes low, the transistor switch VT2 is turned on to output a wake-up signal, the XOR gate of the XOR gate D1 The first input terminal A of D1 and the second input terminal B of the exclusive OR gate D1 both become high, and the second input of the exclusive OR gate D1 becomes high after a delay, so the exclusive OR gate D1 The output terminal outputs the wake-up signal MOV_DETEC in the form of a pulse signal and transmits it to the pin WKUP of the MCU marked D2.
  • the wake-up signal also passes through the current limiting of the first resistor R2 as the identification module to generate the signal MOV_DET_GPIO to The pin GPIO2 of the MCU, so that the MCU can recognize the wake-up signal.
  • the delay circuit is composed of a second resistor R1 and a first capacitor C1.
  • the XOR gate also has a power supply terminal marked as VCC and GND and a grounded ground terminal. The power supply terminal is powered by an external single-chip microcomputer outputting a 3.3V voltage.
  • the pin MCU_3V3 is powered, the power supply terminal of the XOR gate and the output terminal Y of the XOR gate are both connected to one pole of the second capacitor C2, the other pole of the second capacitor C2 is grounded, and the second capacitor C2 can be used To the role of filtering.
  • the isolation module is a diode VT1.
  • the MCU receiving the forwarded wake-up signal includes: Step 501: The MCU reads whether the MCU pin WKUP has a rising edge of the transmitted signal, and if there is a rising edge of the transmitted signal, step 502 is executed, if If not, proceed to step 501; step 502: MCU reads whether the pin GPIO2 of the MCU is high level, if it is high level, go to step 503, if it is low level, go to step 504; step 503: MCU judgment At this time, the wake-up signal is received and the MCU is awakened, and the forwarded wake-up signal is received once, and then go to step 501 to continue to receive the forwarded wake-up signal the next time; Step 504: MCU reads whether the MCU pin GPIO2 If it is high level, go to step 505, if it is low level, continue to detect the pin GPIO2 of the next MCU until the last MCU pin GPIO2 is detected; Step 505: MCU judgment At this time,
  • Step 507 The MCU determines that the wake-up signal is received at this time and wakes up the MCU, and returns to step 501 for execution.
  • the embodiments of the present disclosure also provide a storage medium, the storage medium includes a stored program, wherein the program executes the steps in any one of the foregoing methods when the program runs.
  • the embodiment of the present disclosure also provides a processor, the processor is used to run a program, wherein the program executes the steps in any one of the above methods when the program is running.
  • the foregoing storage medium may include, but is not limited to: U disk, Read Only Memory (ROM, Read Only Memory), Random Access Memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk, etc.
  • U disk Read Only Memory
  • RAM Random Access Memory
  • mobile hard disk magnetic disk or optical disk, etc.
  • the embodiments of the present disclosure include: detecting a wake-up signal sent by the wake-up source through a wake-up module, and forwarding the wake-up signal to the main control module, the number of the wake-up source is more than one; the main control module, and the The wake-up module is connected to receive the forwarded wake-up signal, and the number of the main control module is one.
  • the detection solves the problem that the relatively large number of comparators used for one wake-up source in the related technology makes the cost high, and the wake-up circuit cannot perform detection when there are multiple wake-up sources.
  • the term computer storage medium includes volatile and non-volatile data implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data).
  • Non-removable, removable and non-removable media include but are not limited to RAM, ROM, EEPROM, flash memory or other storage technologies, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, and magnetic tapes. , Disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and that can be accessed by a computer.

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Abstract

一种唤醒电路、唤醒方法，其中，唤醒电路，包括：唤醒模块（11），与唤醒源连接，用于检测唤醒源发送来的唤醒信号，并将唤醒信号转发到主控模块（12）中，唤醒源的数量为一个以上；主控模块（12），与唤醒模块（11）连接，用于接收转发来的唤醒信号，主控模块（12）的数量为一个。

Description

唤醒电路、唤醒方法
本公开要求享有2019年09月19日提交的名称为“唤醒电路、唤醒方法”的中国专利申请CN201910886726.2的优先权，其全部内容通过引用并入本文中。
技术领域
本公开涉及唤醒电路技术领域，尤指一种唤醒电路、唤醒方法。
背景技术
Telematics BOX，简称车载T-BOX，而车联网系统包含四部分，主机、车载T-BOX、手机APP及后台系统。主机主要用于车内的影音娱乐，以及车辆信息显示；车载T-BOX主要用于和后台系统/手机APP通信，实现手机APP的车辆信息显示与控制。
当用户通过手机APP发送控制命令后，如TSP后台这样的后台系统会发出控制命令到车载T-BOX，车载T-BOX在获取到控制命令后，通过CAN总线发送控制报文并实现对车辆的控制，最后反馈操作结果到用户的手机APP；这个功能可以帮助用户远程启动车辆、打开空调、调整座椅至合适位置等。
现有的车载T-BOX产品中的唤醒信号检测，主要装置是包括第一比较器的唤醒电路，第一比较器耦合到输入信号并且被配置为将输入信号与第一比较值进行比较。该唤醒电路包括第二比较器，其耦合到输入信号并且被配置为将输入信号与第二比较值进行比较。该唤醒电路还包括异或门。异或门的第一输入耦合到第一比较器的输出。异或门的第二输入耦合到第二比较器的输出。该唤醒电路还包括可调谐电荷泵，其耦合到异或门的输出并且被配置为将来自异或门的信号转换为DC值以唤醒正在被监控的电路；该唤醒电路的方案针对一个唤醒源使用的比较器的数量较多，使得成本高，并且该唤醒电路只能检测一个作为唤醒源的输入信号，当有多个唤醒源的时候就无法进行检测了。
针对相关技术中存在的上述问题，目前尚未发现有效的解决方案。
发明内容
本公开实施例提供了一种唤醒电路、唤醒方法，通过一个主控模块来接入若干唤醒源，降低了唤醒电路的成本并且适用于多个唤醒源的检测。
本公开实施例提供了一种唤醒电路，包括：唤醒模块，与唤醒源连接，用于检测所述唤醒源发送来的唤醒信号，并将所述唤醒信号转发到主控模块中，所述唤醒源的数量为一个以上；主控模块，与所述唤醒模块连接，用于接收转发来的所述唤醒信号，所述主控模块的数量为一个。
本公开实施例还提供了一种唤醒方法，包括：使用所述唤醒电路进行唤醒。
本公开实施例还提供了一种唤醒方法，包括：检测所述唤醒源发送来的唤醒信号，并将所述唤醒信号转发；接收转发来的所述唤醒信号。
本公开实施例还提供一种存储介质，所述存储介质包括存储的程序，其中，所述程序运行时执行上述的方法。
本公开实施例还提供一种处理器，所述处理器用于运行程序，其中，所述程序运行时执行上述的方法。
本公开的特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本公开而了解。本公开的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
图1为本公开实施例的一种唤醒电路的结构图；
图2为本公开实施例的另一种唤醒电路的结构图；
图3为本公开实施例的另一种唤醒电路的结构图；
图4为本公开实施例的另一种唤醒电路的结构图；
图5为本公开实施例的一种唤醒方法的流程图；
图6为本公开实施例的一种所述检测所述唤醒源发送来的唤醒信号的方法的流程图；
图7为本公开实施例的所述异或门把所述唤醒源的输出端输出的唤醒信号和该唤醒信号经过所述延迟模块延迟后形成的延迟信号进行运算得到脉冲信号的形式下的唤醒信号的方法的流程图；
图8为本公开实施例的另一种所述检测所述唤醒源发送来的唤醒信号的方法的流程图；
图9为本公开实施例的一个实施例的唤醒电路的结构图；
图10为本公开实施例的异或门的输入端和输出端的电压曲线的坐标图；
图11为本公开实施例的实施方式一的唤醒电路的结构图；
图12为本公开实施例的实施方式一的异或门的第一输入端A、异或门的第二输入端B和异或门的输出端Y的电压变化的波形图；
图13为本公开实施例的实施方式二的唤醒电路的结构图。
具体实施方式
下文中将结合附图对本公开的实施例进行详细说明。
需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。需要说明的是，本公开的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
实施例1
本公开实施例唤醒电路的应用场景包括：车载T-BOX的唤醒电路，有多个唤醒源的产品等，其应用前景广阔。
在本公开实施例中提供了一种唤醒电路，如图1所示，包括：唤醒模块11，与唤醒源连接，用于检测所述唤醒源发送来的唤醒信号，并将所述唤醒信号转发到主控模块中，所述唤醒源的数量为一个以上；主控模块12，与所述唤醒模块连接，用于接收转发来的所述唤醒信号，所述主控模块的数量为一个。
本实施例中，通过所述唤醒模块检测所述唤醒源发送来的唤醒信号，并将所述唤醒信号转发到主控模块中，所述唤醒源的数量为一个以上；主控模块，与所述唤醒模块连接，用于接收转发来的所述唤醒信号，所述主控模块的数量为一个。这样就能通过一个主控模块来接入若干唤醒源，由此就能由一个主控模块来接收多个唤醒源发送来的唤醒信号，降低了唤醒电路的成本并且适用于多个唤醒源的检测，解决了相关技术中的针对一个唤醒源使用的比较器的数量较多而使得成本高、唤醒电路在有多个唤醒源的时候就无法进行检测了的问题。
如图2所示，在一实施例中，所述唤醒电路还包括：识别模块13，所述识别模块连接在与所述唤醒模块连接的唤醒源和所述主控模块之间，用于把所述唤醒源传送的唤醒信号发送到所述主控模块中识别。
这样，就能把所述唤醒信号通过所述主控模块识别，就能区分出是哪一个唤醒源传送来的所述唤醒信号，不会混淆唤醒信号的来源。
在一实施例中，所述唤醒模块与其连接的所述唤醒源一一对应，所述唤醒源与其连 接的所述识别模块一一对应。
这样的一一对应的方式就更易于所述主控模块识别所述唤醒源传送的唤醒信号。
如图3所示，在一实施例中，所述唤醒电路还包括：延时模块14，所述延时模块连接在与所述唤醒模块连接的唤醒源和该唤醒模块之间，用于把所述唤醒源传送的唤醒信号进行延迟后以脉冲信号的形式传送到所述主控模块中，所述唤醒模块与其连接的所述延时模块一一对应。
这样，不同的所述唤醒模块在每次传送所述唤醒信号时，都能够在与之对应的所述延时模块延迟后以脉冲信号的形式传送到所述主控模块中，这样就能让所述主控模块有效地接收到以脉冲信号的形式传送来的唤醒信号，更为准确的达到唤醒信号的唤醒功能。
如图4所示，在一实施例中，所述唤醒电路还包括：隔离模块15，所述隔离模块连接在所述唤醒模块与所述主控模块之间，用于隔离所述主控模块对所述唤醒模块传送的倒灌电流，所述唤醒模块与其连接的所述隔离模块一一对应。
这样，运用所述隔离模块就防止所述主控模块对对应的所述唤醒模块传送来倒灌电流造成对所述唤醒模块的伤害。
在一实施例中，所述唤醒模块为异或门，所述异或门的第一输入端与所述唤醒源的输出端连接，所述异或门的第二输入端与所述延时模块的一端连接，所述延时模块的另一端与所述唤醒源的输出端连接，所有所述异或门的输出端均与所述主控模块的一个管脚连接；所述异或门用于把所述唤醒源的输出端输出的唤醒信号和该唤醒信号经过所述延迟模块延迟后形成的延迟信号进行运算，运算后以脉冲信号的形式传送到所述主控模块中。
这样，把所述唤醒信号以脉冲信号的形式传送到所述主控模块中，就能让所述主控模块辨识出唤醒信号，达到辨识出若干唤醒信号的目的，这样就能达到有多个唤醒源的时候就能进行检测其所传送的若干唤醒信号的目的，另外所述异或门成本低廉。
在一实施例中，所述主控模块为MCU，与所有所述异或门的输出端连接的所述MCU的那个管脚用于接收以脉冲信号的形式传送来的唤醒信号；所述MCU还包括与所述识别模块一一对应的管脚，所述识别模块的一端与所述MCU对应的管脚连接，所述识别模块的另一端与对应的所述唤醒源的输出端连接。
这样，主控模块用MCU，MCU就是单片机，价格低廉，用所述MCU的一个管脚用于接收若干唤醒源传送来的唤醒信号，就能实现通过一个主控模块来接入若干唤醒源，由此就能由一个主控模块来接收多个唤醒源发送来的唤醒信号，降低了唤醒电路的成本并且适用于多个唤醒源的检测。而识别模块的两端分别与其对应的唤醒源和对应的MCU的管脚连接，这样就能把唤醒源的输出端发送的唤醒信号经由所述识别模块传送到对应的MCU 的管脚，利于MCU识别所述唤醒信号从哪个唤醒源发送来的。
在一实施例中，所述识别模块为第一电阻，所述第一电阻用于对所述唤醒源的输出端发送到对应的所述MCU的管脚的唤醒信号进行限流后发送到所述MCU中识别。
这样，经过限流后发送到所述MCU中识别，使得发送到所述MCU的信号更为安全和可靠。
在一实施例中，所述延时模块为RC延时电路，所述RC延时电路包括第二电阻和第一电容；所述第二电阻的一端与所述唤醒源的输出端连接，所述第二电阻的另一端、第一电容的一极和所述异或门的第二输入端连接，所述第一电容的另一极接地。
这样，用RC延时电路的第二电阻和第一电容，价格低廉成本低，并且能够有效地达到把所述唤醒信号延时的效果。
在一实施例中，所述隔离模块为二极管，所述二极管的正极与所述异或门的输出端连接，所有所述二极管的负极均与所述MCU的一个管脚连接。
这样，所述二极管的连接方式就能有效防止所述MCU对对应的所述唤醒模块传送来倒灌电流造成对所述异或门的伤害。
实施例2
在本公开实施例中还提供了一种唤醒方法，包括：使用所述唤醒电路进行唤醒。所述唤醒电路，包括：唤醒模块，与唤醒源连接，用于检测所述唤醒源发送来的唤醒信号，并将所述唤醒信号转发到主控模块中，所述唤醒源的数量为一个以上；主控模块，与所述唤醒模块连接，用于接收转发来的所述唤醒信号，所述主控模块的数量为一个。
在本公开实施例中还提供了一种唤醒方法，如图5所示，与唤醒电路的实现原理对应，包括：步骤101，检测所述唤醒源发送来的唤醒信号，并将所述唤醒信号转发；步骤102，接收转发来的所述唤醒信号。
在一实施例中，如图6所示，所述检测所述唤醒源发送来的唤醒信号，包括：步骤201：所述唤醒源的输出端输出唤醒信号；步骤202：输出的所述唤醒信号分别传送到所述异或门的第一输入端和所述RC延时电路；步骤203：在所述RC延时电路对所述唤醒信号进行延迟而形成所述延迟信号后，所述异或门把所述唤醒源的输出端输出的唤醒信号和该唤醒信号经过所述延迟模块延迟后形成的延迟信号进行运算得到脉冲信号的形式下的唤醒信号。
在一实施例中，如图7所示，所述异或门把所述唤醒源的输出端输出的唤醒信号和该唤醒信号经过所述延迟模块延迟后形成的延迟信号进行运算得到脉冲信号的形式下的唤醒信号，包括：步骤301，在所述输出的所述唤醒信号分别传送到所述异或门的第一 输入端和所述RC延时电路之前，所述异或门的第一输入端和所述异或门的第二输入端的输入电平一样，所述异或门的输出端就输出低电平；步骤302，在所述输出的所述唤醒信号分别传送到所述异或门的第一输入端和所述RC延时电路时，在延时的时段里，所述异或门的第一输入端和所述异或门的第二输入端的输入电平不一样，所述异或门的输出端就输出高电平；步骤303，在延时的时段过后，所述异或门的第一输入端和所述异或门的第二输入端的输入电平一样，所述异或门的输出端就输出低电平，由此就形成了脉冲信号形式下的唤醒信号。
这样，通常所述MCU用来接收唤醒信号的那个管脚只能检测唤醒信号的上升沿，如果该管脚直接接多个唤醒源的输出端，则只识别一次唤醒信号后，该管脚由于第一次接收到所述唤醒源的输出端的高电平就会保持持续的高电平，因此无法检测到下一次唤醒信号。形成脉冲信号形式下的唤醒信号，就能让该管脚接收到将以前的只有一次上升沿的唤醒信号转换为一个脉冲信号，从而让所述MCU能对唤醒信号进行辨识。
在一实施例中，如图8所示，所述检测所述唤醒源发送来的唤醒信号，还包括：步骤401：所述唤醒源的输出端输出的唤醒信号还通过所述第一电阻限流后传输到对应的所述MCU的管脚；步骤402：所述MCU就通过传输到对应的所述MCU的管脚来判断出对应的所述唤醒源传送的唤醒信号。
这样，通过所述唤醒源与所述MCU的管脚的对应关系，就能识别具体的唤醒源，使得所述MCU接收到的所述唤醒信号更为准确高效。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本公开各个实施例所述的方法。
实施例3
如图9所示，本实施例的所述唤醒电路包括作为主控模块的MCU，其在图9上的标记为D(N+1)；N个异或门，其在图9上的标记为D1-DN；N个识别模块，其在图9上的标记为识别模块1-识别模块N；N个延时模块，其在图9上的标记为延时模块1-延时模块N；N个隔离模块，其在图9上的标记为隔离模块1-隔离模块路N，其中N为正整数，表示异或门、延迟模块、识别模块和隔离模块的数量。
本实施例中的MCU，其在图9上的标记为D(N+1)为本唤醒电路的主控模块，主要 作用为用单独的管脚WKUP接收唤醒信号，另外，每个不同的唤醒源所发送的唤醒信号接不同的N个MCU的管脚，这些不同的N个MCU的管脚在图9中的标记分别为CHECK1-CHECKN；因此其中一个唤醒信号在对应的MCU的管脚上有波形变化时，则MCU可以检测到具体是由哪一个唤醒源所发送的唤醒信号；所述的管脚均能够是所述MCU的GPIO管脚。
本实施例中标记为D1-DN的异或门主要作用为将唤醒源所发送的唤醒信号变化为脉冲信号，该异或门(一般情况，异或门功能逻辑电路器件有5个管脚，也有多个管脚的情况，但基本原理一样)其中有分别作为第一输入端和第二输入端的2个异或门的输入管脚，还有一个异或门的作为输出端的输出管脚，另外还有接入给异或门供电的供电管脚以及接地的接地管脚；其中延时模块，主要作用为对输入的唤醒源的唤醒信号进行延时，从而使得异或门的两个输入端的电平在输入唤醒信号前是一样的，异或门输出低电平；在有唤醒信号时在延时模块起作用的延时的时间内，异或门的两个输入端的电平不一样，从而使得异或门输出端输出为高电平，在延时模块失效后，异或门的两个输入端的电平一致，因此异或门的输出端输出低电平，由此就形成了脉冲信号形式的唤醒信号，能够为MCU所辨识。
本实施例中识别模块为输入的唤醒信号产生的一个识别信号，该识别信号输入到MCU的标记为CHECK1-CHECKN的管脚，一对一的输入，用于MCU识别具体的唤醒信号所来自的唤醒源；本实施例中隔离模块为隔离多个输入MCU的标记为WKUP的那个管脚的唤醒信号，一般可以为二极管，或其他满足防止电流倒灌的器件。
如图10所示的异或门的输入端和输出端的电压曲线，其中纵坐标上的A和B分别表示异或门的第一输入端的电压和第二输入端的电压，Y表示异或门的输出端的电压：横坐标上的T表示时间，从电压曲线的波形中可以看出在时刻T1前，异或门的两个输入端的输入电平同为0V，因此异或门的输出端输出低电平；在时刻T1时，由于有唤醒信号输入，因此异或门的两个输入端均发生变化，所述异或门的第一输入端在输入的唤醒信号的作用下迅速变成高电平，所述异或门的第二输入端由于延时模块的作用，开始缓慢变化，该延时模块采用的是包括第二电阻和第一电容的RC延时电路，在作为延迟时段的时刻T1到时刻T2的时间段内，由于异或门的两个输入端的电平一高一低，因此异或门的输出端输出高电平；作为延迟时段的时刻T1时刻T2的时间段的时长大小T2-T1的计算公式为式(1)所示：
T2-T1＝-R*C*Ln((E-V)/E)       (1)
公式中R为第二电阻的电阻值大小，单位为Ω，C为第一电容的电容值的大小，单位 为F，E为对异或门的第二输入端输入的高电平的电压值，V为第一电容充电过程中达到的电平的电压值。
在到达时刻T2时，异或门的第二输入端的电容充电完成，异或门的第二输入端的电平也变成高电平，因此在时刻T2时由于异或门的两个输入端的输入电平均为高电平，因此异或门的输出端输出低电平，由此就形成了脉冲信号，便于MCU辨识唤醒信号。
本公开实施例方案中的各个模块可以通过硬件、软件或者结合的形式实现，可以是多种形式的电路，下面通过具体实施方案作详细描述：
实施方式一
如图11所示，本实施方式的唤醒源所发送的唤醒信号为：由外部的单片机的输出3.3V电压的管脚MCU_3V3和外部的电压源输出的供给电位KL30通过比较器D3输出的唤醒信号POWER_LOW，由于供给电位KL30在使用中不断降低，开始供给电位KL30与输出3.3V电压的管脚MCU_3V3的压差较大，比较器D3输出低电平，当供给电位KL30的电压值降低到需要报警的电压值时，即比输出3.3V电压的管脚MCU_3V3的电压值还低，则比较器D3输出高电平，即唤醒信号POWER_LOW为一个从低变高的上升沿波形，此时异或门的第一输入端A的电压值迅速变为1.8V，异或门的第二输入端B的由于连接有由第二电阻R1和第一电容C1组成的RC延时电路，所述第二电阻R1的电阻值为100Ω，所述第一电容C1的电容值为1000*1/1000000，对异或门的第二输入端输入的高电平的电压值为1.8V，第一电容充电过程中达到的电平的电压值为1.6V，这样按照式(1)计算该RC延时电路的延时时段的时长T如下：
T＝-100*1000*1/1000000*ln((1.8-1.6)/1.8)＝0.2197秒
由于一般的逻辑电路MCU判断为高电平是有范围的，因此达到判定为高电平的最低低电压，异或门D1即可判定为高电平，异或门的第二输入端延时0.2197秒到达1.6V，则异或门D1判定异或门的第二输入端为高电平，因此唤醒信号POWER_DETEC信号在发送前为让异或门的输出端输出0V，被发送后有0.2197时长下让异或门的输出端输出为高电平，之后又让异或门的输出端输出0V，具体异或门的第一输入端A、异或门的第二输入端B和异或门的输出端Y的电压变化的波形如图12所示。
另外在图11中，作为识别模块的第一电阻的标记为R2，异或门还具有分别标记为VCC和GND的供电端和接地的接地端，该供电端由外部的单片机的输出3.3V电压的管脚MCU_3V3供电，所述隔离模块为二极管VT1，MCU的标记为D2，所述MCU的管脚WKUP和管脚GPIO分别用来接收脉冲信号形式下的唤醒信号POWER_DETEC和限流后的唤醒信号KL30_DET_GPIO。异或门的供电端与异或门的输出端Y均与第二电容C2的 一极连接，所述第二电容C2的另一极接地，所述第二电容C2能够起到滤波的作用。
这样使用异或门，对异或门的两个输入端输入同样的唤醒信号，但是在异或门的第二输入端增加RC延时电路，从而使得异或门在一段时间内会产生信号翻转，即将唤醒信号的一次上升沿信号转换为一个脉冲信号，从而让MCU对唤醒信号进行检测，并且让唤醒信号接入MCU的管脚GPIO用来识别具体的唤醒源，本唤醒电路能准确，高效，多次的检测唤醒信号，成本极低，布局面积小，并使用二极管对不同唤醒源产生的唤醒信号进行隔离，使得产品可靠性大大提高。
实施方式二
如图13所示，本实施方式的唤醒源中，其信号源MOV_DET初始为高电平信号，其信号源MOV_DET和外部的单片机的输出3.3V电压的管脚MCU_3V3分别与三极管开关VT2的集电极和三极管开关VT2的基极连接，第四电阻R4的一端与信号源MOV_DET连接，第四电阻R4的另一端与电压源VDD连接，第四电阻R4信号源MOV_DET的上拉电阻，上拉到电压源VDD提供的电平，一般电压源VDD提供的电平较高，第三电阻R3的一端与三极管开关VT2的发射极连接，第三电阻R3的另一端接地，第三电阻R3为下拉电阻，三极管开关VT2的发射极所发射的信号就作为所述唤醒信号，三极管开关VT2的发射极与异或门D1的第一输入端连接，默认状态下，由于三极管开关VT2关闭，因此异或门D1的第一输入端和异或门D1的第二输入端均为低电平，当信号源MOV_DET的电平值变低，则三极管开关VT2打开而输出唤醒信号，异或门D1的异或门D1的第一输入端A和异或门D1的第二输入端B均变为高电平，异或门D1的第二输入端是延时后变为高电平的，因此异或门D1的输出端输出脉冲信号的形式下的唤醒信号MOV_DETEC，并传输给标记为D2的MCU的管脚WKUP，所述唤醒信号还同时通过作为识别模块的第一电阻R2的限流后产生信号MOV_DET_GPIO给MCU的管脚GPIO2，这样MCU可以识别唤醒信号。所述延时电路由第二电阻R1和第一电容C1构成，异或门还具有分别标记为VCC和GND的供电端和接地的接地端，该供电端由外部的单片机的输出3.3V电压的管脚MCU_3V3供电，异或门的供电端与异或门的输出端Y均与第二电容C2的一极连接，所述第二电容C2的另一极接地，所述第二电容C2能够起到滤波的作用。所述隔离模块为二极管VT1。
MCU接收转发来的所述唤醒信号，包括：步骤501：MCU读取MCU的管脚WKUP是否有发送来的信号的上升沿，如果有发送来的信号的上升沿产生，则执行步骤502，如果没有则继续执行步骤501；步骤502：MCU读取MCU的管脚GPIO2是否为高电平，如果为高电平，则执行步骤503，如果为低电平则执行步骤504；步骤503：MCU判断此时 接收到唤醒信号并唤醒MCU，完成一次接收转发来的所述唤醒信号，然后转到步骤501继续下一次接收转发来的所述唤醒信号；步骤504：MCU读取MCU的管脚GPIO2是否为高电平，如果为高电平，则执行步骤505，如果为低电平则继续检测下一个MCU的管脚GPIO2，一直到对最后一个MCU的管脚GPIO2进行检测；步骤505：MCU判断此时接收到唤醒信号并唤醒MCU，回到步骤501进行下一次接收转发来的所述唤醒信号；步骤506：MCU读取最后一个MCU的管脚GPIO2是否为高电平，如果是，则执行步骤507，如果不是，则认为所有唤醒源均没有唤醒信号，应为误判MCU的管脚WKUP上发送来的信号为上升沿，回到步骤501，进行下一次接收转发来的所述唤醒信号；步骤507：MCU判断此时接收到唤醒信号并唤醒MCU，并回到步骤501中执行。
本公开实施例还提供一种存储介质，所述存储介质包括存储的程序，其中，所述程序运行时执行上述任一项方法中的步骤。
本公开实施例还提供一种处理器，所述处理器用于运行程序，其中，所述程序运行时执行上述任一项方法中的步骤。
在本实施例中，上述存储介质可以包括但不限于：U盘、只读存储器(ROM，Read Only Memory)、随机存取存储器(RAM，Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
本公开实施例包括：通过唤醒模块检测所述唤醒源发送来的唤醒信号，并将所述唤醒信号转发到主控模块中，所述唤醒源的数量为一个以上；主控模块，与所述唤醒模块连接，用于接收转发来的所述唤醒信号，所述主控模块的数量为一个。这样就能通过一个主控模块来接入若干唤醒源，由此就能由一个主控模块来接收多个唤醒源发送来的唤醒信号，降低了唤醒电路的成本并且适用于多个唤醒源的检测，解决了相关技术中的针对一个唤醒源使用的比较器的数量较多而使得成本高、唤醒电路在有多个唤醒源的时候就无法进行检测了的问题。
本领域普通技术人员可以理解，上文中所公开方法中的全部或某些步骤、系统、装置中的功能模块/单元可以被实施为软件、固件、硬件及其适当的组合。硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些组件或所有组件可以被实施为由处理器，如数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路，这样的软件可以分布在计算机可读介质上，计算机可读介质可以包括计算机存储介质(或非暂时性介质)和通信介质(或暂时性介质)。如本领域普通技术人员公知的，术语计算机存储介质包括在用于存储信 息(诸如计算机可读指令、数据结构、程序模块或其他数据)的任何方法或技术中实施的易失性和非易失性、可移除和不可移除介质，计算机存储介质包括但不限于RAM、ROM、EEPROM、闪存或其他存储器技术、CD-ROM、数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (17)

  1. 一种唤醒电路，包括：
    唤醒模块，与唤醒源连接，用于检测所述唤醒源发送来的唤醒信号，并将所述唤醒信号转发到主控模块中，所述唤醒源的数量为一个以上；
    主控模块，与所述唤醒模块连接，用于接收转发来的所述唤醒信号，所述主控模块的数量为一个。
  2. 根据权利要求1所述的唤醒电路，其中，所述唤醒电路还包括：识别模块，所述识别模块连接在与所述唤醒模块连接的唤醒源和所述主控模块之间，用于把所述唤醒源传送的唤醒信号发送到所述主控模块中识别。
  3. 根据权利要求2所述的唤醒电路，其中，所述唤醒模块与其连接的所述唤醒源一一对应，所述唤醒源与其连接的所述识别模块一一对应。
  4. 根据权利要求2所述的唤醒电路，其中，所述唤醒电路还包括：延时模块，所述延时模块连接在与所述唤醒模块连接的唤醒源和该唤醒模块之间，用于把所述唤醒源传送的唤醒信号进行延迟后以脉冲信号的形式传送到所述主控模块中，所述唤醒模块与其连接的所述延时模块一一对应。
  5. 根据权利要求1或2所述的唤醒电路，其中，所述唤醒电路还包括：隔离模块，所述隔离模块连接在所述唤醒模块与所述主控模块之间，用于隔离所述主控模块对所述唤醒模块传送的倒灌电流，所述唤醒模块与其连接的所述隔离模块一一对应。
  6. 根据权利要求4所述的唤醒电路，其中，所述唤醒模块为异或门，所述异或门的第一输入端与所述唤醒源的输出端连接，所述异或门的第二输入端与所述延时模块的一端连接，所述延时模块的另一端与所述唤醒源的输出端连接，所有所述异或门的输出端均与所述主控模块的一个管脚连接；
    所述异或门用于把所述唤醒源的输出端输出的唤醒信号和该唤醒信号经过所述延迟模块延迟后形成的延迟信号进行运算，运算后以脉冲信号的形式传送到所述主控模块中。
  7. 根据权利要求6所述的唤醒电路，其中，所述主控模块为MCU，与所有所述异或门的输出端连接的所述MCU的那个管脚用于接收以脉冲信号的形式传送来的唤醒信号；
    所述MCU还包括与所述识别模块一一对应的管脚，所述识别模块的一端与所述MCU对应的管脚连接，所述识别模块的另一端与对应的所述唤醒源的输出端连接。
  8. 根据权利要求7所述的唤醒电路，其中，所述识别模块为第一电阻，所述第一电 阻用于对所述唤醒源的输出端发送到对应的所述MCU的管脚的唤醒信号进行限流后发送到所述MCU中识别。
  9. 根据权利要求7所述的唤醒电路，其中，所述延时模块为RC延时电路，所述RC延时电路包括第二电阻和第一电容；
    所述第二电阻的一端与所述唤醒源的输出端连接，所述第二电阻的另一端、第一电容的一极和所述异或门的第二输入端连接，所述第一电容的另一极接地。
  10. 根据权利要求7所述的唤醒电路，其中，所述唤醒电路还包括：隔离模块，所述隔离模块连接在所述唤醒模块与所述主控模块之间，用于隔离所述主控模块对所述唤醒模块传送的倒灌电流，所述唤醒模块与其连接的所述隔离模块一一对应；
    所述隔离模块为二极管，所述二极管的正极与所述异或门的输出端连接，所有所述二极管的负极均与所述MCU的一个管脚连接。
  11. 一种唤醒方法，其特征在于，包括：使用如权利要求1至10中任一项所述唤醒电路进行唤醒。
  12. 一种基于如权利要求1至10中任一项所述唤醒电路的唤醒方法，其特征在于，包括：检测所述唤醒源发送来的唤醒信号，并将所述唤醒信号转发；接收转发来的所述唤醒信号。
  13. 根据权利要求12所述的唤醒方法，其中，所述检测所述唤醒源发送来的唤醒信号，包括：
    所述唤醒源的输出端输出唤醒信号；
    输出的所述唤醒信号分别传送到所述异或门的第一输入端和所述RC延时电路；
    在所述RC延时电路对所述唤醒信号进行延迟而形成所述延迟信号后，所述异或门把所述唤醒源的输出端输出的唤醒信号和该唤醒信号经过所述延迟模块延迟后形成的延迟信号进行运算得到脉冲信号的形式下的唤醒信号。
  14. 根据权利要求13所述的唤醒方法，其中，所述异或门把所述唤醒源的输出端输出的唤醒信号和该唤醒信号经过所述延迟模块延迟后形成的延迟信号进行运算得到脉冲信号的形式下的唤醒信号，包括：
    在所述输出的所述唤醒信号分别传送到所述异或门的第一输入端和所述RC延时电路之前，所述异或门的第一输入端和所述异或门的第二输入端的输入电平一样，使得所述异或门的输出端输出低电平；
    在所述输出的所述唤醒信号分别传送到所述异或门的第一输入端和所述RC延时电路时，在延时的时段里，所述异或门的第一输入端和所述异或门的第二输入端的输入电平不一样，使得所述异或门的输出端输出高电平；
    在延时的时段过后，所述异或门的第一输入端和所述异或门的第二输入端的输入电平一样，使得所述异或门的输出端输出低电平，由此形成脉冲信号形式下的唤醒信号。
  15. 根据权利要求13所述的唤醒方法，其中，所述检测所述唤醒源发送来的唤醒信号，还包括：
    所述唤醒源的输出端输出的唤醒信号还通过所述第一电阻限流后传输到对应的所述MCU的管脚；
    所述MCU通过传输到所述MCU对应的的管脚来判断出对应的所述唤醒源传送的唤醒信号。
  16. 一种存储介质，其中，所述存储介质包括存储的程序，其中，所述程序运行时执行所述权利要求12至15任一项中所述的方法。
  17. 一种处理器，其中，所述处理器用于运行程序，其中，所述程序运行时执行所述权利要求12至15任一项中所述的方法。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113126661A (zh) * 2021-04-22 2021-07-16 傲普(上海)新能源有限公司 一种低功耗光伏追日电路
CN115469575A (zh) * 2022-08-23 2022-12-13 乐歌人体工学科技股份有限公司 基于总线通信的低功耗控制系统、控制器及线性驱动装置
CN116502667A (zh) * 2023-06-21 2023-07-28 杭州海康威视数字技术股份有限公司 射频唤醒电路及摄像系统

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110928212B (zh) * 2019-09-19 2022-05-10 中兴通讯股份有限公司 唤醒电路、唤醒方法
US11950016B2 (en) * 2020-04-15 2024-04-02 Mediatek Inc. Control method and circuitry of receiver
CN112208470B (zh) * 2020-12-11 2022-04-01 智道网联科技(北京)有限公司 一种实现设备低功耗的方法及车载终端
CN112918408B (zh) * 2021-02-07 2022-10-18 上海科世达-华阳汽车电器有限公司 一种唤醒电路和车辆
CN113763958B (zh) * 2021-09-28 2024-02-13 海信视像科技股份有限公司 语音唤醒方法、装置、电子设备和存储介质
CN115817268B (zh) * 2022-08-25 2024-11-12 宁德时代新能源科技股份有限公司 唤醒电路、唤醒方法、设备、系统及存储介质
CN115776715A (zh) * 2022-11-24 2023-03-10 北京海纳川汽车部件股份有限公司 T-Box的节电控制装置、T-Box、车辆及控制方法
CN116400621A (zh) * 2023-03-29 2023-07-07 奇瑞商用车（安徽）有限公司 一种新能源电动汽车远程控制方法及系统
CN117997333B (zh) * 2024-04-03 2024-07-12 宁波均联智行科技股份有限公司 一种控制信号传输电路、车载电子设备及车辆

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6614277B1 (en) * 1999-06-22 2003-09-02 Stmicroelectronics S.R.L. Circuit for providing a minimum wake-up time in the wake-up logic circuits
CN201838037U (zh) * 2009-12-29 2011-05-18 北京万集科技有限责任公司 一种用于etc车载单元的多唤醒源唤醒电路
CN203965866U (zh) * 2014-07-08 2014-11-26 武汉万集信息技术有限公司 一种光唤醒的车载单元
CN206712665U (zh) * 2017-03-28 2017-12-05 杰华特微电子（杭州）有限公司 隔离式开关电路
CN107800273A (zh) * 2017-11-27 2018-03-13 浙江凯发电气有限公司 一种电能表外置断路器电源电路
US20180176864A1 (en) * 2016-12-20 2018-06-21 Intel IP Corporation Method and apparatus to controlling sleep time for bluetooth device and bluetooth enabled device
CN110928212A (zh) * 2019-09-19 2020-03-27 中兴通讯股份有限公司 唤醒电路、唤醒方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6738914B2 (en) * 2001-01-05 2004-05-18 Motorola, Inc. Method and apparatus for determining whether to wake up a system by detecting a status of a push button switch that is remotely located from the system
CN101458538A (zh) * 2008-12-17 2009-06-17 炬力集成电路设计有限公司 一种降低电源系统待机功耗的方法及电源系统
CN102468821B (zh) * 2010-11-16 2014-07-30 博通集成电路（上海）有限公司 唤醒电路、车载单元、滤波器以及频率探测和过滤的方法
US20120286927A1 (en) * 2011-05-12 2012-11-15 Andreas Hagl Wake Channel Indication for Passive Entry System
CN102521555A (zh) * 2011-11-21 2012-06-27 天津中兴软件有限责任公司 一种唤醒信号匹配方法
CN102717763B (zh) * 2012-06-15 2015-08-26 重庆长安汽车股份有限公司 一种电动汽车的整车控制器上下电控制电路及整车控制器
CN103533281B (zh) * 2013-09-27 2017-01-11 广州视源电子科技股份有限公司 增强兼容性的mhl识别控制电路
CN103645794B (zh) * 2013-11-15 2017-02-08 北京兆易创新科技股份有限公司 一种通过边沿检测电路实现睡眠模式唤醒的芯片及方法
CN104035395A (zh) * 2014-03-12 2014-09-10 武汉英泰斯特电子技术有限公司 低功耗车载终端及车载终端实现低功耗的方法
CN104615037B (zh) * 2014-12-22 2019-08-13 厦门雅迅网络股份有限公司 一种基于can总线的车载设备唤醒装置及方法
DE102015102352A1 (de) * 2015-02-19 2016-08-25 Dr. Ing. H.C. F. Porsche Aktiengesellschaft Verfahren und Vorrichtung zum Überwachen eines Ruhezustandes bei einem Kraftfahrzeug
CN205632361U (zh) * 2016-05-16 2016-10-12 广州汽车集团股份有限公司 一种整车控制器的唤醒装置及电动汽车
CN206224174U (zh) * 2016-08-30 2017-06-06 北汽福田汽车股份有限公司 车载终端的低功耗系统和车载终端
WO2019105753A1 (en) * 2017-11-28 2019-06-06 Signify Holding B.V. Apparatus and method for monitoring a circuit
CN109597394A (zh) * 2018-11-23 2019-04-09 北斗航天汽车（北京）有限公司 纯电动汽车整车控制器多路唤醒电路

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6614277B1 (en) * 1999-06-22 2003-09-02 Stmicroelectronics S.R.L. Circuit for providing a minimum wake-up time in the wake-up logic circuits
CN201838037U (zh) * 2009-12-29 2011-05-18 北京万集科技有限责任公司 一种用于etc车载单元的多唤醒源唤醒电路
CN203965866U (zh) * 2014-07-08 2014-11-26 武汉万集信息技术有限公司 一种光唤醒的车载单元
US20180176864A1 (en) * 2016-12-20 2018-06-21 Intel IP Corporation Method and apparatus to controlling sleep time for bluetooth device and bluetooth enabled device
CN206712665U (zh) * 2017-03-28 2017-12-05 杰华特微电子（杭州）有限公司 隔离式开关电路
CN107800273A (zh) * 2017-11-27 2018-03-13 浙江凯发电气有限公司 一种电能表外置断路器电源电路
CN110928212A (zh) * 2019-09-19 2020-03-27 中兴通讯股份有限公司 唤醒电路、唤醒方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP3964899A4

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113126661A (zh) * 2021-04-22 2021-07-16 傲普(上海)新能源有限公司 一种低功耗光伏追日电路
CN113126661B (zh) * 2021-04-22 2023-06-30 傲普(上海)新能源有限公司 一种低功耗光伏追日电路
CN115469575A (zh) * 2022-08-23 2022-12-13 乐歌人体工学科技股份有限公司 基于总线通信的低功耗控制系统、控制器及线性驱动装置
CN116502667A (zh) * 2023-06-21 2023-07-28 杭州海康威视数字技术股份有限公司 射频唤醒电路及摄像系统
CN116502667B (zh) * 2023-06-21 2023-09-29 杭州海康威视数字技术股份有限公司 射频唤醒电路及摄像系统

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