WO2021057656A1 - 阵列基板、液晶显示面板及显示装置 - Google Patents

阵列基板、液晶显示面板及显示装置 Download PDF

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Publication number
WO2021057656A1
WO2021057656A1 PCT/CN2020/116497 CN2020116497W WO2021057656A1 WO 2021057656 A1 WO2021057656 A1 WO 2021057656A1 CN 2020116497 W CN2020116497 W CN 2020116497W WO 2021057656 A1 WO2021057656 A1 WO 2021057656A1
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Prior art keywords
gate
array substrate
dummy
metal layer
drain
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English (en)
French (fr)
Inventor
钟璇
袁洪亮
王建
郑琪
刘建涛
毕谣
王海龙
郭兰军
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Priority to EP20868014.0A priority Critical patent/EP4036975A4/en
Priority to US17/280,966 priority patent/US11782318B2/en
Publication of WO2021057656A1 publication Critical patent/WO2021057656A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133553—Reflecting elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/13356—Structural association of cells with optical devices, e.g. polarisers or reflectors characterised by the placement of the optical elements
    • G02F1/133567—Structural association of cells with optical devices, e.g. polarisers or reflectors characterised by the placement of the optical elements on the back side
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2203/00—Function characteristic
    • G02F2203/02—Function characteristic reflective

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a liquid crystal display panel and a display device.
  • Reflectance and power consumption are an important index to measure the performance of reflective liquid crystal display panel products.
  • the reflective liquid crystal display panel of the related art produces a resin layer with a concave-convex structure on the reflective layer of the TFT. Some parts of the film layer under the resin layer contain metal, and some parts do not contain metal. Metal has a light-reflecting effect, which results in different topography and slope angles of the uneven structure at different positions in the same pixel, resulting in poor reflectivity and uneven brightness display.
  • the power consumption of the display is directly proportional to the display frequency.
  • the reflective liquid crystal display panel of the related technology generally reduces the display drive frequency, such as using a low frequency drive such as 1Hz.
  • the display driving frequency is reduced, the retention time of the pixel voltage increases, and the pixel voltage is continuously reduced due to the existence of leakage current, and the display screen is prone to flicker, which affects the display effect.
  • an array substrate including: a base substrate on which a gate metal layer and a source and drain metal layer are sequentially stacked and arranged on the base substrate; wherein,
  • the gate metal layer includes: a plurality of gate lines and a plurality of dummy gates that are independent of each other;
  • the source-drain metal layer includes: a plurality of data lines and a plurality of dummy drains that are independent of each other;
  • the dummy gate includes: a main body part and a lead part located in a pixel area defined by the gate line and the data line;
  • the dummy drain is located in the pixel region, and the dummy drain includes: a first subsection overlapping with the main body portion, and a second subsection not overlapping with the main body portion.
  • the array substrate further includes: a gate insulating layer located between the gate metal layer and the source/drain metal layer, and a gate insulating layer located on the side of the source/drain metal layer away from the base substrate A plurality of reflective pixel electrodes;
  • C st is the storage capacitance of the reflective pixel electrode
  • ⁇ is the dielectric constant of the gate insulating layer
  • d is the thickness of the gate insulating layer
  • L is the width of the gate line or the data line .
  • the storage capacitor is the sum of the facing capacitance between the first subsection and the main body portion, and the coupling capacitance between the second subsection and the main body portion.
  • the source-drain metal layer further includes a drain, and the drain is electrically connected to the reflective pixel electrode through the dummy drain.
  • the array substrate further includes: a resin layer having a concave-convex structure
  • the resin layer is located between the layer where each of the reflective pixel electrodes is located and the source/drain metal layer;
  • Each of the reflective pixel electrodes has the same uneven structure as the resin layer.
  • the slope of the concave-convex structure is 5°-15°.
  • the lead-out portion extends along the extension direction of the gate line, and the lead-out part is in contact with an edge portion of the main body part away from the gate line.
  • the array substrate further includes: an insulating layer located between the resin layer and the layer where each of the reflective pixel electrodes is located;
  • the insulating layer has the same uneven structure as the resin layer.
  • the gate metal layer further includes a gate, and the gate has a double gate structure.
  • a liquid crystal display panel which is characterized by comprising: an array substrate and a counter substrate that are opposed to each other; the array substrate is the above-mentioned array substrate.
  • the liquid crystal display panel includes a common electrode on the counter substrate or the array substrate; the dummy gate and the common electrode are loaded with the same electrical signal.
  • a display device which is characterized by including the above-mentioned liquid crystal display panel.
  • FIG. 1 is a microscope view of an array substrate provided by an embodiment of the disclosure
  • FIG. 2 is a schematic top view of a pixel structure in an array substrate provided by an embodiment of the disclosure
  • Fig. 3 is a schematic cross-sectional structure view along the line AA' in Fig. 2;
  • FIG. 4 is a schematic diagram of an equivalent circuit of the pixel structure shown in FIG. 2;
  • FIG. 5 is a schematic diagram of the design of a resin layer provided by an embodiment of the disclosure.
  • FIG. 6 is a 3D effect diagram of a resin layer provided by an embodiment of the disclosure.
  • FIG. 7 is a microscope view of the array substrate provided by the comparative embodiment.
  • FIG. 8 is a schematic top view of a pixel structure in an array substrate provided by a comparative embodiment
  • Fig. 9 is a schematic cross-sectional structure view taken along the line BB' in Fig. 8.
  • FIG. 10 is a 3D effect diagram of the resin layer provided by the comparative example.
  • An array substrate provided by an embodiment of the present disclosure includes a plurality of pixel structures P, and each pixel structure P is specifically shown in FIG. 2 and FIG.
  • a gate metal layer and a source-drain metal layer are sequentially stacked on the base substrate 100; wherein,
  • the gate metal layer includes: a plurality of gate lines 101 and a plurality of dummy gates 102 that are independent of each other;
  • the source-drain metal layer includes: a plurality of data lines 103 and a plurality of dummy drains 104 that are independent of each other;
  • the dummy gate 102 includes a main body 1021 located in the pixel area defined by the gate line 101 and the data line 103, and a lead part 1022 in the extending direction of the gate line 101; the lead part 1022 and the main part 1021 are far away from the gate line Contact with the edges;
  • the dummy drain 104 is located in the pixel region, and the dummy drain 104 includes a first sub-section 1041 overlapping with the main body 1021 and a second sub-section 1042 not overlapping with the main body 1021.
  • the main body portion 1021 of the dummy drain electrode 104 and the dummy gate electrode 102 are provided with a first division 1041 that overlaps each other and a second division 1042 that does not overlap each other.
  • the opposite capacitance between the first sub-part 1041 and the main body 1021 and the coupling capacitance between the second sub-part 1042 and the main body 1021 together constitute the storage capacitance of the pixel electrode, which makes the storage capacitance of the pixel electrode larger and effectively reduces
  • the effect of leakage current improves the degree of flicker of the picture and improves the quality of picture display.
  • the dummy drain 104 in order to ensure that the dummy drain 104 is maximally filled in the pixel area, and the voltage change on the gate line 101 and the data line 103 will not adversely affect the pixel voltage. It is necessary to ensure that the dummy drain 104 and the gate line 101, the data line 103, and the transistors in the pixel structure have no positive capacitance; and the dummy drain 104 and the gate line 101 and the data line 103 are generated between the dummy drain 104 and the gate line 101 and the data line 103.
  • the coupling capacitance is less than a certain value.
  • the coupling capacitance C 0 generated between the dummy drain 104 and the gate line 101 and the data line 103 is less than or equal to one thousandth of the pixel electrode storage capacitance C st , that is, C 0 ⁇ C st /1000.
  • ⁇ is the dielectric constant of the gate insulating layer 105
  • d is the thickness of the gate insulating layer 10
  • L is the width of the gate line 101 or the data line 103
  • x is between the dummy drain 104 and the gate line 101 or the data line 103 the distance.
  • the array substrate as shown in FIG. 2 and FIG. 3, further includes: a gate insulating layer 105 located between the gate metal layer and the source and drain metal layers, and a plurality of reflectors located on the side of the source and drain metal layers away from the base substrate 100 Type pixel electrode 106;
  • each dummy drain 104 and the gate line 101 defining the pixel area where it is located, and the data line 103 satisfies the following formula:
  • C st is the storage capacitor of the reflective pixel electrode 106
  • ⁇ is the dielectric constant of the gate insulating layer 105
  • d is the thickness of the gate insulating layer 105
  • L is the width of the gate line 101 or the data line 103.
  • the gate of the gate metal layer has a double-gate structure, and the double-gate structure is electrically connected to two gate lines 101 and is connected to the dummy drain.
  • the gate line 101 with the pole 104 distance x specifically refers to the gate line 101 closer to the dummy drain 104.
  • the distance x between each dummy drain 104 and the gate line 101 defining the pixel region where it is located, and the distance x between the dummy drain 104 and the The value of the distance x between the data lines 103 in the pixel area may be the same or different, which is not limited here.
  • the storage capacitor C st of the reflective pixel electrode 106 is the facing capacitor C st1 between the first sub-part and the main body 1021, and the second sub-part and the main body C st1 The sum of the coupling capacitance C st2 between the parts 1021.
  • the source-drain metal layer further includes a drain 109, which is electrically connected to the reflective pixel electrode 106 through the dummy drain 104.
  • the dummy drain 104 and the reflective pixel electrode 106 are electrically connected through a via H, as shown in FIGS. 2 and 3.
  • an equivalent circuit diagram of a pixel structure in the above-mentioned array substrate provided by an embodiment of the present disclosure.
  • the pixel voltage change ⁇ V pd caused by the voltage change of the data line 103 can be expressed by the following formula:
  • C pd represents the capacitance between the reflective pixel electrode 106 and the data line 103
  • Cst represents the storage capacitance of the reflective pixel electrode 106 (that is, the opposite capacitance C st1 between the first subsection and the main body 1021, and the second The sum of the coupling capacitance C st2 between the two divisions and the main body 1021)
  • C pg represents the capacitance between the reflective pixel electrode 106 and the gate line 101
  • C lc represents the capacitance between the reflective pixel electrode 106 and the liquid crystal molecules
  • V dh -V dl represents the voltage change amount of the data line 103.
  • the storage capacitance Cst of the reflective pixel electrode 106 increases, and the pixel voltage change ⁇ V pd caused by the voltage change of the data line 103 decreases; that is to say, the voltage change of the data line 103 increases with the reflection.
  • the storage capacitance Cst of the pixel electrode 106 increases and decreases. Therefore, the technical solution provided by the present disclosure can effectively prevent flicker, improve the image display quality, and be compatible with low power consumption.
  • the above-mentioned array substrate provided by the embodiment of the present disclosure may further include: a resin layer 107 having a concave-convex structure;
  • the resin layer 107 is located between the layer where each reflective pixel electrode 106 is located and the source/drain metal layer;
  • Each reflective pixel electrode 106 has the same uneven structure as that of the resin layer 107.
  • the reflective pixel electrode 106 and the resin layer 107 have the same concave-convex structure, so that incident light can be diffusely reflected on the reflective pixel electrode 106 with the concave-convex structure, thereby improving the reflectivity. In turn, the brightness and contrast are improved.
  • the evaluation method for reflective liquid crystal display panels mainly uses light incident on the reflective liquid crystal display panel at an angle of 30°, and the reflection under the main viewing angle (that is, the viewing angle range with an angle of ⁇ 5° with the a direction) Rate and contrast are evaluated, as shown in Figure 5.
  • ⁇ 1 represents the incident angle of light, which is 30°
  • ⁇ 2 represents the refraction angle of light in the liquid crystal display panel
  • n cell represents the refractive index of the liquid crystal display panel, which is about 1.5
  • n air represents the refractive index of air, which is 1. Therefore, the refraction angle ⁇ 2 can be obtained as arcsin(1/3).
  • ⁇ 3 represents the incident angle of the light on the uneven structure
  • ⁇ 4 represents the reflection angle of the light on the uneven structure
  • ⁇ 5 represents the slope angle of the light on the uneven structure.
  • the slope angle of the uneven structure is defined as The angle between the tangent to the slope and the horizontal line at half the vertical distance between the lowest point and the highest point of the structure.
  • the slope of the concave-convex structure can be set to be 5°-15°, thereby increasing the brightness of the main viewing angle and expanding the viewing angle range.
  • the resin layer 107 with a concave-convex structure can be produced by the following method: a layer of resin with a certain thickness is coated on the array substrate by a spin coating method, and then a light shield with a bump pattern is placed on the resin, After exposure, development and annealing treatments, a resin layer 107 having a concave-convex structure is formed. Moreover, in the actual manufacturing process, due to the arrangement of the first and second subsections included in the dummy drain 104, the uniformity of the film under the resin layer 107 in the entire pixel area is better (that is, the insulation of the resin layer 107 is better). There is a metal film layer of the dummy drain 104 under most of it).
  • the actual exposure amount irradiated on the resin layer 107 in the pixel display area is basically the same, and the uneven structure of the resin layer 107 has better uniformity (As shown in FIG. 6), the reflectivity of the reflective pixel electrode 106 with the same concave-convex structure is higher, the display brightness and contrast of the liquid crystal display panel are improved, and the picture display quality is higher.
  • the above-mentioned array substrate provided by the embodiment of the present disclosure, as shown in FIG. 3, it further includes: an insulating layer 108 located between the resin layer 107 and the layer where each reflective pixel electrode 106 is located;
  • the insulating layer 108 has the same uneven structure as the resin layer 107.
  • an embodiment of the present disclosure further provides a liquid crystal display panel, including: an array substrate and a counter substrate that are opposed to each other; the array substrate is the above-mentioned array substrate provided by the embodiment of the present disclosure. Since the principle of solving the problem of the liquid crystal display panel is similar to the principle of solving the problem of the above-mentioned array substrate, the implementation of the liquid crystal display panel can refer to the embodiment of the above-mentioned array substrate, and the repetition will not be repeated.
  • the dummy gate electrode 102 is formed such that the reflective pixel electrode of the storage capacitor C st 106 and drain 104 between the dummy, the disclosed embodiment provides the liquid crystal display panel in the present, further comprising: a counter substrate or The common electrode on the array substrate;
  • the dummy gate 102 and the common electrode are loaded with the same electrical signal.
  • a common voltage (V com ) signal is applied to the dummy gate 102 (Dummy Gate), and a pixel voltage (Pixel) signal is applied to the dummy drain 104 (Dummy SD), so that the dummy gate
  • V com common voltage
  • Pixel pixel voltage
  • the storage capacitor C st of the reflective pixel electrode 106 is formed between the gate 102 and the dummy drain 104.
  • the liquid crystal display panel provided by the embodiment of the present disclosure includes the array substrate shown in FIG. 1, a pixel structure on the array substrate is shown in FIGS. 2 and 3, and the topography of the resin layer on the array substrate is shown in FIG. 6. .
  • the liquid crystal display panel provided by the comparative embodiment includes the array substrate shown in FIG. 7, a pixel structure on the array substrate is shown in FIGS. 8 and 9, and the topography of the resin layer on the array substrate is shown in FIG. 10.
  • the array substrate provided by the embodiment of the present disclosure is different from the array substrate provided by the comparative embodiment It is: in the array substrate provided by the embodiment of the present disclosure, the dummy drain 104 includes: a first subsection 1041 that overlaps with the main body 1021 of the dummy gate 102, and does not overlap with the main body 1021 of the dummy gate 102 The second sub-part 1042; and, the topography of the concave-convex structure in the resin layer 107 is more uniform, and the density is greater.
  • the main body portion 1021 of the dummy drain 104 and the dummy gate 102 overlap with each other; the concave-convex structure in the resin layer 107 above the dummy drain 104 has a deeper topography, and the resin layer in other regions The topography of the concave-convex structure in the resin layer 107 is relatively shallow; and the density of the concave-convex structure in the resin layer 107 is relatively small.
  • DP in Table 1 represents the side where the Pad terminal with IC chip and flexible circuit board (FPC) is located
  • DO represents the side opposite to the side where the Pad terminal is located
  • L represents the left side of the side where the Pad terminal is located
  • R represents the side on the side where the Pad terminal is located.
  • the liquid crystal display panel provided by this design at different angles is better than the relevant data of the comparative example. Therefore, the liquid crystal display panel provided by the embodiment of the present disclosure has better optical performance, and its reflectivity And display uniformity are both high.
  • the embodiments of the present disclosure also provide a display device, including the above-mentioned liquid crystal display panel provided in the embodiments of the present disclosure.
  • the display device may be: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame , Navigators, smart watches, fitness wristbands, personal digital assistants and other products or components with display functions. Since the principle of solving the problem of the display device is similar to the principle of solving the problem of the above-mentioned liquid crystal display panel, the implementation of the display device can refer to the embodiment of the above-mentioned liquid crystal display panel, and the repetition will not be repeated.
  • the above-mentioned array substrate, liquid crystal display panel, and display device provided by the embodiments of the present disclosure include: a base substrate, a gate metal layer and a source-drain metal layer stacked in sequence on the base substrate; wherein the gate metal layer includes: mutual Independent multiple gate lines and multiple dummy gates; source-drain metal layer including: multiple independent data lines and multiple pseudo drains; dummy gate including: located in the pixel area defined by the gate lines and the data lines The inner main body part and the lead part in the extending direction of the gate line; the lead part is in contact with the edge part of the main part far away from the gate line; the dummy drain is located in the pixel area, and the dummy drain includes: and the main part The first division that overlaps with each other, and the second division that does not overlap with the main body.
  • the positive capacitance between the first subsection and the main body and the second subsection are
  • the coupling capacitor between the part and the main body together constitutes the storage capacitor of the pixel electrode, which makes the storage capacitor of the pixel electrode larger, effectively reduces the influence of leakage current, improves the degree of flicker of the picture, and improves the quality of the picture display.
  • the arrangement of the dummy drains makes the actual exposure amount irradiated on the resin layer in the pixel display area basically the same in the actual exposure process, and the uneven structure of the resin layer has better morphological uniformity, so that the same uneven structure
  • the reflective pixel electrode has a higher reflectivity, which improves the display brightness and contrast of the liquid crystal display panel, and the picture display quality is higher.

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Abstract

本公开涉及一种阵列基板、液晶显示面板及显示装置，其中，阵列基板包括：衬底基板，在所述衬底基板上依次层叠设置的栅金属层和源漏金属层；所述栅金属层包括：相互独立的多条栅线和多个伪栅极；所述源漏金属层包括：相互独立的多条数据线和多个伪漏极；所述伪栅极包括：位于所述栅线与所述数据线所限定的像素区域内的主体部和引出部；所述伪漏极位于所述像素区域内，且所述伪漏极包括：与所述主体部相互重合的第一分部，以及与所述主体部互不重叠的第二分部。

Description

阵列基板、液晶显示面板及显示装置
相关申请的交叉引用
本申请要求于2019年9月26日递交中国专利局的、申请号为201910918583.9的中国专利申请的权益，该申请的全部公开内容以引用方式并入本文。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、液晶显示面板及显示装置。
背景技术
反射率和功耗是衡量反射型液晶显示面板产品的性能的一个重要指标。为提高全反射LCD的反射率，相关技术的反射型液晶显示面板在TFT的反射层制作出具有凹凸结构的树脂层，树脂层下方膜层有的部分包含金属，有的部分不包含金属，而金属具有反光作用，导致同一像素中不同位置的凹凸结构的形貌和坡度角不同，使得反射率差，亮度显示不均匀等问题。显示器的功耗与显示频率成正比，相关技术的反射型液晶显示面板为了降低产品功耗，一般降低显示驱动频率，如使用1Hz等低频驱动。但在降低显示驱动频率后，像素电压的保持时间增长，因漏电流的存在致使像素电压不断减小，显示画面容易出现闪烁，影响显示效果。
发明内容
根据本公开的一个方面，提供一种阵列基板，包括：衬底基板，在所述衬底基板上依次层叠设置的栅金属层和源漏金属层；其中，
所述栅金属层包括：相互独立的多条栅线和多个伪栅极；
所述源漏金属层包括：相互独立的多条数据线和多个伪漏极；
所述伪栅极包括：位于所述栅线与所述数据线所限定的像素区域内的主体部和引出部；
所述伪漏极位于所述像素区域内，且所述伪漏极包括：与所述主体部相互重合的第一分部，以及与所述主体部互不重叠的第二分部。
在一些实施例中，所述阵列基板还包括：位于所述栅金属层与所述源漏金属层之间的栅绝缘层，以及位于所述源漏金属层背离所述衬底基板一侧的多个反射型像素电极；
每一个所述伪漏极与限定其所在所述像素区域的所述栅线以及所述数据线之间的距离x满足以下公式：
Figure PCTCN2020116497-appb-000001
其中，C st为所述反射型像素电极的存储电容，ε为所述栅绝缘层的介电常数，d为所述栅绝缘层的厚度，L为所述栅线或所述数据线的宽度。
在一些实施例中，所述存储电容为所述第一分部与所述主体部之间的正对电容，以及所述第二分部与所述主体部之间的耦合电容之和。
在一些实施例中，所述源漏金属层还包括：漏极，所述漏极通过所述伪漏极与所述反射型像素电极电连接。
在一些实施例中，所述阵列基板还包括：具有凹凸结构的树脂层；
所述树脂层位于各所述反射型像素电极所在层与所述源漏金属层之间；
各所述反射型像素电极具有与所述树脂层相同的凹凸结构。
在一些实施例中，所述凹凸结构的坡度为5°～15°。
在一些实施例中，所述引出部沿所述栅线的延伸方向延伸，并且所述引出部与所述主体部的远离所述栅线一侧的边缘部分相接触。
在一些实施例中，所述阵列基板还包括：位于所述树脂层与各所述反射型像素电极所在层之间的绝缘层；
所述绝缘层具有与所述树脂层相同的凹凸结构。
在一些实施例中，所述栅金属层还包括：栅极，所述栅极为双栅极结构。
根据本公开的另一方面，提供一种液晶显示面板，其特征在于，包括：相对而置的阵列基板和对向基板；所述阵列基板为上述阵列基板。
在一些实施例中，所述液晶显示面板包括位于所述对向基板或所述阵列基板上的公共电极；所述伪栅极与所述公共电极加载相同的电信号。
根据本公开的另一方面，提供一种显示装置，其特征在于，包括上述液晶显示面板。
附图说明
图1为本公开实施例提供的阵列基板的显微镜图；
图2为本公开实施例提供的阵列基板中一个像素结构的俯视结构示意图；
图3为图2中沿AA’线的剖面结构示意图；
图4为图2所示像素结构的等效电路示意图；
图5为本公开实施例提供的树脂层的设计原理图；
图6为本公开实施例提供的树脂层的3D效果图；
图7为对比实施例提供的阵列基板的显微镜图；
图8为对比实施例提供的阵列基板中一个像素结构的俯视结构示意图；
图9为图8中沿BB’线的剖面结构示意图；以及
图10为对比实施例提供的树脂层的3D效果图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有 其它实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面结合附图，对本公开实施例提供的阵列基板、液晶显示面板及显示装置的具体实施方式进行详细地说明。附图中各膜层的厚度和形状不反映真实比例，目的只是示意说明本公开内容。
本公开实施例提供的一种阵列基板，如图1所示，包括多个像素结构P，并且，每个像素结构P具体如图2和图3所示，包括：衬底基板100，在衬底基板100上依次层叠设置的栅金属层和源漏金属层；其中，
栅金属层，包括：相互独立的多条栅线101和多个伪栅极102；
源漏金属层，包括：相互独立的多条数据线103和多个伪漏极104；
伪栅极102，包括：位于栅线101与数据线103所限定像素区域内的主体部1021，以及在栅线101延伸方向上的引出部1022；引出部1022与主体部1021远离栅线一侧的边缘部分相接触；
伪漏极104位于像素区域内，且伪漏极104，包括：与主体部1021相互重合的第一分部1041，以及与主体部1021互不重叠的第二分部1042。
在本公开实施例提供的上述阵列基板中，通过设置伪漏极104与伪栅极102的主体部1021具有相互重合的第一分部1041，以及互不重叠的第二分部1042，使得第一分部1041与主体部1021之间的正对电容，以及第二分部1042与主体部1021之间的耦合电容共同构成像素电极的存储电容，使得像素电极 的存储电容较大，有效降低了漏电流的影响，改善了画面闪烁程度，提高了画面显示质量。
可选地，在本公开实施例提供的上述阵列基板中，为保证伪漏极104在像素区域内最大化填充，且栅线101和数据线103上的电压变化不会对像素电压起到不利的拉动作用，需要确保伪漏极104与栅线101、数据线103、像素结构中的晶体管均无正对电容产生；且使得伪漏极104分别与栅线101和数据线103之间产生的耦合电容小于某一数值。具体地，根据实际产品经验，伪漏极104分别与栅线101和数据线103之间产生的耦合电容C 0小于或等于像素电极存储电容C st的千分之一，即C 0≤C st/1000。并且，根据平行板电容器边缘效应的计算公式：
Figure PCTCN2020116497-appb-000002
其中，ε为栅绝缘层105的介电常数，d为栅绝缘层10的厚度，L为栅线101或数据线103的宽度，x为伪漏极104与栅线101或数据线103之间的距离。
由上述分析可知，可选地，为避免栅线101、数据线103上的电压对像素电极的拉动作用，且保证伪漏极104在像素区域内最大化填充，在本公开实施例提供的上述阵列基板中，如图2和图3所示，还包括：位于栅金属层与源漏金属层之间的栅绝缘层105，以及位于源漏金属层背离衬底基板100一侧的多个反射型像素电极106；
每一伪漏极104与限定其所在像素区域的栅线101，以及数据线103之间的距离x满足以下公式：
Figure PCTCN2020116497-appb-000003
其中，C st为反射型像素电极106的存储电容，ε为栅绝缘层105的介电常数，d为栅绝缘层105的厚度，L为栅线101或数据线103的宽度。
需要说明的是，在本公开实施例提供的上述阵列基板中，如图2所示，栅金属层的栅极为双栅极结构，双栅极结构与两条栅线101电连接，与伪漏极104距离为x的栅线101具体是指与该伪漏极104较近的栅线101。
此外，值得注意的是，在本公开实施例提供的上述阵列基板中，每一伪漏极104与限定其所在像素区域的栅线101之间的距离x，以及该伪漏极104与限定其所在像素区域的数据线103之间的距离x的取值可以相同，也可以不同，在此不做限定。
具体地，在本公开实施例提供的上述阵列基板中，反射型像素电极106的存储电容C st为第一分部与主体部1021之间的正对电容C st1，以及第二分部与主体部1021之间的耦合电容C st2之和。
可选地，在本公开实施例提供的上述阵列基板中，源漏金属层，还包括：漏极109，漏极109通过伪漏极104与反射型像素电极106电连接。在具体实施时，伪漏极104与反射型像素电极106之间经由过孔H电连接，如图2和图3所示。
如图4所示，为本公开实施例提供的上述阵列基板中一个像素结构的等效电路图。根据该等效电路图可知，数据线103的电压变化而引起的像素电压变化量ΔV pd可用以下公式表示：
Figure PCTCN2020116497-appb-000004
其中，C pd表示反射型像素电极106与数据线103之间的电容，Cst表示反射型像素电极106的存储电容(即第一分部与主体部1021之间的正对电容C st1，以及第二分部与主体部1021之间的耦合电容C st2之和)，C pg表示反射型像素电极106与栅线101之间的电容，C lc表示反射型像素电极106与液晶分子之间的电容，V dh-V dl表示数据线103的电压变化量。由上述公式可以看出，反射型像素电极106的存储电容Cst增大，则数据线103的电压变化而引起的像素电压变化量ΔV pd减小；也就是说数据线103的电压变化随着反射型像素电极 106的存储电容Cst增大而减小，因此，本公开提供的技术方案，可有效防止闪烁，提高画面显示质量，同时兼容低功耗。
相关技术中，反射型液晶显示面板中存在反射率低，外界光源依赖性强等问题，而反射率是衡量反射型产品性能的一个重要指标。可选地，为提高反射率，在本公开实施例提供的上述阵列基板中，如图3所示，还可以包括：具有凹凸结构的树脂层107；
树脂层107位于各反射型像素电极106所在层与源漏金属层之间；
各反射型像素电极106具有与树脂层107相同的凹凸结构。
通过设置具有凹凸结构的树脂层107，使得反射型像素电极106与树脂层107具有相同的凹凸结构，以致入射光在具有凹凸结构的反射型像素电极106上可发生漫反射，从而提高反射率，进而提高亮度和对比度。
目前，对反射型液晶显示面板的评价方法，主要是采用光线以30°角入射至反射型液晶显示面板，对其主视角(即与a方向具有±5°夹角的视角范围)下的反射率和对比度进行评价，如图5所示。
根据折射定律则有：
Figure PCTCN2020116497-appb-000005
其中，θ 1表示光线的入射角，为30°；θ 2表示光线在液晶显示面板内的折射角；n cell表示液晶显示面板的折射率，约为1.5；n air表示空气的折射率，为1。由此可得折射角θ 2为arcsin(1/3)。
且根据反射定律则有：
Figure PCTCN2020116497-appb-000006
其中，θ 3表示光线在凹凸结构上的入射角，θ 4表示光线在凹凸结构上的反射角，θ 5表示光线在凹凸结构的坡度角，在本文中，凹凸结构的坡度角定义为在凹凸结构的最低点和最高点之间的垂直距离的一半处的坡面的切线与水平线之间的夹角。
基于此，在本公开实施例提供的上述阵列基板中，可设置凹凸结构的坡度为5°～15°，从而提高主视角的亮度，并扩大视角范围。
具体地，可通过以下方法制作具有凹凸结构的树脂层107：采用旋涂法在阵列基板上涂覆一层具有一定厚度的树脂，然后在树脂上方放置带有凹凸(Bump)图形的遮光罩，经过曝光、显影和退火处理后，形成具有凹凸结构的树脂层107。并且，在实际制作过程中，由于伪漏极104包含的第一分部和第二分部的设置，使得整个像素区域内树脂层107下方膜层的均一性较好(即树脂层107的绝大部分下方都存在伪漏极104的金属膜层)，因此实际曝光过程中，像素显示区域内照射在树脂层107上的实际曝光量基本相同，树脂层107的凹凸结构形貌均一性较佳(如图6所示)，从而使得具有相同凹凸结构的反射型像素电极106的反射率较高，提高了液晶显示面板显示亮度和对比度，画面显示品质较高。
可选地，在本公开实施例提供的上述阵列基板中，如图3所示，还包括：位于树脂层107与各反射型像素电极106所在层之间的绝缘层108；
绝缘层108具有与树脂层107相同的凹凸结构。
基于同一发明构思，本公开实施例还提供了一种液晶显示面板，包括：相对而置的阵列基板和对向基板；阵列基板为本公开实施例提供的上述阵列基板。由于该液晶显示面板解决问题的原理与上述阵列基板解决问题的原理相似，因此，该液晶显示面板的实施可以参见上述阵列基板的实施例，重复之处不再赘述。
可选地，为使得伪栅极102与伪漏极104之间形成反射型像素电极106的存储电容C st，在本公开实施例提供的上述液晶显示面板中，还包括：位于对向基板或阵列基板上的公共电极；
伪栅极102与公共电极加载相同的电信号。
在本公开实施例提供的上述阵列基板中，伪栅极102(Dummy Gate)上加载公共电压(V com)信号，伪漏极104(Dummy SD)上加载像素电压(Pixel) 信号，从而使得伪栅极102与伪漏极104之间构成反射型像素电极106的存储电容C st。
为更好地说明本公开实施例的技术方案，以下将通过一组对比实施例进行说明。
具体地，本公开实施例提供的液晶显示面板包含图1所示阵列基板，该阵列基板上一个像素结构如图2和图3所示，该阵列基板上树脂层的形貌如图6所示。对比实施例提供的液晶显示面板包含图7所示阵列基板，该阵列基板上一个像素结构如图8和图9所示，该阵列基板上树脂层的形貌如图10所示。
将图1与图7、图2与图8、图3与图9、图6与图10分别进行对比，可知，本公开实施例提供的阵列基板与对比实施例提供的阵列基板的不同之处在于：在本公开实施例提供的阵列基板中，伪漏极104包括：与伪栅极102的主体部1021相互重合的第一分部1041，以及与伪栅极102的主体部1021互不重叠的第二分部1042；并且，树脂层107内的凹凸结构的形貌较均一，且密度较大。在对比实施例提供的阵列基板中，伪漏极104与伪栅极102的主体部1021相互重合；位于伪漏极104上方的树脂层107内凹凸结构的形貌较深，其他区域的树脂层107内凹凸结构的形貌较浅；并且树脂层107内凹凸结构的密度较小。
相应地，在本申请中还针对上述实施例组中的阵列基板的反射率进行了测试，结果如表1所示。其中，表1的DP表示具有IC芯片和柔性电路板(FPC)的Pad端子所在侧，DO表示Pad端子所在侧的相对侧，L表示Pad端子所在侧的左侧，R表示Pad端子所在侧的右侧。
由表1可以看出，本设计提供的液晶显示面板在不同角度的反射率均优于对比实施例的相关数据，因此本公开实施例提供的液晶显示面板具有更优的光学性能，其反射率和显示均一性均较高。
表1
Figure PCTCN2020116497-appb-000007
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述液晶显示面板，该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。由于该显示装置解决问题的原理与上述液晶显示面板解决问题的原理相似，因此，该显示装置的实施可以参见上述液晶显示面板的实施例，重复之处不再赘述。
本公开实施例提供的上述阵列基板、液晶显示面板及显示装置，包括：衬底基板，在衬底基板上依次层叠设置的栅金属层和源漏金属层；其中，栅金属层，包括：相互独立的多条栅线和多条伪栅极；源漏金属层，包括：相互独立的多条数据线和多个伪漏极；伪栅极，包括：位于栅线与数据线所限定像素区域内的主体部，以及在栅线延伸方向上的引出部；引出部与主体部远离栅线一侧的边缘部分相接触；伪漏极位于像素区域内，且伪漏极，包括：与主体部相互重合的第一分部，以及与主体部互不重叠的第二分部。通过设置伪漏极与伪栅极的主体部具有相互重合的第一分部，以及互不重叠的第二分部，使得第一分部与主体部之间的正对电容，以及第二分部与主体部之间的耦合电容共同构成像素电极的存储电容，使得像素电极的存储电容较大，有效降低了漏电流的影响，改善了画面闪烁程度，提高了画面显示质量。此外，伪漏极的设置方式使得，实际曝光过程中，像素显示区域内照射在树脂层上的实际曝光量基本相同，树脂层的凹凸结构形貌均一性较佳，从而使得具有相同凹凸结构的反射型像素电极的反射率较高，提高了液晶显示面板显示亮度和对比度，画面显示品质较高。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (12)

  1. 一种阵列基板，其特征在于，包括：衬底基板，在所述衬底基板上依次层叠设置的栅金属层和源漏金属层；其中，
    所述栅金属层包括：相互独立的多条栅线和多个伪栅极；
    所述源漏金属层包括：相互独立的多条数据线和多个伪漏极；
    所述伪栅极包括：位于所述栅线与所述数据线所限定的像素区域内的主体部和引出部；
    所述伪漏极位于所述像素区域内，且所述伪漏极包括：与所述主体部相互重合的第一分部，以及与所述主体部互不重叠的第二分部。
  2. 如权利要求1所述的阵列基板，其特征在于，还包括：位于所述栅金属层与所述源漏金属层之间的栅绝缘层，以及位于所述源漏金属层背离所述衬底基板一侧的多个反射型像素电极；
    每一个所述伪漏极与限定其所在所述像素区域的所述栅线以及所述数据线之间的距离x满足以下公式：
    Figure PCTCN2020116497-appb-100001
    其中，C st为所述反射型像素电极的存储电容，ε为所述栅绝缘层的介电常数，d为所述栅绝缘层的厚度，L为所述栅线或所述数据线的宽度。
  3. 如权利要求2所述的阵列基板，其特征在于，所述存储电容为所述第一分部与所述主体部之间的正对电容，以及所述第二分部与所述主体部之间的耦合电容之和。
  4. 如权利要求2所述的阵列基板，其特征在于，所述源漏金属层还包括：漏极，所述漏极通过所述伪漏极与所述反射型像素电极电连接。
  5. 如权利要求2-4任一项所述的阵列基板，其特征在于，还包括：具有凹凸结构的树脂层；
    所述树脂层位于各所述反射型像素电极所在层与所述源漏金属层之间；
    各所述反射型像素电极具有与所述树脂层相同的凹凸结构。
  6. 如权利要求5所述的阵列基板，其特征在于，所述凹凸结构的坡度为5°～15°。
  7. 如权利要求1所述的阵列基板，其特征在于，所述引出部沿所述栅线的延伸方向延伸，并且所述引出部与所述主体部的远离所述栅线一侧的边缘部分相接触。
  8. 如权利要求5所述的阵列基板，其特征在于，还包括：位于所述树脂层与各所述反射型像素电极所在层之间的绝缘层；
    所述绝缘层具有与所述树脂层相同的凹凸结构。
  9. 如权利要求1-4任一项所述的阵列基板，其特征在于，所述栅金属层还包括：栅极，所述栅极为双栅极结构。
  10. 一种液晶显示面板，其特征在于，包括：相对而置的阵列基板和对向基板；
    所述阵列基板为如权利要求1-9任一项所述的阵列基板。
  11. 如权利要求10所述的液晶显示面板，其特征在于，包括位于所述对向基板或所述阵列基板上的公共电极；
    所述伪栅极与所述公共电极加载相同的电信号。
  12. 一种显示装置，其特征在于，包括：如权利要求10或11所述的液晶显示面板。
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