WO2021063052A1 - 漏电补偿动态寄存器、数据运算单元、芯片、算力板及计算设备 - Google Patents

漏电补偿动态寄存器、数据运算单元、芯片、算力板及计算设备 Download PDF

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Publication number
WO2021063052A1
WO2021063052A1 PCT/CN2020/098902 CN2020098902W WO2021063052A1 WO 2021063052 A1 WO2021063052 A1 WO 2021063052A1 CN 2020098902 W CN2020098902 W CN 2020098902W WO 2021063052 A1 WO2021063052 A1 WO 2021063052A1
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WIPO (PCT)
Prior art keywords
terminal
leakage compensation
unit
electrically connected
data
Prior art date
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Ceased
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PCT/CN2020/098902
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English (en)
French (fr)
Inventor
张建
张楠赓
鲍进华
刘杰尧
吴敬杰
马晟厚
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Hangzhou Canaan Intelligence Information Technology Co Ltd
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Hangzhou Canaan Intelligence Information Technology Co Ltd
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Priority to CA3156061A priority Critical patent/CA3156061A1/en
Priority to EP20871371.9A priority patent/EP4040440B1/en
Priority to KR1020227013207A priority patent/KR102879270B1/ko
Priority to US17/754,079 priority patent/US11979150B2/en
Publication of WO2021063052A1 publication Critical patent/WO2021063052A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
    • G06F15/7832—Architectures of general purpose stored program computers comprising a single central processing unit without memory on one IC chip (single chip microprocessors)
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters
    • H03K19/17784—Structural details for adapting physical parameters for supply voltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
    • H03K3/356147—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit using pass gates

Definitions

  • the invention relates to a storage device controlled by a clock, in particular to a leakage compensation dynamic register, a data operation unit, a chip, a computing power board and a computing device used in a large-scale data computing device.
  • FIG. 1 is a circuit structure diagram of an existing dynamic register.
  • the dynamic register includes a transmission gate 101, a tri-state inverter 102, and an inverter 103 connected in series between an input terminal D and an output terminal Q.
  • a node S0 is formed between the transmission gate 101 and the three-state inverter 102
  • a node S1 is formed between the three-state inverter 102 and the inverter 103.
  • the data passes through the three-state inverter 102 and the parasitic of the transistor in the inverter 103.
  • the capacitor temporarily exists at node S0 and/or node S1. However, the node S0 is prone to dynamic leakage, resulting in the loss of temporarily stored data.
  • the present invention provides a leakage compensation dynamic register, which can effectively compensate the dynamic leakage current of the node and improve the safety and accuracy of data.
  • the present invention provides a leakage compensation dynamic register, which includes an input terminal for inputting a piece of data; an output terminal for outputting the data; a clock signal terminal for providing a clock signal; an analog A switch unit, which transmits the data under the control of the clock signal; a data latch unit, which latches the data under the control of the clock signal; an output drive unit, which is used to invert and output the data latch
  • the data received by the storage unit; the analog switch unit, the data latch unit, and the output drive unit are sequentially connected in series between the input terminal and the output terminal, and the analog switch unit and the output There is a node between the data latch units; wherein, a leakage compensation unit is further included, and the leakage compensation unit is electrically connected between the node and the output terminal.
  • the leakage compensation unit has a first terminal, a second terminal, and a control terminal.
  • the first terminal is electrically connected to the output terminal, and the second terminal is electrically connected to the output terminal. Connect to the node.
  • the leakage compensation unit includes a PMOS transistor and an NMOS transistor, and the PMOS transistor and the NMOS transistor are connected in series between the output terminal and the node.
  • the above-mentioned leakage compensation dynamic register wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, and the PMOS transistor The source terminal is electrically connected to the output terminal, the drain terminal is electrically connected to the drain terminal of the NMOS transistor, and the source terminal of the NMOS transistor is electrically connected to the node.
  • the PMOS transistor is connected in parallel with the gate terminal of the NMOS transistor and electrically connected to a power source.
  • the PMOS transistor is connected in parallel with the gate terminal of the NMOS transistor and electrically connected to the node.
  • the above-mentioned leakage compensation dynamic register wherein the PMOS transistor has a source terminal, a drain terminal and a gate terminal, the NMOS transistor has a source terminal, a drain terminal and a gate terminal, and the NMOS transistor The source terminal is electrically connected to the output terminal, the drain terminal is electrically connected to the drain terminal of the PMOS transistor, and the source terminal of the PMOS transistor is electrically connected to the node.
  • the PMOS transistor is connected in parallel with the gate terminal of the NMOS transistor and electrically connected to a ground.
  • the PMOS transistor is connected in parallel with the gate terminal of the NMOS transistor and electrically connected to the node.
  • the leakage compensation unit includes a PMOS transistor, the PMOS transistor has a source terminal, a drain terminal, and a gate terminal, and the source terminal of the PMOS transistor is electrically connected to the PMOS transistor.
  • the drain terminal is electrically connected to the node, and the gate terminal is electrically connected to a power source.
  • the leakage compensation unit includes an NMOS transistor, the NMOS transistor has a source terminal, a drain terminal, and a gate terminal, and the drain terminal of the NMOS transistor is electrically connected to the NMOS transistor.
  • the source terminal is electrically connected to the node
  • the gate terminal is electrically connected to a ground.
  • the clock signal includes a first clock signal and a second clock signal, and the first clock signal is inverted from the second clock signal.
  • the analog switch unit is a transmission gate.
  • the data latch unit is a three-state inverter.
  • the output driving unit is an inverter.
  • the leakage compensation dynamic register of the present invention By using the leakage compensation dynamic register of the present invention, the leakage current can be fed back to the node from the output end, the dynamic leakage current of the node can be compensated, the stability of data storage can be improved, and the safety and accuracy of the data can be enhanced.
  • the present invention also provides a data operation unit, including a control circuit, an arithmetic circuit, and a plurality of leakage compensation dynamic registers that are interconnected, and the plurality of leakage compensation dynamic registers are connected in series and/or in parallel. Connection; wherein, the multiple leakage compensation dynamic registers are any of the above-mentioned leakage compensation dynamic registers.
  • the present invention also provides a chip, which includes at least one data operation unit described above.
  • the present invention also provides a computing power board for computing equipment, which includes at least one of the above-mentioned chips.
  • the present invention also provides a computing device, including a power supply board, a control board, a connecting board, a heat sink, and a plurality of computing power boards.
  • the control board communicates with the computing power board through the connecting board.
  • the power board is connected, the heat sink is arranged around the power board, and the power board is used to provide power to the connection board, the control board, the heat sink, and the power board, wherein:
  • the hashrate board is the aforementioned hashrate board.
  • Figure 1 is a schematic diagram of the circuit structure of an existing dynamic register
  • FIG. 2 is a schematic diagram of a circuit structure of a leakage compensation dynamic register according to an embodiment of the present invention
  • FIG. 3 is a schematic diagram of a circuit structure of a leakage compensation dynamic register according to another embodiment of the present invention.
  • FIG. 4 is a schematic diagram of the circuit structure of a leakage compensation dynamic register according to another embodiment of the present invention.
  • FIG. 5 is a schematic diagram of the circuit structure of a leakage compensation dynamic register according to another embodiment of the present invention.
  • FIG. 6 is a schematic diagram of the circuit structure of a leakage compensation dynamic register according to an extended embodiment of the present invention.
  • FIG. 7 is a schematic diagram of the circuit structure of a leakage compensation dynamic register according to another extended embodiment of the present invention.
  • FIG. 8 is a schematic diagram of the structure of the data operation unit of the present invention.
  • Figure 9 is a schematic diagram of the structure of the chip of the present invention.
  • Figure 10 is a schematic diagram of the structure of the hash board of the present invention.
  • FIG. 11 is a schematic diagram of the structure of the computing device of the present invention.
  • 201P, 202P1, 202P2, 204P PMOS transistor
  • 201N, 202N1, 202N2, 204N NMOS transistor
  • connection here includes any direct and indirect electrical connection means. Indirect electrical connection means include connection through other devices.
  • the leakage compensation dynamic register 200 includes an input terminal D, an output terminal Q, a clock signal terminal CKN, a clock signal terminal CKP, an analog switch unit 201, a data latch unit 202, an output drive unit 203, and a leakage compensation unit 204 .
  • the analog switch unit 201, the data latch unit 202, and the output drive unit 203 are sequentially connected in series between the input terminal D and the output terminal Q, and a node S0 is formed between the analog switch unit 201 and the data latch unit 202.
  • the leakage compensation unit 204 is electrically connected between the node S0 and the output terminal Q.
  • the input terminal D is used to input data
  • the output terminal is used to output data
  • the clock signal terminal CKN and the clock signal terminal CKP are used to provide a clock signal CKN and a clock signal CKP
  • the clock signal CKN and the clock signal CKP are inverted clock signals.
  • the analog switch unit 201 of the leakage compensation dynamic register 200 has a transmission gate structure, and the analog switch unit 201 includes a PMOS transistor 201P and an NMOS transistor 201N connected in parallel.
  • the source terminal of the PMOS transistor 201P is connected in parallel with the source terminal of the NMOS transistor 201N, and is electrically connected to the input terminal D
  • the drain terminal of the PMOS transistor 201P is connected in parallel with the drain terminal of the NMOS transistor 201N, and is electrically connected to the node S0 .
  • the gate terminal of the NMOS transistor 201N is electrically connected to the clock signal CKN, and the gate terminal of the PMOS transistor 201P is electrically connected to the clock signal CKP.
  • CKP is at a low level
  • CKN is at a high level
  • the PMOS transistor 201P and the NMOS transistor 201N are both turned on, and the data at the input terminal D is transmitted to the node S0 through the analog switch unit 201.
  • CKP is at a high level
  • CKN is at a low level
  • the PMOS transistor 201P and the NMOS transistor 201N are both in a non-conducting state, and the data at the input terminal D cannot be transmitted to the node S0 through the analog switch unit 201.
  • the analog switch unit 201 uses a transmission gate structure as an example.
  • it can also be other forms of analog switch units, as long as the switch function can be realized under the control of a clock signal, and the present invention does not take this as an example. limit.
  • the data latch unit 202 of the leakage compensation dynamic register 200 has a three-state inverter structure.
  • the data latch unit 202 includes PMOS transistors 202P1, 202P2, and NMOS connected in series between the power supply VDD and the ground VSS.
  • the gate terminals of the PMOS transistor 202P1 and the NMOS transistor 202N2 are connected together to form the input terminal of the data latch unit 202.
  • the drain terminals of the PMOS transistor 202P2 and the NMOS transistor 202N1 are connected together to form the output terminal of the data latch unit 202.
  • the source terminal of the PMOS transistor 202P1 is connected to the power supply VDD, and the source terminal of the NMOS transistor 202N2 is connected to the ground VSS.
  • the source terminal of the PMOS transistor 202P2 is connected to the drain terminal of the PMOS transistor 202P1, and the source terminal of the NMOS transistor 202N1 is connected to the drain terminal of the NMOS transistor 202N2.
  • the gate terminal of the PMOS transistor 202P2 is controlled by the clock signal CKN
  • the gate terminal of the NMOS transistor 202N1 is controlled by the clock signal CKP as the clock control terminal of the data latch unit 202.
  • the gate terminal of the PMOS transistor 20212 is controlled by the clock signal CKN
  • the gate terminal of the NMOS transistor 202N2 is controlled by the clock signal CKP, and the present invention is not limited to this.
  • the output driving unit 203 of the dynamic register 200 has an inverter structure.
  • the data received from the data latch unit 202 is inverted again to form data with the same phase as the data at the input terminal D, and the data The data is output through the output terminal Q.
  • the output drive unit can also improve the data drive capability.
  • the leakage compensation dynamic register 200 further includes a leakage compensation unit 204.
  • the leakage compensation unit 204 includes a PMOS transistor 204P and an NMOS transistor 204N.
  • the PMOS transistor 204P and the NMOS transistor 204N are connected in series between the output terminal Q and the node S0.
  • the source terminal of the PMOS transistor 204P is electrically connected to the output terminal Q
  • the drain terminal of the PMOS transistor 204P is electrically connected to the drain terminal of the NMOS transistor 204N
  • the source terminal of the NMOS transistor 204N is electrically connected to the node S0
  • the gate terminals of 204N are connected in parallel and electrically connected to the power supply VDD.
  • the leakage compensation unit 204 can feed back the leakage current of the output terminal Q to the node S0 to compensate the dynamic leakage current at the node S0, improve the stability of data storage, and thereby enhance the security and accuracy of the data.
  • the leakage compensation dynamic register 200 includes an input terminal D, an output terminal Q, a clock signal terminal CKN, a clock signal terminal CKP, an analog switch unit 201, a data latch unit 202, an output drive unit 203, and a leakage compensation unit 204 .
  • the analog switch unit 201, the data latch unit 202, and the output drive unit 203 are sequentially connected in series between the input terminal D and the output terminal Q, and a node S0 is formed between the analog switch unit 201 and the data latch unit 202.
  • the leakage compensation unit 204 is electrically connected between the node S0 and the output terminal Q.
  • the input terminal D is used to input data
  • the output terminal is used to output data
  • the clock signal terminal CKN and the clock signal terminal CKP are used to provide a clock signal CKN and a clock signal CKP
  • the clock signal CKN and the clock signal CKP are inverted clock signals.
  • the analog switch unit 201 of the leakage compensation dynamic register 200 has a transmission gate structure, and the analog switch unit 201 includes a PMOS transistor 201P and an NMOS transistor 201N connected in parallel.
  • the source terminal of the PMOS transistor 201P is connected in parallel with the source terminal of the NMOS transistor 201N, and is electrically connected to the input terminal D
  • the drain terminal of the PMOS transistor 201P is connected in parallel with the drain terminal of the NMOS transistor 201N, and is electrically connected to the node S0 .
  • the gate terminal of the NMOS transistor 201N is electrically connected to the clock signal CKN
  • the gate terminal of the PMOS transistor 201P is electrically connected to the clock signal CKP.
  • the analog switch unit 201 uses a transmission gate structure as an example. Of course, it can also be other forms of analog switch units, as long as the switch function can be realized under the control of a clock signal, and the present invention does not take this as an example. limit.
  • the data latch unit 202 of the leakage compensation dynamic register 200 has a three-state inverter structure.
  • the data latch unit 202 includes PMOS transistors 202P1, 202P2 and NMOS connected in series between the power supply VDD and the ground VSS. Transistors 202N1 and 202N2.
  • the gate terminals of the PMOS transistor 202P1 and the NMOS transistor 202N2 are connected together to form the input terminal of the data latch unit 202.
  • the drain terminals of the PMOS transistor 202P2 and the NMOS transistor 202N1 are connected together to form the output terminal of the data latch unit 202.
  • the source terminal of the PMOS transistor 202P1 is connected to the power supply VDD, and the source terminal of the NMOS transistor 202N2 is connected to the ground VSS.
  • the source terminal of the PMOS transistor 202P2 is connected to the drain terminal of the PMOS transistor 202P1, and the source terminal of the NMOS transistor 202N1 is connected to the drain terminal of the NMOS transistor 202N2.
  • the gate terminal of the PMOS transistor 202P2 is controlled by the clock signal CKN
  • the gate terminal of the NMOS transistor 202N1 is controlled by the clock signal CKP as the clock control terminal of the data latch unit 202.
  • the gate terminal of the PMOS transistor 20212 is controlled by the clock signal CKN
  • the gate terminal of the NMOS transistor 202N2 is controlled by the clock signal CKP, and the present invention is not limited to this.
  • the output driving unit 203 of the dynamic register 200 has an inverter structure.
  • the data received from the data latch unit 202 is inverted again to form data with the same phase as the data at the input terminal D, and the data The data is output through the output terminal Q.
  • the output drive unit can also improve the data drive capability.
  • the leakage compensation dynamic register 200 further includes a leakage compensation unit 204.
  • the leakage compensation unit 204 includes a PMOS transistor 204P and an NMOS transistor 204N.
  • the PMOS transistor 204P and the NMOS transistor 204N are connected in series between the output terminal Q and the node S0.
  • the source terminal of the PMOS transistor 204P is electrically connected to the node S0, the drain terminal of the PMOS transistor 204P is electrically connected to the drain terminal of the NMOS transistor 204N, the source terminal of the NMOS transistor 204N is electrically connected to the output terminal Q, the PMOS transistor 204P and the NMOS transistor
  • the gate terminals of 204N are connected in parallel and electrically connected to the ground VSS.
  • the leakage compensation unit 204 can feed back the leakage current of the output terminal Q to the node S0, can compensate the leakage current at the node S0, improve the stability of data storage, and thereby enhance the security and accuracy of the data.
  • FIGS. 2 and 4 are schematic diagram of the circuit structure of a leakage compensation dynamic register according to another embodiment of the present invention. As shown in FIGS. 2 and 4, the difference from the embodiment shown in FIG. 2 is that in this embodiment, in the leakage compensation unit 204, the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are connected in parallel, and Sexual connection node S0.
  • the leakage feedback unit 205 can feed back the leakage current of the output terminal Q to the node S0, can compensate the leakage current at the node S0, improve the stability of data storage, and thereby enhance the security and accuracy of the data.
  • FIG. 5 is a schematic diagram of the circuit structure of a leakage compensation dynamic register according to another embodiment of the present invention. As shown in FIGS. 3 and 5, the difference from the embodiment shown in FIG. 3 is that in this embodiment, in the leakage compensation unit 204, the gate terminals of the PMOS transistor 204P and the NMOS transistor 204N are connected in parallel, and Sexual connection node S0.
  • the leakage feedback unit 205 can feed back the leakage current of the output terminal Q to the node S0, can compensate the leakage current at the node S0, improve the stability of data storage, and thereby enhance the security and accuracy of the data.
  • the leakage compensation unit 204 of the leakage compensation dynamic register 200 includes a PMOS transistor 204P, the source terminal of the PMOS transistor 204P is electrically connected to the output terminal, the drain terminal of the PMOS transistor 204P is electrically connected to the node S0, and the PMOS transistor 204P The gate terminal of is electrically connected to the power supply VDD.
  • the leakage compensation unit 204 can feed back the leakage current of the output terminal Q to the node S0, can compensate the leakage current at the node S0, improve the stability of data storage, and thereby enhance the security and accuracy of the data.
  • FIG. 7 is a schematic diagram of the circuit structure of a leakage compensation dynamic register according to another extended embodiment of the present invention.
  • the leakage compensation unit 204 of the leakage compensation dynamic register 200 includes an NMOS transistor 204N.
  • the source terminal of the NMOS transistor 204N is electrically connected to the node S0
  • the drain terminal of the NMOS transistor 204N is electrically connected to the output terminal Q
  • the NMOS transistor The gate terminal of 204N is electrically connected to the ground VSS.
  • the leakage compensation unit 204 can feed back the leakage current of the output terminal Q to the node S0, can compensate the leakage current at the node S0, improve the stability of data storage, and thereby enhance the security and accuracy of the data.
  • FIG. 8 is a schematic diagram of the structure of the data operation unit of the present invention.
  • the data operation unit 800 includes a control circuit 801, an operation circuit 802 and a plurality of dynamic registers 200.
  • the control circuit 801 refreshes the data in the dynamic register 200 and reads data from the dynamic register 200, the operation circuit 802 performs operations on the read data, and the control circuit 801 outputs the operation result.
  • FIG. 9 is a schematic diagram of the structure of the chip of the present invention.
  • the chip 900 includes a control unit 901 and one or more data operation units 800.
  • the control unit 901 inputs data to the data operation unit 800 and processes the data output by the data operation unit 800.
  • FIG. 10 is a schematic diagram of the structure of the power computing board of the present invention. As shown in FIG. 10, each computing power board 1000 includes one or more chips 900 to perform large-scale operations on the working data delivered by the computing device.
  • FIG. 11 is a schematic diagram of the structure of the computing device of the present invention.
  • each computing device 1100 includes a connection board 1101, a control board 1102, a heat sink 1103, a power supply board 1104, and one or more computing power boards 1000.
  • the control board 1102 is connected to the hash board 1000 through the connecting board 1101, and the heat sink 1103 is arranged around the hash board 1000.
  • the power board 1104 is used to provide power to the connection board 1101, the control board 1102, the heat sink 1103 and the hash board 1000.
  • the present invention can also have various other embodiments.
  • those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding All changes and deformations shall belong to the protection scope of the appended claims of the present invention.
  • leakage compensation dynamic register of the present invention and the data operation unit, chip, computing power board and computing device using it have the following beneficial effects:
  • the leakage current can be fed back to the node from the output terminal to compensate the dynamic leakage current of the node, improve the stability of data storage, and thereby enhance the safety and accuracy of the data.

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Abstract

一种漏电补偿动态寄存器、数据运算单元、芯片、算力板及计算设备。漏电补偿动态寄存器包括一输入端(D)，一输出端(Q)，一时钟信号端(CKN,CKP)，一模拟开关单元(201)；一数据锁存单元(202)，在所述时钟信号控制下锁存数据；一输出驱动单元(203)，用于反相并输出从所述数据锁存单元(202)接收到的所述数据；所述模拟开关单元(201)、所述数据锁存单元(202)、所述输出驱动单元(203)依次串接在所述输入端(D)和所述输出端(Q)之间，所述模拟开关单元(201)和所述数据锁存单元(202)之间具有一节点(S0)；其中，还包括一漏电补偿单元(204)，所述漏电补偿单元(204)电性连接在所述节点(S0)与所述输出端(Q)之间。可以有效补偿节点(S0)的动态漏电流，提高数据的安全性和正确率。

Description

漏电补偿动态寄存器、数据运算单元、芯片、算力板及计算设备 技术领域
本发明涉及一种受时钟控制的存储器件，尤其涉及一种在大规模数据运算设备中应用的漏电补偿动态寄存器、数据运算单元、芯片、算力板及计算设备。
背景技术
动态寄存器应用非常广泛，可用做数字信号的寄存。图1为现有动态寄存器的电路结构图。如图1所示，动态寄存器包括串联连接在输入端D及输出端Q之间的传输门101、三态反相器102以及反相器103。传输门101与三态反相器102之间形成节点S0，三态反相器102与反相器103之间形成节点S1，数据通过三态反相器102以及反相器103中晶体管的寄生电容暂存在节点S0和/或节点S1。但是，节点S0容易产生动态漏电，导致所暂存的数据丢失。
因此，如何有效减少动态寄存器的动态漏电实为需要解决的问题。
发明公开
为了解决上述问题，本发明提供一种漏电补偿动态寄存器，可以有效补偿节点的动态漏电流，提高数据的安全性和正确率。
为了实现上述目的，本发明提供一种漏电补偿动态寄存器，包括一输入端，用于输入一数据；一输出端，用于输出所述数据；一时钟信号端，用于提供时钟信号；一模拟开关单元，在所述时钟信号控制下传输所述数据；一数据锁存单元，在所述时钟信号控制下锁存所述数据；一输出驱动单元，用于反相并输出从所述数据锁存单元接收到的所述数据；所述模拟开关单元、所述数据锁存单元、所述输出驱动单元依次串接在所述输入端和所述输出端之间，所述模拟开关单元和所述数据锁存单元之间具有一节点；其中，还包括一漏电补偿单元，所述漏电补偿单元电性连接在所述节点与所述输出端之间。
上述的漏电补偿动态寄存器，其中，所述漏电补偿单元具有一第一端、一第二端以及一控制端，所述第一端电性连接至所述输出端，所述第二端电性连接至所述节点。
上述的漏电补偿动态寄存器，其中，所述漏电补偿单元包括一PMOS晶体 管及一NMOS晶体管，所述PMOS晶体管及所述NMOS晶体管串联连接在所述输出端与所述节点之间。
上述的漏电补偿动态寄存器，其中，所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的所述源极端电性连接至所述输出端，所述漏极端电性连接至所述NMOS晶体管的所述漏极端，所述NMOS晶体管的所述源极端电性连接至所述节点。
上述的漏电补偿动态寄存器，其中，所述PMOS晶体管与所述NMOS晶体管的栅极端并联并电性连接至一电源。
上述的漏电补偿动态寄存器，其中，所述PMOS晶体管与所述NMOS晶体管的栅极端并联并电性连接至所述节点。
上述的漏电补偿动态寄存器，其中，所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的所述源极端电性连接至所述输出端，所述漏极端电性连接至所述PMOS晶体管的所述漏极端，所述PMOS晶体管的所述源极端电性连接至所述节点。
上述的漏电补偿动态寄存器，其中，所述PMOS晶体管与所述NMOS晶体管的栅极端并联并电性连接至一地。
上述的漏电补偿动态寄存器，其中，所述PMOS晶体管与所述NMOS晶体管的栅极端并联并电性连接至所述节点。
上述的漏电补偿动态寄存器，其中，所述漏电补偿单元包括一PMOS晶体管，所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的所述源极端电性连接至所述输出端，所述漏极端电性连接至所述节点，所述栅极端电性连接至一电源。
上述的漏电补偿动态寄存器，其中，所述漏电补偿单元包括一NMOS晶体管，所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的所述漏极端电性连接至所述输出端，所述源极端电性连接至所述节点，所述栅极端电性连接至一地。
上述的漏电补偿动态寄存器，其中，所述时钟信号包括一第一时钟信号及一第二时钟信号，所述第一时钟信号与所述第二时钟信号反相。
上述的漏电补偿动态寄存器，其中，所述模拟开关单元为传输门。
上述的漏电补偿动态寄存器，其中，所述数据锁存单元为三态反相器。
上述的漏电补偿动态寄存器，其中，所述输出驱动单元为反相器。
使用本发明的漏电补偿动态寄存器，可以从输出端反馈漏电电流到节点，补偿节点的动态漏电流，提高数据存储的稳定性，进而增强数据的安全性和正确率。
为了更好地实现上述目的，本发明还提供了一种数据运算单元，包括互联连接的控制电路、运算电路、多个漏电补偿动态寄存器，所述多个漏电补偿动态寄存器为串联和/或并联连接；其中，所述多个漏电补偿动态寄存器为上述的任意一种漏电补偿动态寄存器。
为了更好地实现上述目的，本发明还提供了一种芯片，其中，包括至少一个上述的数据运算单元。
为了更好地实现上述目的，本发明还提供了一种用于计算设备的算力板，其中，包括至少一个上述的芯片。
为了更好地实现上述目的，本发明还提供了一种计算设备，包括电源板、控制板、连接板、散热器以及多个算力板，所述控制板通过所述连接板与所述算力板连接，所述散热器设置在所述算力板的周围，所述电源板用于向所述连接板、所述控制板、所述散热器以及所述算力板提供电源，其中，所述算力板为上述的算力板。
以下结合附图和具体实施例对本发明进行详细描述，但不作为对本发明的限定。
附图简要说明
图1为现有动态寄存器的电路结构示意图；
图2为本发明一实施例漏电补偿动态寄存器的电路结构示意图；
图3为本发明又一实施例漏电补偿动态寄存器的电路结构示意图；
图4为本发明另一实施例漏电补偿动态寄存器的电路结构示意图；
图5为本发明再一实施例漏电补偿动态寄存器的电路结构示意图；
图6为本发明拓展实施例漏电补偿动态寄存器的电路结构示意图；
图7为本发明又一拓展实施例漏电补偿动态寄存器的电路结构示意图；
图8为本发明数据运算单元的结构示意图；
图9为本发明芯片的结构示意图；
图10为本发明算力板的结构示意图；
图11为本发明计算设备的结构示意图。
其中，附图标记：
100：动态寄存器
101：传输门
102：三态反相器
103：反相器
200：漏电补偿动态寄存器
201：模拟开关单元
202：数据锁存单元
203：输出驱动单元
204：漏电补偿单元
201P、202P1、202P2、204P：PMOS晶体管
201N、202N1、202N2、204N：NMOS晶体管
800：数据运算单元
801：控制电路
802：运算电路
900：芯片
901：控制单元
1000：算力板
1100：计算设备
1101：连接板
1102：控制板
1103：散热器
1104：电源板
D：输入端
Q：输出端
CKP、CKN：时钟信号
S0、S1：节点
实现本发明的最佳方式
下面结合附图对本发明的结构原理和工作原理作具体的描述：
在说明书及后续的权利要求当中使用了某些词汇来指称特定组件。所属领域中具有通常知识者应可理解，制造商可能会用不同的名词来称呼同一个组件。本说明书及后续的权利要求并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的准则。
在通篇说明书及后续的权利要求当中所提及的“包括”和“包含”为一开放式的用语，故应解释成“包含但不限定于”。以外，“连接”一词在此为包含任何直接及间接的电性连接手段。间接的电性连接手段包括通过其它装置进行连接。
实施例一：
图2为本发明一实施例漏电补偿动态寄存器的电路结构示意图。如图2所示，漏电补偿动态寄存器200包括输入端D、输出端Q、时钟信号端CKN、时钟信号端CKP、模拟开关单元201、数据锁存单元202、输出驱动单元203以及漏电补偿单元204。模拟开关单元201、数据锁存单元202以及输出驱动单元203依次串联连接在输入端D和输出端Q之间，模拟开关单元201和数据锁存单元202之间形成节点S0。漏电补偿单元204电性连接在节点S0以及输出端Q之间。其中，输入端D用于输入数据，输出端用于输出数据，时钟信号端CKN以及时钟信号端CKP用于提供时钟信号CKN以及时钟信号CKP，时钟信号CKN与时钟信号CKP为反相时钟信号。
具体的，如图2所示，漏电补偿动态寄存器200的模拟开关单元201为传输门结构，模拟开关单元201包括并联连接的PMOS晶体管201P以及NMOS晶体管201N。其中，PMOS晶体管201P的源极端与NMOS晶体管201N的源极端并联连接，并电性连接至输入端D，PMOS晶体管201P的漏极端与NMOS晶体管201N的漏极端并联连接，并电性连接至节点S0。NMOS晶体管201N的栅极端电性连接至时钟信号CKN，PMOS晶体管201P的栅极端电性连接至时钟信号CKP。当CKP为低电平时，CKN为高电平，PMOS晶体管201P与NMOS晶体管201N均为导通状态，输入端D的数据通过模拟开关单元201传送至节点S0。当CKP 为高电平时，CKN为低电平，PMOS晶体管201P与NMOS晶体管201N均为不导通状态，输入端D的数据不能通过模拟开关单元201向节点S0进行传送。在本实施例中，模拟开关单元201以传输门结构进行举例，当然，也可以是其他形式的模拟开关单元，只要能够在时钟信号的控制下实现开关功能即可，本发明并不以此为限。
继续参照图2所示，漏电补偿动态寄存器200的数据锁存单元202为三态反相器结构，数据锁存单元202包括串联连接在电源VDD以及地VSS之间的PMOS晶体管202P1、202P2以及NMOS晶体管202N1、202N2。PMOS晶体管202P1和NMOS晶体管202N2的栅极端连接在一起，形成数据锁存单元202的输入端。PMOS晶体管202P2和NMOS晶体管202N1的漏极端连接在一起，形成数据锁存单元202的输出端。PMOS晶体管202P1的源极端连接到电源VDD，NMOS晶体管202N2的源极端连接到地VSS。PMOS晶体管202P2的源极端连接到PMOS晶体管202P1的漏极端，NMOS晶体管202N1的源极端连接到NMOS晶体管202N2的漏极端。
在本实施例中，PMOS晶体管202P2的栅极端受时钟信号CKN的控制，NMOS晶体管202N1的栅极端受时钟信号CKP的控制，作为数据锁存单元202的时钟控制端。当然，也可以是PMOS晶体管20212的栅极端受时钟信号CKN的控制，NMOS晶体管202N2的栅极端受时钟信号CKP的控制，本发明并不以此为限。
当CKP为低电平时，CKN为高电平，PMOS晶体管202P2与NMOS晶体管202N1均为不导通状态，数据锁存单元202呈高阻状态，节点S0处的数据不能通过数据锁存单元202，节点S0处的数据被锁存，保持原来的状态，起到数据寄存的作用。
当CKP为高电平时，CKN为低电平，PMOS晶体管202P2与NMOS晶体管202N1均为导通状态，数据锁存单元202起到将节点S0即数据锁存单元输入端的数据进行反相的作用，此时，将节点S0处的数据进行反相，并输出到输出驱动单元203，改写输出端Q的数据。
如图2所示，动态寄存200的输出驱动单元203为反相器结构，将从数据锁存单元202接收的数据再次反相，以形成与输入端D的数据相同相位的数据，并将数据通过输出端Q将数据输出。同时，输出驱动单元还能够提高数据的驱动能力。
如图2所示，漏电补偿动态寄存器200还包括漏电补偿单元204。在本实施例中，漏电补偿单元204包括PMOS晶体管204P以及NMOS晶体管204N，PMOS晶体管204P以及NMOS晶体管204N串联连接在输出端Q以及节点S0之间。PMOS晶体管204P的源极端电性连接至输出端Q，PMOS晶体管204P的漏极端电性连接至NMOS晶体管204N的漏极端，NMOS晶体管204N的源极端电性连接至节点S0，PMOS晶体管204P以及NMOS晶体管204N的栅极端并联连接在一起，并电性连接至电源VDD。
由于PMOS晶体管204P以及NMOS晶体管204N的栅极端同样都电性连接至电源VDD，在电源VDD的高电平信号驱动下，PMOS晶体管204P处于截止状态，NMOS晶体管204N处于导通状态。此时，漏电补偿单元204可以将输出端Q的漏电电流反馈至节点S0处，补偿节点S0处的动态漏电电流，提高数据存储的稳定性，进而增强数据的安全性和正确率。
实施例二：
图3为本发明一实施例漏电补偿动态寄存器的电路结构示意图。如图3所示，漏电补偿动态寄存器200包括输入端D、输出端Q、时钟信号端CKN、时钟信号端CKP、模拟开关单元201、数据锁存单元202、输出驱动单元203以及漏电补偿单元204。模拟开关单元201、数据锁存单元202以及输出驱动单元203依次串联连接在输入端D和输出端Q之间，模拟开关单元201和数据锁存单元202之间形成节点S0。漏电补偿单元204电性连接在节点S0以及输出端Q之间。其中，输入端D用于输入数据，输出端用于输出数据，时钟信号端CKN以及时钟信号端CKP用于提供时钟信号CKN以及时钟信号CKP，时钟信号CKN与时钟信号CKP为反相时钟信号。
具体的，如图3所示，漏电补偿动态寄存器200的模拟开关单元201为传输门结构，模拟开关单元201包括并联连接的PMOS晶体管201P以及NMOS晶体管201N。其中，PMOS晶体管201P的源极端与NMOS晶体管201N的源极端并联连接，并电性连接至输入端D，PMOS晶体管201P的漏极端与NMOS晶体管201N的漏极端并联连接，并电性连接至节点S0。NMOS晶体管201N的栅极端电性连接至时钟信号CKN，PMOS晶体管201P的栅极端电性连接至时钟信号CKP。当CKP为低电平时，CKN为高电平，PMOS晶体管201P与NMOS晶体管201N均为导通状态，输入端D的数据通过模拟开关单元201传送至节点S0。当CKP 为高电平时，CKN为低电平，PMOS晶体管201P与NMOS晶体管201N均为不导通状态，输入端D的数据不能通过模拟开关单元201向节点S0进行传送。在本实施例中，模拟开关单元201以传输门结构进行举例，当然，也可以是其他形式的模拟开关单元，只要能够在时钟信号的控制下实现开关功能即可，本发明并不以此为限。
继续参照图3所示，漏电补偿动态寄存器200的数据锁存单元202为三态反相器结构，数据锁存单元202包括串联连接在电源VDD以及地VSS之间的PMOS晶体管202P1、202P2以及NMOS晶体管202N1、202N2。PMOS晶体管202P1和NMOS晶体管202N2的栅极端连接在一起，形成数据锁存单元202的输入端。PMOS晶体管202P2和NMOS晶体管202N1的漏极端连接在一起，形成数据锁存单元202的输出端。PMOS晶体管202P1的源极端连接到电源VDD，NMOS晶体管202N2的源极端连接到地VSS。PMOS晶体管202P2的源极端连接到PMOS晶体管202P1的漏极端，NMOS晶体管202N1的源极端连接到NMOS晶体管202N2的漏极端。
在本实施例中，PMOS晶体管202P2的栅极端受时钟信号CKN的控制，NMOS晶体管202N1的栅极端受时钟信号CKP的控制，作为数据锁存单元202的时钟控制端。当然，也可以是PMOS晶体管20212的栅极端受时钟信号CKN的控制，NMOS晶体管202N2的栅极端受时钟信号CKP的控制，本发明并不以此为限。
当CKP为低电平时，CKN为高电平，PMOS晶体管202P2与NMOS晶体管202N1均为不导通状态，数据锁存单元202呈高阻状态，节点S0处的数据不能通过数据锁存单元202，节点S0处的数据被锁存，保持原来的状态，起到数据寄存的作用。
当CKP为高电平时，CKN为低电平，PMOS晶体管202P2与NMOS晶体管202N1均为导通状态，数据锁存单元202起到将节点S0即数据锁存单元输入端的数据进行反相的作用，此时，将节点S0处的数据进行反相，并输出到输出驱动单元203，改写输出端Q的数据。
如图3所示，动态寄存200的输出驱动单元203为反相器结构，将从数据锁存单元202接收的数据再次反相，以形成与输入端D的数据相同相位的数据，并将数据通过输出端Q将数据输出。同时，输出驱动单元还能够提高数据的驱动能力。
如图3所示，漏电补偿动态寄存器200还包括漏电补偿单元204。与图2所示实施例不同之处在于，在本实施例中，漏电补偿单元204包括PMOS晶体管204P以及NMOS晶体管204N，PMOS晶体管204P以及NMOS晶体管204N串联连接在输出端Q以及节点S0之间。PMOS晶体管204P的源极端电性连接至节点S0，PMOS晶体管204P的漏极端电性连接至NMOS晶体管204N的漏极端，NMOS晶体管204N的源极端电性连接至输出端Q，PMOS晶体管204P以及NMOS晶体管204N的栅极端并联连接在一起，并电性连接至地VSS。
由于PMOS晶体管204P以及NMOS晶体管204N的栅极端同样都电性连接至地VSS，在地VSS低电平信号的驱动下，PMOS晶体管204P处于导通状态，NMOS晶体管204N处于截止状态。因此，漏电补偿单元204可以将输出端Q的漏电电流反馈至节点S0，可以补偿节点S0处的漏电电流，提高数据存储的稳定性，进而增强数据的安全性和正确率。
变形例：
图4为本发明另一实施例漏电补偿动态寄存器的电路结构示意图。如图2及图4所示，与图2所示实施例不同之处在于，在本实施例中，漏电补偿单元204中，PMOS晶体管204P以及NMOS晶体管204N的栅极端并联连接在一起，并电性连接节点S0。
由于PMOS晶体管205P以及NMOS晶体管205N的栅极端同样都电性连接至节点S0，在相同电平的信号驱动下，PMOS晶体管205P以及NMOS晶体管205N不会同时导通，只能有一个处于导通状态，另一个处于截止状态。例如，当节点S0处的电位为高电平时，PMOS晶体管205P处于截止状态，而NMOS晶体管205N处于导通状态；当节点S0处的电位为低电平时，PMOS晶体管205P处于导通状态，而NMOS晶体管205N处于截止状态。因此，漏电反馈单元205可以将输出端Q的漏电电流反馈至节点S0，可以补偿节点S0处的漏电电流，提高数据存储的稳定性，进而增强数据的安全性和正确率。
图5为本发明再一实施例漏电补偿动态寄存器的电路结构示意图。如图3及图5所示，与图3所示实施例不同之处在于，在本实施例中，漏电补偿单元204中，PMOS晶体管204P以及NMOS晶体管204N的栅极端并联连接在一起，并电性连接节点S0。
由于PMOS晶体管205P以及NMOS晶体管205N的栅极端同样都电性连接至 节点S0，在相同电平的信号驱动下，PMOS晶体管205P以及NMOS晶体管205N不会同时导通，只能有一个处于导通状态，另一个处于截止状态。例如，当节点S0处的电位为高电平时，PMOS晶体管205P处于截止状态，而NMOS晶体管205N处于导通状态；当节点S0处的电位为低电平时，PMOS晶体管205P处于导通状态，而NMOS晶体管205N处于截止状态。因此，漏电反馈单元205可以将输出端Q的漏电电流反馈至节点S0，可以补偿节点S0处的漏电电流，提高数据存储的稳定性，进而增强数据的安全性和正确率。
图6为本发明拓展实施例漏电补偿动态寄存器的电路结构示意图。如图6所示，漏电补偿动态寄存器200的漏电补偿单元204包括PMOS晶体管204P，PMOS晶体管204P的源极端电性连接至输出端，PMOS晶体管204P的漏极端电性连接至节点S0，PMOS晶体管204P的栅极端电性连接至电源VDD。
由于PMOS晶体管204P的栅极端电性连接至电源VDD，在电源VDD高电平信号的驱动下，PMOS晶体管204P处于截止状态。因此，漏电补偿单元204可以将输出端Q的漏电电流反馈至节点S0，可以补偿节点S0处的漏电电流，提高数据存储的稳定性，进而增强数据的安全性和正确率。
图7为本发明又一拓展实施例漏电补偿动态寄存器的电路结构示意图。如图7所示，漏电补偿动态寄存器200的漏电补偿单元204包括NMOS晶体管204N，NMOS晶体管204N的源极端电性连接至节点S0，NMOS晶体管204N的漏极端电性连接至输出端Q，NMOS晶体管204N的栅极端电性连接至地VSS。
由于NMOS晶体管204N的栅极端电性连接至地VSS，在地VSS低电平信号的驱动下，NMOS晶体管204N处于截止状态。因此，漏电补偿单元204可以将输出端Q的漏电电流反馈至节点S0，可以补偿节点S0处的漏电电流，提高数据存储的稳定性，进而增强数据的安全性和正确率。
本发明还提供一种数据运算单元，图8为本发明数据运算单元的结构示意图。如图8所示，数据运算单元800包括控制电路801、运算电路802以及多个动态寄存200。控制电路801对动态寄存200中的数据进行刷新并从动态寄存200中读取数据，运算电路802对读取的数据进行运算，再由控制电路801将运算结果输出。
本发明还提供一种芯片，图9为本发明芯片的结构示意图。如图9所示，芯片900包括控制单元901，以及一个或多个数据运算单元800。控制单元901 向数据运算单元800输入数据并将数据运算单元800输出的数据进行处理。
本发明还提供一种算力板，图10为本发明算力板的结构示意图。如图10所示，每一个算力板1000上包括一个或多个芯片900，对计算设备下发的工作数据进行大规模运算。
本发明还提供一种计算设备，所述计算设备优选用于挖掘虚拟数字货币的运算，当然所述计算设备也可以用于其他任何海量运算。图11为本发明计算设备的结构示意图。如图11所示，每一个计算设备1100包括连接板1101、控制板1102、散热器1103、电源板1104，以及一个或多个算力板1000。控制板1102通过连接板1101与算力板1000连接，散热器1103设置在算力板1000的周围。电源板1104用于向连接板1101、控制板1102、散热器1103以及算力板1000提供电源。
需要说明的是，在本发明的描述中，术语“横向”、“纵向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，并不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
换言之，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形，但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。
工业应用性
采用本发明的漏电补偿动态寄存器及应用其的数据运算单元、芯片、算力板和计算设备，具有以下有益效果：
可以从输出端反馈漏电电流到节点，补偿节点的动态漏电流，提高数据存储的稳定性，进而增强数据的安全性和正确率。

Claims (19)

  1. 一种漏电补偿动态寄存器，其特征在于，包括：
    一输入端，用于输入一数据；
    一输出端，用于输出所述数据；
    一时钟信号端，用于提供时钟信号；
    一模拟开关单元，在所述时钟信号控制下传输所述数据；
    一数据锁存单元，在所述时钟信号控制下锁存所述数据；
    一输出驱动单元，用于反相并输出从所述数据锁存单元接收到的所述数据；
    所述模拟开关单元、所述数据锁存单元、所述输出驱动单元依次串接在所述输入端和所述输出端之间，所述模拟开关单元和所述数据锁存单元之间具有一节点；
    其中，还包括一漏电补偿单元，所述漏电补偿单元电性连接在所述节点与所述输出端之间。
  2. 如权利要求1所述的漏电补偿动态寄存器，其特征在于：所述漏电补偿单元具有一第一端、一第二端以及一控制端，所述第一端电性连接至所述输出端，所述第二端电性连接至所述节点。
  3. 如权利要求2所述的漏电补偿动态寄存器，其特征在于：所述漏电补偿单元包括一PMOS晶体管及一NMOS晶体管，所述PMOS晶体管及所述NMOS晶体管串联连接在所述输出端与所述节点之间。
  4. 如权利要求3所述的漏电补偿动态寄存器，其特征在于：所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的所述源极端电性连接至所述输出端，所述漏极端电性连接至所述NMOS晶体管的所述漏极端，所述NMOS晶体管的所述源极端电性连接至所述节点。
  5. 如权利要求4所述的漏电补偿动态寄存器，其特征在于：所述PMOS晶体管与所述NMOS晶体管的栅极端并联并电性连接至一电源。
  6. 如权利要求4所述的漏电补偿动态寄存器，其特征在于：所述PMOS晶体管与所述NMOS晶体管的栅极端并联并电性连接至所述节点。
  7. 如权利要求3所述的漏电补偿动态寄存器，其特征在于：所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的所述源极端电性连接至所述输出端，所述漏极端电性连接至所述PMOS晶体管的所述漏极端，所述PMOS晶体管的所述源极端电性连接至所述节点。
  8. 如权利要求7所述的漏电补偿动态寄存器，其特征在于：所述PMOS晶体管与所述NMOS晶体管的栅极端并联并电性连接至一地。
  9. 如权利要求7所述的漏电补偿动态寄存器，其特征在于：所述PMOS晶体管与所述NMOS晶体管的栅极端并联并电性连接至所述节点。
  10. 如权利要求2所述的漏电补偿动态寄存器，其特征在于：所述漏电补偿单元包括一PMOS晶体管，所述PMOS晶体管具有一源极端、一漏极端及一栅极端，所述PMOS晶体管的所述源极端电性连接至所述输出端，所述漏极端电性连接至所述节点，所述栅极端电性连接至一电源。
  11. 如权利要求2所述的漏电补偿动态寄存器，其特征在于：所述漏电补偿单元包括一NMOS晶体管，所述NMOS晶体管具有一源极端、一漏极端及一栅极端，所述NMOS晶体管的所述漏极端电性连接至所述输出端，所述源极端电性连接至所述节点，所述栅极端电性连接至一地。
  12. 如权利要求1所述的漏电补偿动态寄存器，其特征在于：所述时钟信号包括一第一时钟信号及一第二时钟信号，所述第一时钟信号与所述第二时钟信号反相。
  13. 如权利要求1所述的漏电补偿动态寄存器，其特征在于：所述模拟开关单元为传输门。
  14. 如权利要求1所述的漏电补偿动态寄存器，其特征在于：所述数据锁存单元为三态反相器。
  15. 如权利要求1所述的漏电补偿动态寄存器，其特征在于：所述输出驱动单元为反相器。
  16. 一种数据运算单元，包括互联连接的控制电路、运算电路、多个漏电补偿动态寄存器，所述多个漏电补偿动态寄存器为串联和/或并联连接；其特征在于：所述多个漏电补偿动态寄存器为权利要求1-15中任意一种所述的漏电补偿动态寄存器。
  17. 一种芯片，其特征在于，包括至少一个如权利要求16所述的数据运算单元。
  18. 一种用于计算设备的算力板，其特征在于，包括至少一个如权利要求17所述的芯片。
  19. 一种计算设备，包括电源板、控制板、连接板、散热器以及多个算力板，所述控制板通过所述连接板与所述算力板连接，所述散热器设置在所述算力板的周围，所述电源板用于向所述连接板、所述控制板、所述散热器以及所述算力板提供电源，其特征在于：所述算力板为如权利要求18所述的算力板。
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