WO2021081765A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2021081765A1
WO2021081765A1 PCT/CN2019/114061 CN2019114061W WO2021081765A1 WO 2021081765 A1 WO2021081765 A1 WO 2021081765A1 CN 2019114061 W CN2019114061 W CN 2019114061W WO 2021081765 A1 WO2021081765 A1 WO 2021081765A1
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WIPO (PCT)
Prior art keywords
layer
area
insulating
bonding
base substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2019/114061
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English (en)
French (fr)
Inventor
马宏伟
董向丹
汪锐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201980002170.4A priority Critical patent/CN113056827B/zh
Priority to PCT/CN2019/114061 priority patent/WO2021081765A1/zh
Priority to US16/975,521 priority patent/US12004387B2/en
Priority to CN202410660695.XA priority patent/CN118488767A/zh
Priority to EP19945410.9A priority patent/EP4053901B1/en
Publication of WO2021081765A1 publication Critical patent/WO2021081765A1/zh
Anticipated expiration legal-status Critical
Priority to US18/645,581 priority patent/US12477911B2/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/82—Interconnections, e.g. terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness

Definitions

  • the embodiments of the present disclosure relate to a display substrate, a preparation method thereof, and a display device.
  • OLED Organic Light-Emitting Diode
  • touch OLED display devices consumers have higher and higher requirements for display-based touch experience.
  • the frame of the display device is gradually reduced, the screen-to-body ratio is gradually increased, and the thickness is gradually reduced.
  • At least one embodiment of the present disclosure provides a display substrate, including a base substrate, a lead, a plurality of contact pads, a first insulating laminated layer, and a second insulating laminated layer.
  • the base substrate includes a display area and a cofferdam area at least partially surrounding the display area, the cofferdam area is far from the transition area on the side of the display area, and the transition area is far from the first cofferdam area on the side of the cofferdam area.
  • a bonding area and a bonding peripheral area is located between the first bonding area and the transition area; the leads are located in the first bonding area; and a plurality of contact pads are located in the The first bonding area is configured to be electrically connected to the lead; a first insulating laminate layer is located in the first bonding area; a second insulating laminate layer is located in the bonding peripheral area, and the second At least two insulating layers of the insulating laminated layer extend into the first bonding region to obtain the first insulating laminated layer, wherein the first insulating laminated layer is in a direction perpendicular to the base substrate The thickness is smaller than the thickness of the second insulating laminate layer in a direction perpendicular to the base substrate.
  • the plurality of contact pads includes a plurality of first contact pads and a plurality of second contact pads, wherein the plurality of first contact pads are arranged in at least one row, so The first contact pad and the second contact pad include a conductive pattern stack.
  • a third insulating laminate layer is located in the transition area, and the third insulating laminate layer includes a first insulating laminate sublayer and a second insulating laminate sublayer, so The orthographic projection of the first insulating laminated layer sublayer on the base substrate at least partially covers the transition area and the bonding peripheral area, and the second insulating laminated layer sublayer is on the base substrate The orthographic projection at least partially covers the transition area and the bonding peripheral area.
  • the third insulating laminated layer further includes a third insulating laminated layer sublayer, which is disposed on the first insulating laminated layer sublayer and the second insulating laminated layer Between the sub-layers, wherein the orthographic projection of the third insulating laminated layer sub-layer on the base substrate does not overlap with the first bonding area and the bonding peripheral area.
  • the at least two insulating layers include a first insulating layer and a second insulating layer, the first insulating layer is located on the base substrate, and the second insulating layer The insulating layer is located on the side of the first insulating layer away from the base substrate, wherein the first insulating laminate layer sublayer extends to the bonding peripheral area to obtain the first insulating layer, The two insulating laminated layer sublayers extend to the bonding peripheral area to obtain the second insulating layer.
  • the display substrate provided by at least one embodiment of the present disclosure further includes a pixel structure located in the display area, wherein the pixel structure includes a pixel drive circuit, a first planarization layer, a first transfer electrode, and a second planarization layer.
  • the pixel driving circuit includes a thin film transistor, the thin film transistor includes a gate electrode, a source and drain electrode, and an interlayer insulating layer, and the interlayer insulating layer is located on the gate electrode away from the base substrate.
  • the first planarization layer is provided on the side of the pixel driving circuit away from the base substrate to provide a first planarized surface and includes a first planarization surface.
  • the first transfer electrode is on the first planarized surface and is electrically connected to one of the source and drain electrodes of the thin film transistor through the first via hole
  • the second planarization layer A second planarized surface is provided on the side of the first transfer electrode away from the base substrate and includes a second via hole
  • the light-emitting element is on the second planarized surface and passes through the second
  • the via hole is electrically connected to the first transfer electrode, wherein the interlayer insulating layer and the first insulating layer are provided in the same layer, and the second planarization layer and the second insulating layer are provided in the same layer,
  • the first planarization layer and the third insulating laminated layer sublayer are arranged in the same layer.
  • the thickness of the second planarization layer in the direction perpendicular to the base substrate is in the transition region with the third insulating laminated layer sublayer, and the second insulating layer is in the transition region.
  • the thickness of the bonding peripheral area along the direction perpendicular to the base substrate is substantially equal.
  • the height of the second insulating layer in the first bonding region is smaller than that of the second insulating layer in the bonding region.
  • the height of the surrounding area is smaller than that of the second insulating layer in the bonding region.
  • the thickness of the second insulating layer in the bonding peripheral area along the direction perpendicular to the base substrate and the second insulating laminated layer sublayer in the transition area is substantially equal.
  • the first insulating layer and the second insulating layer extend into the first bonding region to obtain the first insulating laminated layer.
  • the at least two insulating layers further include a third insulating layer, and the third insulating layer is located on a side of the second insulating layer away from the base substrate.
  • the side is configured to expose the second insulating layer on a side close to the plurality of contact pads.
  • the display area includes a signal line for electrical connection with the lead.
  • the conductive pattern stack includes at least two conductive patterns, wherein at least one insulating layer of the first insulating stack covers one of the at least two conductive patterns. The edge of one and the edge of the at least one insulating layer is covered by the other of the at least two conductive patterns.
  • the conductive pattern stack includes a first conductive pattern and a second conductive pattern, wherein the first conductive pattern is located on the lead away from the base substrate.
  • the second conductive pattern is located on the side of the first conductive pattern away from the base substrate and covers the edge of the first conductive pattern, wherein the first insulating The second insulating layer in the laminated layer covers the edge of the second conductive pattern.
  • the first insulating layer in the first insulating laminated layer is located between the first conductive pattern and the lead, and the first conductive pattern is connected to
  • the first insulating layer between the leads has a first conductive pattern via; the first conductive pattern and the lead are electrically connected through the first conductive pattern via.
  • the pixel structure further includes a first display area metal layer, wherein the first conductive pattern and the first display area metal layer are provided in the same layer;
  • the second conductive pattern is arranged in the same layer as the first transfer electrode.
  • the source and drain electrodes of the thin film transistor are located in the metal layer of the first display area.
  • the base substrate further includes a second bonding area, and the second bonding area is located on a side of the first bonding area away from the display area ,
  • the first insulating layer extends to the second bonding area
  • the display substrate further includes a plurality of third contact pads and second bonding area leads, and the plurality of third contact pads are located in the second bonding area.
  • the bonding area is arranged on the side of the first insulating layer away from the base substrate
  • the third contact pad includes a plurality of contact pad metal layers
  • the second bonding area leads are located in the first bonding layer. Between the area and the second bonding area, and is configured to connect the second contact pad and the third contact pad.
  • the plurality of contact pad metal layers includes a first contact pad metal layer and a second contact pad metal layer, and the first contact pad metal layer is disposed on the first insulating pad.
  • the second contact pad metal layer is laminated with the first contact pad metal layer and covers the periphery of the second contact pad metal layer, wherein the first contact pad The metal layer and the first conductive pattern layer are arranged in the same layer, and the second contact pad metal layer and the second conductive pattern layer are arranged in the same layer.
  • the second contact pad metal layer extends to the first bonding area to form the second bonding area lead, wherein the second insulating layer extends to The second bonding area covers the leads of the second bonding area and the edges of the second contact pad metal layer.
  • the portion of the second insulating layer located between the first bonding area and the second bonding area is in a direction perpendicular to the base substrate.
  • the thickness is substantially the same as the thickness of the portion of the second insulating layer located in the first bonding area in the direction perpendicular to the base substrate, and the second insulating layer located in the first bonding area is the second
  • the orthographic projection of the part between the bonding regions on the base substrate and the orthographic projection of the second bonding region lead on the base substrate at least partially overlap.
  • the conductive pattern stack further includes a third conductive pattern, and the third conductive pattern is located on a side of the second conductive pattern away from the base substrate, The edge of the second insulating layer in the first insulating laminated layer is covered by the third conductive pattern.
  • the plurality of contact pad metal layers further includes a third contact pad metal layer, and the third contact pad metal layer is located on the second contact pad metal layer away from the liner.
  • One side of the base substrate covers the edge of the second insulating layer in the second bonding area, wherein the third contact pad metal layer and the third conductive pattern layer are provided in the same layer.
  • the display substrate provided by at least one embodiment of the present disclosure further includes an encapsulation layer, an auxiliary electrode, and a display area protection layer, the encapsulation layer is located at least in the display area, and the encapsulation layer includes at least one encapsulation sublayer, so The auxiliary electrode and the display area protection layer are located in the display area, the auxiliary electrode is arranged on the side of the encapsulation layer away from the base substrate, and the display area protection layer is arranged on the auxiliary electrode away from the base substrate One side of the display area, wherein the third conductive pattern and the auxiliary electrode are provided in the same layer, and the third insulating layer and the display area protection layer are provided in the same layer.
  • the pixel structure further includes a storage capacitor.
  • the storage capacitor includes a first storage capacitor electrode and a second storage capacitor electrode.
  • One of the storage capacitor electrode and the second storage capacitor electrode are arranged in the same layer.
  • the first bonding area includes a bonding border area, and the bonding border area is located between the first bonding area and the surrounding bonding area ,
  • the bonding boundary area further includes a marking metal layer located between the first insulating layer and the second insulating layer, wherein the marking metal layer is connected to the first conductive pattern and the second conductive One of the patterns is set on the same layer.
  • At least one embodiment of the present disclosure provides a display device including the display substrate as described in any one of the above.
  • At least one embodiment of the present disclosure provides a method for preparing a display substrate, including: providing a base substrate, which includes a display area and a dam area at least partially surrounding the display area, the dam area being far away from the display area One side of the transition zone, the transition zone is far from the first bonding zone on the side of the cofferdam area and the bonding surrounding zone, the bonding periphery zone is located between the first bonding zone and the transition zone Between; forming leads in the first bonding area; forming a plurality of contact pads in the first bonding area, wherein the contact pads are formed to be electrically connected to the leads; in the first A first insulating laminate layer is formed in the bonding area; a second insulating laminate layer is formed in the bonding peripheral area so that at least two insulating layers of the second insulating laminate layer extend into the first bonding area In order to obtain the first insulating laminated layer, the thickness of the first insulating laminated layer in the direction perpendicular to the base substrate is smaller than that of the
  • forming the second insulating laminated layer includes: forming a first insulating layer of the second insulating laminated layer on the base substrate, and forming a first insulating layer located on the base substrate.
  • the second insulating layer of the second insulating laminate layer on the side of the first insulating layer away from the base substrate, wherein the first insulating layer and the second insulating layer extend to the first insulating layer
  • the first insulating layer stack is formed in a bonding area.
  • the manufacturing method provided in at least one embodiment of the present disclosure further includes: forming a pixel structure in the display area, wherein the pixel structure includes a pixel driving circuit, a first planarization layer, a first switching electrode,
  • the second planarization layer and the light-emitting element forming a pixel structure in the display area includes: forming the pixel driving circuit on the base substrate, wherein a thin film transistor is formed in the pixel driving circuit, and A gate, source and drain electrodes, and an interlayer insulating layer are formed in the thin film transistor, and the interlayer insulating layer is located on the side of the gate away from the base substrate and on the side of the source and drain electrodes close to the base substrate , Forming the first planarization layer on the side of the pixel driving circuit away from the base substrate to provide a first planarization surface, and forming a first via hole in the first planarization layer, and A first transfer electrode is formed on the first planarized surface, and the first transfer electrode is electrically connected to one of
  • the second planarization layer is formed on one side of the base substrate to provide a second planarized surface, and a second via is formed in the second planarized surface, and the second planarized surface is formed on the second planarized surface.
  • the light-emitting element, and the light-emitting element is electrically connected to the first switching electrode through the second via hole.
  • forming the second insulating layer includes: after forming the second conductive pattern of the conductive pattern stack and the pixel driving circuit, on a base substrate Depositing a first insulating material layer; performing a patterning process on the first insulating material layer so that the portion of the first insulating material layer located in the display area is formed as a second planarization layer, and the second planarization layer
  • the second via hole is formed in the layer, the portion of the first insulating material layer overlapping with the second conductive pattern is removed, and the portion of the first insulating material layer located in the first bonding region is thinned to
  • the second insulating layer is formed so that the height of the second insulating layer in the first bonding area relative to the base substrate is smaller than the height in the bonding peripheral area, and covers the second The edge of the conductive pattern.
  • the patterning process on the first insulating material layer includes: patterning the first insulating material layer using a gray tone mask or a halftone mask patterning process .
  • FIG. 1A is a plan view of a display substrate provided by an embodiment of the disclosure.
  • 1B is a plan view of a first bonding area of a display substrate provided by an embodiment of the disclosure.
  • 1C is a plan view of a transition area of a display substrate provided by an embodiment of the disclosure.
  • FIG. 2A is a schematic cross-sectional view of the display substrate shown in FIG. 1B along M2-N2;
  • 2B is a schematic cross-sectional view of the display substrate shown in FIG. 1A along M1-N1;
  • 2C is a schematic cross-sectional view of the display substrate provided by an embodiment of the disclosure along C1-D1 in the transition area shown in FIG. 1C;
  • FIG. 3 is a schematic cross-sectional view of the display area of the display substrate shown in FIG. 1A;
  • FIG. 4A is a plan view of another display substrate provided by an embodiment of the disclosure.
  • 4B is a plan view of another first bonding area of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 5A is a schematic cross-sectional view of the display substrate shown in FIG. 1B along M4-N4;
  • 5B is a schematic cross-sectional view of the display substrate shown in FIG. 1A along M3-N3;
  • FIG. 6 is a schematic cross-sectional view of the display area of the display substrate shown in FIG. 4A;
  • FIG. 7 is a schematic cross-sectional view of a display area of another display substrate provided by another embodiment of the present disclosure.
  • 8A to 8K are process diagrams of a method for manufacturing a display substrate provided by some embodiments of the present disclosure.
  • Display devices that use flexible display on-cell touch technology (Felxible Multi Layer On Cell Touch, FMLOC) can directly integrate The touch sensor is fabricated on the display substrate by traditional deposition, coating, exposure, and etching processes to obtain a thinner display device.
  • the method of adding a transfer electrode layer in the display substrate is adopted to reduce the resistance of the wiring, thereby improving the unevenness of the display.
  • the external circuit may include a flexible circuit board (for example, Chip On Film, COF for short) on which a chip is mounted, and a control chip or a driving chip is provided on the flexible circuit board. Wait.
  • the increase in the number of film layers will lead to an increase in the film level difference in the boundary zone of the bonding zone, and more bubbles are prone to appear in the bonding process at the film level difference in the boundary zone. These bubbles will directly affect the bonding effect of the bonding area. In severe cases, it may cause the mark to be unrecognized during the bonding process, thereby failing to bond the external circuit to the bonding area, reducing the product yield.
  • At least one embodiment of the present disclosure provides a display substrate, a preparation method thereof, and a display device.
  • the display substrate provided by at least one embodiment of the present disclosure includes a base substrate, a lead, a plurality of contact pads, a first insulating laminated layer and a second insulating laminated layer.
  • the base substrate includes a display area and a cofferdam area at least partially surrounding the display area, a transition area on the side of the cofferdam area away from the display area, a first bonding area on the side away from the cofferdam area and a surrounding area of the bonding area.
  • the fixed peripheral area is located between the first bonding area and the transition area; the lead is located in the first bonding area; a plurality of contact pads are located in the first bonding area and are configured to be electrically connected to the lead; the first insulating stack
  • the second insulating layer is located in the peripheral area of the bonding, and at least two insulating layers of the second insulating layer are extended into the first bonding area to obtain the first insulating layer, wherein, The thickness of the first insulating laminated layer in the direction perpendicular to the base substrate is smaller than the thickness of the second insulating laminated layer in the direction perpendicular to the base substrate.
  • the first insulating laminate layer is provided in the bonding boundary area, and the height of the first insulating laminate layer opposite to the base substrate is smaller than the height of the second insulating laminate layer located in the bonding peripheral area opposite to the base substrate.
  • the height thereby reducing the height of the film level difference in the surrounding area of the bonding, to reduce the risk of generating bubbles in the surrounding area of the bonding and the boundary area of the bonding, which is more helpful to complete the bonding process and improve the product yield of the display substrate. And reliability.
  • a spatial rectangular coordinate system is established based on the base substrate of the display substrate, and the position of each structure in the display substrate is described based on this.
  • the X axis and the Y axis are parallel to the plane where the base substrate is located, and the Z axis is perpendicular to the plane where the base substrate is located.
  • FIG. 1A is a plan view of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 1B is a plan view of a first bonding area of a display substrate provided by an embodiment of the disclosure.
  • the display substrate is used in, for example, an organic light emitting diode (OLED) display device or a quantum dot light emitting diode (QLED) display device.
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • the display area 1100 includes a plurality of sub-pixels and a plurality of signal lines 1101, and the plurality of signal lines 1101 includes signal lines (such as gates) extending in a first direction (the X-axis direction in the figure).
  • Line G and signal lines extending along the second direction (the Y-axis direction in the figure) (for example, data line D.
  • These signal lines extend or route to the first bonding area located at least one side of the display area 1100, for example, the signal
  • the line 1101 is electrically connected to the corresponding lead, and thus can be electrically connected to the driving chip, flexible circuit board, etc. bonded in the first bonding area.
  • the signal line 1101 can provide scanning of control signals, data signals, voltage signals, etc. for the pixel array Line (gate line), data line, power line, detection line, etc.
  • the display substrate 100 includes a base substrate, the base substrate includes a display area 1100 and a display peripheral area 1200 surrounding the display area 1100, and the display peripheral area 1200 includes a dam area 1102 and a transition area. 1103, the cofferdam area 1102 surrounds the display area, and the transition area 1103 is located on the side of the display area 1100.
  • the cofferdam area 1102 includes a barrier dam, and the barrier dam may be formed as a one-layer or multi-layer structure.
  • the base substrate further includes a first bonding area 1300 and a bonding peripheral area 1500 located on one side of the display area 1100.
  • the first bonding area 1300 includes the bonding border area 1400.
  • the Bonding Border Area 1400 is located between the First Bonding Area 1300 and the Bonding Peripheral Area 1500.
  • the first bonding area 1300 may use COP (Chip on Pi) technology to bond integrated circuit chips to a flexible substrate (such as a Pi substrate) of a display substrate.
  • the display peripheral area 1200 further includes a second bonding area located on the side of the first bonding area 1300 away from the display area 1100.
  • the second bonding area may be an area where a FOP (Flexible Printed Circuit (FPC) On Pi) double-sided bonding process is used.
  • FOP Flexible Printed Circuit
  • the display substrate 100 may further include a plurality of leads 1210 and a plurality of contact pads 1310, and the plurality of contact pads 1310 are arranged in the first bonding region 1300.
  • the plurality of contact pads 1310 includes a plurality of first contact pads 1311 and a plurality of second contact pads 1312.
  • the plurality of first contact pads 1311 are located on the side of the first bonding area 1300 close to the display area, and the plurality of second contact pads 1312 are located on the side of the first bonding area 1300 away from the display area.
  • the plurality of second contact pads 1312 are arranged in at least one row (one row is shown), and the plurality of first contact pads 1311 are arranged in at least one row (one row is shown).
  • the direction of the row is the direction in which the first bonding area 1300 faces the display area 1100.
  • the plurality of first contact pads 1311 and the plurality of second contact pads 1312 may also be arranged in multiple rows, and the embodiment of the present disclosure is not limited thereto.
  • the multiple leads 1210 are electrically connected to the multiple contact pads 1310 in a one-to-one correspondence.
  • One end of the lead 1210 extends to the display area 1100 to be electrically connected to a corresponding signal line (such as a data line) in the display area 1100, and the other end of the lead 1210 extends to the first bonding area 1300 to be electrically connected to the contact pad 1310.
  • the leads 1210 are provided in the same layer as the signal lines in the display area 1100, and thus can be formed integrally or in different layers, and thus need to be electrically connected to each other through the via holes in the interlayer insulating layer between the two.
  • the first contact pad 1311 and the second contact pad 1312 are configured to transmit signals in the external circuit, such as display signals, to the leads of the display area.
  • the display substrate 100 further includes a plurality of second bonding area leads 1620 and a plurality of third contact pads 1610.
  • the plurality of second bonding area leads 1620 are electrically connected to the plurality of third contact pads 1620, for example, they may be electrically connected in a one-to-one correspondence, or a plurality of contact pads may be electrically connected to a lead, such as a plurality of third contact pads 1620 and One second bonding zone lead 1620 is electrically connected, which is not limited in this embodiment.
  • One end of the second bonding area lead 1620 extends to the first bonding area 1300 to be electrically connected to the second contact pad 1312, and the other end of the second bonding area lead 1620 extends to the second bonding area 1600 and the third contact The pad 1610 is electrically connected.
  • the third contact pad 1620 is configured to transmit a signal from an external circuit, such as a display signal, to the second contact pad in the first bonding area, and then the second contact pad transmits the signal to Leads to the display area.
  • an external circuit such as a display signal
  • the transition zone 1103 includes a first fan-out zone 1104, a bending zone 1105, and a second fan-out zone 1106.
  • the first fan-out area 1104 is located at the side of the transition area 1103 close to the display area 1100
  • the second fan-out area 1106 is located at the side of the transition area 1103 close to the first bonding area 1300
  • the bending area is located at the first fan-out area 1105 and Between the second fan-out area 1106.
  • the section line M1-N1 in FIG. 1A passes through the first contact pad 1311 in the first bonding area 1300, the second contact pad 1312, and the third contact pad 1610 in the second bonding area 1600 to show the first The film layer change relationship between the bonding area 1300 and the second bonding area 1600.
  • the contact pad 1310 includes a conductive pattern stack 13110.
  • the section line M2-N2 passes through the second contact pad 1312 located in the L1 row close to the bonding boundary area 1400, and passes through the bonding boundary area 1400 and the bonding peripheral area 1500 to show the first state.
  • the relationship between the film layer changes in the fixed area 1300, the bonded boundary area 1400, and the bonded peripheral area 1500.
  • the film layer change at the cross-section line M2-N2 in the first bonding area 1300 is the same as the film layer change at the symmetrical position.
  • the situation shown in FIG. 1B is taken as an example for illustration. .
  • the display substrate 100 further includes a first insulating laminated layer 1320 and a second insulating laminated layer 1330.
  • the first insulating laminate layer 1320 is located in the bonding boundary area 1400, and the second insulating laminate layer 1330 is located in the bonding peripheral area 1500.
  • the insulating layer on the top layer of the first insulating laminated layer 1320 extends to the first bonding area 1300 and covers the edges of the plurality of contact pads 1310.
  • the lead 1210 connecting the second contact pad 1312 extends through the gap of the first contact pad 1311 in the first bonding area 1300, and then extends to the display area 1100, so that the contact pad 1310 has a larger size.
  • the multiple leads 1210 may also be located in different layers.
  • the lead 1210 used to connect the second contact pad 1312 is located at a layer closer to the base substrate
  • the lead 1210 used to connect the first contact pad 1311 is located in a layer closer to the base substrate. It is located at a layer relatively farther away from the base substrate 1000 (but still between the contact pad and the base substrate). Therefore, the spacing between the multiple leads 1210 in the same layer can be increased, which reduces the risk of interference and short circuit between the leads, which is beneficial to forming a display device with high pixel resolution.
  • multiple leads 1210 in the same layer can be prepared in the same patterning process; multiple leads 1210 in different layers can be prepared in different patterning processes.
  • the material of the lead 1210 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, and titanium.
  • FIG. 2A is a schematic cross-sectional view of the display substrate shown in FIG. 1B along M2-N2.
  • the contact pad 1310 is located on the side of the lead 1210 away from the base substrate 1000.
  • At least two insulating layers of the second insulating laminated layer 1330 extend into the bonding boundary region 1400 to obtain the first insulating laminated layer 1320.
  • the height C3 of the first insulating laminated layer 1320 relative to the base substrate 1000 is smaller than the height C1 of the second insulating laminated layer 1330 relative to the base substrate 1000.
  • the height of the film level difference in the surrounding area of the bonding is reduced, so as to reduce the risk of generating bubbles in the surrounding area of the bonding and the bonding boundary area, and improve the product yield and reliability of the display substrate.
  • the base substrate 1000 may be a glass plate, a quartz plate, a metal plate, or a resin-based plate.
  • the material of the base substrate may include an organic material.
  • the organic material may be polyimide (Pi), polycarbonate, polyacrylate, polyetherimide, polyethersulfone, and polyethylene terephthalate.
  • resin materials such as glycol ester and polyethylene naphthalate
  • the base substrate 1000 may be a flexible substrate or a non-flexible substrate, which is not limited in the embodiments of the present disclosure.
  • the second insulating laminate layer 1330 includes a first insulating layer 1331 and a second insulating layer 1332 in the bonding peripheral region 1500.
  • the first insulating layer 1331 is located on the base substrate 1000, and the second insulating layer 1332 is located on the side of the first insulating layer 1331 away from the base substrate 1000.
  • the first insulating layer 1331 and the second insulating layer 1332 extend into the bonding boundary region 1400 to obtain the first insulating layer stack 1320.
  • the height C3 of the second insulating layer 1332 in the bonding boundary region 1400 is smaller than the height C2 of the second insulating layer 1332 in the bonding peripheral region 1500, that is, in the bonding boundary region 1400 and in the bonding boundary region 1400.
  • the second insulating layer 1332 is integrated, but has different heights.
  • the parts with different heights can be continuously transitioned, for example, have a slope angle relative to the base substrate.
  • the slope angle is, for example, about 40 degrees to 60 degrees, and for example, about 50 degrees.
  • the height of the second insulating layer 1332 refers to the vertical distance from the surface of the second insulating layer 1332 to the surface of the base substrate 1000.
  • the film thickness of the second insulating layer 1332 in the bonding boundary region 1400 may be about 1.0 ⁇ m to 1.4 ⁇ m
  • the value of the vertical distance may be about 1.2 microns.
  • the film thickness of the second insulating layer 1332 in the bonding peripheral region 1500 may range from about 1.8 ⁇ m to 2.2 ⁇ m, for example, the film thickness may be about 2 ⁇ m.
  • the value range of the height difference H1 between the height C2 of the second insulating layer 1332 in the bonding peripheral region 1500 and the height of the second insulating layer 1332 in the bonding boundary region 1400 may be about 0.4 micrometers to 1.2 micrometers, for example ,
  • the height difference can be about 0.8 microns.
  • the height difference of the film layer in the bonding boundary area in the surrounding area of the bonding that is, the film level difference is reduced, to reduce the risk of air bubbles in the surrounding area of the bonding and the bonding boundary area, and to improve the product yield of the display substrate and reliability.
  • the word "about” indicates the range of variation of a given value, which is within ⁇ 15% of the value, such as ⁇ 5%, ⁇ 10%, etc.
  • the material of the first insulating layer 1331 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or the like, or may include polyimide (Pi), polyphthalimide, polyphthalamide, acrylic resin, and benzene. And organic insulating materials such as cyclobutene or phenolic resin.
  • inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or the like, or may include polyimide (Pi), polyphthalimide, polyphthalamide, acrylic resin, and benzene.
  • organic insulating materials such as cyclobutene or phenolic resin.
  • the embodiment of the present disclosure does not specifically limit the material of the first insulating layer.
  • the material of the second insulating layer 1332 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or the like, or may include polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or Organic insulating materials such as phenolic resin.
  • the embodiment of the present disclosure does not specifically limit the material of the second insulating layer.
  • At least two insulating layers of the second insulating laminated layer 1330 further include a third insulating layer 1333.
  • the third insulating layer 1333 is located on the side of the second insulating layer 1332 away from the base substrate 1000 and is configured to expose the second insulating layer 1332 on the side close to the contact pad 1310.
  • the side of the third insulating layer 1333 close to the bonding boundary area 1320 has a slope angle side, and this side is different from the side of the second insulating layer 1332 at the bonding peripheral area 1330 close to the bonding boundary area 1320. The sides of the slope angle are not aligned.
  • the distance between the side edge of the third insulating layer 1333 and the bonding boundary area 1320 is greater than the distance between the side edge of the second insulating layer 1332 and the bonding boundary area 1320.
  • the greater the distance between the third insulating layer and the bonding boundary area the more conducive to reducing the risk of bubbles in the bonding boundary area during the bonding process.
  • the third insulating layer 1333 can also protect the surrounding lines. effect.
  • the film thickness of the third insulating layer 1333 may be about 3 microns.
  • the height difference H1 between the height C2 of the second insulating layer 1332 in the bonding peripheral area 1500 and the height of the second insulating layer 1332 in the bonding boundary area 1400 plus the thickness of the third insulating layer 1333 is the distance from the second insulating layer 1330
  • the difference h1 between the height C1 of the base substrate 1000 and the height C3 of the first insulating laminated layer 1320 from the base substrate 1000, the value range of the difference h1, for example, may be about 3.4 to 4.2 microns.
  • the difference can be about 3.8 microns.
  • the distance d1 obtained by the projection of the above-mentioned difference h1 on the base substrate is approximately between 100 micrometers and 200 micrometers.
  • the material of the third insulating layer 1333 may include an organic insulating material.
  • the organic insulating material may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as polymer resin.
  • the display substrate 100 further includes a bonding region buffer layer 1341 located above the base substrate 100 and a bonding region gate insulating layer 1342 located on the side of the bonding region buffer layer 1341 away from the base substrate 1000.
  • the lead 1210 is located on the gate insulating layer 1342 in the bonding area. One end of the lead 1210 is electrically connected to the contact pad 1311.
  • the first insulating layer 1331 extends to the first bonding area between the contact pad 1311 and the lead 1210.
  • the conductive pattern stack of the contact pad includes at least two conductive patterns, at least one insulating layer of the first insulating stack covers the edge of one of the at least two conductive patterns, and the edge of the at least one insulating layer is in the at least two conductive patterns. Covered by the other.
  • the conductive pattern stack 13110 includes a first conductive pattern 13111 and a second conductive pattern 13112.
  • the first conductive pattern 13111 is located on a side of the lead 1210 away from the base substrate 1000 and is electrically connected to the lead 1210.
  • the second conductive pattern 13112 is located on a side of the first conductive pattern 13111 away from the base substrate 1000 and covers the edge of the first conductive pattern 13111 to prevent the first conductive pattern 13111 from being corroded by the etching solution.
  • the first insulating layer 1331 is located between the first conductive pattern 13111 and the lead 1210 such that the first conductive pattern 13111 and the lead 1210 are electrically insulated.
  • a first conductive pattern via 13114 is formed in the first insulating layer 1331.
  • the first conductive pattern 13111 and the lead 1331 are electrically connected through the first conductive pattern via 13114.
  • the second insulating layer 1332 in the first insulating laminated layer 1320 extends to the first bonding area to cover the edge of the second conductive pattern 13112 to prevent the second conductive pattern 13112 from being corroded.
  • the second conductive pattern 13112 is configured to expose the first insulating laminated layer 1320 for electrical connection with an external circuit.
  • the material of the first conductive pattern 13111 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, and the like.
  • the material of the second conductive pattern 13112 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, and titanium.
  • the conductive pattern stack 13110 further includes a third conductive pattern 13113.
  • the third conductive pattern 13113 is located on a side of the second conductive pattern 13112 away from the base substrate 1000 and covers the edge of the second insulating layer 1332 in the first insulating laminated layer 1320.
  • the edge of the second insulating layer refers to the edge where the second insulating layer 1332 is broken on the second conductive pattern 13112.
  • the material of the third conductive pattern 13113 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, and titanium.
  • the bonding boundary area 1400 further includes a marking metal layer 1350 located between the first insulating layer 1331 and the second insulating layer 1332, which is used for the external circuit during the bonding process. Counterpoint.
  • the marking metal layer may be provided in the same layer as the first conductive pattern 13111 or the second conductive pattern 13112.
  • the embodiment of the present disclosure has no limitation on the plane pattern of the marking metal layer, for example, it may be a cross, a square, a rectangle, and the like.
  • the third contact pad located in the second bonding area includes a plurality of contact pad metal layers, and the plurality of contact pad metal layers includes a first contact pad metal layer and a second contact pad metal layer,
  • the first contact pad metal layer is arranged on the side of the first insulating layer away from the base substrate, the second contact pad metal layer is laminated with the first contact pad metal layer and covers the periphery of the second contact pad metal layer, wherein the first contact The pad metal layer and the first conductive pattern layer are arranged in the same layer, and the second contact pad metal layer and the second conductive pattern layer are arranged in the same layer.
  • the second contact pad metal layer extends to the first bonding area to form a second bonding area lead, and the second insulating layer extends to the second bonding area and covers the second bonding area. Zone leads and the edges of the second contact pad metal layer.
  • the thickness of the portion of the second insulating layer located between the first bonding area and the second bonding area in the direction perpendicular to the base substrate is equal to the thickness of the second insulating layer located in the first bonding area.
  • the part of the substrate of the second insulating layer is opposite to each other, and the orthographic projection of the part of the second insulating layer between the first bonding area and the second bonding area on the base substrate and the orthographic projection of the leads of the second bonding area on the base substrate are at least Partially overlapped.
  • the plurality of contact pad metal layers further includes a third contact pad metal layer, and the third contact pad metal layer is located on the side of the second contact pad metal layer away from the base substrate and covers the second contact pad metal layer. At the edge of the second insulating layer in the bonding area, the third contact pad metal layer and the third conductive pattern layer are arranged in the same layer.
  • FIG. 2B is a schematic cross-sectional view of the display substrate shown in FIG. 1A along M1-N1.
  • the bonding region buffer layer 1341 and the bonding region gate insulating layer 1342 further extend to the second bonding region 1600.
  • the lead 1210 connected to the first contact pad 1311 further extends to the bonding boundary area 1500.
  • the film stack at the bonding boundary region 1500 includes a lead 1210, a first insulating layer 1331, a second insulating layer 1332, and a third insulating layer 1333.
  • the thickness of the second insulating layer 1332 in the bonding peripheral area is greater than that in the first bonding area, and the difference in thickness is approximately the same as the value of H1 shown in FIG. 2A.
  • the third contact pad 1610 includes a first contact pad metal layer 1611, a second contact pad metal layer 1612, and a third contact pad metal layer 1613.
  • the first contact pad metal layer 1611 is located on the gate insulating layer 1342 in the bonding area.
  • the first contact pad metal layer 1611 and the first conductive pattern 13111 are provided in the same layer. Therefore, the first contact pad metal layer 1611 and the first conductive pattern 13111 can be used The same patterning process is prepared to simplify the process flow.
  • the second contact pad metal layer 1612 is located on the side of the first contact pad metal layer 1611 away from the base substrate, and covers the edge of the first contact pad metal layer 1611 to prevent the first contact pad metal layer 1611 from being corroded by the etching solution .
  • the second bonding area lead 1620 is covered between the edge of the first contact metal layer 1611 on the side of the first bonding area 1300 and the edge of the second conductive pattern 13112 on the side of the second bonding area 1600.
  • the second contact pad metal layer 1612 extends toward the first bonding area 1300 to form a second bonding area lead 1620.
  • the second insulating layer 1332 extends to the second bonding area 1600 and covers the edges of the second bonding area leads 1620 and the second contact pad metal layer 1612.
  • the second contact pad metal layer 1612 and the second conductive pattern 13112 are provided in the same layer, so the second contact pad metal layer 1612 and the second conductive pattern 13112 can be prepared by the same patterning process to simplify the process flow.
  • the second insulating layer 1332 located between the first bonding area 1300 and the second bonding area 1600 is located on the side of the second conductive pattern 13112 away from the base substrate 1000, and the second insulating layer 1332 extends to the second bonding area 1600 And cover the edge of the second contact pad metal layer 1612 to prevent the second contact pad metal layer 1612 from being corroded.
  • the third contact pad metal layer 1613 is located on the side of the second contact pad metal layer 1612 away from the base substrate 1612 and covers the edge of the second insulating layer 1332.
  • the third contact pad metal layer 1613 may be provided in the same layer as the third conductive pattern 13113. Therefore, the third contact pad metal layer 1613 and the third conductive pattern 13113 can be prepared by the same patterning process to simplify the manufacturing process.
  • the third contact pad metal layer 1613 is configured to expose the second insulating layer 1332 for electrical connection with an external circuit.
  • “same layer arrangement” means that two functional layers (for example, the first contact pad metal layer and the first conductive pattern) are formed in the same layer and the same material in the hierarchical structure of the display substrate, that is, in the preparation process
  • the two structural layers can be formed of the same material layer, and the required patterns and structures can be formed through the same patterning process.
  • the material layer can be formed by the patterning process after the material layer is formed first.
  • the two structure layers may be formed of the same material layer, but the required patterns and structures are formed through different patterning processes.
  • the two structural layers are located on the same layer, and the two structural layers may be formed of different material layers, and the required patterns and structures are formed through the same patterning process.
  • the display substrate further includes a third insulating laminate layer located in the transition area.
  • the third insulating laminate layer includes a first insulating laminate sublayer and a second insulating laminate sublayer.
  • the first insulating laminate The orthographic projection of the layer sublayer on the base substrate at least partially covers the transition area and the bonding peripheral area, and the orthographic projection of the second insulating laminated layer sublayer on the base substrate at least partially covers the transition area and the bonding peripheral area.
  • the third insulating laminated layer further includes a third insulating laminated layer sublayer, which is disposed between the first insulating laminated layer sublayer and the second insulating laminated layer sublayer, and the third insulating laminated layer
  • the orthographic projection of the sub-layer on the base substrate does not overlap with the first bonding area and the bonding peripheral area.
  • the first insulating laminate layer sublayer extends to the bonding peripheral area to obtain the first insulating layer
  • the second insulating laminate layer sublayer extends to the bonding peripheral area to obtain the second insulating layer
  • the second insulating laminate sublayer 1108 and the third insulating laminate sublayer 1109 at least partially overlap the first fan-out region and the second fan-out region, respectively.
  • the third insulating laminate layer includes a first insulating laminate sublayer 1107, a second insulating laminate sublayer 1108, and a third insulating laminate sublayer 1109.
  • the first insulating laminate sublayer 1107 is The orthographic projection on the base substrate 1000 covers the first fan-out area 1104 and the second fan-out area 1106, that is, the first insulating laminated layer sublayer 1107 is broken in the bending area 1105.
  • the first insulating laminated layer sublayer 1107 extends to the bonding peripheral area to obtain the first insulating layer 1331. Therefore, the first insulating laminated layer sublayer and the first insulating layer are arranged in the same layer.
  • the orthographic projection of the second insulating laminated layer sublayer 1108 on the base substrate 1000 covers the first fan-out area 1104, the bending area 1105, and the second fan-out area 1106, and extends to the bonding peripheral area to obtain the second insulating layer 1332, therefore, the second insulating laminated layer sub-layer and the second insulating layer are arranged in the same layer.
  • the orthographic projection of the third insulating laminate sublayer 1109 on the base substrate 1000 covers the first fan-out area 1104, the bending area 1105, and the second fan-out area 1106, the third insulating laminate sublayer 1109 and the bonding peripheral area Do not overlap.
  • the third insulating layer stack further includes a transition region buffer layer 1021, a transition region gate insulating layer 1028, and a transition region metal layer 1027.
  • the transition region buffer layer 1021 is provided in the same layer as the bonding region buffer layer 1341
  • the transition region gate insulating layer 1028 is provided in the same layer as the bonding region gate insulating layer 1342
  • the transition region metal layer 1027 is provided in the same layer as the first conductive pattern 13111.
  • the sub-pixels of each pixel unit in the pixel array of the display area of the display substrate may further include a pixel structure.
  • the pixel structure includes a pixel driving circuit, a first planarization layer, a first switching electrode, a second planarization layer, and a light-emitting element.
  • the first planarization layer is on a side of the pixel driving circuit away from the base substrate to provide a first planarization surface and includes a first via hole.
  • the first transfer electrode is on the first planarized surface and is electrically connected to the pixel driving circuit through the first via hole.
  • the second planarization layer is on a side of the first transfer electrode away from the base substrate to provide a second planarization surface and includes a second via hole.
  • the light emitting element is on the second planarized surface and is electrically connected to the first transfer electrode through the second via hole.
  • the second planarization layer and the second insulating layer are provided in the same layer. This simplifies the preparation process of the display substrate and reduces the cost of the product.
  • the pixel driving circuit may include thin film transistors, storage capacitors, etc., and may be implemented in various types, such as 2T1C type (that is, including two thin film transistors and a storage capacitor), and may further include more than 2T1C type.
  • 2T1C type that is, including two thin film transistors and a storage capacitor
  • Many transistors and/or capacitors can have functions of compensation, reset, light emission control, detection, etc.
  • the embodiments of the present disclosure do not impose limitations on the pixel driving circuit.
  • the thin film transistor directly electrically connected to the light-emitting element may be a driving transistor, a light-emitting control transistor, or the like.
  • FIG. 3 is a schematic cross-sectional view of the display area of the display substrate shown in FIG. 1A.
  • the sub-pixels in the display area of the display substrate 100 may further include a pixel structure 1110 for implementing light emission driving and control.
  • the pixel structure 1110 includes a pixel driving circuit 1120, a first planarization layer 1130, a first transfer electrode 1180, a second planarization layer 1190, and a light-emitting element 1140.
  • the pixel structure 1110 further includes a buffer layer 1121 located on the base substrate 1000
  • the pixel driving circuit 1120 may include an active layer 1122 located on the buffer layer 1121, and a gate insulation located on the side of the active layer 1122 away from the base substrate 1000.
  • the gate 11211 may be provided in the same layer as the lead 1210 in the first bonding region 1300. Therefore, the gate 11211 and the lead 1210 can be formed in the same layer during the manufacturing process, for example, the same material layer is used to form the same layer through a patterning process.
  • the interlayer insulating layer 1129 and the first insulating layer 1331 are arranged in the same layer. Therefore, the interlayer insulating layer 1129 and the first insulating layer 1331 can be formed in the same layer during the preparation process, for example, the same material layer is formed through a patterning process.
  • the buffer layer 1121 in the display area is arranged in the same layer as the transition area buffer layer 1021 and the bonding area buffer layer 1341, and the buffer layer 1121, the transition area buffer layer 1021 and the bonding area buffer layer 1341 can be formed in the same layer in the manufacturing process.
  • the gate insulating layer 1128 in the display area is arranged in the same layer as the gate insulating layer 1342 of the bonding area and the gate insulating layer 1028 of the transition area.
  • the gate insulating layer 1128, the gate insulating layer 1342 of the bonding area and the gate insulating layer 1028 of the transition area can be prepared in the manufacturing process. Formed in the same layer.
  • the buffer layer 1121 serves as a transition layer, which can prevent harmful substances in the base substrate from intruding into the interior of the display substrate, and can increase the adhesion of the film layer in the display substrate 100 on the base substrate 1000.
  • the material of the buffer layer 1121 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the material of one or more of the fourth insulating layer 11210, the interlayer insulating layer 1129, and the gate insulating layer 1128 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the materials of the fourth insulating layer 11210, the interlayer insulating layer 1129, and the gate insulating layer 1128 may be the same or different.
  • the active layer 1122 may include a source region 1123, a drain region 1124, and a channel region located between the source region 1123 and the drain region 1124.
  • the fourth insulating layer 11210, the interlayer insulating layer 1129, and the gate insulating layer 1128 have via holes in them to expose the source region 1123 and the drain region 1124.
  • the source electrode 1125 and the drain electrode 1126 are electrically connected to the source region 1123 and the drain region 1124 through via holes, respectively.
  • the gate 11211 overlaps the channel region between the source region 1123 and the drain region 1124 in the active layer 1122 in a direction perpendicular to the base substrate 1000.
  • the first planarization layer 1130 is located above the source electrode 1125 and the drain electrode 1126 for planarizing the surface of the pixel driving circuit away from the base substrate.
  • the first planarization layer 1130 may planarize the uneven surface caused by the pixel driving circuit, and thus prevent the unevenness caused by the pixel driving circuit from causing defects in the light emitting device.
  • a first via hole 1131 is formed in the first planarization layer 1130 to expose the source electrode 1125 or the drain electrode 1126 (the case shown in the figure), and a first transfer electrode 1180 is formed on the first planarization layer 1130.
  • the first transfer electrode 1180 is electrically connected to the drain 1126 through the first via hole 1131.
  • the first transfer electrode can avoid directly forming a straight through hole with a relatively large diameter in the first planarization layer and the second planarization layer. Therefore, the quality of the electrical connection of the via is improved, and at the same time, the first transfer electrode can also be formed in the same layer as other signal lines (such as power lines, etc.), which will not lead to an increase in process steps.
  • the first connecting electrode 1180 and the second conductive pattern 13112 of the contact pad 1310 are arranged in the same layer. Therefore, the first connecting electrode 2180 and the second conductive pattern 13112 can be formed in the same layer during the preparation process, for example, the same material layer is used for patterning. The process is formed, thereby simplifying the preparation process.
  • the material of the first transfer electrode 1180 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, and titanium.
  • the material of the active layer 1122 may include polysilicon or oxide semiconductor (for example, indium gallium zinc oxide).
  • the material of the gate 11211 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, and titanium.
  • the multi-layer structure is a multi-metal laminated layer (such as three layers of titanium, aluminum, and titanium). Metal stack (Al/Ti/Al)).
  • the material of the source electrode 1125 and the drain electrode 1126 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, and titanium.
  • the multi-layer structure is a multi-metal laminated layer (such as titanium, Aluminum and titanium three-layer metal stack (Al/Ti/Al)).
  • the embodiments of the present disclosure do not specifically limit the material of each functional layer.
  • the pixel driving circuit 1120 may further include a first display metal layer 1127, and the first display area metal layer 1127 and the first conductive pattern 13111 are provided in the same layer.
  • the first display metal layer 2127 includes the source electrode 1125 and the drain electrode 1126 of the above-mentioned thin film transistor in the pixel driving circuit.
  • the source electrode 1125 and the drain electrode 1126 are arranged in the same layer as the first conductive pattern 13111. Therefore, the source electrode 1125 and the drain electrode 1126 and the first contact pad metal layer 1215 can be formed in the same layer during the manufacturing process, for example, the same material layer is formed through a patterning process, thereby simplifying the manufacturing process and reducing the manufacturing cost of the product.
  • the second planarization layer 1190 is disposed on the side of the first transfer electrode 1180 away from the base substrate 1000, and is used to place the first transfer electrode 1180 away from the substrate 1000.
  • a flattened surface is provided on one side of the base substrate 1000.
  • a second via 1191 is formed in the second planarization layer 1190.
  • the second planarization layer 1190 and the second insulating layer 1332 are formed in the same layer. Therefore, the second planarization layer 1190 and the second insulating layer 1332 can be formed in the same layer during the preparation process, for example, the same material layer is formed by a patterning process, thereby simplifying Preparation Process.
  • the light-emitting element 1140 is formed on the second planarization layer, that is, the light-emitting element 1140 is disposed on the side of the second planarization layer 1190 away from the base substrate.
  • the light emitting element 1140 includes a first electrode 1141, a light emitting layer 1142 and a second electrode 1143.
  • the first electrode 1141 of the light-emitting element is electrically connected to the drain 1126 through the first via 1131 in the first planarization layer 1130.
  • a pixel defining layer 1144 is formed on the first electrode 1141, and the pixel defining layer 1144 includes a plurality of openings to define a plurality of pixel units.
  • Each of the plurality of openings exposes the first electrode 1141, and the light emitting layer 1142 is disposed in the plurality of openings of the pixel defining layer 1144.
  • the second electrode 1143 may be disposed in a part or the entire display area, for example, so that it may be formed on the entire surface during the manufacturing process.
  • the first electrode 1141 may include a reflective layer
  • the second electrode 1143 may include a transparent layer or a semi-transparent layer.
  • the first electrode 1141 can reflect the light emitted from the light-emitting layer 1142, and this part of the light is emitted into the external environment through the second electrode 1143, so that the light emission rate can be improved.
  • the second electrode 1143 includes a semi-transmissive layer, some light reflected by the first electrode 1141 is reflected again by the second electrode 1143, so the first electrode 1141 and the second electrode 1143 form a resonance structure, so that light emission efficiency can be improved.
  • the material of the first electrode 1141 may include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and the like.
  • the first electrode 1141 may include a metal having high reflectivity as a reflective layer, such as silver (Ag).
  • the light-emitting layer 1142 may include small molecular organic materials or polymer molecular organic materials, which may be fluorescent light-emitting materials or phosphorescent light-emitting materials, which can emit red light, green light, blue light, or white light; and, as required
  • the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light-emitting layer may include quantum dot materials, for example, silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, selenium Lead fluoride quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc.
  • the particle size of the quantum dots is 2-20nm.
  • the material of the pixel defining layer 1144 may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic materials such as silicon oxide and silicon nitride.
  • organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic materials such as silicon oxide and silicon nitride.
  • the insulating material is not limited in the embodiment of the present disclosure.
  • the display substrate 100 further includes a storage capacitor 1160
  • the storage capacitor 1160 may include a first capacitor electrode 1161 and a second capacitor electrode 1162.
  • the first capacitor electrode 1161 is disposed between the gate insulating layer 1128 and the interlayer insulating layer 1129
  • the second capacitor electrode 1162 is disposed between the interlayer insulating layer 1129 and the fourth insulating layer 11210.
  • the first capacitor electrode 1161 and the second capacitor electrode 1162 overlap and at least partially overlap in a direction perpendicular to the base substrate 1000.
  • the first capacitor electrode 1161 and the second capacitor electrode 1162 use the interlayer insulating layer 1129 as a dielectric material to form a storage capacitor.
  • the first storage capacitor electrode 1161 is arranged in the same layer as the gate 11211 in the pixel driving circuit 1120 and the lead 1210 in the first bonding area 1200. Therefore, the first storage capacitor electrode 1161, the gate 11211, and the lead 1210 can be prepared in the manufacturing process.
  • the same layer is formed, for example, the same material layer is formed through a patterning process, thereby simplifying the manufacturing process and reducing the manufacturing cost of the product.
  • the first capacitor electrode of the storage capacitor is still arranged in the same layer as the gate electrode 11211, and the second capacitor electrode of the storage capacitor is the same as the source electrode 1125 and the drain electrode of the thin film transistor.
  • 1126 is arranged in the same layer (that is, it is also located in the first display metal layer 1127), so the first capacitor electrode and the second capacitor electrode are formed by using a stack of the interlayer insulating layer 1129 and the fourth insulating layer 11210 as a dielectric material Storage capacitor.
  • the first capacitor electrode of the storage capacitor is no longer arranged in the same layer as the gate electrode 11211, but is located between the interlayer insulating layer 1129 and the fourth insulating layer 11210 in the display area.
  • the second capacitor electrode of the storage capacitor is arranged in the same layer as the source electrode 1125 and drain electrode 1126 of the thin film transistor (that is, it is also located in the first display metal layer 1127), so the first capacitor electrode and the second capacitor electrode are used
  • the fourth insulating layer 11210 is used as a dielectric material to form a storage capacitor.
  • the display substrate 100 further includes an encapsulation layer 1150 on the light-emitting element 1140.
  • the encapsulation layer 1150 seals the light emitting element 1140, so that deterioration of the light emitting element 1140 caused by moisture and/or oxygen included in the environment can be reduced or prevented.
  • the encapsulation layer 1150 may be a single-layer structure or a composite layer structure, and the composite layer structure includes a structure in which an inorganic layer and an organic layer are stacked.
  • the encapsulation layer 1150 includes at least one encapsulation sublayer.
  • the encapsulation layer 1150 may include a first inorganic encapsulation layer 1151, a first organic encapsulation layer 1152, and a second inorganic encapsulation layer 1153 that are sequentially arranged.
  • the encapsulation layer does not cover the contact pads.
  • the barrier dam of the dam region 1102 can be arranged in the same layer as one or more of the first planarization layer, the second planarization layer, and the pixel defining layer, thereby preventing the encapsulation layer from Overflow of organic layer.
  • the material of the blocking dam may include an organic insulating material.
  • the organic insulating material may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as polymer resin.
  • the display substrate further includes a fifth insulating layer 11110 located in the display area, an auxiliary conductive electrode 11120, and a display area protection layer 11130.
  • the fifth insulating layer 11110 is disposed on the packaging layer 1150 to cover the packaging layer 1150.
  • the fifth insulating layer 11110 is not necessary.
  • the fifth insulating layer 11110 may also be removed to reduce the thickness of the display substrate.
  • the auxiliary electrode 11120 is disposed on a side of the fifth insulating layer 11110 away from the base substrate.
  • the auxiliary electrode 11120 can be used for other auxiliary functions, such as a touch function, and has an opening on one pixel structure 1110.
  • the display area protection layer 11130 is disposed on the side of the auxiliary electrode 11120 away from the base substrate to protect the auxiliary electrode 11120.
  • the display area protection layer 11130 and the third insulating layer 1333 are provided in the same layer.
  • the material of the fifth insulating layer 11110 may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or include silicon oxide, silicon nitride, etc.
  • organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or include silicon oxide, silicon nitride, etc.
  • organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or include silicon oxide, silicon nitride, etc.
  • Inorganic insulating materials the embodiments of the present disclosure do not limit this.
  • the auxiliary electrode used to implement the touch function can be used to implement a capacitive touch structure, and the capacitive touch structure is a self-capacitance type or a mutual-capacitance type.
  • the self-capacitive touch structure includes a plurality of self-capacitance electrodes arranged in an array (on the same layer), and each self-capacitance electrode is electrically connected to a touch processing circuit (touch chip) through a touch lead.
  • the position detection is achieved by detecting the change in capacitance of the self-capacitance electrode due to, for example, the approach of a finger during touch.
  • the mutual capacitance type touch structure includes a plurality of first touch signal lines extending in a first direction and a plurality of second touch signal lines extending in a second direction, the first touch signal line and the second touch signal line All are electrically connected to the touch processing circuit (touch chip) through the touch lead.
  • the first direction and the second direction cross each other and form an opening, thereby forming a touch capacitance at the crossing position of the first touch signal line and the second touch signal line, which is caused by, for example, the approach of a finger during touch.
  • the change of touch capacitance realizes position detection.
  • the embodiments of the present disclosure take a mutual capacitance type touch structure as an example for description.
  • the mutual-capacitive touch structure includes excitation electrodes and sensing electrodes intersecting each other and arranged in the same layer to realize the touch function of the display substrate.
  • the first sensing electrode is segmented, and the exciting electrode is continuous.
  • a bridging electrode located on a different layer from the exciting electrode and the sensing electrode is provided. (Shown) to electrically connect two adjacent sections of the sensing electrode to each other.
  • the auxiliary electrode 11120 and the third conductive pattern 13113 are provided in the same layer.
  • the third conductive pattern 13113 may be made of the same material as the sensing electrode and the excitation electrode, and formed by the same patterning process.
  • the material forming the auxiliary electrode 11120 may include indium tin oxide (ITO), and a transparent electrode may be obtained therefrom, or the material forming the auxiliary electrode 11120 may include a metal mesh, or a transparent electrode may be obtained therefrom.
  • ITO indium tin oxide
  • the auxiliary electrode 11120 may be used as a touch electrode in other embodiments.
  • At least one embodiment of the present disclosure further provides a display substrate, which includes a base substrate, a lead, a contact pad, a first insulating laminated layer, and a second insulating laminated layer.
  • the base substrate includes a display area and a display peripheral area at least partially surrounding the display area.
  • the display peripheral area includes a first bonding area, a bonding boundary area, and a bonding peripheral area located on one side of the display area, and the bonding boundary area is located at the first bonding area.
  • the lead is located in the first bonding area;
  • the contact pad is located in the first bonding area, the contact pad includes at least two conductive patterns, and the contact pad is located on a lead away from the base substrate Side and electrically connected to the lead;
  • the first insulating laminate layer is located in the bonding boundary area;
  • the second insulating laminate layer is located in the bonding peripheral area, and at least one insulating layer of the second insulating laminate layer extends into the bonding boundary area to obtain
  • the first insulating laminated layer, at least one insulating layer of the first insulating laminated layer covers the edge of one of the at least two conductive patterns and the edge of the at least one insulating layer is covered by the other of the at least two conductive patterns.
  • a first insulating laminate layer is provided in the bonding boundary area of the display peripheral area, at least one edge of the first insulating laminate layer covers the edge of one of the at least two conductive patterns, and at least one insulating layer
  • the edge of the at least two conductive patterns is covered by the other of the at least two conductive patterns, so as to prevent the conductive pattern on the side close to the base substrate from being corroded by the etching solution during the preparation of other film layers, and also prevent the metal in the conductive pattern from falling off and Stripping is more helpful to complete the bonding process, thereby improving the product yield of the display substrate.
  • FIG. 4A is a plan view of another display substrate provided by an embodiment of the present disclosure.
  • 4B is a plan view of the first bonding area of another display substrate provided by an embodiment of the disclosure.
  • the display substrate is used in, for example, an organic light emitting diode (OLED) display device or a quantum dot light emitting diode (QLED) display device.
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • the display area 2100 includes a plurality of sub-pixels and a plurality of signal lines 2101, and the plurality of signal lines 2101 includes signal lines (such as gates) extending in a first direction (the X-axis direction in the figure).
  • Line G and signal lines extending along the second direction (the Y-axis direction in the figure) (for example, data line D.
  • These signal lines extend or route to the first bonding area located at least one side of the display area 2100, for example, the signal The line 2103 is electrically connected to the corresponding lead, so that it can be electrically connected to the driver chip, flexible circuit board, etc. bonded in the first bonding area.
  • the signal line 2101 can provide scanning of control signals, data signals, voltage signals, etc. for the pixel array Line (gate line), data line, power line, detection line, etc.
  • the display substrate 200 includes a base substrate.
  • the base substrate includes a display area 2100 and a display peripheral area 2200 surrounding the display area 2100.
  • the display peripheral area 2200 includes a dam area 2102 and a transition area. 2103, the cofferdam area 2102 surrounds the display area, and the transition area 2103 is located on the side of the display area 2100.
  • the cofferdam area 2102 includes a barrier dam, which may be formed as a one-layer or multi-layer structure.
  • the base substrate further includes a first bonding area 2300 and a bonding peripheral area 2500 located on the side of the display area 2100.
  • the first bonding area 2300 includes the bonding border area 2400.
  • the Bonding Border Area 2400 is located between the First Bonding Area 2300 and the Bonding Peripheral Area 2500.
  • the first bonding area 2300 may use COP (Chip on Pi) packaging technology to bond the integrated circuit chip to the flexible substrate (for example, Pi substrate) of the display substrate.
  • the display peripheral area 2200 also includes a second bonding area 2600 located on the side of the second bonding area 2300 away from the display area 2100 using FOP (FPC (Flexible Printed Circuit) On Pi) double-sided bonding technology. .
  • FOP FPC (Flexible Printed Circuit) On Pi) double-sided bonding technology.
  • the figure shows one first bonding area 2300, but the number of first bonding areas in the present disclosure is not limited to this. It should be noted that the detailed structure and film arrangement of the transition region 2103 shown in FIG. 4A are the same as those of the transition region 1103 shown in FIG. 1A, and will not be described in detail here.
  • the display substrate 200 may further include a plurality of leads 2210 and a plurality of contact pads 2310, and the plurality of contact pads 2310 are arranged in the first bonding region 1300.
  • the plurality of contact pads 2310 includes a plurality of first contact pads 2311 and a plurality of second contact pads 2312.
  • the plurality of first contact pads 2311 are located on the side of the first bonding area 2300 close to the display area, and the plurality of second contact pads 2312 are located on the side of the first bonding area 2300 away from the display area.
  • the plurality of second contact pads 2312 are arranged in at least one row (one row is shown), and the plurality of first contact pads 2311 are arranged in at least one row (one row is shown).
  • the direction of the row is the direction in which the first bonding area 2300 faces the display area 2100.
  • the plurality of first contact pads 2311 and the plurality of second contact pads 2312 may also be arranged in multiple rows, respectively, and the embodiment of the present disclosure is not limited thereto.
  • the multiple leads 2210 are electrically connected to the multiple contact pads 2310 in a one-to-one correspondence.
  • One end of the lead 2210 extends to the display area 2100 to be electrically connected to a corresponding signal line (such as a data line) in the display area 2100, and the other end of the lead 2210 extends to the first bonding area 2300 to be electrically connected to the contact pad 2310.
  • the leads 2210 are arranged in the same layer as the signal lines in the display area 2100, and thus can be formed integrally or in different layers, and thus need to be electrically connected to each other through vias in the interlayer insulating layer between the two.
  • the first contact pad 2311 and the second contact pad 2312 are configured to transmit signals in the external circuit, such as display signals, to the leads of the display area.
  • the third contact pad 2620 is configured to transmit a signal in the external circuit, such as a display signal, to the second contact pad in the first bonding area, and then the second contact pad transmits the signal to Leads to the display area.
  • a signal in the external circuit such as a display signal
  • the display substrate 200 further includes a plurality of second bonding area leads 2620 and a plurality of third contact pads 2610.
  • the plurality of second bonding area leads 2620 are electrically connected to the plurality of third contact pads 2620 in a one-to-one correspondence.
  • One end of the second bonding area lead 2620 extends to the first bonding area 2300 to be electrically connected to the second contact pad 2311, and the other end of the second bonding area lead 2620 extends to the second bonding area 2600 and the third contact
  • the pad 2610 is electrically connected.
  • the section line M3-N3 in FIG. 4A passes through the first contact pad 2311, the second contact pad 2322 in the first bonding area 2300, and the third contact pad 2610 in the second bonding area 2600 to show The film layer change relationship between the first bonding area 2300 and the second bonding area 1600 is shown.
  • the contact pad 2310 includes a conductive pattern stack 13110.
  • the section line M4-N4 passes through the second contact pad 2312 near the bonding border area 2400 in row L3, and passes through the bonding border area 2400 and the bonding peripheral area 2500 to show the first state.
  • the relationship between the film layer changes in Ding District 2300, Bonding Boundary Zone 2400, and Bonding Peripheral Zone 2500.
  • the display substrate 200 further includes a first insulating laminated layer 2320 and a second insulating laminated layer 2330.
  • the first insulating laminate layer 2320 is located in the bonding boundary area 2400, and the second insulating laminate layer 2330 is located in the bonding peripheral area 2500.
  • the insulating layer on the top layer of the first insulating laminated layer 2320 extends to the first bonding area 2300 and covers the edges of the plurality of contact pads 2310.
  • the lead 2210 connecting the second contact pad 2312 extends through the gap of the first contact pad 2311 in row L4 in the first bonding area, and then extends to the display area 2100, so that the contact pad 2310 has It has a larger arrangement space and can avoid mutual interference or short-circuit with the lead 2210 connected to the first contact pad 2311 of the L4 row.
  • the multiple leads 2210 may also be located in different layers.
  • the lead 2210 used to connect the second contact pad 2312 is located at a layer closer to the base substrate
  • the lead 2210 used to connect the first contact pad 2311 is located in a layer closer to the base substrate.
  • the spacing between the multiple leads 2210 in the same layer can be increased, which reduces the risk of interference and short circuit between the leads, which is beneficial to forming a display device with high pixel resolution.
  • multiple leads 2210 in the same layer can be prepared in the same patterning process; multiple leads 2210 in different layers can be prepared in different patterning processes.
  • the material of the lead 2210 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, and titanium.
  • FIG. 5A is a schematic cross-sectional view of the display substrate shown in FIG. 4B along M4-N4.
  • the contact pad 2310 is located on the side of the lead 2210 away from the base substrate 2000.
  • At least two insulating layers of the second insulating laminated layer 2330 extend into the bonding boundary region 2400 to obtain the first insulating laminated layer 2320.
  • the height C6 of the first insulating laminated layer 2320 relative to the base substrate 2000 is smaller than the height C4 of the second insulating laminated layer 2330 relative to the base substrate 2000.
  • the height of the film level difference in the surrounding area of the bonding is reduced, so as to reduce the risk of generating bubbles in the surrounding area of the bonding and the bonding boundary area, and improve the product yield and reliability of the display substrate.
  • the base substrate 2000 may be a glass plate, a quartz plate, a metal plate, or a resin plate.
  • the material of the base substrate may include an organic material.
  • the organic material may be polyimide (Pi), polycarbonate, polyacrylate, polyetherimide, polyethersulfone, and polyethylene terephthalate.
  • resin materials such as glycol ester and polyethylene naphthalate
  • the base substrate 2000 may be a flexible substrate or a non-flexible substrate, which is not limited in the embodiments of the present disclosure.
  • the second insulating layer stack 2330 includes the first insulating layer 2331 and the second insulating layer 2332 in the bonding peripheral region 2500.
  • the first insulating layer 2331 is located on the base substrate 2000
  • the second insulating layer 2332 is located on the side of the first insulating layer 2331 away from the base substrate 2000.
  • the first insulating layer 2331 and the second insulating layer 2332 extend into the bonding boundary region 2400 to obtain the first insulating layered layer 2320.
  • the height C6 of the second insulating layer 2332 in the bonding boundary region 2400 is smaller than the height C5 of the second insulating layer 2332 in the bonding peripheral region 2500.
  • the second insulating layer 2332 in the bonding boundary area 2400 and in the bonding peripheral area 2500, although the second insulating layer 2332 is integrated, it has different heights. As shown in the figure, the parts with different heights can be continuously transitioned. For example, it has a slope angle relative to the base substrate, and the slope angle is, for example, about 40-60 degrees, and for example, about 50 degrees. It should be noted that the height of the second insulating layer 2332 refers to the vertical distance from the surface of the second insulating layer 2332 to the surface of the base substrate 2000.
  • the film thickness of the second insulating layer 2332 in the bonding boundary region 2400 may be about 1.0 ⁇ m to 1.4 ⁇ m
  • the value of the vertical distance may be about 1.2 microns.
  • the film thickness of the second insulating layer 2332 in the bonding peripheral region 2500 may range from about 1.8 ⁇ m to 2.2 ⁇ m, for example, the film thickness may be about 2 ⁇ m.
  • the value range of the height difference H1 between the height C2 of the second insulating layer 2332 in the bonding peripheral region 2500 and the height of the second insulating layer 2332 in the bonding boundary region 2400 may be about 0.4 to 1.2 micrometers, for example ,
  • the height difference can be about 0.8 microns.
  • the height difference of the film layer in the bonding boundary area in the surrounding area of the bonding that is, the film level difference is reduced, to reduce the risk of air bubbles in the surrounding area of the bonding and the bonding boundary area, and to improve the product yield of the display substrate and reliability.
  • the word "about” indicates the range of variation of a given value, which is within ⁇ 15% of the value, such as ⁇ 5%, ⁇ 10%, etc.
  • the material of the first insulating layer 2331 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc., or may include polyimide (Pi), polyphthalimide, polyphthalamide, acrylic resin, or benzene. And organic insulating materials such as cyclobutene or phenolic resin.
  • inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc.
  • polyimide (Pi) polyphthalimide
  • polyphthalamide acrylic resin
  • acrylic resin or benzene
  • organic insulating materials such as cyclobutene or phenolic resin.
  • the embodiment of the present disclosure does not specifically limit the material of the first insulating layer.
  • the material of the second insulating layer 2332 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or may include polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or Organic insulating materials such as phenolic resin.
  • the embodiment of the present disclosure does not specifically limit the material of the second insulating layer.
  • At least two insulating layers of the second insulating laminated layer 2330 further include a third insulating layer 2333.
  • the third insulating layer 2333 is located on the side of the second insulating layer 2332 away from the base substrate 2000 and is configured to expose the second insulating layer 2332 on the side close to the contact pad 2310.
  • the third insulating layer 2333 has a side with a slope angle on the side close to the bonding boundary area 2320, and this side is different from the side of the second insulating layer 2332 at the bonding peripheral area 2330 close to the bonding boundary area 2320. The sides of the slope angle are not aligned.
  • the distance from the side of the third insulating layer 2333 to the bonding boundary area 2320 is greater than the distance from the side of the second insulating layer 2332 to the bonding boundary area 2320.
  • the greater the distance between the third insulating layer and the bonding boundary area the more conducive to reducing the risk of bubbles in the bonding boundary area during the bonding process.
  • the third insulating layer 2333 can also protect the surrounding lines. effect.
  • the film thickness of the third insulating layer 2333 may be about 3 microns.
  • the height difference H2 between the height C5 of the second insulating layer 2332 in the bonding peripheral area 2500 and the height of the second insulating layer 2332 in the bonding boundary area 2400 plus the thickness of the third insulating layer 2333 is the distance of the second insulating layer 2330
  • the difference h2 between the height C4 of the base substrate 2000 and the height C6 of the first insulating laminate layer 1320 from the base substrate 1000, the value range of the difference h2, for example, may be about 3.4 to 4.2 microns. The difference can be about 3.8 microns.
  • the range of the distance d2 obtained by the projection of the above difference h2 on the base substrate is approximately between 100 micrometers and 200 micrometers.
  • the material of the third insulating layer 2333 may include an organic insulating material.
  • the organic insulating material may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as polymer resin.
  • the display substrate 200 further includes a bonding region buffer layer 2341 located above the base substrate 200 and a bonding region gate insulating layer 2342 located on the side of the bonding region buffer layer 2341 away from the base substrate 2000.
  • the lead 2210 is located on the gate insulating layer 2242 in the bonding area. One end of the lead 2210 is electrically connected to the contact pad 2310.
  • the first insulating layer 2331 extends until the first bonding area is located between the contact pad 2310 and the lead 2210.
  • the conductive pattern stack of the contact pad includes at least two conductive patterns, at least one insulating layer of the first insulating stack covers the edge of one of the at least two conductive patterns, and the edge of the at least one insulating layer is in the at least two conductive patterns. Covered by the other.
  • the conductive pattern stack 23110 includes a first conductive pattern 23111 and a second conductive pattern 23112.
  • the first conductive pattern 23111 is located on the side of the lead 2210 away from the base substrate 2000 and is electrically connected to the lead 2210.
  • the second conductive pattern 23112 is located on a side of the first conductive pattern 23111 away from the base substrate 2000 and covers the edge of the first conductive pattern 23111 to prevent the first conductive pattern 23111 from being corroded by the etching solution.
  • the first insulating layer 2331 is located between the first conductive pattern 23111 and the lead 2210 such that the first conductive pattern 23111 and the lead 2210 are electrically insulated.
  • a first conductive pattern via 23114 is formed in the first insulating layer 2331.
  • the first conductive pattern 23111 and the lead 2331 are electrically connected through the first conductive pattern via 23114.
  • the second insulating layer 2332 in the first insulating laminated layer 2320 extends to the first bonding area to cover the edge of the second conductive pattern 23112 to prevent the second conductive pattern 23112 from being corroded.
  • the second conductive pattern 23112 is configured to expose the first insulating laminated layer 2320 for electrical connection with an external circuit.
  • the material of the first conductive pattern 23111 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, and the like.
  • the material of the second conductive pattern 23112 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, and titanium.
  • the bonding boundary area 2400 further includes a marking metal layer 2350 located between the first insulating layer 2331 and the second insulating layer 2332, which is used for external bonding during the bonding process. Alignment of the circuit.
  • the marking metal layer 2350 may be provided in the same layer as the first conductive pattern 23111 or the second conductive pattern 23112.
  • the embodiment of the present disclosure has no limitation on the plane pattern of the marking metal layer, for example, it may be a cross, a square, a rectangle, and the like.
  • the third contact pad located in the second bonding area includes a plurality of contact pad metal layers, and the plurality of contact pad metal layers includes a first contact pad metal layer and a second contact pad metal layer,
  • the first contact pad metal layer is arranged on the side of the first insulating layer away from the base substrate, the second contact pad metal layer is laminated with the first contact pad metal layer and covers the periphery of the second contact pad metal layer, wherein the first contact The pad metal layer and the first conductive pattern layer are arranged in the same layer, and the second contact pad metal layer and the second conductive pattern layer are arranged in the same layer.
  • the second contact pad metal layer extends to the first bonding area to form a second bonding area lead, and the second insulating layer extends to the second bonding area and covers the second bonding area. Zone leads and the edges of the second contact pad metal layer.
  • the thickness of the portion of the second insulating layer located between the first bonding area and the second bonding area in the direction perpendicular to the base substrate is different from the thickness of the second insulating layer located in the first state.
  • the thickness of the part of the fixed area in the direction perpendicular to the base substrate is basically the same.
  • the orthographic projection of the part of the second insulating layer between the first bonding area and the second bonding area on the base substrate is the same as that of the second bonding.
  • FIG. 5B is a schematic cross-sectional view of the display substrate shown in FIG. 4A along M1-N1.
  • the bonding region buffer layer 2341 and the bonding region gate insulating layer 2342 further extend to the second bonding region 2600.
  • the lead 2210 connected to the first contact pad 2311 further extends to the bonding boundary area 2500.
  • the film stack at the bonding boundary region 2500 includes a lead 2210, a first insulating layer 2331, a second insulating layer 2332, and a third insulating layer 2333.
  • the thickness of the second insulating layer 2332 in the bonding peripheral area is greater than that in the first bonding area, and the difference in thickness is approximately the same as the value of H2 shown in FIG. 5A.
  • the third contact pad 2610 includes a first contact pad metal layer 2611 and a second contact pad metal layer 2612.
  • the first contact pad metal layer 2611 is located on the gate insulating layer 2342 in the bonding area.
  • the first contact pad metal layer 2611 and the first conductive pattern 23111 are provided in the same layer. Therefore, the first contact pad metal layer 2611 and the first conductive pattern 23111 can be used The same patterning process is prepared to simplify the process flow.
  • the second contact pad metal layer 2612 is located on the side of the first contact pad metal layer 2611 away from the base substrate, and covers the edge of the first contact pad metal layer 2611 to prevent the first contact pad metal layer 2611 from being corroded by the etching solution .
  • the second bonding area lead 2620 is covered between the edge of the first contact metal layer 1611 on the side of the first bonding area 2300 and the edge of the second conductive pattern 13112 on the side of the second bonding area 2600.
  • the second contact pad metal layer 2612 extends toward the first bonding area 2300 to form a second bonding area lead 2620.
  • the second insulating layer 2332 extends to the second bonding area 2600 and covers the edges of the second bonding area leads 2620 and the second contact pad metal layer 2612.
  • the second contact pad metal layer 2612 and the second conductive pattern 23112 are provided in the same layer, so the second contact pad metal layer 2612 and the second conductive pattern 23112 can be prepared by the same patterning process to simplify the process flow.
  • the second insulating layer 2332 located between the first bonding area 2300 and the second bonding area 2600 is located on the side of the second conductive pattern 23112 away from the base substrate 2000, and the second insulating layer 2332 extends to the second bonding area 2600 And cover the second contact pad metal layer 2612 to prevent the second contact pad metal layer 2612 from being corroded.
  • the second contact pad metal layer 2612 is configured to expose the second insulating layer 2332 for electrical connection with an external circuit.
  • “same layer arrangement” means that two functional layers (for example, the first contact pad metal layer and the first conductive pattern) are formed in the same layer and the same material in the hierarchical structure of the display substrate, that is, in the preparation process
  • the two structural layers can be formed of the same material layer, and the required patterns and structures can be formed through the same patterning process.
  • the material layer can be formed by the patterning process after the material layer is formed first.
  • the two structure layers may be formed of the same material layer, but the required patterns and structures are formed through different patterning processes.
  • the two structural layers are located on the same layer, and the two structural layers may be formed of different material layers, and the required patterns and structures are formed through the same patterning process.
  • the sub-pixels of each pixel unit in the pixel array of the display area of the display substrate may further include a pixel structure.
  • the pixel structure includes a pixel driving circuit, a first planarization layer, a first switching electrode, a second planarization layer, and a light-emitting element.
  • the first planarization layer is on a side of the pixel driving circuit away from the base substrate to provide a first planarization surface and includes a first via hole.
  • the first transfer electrode is on the first planarized surface and is electrically connected to the pixel driving circuit through the first via hole.
  • the second planarization layer is on a side of the first transfer electrode away from the base substrate to provide a second planarization surface and includes a second via hole.
  • the light emitting element is on the second planarized surface and is electrically connected to the first transfer electrode through the second via hole.
  • the second planarization layer and the second insulating layer are provided in the same layer. This simplifies the preparation process of the display substrate and reduces the cost of the product.
  • the pixel driving circuit may include thin film transistors, storage capacitors, etc., and may be implemented in various types, such as 2T1C type (that is, including two thin film transistors and a storage capacitor), and may further include more than 2T1C type.
  • 2T1C type that is, including two thin film transistors and a storage capacitor
  • Many transistors and/or capacitors can have functions of compensation, reset, light emission control, detection, etc.
  • the embodiments of the present disclosure do not impose limitations on the pixel driving circuit.
  • the thin film transistor directly electrically connected to the light-emitting element may be a driving transistor, a light-emitting control transistor, or the like.
  • FIG. 6 is a schematic cross-sectional view of the display area of the display substrate shown in FIG. 4A.
  • the sub-pixels in the display area of the display substrate 200 may further include a pixel structure 2110 for implementing light emission driving and control.
  • the pixel structure 2110 includes a pixel driving circuit 2120, a first planarization layer 2130, a first transfer electrode 2180, a second planarization layer 2190, and a light-emitting element 2140.
  • the pixel structure 2110 further includes a buffer layer 2121 located on the base substrate 2000
  • the pixel driving circuit 2120 may include an active layer 2122 located on the buffer layer 2121, and a gate insulation located on the side of the active layer 2122 away from the base substrate 2000.
  • the gate 21211 may be provided in the same layer as the lead 2210 in the first bonding region 2300. Therefore, the gate 21211 and the lead 2210 can be formed in the same layer during the preparation process, for example, formed by a patterning process using the same material layer.
  • the interlayer insulating layer 2129 and the first insulating layer 2331 are provided in the same layer. Therefore, the interlayer insulating layer 2129 and the first insulating layer 2331 can be formed in the same layer during the preparation process, for example, the same material layer is formed through a patterning process.
  • the buffer layer 2121 in the display area and the bonding area buffer layer 2341 are arranged in the same layer, and the buffer layer 2121 and the bonding area buffer layer 2341 can be formed in the same layer during the manufacturing process.
  • the gate insulating layer 2128 in the display area and the bonding area gate insulating layer 2342 are provided in the same layer, and the gate insulating layer 2128 and the bonding area gate insulating layer 2342 can be formed in the same layer during the manufacturing process.
  • the buffer layer 2121 serves as a transition layer, which can prevent harmful substances in the base substrate from intruding into the interior of the display substrate, and can increase the adhesion of the film layer in the display substrate 200 on the base substrate 2000.
  • the material of the buffer layer 2121 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the material of one or more of the fourth insulating layer 21210, the interlayer insulating layer 2129, and the gate insulating layer 2128 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the materials of the fourth insulating layer 21210, the interlayer insulating layer 2129, and the gate insulating layer 2128 may be the same or different.
  • the active layer 2122 may include a source region 2123, a drain region 2124, and a channel region located between the source region 2123 and the drain region 2124.
  • the fourth insulating layer 21210, the interlayer insulating layer 2129, and the gate insulating layer 2128 have via holes in them to expose the source region 2123 and the drain region 2124.
  • the source 2125 and the drain 2126 are electrically connected to the source region 2123 and the drain region 2124 through via holes, respectively.
  • the gate 21211 overlaps with the channel region located between the source region 2123 and the drain region 2124 in the active layer 2122 in a direction perpendicular to the base substrate 2000.
  • the first planarization layer 2130 is located above the source electrode 2125 and the drain electrode 2126 for planarizing the surface of the pixel driving circuit away from the base substrate.
  • the first planarization layer 2130 may planarize the uneven surface caused by the pixel driving circuit, and thus prevent the unevenness caused by the pixel driving circuit from causing defects in the light emitting device.
  • a first via 2131 is formed in the first planarization layer 2130 to expose the source electrode 2125 or the drain electrode 2126 (the case shown in the figure), and a first transfer electrode 2180 is formed on the first planarization layer 2130.
  • the first transfer electrode 2180 is electrically connected to the drain 2126 through the first via 2131.
  • the first transfer electrode can avoid directly forming a straight through hole with a relatively large diameter in the first planarization layer and the second planarization layer. Therefore, the quality of the electrical connection of the via is improved, and at the same time, the first transfer electrode can also be formed in the same layer as other signal lines (such as power lines, etc.), which will not lead to an increase in process steps.
  • the first connecting electrode 2180 and the second conductive pattern 23112 of the contact pad 2310 are arranged in the same layer. Therefore, the first connecting electrode 2180 and the second conductive pattern 23112 can be formed in the same layer during the preparation process, for example, the same material layer is used for patterning. The process is formed, thereby simplifying the preparation process.
  • the material of the first transfer electrode 2180 may include a metal single-layer or multi-layer structure formed of a metal material or an alloy material, such as molybdenum, aluminum, and titanium.
  • the material of the active layer 2122 may include polysilicon or oxide semiconductor (for example, indium gallium zinc oxide).
  • the material of the gate 21211 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, and titanium.
  • the multi-layer structure is a multi-metal laminated layer (such as three layers of titanium, aluminum, and titanium). Metal stack (Al/Ti/Al)).
  • the material of the source electrode 2125 and the drain electrode 2126 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, etc., for example, the multi-layer structure is a multi-metal laminated layer (such as titanium, Aluminum and titanium three-layer metal stack (Al/Ti/Al)).
  • a metal material or an alloy material such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, etc.
  • the multi-layer structure is a multi-metal laminated layer (such as titanium, Aluminum and titanium three-layer metal stack (Al/Ti/Al)).
  • Al/Ti/Al three-layer metal stack
  • the pixel driving circuit 2120 may further include a first display metal layer 2127, and the first display area metal layer 2127 and the first conductive pattern 23111 are provided in the same layer.
  • the first display metal layer 2127 includes the source 2125 and the drain 2126 of the above-mentioned thin film transistor in the pixel driving circuit.
  • the source electrode 2125 and the drain electrode 2126 are arranged in the same layer as the first conductive pattern 23111. Therefore, the source electrode 2125 and the drain electrode 2126 and the first contact pad metal layer 2215 can be formed in the same layer during the manufacturing process, for example, the same material layer is formed through a patterning process, thereby simplifying the manufacturing process and reducing the manufacturing cost of the product.
  • the second planarization layer 2190 is disposed on the side of the first transfer electrode 2180 away from the base substrate 2000, and is used to place the first transfer electrode 2180 away from the substrate 2000.
  • a flattened surface is provided on one side of the base substrate 2000.
  • a second via 2191 is formed in the second planarization layer 2190.
  • the second planarization layer 2190 and the second insulating layer 2332 are formed in the same layer. Therefore, the second planarization layer 2190 and the second insulating layer 2332 can be formed in the same layer during the preparation process, for example, the same material layer is formed by a patterning process, thereby simplifying Preparation Process.
  • the light-emitting element 2140 is formed on the second planarization layer, that is, the light-emitting element 2140 is disposed on the side of the second planarization layer 2190 away from the base substrate.
  • the light emitting element 2140 includes a first electrode 2141, a light emitting layer 2142, and a second electrode 2143.
  • the first electrode 2141 of the light-emitting element is electrically connected to the drain 2126 through the first via 2131 in the first planarization layer 2130.
  • a pixel defining layer 2144 is formed on the first electrode 2141, and the pixel defining layer 2144 includes a plurality of openings to define a plurality of pixel units.
  • Each of the plurality of openings exposes the first electrode 2141, and the light emitting layer 2142 is disposed in the plurality of openings of the pixel defining layer 2144.
  • the second electrode 2143 may be disposed in a part or the entire display area, so that it may be formed on the entire surface during the manufacturing process.
  • the first electrode 2141 may include a reflective layer
  • the second electrode 2143 may include a transparent layer or a semi-transparent layer.
  • the first electrode 2141 can reflect the light emitted from the light-emitting layer 2142, and this part of the light is emitted into the external environment through the second electrode 2143, so that the light emission rate can be improved.
  • the second electrode 2143 includes a semi-transmissive layer, some of the light reflected by the first electrode 2141 is reflected again by the second electrode 2143, so the first electrode 2141 and the second electrode 2143 form a resonance structure, so that the light emission efficiency can be improved.
  • the material of the first electrode 2141 may include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and the like.
  • the first electrode 2141 may include a metal having high reflectivity as a reflective layer, such as silver (Ag).
  • the light-emitting layer 2142 may include small molecular organic materials or polymer molecular organic materials, may be fluorescent light-emitting materials or phosphorescent light-emitting materials, may emit red, green, blue, or white light; and, as required
  • the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light-emitting layer may include quantum dot materials, for example, silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, selenium Lead fluoride quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc.
  • the particle size of the quantum dots is 2-20nm.
  • the second electrode 2143 may include various conductive materials.
  • the second electrode 2143 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
  • the material of the pixel defining layer 2144 may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic materials such as silicon oxide and silicon nitride.
  • organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic materials such as silicon oxide and silicon nitride.
  • the insulating material is not limited in the embodiment of the present disclosure.
  • the display substrate 200 further includes an encapsulation layer 2150 on the light-emitting element 2140.
  • the encapsulation layer 2150 seals the light emitting element 2140, so that the deterioration of the light emitting element 2140 caused by moisture and/or oxygen included in the environment can be reduced or prevented.
  • the encapsulation layer 2150 may be a single-layer structure or a composite layer structure.
  • the composite layer structure includes a stacked structure of an inorganic layer and an organic layer.
  • the encapsulation layer 2150 includes at least one encapsulation sublayer.
  • the encapsulation layer 2150 may include a first inorganic encapsulation layer 2151, a first organic encapsulation layer 2152, and a second inorganic encapsulation layer 2153 arranged in sequence.
  • the encapsulation layer does not cover the contact pads.
  • One layer of the encapsulation layer 2150 is provided on the same layer as the third insulating layer 2333 in the bonding peripheral area 2500.
  • One layer of the encapsulation layer 2150 and the third insulating layer 2333 can be formed by the same patterning process.
  • the material of the encapsulation layer may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resin.
  • Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water and oxygen;
  • the material of the organic encapsulation layer can be a polymer material containing a desiccant or a polymer material that can block water vapor, etc.
  • polymer resins are used to flatten the surface of the display substrate, and can relieve the stress of the first inorganic encapsulation layer and the second inorganic encapsulation layer, and can also include water-absorbing materials such as desiccant to absorb water intruding into the interior, Oxygen and other substances.
  • the barrier dam of the dam area 2102 may be arranged in the same layer as one or more of the first planarization layer, the second planarization layer, and the pixel defining layer, thereby preventing damage in the encapsulation layer.
  • the material of the blocking dam may include an organic insulating material.
  • the organic insulating material may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as polymer resin.
  • the display substrate 200 further includes a storage capacitor 2160
  • the storage capacitor 2160 may include a first capacitor electrode 2161 and a second capacitor electrode 2162.
  • the first capacitor electrode 2161 is disposed between the gate insulating layer 2128 and the interlayer insulating layer 2129
  • the second capacitor electrode 2162 is disposed between the interlayer insulating layer 2129 and the fourth insulating layer 21210.
  • the first capacitor electrode 2161 and the second capacitor electrode 2162 overlap and at least partially overlap in a direction perpendicular to the base substrate 2000.
  • the first capacitor electrode 2161 and the second capacitor electrode 2162 use the interlayer insulating layer 2129 as a dielectric material to form a storage capacitor.
  • the first storage capacitor electrode 2161 is arranged in the same layer as the gate 21211 in the pixel driving circuit 2120 and the lead 2210 in the first bonding area 2300. Therefore, the first storage capacitor electrode 2161, the gate 21211, and the lead 2210 can be prepared in the manufacturing process.
  • the same layer is formed, for example, the same material layer is formed through a patterning process, thereby simplifying the manufacturing process and reducing the manufacturing cost of the product.
  • the first capacitance electrode of the storage capacitor is still arranged in the same layer as the gate 21211, and the second capacitance electrode of the storage capacitor is the same as the source electrode 2125 and the drain electrode of the thin film transistor.
  • 2126 is arranged in the same layer (that is, it is also located in the first display metal layer 2127), whereby the first capacitor electrode and the second capacitor electrode are formed by using a stack of the interlayer insulating layer 2129 and the fourth insulating layer 21210 as a dielectric material Storage capacitor.
  • the first capacitor electrode of the storage capacitor is no longer provided in the same layer as the gate 21211, but is located between the interlayer insulating layer 2129 and the fourth insulating layer 21210 in the display area.
  • the second capacitor electrode of the storage capacitor is arranged in the same layer as the source 2125 and drain 2126 of the thin film transistor (that is, it is also located in the first display metal layer 2127), so the first capacitor electrode and the second capacitor electrode are used
  • the fourth insulating layer 21210 is used as a dielectric material to form a storage capacitor.
  • the structure of the display substrate shown in FIG. 6 is compared with the structure of the display substrate shown in FIG. 3, the difference is that: the display substrate in FIG. 6 no longer has the fifth insulating layer 11110 and the auxiliary electrode. 11120 and the display area protection layer 11130, that is, the display substrate in FIG. 6 does not have a touch function, but can also provide a touch function according to needs.
  • FIG. 7 is a schematic cross-sectional view of a display area of another display substrate provided by another embodiment of the present disclosure.
  • the sub-pixels in the display area of the display substrate may further include a pixel structure 3110 for implementing light-emitting drive and control.
  • the pixel structure 3110 includes a pixel driving circuit 3120, a first planarization layer 3130, a first transition electrode 3180, a second planarization layer 3190, and a light-emitting element 3140.
  • the pixel structure 3110 further includes a buffer layer 23121 located on the base substrate 3000
  • the pixel driving circuit 3120 may include an active layer 3122 located on the buffer layer 3121, and a gate insulating layer located on the side of the active layer 3122 away from the base substrate 3000.
  • the layer 3128, the gate 31211 on the gate insulating layer 3128, the gate 31211 on the side away from the base substrate 3000 and the source and drain electrodes (source 3125 and drain 3126 in FIG. 3) close to the side of the base substrate 3000
  • the gate electrode 31211 may be provided in the same layer as the lead wire 2210 in the first bonding region 2300. Therefore, the gate 31211 and the lead 2210 can be formed in the same layer during the manufacturing process, for example, the same material layer is used to form the same layer through a patterning process.
  • the interlayer insulating layer 3129 and the first insulating layer 2331 are provided in the same layer. Therefore, the interlayer insulating layer 3129 and the first insulating layer 2331 can be formed in the same layer in the preparation process, for example, the same material layer is formed through a patterning process.
  • the buffer layer 3121 in the display area and the bonding area buffer layer 2341 are arranged in the same layer, and the buffer layer 3121 and the bonding area buffer layer 2341 can be formed in the same layer in the manufacturing process.
  • the gate insulating layer 3128 in the display area and the bonding area gate insulating layer 2342 are provided in the same layer, and the gate insulating layer 2128 and the bonding area gate insulating layer 2342 can be formed in the same layer during the manufacturing process.
  • the buffer layer 3121 serves as a transition layer, which can prevent harmful substances in the base substrate from intruding into the interior of the display substrate, and can increase the adhesion of the film layer in the display substrate on the base substrate 3000.
  • the pixel structure 3110 further includes a passivation layer 31212 on the source electrode 3125 and the drain electrode 3126.
  • the passivation layer 31212 is located between the pixel driving circuit 3120 and the first planarization layer 3130 and includes passivation layer via holes.
  • the passivation layer 31212 can protect the source and drain electrodes of the pixel driving circuit 3130 from being corroded by water vapor.
  • the pixel driving circuit and the first transfer electrode 3180 are also electrically connected through the passivation layer via hole.
  • the structure of the display substrate shown in FIG. 7 is compared with the structure of the display substrate shown in FIG. 6, the difference is that the display substrate in FIG. 6 adds a fourth layer between the interlayer insulating layer and the source and drain electrodes.
  • the insulating layer, the fourth insulating layer is located on the side of the second capacitor electrode 2162 away from the base substrate, and is used to provide insulation protection for the second capacitor circuit electrode 2162; the display substrate in FIG. 7 adds passivation on the source and drain electrodes Layer 31212 to protect the pixel driving circuit.
  • the active layer 3122 may include a source region 3123, a drain region 3124, and a channel region located between the source region 3123 and the drain region 3124.
  • the interlayer insulating layer 3129 and the gate insulating layer 3128 have via holes to expose the source region 3123 and the drain region 3124.
  • the source 3125 and the drain 3126 are electrically connected to the source region 3123 and the drain region 3124 through via holes, respectively.
  • the gate 31211 overlaps with the channel region located between the source region 3123 and the drain region 3124 in the active layer 3122 in a direction perpendicular to the base substrate 3000.
  • the first planarization layer 3130 is located above the source electrode 3125 and the drain electrode 3126 for planarizing the surface of the pixel driving circuit away from the base substrate.
  • the first planarization layer 3130 may planarize the uneven surface caused by the pixel driving circuit, and thus prevent the unevenness caused by the pixel driving circuit from causing defects in the light emitting device.
  • a first via 3131 is formed in the first planarization layer 3130 to expose the source electrode 3125 or the drain electrode 3126 (the case shown in the figure), and a first transfer electrode 3180 is formed on the first planarization layer 3130.
  • the first transfer electrode 3180 is electrically connected to the source electrode 3125 through the first via 3131 and the passivation layer via 3131.
  • the first transfer electrode can avoid directly forming apertures in the first planarization layer and the second planarization layer A relatively large straight through hole improves the quality of the electrical connection of the via hole.
  • the first transfer electrode can also be formed in the same layer as other signal lines (such as power lines, etc.), which will not lead to an increase in process steps.
  • the source electrode 3125 and the drain electrode 3126 are arranged in the same layer as the first conductive pattern 23111. Therefore, the source electrode 3125 and the drain electrode 3126 and the first conductive pattern 23111 can be formed in the same layer during the preparation process, for example, the same material layer is used to form the same layer through a patterning process.
  • the first connecting electrode 3180 and the second conductive pattern 23112 of the contact pad 2310 are arranged in the same layer. Therefore, the first connecting electrode 3180 and the second conductive pattern 23112 can be formed in the same layer during the preparation process, for example, the same material layer is used for patterning. The process is formed, thereby simplifying the preparation process.
  • the second planarization layer 3190 is disposed on the side of the first transfer electrode 3180 away from the base substrate 3000, so as to provide the first transfer electrode 3180 away from the substrate 3000.
  • a flattened surface is provided on one side of the base substrate 3000.
  • a second via 3191 is formed in the second planarization layer 3190.
  • the second planarization layer 3190 and the second insulating layer 2332 are formed in the same layer. Therefore, the second planarization layer 3190 and the second insulating layer 2332 can be formed in the same layer in the preparation process, for example, the same material layer is formed by a patterning process, thereby simplifying Preparation Process.
  • the light-emitting element 3140 is formed on the second planarization layer, that is, the light-emitting element 3140 is disposed on the side of the second planarization layer 3190 away from the base substrate.
  • the light-emitting element 3140 includes a first electrode 3141, a light-emitting layer 3142, and a second electrode 3143.
  • the first electrode 3141 of the light-emitting element is electrically connected to the drain 3126 through the first via 3131 in the first planarization layer 3130.
  • a pixel defining layer 3144 is formed on the first electrode 3141, and the pixel defining layer 3144 includes a plurality of openings to define a plurality of pixel units.
  • Each of the plurality of openings exposes the first electrode 3141, and the light emitting layer 3142 is disposed in the plurality of openings of the pixel defining layer 3144.
  • the second electrode 3143 may be disposed in a part or the entire display area, for example, so that it may be formed on the entire surface during the manufacturing process.
  • the first electrode 3141 may include a reflective layer
  • the second electrode 3143 may include a transparent layer or a semi-transparent layer.
  • the first electrode 3141 can reflect the light emitted from the light-emitting layer 3142, and this part of the light is emitted into the external environment through the second electrode 3143, so that the light emission rate can be improved.
  • the second electrode 3143 includes a semi-transmissive layer, some of the light reflected by the first electrode 3141 is reflected again by the second electrode 3143, so the first electrode 3141 and the second electrode 3143 form a resonance structure, so that the light emission efficiency can be improved.
  • the display substrate 200 further includes an encapsulation layer 3150 on the light-emitting element 3140.
  • the encapsulation layer 3150 seals the light emitting element 3140, so that the deterioration of the light emitting element 3140 caused by moisture and/or oxygen included in the environment can be reduced or prevented.
  • the encapsulation layer 3150 may be a single-layer structure or a composite layer structure, and the composite layer structure includes a stacked structure of an inorganic layer and an organic layer.
  • the encapsulation layer 3150 includes at least one encapsulation sublayer.
  • the encapsulation layer 3150 may include a first inorganic encapsulation layer 3151, a first organic encapsulation layer 3152, and a second inorganic encapsulation layer 3153 arranged in sequence.
  • the encapsulation layer 3150 may extend to the first bonding area. In the above example, the encapsulation layer does not cover the contact pads.
  • One layer of the encapsulation layer 3150 is provided in the same layer as the third insulating layer 2333 in the bonding peripheral area 2500.
  • One layer of the encapsulation layer 3150 and the third insulating layer 2333 can be formed by the same patterning process.
  • At least one embodiment of the present disclosure provides a display device, which may include the display substrate of any one of the above-mentioned embodiments.
  • the display device may further include a flexible circuit board and a control chip.
  • the flexible circuit board is bonded to the bonding area of the display substrate, and the control chip is mounted on the flexible circuit board to be electrically connected to the display area; or, the control chip is directly bonded to the bonding area, thereby connecting to the display area. Electric connection.
  • control chip may be a central processing unit, a digital signal processor, a system chip (SoC), and so on.
  • the control chip may also include a memory, and may also include a power supply module, etc., and the functions of power supply and signal input and output are realized through separately provided wires, signal lines, and the like.
  • the control chip may also include hardware circuits and computer executable codes.
  • Hardware circuits can include conventional very large-scale integration (VLSI) circuits or gate arrays, and existing semiconductors such as logic chips, transistors, or other discrete components; hardware circuits can also include field programmable gate arrays, programmable array logic, Programmable logic equipment, etc.
  • VLSI very large-scale integration
  • the display device provided by at least one embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • At least one embodiment of the present disclosure further provides a method for preparing a display substrate.
  • the method includes: providing a base substrate, which includes a display area and a dam area at least partially surrounding the display area, and the dam area is far away from the display area.
  • the transitional area on the side of the cofferdam is far from the first bonding area, the bonding border area and the surrounding area of the bonding area.
  • the bonding boundary area is located between the first bonding area and the surrounding area of the bonding; Leads are formed in a bonding area; a plurality of contact pads are formed in the first bonding area, wherein the contact pads are formed to be electrically connected to the leads; a first insulating layer stack is formed in the bonding boundary area; The second insulating laminated layer is formed in the region, so that at least two insulating layers of the second insulating laminated layer extend into the bonding boundary region to obtain the first insulating laminated layer, and the height of the first insulating laminated layer opposite to the base substrate It is smaller than the height of the second insulating laminate layer relative to the base substrate.
  • the first insulating laminate layer is formed in the bonding boundary area, so that the height of the opposite base substrate of the first insulating laminate layer is smaller than that of the first insulating laminate layer located in the bonding peripheral area.
  • the height of the two insulating laminated layers relative to the base substrate thereby reducing the height of the film level difference in the surrounding area of the bonding, so as to reduce the risk of generating bubbles in the surrounding area of the bonding and the boundary area of the bonding, which is more helpful to complete the bonding Process, improve the product yield and reliability of the display substrate.
  • forming the second insulating laminated layer includes: forming a first insulating layer of the second insulating laminated layer located on the base substrate, and forming the first insulating layer located on the side of the first insulating layer away from the base substrate.
  • the second insulating layer of the second insulating laminated layer, the first insulating layer and the second insulating layer extend into the bonding boundary area to form the first insulating laminated layer.
  • the manufacturing method further includes: forming a pixel structure in the display area.
  • the pixel structure includes a pixel driving circuit, a first planarization layer, a first transfer electrode, a second planarization layer, and a light emitting device.
  • forming a pixel structure in the display area includes: forming a pixel drive circuit on a base substrate, wherein a thin film transistor is formed in the pixel drive circuit, and a gate, source and drain electrodes, and an interlayer insulating layer are formed in the thin film transistor.
  • the inter-insulating layer is located on the side of the gate away from the base substrate and on the side of the source and drain electrodes close to the base substrate.
  • a first planarization layer is formed on the side of the pixel driving circuit away from the base substrate to provide a first planarized surface , And a first via hole is formed in the first planarization layer, a first transfer electrode is formed on the first planarization surface, and the first transfer electrode is electrically connected to one of the source and drain electrodes through the first via hole.
  • a second planarization layer is formed on the side of the first transfer electrode away from the base substrate to provide a second planarized surface, and a second via hole is formed in the second planarized surface, and a light-emitting element is formed on the second planarized surface , And the light-emitting element is electrically connected to the first switching electrode through the second via hole.
  • forming the second insulating layer includes: depositing a first insulating material layer on the base substrate after forming the second conductive pattern of the conductive pattern stack and the pixel driving circuit; The material layer is subjected to a patterning process, so that the portion of the first insulating material layer located in the display area is formed as a second planarization layer, and a second via hole is formed in the second planarization layer, and the first insulating material layer and the first insulating material layer are removed.
  • performing a patterning process on the first insulating material layer includes: patterning the first insulating material layer using a gray tone mask or a halftone mask patterning process.
  • forming the second insulating layer includes: after forming the second conductive pattern of the conductive pattern stack and the pixel driving circuit, depositing a first insulating material layer on the base substrate, and the first insulating material
  • the layer includes a photosensitive resin; a gray tone mask or a halftone mask is used to expose the first insulating material layer, and the exposed photoresist is developed so that the portion of the first insulating material layer located in the display area is formed as The second planarization layer, and a second via hole is formed in the second planarization layer, the portion of the first insulating material layer overlapping with the second conductive pattern is removed, and the bonding boundary area of the first insulating material layer is thinned
  • a second insulating layer is formed on the part of the second insulating layer, so that the height of the second insulating layer in the bonding boundary area relative to the base substrate is smaller than the height in the bonding peripheral area, and covers the edge of the second conductive pattern.
  • the sub-pixels in the display area of the display substrate may include the pixel structure 1110.
  • the pixel structure 1110 may include a pixel driving circuit 1120, a first planarization layer 1130, a first transfer electrode 1180, a second planarization layer 1190, and a light-emitting element 1140.
  • a base substrate 1000 is provided, and the base substrate 1000 includes a display area and a first bonding area, a bonding border area, and a bonding peripheral area located on one side of the display area.
  • the buffer layer 1121 is formed in the display area of the base substrate 1000 by deposition, and the bonding area buffer layer 1341 is formed in the first bonding area.
  • the base substrate 1000 may include an organic material, for example, the organic material may be polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and
  • the base substrate 1000 may be a flexible substrate or a non-flexible substrate, which is not limited in the embodiments of the present disclosure.
  • the materials of the buffer layer 1121 and the bonding region buffer layer 1341 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the active layer 1122 is formed on the buffer layer 1121.
  • a semiconductor material layer is deposited on the base substrate 1000, and then a patterning process is performed on the semiconductor material layer to form the active layer 1122.
  • the active layer 1121 includes a source region 1123 and a drain region 1124 and a channel region between the source region 1123 and the drain region 1124.
  • the semiconductor material of the active layer 1122 may include polysilicon or oxide semiconductor (for example, indium gallium zinc oxide) or the like.
  • a gate insulating layer 1128 can be formed on the active layer 1212 by deposition or the like, and a bonding region gate insulating layer 1342 can be formed on the bonding region buffer layer 1341 of the first bonding region.
  • the material of the gate insulating layer 1128 and the gate insulating layer 1342 of the bonding region may include, for example, insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • the gate electrode 11211 and the first capacitor electrode 1161 can be formed on the gate insulating layer 1128 in the display area through a patterning process, and a plurality of strips can be formed on the base substrate 1000 in the first bonding area. ⁇ 1210 ⁇ Lead 1210.
  • the material of the gate and the first capacitor electrode may include metal materials or alloy materials such as metal materials such as molybdenum, aluminum and titanium or their alloys.
  • the multilayer structure is a multi-metal laminated layer (such as titanium, aluminum and titanium three-layer metal Stack (Al/Ti/Al)).
  • the gate electrode can be used as a mask to form a conductive source region 1123 and drain region 1124 by doping the active layer, and between the source region 1123 and the drain region 1124 The channel region is undoped due to the shielding effect of the gate.
  • an insulating material can be deposited on the base substrate by deposition or the like, an interlayer insulating layer 1129 is formed on the gate 11211, and the first The bonding area forms a first insulating layer 1331 on the plurality of leads 1210 and the bonding peripheral area 1500 and the bonding boundary area 1400 through a patterning process.
  • a first conductive pattern via 13114 is formed in the first insulating layer 1331.
  • the material of the interlayer insulating layer and the first insulating layer may include, for example, insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • a metal material layer is deposited on the base substrate of the display area, and the second capacitor electrode 1162 is formed in the portion overlapping with the first capacitor electrode 1161 through a patterning process.
  • the first capacitor electrode 1161 and the second capacitor electrode 1162 are implemented as a storage capacitor 1160.
  • the fourth insulating layer 11210 may be formed in the display area by deposition or the like.
  • the material of the fourth insulating layer 11210 may include, for example, insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. .
  • via holes are formed in the gate insulating layer 1128, the interlayer insulating layer 1129, and the fourth insulating layer 11210 to expose the source region 2123 and the drain region 2124 of the active layer 2122.
  • the source electrode 1125 and the drain electrode 1126 are formed in the display area through a patterning process, and the first conductive pattern 13111 is formed in the first bonding area.
  • the first conductive pattern 13111 is electrically connected to the lead 1210 through the first conductive via 13114 in the first insulating layer 1331.
  • an insulating material is deposited in the display area, a first planarization layer 1130 is formed through a patterning process, and a first via 1131 is formed in the first planarization layer 1130.
  • a pixel driving circuit 1120, a storage capacitor 1160, a first planarization layer 1130, and leads 1210 and a first insulating layer 1331 located in the first bonding area are formed on the display substrate.
  • a metal material layer is deposited on the base substrate.
  • a patterning process is performed on the metal material layer to form a first transfer electrode 1180 in the display area, a second conductive pattern 13112 in the first bonding area, and a marking metal layer 1350 located in the bonding boundary area.
  • the second conductive pattern 13112 covers the edge of the first conductive pattern 13111 to prevent the first conductive pattern 13111 from being corroded.
  • the materials of the first transfer electrode, the second conductive pattern, and the marking metal layer may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum, and titanium.
  • the marking metal layer 1350 may also be formed in the same layer as the first conductive pattern layer 13111, and the embodiments of the present disclosure are not limited thereto.
  • a first insulating material layer 1710 is deposited on the base substrate.
  • the first insulating material layer 2710 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • a photoresist 1720 is deposited on the first insulating material layer 1710.
  • a first mask 1730 is provided to expose the photoresist 1720.
  • the first mask 1730 includes a completely transparent area, a partially transparent area, and an opaque area.
  • the first mask 1730 includes a second light-transmitting pattern 1732 overlapping the gap between the first bonding area 1300 and the contact pad 1310, and a first light-transmitting pattern 1731 overlapping the contact pad 1310, in the bonding boundary area 1400
  • the second light-transmitting pattern 1732 is the non-light-transmitting pattern 1733 in the peripheral area 1500 of the bonding.
  • the first mask 1730 includes a first light-transmitting pattern 1731 and a non-light-transmitting pattern 1733 in the display area.
  • the first light-transmitting pattern 1731 is located in a completely light-transmitting area
  • the second light-transmitting pattern 1732 is located in a partially light-transmitting area
  • the non-light-transmitting pattern 1733 is located in an opaque area. That is, the second mask 1730 is a gray mask or a halftone mask.
  • the photoresist is a positive photoresist, and correspondingly, the light transmittance of the second light-transmitting pattern 1732 is lower than the light transmittance of the first light-transmitting pattern 1731.
  • the part of the photoresist 1720 corresponding to the first light-transmitting pattern 1731 may be completely exposed, and the part of the photoresist 1720 corresponding to the second light-transmitting pattern 1732 may be partially exposed. The portion of the photoresist 1720 corresponding to the non-light-transmitting pattern 1733 is not exposed.
  • the photoresist 1720 is developed, and the completely exposed part of the photoresist 1720 is removed, that is, in the display peripheral area, the photoresist 1720 overlapping the contact pad 1310 is removed, and the photoresist 1720 is removed.
  • the partially exposed portion of the resist 1720 is thinned, and the thickness of the unexposed portion of the photoresist 1720 is, for example, substantially unchanged.
  • the photoresist 1720 is formed as a photoresist pattern 1721 in the first bonding area.
  • the completely exposed photoresist 1720 is removed.
  • the photoresist 1720 is formed as a photoresist pattern 1722 in the display area.
  • negative photoresist can also be used, and the mask used is, for example, a mask complementary to the first mask 1730, so that the above photolithography is obtained after exposure and development.
  • the first insulating material layer 1710 in the display peripheral area and the display area is etched to remove the insulating material layer overlapping the contact pad in the first bonding area, and the second insulating material layer is formed in the display area.
  • the via hole 1191 exposes the first transfer electrode 1180.
  • an ashing process is performed to remove the partially exposed photoresist in the display peripheral area and thin the exposed photoresist to form a photoresist pattern 1721 and thin the photoresist in the display area. Resist pattern 1722. Then, using the current photoresist pattern, the remaining first insulating material layer 1710 in the first bonding region is etched and the etching thickness is controlled to form the second insulating layer 1332.
  • the second insulating layer 1332 covers the edge of the second conductive pattern 13112.
  • the height of the first insulating layer 1332 in the bonding boundary area 1400 relative to the surface of the base substrate 1000 is smaller than the height of the first insulating layer 1332 in the bonding peripheral area 1500 relative to the surface of the base substrate 1000.
  • the second insulating layer 1332 has a slope angle with respect to the base substrate, and the slope angle is, for example, about 40 degrees to 60 degrees, and for example, about 50 degrees.
  • a second planarization layer 1190 is formed in the display area to provide a planarized surface.
  • the first electrode 1141 of the light-emitting element 1140 is formed on the second planarization 1190 of the display area; the pixel defining layer 1144 is formed on the second planarization 1190 and the first electrode 1141, and the pixel defining layer 1144 is formed on the second planarization 1190 and the first electrode 1141.
  • a plurality of openings are included to define a plurality of pixel units. Each of the plurality of openings exposes the corresponding first electrode 1141.
  • the light emitting layer 1142 is formed in the plurality of openings of the pixel defining layer 1144 by, for example, an evaporation process, and then the second electrode 1143 is formed on the pixel defining layer 1144 and the light emitting layer 1142.
  • the second electrode 1143 may be formed on the pixel defining layer 1144 and the light emitting layer 1142. Part or the entire display area can be formed on the entire surface during the manufacturing process.
  • the first electrode 1141 of the light emitting element 1140 is electrically connected to the first transfer electrode 1180 through the second via 1191.
  • the material of the first electrode 1141 may include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and the like.
  • the first electrode 1141 may include a metal having high reflectivity as a reflective layer, such as silver (Ag).
  • the light-emitting layer 1142 may include small molecular organic materials or polymer molecular organic materials, which may be fluorescent light-emitting materials or phosphorescent light-emitting materials, which can emit red light, green light, blue light, or white light; and, as required
  • the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the light-emitting layer 1142 may include quantum dot materials, for example, silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, Lead selenide quantum dots, indium phosphide quantum dots and indium arsenide quantum dots, etc.
  • the particle size of the quantum dots is 2-20nm.
  • the second electrode 1143 may include various conductive materials.
  • the second electrode 1143 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
  • the material of the pixel defining layer 1144 may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic materials such as silicon oxide and silicon nitride.
  • organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic materials such as silicon oxide and silicon nitride.
  • the insulating material is not limited in the embodiment of the present disclosure.
  • an insulating material is deposited on the light emitting element 1140 in the display area, and the fifth insulating layer 11110 is formed in the display area through a patterning process.
  • the fifth insulating layer 11110 may provide a planarized surface.
  • the material of the fifth insulating layer 11110 may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic insulating materials such as silicon oxide and silicon nitride. Materials, the embodiments of the present disclosure do not limit this.
  • a metal material layer is deposited on the fifth insulating layer 11110, the auxiliary electrode 11120 is formed in the display area through a patterning process, the third conductive pattern 13113 is formed in the first bonding area, and the second insulating layer covered by the third conductive pattern 13113 The edge of 1332.
  • the metal material layer may include indium tin oxide (ITO), thereby obtaining a transparent electrode, or the material forming the auxiliary electrode 11120 may include a metal mesh, or a transparent electrode may be obtained therefrom.
  • the auxiliary electrode 11120 may be used as a touch electrode in other embodiments.
  • an insulating material is deposited on the base substrate, a display area protection layer 11130 is formed in the display area and a third insulating layer 1333 is formed in the bonding peripheral area through a patterning process.
  • the third insulating layer 2333 plays a role of sealing the first bonding area to prevent the internal structure of the first bonding area from being damaged by corrosion.
  • the material of the third insulating layer may include an organic insulating material.
  • the organic insulating material may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as polymer resin.
  • the preparation method of the display substrate shown in FIG. 3 may include FIGS. 8C to 8H, and the process shown in FIGS. 8C to 8H can refer to the relevant description of the above example.
  • the first insulating material layer 1710 may be a photosensitive resin material, such as photoresist.
  • the photosensitive resin material is a positive photoresist.
  • exposure is performed using, for example, the above-mentioned first mask 1730.
  • the first mask 1730 includes completely transparent Light zone, partial light-transmitting area and non-light-transmitting area.
  • the first mask 1730 includes a first light-transmitting pattern 1731 and a non-light-transmitting pattern 1733 in the display area.
  • the first light-transmitting pattern 1731 is located in a completely light-transmitting area
  • the second light-transmitting pattern 1732 is located in a partially light-transmitting area
  • the non-light-transmitting pattern 1733 is located in an opaque area. That is, the second mask 1730 is a gray mask or a halftone mask.
  • the photoresist is a positive photoresist, and correspondingly, the light transmittance of the second light-transmitting pattern 1732 is lower than the light transmittance of the first light-transmitting pattern 1731.
  • the part of the first insulating material layer 1710 corresponding to the first light-transmitting pattern 1731 is completely exposed, the part corresponding to the second light-transmitting pattern 1732 is partially exposed, and the non-light-transmitting pattern in the display area is partially exposed.
  • the part corresponding to 1733 has not been exposed.
  • the unexposed first insulating material layer 1710 in the display area forms a second planarization layer 1190.
  • a second insulating layer 1332 is formed on the partially exposed first insulating material layer 1710 in the first bonding region.
  • the second insulating layer 1332 covers the edge of the second conductive pattern 13112.
  • the height of the first insulating layer 1332 in the bonding boundary area 1400 relative to the surface of the base substrate 1000 is smaller than the height of the first insulating layer 1332 in the bonding peripheral area 1500 relative to the surface of the base substrate 1000.
  • the completely exposed first insulating material layer 1710 in the display area and the first bonding area is removed, forming the second via 1191 in the display area and exposing the contact pads in the first bonding area.
  • the above preparation method can also obtain the display substrate of the embodiment shown in FIG. 8H.
  • the photosensitive resin material may also be a negative photoresist.
  • the mask used is, for example, a mask complementary to the first mask 1730, so that the second mask is also formed in the display area after exposure and development.
  • the planarization layer exposes the contact pad in the first bonding area and the first insulating layer covering the periphery of the contact pad.
  • a first insulating laminate layer is formed in the bonding boundary area of the display peripheral area, so that the height of the first insulating laminate layer opposite to the base substrate is smaller than that of the second insulating laminate located in the bonding peripheral area
  • the height of the layer relative to the base substrate thereby reducing the height of the film layer difference in the surrounding area of the bonding, so as to reduce the risk of generating bubbles in the surrounding area of the bonding and the boundary area of the bonding, which is more helpful to complete the bonding process and improve Show the product yield and reliability of the substrate.
  • a manufacturing method corresponding to the display substrate shown in FIG. 7 is provided. Compared with the structure of the display substrate shown in FIG. 6 in the structure of the display substrate shown in FIG. 7, the display substrate in FIG. 7 adds a passivation layer 31212 on the source and drain electrodes to protect the pixel driving circuit.
  • a step of forming a passivation layer may be added.
  • a passivation layer film is formed to cover the source electrode 3125 and the drain electrode 3126, and then the passivation layer film is patterned to form a passivation layer via hole exposing the drain source electrode 3125 in the display area.
  • the material of the passivation layer may include an organic insulating material or an inorganic insulating material, for example, silicon nitride material. Due to its high dielectric constant and good hydrophobic function, it can well protect the pixel drive circuit from being damaged. Corroded by water vapor.
  • the flow of the method for manufacturing the display device may include more or fewer operations, and these operations may be performed sequentially or in parallel.
  • the flow of the preparation method described above includes multiple operations appearing in a specific order, it should be clearly understood that the order of the multiple operations is not limited.
  • the preparation method described above can be executed once, or can be executed multiple times according to predetermined conditions.

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Abstract

一种显示基板及其制备方法、显示装置。该显示基板(100)包括衬底基板(1000)、引线(1210)、多个接触垫(1310)、第一绝缘层叠层(1320)及第二绝缘层叠层(1330)。衬底基板(1000)包括显示区(1100)与至少部分围绕显示区的围堰区(1102)，围堰区(1102)远离显示区一侧的过渡区(1103)，过渡区(1103)远离围堰区(1102)一侧的第一邦定区(1300)以及邦定周边区(1500)；多个接触垫(1310)位于第一邦定区(1300)，被配置为与引线(1210)电连接；第一绝缘层叠层(1320)位于第一邦定区(1300)；第二绝缘层叠层(1330)位于邦定周边区(1500)，第二绝缘层叠层(330)的至少两个绝缘层延伸到第一邦定区(1300)中以得到第一绝缘层叠层(1320)，第一绝缘层叠层(1320)的在垂直于衬底基板方向上的厚度小于第二绝缘层叠层(1330)在垂直于衬底基板方向上的厚度。

Description

显示基板及其制备方法、显示装置 技术领域
本公开的实施例涉及一种显示基板及其制备方法、显示装置。
背景技术
随着有机发光二极管(Organic Light-Emitting Diode,OLED)显示装置，尤其是触控OLED显示装置的发展，消费者对于显示基触控体验的要求也越来越高。为了满足日益增长的消费者对于显示装置的厚度及触控体验的需求，显示装置的边框逐渐减小、屏占比逐渐提升以及厚度逐渐减小。
发明内容
本公开至少一实施例提供一种显示基板，包括衬底基板、引线、多个接触垫、第一绝缘层叠层及第二绝缘层叠层。衬底基板，包括显示区与至少部分围绕所述显示区的围堰区，所述围堰区远离所述显示区一侧的过渡区，所述过渡区远离所述围堰区一侧的第一邦定区以及邦定周边区，所述邦定周边区位于所述第一邦定区与所述过渡区之间；引线，位于所述第一邦定区；多个接触垫，位于所述第一邦定区，被配置为与所述引线电连接；第一绝缘层叠层，位于所述第一邦定区；第二绝缘层叠层，位于所述邦定周边区，所述第二绝缘层叠层的至少两个绝缘层延伸到所述第一邦定区中以得到所述第一绝缘层叠层，其中，所述第一绝缘层叠层的在垂直于所述衬底基板方向上的厚度小于所述第二绝缘层叠层在垂直于所述衬底基板方向上的厚度。
例如，本公开至少一实施例提供的显示基板中，多个接触垫包括多个第一接触垫以及多个第二接触垫，其中，多个所述第一接触垫排布为至少一行，所述第一接触垫和所述第二接触垫包括导电图案叠层。
例如，本公开至少一实施例提供的显示基板，第三绝缘层叠层,位于所述过渡区，所述第三绝缘层叠层包括第一绝缘层叠层子层以及第二绝缘叠层子层，所述第一绝缘层叠层子层在所述衬底基板上的正投影至少部分覆盖所述过渡区以及所述邦定周边区，所述第二绝缘层叠层子层 在所述衬底基板上的正投影至少部分覆盖所述过渡区以及所述邦定周边区。
例如，本公开至少一实施例提供的显示基板中，所述第三绝缘层叠层还包括第三绝缘层叠层子层，设置在所述第一绝缘层叠层子层以及所述第二绝缘层叠层子层之间，其中，所述第三绝缘层叠层子层在所述衬底基板的正投影与所述第一邦定区以及所述邦定周边区不交叠。
例如，本公开至少一实施例提供的显示基板中，所述至少两个绝缘层包括第一绝缘层及第二绝缘层，所述第一绝缘层位于所述衬底基板上，所述第二绝缘层位于所述第一绝缘层远离所述衬底基板的一侧，其中，所述第一绝缘层叠层子层延伸至所述邦定周边区以得到所述第一绝缘层，所述第二绝缘层叠层子层延伸至所述邦定周边区以得到所述第二绝缘层。
例如，本公开至少一实施例提供的显示基板，还包括像素结构，位于所述显示区，其中，所述像素结构包括像素驱动电路、第一平坦化层、第一转接电极、第二平坦化层以及发光元件，所述像素驱动电路包括薄膜晶体管，所述薄膜晶体管包括栅极、源漏电极及层间绝缘层，所述层间绝缘层位于所述栅极远离所述衬底基板的一侧且位于所述源漏电极靠近所述衬底基板一侧，所述第一平坦化层在所述像素驱动电路远离所述衬底基板的一侧以提供第一平坦化表面且包括第一过孔，所述第一转接电极在所述第一平坦化表面上，且通过所述第一过孔与所述薄膜晶体管的源漏电极之一电连接，所述第二平坦化层在所述第一转接电极远离所述衬底基板的一侧以提供第二平坦化表面且包括第二过孔，所述发光元件在所述第二平坦化表面上且通过所述第二过孔与所述第一转接电极电连接，其中，所述层间绝缘层与所述第一绝缘层同层设置，所述第二平坦化层与所述第二绝缘层同层设置，所述第一平坦化层与所述第三绝缘层叠层子层同层设置。
例如，本公开至少一实施例提供的显示基板中，所述第二平坦化层在垂直于衬底基板方向上的厚度与第三绝缘层叠层子层在过渡区以及所述第二绝缘层在邦定周边区沿垂直于衬底基板方向上的厚度基本相等。
例如，本公开至少一实施例提供的显示基板中，相对于所述衬底基 板,所述第二绝缘层在所述第一邦定区的高度小于所述第二绝缘层在所述邦定周边区的高度。
例如，本公开至少一实施例提供的显示基板中，所述第二绝缘层在所述邦定周边区沿垂直于衬底基板方向上的厚度与第二绝缘层叠层子层在所述过渡区沿垂直于衬底基板方向上的厚度基本相等。
例如，本公开至少一实施例提供的显示基板中，所述第一绝缘层及所述第二绝缘层延伸到所述第一邦定区中以得到所述第一绝缘层叠层。
例如，本公开至少一实施例提供的显示基板中，所述至少两个绝缘层还包括第三绝缘层，所述第三绝缘层位于所述第二绝缘层的远离所述衬底基板的一侧且被配置为在靠近多个所述接触垫的一侧露出所述第二绝缘层。
例如，本公开至少一实施例提供的显示基板中，所述显示区包括信号线，用于与所述引线电连接。
例如，本公开至少一实施例提供的显示基板中，所述导电图案叠层包括至少两个导电图案，其中，所述第一绝缘层叠层的至少一个绝缘层覆盖所述至少两个导电图案之一的边缘并且所述至少一个绝缘层的边缘被所述至少两个导电图案中另一个所覆盖。例如，本公开至少一实施例提供的显示基板中，所述导电图案叠层包括第一导电图案和第二导电图案，其中，所述第一导电图案位于所述引线远离所述衬底基板的一侧且与所述引线电连接，所述第二导电图案位于所述第一导电图案远离所述衬底基板的一侧且覆盖所述第一导电图案的边缘，其中，所述第一绝缘层叠层中的所述第二绝缘层覆盖所述第二导电图案的边缘。
例如，本公开至少一实施例提供的显示基板中，所述第一绝缘层叠层中的所述第一绝缘层位于所述第一导电图案与所述引线之间，所述第一导电图案与所述引线之间所述第一绝缘层具有第一导电图案过孔；所述第一导电图案与所述引线通过所述第一导电图案过孔电连接。
例如，本公开至少一实施例提供的显示基板中，所述像素结构还包括第一显示区金属层，其中，所述第一导电图案与所述第一显示区金属层同层设置；所述第二导电图案与所述第一转接电极同层设置。
例如，本公开至少一实施例提供的显示基板中，所述薄膜晶体管的源漏电极位于所述第一显示区金属层中。
例如，本公开至少一实施例提供的显示基板中，所述衬底基板还包括第二邦定区，所述第二邦定区位于所述第一邦定区远离所述显示区的一侧，所述第一绝缘层延伸至所述第二邦定区，所述显示基板还包括多个第三接触垫以及第二邦定区引线，多个所述第三接触垫位于所述第二邦定区并设置在所述第一绝缘层远离衬底基板的一侧，所述第三接触垫包括多个接触垫金属层，所述第二邦定区引线，位于所述第一邦定区及第二邦定区之间，并配置为连接所述第二接触垫以及所述第三接触垫。
例如，本公开至少一实施例提供的显示基板中，多个接触垫金属层包括第一接触垫金属层以及第二接触垫金属层，所述第一接触垫金属层设置在所述第一绝缘层远离所述衬底基板的一侧，所述第二接触垫金属层与所述第一接触垫金属层层叠并覆盖所述第二接触垫金属层的周边，其中，所述第一接触垫金属层与所述第一导电图案层同层设置，所述第二接触垫金属层与所述第二导电图案层同层设置。
例如，本公开至少一实施例提供的显示基板中，所述第二接触垫金属层向第一邦定区延伸以形成所述第二邦定区引线，其中，所述第二绝缘层延伸至所述第二邦定区，并覆盖所述第二邦定区引线以及所述第二接触垫金属层的边缘。
例如，本公开至少一实施例提供的显示基板中，所述第二绝缘层的位于所述第一邦定区与第二邦定区之间的部分在垂直于所述衬底基板方向上的厚度与所述第二绝缘层位于所述第一邦定区的部分在垂直于所述衬底基板方向上的厚度基本相同，所述第二绝缘层的位于所述第一邦定区域第二邦定区之间的部分在所述衬底基板上的正投影与所述第二邦定区引线在所示衬底基板上的正投影至少部分重叠。
例如，本公开至少一实施例提供的显示基板中，所述导电图案叠层还包括第三导电图案，所述第三导电图案位于所述第二导电图案远离所述衬底基板的一侧，所述第一绝缘层叠层中的所述第二绝缘层的边缘被所述第三导电图案所覆盖。
例如，本公开至少一实施例提供的显示基板中，所述多个接触垫金属层还包括第三接触垫金属层，所述第三接触垫金属层位于所述第二接触垫金属层远离衬底基板的一侧，并覆盖第二邦定区中所述第二绝缘层的边缘，其中，所述第三接触垫金属层与所述第三导电图案层同层设置。
例如，本公开至少一实施例提供的显示基板，还包括封装层、辅助电极以及显示区保护层，所述封装层至少位于所述显示区，所述封装层包括至少一层封装子层，所述辅助电极以及所述显示区保护层位于所述显示区，所述辅助电极设置在所述封装层远离衬底基板的一侧，所述显示区保护层设置在所述辅助电极远离衬底基板的一侧，其中，所述第三导电图案与所述辅助电极同层设置，所述第三绝缘层与所述显示区保护层同层设置。
例如，本公开至少一实施例提供的显示基板中，所述像素结构还包括存储电容器，所述存储电容器包括第一存储电容电极及第二存储电容电极，所述引线与所述存储电容器的第一存储电容电极及第二存储电容电极的其中之一同层设置。
例如，本公开至少一实施例提供的显示基板中，所述第一邦定区包括邦定边界区，所述邦定边界区位于所述第一邦定区与所述邦定周边区之间，所述邦定边界区还包括位于所述第一绝缘层与所述第二绝缘层之间的标记金属层，其中，所述标记金属层与所述第一导电图案及所述第二导电图案的其中之一同层设置。
本公开至少一实施例提供一种显示装置，包括如上述任一项所述的显示基板。
本公开至少一实施例提供一种显示基板的制备方法，包括：提供衬底基板，其中，包括显示区与至少部分围绕所述显示区的围堰区，所述围堰区远离所述显示区一侧的过渡区，所述过渡区远离所述围堰区一侧的第一邦定区以及邦定周边区，所述邦定周边区位于所述第一邦定区与所述过渡区之间；在所述第一邦定区中形成引线；在所述第一邦定区中形成多个接触垫，其中，所述接触垫被形成为与所述引线电连接；在所述第一邦定区中形成第一绝缘层叠层；在所述邦定周边区中形成第二绝缘层叠层，使得所述第二绝缘层叠层的至少两个绝缘层延伸到所述第一邦定区中以得到所述第一绝缘层叠层，并使得所述第一绝缘层叠层的在垂直于所述衬底基板方向上的厚度小于所述第二绝缘层叠层在垂直于所述衬底基板方向上的厚度。
例如，在本公开至少一实施例提供的制备方法中，形成所述第二绝缘层叠层包括：形成位于所述衬底基板上的所述第二绝缘层叠层的第一 绝缘层，形成位于所述第一绝缘层远离所述衬底基板的一侧的所述第二绝缘层叠层的所述第二绝缘层，其中，所述第一绝缘层及所述第二绝缘层延伸到所述第一邦定区中形成所述第一绝缘层叠层。
例如，在本公开至少一实施例提供的制备方法，还包括：在所述显示区中形成像素结构，其中，所述像素结构包括像素驱动电路、第一平坦化层、第一转接电极、第二平坦化层以及发光元件，在所述显示区中形成像素结构包括：在所述衬底基板上形成所述像素驱动电路，其中，在所述像素驱动电路中形成薄膜晶体管，在所述薄膜晶体管中形成栅极、源漏电极及层间绝缘层，所述层间绝缘层位于所述栅极远离所述衬底基板的一侧且位于源漏电极靠近所述衬底基板的一侧，在所述像素驱动电路远离所述衬底基板的一侧形成所述第一平坦化层以提供第一平坦化表面，且在所述第一平坦化层中形成第一过孔，在所述第一平坦化表面上形成第一转接电极，且所述第一转接电极通过所述第一过孔与所述源漏电极之一电连接，在所述第一转接电极远离所述衬底基板的一侧形成所述第二平坦化层以提供第二平坦化表面，且在所述第二平坦化表面中形成第二过孔，在所述第二平坦化表面上形成所述发光元件，且所述发光元件通过所述第二过孔与所述第一转接电极电连接。
例如，在本公开至少一实施例提供的制备方法中，形成所述第二绝缘层包括：在形成所述导电图案叠层的第二导电图案以及所述像素驱动电路之后，在衬底基板上沉积第一绝缘材料层；对所述第一绝缘材料层进行构图工艺，以使得所述第一绝缘材料层的位于显示区的部分形成为第二平坦化层，且在所述第二平坦化层中形成所述第二过孔，去除第一绝缘材料层的与所述第二导电图案重叠的部分，并且减薄所述第一绝缘材料层的位于所述第一邦定区的部分以形成所述第二绝缘层，以使得所述第二绝缘层在所述第一邦定区相对于所述衬底基板的高度小于在所述邦定周边区的高度，且覆盖所述第二导电图案的边缘。
例如，在本公开至少一实施例提供的制备方法中，对所述第一绝缘材料层进行构图工艺包括：使用灰色调掩模板或半色调掩模板构图工艺对所述第一绝缘材料层进行构图。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A为本公开实施例提供的一种显示基板的平面图；
图1B为本公开实施例提供的一种显示基板的第一邦定区的平面图；
图1C为本公开实施例提供的一种显示基板的过渡区的平面图；
图2A为图1B所示显示基板沿M2-N2的截面示意图；
图2B为图1A所示显示基板沿M1-N1的截面示意图；
图2C为本公开实施例提供的显示基板在图1C所示的过渡区沿C1-D1的截面示意图；
图3为图1A所示显示基板的显示区的截面示意图；
图4A为本公开实施例提供的另一种显示基板的平面图；
图4B为本公开实施例提供的另一种显示基板的第一邦定区的平面图；
图5A为图1B所示显示基板沿M4-N4的截面示意图；
图5B为图1A所示显示基板沿M3-N3的截面示意图；
图6为图4A所示显示基板的显示区的截面示意图；
图7为本公开另一实施例提供的另一种显示基板的显示区的截面示意图；及
图8A至图8K为本公开一些实施例提供的一种显示基板的制备方法的过程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限 制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
目前，如何减小显示装置的厚度以及实现更好的触控体验成为行业内研究的热点，使用柔性显示on-cell触控技术(Felxible Multi Layer On Cell Touch,FMLOC)的显示装置可以通过直接将触控传感器用传统的沉积、镀膜、曝光及刻蚀等工艺制作到显示基板上，以得到更薄的显示装置。为了更进一步提高显示装置的显示效果，提升显示装置的显示均一性，采用在显示基板中增加转接电极层的方式来减低走线的电阻，从而改善显示不均现象。
发明人在研究中注意到，上述显示装置的设计方案中，随着显示装置的膜层数量增加，显示装置的膜层叠层结构更加复杂，将引起一些其他的工艺问题。例如，在显示基板的用于邦定外部电路的邦定区中，外部电路可以包括安装芯片的柔性电路板(例如，Chip On Film,简称COF)，该柔性电路板上设置控制芯片或驱动芯片等。膜层数量的增加将导致在邦定区的边界区的膜层段差增大，进而在边界区的膜层段差处在邦定过程中容易出现较多的气泡。这些气泡会直接影响邦定区的邦定效果，严重时，可能导致邦定工艺过程中无法识别对位标记(mark)，从而无法将外部电路邦定到邦定区，降低产品良率。
针对上述问题，本公开至少一实施例提供一种显示基板及其制备方法、显示装置。
本公开至少一实施例提供的显示基板包括衬底基板、引线、多个接触垫、第一绝缘层叠层及第二绝缘层叠层。衬底基板包括显示区与至少部分围绕显示区的围堰区，围堰区远离显示区一侧的过渡区，过渡区远离围堰区一侧的第一邦定区以及邦定周边区，邦定周边区位于第一邦定区与所述过渡区之间；引线，位于第一邦定区；多个接触垫，位于第一邦定区，被配置为与引线电连接；第一绝缘层叠层，位于第一邦定区；第二绝缘层叠层，位于邦定周边区，第二绝缘层叠层的至少两个绝缘层延伸到第一邦定区中以得到第一绝缘层叠层，其中，第一绝缘层叠层的在垂直于衬底基板方向上的厚度小于 第二绝缘层叠层在垂直于衬底基板方向上的厚度。
上述实施例的显示基板中，在邦定边界区中设置第一绝缘层叠层，第一绝缘层叠层的相对衬底基板的高度小于位于邦定周边区的第二绝缘层叠层相对衬底基板的高度，进而减小邦定周边区的膜层段差的高度，以降低并对邦定周边区及邦定边界区产生气泡的风险，更有助于完成邦定工艺，提高显示基板的产品良率和可靠性。
下面，结合附图对根据本公开实施例提供的显示基板及其制备方法、显示装置进行说明。
需要说明的是，在本公开的各个附图中，为了清楚描述，基于显示基板的衬底基板建立空间直角坐标系，并以此对显示基板中的各个结构的位置进行说明。在该空间直角坐标系中，X轴和Y轴平行于衬底基板所在平面，Z轴垂直于衬底基板所在平面。
本公开至少一实施例提供一种显示基板，图1A为本公开实施例提供的一种显示基板的平面图。图1B为本公开实施例提供的一种显示基板的第一邦定区的平面图。显示基板例如用于有机发光二极管(OLED)显示装置或量子点发光二极管(QLED)显示装置。
在该实施例中，如图1A所示，显示区1100包括多个子像素以及多条信号线1101，多条信号线1101包括沿第一方向(图中X轴方向)延伸的信号线(例如栅线G)和沿第二方向(图中Y轴方向)延伸的信号线(例如数据线D。这些信号线延伸或走线到位于显示区1100至少一侧的第一邦定区，例如，信号线1101与对应的引线电连接，由此可以与第一邦定区邦定的驱动芯片、柔性电路板等电连接。信号线1101可以为像素阵列提供控制信号、数据信号、电压信号等的扫描线(栅线)、数据线、电源线、检测线等。
例如，如图1A及图1B所示，显示基板100包括衬底基板，衬底基板包括显示区1100和围绕显示区1100的显示周边区1200，该显示周边区1200包括围堰区1102以及过渡区1103，围堰区1102围绕所述显示区，过渡区1103位于显示区1100一侧。围堰区1102包括阻挡坝，该阻挡坝可以形成为一层或多层结构。衬底基板还包括位于显示区1100一侧的第一邦定区1300及邦定周边区1500。第一邦定区1300包括邦定边界区1400。邦定边界区1400位于第一邦定区1300与邦定周边区1500之间。例如，第一邦定区1300可以使用COP(Chip on Pi)技术，将集成电路芯片邦定到显示基板的柔性衬底基板(例如Pi衬底 基板)上。例如，显示周边区1200还包括位于第一邦定区1300远离显示区1100一侧的第二邦定区。该第二邦定区可以为使用FOP(FPC(Flexible Printed Circuit,柔性电路板)On Pi)双面邦定工艺的的区域。图中示出了一个第一邦定区1300，但是本公开的第一邦定区的数量不限于此。例如，如图1A及图1B所示，显示基板100还可以包括多条引线1210及多个接触垫1310，多个接触垫1310设置在第一邦定区1300中。多个接触垫1310包括多个第一接触垫1311以及多个第二接触垫1312。多个第一接触垫1311位于第一邦定区1300靠近显示区的一侧，多个第二接触垫1312位于第一邦定区1300远离显示区的一侧。多个第二接触垫1312排布为至少一行(示出一行)，多个第一接触垫1311排布为至少一行(示出一行)。这里，行的方向为第一邦定区1300面对显示区1100延伸的方向。多个第一接触垫1311以及多个第二接触垫1312也可以分别排布为多行，本公开实施例不以此为限。多条引线1210与多个接触垫1310一一对应电连接。引线1210的一端部延伸至显示区1100与显示区1100中对应的一条信号线(例如数据线)电连接，引线1210的另一端部延伸至第一邦定区1300与接触垫1310电连接。例如，引线1210例如与显示区1100中的信号线同层设置，由此可以一体形成，或者形成在不同层，由此需要通过二者之间的层间绝缘层中的过孔彼此电连接。
在本公开的示例中，第一接触垫1311以及第二接触垫1312被配置为将外部电路中的信号，例如显示信号，传送给显示区的引线。
例如，如图1A所示，显示基板100还包括多条第二邦定区引线1620及多个第三接触垫1610。多条第二邦定区引线1620与多个第三接触垫1620对应电连接，例如可以一一对应电连接，也可以多个接触垫与一条引线电连接，如多个第三接触垫1620与一条第二邦定区引线1620电连接，本实施例不做限制。第二邦定区引线1620的一端部延伸至第一邦定区1300与第二接触垫1312电连接，第二邦定区引线1620的另一端部延伸至第二邦定区1600与第三接触垫1610电连接。
在本公开的示例中，第三接触垫1620被配置为将外部电路中的信号，例如显示信号，传送给第一邦定区中的第二接触垫，然后第二接触垫将该信号传送给到显示区的引线。
例如，如图1C所示，所述过渡区1103包括第一扇出区1104、弯折区1105以及第二扇出区1106。第一扇出区1104位于过渡区1103靠近显示区1100的一 侧，第二扇出区1106位于过渡区1103靠近第一邦定区1300的一侧，弯折区位于第一扇出区1105以及第二扇出区1106之间。
图1A中的截线M1-N1穿过第一邦定区1300中的第一接触垫1311、第二接触垫1312及第二邦定区1600中的第三接触垫1610，以示出第一邦定区1300与第二邦定区1600之间的膜层变化关系。
例如，如图1B所示，在第一邦定区1300中，同一行中多个第一接触垫1311之间或第二接触垫1312之间存在间隔，多个第一接触垫1311与多个第二接触垫1312之间也存在间隔。接触垫1310包括导电图案叠层13110。如图所示，截线M2-N2穿过位于L1行的靠近邦定边界区1400的第二接触垫1312，并且穿过邦定边界区1400及邦定周边区1500，以示出第一邦定区1300、邦定边界区1400及邦定周边区1500的膜层变化关系。
在本公开的一些实施例中，在第一邦定区1300的与截线M2-N2处的膜层变化与其对称位置处的膜层变化相同，以图1B中示出的情况为例进行说明。
例如，如图1B所示，显示基板100还包括第一绝缘层叠层1320及第二绝缘层叠层1330。第一绝缘层叠层1320位于邦定边界区1400，第二绝缘层叠层1330位于邦定周边区1500。第一绝缘层叠层1320位于顶层的绝缘层延伸至第一邦定区1300，覆盖多个接触垫1310的边缘。
例如，如图1B所示，连接第二接触垫1312的引线1210在第一邦定区1300延伸经过第一接触垫1311的间隙，然后再延伸到显示区1100，从而使得接触垫1310具有更大的排列空间并且可以避免与连接第一接触垫1311的引线1210相互干扰或短路。
在其他示例中，多条引线1210也可以位于不同层中，例如用于连接第二接触垫1312的引线1210位于更靠近衬底基板的一层，而用于连接第一接触垫1311的引线1210位于相对更远离衬底基板1000的一层(但仍然在接触垫和衬底基板之间)。因此，同一层中的多条引线1210之间的间距得以加大，降低了引线的之间干扰以及短路的风险，有利于形成高像素分辨率的显示装置。而且，同一层中的多条引线1210可以在同一构图工艺中制备；不同层中的多条引线1210可以在不同构图工艺中制备。
例如，引线1210的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构。
例如，图2A为图1B所示显示基板沿M2-N2的截面示意图。如图2A所示， 接触垫1310位于引线1210背离衬底基板1000的一侧。第二绝缘层叠层1330的至少两个绝缘层延伸到邦定边界区1400中以得到第一绝缘层叠层1320。第一绝缘层叠层1320的相对于衬底基板1000的高度C3小于第二绝缘层叠层1330的相对于衬底基板1000的高度C1。进而减小邦定周边区的膜层段差的高度，以降低并对邦定周边区及邦定边界区产生气泡的风险，提高显示基板的产品良率和可靠性。
例如，衬底基板1000可以为玻璃板、石英板、金属板或树脂类板件等。例如，衬底基板的材料可以包括有机材料，例如该有机材料可以为聚酰亚胺(Pi)、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料，衬底基板1000可以为柔性基板或非柔性基板，本公开的实施例对此不作限制。
例如，如图2A所示，第二绝缘层叠层1330包括在邦定周边区1500中的第一绝缘层1331及第二绝缘层1332。第一绝缘层1331位于衬底基板1000上，第二绝缘层1332位于第一绝缘层1331远离衬底基板1000的一侧。第一绝缘层1331及第二绝缘层1332延伸到邦定边界区1400中以得到第一绝缘层叠层1320。相对于衬底基板1000，第二绝缘层1332在邦定边界区1400的高度C3小于第二绝缘层1332在邦定周边区1500的高度C2，也即，在邦定边界区1400以及在邦定周边区1500，第二绝缘层1332虽然是一体的，但是却具有不同的高度，如图所示，该高度不同的部分之间可以是连续过渡的，例如，相对于衬底基板具有坡度角，该坡度角例如约为40度～60度，又例如约为50度。需要说明的是，第二绝缘层1332的高度是指第二绝缘层1332的表面至衬底基板1000的表面的垂直距离。第二绝缘层1332在邦定边界区1400的膜层厚度，即，第二绝缘层1332的上表面与下表面之间的垂直距离的取值范围，例如可以约为1.0微米至1.4微米之间，又例如，该垂直距离的取值可以约为1.2微米。第二绝缘层1332在邦定周边区1500的膜层厚度的取值范围，例如可以约为1.8微米至2.2微米之间，又例如，该膜层厚度的取值可以约为2微米。所以，第二绝缘层1332在邦定周边区1500的高度C2与第二绝缘层1332在邦定边界区1400的高度差值H1的取值范围，例如可以约为0.4微米至1.2微米，又例如，该高度差值的取值可以约为0.8微米。邦定周边区域邦定边界区的膜层的高度差值，即膜层段差被减小，以降低并对邦定周边区及邦定边界区产生气泡的风险，提高显示基板的产品良率和可靠性。
在本公开的实施例中，“约”字表示所给定数值的变化范围，在该数值的±15％之内，例如可以为±5％，±10％等。
例如，第一绝缘层1331的材料可以包括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，或者可以包括聚酰亚胺(Pi)、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料。本公开的实施例对第一绝缘层的材料不做具体限定。第二绝缘层1332的材料可以包括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，或者可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料。本公开的实施例对第二绝缘层的材料不做具体限定。
例如，如图2A所示，第二绝缘层叠层1330的至少两个绝缘层还包括第三绝缘层1333。第三绝缘层1333位于第二绝缘层1332远离衬底基板1000的一侧且被配置为在靠近接触垫1310的一侧露出所述第二绝缘层1332。第三绝缘层1333靠近邦定边界区1320的一侧具有坡度角的侧边，并且该侧边与邦定周边区1330处的第二绝缘层1332的靠近邦定边界区1320的一侧具有的坡度角的侧边不对齐。第三绝缘层1333的侧边距离邦定边界区1320的距离大于第二绝缘层1332的侧边距离邦定边界区1320的距离。第三绝缘层距离邦定边界区的距离越大，将更有利于降低邦定边界区在邦定过程中产生气泡的风险，此外，第三绝缘层1333还可以起到对周边线路起到保护作用。第三绝缘层1333的膜层厚度可以约为3微米。第二绝缘层1332在邦定周边区1500的高度C2与第二绝缘层1332在邦定边界区1400的高度差值H1加上第三绝缘层1333的厚度即为，第二绝缘层叠层1330距离衬底基板1000的高度C1与第一绝缘层叠层1320距离衬底基板1000的高度C3的差值h1，该差值h1的取值范围，例如可以约为3.4微米至4.2微米，又例如，该差值的取值可以约为3.8微米。而在平行与衬底基板1000的方向上，上述差值h1在衬底基板上的投影所得到的距离d1的范围约在100微米与200微米之间。
例如，第三绝缘层1333的材料可以包括有机绝缘材料。有机绝缘材料可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，例如高分子树脂等。
例如，继续如图2A所示，显示基板100还包括位于衬底基板100上方的邦定区缓冲层1341及位于邦定区缓冲层1341远离衬底基板1000一侧的邦定区栅绝缘层1342。引线1210位于邦定区栅绝缘层1342上。引线1210的一端与接 触垫1311电连接。第一绝缘层1331延伸到第一邦定区位于接触垫1311与引线1210之间。
例如，接触垫的导电图案叠层包括至少两个导电图案，第一绝缘层叠层的至少一个绝缘层覆盖至少两个导电图案之一的边缘并且至少一个绝缘层的边缘被至少两个导电图案中另一个所覆盖。
例如，如图2A所示，导电图案叠层13110包括第一导电图案13111、第二导电图案13112。第一导电图案13111位于引线1210远离衬底基板1000的一侧且与引线1210电连接。第二导电图案13112位于第一导电图案13111远离衬底基板1000的一侧且覆盖第一导电图案13111的边缘，以避免第一导电图案13111被刻蚀液腐蚀。第一绝缘层1331位于第一导电图案13111与引线1210之间，使得第一导电图案13111与引线1210电绝缘。在第一绝缘层1331中形成第一导电图案过孔13114。第一导电图案13111与引线1331通过第一导电图案过孔13114电连接。第一绝缘层叠层1320中的第二绝缘层1332延伸至第一邦定区，以覆盖第二导电图案13112的边缘，以避免第二导电图案13112被腐蚀。第二导电图案13112被配置为露出第一绝缘层叠层1320，用于与外部电路的电连接。
例如，第一导电图案13111的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构。第二导电图案13112的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构。
例如，如图2A所示，导电图案叠层13110还包括第三导电图案13113。第三导电图案13113位于第二导电图案13112远离衬底基板1000的一侧，并且覆盖第一绝缘层叠层1320中的第二绝缘层1332的边缘。这里，第二绝缘层的边缘指的是第二绝缘层1332在第二导电图案13112上被断开处的边缘。
例如，第三导电图案13113的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构。
例如，如图1A图1B及2A所示，邦定边界区1400还包括位于第一绝缘层1331及第二绝缘层1332之间的标记金属层1350，用于邦定工艺过程中对外部电路的对位。标记金属层可以与第一导电图案13111或第二导电图案13112同层设置。本公开的实施例对于标记金属层的平面图案没有限制，例如可以为十字、正方形、矩形等。
例如，在本公开的一些示例中，位于第二邦定区的第三接触垫包括多个接触垫金属层，多个接触垫金属层包括第一接触垫金属层以及第二接触垫金属层，第一接触垫金属层设置在第一绝缘层远离衬底基板的一侧，第二接触垫金属层与第一接触垫金属层层叠并覆盖第二接触垫金属层的周边，其中，第一接触垫金属层与第一导电图案层同层设置，第二接触垫金属层与第二导电图案层同层设置。
例如，在本公开的一些示例中，第二接触垫金属层向第一邦定区延伸以形成第二邦定区引线，第二绝缘层延伸至第二邦定区，并覆盖第二邦定区引线以及第二接触垫金属层的边缘。
例如，在本公开的一些示例中，第二绝缘层的位于第一邦定区域第二邦定区之间的部分在垂直于衬底基板方向上的厚度与第二绝缘层位于第一邦定区的部分基板相对，第二绝缘层的位于第一邦定区域第二邦定区之间的部分在衬底基板上的正投影与第二邦定区引线在衬底基板上的正投影至少部分重叠。例如，在本公开的一些示例中，多个接触垫金属层还包括第三接触垫金属层，第三接触垫金属层位于第二接触垫金属层远离衬底基板的一侧，并覆盖第二邦定区中第二绝缘层的边缘，第三接触垫金属层与第三导电图案层同层设置。
例如，在本公开的一些示例中，图2B为图1A所示显示基板沿M1-N1的截面示意图。如图2B所示，邦定区缓冲层1341及邦定区栅绝缘层1342进一步延伸至第二邦定区1600。连接第一接触垫1311的引线1210进一步延伸至邦定边界区1500。在邦定边界区1500处的膜层叠层包括引线1210、第一绝缘层1331、第二绝缘层1332以及第三绝缘层1333。第二绝缘层1332在邦定周边区的厚度大于在第一邦定区的厚度，厚度的差值与图2A所示的H1的值大致相同。第三接触垫1610包括第一接触垫金属层1611、第二接触垫金属层1612及第三接触垫金属层1613。第一接触垫金属层1611位于邦定区栅绝缘层1342上，第一接触垫金属层1611与第一导电图案13111同层设置，因此第一接触垫金属层1611与第一导电图案13111可以采用同一构图工艺制备，以简化工艺流程。第二接触垫金属层1612位于第一接触垫金属层1611的远离衬底基板的一侧，并且覆盖第一接触垫金属层1611的边缘，以避免第一接触垫金属层1611被刻蚀液腐蚀。第一接触金属层1611靠近第一邦定区1300一侧的边缘与第二导电图案13112靠近第二邦定区1600一侧的边缘之间覆盖第二邦定区引 线1620。第二接触垫金属层1612向第一邦定区1300延伸以形成第二邦定区引线1620。第二绝缘层1332延伸至第二邦定区1600，并覆盖第二邦定区引线1620以及第二接触垫金属层1612的边缘。并且，第二接触垫金属层1612与第二导电图案13112同层设置，因此第二接触垫金属层1612与第二导电图案13112可以采用同一构图工艺制备，以简化工艺流程。位于第一邦定区1300与第二邦定区1600之间的第二绝缘层1332位于第二导电图案13112远离衬底基板1000的一侧，第二绝缘层1332延伸至第二邦定区1600并覆盖第二接触垫金属层1612的边缘，以避免第二接触垫金属层1612被腐蚀。第三接触垫金属层1613位于第二接触垫金属层1612远离衬底基板1612的一侧，且覆盖第二绝缘层1332的边缘。第三接触垫金属层1613可以与第三导电图案13113同层设置。因此，第三接触垫金属层1613与第三导电图案13113可以采用同一构图工艺制备，以简化制备工艺流程。第三接触垫金属层1613被配置为露出第二绝缘层1332，用于与外部电路的电连接。
在本公开的实施例中，“同层设置”为两个功能层(例如第一接触垫金属层与第一导电图案)在显示基板的层级结构中同层且同材料形成，即在制备工艺中，该两个结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构，例如可以在先形成该材料层后，由该材料层经过构图工艺形成。或者，在制备工艺中，该两个结构层可以由同一个材料层形成，但是通过不同的构图工艺形成所需要的图案和结构。或者，在制备工艺中，该两个结构层位于同一层上，而该两个结构层的可以由不同的材料层形成，通过同一构图工艺形成所需的图案和结构。
例如，在本公开的一些示例中，显示基板还包括第三绝缘层叠层，位于过渡区，第三绝缘层叠层包括第一绝缘层叠层子层以及第二绝缘叠层子层，第一绝缘层叠层子层在衬底基板上的正投影至少部分覆盖过渡区以及邦定周边区，第二绝缘层叠层子层在衬底基板上的正投影至少部分覆盖过渡区以及邦定周边区。
例如，在本公开的一些示例中，第三绝缘层叠层还包括第三绝缘层叠层子层，设置在第一绝缘层叠层子层以及第二绝缘层叠层子层之间，第三绝缘层叠层子层在衬底基板的正投影与第一邦定区以及邦定周边区不交叠。
例如，在本公开的一些实例中，第一绝缘层叠层子层延伸至邦定周边区以得到第一绝缘层，第二绝缘层叠层子层延伸至邦定周边区以得到第二绝缘 层。
例如，在本公开的一些实例中，第二绝缘叠层子层1108以及第三绝缘叠层子层1109分别与第一扇出区以及第二扇出区至少部分交叠。
例如，如图2C所示，第三绝缘层叠层包括第一绝缘层叠层子层1107、第二绝缘叠层子层1108以及第三绝缘叠层子层1109，第一绝缘层叠层子层1107在衬底基板1000上的正投影覆盖第一扇出区1104以及第二扇出区1106，即，第一绝缘层叠层子层1107在弯折区1105中断开。第一绝缘层叠层子层1107延伸至邦定周边区得到第一绝缘层1331，所以，第一绝缘层叠层子层与第一绝缘层同层设置。第二绝缘层叠层子层1108在衬底基板1000上的正投影覆盖第一扇出区1104、弯折区1105以及第二扇出区1106，并且延伸至邦定周边区以得到第二绝缘层1332，所以，第二绝缘层叠层子层与所述第二绝缘层同层设置。第三绝缘层叠层子层1109在衬底基板1000上的正投影覆盖第一扇出区1104、弯折区1105以及第二扇出区1106，第三绝缘层叠层子层1109与邦定周边区不交叠。
例如，如图2C所示，第三绝缘层叠层还包括过渡区缓冲层1021、过渡区栅绝缘层1028、过渡区金属层1027。过渡区缓冲层1021与邦定区缓冲层1341同层设置，过渡区栅绝缘层1028与邦定区栅绝缘层1342同层设置，过渡区金属层1027与第一导电图案13111同层设置。
例如，在本公开的一些示例中，显示基板的显示区的像素阵列中每个像素单元的子像素还可以包括像素结构。像素结构包括像素驱动电路、第一平坦化层、第一转接电极、第二平坦化层以及发光元件。第一平坦化层在像素驱动电路远离所述衬底基板的一侧以提供第一平坦化表面且包括第一过孔。第一转接电极在第一平坦化表面上，且通过第一过孔与像素驱动电路电连接。第二平坦化层在第一转接电极远离衬底基板的一侧以提供第二平坦化表面且包括第二过孔。发光元件在第二平坦化表面上且通过第二过孔与第一转接电极电连接。第二平坦化层与第二绝缘层同层设置。从而简化显示基板的制备工艺，减少产品的成本。
例如，像素驱动电路可以包括薄膜晶体管、存储电容等，可以实现为各种不同类型，例如为2T1C型(即包括两个薄膜晶体管和一个存储电容)，还可以在2T1C型的基础上进一步包括更多的晶体管和/或电容以具有补偿、复位、发光控制、检测等功能，本公开的实施例对于像素驱动电路不作限制。 例如，在一些实施例中，与发光元件直接电连接的薄膜晶体管可以为驱动晶体管或发光控制晶体管等。
例如，在本公的一些示例中，图3为图1A所示显示基板的显示区的截面示意图。如图3所示，显示基板100的显示区的子像素还可以包括像素结构1110，以用于实现发光驱动、控制。该像素结构1110包括像素驱动电路1120、第一平坦化层1130、第一转接电极1180、第二平坦化层1190及发光元件1140。
例如，像素结构1110还包括位于衬底基板1000上的缓冲层1121，像素驱动电路1120可以包括位于缓冲层1121上的有源层1122、位于有源层1122远离衬底基板1000一侧的栅绝缘层1128、位于栅绝缘层1128上的栅极11211、位于栅极11211远离衬底基板1000一侧且位于源漏电极(图3中的源极1125及漏极1126)靠近衬底基板1000一侧的层间绝缘层1129、位于层间绝缘层1129上的第四绝缘层(另一层间绝缘层)11210以及位于第四绝缘层11210上的源极1125及漏极1126。栅极11211可以与第一邦定区1300中的引线1210同层设置。因此，栅极11211和引线1210可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成。层间绝缘层1129第一绝缘层1331同层设置，因此，层间绝缘层1129和第一绝缘层1331可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成。显示区中的缓冲层1121与过渡区缓冲层1021及邦定区缓冲层1341同层设置，缓冲层1121与过渡区缓冲层1021及邦定区缓冲层1341可以在制备工艺中同层形成。显示区中的栅绝缘层1128与邦定区栅绝缘层1342及过渡区栅绝缘层1028同层设置，栅绝缘层1128与邦定区栅绝缘层1342及过渡区栅绝缘层1028可以在制备工艺中同层形成。缓冲层1121作为过渡层，其即可以防止衬底基板中的有害物质侵入显示基板的内部，又可以增加显示基板100中的膜层在衬底基板1000上的附着力。
例如，缓冲层1121的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。第四绝缘层11210、层间绝缘层1129及栅绝缘层1128中的一种或多种的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。第四绝缘层11210、层间绝缘层1129及栅绝缘层1128的材料可以相同也可以不相同。
例如，如图3所示，有源层1122可以包括源极区1123、漏极区1124以及位于源极区1123和漏极区1124之间的沟道区。第四绝缘层11210、层间绝缘层1129及栅绝缘层1128中具有过孔，以暴露源极区1123和漏极区1124。源极1125及漏极1126分别通过过孔与源极区1123和漏极区1124电连接。栅极11211 在垂直于衬底基板1000的方向上与有源层1122中位于源极区1123和漏极区1124之间的沟道区重叠。第一平坦化层1130位于源极1125及漏极1126的上方用于平坦化像素驱动电路远离衬底基板一侧的表面。第一平坦化层1130可以平坦化由像素驱动电路导致被不平坦表面，并因此防止由像素驱动电路引起的凹凸而导致在发光器件中出现缺陷。第一平坦化层1130中形成第一过孔1131，以暴露源极1125或漏极1126(图中示出的情况)，第一平坦化层1130上形成第一转接电极1180。第一转接电极1180通过第一过孔1131与漏极1126电连接，该第一转接电极可以避免直接在第一平坦化层和第二平坦化层中形成孔径比较大的直通过孔，从而改善过孔电连接的质量，同时第一转接电极还可以与其他信号线(例如电源线等)等同层形成，由此不会导致工艺步骤增加。第一转接电极1180与接触垫1310的第二导电图案13112同层设置，因此，第一转接电极2180与第二导电图案13112可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成，从而简化制备工艺。
例如，第一转接电极1180的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构。
例如，有源层1122的材料可以包括多晶硅或氧化物半导体(例如，氧化铟镓锌)。栅极11211的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Al/Ti/Al))。源极1125及漏极1126的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Al/Ti/Al))。本公开的实施例对各功能层的材料不做具体限定。
例如，在本公开的一些示例中，如图3所示，像素驱动电路1120还可以包括第一显示金属层1127，第一显示区金属层1127与第一导电图案13111同层设置。第一显示金属层2127包括像素驱动电路中上述薄膜晶体管的源极1125和漏极1126。源极1125和漏极1126与第一导电图案13111同层设置。因此，源极1125和漏极1126与第一接触垫金属层1215可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成，从而简化制备工艺，减少产品的制备成本。
例如，在本公开的一些示例中，如图3所示，第二平坦化层1190设置在第一转接电极1180远离衬底基板1000的一侧，用以在第一转接电极1180远离 衬底基板1000一侧提供平坦化表面。并且，在第二平坦化层1190中形成第二过孔1191。第二平坦化层1190与第二绝缘层1332同层形成，因此第二平坦化层1190与第二绝缘层1332可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成，从而简化制备工艺。
例如，继续如图3所示，在第二平坦化层上形成发光元件1140，即发光元件1140设置在第二平坦化层1190远离衬底基板一侧。发光元件1140包括第一电极1141、发光层1142及第二电极1143。发光元件的第一电极1141通过第一平坦化层1130中的第一过孔1131与漏极1126电连接。第一电极1141上形成像素限定层1144，像素限定层1144包括多个开口，以限定多个像素单元。多个开口的每个暴露第一电极1141，发光层1142设置在像素限定层1144的多个开口中。第二电极1143例如可以设置在部分或整个显示区域中，从而在制备工艺中可以整面形成。
例如，第一电极1141可以包括反射层，第二电极1143可以包括透明层或半透明层。由此，第一电极1141可以反射从发光层1142发射的光，该部分光通过第二电极1143发射到外界环境中，从而可以提供光出射率。当第二电极1143包括半透射层时，由第一电极1141反射的一些光通过第二电极1143再次反射，因此第一电极1141和第二电极1143形成共振结构，从而可以改善光出射效率。
例如，第一电极1141的材料可以包括至少一种透明导电氧化物材料，包括氧化锢锡(ITO)、氧化锢锌(IZO)、氧化锌(ZnO)等。此外，第一电极1141可以包括具有高反射率的金属作为反射层，诸如银(Ag)。
例如，对于OLED，发光层1142可以包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光；并且，根据需要发光层还可以进一步包括电子注入层、电子传输层、空穴注入层、空穴传输层等功能层。对于QLED，发光层可以包括量子点材料，例如，硅量子点、锗量子点、硫化镉量子点、硒化镉量子点、碲化镉量子点、硒化锌量子点、硫化铅量子点、硒化铅量子点、磷化铟量子点和砷化铟量子点等，量子点的粒径为2-20nm。
例如，第二电极1143可以包括各种导电材料。例如，第二电极1143可以包括锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。
例如，像素限定层1144的材料可以包括聚酰亚胺、聚酞亚胺、聚酞胺、 丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料，或者包括氧化硅、氮化硅等无机绝缘材料，本公开的实施例对此不做限定。
例如，如图3所示，显示基板100还包括存储电容器1160，存储电容器1160可以包括第一电容电极1161和第二电容电极1162。第一电容电极1161设置在栅绝缘层1128与层间绝缘层1129之间，第二电容电极1162设置在层间绝缘层1129与第四绝缘层11210之间。第一电容电极1161和第二电容电极1162叠置，在垂直于衬底基板1000的方向上至少部分重叠。第一电容电极1161和第二电容电极1162使用层间绝缘层1129作为介电材料来形成存储电容器。第一存储电容电极1161与像素驱动电路1120中的栅极11211、第一邦定区1200中的引线1210同层设置，因此，第一存储电容电极1161与栅极11211、引线1210可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成，从而简化制备工艺，减少产品的制备成本。
在另一示例中，作为图3所示示例的变型，存储电容器的第一电容电极仍然与栅极11211同层设置，而存储电容器的第二电容电极与薄膜晶体管中的源极1125和漏极1126同层设置(即也位于第一显示金属层1127中)，由此第一电容电极和第二电容电极使用层间绝缘层1129以及第四绝缘层11210的叠层来作为介电材料来形成存储电容器。
在再一示例中，作为图3所示示例的变型，存储电容器的第一电容电极不再与栅极11211同层设置，而是位于在显示区层间绝缘层1129与第四绝缘层11210之间，而存储电容器的第二电容电极与薄膜晶体管中的源极1125和漏极1126同层设置(即也位于第一显示金属层1127中)，由此第一电容电极和第二电容电极使用第四绝缘层11210来作为介电材料来形成存储电容器。
例如，在本公开的一些示例中，如图3所示，显示基板100还包括位于发光元件1140上的封装层1150。封装层1150将发光元件1140密封，从而可以减少或防止由环境中包括的湿气和/或氧引起的发光元件1140的劣化。封装层1150可以为单层结构，也可以为复合层结构，该复合层结构包括无机层和有机层堆叠的结构。封装层1150包括至少一层封装子层。例如，封装层1150可以包括依次设置的第一无机封装层1151、第一有机封装层1152、第二无机封装层1153。在上述示例中，该封装层未覆盖接触垫。
例如，该封装层的材料可以包括氮化硅、氧化硅、氮氧化硅、高分子树脂等绝缘材料。氮化硅、氧化硅、氮氧化硅等无机材料的致密性高，可以防 止水、氧等的侵入；有机封装层的材料可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，例如高分子树脂等以对显示基板的表面进行平坦化处理，并且可以缓解第一无机封装层和第二无机封装层的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。
例如，在本公开一些示例中，围堰区1102的阻挡坝可以与第一平坦化层、第二平坦化层以及像素限定层中的一层或多层同层设置，从而防止封装层中的有机层溢流。阻挡坝的材料可以包括有机绝缘材料。有机绝缘材料可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，例如高分子树脂等。
例如，在本公开一些示例中，如图3所示，显示基板还包括位于显示区的第五绝缘层11110、辅助导电极11120以及显示区保护层11130，。第五绝缘层11110设置在封装层1150上，以覆盖封装层1150。在本公开的实施例中，第五绝缘层11110不是必须的，在其它实施例中，也可以将第五绝缘层11110去除，以降低显示基板的厚度。辅助电极11120设置在第五绝缘层11110远离衬底基板的一侧，辅助电极11120可以用于其他辅助功能，例如触控功能，并且在一个像素结构1110上具有开口。显示区保护层11130设置在辅助电极11120的远离衬底基板的一侧，以对辅助电极11120提供保护。显示区保护层11130与第三绝缘层1333同层设置。
例如，第五绝缘层11110的材料可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料，或者包括氧化硅、氮化硅等无机绝缘材料，本公开的实施例对此不做限定。
例如，用于实现触控功能的辅助电极可以用于实现电容型触控结构，该电容型触控结构为自电容型或互电容型。自电容型触控结构包括多个阵列排布(在同一层)的自电容电极，每个自电容电极通过触控引线与触控处理电路(触控芯片)电连接。通过检测在触控时由于例如手指靠近而导致自电容电极的电容变化而实现位置检测。互电容型触控结构包括多条沿第一方向延伸的第一触控信号线和多条沿第二方向延伸的第二触控信号线，第一触控信号线和第二触控信号线均通过触控引线与触控处理电路(触控芯片)电连接。第一方向和第二方向彼此交叉并且形成开口，由此在第一触控信号线和第二触控信号线交叉位置处形成触控电容，通过检测在触控时由于例如手指靠近而导致该触控电容的变化而实现位置检测。本公开的实施例以互电容型触控 结构为例进行说明。
如图3所示，该互电容型触控结构包括相互交叉且同层设置的激励电极以及感应电极，以实现显示基板的触控功能。在该触控结构中，例如，第感应电极多个分段，而激励电极为连续的，在激励电极和感应电极彼此交叉的位置，提供与激励电极及感应电极位于不同层的桥接电极(未示出)，以将感应电极的两个相邻的分段彼此电连接。通过设置感应电极及第二激励电极可以提高显示基板触控的灵敏度。辅助电极11120与第三导电图案13113同层设置。第三导电图案13113可以与感应电极及激励电极的其中一个的材料相同，采用同一构图工艺形成。
例如，形成辅助电极11120的材料可以包括氧化锢锡(ITO)，并且由此得到透明电极，或者形成辅助电极11120的材料可以包括金属网格，也可以由此得到透明电极。例如，辅助电极11120在其它实施例中可以用作触控电极。
本公开至少一实施例还提供一种显示基板，该包括衬底基板、引线、接触垫、第一绝缘层叠层及第二绝缘层叠层。衬底基板，包括显示区与至少部分围绕显示区的显示周边区，显示周边区包括位于显示区一侧的第一邦定区、邦定边界区以及邦定周边区，邦定边界区位于第一邦定区与邦定周边区之间；引线，位于第一邦定区；接触垫，位于第一邦定区，接触垫包括至少两个导电图案，接触垫位于引线远离衬底基板的一侧且与引线电连接；第一绝缘层叠层，位于邦定边界区；第二绝缘层叠层，位于邦定周边区，第二绝缘层叠层的至少一个绝缘层延伸到邦定边界区中以得到第一绝缘层叠层，第一绝缘层叠层的至少一个绝缘层覆盖至少两个导电图案之一的边缘并且至少一个绝缘层的边缘被至少两个导电图案中另一个所覆盖。
在上述实施例提供的显示基板中，在显示周边区的邦定边界区设置第一绝缘层叠层，第一绝缘层叠层的至少一个边缘覆盖至少两个导电图案之一的边缘并且至少一个绝缘层的边缘被至少两个导电图案中另一个所覆盖，进而避免位于靠近衬底基板一侧的导电图案在制备其它膜层的过程中被刻蚀液腐蚀，还可防止导电图案中金属的脱落与剥离，更有助于完成邦定工艺，进而提高显示基板的产品良率。
本公开至少一实施例提供另一种显示基板，图4A为本公开实施例提供的另一种显示基板的平面图。图4B为本公开实施例提供的另一种显示基板的第一邦定区的平面图。显示基板例如用于有机发光二极管(OLED)显示装置 或量子点发光二极管(QLED)显示装置。
在该实施例中，如图4A所示，显示区2100包括多个子像素以及多条信号线2101，多条信号线2101包括沿第一方向(图中X轴方向)延伸的信号线(例如栅线G)和沿第二方向(图中Y轴方向)延伸的信号线(例如数据线D。这些信号线延伸或走线到位于显示区2100至少一侧的第一邦定区，例如，信号线2103与对应的引线电连接，由此可以与第一邦定区邦定的驱动芯片、柔性电路板等电连接。信号线2101可以为像素阵列提供控制信号、数据信号、电压信号等的扫描线(栅线)、数据线、电源线、检测线等。
例如，如图4A及图4B所示，显示基板200包括衬底基板，衬底基板包括显示区2100和围绕显示区2100的显示周边区2200，该显示周边区2200包括围堰区2102以及过渡区2103，围堰区2102围绕所述显示区，过渡区2103位于显示区2100一侧。围堰区2102包括阻挡坝，该阻挡坝可以形成为一层或多层结构。衬底基板还包括位于显示区2100一侧的第一邦定区2300及邦定周边区2500。第一邦定区2300包括邦定边界区2400。邦定边界区2400位于第一邦定区2300与邦定周边区2500之间。例如，第一邦定区2300可以使用COP(Chip on Pi)封装技术，将集成电路芯片邦定到显示基板的柔性衬底基板(例如Pi衬底基板)上。例如，显示周边区2200还包括位于第二邦定区2300远离显示区2100一侧的使用FOP(FPC(Flexible Printed Circuit,柔性电路板)On Pi)双面邦定工艺的第二邦定区2600。图中示出了一个第一邦定区2300，但是本公开的第一邦定区的数量不限于此。需要说明的是，在图4A所示出的过渡区2103的详细结构与膜层布置与图1A中示出的过渡区1103相同，这里将不再详细赘述。
例如，如图4A及图4B所示，显示基板200还可以包括多条引线2210及多个接触垫2310，多个接触垫2310设置在第一邦定区1300中。多个接触垫2310包括多个第一接触垫2311以及多个第二接触垫2312。多个第一接触垫2311位于第一邦定区2300靠近显示区的一侧，多个第二接触垫2312位于第一邦定区2300远离显示区的一侧。多个第二接触垫2312排布为至少一行(示出一行)，多个第一接触垫2311排布为至少一行(示出一行)。这里，行的方向为第一邦定区2300面对显示区2100延伸的方向。多个第一接触垫2311以及多个第二接触垫2312也可以分别排布为多行，本公开实施例不以此为限。多条引线2210与多个接触垫2310一一对应电连接。引线2210的一端部延伸至显示区 2100与显示区2100中对应的一条信号线(例如数据线)电连接，引线2210的另一端部延伸至第一邦定区2300与接触垫2310电连接。引线2210例如与显示区2100中的信号线同层设置，由此可以一体形成，或者形成在不同层，由此需要通过二者之间的层间绝缘层中的过孔彼此电连接。
在本公开的示例中，第一接触垫2311以及第二接触垫2312被配置为将外部电路中的信号，例如显示信号，传送给显示区的引线。
在本公开的示例中，第三接触垫2620被配置为将外部电路中的信号，例如显示信号，传送给第一邦定区中的第二接触垫，然后第二接触垫将该信号传送给到显示区的引线。
例如，如图4A所示，显示基板200还包括多条第二邦定区引线2620及多个第三接触垫2610。多条第二邦定区引线2620与多个第三接触垫2620一一对应电连接。第二邦定区引线2620的一端部延伸至第一邦定区2300与第二接触垫2311电连接，第二邦定区引线2620的另一端部延伸至第二邦定区2600与第三接触垫2610电连接。
图4A中的截线M3-N3穿过第一邦定区2300中的第一接触垫2311、第二接触垫2322及第二邦定区邦定区2600中的第三接触垫2610，以示出第一邦定区2300与第二邦定区1600之间的膜层变化关系。
例如，如图4B所示，在第一邦定区2300中，同一行中多个第一接触垫2311之间或第二接触垫2312之间存在间隔，多个第一接触垫2311与多个第二接触垫2312之间也存在间隔。接触垫2310包括导电图案叠层13110。如图所示，截线M4-N4穿过位于L3行的靠近邦定边界区2400的第二接触垫2312，并且穿过邦定边界区2400及邦定周边区2500，以示出第一邦定区2300、邦定边界区2400及邦定周边区2500的膜层变化关系。
在本公开的一些实施例中，在第一邦定区2300的与截线M4-N4处的膜层变化与其对称位置处的膜层变化相同，以图4B中示出的情况为例进行说明。
例如，如图4B所示，显示基板200还包括第一绝缘层叠层2320及第二绝缘层叠层2330。第一绝缘层叠层2320位于邦定边界区2400，第二绝缘层叠层2330位于邦定周边区2500。第一绝缘层叠层2320位于顶层的绝缘层延伸至第一邦定区2300，覆盖多个接触垫2310的边缘。
例如，如图4B所示，连接第二接触垫2312的引线2210在第一邦定区延伸经过L4行的第一接触垫2311的间隙，然后再延伸到显示区2100，从而使得接 触垫2310具有更大的排列空间并且可以避免与连接L4行的第一接触垫2311的引线2210相互干扰或短路。
在其他示例中，多条引线2210也可以位于不同层中，例如用于连接第二接触垫2312的引线2210位于更靠近衬底基板的一层，而用于连接第一接触垫2311的引线2210位于相对更远离衬底基板的一层(但仍然在接触垫和衬底基板之间)。因此，同一层中的多条引线2210之间的间距得以加大，降低了引线的之间干扰以及短路的风险，有利于形成高像素分辨率的显示装置。而且，同一层中的多条引线2210可以在同一构图工艺中制备；不同层中的多条引线2210可以在不同构图工艺中制备。
例如，引线2210的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构。
例如，图5A为图4B所示显示基板沿M4-N4的截面示意图。如图5A所示，接触垫2310位于引线2210背离衬底基板2000的一侧。第二绝缘层叠层2330的至少两个绝缘层延伸到邦定边界区2400中以得到第一绝缘层叠层2320。第一绝缘层叠层2320的相对于衬底基板2000的高度C6小于第二绝缘层叠层2330的相对于衬底基板2000的高度C4。进而减小邦定周边区的膜层段差的高度，以降低并对邦定周边区及邦定边界区产生气泡的风险，提高显示基板的产品良率和可靠性。
例如，衬底基板2000可以为玻璃板、石英板、金属板或树脂类板件等。例如，衬底基板的材料可以包括有机材料，例如该有机材料可以为聚酰亚胺(Pi)、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料，衬底基板2000可以为柔性基板或非柔性基板，本公开的实施例对此不作限制。
例如，如图5A所示，第二绝缘层叠层2330包括邦定周边区2500中的第一绝缘层2331及第二绝缘层2332。第一绝缘层2331位于衬底基板2000上，第二绝缘层2332位于第一绝缘层2331远离衬底基板2000的一侧。第一绝缘层2331及第二绝缘层2332延伸到邦定边界区2400中以得到第一绝缘层叠层2320。相对于衬底基板2000，第二绝缘层2332在邦定边界区2400的高度C6小于第二绝缘层2332在邦定周边区2500的高度C5。也即，在邦定边界区2400以及在邦定周边区2500，第二绝缘层2332虽然是一体的，但是却具有不同的高度，如图所示，该高度不同的部分之间可以是连续过渡的，例如，相对于衬底基板具 有坡度角，该坡度角例如约为40～60度，又例如约为50度。需要说明的是，第二绝缘层2332的高度是指第二绝缘层2332的表面至衬底基板2000的表面的垂直距离。第二绝缘层2332在邦定边界区2400的膜层厚度，即，第二绝缘层2332的上表面与下表面之间的垂直距离的取值范围，例如可以约为1.0微米至1.4微米之间，又例如，该垂直距离的取值可以约为1.2微米。第二绝缘层2332在邦定周边区2500的膜层厚度的取值范围，例如可以约为1.8微米至2.2微米之间，又例如，该膜层厚度的取值可以约为2微米。所以，第二绝缘层2332在邦定周边区2500的高度C2与第二绝缘层2332在邦定边界区2400的高度差值H1的取值范围，例如可以约为0.4微米至1.2微米，又例如，该高度差值的取值可以约为0.8微米。邦定周边区域邦定边界区的膜层的高度差值，即膜层段差被减小，以降低并对邦定周边区及邦定边界区产生气泡的风险，提高显示基板的产品良率和可靠性。
在本公开的实施例中，“约”字表示所给定数值的变化范围，在该数值的±15％之内，例如可以为±5％，±10％等。
例如，第一绝缘层2331的材料可以包括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，或者可以包括聚酰亚胺(Pi)、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料。本公开的实施例对第一绝缘层的材料不做具体限定。第二绝缘层2332的材料可以包括氧化硅、氮化硅、氮氧化硅等无机绝缘材料，或者可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料。本公开的实施例对第二绝缘层的材料不做具体限定。
例如，如图5A所示，第二绝缘层叠层2330的至少两个绝缘层还包括第三绝缘层2333。第三绝缘层2333位于第二绝缘层2332远离衬底基板2000的一侧且被配置为在靠近接触垫2310的一侧露出所述第二绝缘层2332。第三绝缘层2333靠近邦定边界区2320的一侧具有坡度角的侧边，并且该侧边与邦定周边区2330处的第二绝缘层2332的靠近邦定边界区2320的一侧具有的坡度角的侧边不对齐。第三绝缘层2333的侧边距离邦定边界区2320的距离大于第二绝缘层2332的侧边距离邦定边界区2320的距离。第三绝缘层距离邦定边界区的距离越大，将更有利于降低邦定边界区在邦定过程中产生气泡的风险，此外，第三绝缘层2333还可以起到对周边线路起到保护作用。第三绝缘层2333的膜层厚度可以约为3微米。第二绝缘层2332在邦定周边区2500的高度C5与第二 绝缘层2332在邦定边界区2400的高度差值H2加上第三绝缘层2333的厚度即为，第二绝缘层叠层2330距离衬底基板2000的高度C4与第一绝缘层叠层1320距离衬底基板1000的高度C6的差值h2，该差值h2的取值范围，例如可以约为3.4微米至4.2微米，又例如，该差值的取值可以约为3.8微米。而在平行与衬底基板2000的方向上，上述差值h2在衬底基板上的投影所得到的距离d2的范围约在100微米与200微米之间。
例如，第三绝缘层2333的材料可以包括有机绝缘材料。有机绝缘材料可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，例如高分子树脂等。
例如，继续如图5A所示，显示基板200还包括位于衬底基板200上方的邦定区缓冲层2341及位于邦定区缓冲层2341远离衬底基板2000一侧的邦定区栅绝缘层2342。引线2210位于邦定区栅绝缘层2242上。引线2210的一端与接触垫2310电连接。第一绝缘层2331延伸到第一邦定区位于接触垫2310与引线2210之间。
例如，接触垫的导电图案叠层包括至少两个导电图案，第一绝缘层叠层的至少一个绝缘层覆盖至少两个导电图案之一的边缘并且至少一个绝缘层的边缘被至少两个导电图案中另一个所覆盖。
例如，如图5A所示，导电图案叠层23110包括第一导电图案23111、第二导电图案23112。第一导电图案23111位于引线2210远离衬底基板2000的一侧且与引线2210电连接。第二导电图案23112位于第一导电图案23111远离衬底基板2000的一侧且覆盖第一导电图案23111的边缘，以避免第一导电图案23111被刻蚀液腐蚀。第一绝缘层2331位于第一导电图案23111与引线2210之间，使得第一导电图案23111与引线2210电绝缘。在第一绝缘层2331中形成第一导电图案过孔23114。第一导电图案23111与引线2331通过第一导电图案过孔23114电连接。第一绝缘层叠层2320中的第二绝缘层2332延伸至第一邦定区，以覆盖第二导电图案23112的边缘，以避免第二导电图案23112被腐蚀。第二导电图案23112被配置为露出第一绝缘层叠层2320，用于与外部电路的电连接。
例如，第一导电图案23111的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构。第二导电图案23112的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多 层结构。
例如，如图4A、图4B及图5A所示，邦定边界区2400还包括位于第一绝缘层2331及第二绝缘层2332之间的标记金属层2350，用于邦定工艺过程中对外部电路的对位。标记金属层2350可以与第一导电图案23111或第二导电图案23112同层设置。本公开的实施例对于标记金属层的平面图案没有限制，例如可以为十字、正方形、矩形等。
例如，在本公开的一些示例中，位于第二邦定区的第三接触垫包括多个接触垫金属层，多个接触垫金属层包括第一接触垫金属层以及第二接触垫金属层，第一接触垫金属层设置在第一绝缘层远离衬底基板的一侧，第二接触垫金属层与第一接触垫金属层层叠并覆盖第二接触垫金属层的周边，其中，第一接触垫金属层与第一导电图案层同层设置，第二接触垫金属层与第二导电图案层同层设置。
例如，在本公开的一些示例中，第二接触垫金属层向第一邦定区延伸以形成第二邦定区引线，第二绝缘层延伸至第二邦定区，并覆盖第二邦定区引线以及第二接触垫金属层的边缘。
例如，在本公开的一些示例中，第二绝缘层的位于第一邦定区与第二邦定区之间的部分在垂直于衬底基板方向上的厚度与第二绝缘层位于第一邦定区的部分在垂直于衬底基板方向上的厚度基本相同，第二绝缘层的位于第一邦定区域第二邦定区之间的部分在衬底基板上的正投影与第二邦定区引线在衬底基板上的正投影至少部分重叠。
例如，在本公开的一些示例中，图5B为图4A所示显示基板沿M1-N1的截面示意图。如图5B所示，邦定区缓冲层2341及邦定区栅绝缘层2342进一步延伸至第二邦定区2600。连接第一接触垫2311的引线2210进一步延伸至邦定边界区2500。在邦定边界区2500处的膜层叠层包括引线2210、第一绝缘层2331、第二绝缘层2332以及第三绝缘层2333。第二绝缘层2332在邦定周边区的厚度大于在第一邦定区的厚度，厚度的差值与图5A所示的H2的值大致相同。第三接触垫2610包括第一接触垫金属层2611以及第二接触垫金属层2612。第一接触垫金属层2611位于邦定区栅绝缘层2342上，第一接触垫金属层2611与第一导电图案23111同层设置，因此第一接触垫金属层2611与第一导电图案23111可以采用同一构图工艺制备，以简化工艺流程。第二接触垫金属层2612位于第一接触垫金属层2611的远离衬底基板的一侧，并且覆盖第 一接触垫金属层2611的边缘，以避免第一接触垫金属层2611被刻蚀液腐蚀。第一接触金属层1611靠近第一邦定区2300一侧的边缘与第二导电图案13112靠近第二邦定区2600一侧的边缘之间覆盖第二邦定区引线2620。第二接触垫金属层2612向第一邦定区2300延伸以形成第二邦定区引线2620。第二绝缘层2332延伸至第二邦定区2600，并覆盖第二邦定区引线2620以及第二接触垫金属层2612的边缘。并且，第二接触垫金属层2612与第二导电图案23112同层设置，因此第二接触垫金属层2612与第二导电图案23112可以采用同一构图工艺制备，以简化工艺流程。位于第一邦定区2300与第二邦定区2600之间的第二绝缘层2332位于第二导电图案23112远离衬底基板2000的一侧，第二绝缘层2332延伸至第二邦定区2600并覆盖第二接触垫金属层2612，以避免第二接触垫金属层2612被腐蚀。第二接触垫金属层2612被配置为露出第二绝缘层2332，用于与外部电路的电连接。
在本公开的实施例中，“同层设置”为两个功能层(例如第一接触垫金属层与第一导电图案)在显示基板的层级结构中同层且同材料形成，即在制备工艺中，该两个结构层可以由同一个材料层形成，且可以通过同一构图工艺形成所需要的图案和结构，例如可以在先形成该材料层后，由该材料层经过构图工艺形成。或者，在制备工艺中，该两个结构层可以由同一个材料层形成，但是通过不同的构图工艺形成所需要的图案和结构。或者，在制备工艺中，该两个结构层位于同一层上，而该两个结构层的可以由不同的材料层形成，通过同一构图工艺形成所需的图案和结构。
例如，在本公开的一些示例中，显示基板的显示区的像素阵列中每个像素单元的子像素还可以包括像素结构。像素结构包括像素驱动电路、第一平坦化层、第一转接电极、第二平坦化层以及发光元件。第一平坦化层在像素驱动电路远离所述衬底基板的一侧以提供第一平坦化表面且包括第一过孔。第一转接电极在第一平坦化表面上，且通过第一过孔与像素驱动电路电连接。第二平坦化层在第一转接电极远离衬底基板的一侧以提供第二平坦化表面且包括第二过孔。发光元件在第二平坦化表面上且通过第二过孔与第一转接电极电连接。第二平坦化层与第二绝缘层同层设置。从而简化显示基板的制备工艺，减少产品的成本。
例如，像素驱动电路可以包括薄膜晶体管、存储电容等，可以实现为各种不同类型，例如为2T1C型(即包括两个薄膜晶体管和一个存储电容)，还 可以在2T1C型的基础上进一步包括更多的晶体管和/或电容以具有补偿、复位、发光控制、检测等功能，本公开的实施例对于像素驱动电路不作限制。例如，在一些实施例中，与发光元件直接电连接的薄膜晶体管可以为驱动晶体管或发光控制晶体管等。
例如，在本公的一些示例中，图6为图4A所示显示基板的显示区的截面示意图。如图6所示，显示基板200的显示区的子像素还可以包括像素结构2110，以用于实现发光驱动、控制。该像素结构2110包括像素驱动电路2120、第一平坦化层2130、第一转接电极2180、第二平坦化层2190及发光元件2140。
例如，像素结构2110还包括位于衬底基板2000上的缓冲层2121，像素驱动电路2120可以包括位于缓冲层2121上的有源层2122、位于有源层2122远离衬底基板2000一侧的栅绝缘层2128、位于栅绝缘层2128上的栅极21211、位于栅极21211远离衬底基板2000一侧且位于源漏电极(图3中的源极2125及漏极2126)靠近衬底基板2000一侧的层间绝缘层2129、位于层间绝缘层2129上的第四绝缘层(另一层间绝缘层)21210以及位于第四绝缘层21210上的源极2125及漏极2126。栅极21211可以与第一邦定区2300中的引线2210同层设置。因此，栅极21211和引线2210可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成。层间绝缘层2129与第一绝缘层2331同层设置，因此，层间绝缘层2129和第一绝缘层2331可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成。显示区中的缓冲层2121与邦定区缓冲层2341同层设置，缓冲层2121与邦定区缓冲层2341可以在制备工艺中同层形成。显示区中的栅绝缘层2128与邦定区栅绝缘层2342同层设置，栅绝缘层2128与邦定区栅绝缘层2342可以在制备工艺中同层形成。缓冲层2121作为过渡层，其即可以防止衬底基板中的有害物质侵入显示基板的内部，又可以增加显示基板200中的膜层在衬底基板2000上的附着力。
例如，缓冲层2121的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。第四绝缘层21210、层间绝缘层2129及栅绝缘层2128中的一种或多种的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。第四绝缘层21210、层间绝缘层2129及栅绝缘层2128的材料可以相同也可以不相同。
例如，如图6所示，有源层2122可以包括源极区2123、漏极区2124以及位于源极区2123和漏极区2124之间的沟道区。第四绝缘层21210、层间绝缘层2129及栅绝缘层2128中具有过孔，以暴露源极区2123和漏极区2124。源极 2125及漏极2126分别通过过孔与源极区2123和漏极区2124电连接。栅极21211在垂直于衬底基板2000的方向上与有源层2122中位于源极区2123和漏极区2124之间的沟道区重叠。第一平坦化层2130位于源极2125及漏极2126的上方用于平坦化像素驱动电路远离衬底基板一侧的表面。第一平坦化层2130可以平坦化由像素驱动电路导致被不平坦表面，并因此防止由像素驱动电路引起的凹凸而导致在发光器件中出现缺陷。第一平坦化层2130中形成第一过孔2131，以暴露源极2125或漏极2126(图中示出的情况)，第一平坦化层2130上形成第一转接电极2180。第一转接电极2180通过第一过孔2131与漏极2126电连接，该第一转接电极可以避免直接在第一平坦化层和第二平坦化层中形成孔径比较大的直通过孔，从而改善过孔电连接的质量，同时第一转接电极还可以与其他信号线(例如电源线等)等同层形成，由此不会导致工艺步骤增加。第一转接电极2180与接触垫2310的第二导电图案23112同层设置，因此，第一转接电极2180与第二导电图案23112可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成，从而简化制备工艺。
例如，第一转接电极2180的材料可以包括包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构。
例如，有源层2122的材料可以包括多晶硅或氧化物半导体(例如，氧化铟镓锌)。栅极21211的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Al/Ti/Al))。源极2125及漏极2126的材料可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Al/Ti/Al))。本公开的实施例对各功能层的材料不做具体限定。
例如，在本公开的一些示例中，如图6所示，像素驱动电路2120还可以包括第一显示金属层2127，第一显示区金属层2127与第一导电图案23111同层设置。第一显示金属层2127包括像素驱动电路中上述薄膜晶体管的源极2125和漏极2126。源极2125和漏极2126与第一导电图案23111同层设置。因此，源极2125和漏极2126与第一接触垫金属层2215可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成，从而简化制备工艺，减少产品的制备成本。
例如，在本公开的一些示例中，如图6所示，第二平坦化层2190设置在 第一转接电极2180远离衬底基板2000的一侧，用以在第一转接电极2180远离衬底基板2000一侧提供平坦化表面。并且，在第二平坦化层2190中形成第二过孔2191。第二平坦化层2190与第二绝缘层2332同层形成，因此第二平坦化层2190与第二绝缘层2332可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成，从而简化制备工艺。
例如，继续如图6所示，在第二平坦化层上形成发光元件2140，即发光元件2140设置在第二平坦化层2190远离衬底基板一侧。发光元件2140包括第一电极2141、发光层2142及第二电极2143。发光元件的第一电极2141通过第一平坦化层2130中的第一过孔2131与漏极2126电连接。第一电极2141上形成像素限定层2144，像素限定层2144包括多个开口，以限定多个像素单元。多个开口的每个暴露第一电极2141，发光层2142设置在像素限定层2144的多个开口中。第二电极2143例如可以设置在部分或整个显示区域中，从而在制备工艺中可以整面形成。
例如，第一电极2141可以包括反射层，第二电极2143可以包括透明层或半透明层。由此，第一电极2141可以反射从发光层2142发射的光，该部分光通过第二电极2143发射到外界环境中，从而可以提供光出射率。当第二电极2143包括半透射层时，由第一电极2141反射的一些光通过第二电极2143再次反射，因此第一电极2141和第二电极2143形成共振结构，从而可以改善光出射效率。
例如，第一电极2141的材料可以包括至少一种透明导电氧化物材料，包括氧化锢锡(ITO)、氧化锢锌(IZO)、氧化锌(ZnO)等。此外，第一电极2141可以包括具有高反射率的金属作为反射层，诸如银(Ag)。
例如，对于OLED，发光层2142可以包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光；并且，根据需要发光层还可以进一步包括电子注入层、电子传输层、空穴注入层、空穴传输层等功能层。对于QLED，发光层可以包括量子点材料，例如，硅量子点、锗量子点、硫化镉量子点、硒化镉量子点、碲化镉量子点、硒化锌量子点、硫化铅量子点、硒化铅量子点、磷化铟量子点和砷化铟量子点等，量子点的粒径为2-20nm。
例如，第二电极2143可以包括各种导电材料。例如，第二电极2143可以包括锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。
例如，像素限定层2144的材料可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料，或者包括氧化硅、氮化硅等无机绝缘材料，本公开的实施例对此不做限定。
例如，继续如图6所示，在至少一个示例中，显示基板200还包括位于发光元件2140上的封装层2150。封装层2150将发光元件2140密封，从而可以减少或防止由环境中包括的湿气和/或氧引起的发光元件2140的劣化。封装层2150可以为单层结构，也可以为复合层结构，该复合层结构包括无机层和有机层堆叠的结构。封装层2150包括至少一层封装子层。例如，封装层2150可以包括依次设置的第一无机封装层2151、第一有机封装层2152、第二无机封装层2153。在上述示例中，该封装层未覆盖接触垫。封装层2150中的一层与邦定周边区2500中的第三绝缘层2333同层设置。封装层2150中的一层与第三绝缘层2333可以采用同一构图工艺形成。
例如，该封装层的材料可以包括氮化硅、氧化硅、氮氧化硅、高分子树脂等绝缘材料。氮化硅、氧化硅、氮氧化硅等无机材料的致密性高，可以防止水、氧等的侵入；有机封装层的材料可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，例如高分子树脂等以对显示基板的表面进行平坦化处理，并且可以缓解第一无机封装层和第二无机封装层的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。
例如，在本公开一些示例中，围堰区2102的阻挡坝可以与第一平坦化层、第二平坦化层以及像素限定层中的一层或多层同层设置，从而防止封装层中的有机层溢流。阻挡坝的材料可以包括有机绝缘材料。有机绝缘材料可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，例如高分子树脂等。
例如，如图6所示，显示基板200还包括存储电容器2160，存储电容器2160可以包括第一电容电极2161和第二电容电极2162。第一电容电极2161设置在栅绝缘层2128与层间绝缘层2129之间，第二电容电极2162设置在层间绝缘层2129与第四绝缘层21210之间。第一电容电极2161和第二电容电极2162叠置，在垂直于衬底基板2000的方向上至少部分重叠。第一电容电极2161和第二电容电极2162使用层间绝缘层2129作为介电材料来形成存储电容器。第一存储电容电极2161与像素驱动电路2120中的栅极21211、第一邦定区2300中的引线2210同层设置，因此，第一存储电容电极2161与栅极21211、引线2210可 以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成，从而简化制备工艺，减少产品的制备成本。
在另一示例中，作为图6所示示例的变型，存储电容器的第一电容电极仍然与栅极21211同层设置，而存储电容器的第二电容电极与薄膜晶体管中的源极2125和漏极2126同层设置(即也位于第一显示金属层2127中)，由此第一电容电极和第二电容电极使用层间绝缘层2129以及第四绝缘层21210的叠层来作为介电材料来形成存储电容器。
在再一示例中，作为图6所示示例的变型，存储电容器的第一电容电极不再与栅极21211同层设置，而是位于在显示区层间绝缘层2129与第四绝缘层21210之间，而存储电容器的第二电容电极与薄膜晶体管中的源极2125和漏极2126同层设置(即也位于第一显示金属层2127中)，由此第一电容电极和第二电容电极使用第四绝缘层21210来作为介电材料来形成存储电容器。
需要说明的是，图6中所示的显示基板的结构与图3中所示显示基板的结构相比，区别点在于：图6中的显示基板中不再设置第五绝缘层11110、辅助电极11120以及显示区保护层11130，也即，图6中的显示基板不具备触控功能，但是根据需要，也可以提供触控功能。
例如，在本公开至少一实施例提供另一中显示基板。图7为本公开另一实施例提供的另一种显示基板的显示区的截面示意图。如图7所示，显示基板的显示区的子像素还可以包括像素结构3110，以用于实现发光驱动、控制。该像素结构3110包括像素驱动电路3120、第一平坦化层3130、第一转接电极3180、第二平坦化层3190及发光元件3140。
例如，像素结构3110还包括位于衬底基板3000上的缓冲层23121，像素驱动电路3120可以包括位于缓冲层3121上的有源层3122、位于有源层3122远离衬底基板3000一侧的栅绝缘层3128、位于栅绝缘层3128上的栅极31211、位于栅极31211远离衬底基板3000一侧且位于源漏电极(图3中的源极3125及漏极3126)靠近衬底基板3000一侧的层间绝缘层3129以及位于层间绝缘层3129上的源极3125及漏极3126。栅极31211可以与第一邦定区2300中的引线2210同层设置。因此，栅极31211和引线2210可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成。层间绝缘层3129与第一绝缘层2331同层设置，因此，层间绝缘层3129和第一绝缘层2331可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成。显示区中的缓冲层3121与邦 定区缓冲层2341同层设置，缓冲层3121与邦定区缓冲层2341可以在制备工艺中同层形成。显示区中的栅绝缘层3128与邦定区栅绝缘层2342同层设置，栅绝缘层2128与邦定区栅绝缘层2342可以在制备工艺中同层形成。缓冲层3121作为过渡层，其即可以防止衬底基板中的有害物质侵入显示基板的内部，又可以增加显示基板中的膜层在衬底基板3000上的附着力。
例如，如图7所示，像素结构3110还包括以及位于源极3125及漏极3126上的钝化层31212。钝化层31212位于像素驱动电路3120与第一平坦化层3130之间且包括钝化层过孔。钝化层31212可以保护像素驱动电路3130的源漏电极不被水汽腐蚀。像素驱动电路和第一转接电极3180还通过钝化层过孔电连接。
例如，图7中所示的显示基板的结构与图6中所示的显示基板的结构相比，区别在于，图6中的显示基板在层间绝缘层与源漏电极之间增加了第四绝缘层，第四绝缘层位于第二电容电极2162的远离衬底基板的一侧，用于对第二电容电路电极2162提供绝缘保护；图7中的显示基板增加位于源漏电极上的钝化层31212以保护像素驱动电路。
例如，如图7所示，有源层3122可以包括源极区3123、漏极区3124以及位于源极区3123和漏极区3124之间的沟道区。层间绝缘层3129及栅绝缘层3128中具有过孔，以暴露源极区3123和漏极区3124。源极3125及漏极3126分别通过过孔与源极区3123和漏极区3124电连接。栅极31211在垂直于衬底基板3000的方向上与有源层3122中位于源极区3123和漏极区3124之间的沟道区重叠。第一平坦化层3130位于源极3125及漏极3126的上方用于平坦化像素驱动电路远离衬底基板一侧的表面。第一平坦化层3130可以平坦化由像素驱动电路导致被不平坦表面，并因此防止由像素驱动电路引起的凹凸而导致在发光器件中出现缺陷。第一平坦化层3130中形成第一过孔3131，以暴露源极3125或漏极3126(图中示出的情况)，第一平坦化层3130上形成第一转接电极3180。第一转接电极3180通过第一过孔3131及钝化层过孔3131与源极3125电连接，该第一转接电极可以避免直接在第一平坦化层和第二平坦化层中形成孔径比较大的直通过孔，从而改善过孔电连接的质量，同时第一转接电极还可以与其他信号线(例如电源线等)等同层形成，由此不会导致工艺步骤增加。源极3125和漏极3126与第一导电图案23111同层设置。因此，源极3125和漏极3126与第一导电图案23111可以在制备工艺中同层形成，例如采用同 一材料层通过构图工艺形成。第一转接电极3180与接触垫2310的第二导电图案23112同层设置，因此，第一转接电极3180与第二导电图案23112可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成，从而简化制备工艺。
例如，在本公开的一些示例中，如图7所示，第二平坦化层3190设置在第一转接电极3180远离衬底基板3000的一侧，用以在第一转接电极3180远离衬底基板3000一侧提供平坦化表面。并且，在第二平坦化层3190中形成第二过孔3191。第二平坦化层3190与第二绝缘层2332同层形成，因此第二平坦化层3190与第二绝缘层2332可以在制备工艺中同层形成，例如采用同一材料层通过构图工艺形成，从而简化制备工艺。
例如，继续如图7所示，在第二平坦化层上形成发光元件3140，即发光元件3140设置在第二平坦化层3190远离衬底基板一侧。发光元件3140包括第一电极3141、发光层3142及第二电极3143。发光元件的第一电极3141通过第一平坦化层3130中的第一过孔3131与漏极3126电连接。第一电极3141上形成像素限定层3144，像素限定层3144包括多个开口，以限定多个像素单元。多个开口的每个暴露第一电极3141，发光层3142设置在像素限定层3144的多个开口中。第二电极3143例如可以设置在部分或整个显示区域中，从而在制备工艺中可以整面形成。
例如，第一电极3141可以包括反射层，第二电极3143可以包括透明层或半透明层。由此，第一电极3141可以反射从发光层3142发射的光，该部分光通过第二电极3143发射到外界环境中，从而可以提供光出射率。当第二电极3143包括半透射层时，由第一电极3141反射的一些光通过第二电极3143再次反射，因此第一电极3141和第二电极3143形成共振结构，从而可以改善光出射效率。
例如，继续如图7所示，在至少一个示例中，显示基板200还包括位于发光元件3140上的封装层3150。封装层3150将发光元件3140密封，从而可以减少或防止由环境中包括的湿气和/或氧引起的发光元件3140的劣化。封装层3150可以为单层结构，也可以为复合层结构，该复合层结构包括无机层和有机层堆叠的结构。封装层3150包括至少一层封装子层。例如，封装层3150可以包括依次设置的第一无机封装层3151、第一有机封装层3152、第二无机封装层3153。封装层3150可以延伸至第一邦定区，在上述示例中，该封装层未 覆盖接触垫。封装层3150中的一层与邦定周边区2500中的第三绝缘层2333同层设置。封装层3150中的一层与第三绝缘层2333可以采用同一构图工艺形成。
需要说明的是，图7中的显示基板与图6中显示基板相同的膜层结构的材料将不再详细赘述。
本公开至少一个实施例提供一种显示装置，该显示装置可以包括上述任一实施例的显示基板。
例如，在一些示例中，显示装置还可以包括柔性电路板及控制芯片。例如，柔性电路板邦定到显示基板的邦定区，而控制芯片安装在柔性电路板上，由此与显示区电连接；或者，控制芯片直接邦定到邦定区，由此与显示区电连接。
例如，控制芯片可以为中央处理器、数字信号处理器、系统芯片(SoC)等。例如，控制芯片还可以包括存储器，还可以包括电源模块等，且通过另外设置的导线、信号线等实现供电以及信号输入输出功能。例如，控制芯片还可以包括硬件电路以及计算机可执行代码等。硬件电路可以包括常规的超大规模集成(VLSI)电路或者门阵列以及诸如逻辑芯片、晶体管之类的现有半导体或者其它分立的元件；硬件电路还可以包括现场可编程门阵列、可编程阵列逻辑、可编程逻辑设备等。
例如，本公开至少一个实施例提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开至少一个实施例还提供一种显示基板的制备方法，该方法包括：提供衬底基板，其中，包括显示区与至少部分围绕所述显示区的围堰区，围堰区远离显示区一侧的过渡区，过渡区远离围堰区一侧的第一邦定区、邦定边界区以及邦定周边区，邦定边界区位于第一邦定区与邦定周边区之间；在第一邦定区中形成引线；在第一邦定区中形成多个接触垫，其中，接触垫被形成为与引线电连接；在邦定边界区中形成第一绝缘层叠层；在邦定周边区中形成第二绝缘层叠层，使得第二绝缘层叠层的至少两个绝缘层延伸到邦定边界区中以得到第一绝缘层叠层，并使得第一绝缘层叠层的相对衬底基板的高度小于第二绝缘层叠层相对衬底基板的高度。
例如，在利用上述实施例的制备方法获得的显示基板中，在邦定边界区 中形成第一绝缘层叠层，使得第一绝缘层叠层的相对衬底基板的高度小于位于邦定周边区的第二绝缘层叠层相对衬底基板的高度，进而减小邦定周边区的膜层段差的高度，以降低并对邦定周边区及邦定边界区产生气泡的风险，更有助于完成邦定工艺，提高显示基板的产品良率和可靠性。
例如，在本公开的一些示例中，形成第二绝缘层叠层包括：形成位于衬底基板上的第二绝缘层叠层的第一绝缘层，形成位于第一绝缘层远离衬底基板的一侧的第二绝缘层叠层的第二绝缘层，第一绝缘层及第二绝缘层延伸到邦定边界区中形成第一绝缘层叠层。
例如，在本公开的一些示例中，该制备方法还包括：在显示区中形成像素结构，像素结构包括像素驱动电路、第一平坦化层、第一转接电极、第二平坦化层以及发光元件，在显示区中形成像素结构包括：在衬底基板上形成像素驱动电路，其中，在像素驱动电路中形成薄膜晶体管，在薄膜晶体管中形成栅极、源漏电极及层间绝缘层，层间绝缘层位于栅极远离衬底基板的一侧且位于源漏电极靠近衬底基板的一侧，在像素驱动电路远离衬底基板的一侧形成第一平坦化层以提供第一平坦化表面，且在第一平坦化层中形成第一过孔，在第一平坦化表面上形成第一转接电极，且第一转接电极通过第一过孔与源漏电极之一电连接，在第一转接电极远离衬底基板的一侧形成第二平坦化层以提供第二平坦化表面，且在第二平坦化表面中形成第二过孔，在第二平坦化表面上形成发光元件，且发光元件通过第二过孔与第一转接电极电连接。
例如，在本公开的一些示例中，形成第二绝缘层包括：在形成导电图案叠层的第二导电图案以及像素驱动电路之后，在衬底基板上沉积第一绝缘材料层；对第一绝缘材料层进行构图工艺，以使得第一绝缘材料层的位于显示区的部分形成为第二平坦化层，且在第二平坦化层中形成第二过孔，去除第一绝缘材料层的与第二导电图案重叠的部分，并且减薄第一绝缘材料层的位于邦定边界区的部分以形成第二绝缘层，以使得第二绝缘层在邦定边界区相对于衬底基板的高度小于在邦定周边区的高度，且覆盖第二导电图案的边缘。
例如，在本公开的一些示例中，对第一绝缘材料层进行构图工艺包括：使用灰色调掩模板或半色调掩模板构图工艺对第一绝缘材料层进行构图。
例如，在本公开的一些示例中，形成第二绝缘层包括：在形成导电图案 叠层的第二导电图案以及像素驱动电路之后，在衬底基板上沉积第一绝缘材料层，第一绝缘材料层包括光敏树脂；使用灰色调掩模板或半色调掩模板对第一绝缘材料层进行曝光，对曝光之后的光刻胶进行显影后，以使得第一绝缘材料层的位于显示区的部分形成为第二平坦化层，且在第二平坦化层中形成第二过孔，去除第一绝缘材料层的与第二导电图案重叠的部分，并且减薄第一绝缘材料层的位于邦定边界区的部分以形成第二绝缘层，以使得第二绝缘层在邦定边界区相对于衬底基板的高度小于在邦定周边区的高度，且覆盖第二导电图案的边缘。
下面，以制备图3所示的显示基板为例，结合图8A至图8K详细介绍本公开实施例中显示基板的制作方法。
例如，显示基板的显示区中的子像素可以包括像素结构1110。像素结构1110可以包括像素驱动电路1120、第一平坦化层1130、第一转接电极1180、第二平坦化层1190及发光元件1140。
例如，提供衬底基板1000，该衬底基板1000包括显示区和位于显示区一侧的第一邦定区、邦定边界区及邦定周边区。例如，在衬底基板1000的显示区通过沉积方式形成缓冲层1121，同时在第一邦定区形成邦定区缓冲层1341。
例如，衬底基板1000可以包括有机材料，例如该有机材料可以为聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料，衬底基板1000可以为柔性基板或非柔性基板，本公开的实施例对此不作限制。
例如，缓冲层1121及邦定区缓冲层1341的材料可以包括氧化硅、氮化硅、氧氮化硅等绝缘材料。
例如，在缓冲层1121上形成有源层1122。例如，在衬底基板1000上沉积半导体材料层，然后对半导体材料层进行构图工艺形成有源层1122。有源层1121包括源极区1123和漏极区1124以及源极区1123和漏极区1124之间的沟道区。
例如，有源层1122的半导体材料可以包括多晶硅或氧化物半导体(例如，氧化铟镓锌)等。
例如，在有源层1122形成后，可以通过沉积等方式在有源层1212上形成栅绝缘层1128，在第一邦定区的邦定区缓冲层1341上形成邦定区栅绝缘层 1342。栅绝缘层1128及邦定区栅绝缘层1342的材料例如可以包括氧化硅、氮化硅、氧氮化硅等绝缘材料。
例如，在栅绝缘层1128形成后，可以通过构图工艺在显示区的栅绝缘层1128上形成栅极11211及第一电容电极1161，并且在第一邦定区的衬底基板1000上形成多条引线1210。栅极及第一电容电极的材料可以包括金属材料或者合金材料例如钼、铝及钛等金属材料或其合金，例如，该多层结构为多金属层叠层(如钛、铝及钛三层金属叠层(Al/Ti/Al))。
在一些示例中，可以使用栅极进行作为掩膜，通过对有源层进行掺杂以形成导电的源极区1123及漏极区1124，而在源极区1123及漏极区1124之间的沟道区由于栅极的遮挡作用而未掺杂。
例如，在栅极11211、第一电容电极1161及多条引线1210形成后，可以通过沉积等方式在衬底基板上沉积绝缘材料，在栅极11211上形成层间绝缘层1129，并且在第一邦定区通过构图工艺在多条引线1210上以及邦定周边区1500、邦定边界区1400上形成第一绝缘层1331。第一绝缘层1331中形成有第一导电图案过孔13114。层间绝缘层及第一绝缘层的材料例如可以包括氧化硅、氮化硅、氧氮化硅等绝缘材料。
例如，然后，在显示区的衬底基板上沉积金属材料层，通过构图工艺在与第一电容电极1161重叠的部分形成第二电容电极1162。第一电容电极1161和第二电容电极1162实现为存储电容1160。
例如，在形成第二电容电极1162后，在显示区可以通过沉积等方式形成第四绝缘层11210，第四绝缘层11210的材料例如可以包括氧化硅、氮化硅、氧氮化硅等绝缘材料。
例如，在栅绝缘层1128、层间绝缘层1129及第四绝缘层11210中形成过孔，以暴露有源层2122的源极区2123及漏极区2124。
例如，然后，通过构图工艺在显示区形成源极1125和漏极1126，在第一邦定区形成第一导电图案13111。第一导电图案13111通过第一绝缘层1331中的第一导电过孔13114与引线1210电连接。
例如，在显示区中沉积绝缘材料，通过构图工艺形成第一平坦化层1130，在第一平坦化层1130中形成第一过孔1131。
例如，如图8A所示，在显示基板上形成位于显示区的像素驱动电路1120、存储电容器1160、第一平坦化层1130，以及位于第一邦定区的引线1210、第 一绝缘层1331、第一导电图案13111后，在衬底基板上沉积金属材料层。对金属材料层进行构图工艺，以在显示区形成第一转接电极1180，在第一邦定区形成第二导电图案13112以及位于邦定边界区的标记金属层1350。第二导电图案13112覆盖第一导电图案13111的边缘，以避免第一导电图案13111被腐蚀。第一转接电极、第二导电图案及标记金属层的材料可以包括金属材料或者合金材料，例如钼、铝及钛等形成的金属单层或多层结构。
在本公开的一些实施中，标记金属层1350还可以与第一导电图案层13111同层形成，本公开的实施例不以此为限。
例如，如图8B所示，在衬底基板上沉积第一绝缘材料层1710。第一绝缘材料层2710可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料。
例如，如图8C所示，在第一绝缘材料层1710上沉积光刻胶1720。
例如，如图8D所示，提供第一掩膜版1730对光刻胶1720进行曝光，第一掩膜版1730包括完全透光区、部分透光区及不透光区。第一掩膜版1730包括在第一邦定区1300与接触垫1310之间的间隙重叠的第二透光图案1732及与接触垫1310重叠的第一透光图案1731、在邦定边界区1400的第二透光图案1732、在邦定周边区1500的非透光图案1733。第一掩膜版1730在显示区包括与第一透光图案1731及非透光图案1733。第一透光图案1731位于完全透光区，第二透光图案1732位于部分透光区，非透光图案1733位于不透光区。即，第二掩膜版1730为灰色掩膜版或半色调掩膜版。光刻胶为正性光刻胶，对应地，第二透光图案1732的透光率小于第一透光图案1731的透光率。在曝光过程中，可以在使得光刻胶1720中与第一透光图案1731对应的部分被完全曝光的情况下，光刻胶1720中与第二透光图案1732对应的部分被部分曝光。光刻胶1720与非透光图案1733对应的部分未被曝光。
例如，如图8E所示，对光刻胶1720进行显影，光刻胶1720的被完全曝光的部分去除，即，在显示周边区中，与接触垫1310重叠的光刻胶1720被去除，光刻胶1720的被部分曝光的部分被减薄，而光刻胶1720的未被曝光的部分的厚度例如基本未改变。显影后，光刻胶1720在第一邦定区形成为光刻胶图案1721。同样地，在显示区中，被完全曝光的光刻胶1720被去除。显影后，光刻胶1720在显示区形成为光刻胶图案1722。
又例如，在上述构图工艺中，也可以采用负性光刻胶，那么所采用的掩模板例如是与上述第一掩膜版1730互补的掩模板，由此在曝光、显影后得到 上述光刻胶图案1721及光刻胶图案1722。
例如，如图8F所示，对显示周边区及显示区中的第一绝缘材料层1710进行刻蚀以去除在第一邦定区与接触垫重叠的绝缘材料层，以及在显示区形成第二过孔1191以暴露第一转接电极1180。
例如，如图8G所示，之后，进行灰化工艺去除显示周边区中的被部分曝光的光刻胶以及减薄为被曝光的光刻胶形成光刻胶图案1721和减薄显示区的光刻胶图案1722。然后，利用当前的光刻胶图案，对第一邦定区中剩余的第一绝缘材料层1710进行刻蚀并控制刻蚀厚度以形成第二绝缘层1332。第二绝缘层1332覆盖第二导电图案13112的边缘。并且使得第一绝缘层1332在邦定边界区1400相对于衬底基板1000的表面的高度小于第一绝缘层1332在邦定周边区1500相对于衬底基板1000的表面的高度。例如，在邦定边界区1400以及在邦定周边区1500，第二绝缘层1332相对于衬底基板具有坡度角，该坡度角例如约为40度～60度，又例如约为50度。
例如，如图8H所示，去除显示区的光刻胶图案1722及显示周边区的光刻胶图案1721。在显示区形成第二平坦化层1190以提供平坦化表面。
例如，如图8I所示，在显示区的第二平坦化1190上形成发光元件1140的第一电极1141；在第二平坦化1190以及第一电极1141上形成像素限定层1144，像素限定层1144包括多个开口，以限定多个像素单元。多个开口的每个暴露对应的第一电极1141。之后，将发光层1142通过例如蒸镀工艺形成在像素限定层1144的多个开口中，然后将第二电极1143形成在像素限定层1144以及发光层1142上，例如该第二电极1143可以形成在部分或整个显示区域中，从而在制备工艺中可以整面形成。发光元件1140的第一电极1141通过第二过孔1191与第一转接电极1180电连接。
例如，第一电极1141的材料可以包括至少一种透明导电氧化物材料，包括氧化锢锡(ITO)、氧化锢锌(IZO)、氧化锌(ZnO)等。此外，第一电极1141可以包括具有高反射率的金属作为反射层，诸如银(Ag)。
例如，对于OLED，发光层1142可以包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光；并且，根据需要发光层还可以进一步包括电子注入层、电子传输层、空穴注入层、空穴传输层等功能层。对于QLED，发光层1142可以包括量子点材料，例如，硅量子点、锗量子点、硫化镉量子点、硒化镉量子 点、碲化镉量子点、硒化锌量子点、硫化铅量子点、硒化铅量子点、磷化铟量子点和砷化铟量子点等，量子点的粒径为2-20nm。
例如，第二电极1143可以包括各种导电材料。例如，第二电极1143可以包括锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料。
例如，像素限定层1144的材料可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料，或者包括氧化硅、氮化硅等无机绝缘材料，本公开的实施例对此不做限定。
例如，如图8J所示，在显示区的发光元件1140上沉积绝缘材料，通过构图工艺在显示区形成第五绝缘层11110。第五绝缘层11110可以提供平坦化表面。第五绝缘层11110的材料可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料，或者包括氧化硅、氮化硅等无机绝缘材料，本公开的实施例对此不做限定。
例如，在第五绝缘层11110上沉积金属材料层，通过构图工艺以在显示区形成辅助电极11120，在第一邦定区形成第三导电图案13113，第三导电图案13113覆盖的第二绝缘层1332的边缘。金属材料层可以包括包括氧化锢锡(ITO)，并且由此得到透明电极，或者形成辅助电极11120的材料可以包括金属网格，也可以由此得到透明电极。例如，辅助电极11120在其它实施例中可以用作触控电极。
例如，如图8K所示，在衬底基板上沉积绝缘材料，通过构图工艺在显示区形成显示区保护层11130以及在邦定周边区形成第三绝缘层1333。第三绝缘层2333起到对第一邦定区的密封作用，以避免第一邦定区的内部结构被腐蚀破坏。第三绝缘层的材料可以包括有机绝缘材料。有机绝缘材料可以为含有干燥剂的高分子材料或可阻挡水汽的高分子材料等，例如高分子树脂等。
在本公开的另一个示例中，如图3所示的显示基板的制备方法可以包括图8C～图8H，如图8C～图8H所示的工艺可以参见上述示例的相关说明。
例如，在该示例中，第一绝缘材料层1710可以为光敏树脂材料，例如光刻胶。例如，该光敏树脂材料为正性光刻胶，在涂覆了该光敏树脂材料以形成第一绝缘材料层之后，使用例如上述第一掩模板1730进行曝光，第一掩膜版1730包括完全透光区、部分透光区及不透光区。第一掩膜版1730在显示区包括与第一透光图案1731及非透光图案1733。第一透光图案1731位于完全透光区，第二透光图案1732位于部分透光区，非透光图案1733位于不透光区。 即，第二掩膜版1730为灰色掩膜版或半色调掩膜版。光刻胶为正性光刻胶，对应地，第二透光图案1732的透光率小于第一透光图案1731的透光率。
在曝光过程中，使得第一绝缘材料层1710中与第一透光图案1731对应的部分被完全曝光，与第二透光图案1732对应的部分被部分曝光，而与显示区的非透光图案1733对应的部分未被曝光。在显影后，显示区中未被曝光的第一绝缘材料层1710形成第二平坦化层1190。对第一邦定区中被部分曝光的第一绝缘材料层1710形成第二绝缘层1332。第二绝缘层1332覆盖第二导电图案13112的边缘。并且使得第一绝缘层1332在邦定边界区1400相对于衬底基板1000的表面的高度小于第一绝缘层1332在邦定周边区1500相对于衬底基板1000的表面的高度。相应的，显示区中和第一邦定区中被完全曝光的第一绝缘材料层1710被去除，形成显示区中的第二过孔1191以及暴露出第一邦定区中的接触垫。上述制备方法同样可以得到如图8H所示的实施例的显示基板。
又例如，该光敏树脂材料也可以为负性光刻胶，此时采用的掩模板例如与上述第一掩模板1730互补的掩模板，由此在曝光、显影之后也同样在显示区形成第二平坦化层，在第一邦定区露出接触垫以及覆盖接触垫的周边第一绝缘层。
利用上述制备方法获得的显示基板中，在显示周边区的邦定边界区形成第一绝缘层叠层，使得第一绝缘层叠层的相对衬底基板的高度小于位于邦定周边区的第二绝缘层叠层相对衬底基板的高度，进而减小邦定周边区的膜层段差的高度，以降低并对邦定周边区及邦定边界区产生气泡的风险，更有助于完成邦定工艺，提高显示基板的产品良率和可靠性。
又例如，在另一个实施例中，提供对应于图7中示出的显示基板的制备方法。图7中所示的显示基板的结构与图6中所示的显示基板的结构相比，图7中的显示基板增加位于源漏电极上的钝化层31212以保护像素驱动电路。
在该实施例中，可以在像素驱动电路的源漏电极形成之后，第一平坦化层形成之前，增加形成钝化层的步骤。例如，形成钝化层薄膜以覆盖源极3125和漏极3126，然后对于该钝化层薄膜构图以在显示区形成暴露漏源极3125的钝化层过孔。
例如，钝化层的材料可以包括有机绝缘材料或无机绝缘材料，例如，氮化硅材料，由于其具有较高的介电常数且具有很好的疏水功能，能够很好的保护像素驱动电路不被水汽腐蚀。
需要说明的是，本公开的多个实施例中，该显示装置的制备方法的流程可以包括更多或更少的操作，这些操作可以顺序执行或并行执行。虽然上文描述的制备方法的流程包括特定顺序出现的多个操作，但是应该清楚地了解，多个操作的顺序并不受限制。上文描述的制备方法可以执行一次，也可以按照预定条件执行多次。
关于上述实施例提供的显示装置的制备方法的技术效果可以参考本公开的实施例中提供的显示装置的技术效果，这里不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (32)

  1. 一种显示基板，包括：
    衬底基板，包括显示区与至少部分围绕所述显示区的围堰区，所述围堰区远离所述显示区一侧的过渡区，所述过渡区远离所述围堰区一侧的第一邦定区以及邦定周边区，所述邦定周边区位于所述第一邦定区与所述过渡区之间；
    引线，位于所述第一邦定区；
    多个接触垫，位于所述第一邦定区，被配置为与所述引线电连接；
    第一绝缘层叠层，位于所述第一邦定区；
    第二绝缘层叠层，位于所述邦定周边区，所述第二绝缘层叠层的至少两个绝缘层延伸到所述第一邦定区中以得到所述第一绝缘层叠层，
    其中，所述第一绝缘层叠层的在垂直于所述衬底基板方向上的厚度小于所述第二绝缘层叠层在垂直于所述衬底基板方向上的厚度。
  2. 根据权利要求1所述的显示基板，其中，所述多个接触垫包括多个第一接触垫以及多个第二接触垫，
    其中，多个所述第一接触垫排布为至少一行，
    所述第一接触垫和所述第二接触垫包括导电图案叠层。
  3. 根据权利要求1或2所述的显示基板，还包括:
    第三绝缘层叠层,位于所述过渡区，所述第三绝缘层叠层包括第一绝缘层叠层子层以及第二绝缘叠层子层，所述第一绝缘层叠层子层在所述衬底基板上的正投影至少部分覆盖所述过渡区以及所述邦定周边区，所述第二绝缘层叠层子层在所述衬底基板上的正投影至少部分覆盖所述过渡区以及所述邦定周边区。
  4. 根据权利要求3所述的显示基板，所述第三绝缘层叠层还包括第三绝缘层叠层子层，设置在所述第一绝缘层叠层子层以及所述第二绝缘层叠层子层之间，
    其中，所述第三绝缘层叠层子层在所述衬底基板的正投影与所述第一邦定区以及所述邦定周边区不交叠。
  5. 根据权利要求4所的显示基板，其中，所述至少两个绝缘层包括第一绝缘层及第二绝缘层，所述第一绝缘层位于所述衬底基板上，所述第 二绝缘层位于所述第一绝缘层远离所述衬底基板的一侧，
    其中，所述第一绝缘层叠层子层延伸至所述邦定周边区以得到所述第一绝缘层，所述第二绝缘层叠层子层延伸至所述邦定周边区以得到所述第二绝缘层。
  6. 根据权利要求5所述的显示基板，还包括：
    像素结构，位于所述显示区，
    其中，所述像素结构包括像素驱动电路、第一平坦化层、第一转接电极、第二平坦化层以及发光元件，
    所述像素驱动电路包括薄膜晶体管，所述薄膜晶体管包括栅极、源漏电极及层间绝缘层，所述层间绝缘层位于所述栅极远离所述衬底基板的一侧且位于所述源漏电极靠近所述衬底基板一侧，
    所述第一平坦化层在所述像素驱动电路远离所述衬底基板的一侧以提供第一平坦化表面且包括第一过孔，
    所述第一转接电极在所述第一平坦化表面上，且通过所述第一过孔与所述薄膜晶体管的源漏电极之一电连接，
    所述第二平坦化层在所述第一转接电极远离所述衬底基板的一侧以提供第二平坦化表面且包括第二过孔，
    所述发光元件在所述第二平坦化表面上且通过所述第二过孔与所述第一转接电极电连接，其中,所述层间绝缘层与所述第一绝缘层同层设置，所述第二平坦化层与所述第二绝缘层同层设置，所述第一平坦化层与所述第三绝缘层叠层子层同层设置。
  7. 根据权利要求6所述的显示基板，其中，所述第二平坦化层在垂直于衬底基板方向上的厚度与第三绝缘层叠层子层在过渡区以及所述第二绝缘层在邦定周边区沿垂直于衬底基板方向上的厚度基本相等。
  8. 根据权利要求5-7任一项所述的显示基板，其中，相对于所述衬底基板,所述第二绝缘层在所述第一邦定区的高度小于所述第二绝缘层在所述邦定周边区的高度。
  9. 根据权利要求8所述的显示基板，其中，所述第二绝缘层在所述邦定周边区沿垂直于衬底基板方向上的厚度与第二绝缘层叠层子层在所述过渡区沿垂直于衬底基板方向上的厚度基本相等。
  10. 根据权利要求5-9任一项所述的显示基板，其中，所述第一绝缘 层及所述第二绝缘层延伸到所述第一邦定区中以得到所述第一绝缘层叠层。
  11. 根据权利要求5-10任一项所述的显示基板，其中，所述至少两个绝缘层还包括第三绝缘层，
    所述第三绝缘层位于所述第二绝缘层的远离所述衬底基板的一侧且被配置为在靠近多个所述接触垫的一侧露出所述第二绝缘层。
  12. 根据权利要求10-11任一项所述的显示基板，其中，所述显示区包括信号线，用于与所述引线电连接。
  13. 根据权利要求12所述的显示基板，其中，所述导电图案叠层包括至少两个导电图案，
    其中，所述第一绝缘层叠层的至少一个绝缘层覆盖所述至少两个导电图案之一的边缘并且所述至少一个绝缘层的边缘被所述至少两个导电图案中另一个所覆盖。
  14. 根据权利要求13所述的显示基板，其中，所述导电图案叠层包括第一导电图案和第二导电图案，
    其中，所述第一导电图案位于所述引线远离所述衬底基板的一侧且与所述引线电连接，
    所述第二导电图案位于所述第一导电图案远离所述衬底基板的一侧且覆盖所述第一导电图案的边缘，
    其中，所述第一绝缘层叠层中的所述第二绝缘层覆盖所述第二导电图案的边缘。
  15. 根据权利要求13或14所述的显示基板，其中，所述第一绝缘层叠层中的所述第一绝缘层位于所述第一导电图案与所述引线之间，
    所述第一导电图案与所述引线之间所述第一绝缘层具有第一导电图案过孔；
    所述第一导电图案与所述引线通过所述第一导电图案过孔电连接。
  16. 根据权利要求13-15任一项所述的显示基板，其中，所述像素结构还包括第一显示区金属层，
    其中，所述第一导电图案与所述第一显示区金属层同层设置；
    所述第二导电图案与所述第一转接电极同层设置。
  17. 根据权利要求16所述的显示基板，其中，所述薄膜晶体管的源 漏电极位于所述第一显示区金属层中。
  18. 根据权利要求15-17任一项所述的显示基板，所述衬底基板还包括第二邦定区，所述第二邦定区位于所述第一邦定区远离所述显示区的一侧，所述第一绝缘层延伸至所述第二邦定区，
    所述显示基板还包括多个第三接触垫以及第二邦定区引线，多个所述第三接触垫位于所述第二邦定区并设置在所述第一绝缘层远离衬底基板的一侧，所述第三接触垫包括多个接触垫金属层，
    所述第二邦定区引线，位于所述第一邦定区及第二邦定区之间，并配置为连接所述第二接触垫以及所述第三接触垫。
  19. 根据权利要求18所述的显示基板，其中，多个接触垫金属层包括第一接触垫金属层以及第二接触垫金属层，所述第一接触垫金属层设置在所述第一绝缘层远离所述衬底基板的一侧，所述第二接触垫金属层与所述第一接触垫金属层层叠并覆盖所述第二接触垫金属层的周边，
    其中，所述第一接触垫金属层与所述第一导电图案层同层设置，
    所述第二接触垫金属层与所述第二导电图案层同层设置。
  20. 根据权利要求19所述的显示基板，其中，所述第二接触垫金属层向第一邦定区延伸以形成所述第二邦定区引线，
    其中，所述第二绝缘层延伸至所述第二邦定区，并覆盖所述第二邦定区引线以及所述第二接触垫金属层的边缘。
  21. 根据权利要求20所述的显示基板，其中，所述第二绝缘层的位于所述第一邦定区与第二邦定区之间的部分在垂直于所述衬底基板方向上的厚度与所述第二绝缘层位于所述第一邦定区的部分在垂直于所述衬底基板方向上的厚度基本相同，
    所述第二绝缘层的位于所述第一邦定区域第二邦定区之间的部分在所述衬底基板上的正投影与所述第二邦定区引线在所述衬底基板上的正投影至少部分重叠。
  22. 根据权利要求15-21任一项所述的显示基板，其中，所述导电图案叠层还包括第三导电图案，
    所述第三导电图案位于所述第二导电图案远离所述衬底基板的一侧，所述第一绝缘层叠层中的所述第二绝缘层的边缘被所述第三导电图案所覆盖。
  23. 根据权利要求22所述的显示基板，其中，所述多个接触垫金属层还包括第三接触垫金属层，所述第三接触垫金属层位于所述第二接触垫金属层远离衬底基板的一侧，并覆盖第二邦定区中所述第二绝缘层的边缘，
    其中，所述第三接触垫金属层与所述第三导电图案层同层设置。
  24. 根据权利要求23所述的显示基板，还包括：
    封装层、辅助电极以及显示区保护层，所述封装层至少位于所述显示区，所述封装层包括至少一层封装子层，
    所述辅助电极以及所述显示区保护层位于所述显示区，所述辅助电极设置在所述封装层远离衬底基板的一侧，所述显示区保护层设置在所述辅助电极远离衬底基板的一侧，
    其中，所述第三导电图案与所述辅助电极同层设置，所述第三绝缘层与所述显示区保护层同层设置。
  25. 根据权利要求15-24任一项所述的显示基板，其中，所述像素结构还包括存储电容器，所述存储电容器包括第一存储电容电极及第二存储电容电极，
    所述引线与所述存储电容器的第一存储电容电极及第二存储电容电极的其中之一同层设置。
  26. 根据权利要求15-25任一项所述的显示基板，其中，所述第一邦定区包括邦定边界区，所述邦定边界区位于所述第一邦定区与所述邦定周边区之间，
    所述邦定边界区还包括位于所述第一绝缘层与所述第二绝缘层之间的标记金属层，其中，
    所述标记金属层与所述第一导电图案及所述第二导电图案的其中之一同层设置。
  27. 一种显示装置，包括如权利要求1-26任一项所述的显示基板。
  28. 一种显示基板的制备方法，包括：
    提供衬底基板，其中，包括显示区与至少部分围绕所述显示区的围堰区，所述围堰区远离所述显示区一侧的过渡区，所述过渡区远离所述围堰区一侧的第一邦定区以及邦定周边区，所述邦定周边区位于所述第一邦定区与所述过渡区之间；
    在所述第一邦定区中形成引线；
    在所述第一邦定区中形成多个接触垫，其中，所述接触垫被形成为与所述引线电连接；
    在所述第一邦定区中形成第一绝缘层叠层；
    在所述邦定周边区中形成第二绝缘层叠层，使得所述第二绝缘层叠层的至少两个绝缘层延伸到所述第一邦定区中以得到所述第一绝缘层叠层，并使得所述第一绝缘层叠层的在垂直于所述衬底基板方向上的厚度小于所述第二绝缘层叠层在垂直于所述衬底基板方向上的厚度。
  29. 根据权利要求28所述制备方法，其中，形成所述第二绝缘层叠层包括：
    形成位于所述衬底基板上的所述第二绝缘层叠层的第一绝缘层，形成位于所述第一绝缘层远离所述衬底基板的一侧的所述第二绝缘层叠层的所述第二绝缘层，
    其中，所述第一绝缘层及所述第二绝缘层延伸到所述第一邦定区中形成所述第一绝缘层叠层。
  30. 根据权利要求29所述的制备方法，还包括：
    在所述显示区中形成像素结构，其中，所述像素结构包括像素驱动电路、第一平坦化层、第一转接电极、第二平坦化层以及发光元件，
    在所述显示区中形成像素结构包括：
    在所述衬底基板上形成所述像素驱动电路，其中，在所述像素驱动电路中形成薄膜晶体管，在所述薄膜晶体管中形成栅极、源漏电极及层间绝缘层，所述层间绝缘层位于所述栅极远离所述衬底基板的一侧且位于源漏电极靠近所述衬底基板的一侧，
    在所述像素驱动电路远离所述衬底基板的一侧形成所述第一平坦化层以提供第一平坦化表面，且在所述第一平坦化层中形成第一过孔，
    在所述第一平坦化表面上形成第一转接电极，且所述第一转接电极通过所述第一过孔与所述源漏电极之一电连接，
    在所述第一转接电极远离所述衬底基板的一侧形成所述第二平坦化层以提供第二平坦化表面，且在所述第二平坦化表面中形成第二过孔，
    在所述第二平坦化表面上形成所述发光元件，且所述发光元件通过所述第二过孔与所述第一转接电极电连接。
  31. 根据权利要求30所述的制备方法，其中，形成所述第二绝缘层 包括：
    在形成所述导电图案叠层的第二导电图案以及所述像素驱动电路之后，在衬底基板上沉积第一绝缘材料层；
    对所述第一绝缘材料层进行构图工艺，以使得所述第一绝缘材料层的位于显示区的部分形成为第二平坦化层，且在所述第二平坦化层中形成所述第二过孔，去除第一绝缘材料层的与所述第二导电图案重叠的部分，并且减薄所述第一绝缘材料层的位于所述第一邦定区的部分以形成所述第二绝缘层，以使得所述第二绝缘层在所述第一邦定区相对于所述衬底基板的高度小于在所述邦定周边区的高度，且覆盖所述第二导电图案的边缘。
  32. 根据权利要求31所述的制备方法，其中，对所述第一绝缘材料层进行构图工艺包括：
    使用灰色调掩模板或半色调掩模板构图工艺对所述第一绝缘材料层进行构图。
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