WO2021109794A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2021109794A1
WO2021109794A1 PCT/CN2020/126966 CN2020126966W WO2021109794A1 WO 2021109794 A1 WO2021109794 A1 WO 2021109794A1 CN 2020126966 W CN2020126966 W CN 2020126966W WO 2021109794 A1 WO2021109794 A1 WO 2021109794A1
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Prior art keywords
layer
substrate
trench
opening
dielectric layer
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English (en)
French (fr)
Inventor
胡胜
杨帆
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Priority to EP20897017.8A priority Critical patent/EP4071818A4/en
Priority to KR1020227019570A priority patent/KR102662140B1/ko
Publication of WO2021109794A1 publication Critical patent/WO2021109794A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/807—Pixel isolation structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/014—Manufacture or treatment of image sensors covered by group H10F39/12 of CMOS image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/011—Manufacture or treatment of image sensors covered by group H10F39/12
    • H10F39/026—Wafer-level processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/18—Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors
    • H10F39/199—Back-illuminated image sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/80—Constructional details of image sensors
    • H10F39/811—Interconnections

Definitions

  • the present invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a semiconductor device and a manufacturing method thereof.
  • CMOS Image Sensor BSI-CIS
  • DTI Deep Trench Isolation
  • BSI-CIS Backside Metal Grid
  • the purpose of the present invention is to provide a semiconductor device and a manufacturing method thereof, so that the metal grid layer is electrically connected to the exposed part of the substrate and/or the trench filling structure, thereby enabling the semiconductor device to be electrically connected. Optimization and improvement in performance.
  • the present invention provides a method for manufacturing a semiconductor device, including:
  • a trench is formed in the substrate of the pixel region, and a filling material is filled in the trench, and a high-K dielectric layer is formed between the sidewall of the filling material and the substrate to form the trench Slot filling structure;
  • the buffer dielectric layer is etched to form a first opening that exposes at least a part of the substrate around the top sidewall of the trench filling structure and/or at least a part of the top of the trench filling structure ;as well as,
  • a metal grid layer is formed on the buffer dielectric layer, and the metal grid layer fills the first opening so as to be electrically connected to the exposed portion of the substrate and/or the trench filling structure.
  • the step of forming the trench and the trench filling structure in the substrate of the pixel region includes:
  • a first patterned photoresist layer is formed on the pad oxide layer, and the pad oxide layer and at least part of the thickness of the substrate are processed using the first patterned photoresist layer as a mask. Etching to form a trench in the substrate of the pixel area;
  • Filling the filling material in the trench, and the filling material also covers the second isolation oxide layer outside the trench;
  • An etching or chemical mechanical polishing process is used to remove the filling material, the second isolation oxide layer, the high-K dielectric layer, and the first isolation oxide layer on the surface of the substrate covering the trench, or only Removing the filling material covering the surface of the substrate outside the trench to form a trench filling structure in the trench.
  • the filling material includes a first conductive metal layer
  • the first opening exposing at least a part of the top of the trench filling structure includes: the first opening surrounds the top sidewall of the trench filling structure Opening to expose the first conductive metal layer on the top sidewall of the trench filling structure, and/or the first opening is located on the top surface of the trench filling structure to expose the trench The trench fills part or all of the top surface of the first conductive metal layer of the structure.
  • the step of etching the buffer dielectric layer to form the first opening includes:
  • a second patterned photoresist layer is formed on the buffer medium layer, and the buffer medium layer is etched using the second patterned photoresist layer as a mask to etch the buffer medium layer in the pixel area.
  • the first opening is formed in the buffer medium layer of, and the first opening exposes at least a part of the substrate surrounding the top sidewall of the trench-filled structure and/or at least a part of the top of the trench-filled structure; and ,
  • the second patterned photoresist layer is removed.
  • the step of forming the metal grid layer on the buffer medium layer includes:
  • a third patterned photoresist layer is formed on the second conductive metal layer, and the second conductive metal layer is etched by using the third patterned photoresist layer as a mask.
  • the pixel area forms a metal grid layer, and the metal grid layer is electrically connected to the portion of the substrate exposed by the first opening and/or the trench filling structure; and,
  • the third patterned photoresist layer is removed.
  • the substrate further has a pad area located at the periphery of the pixel area, and a metal interconnection structure and a plug structure located above the metal interconnection structure are formed in the substrate of the pad area, The bottom of the plug structure is electrically connected to the metal interconnection structure.
  • the plug structure is formed in the substrate of the pad area.
  • the buffer medium layer further extends to cover the substrate surface of the pad area, so that the buffer A dielectric layer burys the plug structure; while etching the buffer dielectric layer on the pixel area to form the first opening, it also etches the buffer on the pad area A dielectric layer to form a second opening that exposes the top surface of the portion of the plug structure; and, forming the metal grid layer on the buffer dielectric layer in the pixel area
  • a pad structure is also formed on the buffer dielectric layer of the pad area, and the pad structure fills the second opening to be electrically connected to the exposed top of the plug structure.
  • the present invention also provides a semiconductor device, including:
  • a substrate having a pixel area, and a trench is formed in the substrate of the pixel area;
  • a trench filling structure is formed in the substrate of the pixel area.
  • the trench filling structure includes a filling material filled in the trench and a filling material between the sidewall of the filling material and the substrate.
  • the buffer medium layer covers the surface of the substrate of the pixel area, the buffer medium layer has a first opening, and the first opening exposes at least a part of the substrate and the periphery of the top sidewall of the trench filling structure /Or at least part of the top of the trench filling structure;
  • a metal grid layer is formed on the buffer dielectric layer, and the metal grid layer fills the first opening to be electrically connected to the exposed portion of the substrate and/or the trench filling structure.
  • the trench filling structure includes a first isolation oxide layer, the high-K dielectric layer, a second isolation oxide layer sequentially covering the surface of the trench, and all the trenches filled in the trench.
  • the filling material, the first isolation oxide layer, the high-K dielectric layer and the second isolation oxide layer are at least located between the sidewall of the filling material and the substrate.
  • the filling material includes a first conductive metal layer
  • the first opening exposing at least a part of the top of the trench filling structure includes: the first opening surrounds the top sidewall of the trench filling structure Opening to expose the first conductive metal layer on the top sidewall of the trench filling structure, and/or the first opening is located on the top surface of the trench filling structure to expose the trench The trench fills part or all of the top surface of the first conductive metal layer of the structure.
  • the K value of the high-K dielectric layer is greater than 7.
  • the substrate further has a pad area located at the periphery of the pixel area, and a metal interconnection structure and a plug structure located above the metal interconnection structure are formed in the substrate of the pad area, The bottom of the plug structure is electrically connected to the metal interconnection structure.
  • a through hole is formed in the substrate of the pad area, and the through hole exposes at least a part of the top surface of the metal interconnection structure, and the plug structure includes: located on the side of the through hole A third isolation oxide layer on the wall, and a third conductive metal layer filling the through hole.
  • the buffer dielectric layer also extends to cover the surface of the substrate of the pad area, and the buffer dielectric layer has a second opening exposing at least a part of the top of the plug structure;
  • a pad structure is also formed on the buffer dielectric layer of the disk area, and the pad structure fills the second opening to be electrically connected to the exposed top of the plug structure.
  • a trench filling structure is formed in the substrate of the pixel area, and the sidewall of the filling material in the trench filling structure is sandwiched between the substrate and the substrate.
  • K dielectric layer covering a buffer dielectric layer on the substrate surface of the pixel area, and the buffer dielectric layer burying the trench filling structure; etching the buffer dielectric layer to form a first opening, The first opening exposes at least a part of the substrate around the top sidewall of the trench-filled structure and/or at least a part of the top of the trench-filled structure; and a metal grid layer is formed on the buffer dielectric layer
  • the metal grid layer fills the first opening, so that the metal grid layer is electrically connected to the exposed part of the substrate and/or the trench filling structure, thereby enabling the semiconductor
  • the electrical performance of the device is optimized and improved; and the high-K dielectric layer sandwiched between the sidewall of the filling material and the substrate also optimizes the performance of the semiconductor device
  • the semiconductor device of the present invention includes a trench filling structure formed in the substrate of the pixel area, and the trench filling structure includes filling materials filled in the trenches in the substrate and intervening A high-K dielectric layer between the sidewall of the filling material and the substrate; a buffer medium layer formed on the surface of the substrate in the pixel area, the buffer medium layer having a first opening, the second An opening exposes at least a part of the substrate at the periphery of the top sidewall of the trench filling structure and/or at least a part of the top of the trench filling structure; and, a metal grid layer formed on the buffer dielectric layer, The metal grid layer fills the first opening, so that the metal grid layer is electrically connected to the exposed portion of the substrate and/or the trench filling structure, thereby enabling electrical performance of the semiconductor device Aspects of optimization and improvement; and, the high-K dielectric layer sandwiched between the sidewall of the filling material and the substrate also optimizes the performance of the semiconductor device.
  • 1a to 1f are schematic diagrams of a semiconductor device during the manufacturing process
  • FIG. 2 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention
  • 3a to 3i are schematic diagrams of the device of Embodiment 1 in the manufacturing method of the semiconductor device shown in FIG. 2;
  • FIG. 4a to 4e are schematic diagrams of the device of the second embodiment in the manufacturing method of the semiconductor device shown in FIG. 2;
  • 5a to 5e are schematic diagrams of the device in the third embodiment of the manufacturing method of the semiconductor device shown in FIG. 2;
  • 6a to 6g are schematic diagrams of the device of the fourth embodiment in the manufacturing method of the semiconductor device shown in FIG. 2;
  • FIG. 7 is a schematic diagram of a device of Embodiment 5 in the manufacturing method of the semiconductor device shown in FIG. 2;
  • 8a to 8P are device schematic diagrams of Embodiment 6 in the manufacturing method of the semiconductor device shown in FIG. 2.
  • a manufacturing process of the metal grid layer in the pixel area is as follows:
  • a substrate 10 having a pixel area 11 is provided;
  • a pad oxide layer 12 is formed on the pixel region 11
  • a first patterned photoresist layer 13 is formed on the pad oxide layer 12, and the first patterned
  • the photoresist layer 13 is used as a mask to etch the pad oxide layer 12 on the pixel region 11 and a part of the thickness of the substrate 10 to form a trench 14 in the substrate 10 of the pixel region 11 , Remove the first patterned photoresist layer 13;
  • an isolation oxide layer 151 is formed on the surface of the trench 14 and the surface of the pad oxide layer 12, and a conductive metal layer 152 is filled in the trench 14, and the conductive metal layer 152 Covering the pad oxide layer 12, the conductive metal layer 152, the isolation oxide layer 151, and the pad oxide layer 12 covering the substrate 10 can be removed by a chemical mechanical polishing process to obtain A trench filling structure 15 in the trench 14, the trench filling structure 15 including the isolation oxide layer 151 and a conductive metal layer 152;
  • a buffer oxide layer 16 and a metal grid film layer 17 are sequentially formed to cover the substrate 10;
  • a second patterned photoresist layer 18 is formed on the metal grid film layer 17, and the second patterned photoresist layer 18 is used as a mask.
  • the metal grid film layer 17 is etched to form a metal grid layer 19 on the buffer oxide layer 16, and the second patterned photoresist layer 18 is removed, wherein the metal grid layer 19 corresponds to Located above the trench filling structure 15.
  • the present invention provides a semiconductor device and a manufacturing method thereof, which can realize electrical connection between the metal grid layer and the underlying substrate and trench filling structure, thereby enabling the optimization of the electrical performance of the semiconductor device. And improve.
  • FIG. 2 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
  • the method for manufacturing a semiconductor device includes:
  • Step S11 providing a substrate with a pixel area
  • Step S12 forming a trench in the substrate of the pixel area, and filling the trench with a filling material to form a trench filling structure, and the sidewall of the filling material and the substrate are also sandwiched There is a high-K dielectric layer;
  • Step S13 covering a buffer dielectric layer on the substrate surface of the pixel area, and the buffer dielectric layer burying the trench filling structure;
  • Step S14 The buffer dielectric layer is etched to form a first opening that exposes at least a part of the substrate around the top sidewall of the trench filling structure and/or the trench filling structure At least part of the top
  • Step S15 A metal grid layer is formed on the buffer medium layer, and the metal grid layer fills the first opening so as to be electrically connected to the exposed part of the substrate and/or the trench filling structure. connection.
  • FIGS. 3a to 8p are also schematic longitudinal cross-sectional views of the semiconductor device.
  • a substrate 20 having a pixel region 21 is provided.
  • the material of the substrate 20 can be any suitable substrate known to those skilled in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe) ), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III/V compound semiconductors.
  • a trench 211 is formed in the substrate 20 of the pixel region 21, and a filling material is filled in the trench 211 to form a trench filling structure 212.
  • the sidewalls of the filling material and the A high-K dielectric layer 2122 is also sandwiched between the substrates 20.
  • the trench 211 may be a deep trench with a depth of 1 ⁇ m to 5 ⁇ m. It should be noted that the depth of the trench 211 is not limited to this depth range, and a suitable depth may be formed according to the performance requirements of the semiconductor device. ⁇ 211 ⁇ Groove 211.
  • the trench filling structure 212 may play a role in isolating various devices in the substrate 20 of the pixel region 21.
  • the K (dielectric constant) value of the high-K dielectric layer 2122 is preferably greater than 7, and the material of the high-K dielectric layer 2122 may include nitride or metal oxide, such as silicon nitride, silicon oxynitride, or titanium dioxide. , Tantalum pentoxide, etc.
  • the high-K dielectric layer 2122 has different frequency band voltages and charges with different properties, so that the high-K dielectric layer 2122 can change the charge in the substrate 20, thereby reducing dark current and avoiding dark current. The generated noise affects the performance of the semiconductor device.
  • the step of forming the trench 211 and the trench filling structure 212 in the substrate 20 of the pixel region 21 includes: first, as shown in FIG. 3a, a pad oxide layer 23 is covered in the pixel region 21 On the surface of the substrate 20, the pad oxide layer 23 is used to protect the surface of the substrate 20 when the first patterned photoresist layer 24 is formed by subsequent photolithography; then, as shown in FIGS. 3a and 3b As shown, a first patterned photoresist layer 24 is formed on the pad oxide layer 23.
  • the pad oxide layer 23 and at least part of the The thickness of the substrate 20 is etched to form trenches 211 in the substrate 20 of the pixel region 21; then, the first patterned photoresist layer 24 and the pad oxide layer 23 are removed; then , A first isolation oxide layer 2121, a high-K dielectric layer 2122, and a second isolation oxide layer 2123 are sequentially formed on the surface of the trench 211 and the substrate 20.
  • the first isolation oxide layer in the trench 211 2121, the high-K dielectric layer 2122 and the second isolation oxide layer 2123 may be located only on the sidewalls of the trench 211, or both may be located on the sidewalls and the bottom wall of the trench 211; then, filling the filling Material in the trench 211, and the filling material also covers the second isolation oxide layer 2123 on the periphery of the trench 211;
  • the filling material, the second isolation oxide layer 2123, the high-K dielectric layer 2122 and the first isolation oxide layer 2121 (as shown in FIG. 3c) on the surface of the substrate 20 at the periphery of the trench 211, or only the cover is removed
  • the filling material (as shown in FIG.
  • the first isolation oxide layer 2121, the high-K dielectric layer 2122, and the second isolation oxide layer 2123 in FIG. 6a still cover the substrate 20.
  • the filling material may include a dielectric material or a metal material, or both a dielectric material and a metal material; when the filling material is a metal material, as shown in FIG. 3c, the trench filling structure 212 includes The first isolation oxide layer 2121 on the surface of the trench 211, the high-K dielectric layer 2122, the second isolation oxide layer 2123, and the first conductive metal layer 2124 filling the trench 211 (that is, the filling material is the The first conductive metal layer 2124).
  • the dielectric material may include at least one of silicon dioxide, silicon nitride, tetraethyl orthosilicate, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, and silicon oxynitride, and the metal material may include tungsten, At least one of nickel, aluminum, silver, gold, and titanium.
  • top surface of the trench filling structure 212 may be flush with the top surface of the substrate 20, or the top surface of the trench filling structure 212 may be higher than the top surface of the substrate 20, or, Only the top surface of the filling material in the trench filling structure 212 is higher than the top surface of the substrate 20.
  • a buffer dielectric layer 25 is covered on the surface of the substrate 20 of the pixel region 21, and the buffer dielectric layer 25 burying the trench filling structure 212, as shown in FIG. 3d.
  • the material of the buffer medium layer 25 may include at least one of silicon dioxide, silicon nitride, tetraethyl orthosilicate, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, and silicon oxynitride. As shown in FIGS.
  • the first isolation oxide layer 2121, the high-K dielectric layer 2122, and the second isolation oxide layer 2123 can also be understood as constituting the buffer medium Part of layer 25.
  • the buffer dielectric layer 25 is etched to form a first opening that exposes at least a part of the substrate 20 or the trench filling at the periphery of the top sidewall of the trench filling structure 212 At least a part of the top of the structure 212, or at least a part of the substrate 20 at the periphery of the top sidewall of the trench-filled structure 212 and at least a part of the top of the trench-filled structure 212 are exposed.
  • the first opening exposes at least a portion of the substrate 20 at the periphery of the top sidewall of the trench filling structure 212, that is, the first opening is disposed at least around the top periphery of the trench filling structure 212 , To expose at least a portion of the substrate 20 surrounding the top periphery of the trench filling structure 212.
  • the situation where the first opening exposes at least part of the top of the trench filling structure 212 includes: when the top surface of the trench filling structure 212 is higher than the top surface of the substrate 20, the first opening It is possible to open only around the top sidewall of the trench filling structure 212 to expose the first isolation oxide layer 2121 on the top sidewall of the trench filling structure 212.
  • the first opening also exposes Part of the substrate 20 at the periphery of the top sidewall of the trench filling structure 212; when only the top surface of the filling material in the trench filling structure 212 is higher than the top surface of the substrate 20, the first The opening may only be opened around the top sidewall of the trench filling structure 212 to expose the filling material on the top sidewall of the trench filling structure 212; when the top surface of the trench filling structure 212 is higher than or When equal to the top surface of the substrate 20, the first opening may also be located on the top surface of the trench filling structure 212 to expose part or all of the top surface of the trench filling structure 212, including Expose part or all of the top surface of the filling material, or expose part or all of the top surface of the filling material, and expose the first isolation oxide layer 2121 and/or the high-K dielectric layer 2122 and /Or part or all of the top surface of the second isolation oxide layer 2123; when the top surface of the trench filling structure 212 is higher than
  • the situation where the first opening exposes at least a part of the top of the trench filling structure 212 includes: the first opening surrounds the trench filling structure 212 The top sidewall is opened to expose the first conductive metal layer 2124 on the top sidewall of the trench filling structure 212; or, the first opening is located on the top surface of the trench filling structure 212 to expose Part or all of the top surface of the first conductive metal layer 2124 of the trench filling structure 212; or, the first opening simultaneously exposes the first conductive metal on the top sidewall of the trench filling structure 212 The layer 2124 and part or all of the top surface of the first conductive metal layer 2124 of the trench filling structure 212.
  • FIGS. 3e to 3i, FIGS. 4a to 4e and FIGS. 5a to 5e show examples in which the top surface of the trench filling structure 212 is flush with the top surface of the substrate 20, as shown in FIGS. 6c to 6g It means that the top surface of the trench filling structure 212 is higher than the top surface of the substrate 20, and the first isolation oxide layer 2121, the high-K dielectric layer 2122, and the second isolation oxide layer 2123 still cover the Example on substrate 20.
  • the step of forming the first opening 2131 may include: forming a second patterned photoresist layer 261 on the buffer dielectric layer 25 (as shown in FIG. 3e), so that the second The patterned photoresist layer 261 is a mask, and the buffer medium layer 25 is etched to form the first opening 2131 in the buffer medium layer 25 of the pixel region 21, and the first opening 2131 A portion of the substrate 20 at the periphery of the top sidewall of the trench filling structure 212 and the entire top surface of the trench filling structure 212 are exposed, as shown in FIG. 3f.
  • the step of forming the first opening 2132 may include: forming a second patterned photoresist layer 262 on the buffer dielectric layer 25 (as shown in FIG. 4a), so as to The second patterned photoresist layer 262 is a mask, and the buffer dielectric layer 25 is etched to form the first opening 2132 in the buffer dielectric layer 25 of the pixel region 21.
  • the opening 2132 exposes part of the top surface of the trench filling structure 212, for example, the top surface of the part of the filling material, as shown in FIG. 4b, the filling material is the first conductive metal layer 2124, Then, the first opening 2132 exposes the top surface of the portion of the first conductive metal layer 2124 of the trench filling structure 212.
  • the step of forming the first opening 2133 may include: forming a second patterned photoresist layer 263 on the buffer dielectric layer 25 (as shown in FIG. 5a), so that the The second patterned photoresist layer 263 is a mask, and the buffer dielectric layer 25 is etched to form the first opening 2133 in the buffer dielectric layer 25 of the pixel area 21, as shown in FIG. 5b As shown, the first opening 2133 exposes a portion of the substrate 20 around the top sidewall of the trench filling structure 212.
  • the step of forming the first opening 2134 may include: forming a second patterned photoresist layer 264 on the buffer dielectric layer 25 (as shown in FIG. 6c), so that the The second patterned photoresist layer 264 is used as a mask to etch the buffer dielectric layer 25, the second isolation oxide layer 2123, the high-K dielectric layer 2122, and the first isolation oxide layer 2121 covering the substrate 20 Etching to form the first opening 2134 in the buffer dielectric layer 25 of the pixel region 21, and the first opening 2134 exposes a portion of the substrate 20 and the outer periphery of the top sidewall of the trench filling structure 212 On the entire top surface of the trench filling structure 212, as shown in FIG. 6d, the height of the first conductive metal layer 2124 after etching is still higher than that of the substrate 20, so that the first opening 2134 is still exposed The sidewalls of the top of the first conductive metal layer 2124 are exposed.
  • the second patterned photoresist layer is removed.
  • a metal grid layer is formed on the buffer medium layer 25, and the metal grid layer fills the first opening so as to interact with the exposed portion of the substrate 20 or the trench filling structure 212 It is electrically connected, or, at the same time, electrically connected to the exposed portion of the substrate 20 and the trench filling structure 212.
  • the metal grid layer can be electrically connected to the exposed portion of the substrate 20 and/or the trench filling structure 212, the electrical performance of the semiconductor device can be optimized and improved, such as optimization and improvement. Dark current of semiconductor devices.
  • the high-K dielectric layer 2122 further reduces the dark current of the semiconductor device, thereby further optimizing and improving the electrical performance of the semiconductor device.
  • the metal grid layer is only electrically connected to the exposed part of the substrate 20; when the first opening at least exposes the groove
  • the corresponding situation that the metal grid layer is electrically connected to the underlying structure includes: when the top surface of the trench filling structure 212 is high On the top surface of the substrate 20, and the first opening is only opened around the top sidewall of the trench filling structure 212 (that is, exposing the first isolation oxide layer 2121 on the top sidewall), then the metal The grid layer is also only electrically connected to the exposed part of the substrate 20; when only the top surface of the filling material in the trench filling structure 212 is higher than the top surface of the substrate 20, and the second An opening is only opened around the top sidewall of the trench filling structure 212.
  • the filling material is the first conductive metal layer 2124, the metal grid layer and the top sidewall of the trench filling structure 212
  • the upper first conductive metal layer 2124 is electrically connected; when the top surface of the trench filling structure 212 is higher than or equal to the top surface of the substrate 20, and the first opening is located in the trench filling structure 212
  • the top surface of 2124 is electrically connected; when the top surface of the trench filling structure 212 is higher than the top surface of the substrate 20, and the first opening simultaneously exposes the top sidewall of the trench filling structure 212
  • the isolation oxide layer 2121 or the first conductive metal layer 2124 on the upper surface and part or all of the top surface of the first conductive metal layer 2124 are exposed, the metal grid layer is simultaneously connected to the part of the substrate 20 and the first The conductive metal layer 2124 is electrically connected.
  • the method of forming the metal grid layer on the buffer medium layer 25 may be include:
  • the step of forming the metal grid layer 2141 on the buffer dielectric layer 25 includes: first, as shown in FIG. 3g, a second conductive metal layer 27 is formed to cover the buffer dielectric layer 25 , And the second conductive metal layer 27 fills the first opening 2131; then, a third patterned photoresist layer 281 is formed on the second conductive metal layer 27 (as shown in FIG. 3h) Using the third patterned photoresist layer 281 as a mask, the second conductive metal layer 27 is etched to form a metal grid layer 2141 in the pixel area 21 (as shown in FIG.
  • the metal grid layer 2141 and the first opening 2131 exposed a portion of the substrate 20 on the periphery of the top sidewall of the trench filling structure 212 and the entire top surface of the trench filling structure 212 ( That is, all the top surfaces of the conductive material of the trench filling structure 212 are electrically connected.
  • the step of forming the metal grid layer 2142 on the buffer medium layer 25 includes: first, as shown in FIG. 4c, a second conductive metal layer 27 is formed to cover the buffer medium layer 25, and the second conductive metal layer 27 fills the first opening 2132; then, a third patterned photoresist layer 282 is formed on the second conductive metal layer 27 (as shown in FIG. 4d) (Shown), using the third patterned photoresist layer 282 as a mask, the second conductive metal layer 27 is etched to form a metal grid layer 2142 in the pixel area 21 (as shown in FIG. 4e (Shown), the metal grid layer 2142 is electrically connected to the top surface of the portion of the first conductive metal layer 2124 of the trench filling structure 212 exposed by the first opening 2132.
  • the step of forming the metal grid layer 2143 on the buffer medium layer 25 includes: first, as shown in FIG. 5c, a second conductive metal layer 27 is formed to cover the buffer medium layer 25, and the second conductive metal layer 27 fills the first opening 2133; then, a third patterned photoresist layer 283 is formed on the second conductive metal layer 27 (as shown in FIG. 5d) (Shown), using the third patterned photoresist layer 283 as a mask to etch the second conductive metal layer 27 to form a metal grid layer 2143 in the pixel area 21 (as shown in FIG. 5e (Shown), the metal grid layer 2143 is electrically connected to a portion of the substrate 20 on the periphery of the top sidewall of the trench filling structure 212 exposed by the first opening 2133.
  • the step of forming the metal grid layer 2144 on the buffer medium layer 25 includes: first, as shown in FIG. 6e, a second conductive metal layer 27 is formed to cover the buffer medium layer 25, and the second conductive metal layer 27 fills the first opening 2134; then, a third patterned photoresist layer 284 is formed on the second conductive metal layer 27 (as shown in FIG. 6f) (Shown), using the third patterned photoresist layer 284 as a mask to etch the second conductive metal layer 27 to form a metal grid layer 2144 in the pixel area 21 (as shown in FIG.
  • the metal grid layer 2144 and the part of the substrate 20 at the periphery of the top sidewall of the trench filling structure 212 exposed by the first opening 2134 and the entire top of the trench filling structure 212 The surface is electrically connected, and the metal grid layer 2144 is also in contact with the sidewall of the top of the first conductive metal layer 2124.
  • the material of the second conductive metal layer 27 may include at least one of nickel, aluminum, silver, gold, titanium, and copper.
  • the metal grid layer 2145 may also be in contact with a portion of the substrate 20 on the periphery of the top sidewall of the trench filling structure 212 exposed by the first opening and the trench filling structure The top surface of the portion of the first conductive metal layer 2124 of 212 is electrically connected.
  • the substrate further has a pad area located at the periphery of the pixel area, and a metal interconnect structure and a plug structure located above the metal interconnect structure are formed in the substrate of the pad area.
  • the bottom of the plug structure is electrically connected with the metal interconnection structure, and the top of the plug structure is also electrically connected with a pad structure.
  • other metal structures other than the metal interconnection structure may also be formed in the substrate of the pad area, and the bottom of the plug structure is electrically connected to the metal structure; for example,
  • the metal structure may be a conductive contact plug, and the bottom of the plug structure is electrically connected to the conductive contact plug.
  • the metal structure is a metal interconnection structure.
  • the high-K dielectric layer When the high-K dielectric layer is formed in the plug structure of the pad area, the capacitance of the device will increase, which in turn will cause serious transmission delay (RC delay), and the performance of the semiconductor device will be affected. Therefore, the high-K dielectric layer cannot be formed in the plug structure of the pad area, so the trench filling structure of the pixel area and the plug structure of the pad area need to be fabricated separately.
  • RC delay transmission delay
  • the step of forming each structure of the pad area may include: after forming the trench filling structure and before covering the buffer medium layer on the substrate surface of the pixel area, forming the plug structure on the substrate surface of the pixel area.
  • the pad area In the substrate of the pad area; while covering the buffer dielectric layer on the substrate surface of the pixel area, it also covers the buffer dielectric layer on the substrate surface of the pad area to So that the buffer dielectric layer bury the plug structure; while etching the buffer dielectric layer on the pixel area to form the first opening, the pad area is also etched
  • the buffer medium layer to form a second opening that exposes the top surface of the part of the plug structure; and, when the metal grid layer is formed in the buffer in the pixel area, the second opening exposes the top surface of the plug structure.
  • a pad structure is also formed on the buffer dielectric layer of the pad area, and the pad structure fills the second opening so as to be in contact with the exposed top of the plug structure Electrical connection.
  • a substrate 20 having a pixel area 21 and a pad area 22 is provided, and the pad area 22 is located at the periphery of the pixel area 21.
  • a metal interconnect structure 221 is formed in the substrate 20 of the pad area 22.
  • a trench 211 is formed in the substrate 20 of the pixel region 21, and a filling material is filled in the trench 211 to form a trench filling structure 212.
  • the filling material A high-K dielectric layer 2122 is sandwiched between the sidewall of the substrate 20 and the substrate 20.
  • the step of forming the trench 211 and the trench filling structure 212 in the substrate 20 of the pixel region 21 includes: first, as shown in FIG. 8a, a pad oxide layer 23 is covered in the pixel region 21 And the pad area 22 on the surface of the substrate 20, the pad oxide layer 23 is used to protect the surface of the substrate 20 when the first patterned photoresist layer 24 is formed by subsequent photolithography; then, As shown in FIGS.
  • a first patterned photoresist layer 24 is formed on the pad oxide layer 23, and the first patterned photoresist layer 24 is used as a mask for the pixel area
  • the pad oxide layer 23 of 21 and at least a part of the thickness of the substrate 20 are etched to form trenches 211 in the substrate 20 of the pixel region 21; then, the first patterned photoresist is removed Layer 24 and pad oxide layer 23; then, sequentially form a first isolation oxide layer 2121, a high-K dielectric layer 2122, and a second isolation oxide layer 2123 on the surface of the trench 211 and the substrate 20, and fill all
  • the first conductive metal layer 2124 (that is, the filling material) is in the trench 211, and the first conductive metal layer 2124 also covers the second isolation oxide layer 2123 on the periphery of the trench 211 ;
  • an etching or chemical mechanical polishing process is used to remove the first conductive metal layer 2124 covering the surface of the substrate 20 on the periphery of the trench 211 to
  • the plug structure 224 is formed in the substrate 20 of the pad region 22.
  • the steps may include: first, as shown in FIG. 8d, a first buffer medium layer 251 is covered on the surface of the substrate 20 of the pixel region 21 and the pad region 22, and the first buffer medium layer 251 is placed on the surface of the substrate 20.
  • the trench filling structure 212 is buried; then, a fourth patterned photoresist layer 29 is formed on the first buffer dielectric layer 251 (as shown in FIG.
  • the resist layer 29 is a mask to etch the first buffer dielectric layer 251, the second isolation oxide layer 2123, the high-K dielectric layer 2122, and the first isolation oxide layer 2121 on the pad area 22 to
  • a third opening 222 is formed in the first buffer dielectric layer 251 on the pad area 22 (as shown in FIG. 8f), and the third opening 222 exposes a part of the top of the substrate 20 above the metal interconnect structure 221.
  • a second buffer medium layer 252 is filled in the third opening 222, and the second buffer medium layer 252 covers the first buffer medium layer 251;
  • the fifth patterned photoresist layer 30 is on the second buffer dielectric layer 252 (as shown in FIG. 8h).
  • the third The second buffer dielectric layer 252 in the opening 222 and at least a part of the thickness of the substrate 20 are etched to form a through hole 223 in the second buffer dielectric layer 252 on the pad area 22 and the substrate 20, As shown in FIG.
  • the through hole 223 exposes at least a part of the top surface of the metal interconnect structure 221; then, a third isolation oxide layer 2241 is formed on the sidewall of the through hole 223, and the first A three isolation oxide layer 2241 covers the substrate 20; then, a third conductive metal layer 2242 is filled in the through hole 223, and the third conductive metal layer 2242 also covers the periphery of the through hole 223 On the third isolation oxide layer 2241; then, an etching or chemical mechanical polishing process is used to remove the third conductive metal layer 2242 and the third isolation oxide layer on the substrate 20 covering the periphery of the through hole 223 2241 to form a plug structure 224.
  • the bottom of the third conductive metal layer 2242 in the plug structure 224 is electrically connected to the metal interconnect structure 221, as shown in FIG. 8j.
  • the third opening 222 is first formed to expose part of the top surface of the substrate 20 above the metal interconnect structure 221; then the second buffer dielectric layer 252 is filled in the third opening 222, And the second buffer medium layer 252 covers the first buffer medium layer 251; then the second buffer medium layer 252 in the third opening 222 and at least a part of the thickness of the substrate 20 are etched
  • the accuracy and reliability of the etching process for forming the through hole 223 can be improved.
  • the first buffer dielectric layer 251 and at least a part of the thickness of the substrate 20 may also be directly etched to form the through hole 223, that is, the third opening is no longer formed 222, which can simplify the manufacturing process.
  • a third buffer dielectric layer 253 is covered on the surface of the substrate 20 of the pixel region 21 and the pad region 22, and the third buffer dielectric layer 253 covers the plug structure 224 Buried in.
  • the first isolation oxide layer 2121 covering the substrate 20 and burying the trench filling structure 212 and the plug structure 224 The dielectric layer 2122, the second isolation oxide layer 2123, the first buffer dielectric layer 251, the second buffer dielectric layer 252 and the third buffer dielectric layer 253 constitute the buffer dielectric layer 25.
  • the buffer medium layer is etched to form a first opening 2134 in the buffer medium layer of the pixel region 21 and a second opening 2134 in the buffer medium layer of the pad region 22 Two openings 225.
  • the first opening 2134 exposes a portion of the substrate 20 at the periphery of the top sidewall of the trench filling structure 212 and the entire top surface of the trench filling structure 212, and the second opening 225 exposes The top surface of the part of the plug structure 224 is shown.
  • the step of forming the first opening 2134 and the second opening 225 may include: forming a second patterned photoresist layer 264 on the third buffer dielectric layer 253 (as shown in FIG.
  • the second patterned photoresist layer 264 is a mask, and the third buffer dielectric layer 253, the first buffer dielectric layer 251, the second isolation oxide layer 2123, the high-K dielectric layer 2122 and the The first isolation oxide layer 2121 is etched, and the third buffer dielectric layer 253 on the pad region 22 is etched to form the first opening in the buffer dielectric layer of the pixel region 21 2134 and a second opening 225 is formed in the buffer dielectric layer of the pad area 22.
  • a second patterned photoresist layer 264 is a mask
  • the third buffer dielectric layer 253, the first buffer dielectric layer 251, the second isolation oxide layer 2123, the high-K dielectric layer 2122 and the The first isolation oxide layer 2121 is etched, and the third buffer dielectric layer 253 on the pad region 22 is etched
  • the first opening 2134 exposes part of the substrate around the top sidewall of the trench filling structure 212 20 and the entire top surface of the trench filling structure 212, the first opening 2134 also exposes the sidewall of the top of the first conductive metal layer 2124, and the second opening 225 exposes the insert The top surface of the portion of the third conductive metal layer 2242 of the plug structure 224.
  • a metal grid layer 2144 is formed on the third buffer medium layer 253 of the pixel area 21 and a pad structure 226 is formed on the third buffer medium of the pad area 22
  • the metal grid layer 2144 fills the first opening 2134 to be electrically connected to the exposed portion of the substrate 20 and the trench filling structure 212; the pad structure 226 fills The second opening 225 is filled to electrically connect with the exposed top of the plug structure 224.
  • the steps of forming a metal grid layer 2144 on the third buffer dielectric layer 253 of the pixel region 21 and forming a pad structure 226 on the third buffer dielectric layer 253 of the pad region 22 include: first, as As shown in FIG. 8n, a second conductive metal layer 27 is formed to cover the third buffer dielectric layer 253, and the second conductive metal layer 27 fills the first opening 2134 and the second opening 225; Then, a third patterned photoresist layer 284 is formed on the second conductive metal layer 27 (as shown in FIG. 8o), and the third patterned photoresist layer 284 is used as a mask.
  • the second conductive metal layer 27 is etched to form a metal grid layer 2144 in the pixel area 21 and a pad structure 226 in the pad area 22 (as shown in FIG. 8p).
  • the layer 2144 is electrically connected to the part of the substrate 20 on the periphery of the top sidewall of the trench filling structure 212 exposed by the first opening 2134 and the entire top surface of the trench filling structure 212, and the pad
  • the structure 226 is electrically connected to the exposed top surface of the portion of the third conductive metal layer 2242 of the plug structure 224.
  • the various steps in the above-mentioned semiconductor device manufacturing method are not limited to the above-mentioned formation sequence, and the sequence of the various steps can be adjusted adaptively.
  • the method for manufacturing a semiconductor device includes: providing a substrate with a pixel region; forming a trench in the substrate of the pixel region, and filling the trench with a filling material, To form a trench filling structure, a high-K dielectric layer is sandwiched between the sidewall of the filling material and the substrate; the buffer dielectric layer is covered on the surface of the substrate in the pixel area, and the buffer dielectric layer The trench filling structure is buried; the buffer dielectric layer is etched to form a first opening that exposes at least part of the substrate and/or the periphery of the top sidewall of the trench filling structure Or at least part of the top of the trench filling structure; and forming a metal grid layer on the buffer dielectric layer, and the metal grid layer fills the first opening so as to be in contact with the exposed part of the substrate And/or the trench filling structure is electrically connected.
  • the manufacturing method of the semiconductor device of the present invention enables the metal grid layer to be electrically connected to the exposed
  • An embodiment of the present invention provides a semiconductor device.
  • the semiconductor device includes a substrate, a trench filling structure, a buffer dielectric layer, and a metal grid layer.
  • the substrate has a pixel area; the trench filling structure is formed in In the substrate of the pixel area, the trench filling structure includes a filling material filled in the trench in the substrate and a filling material sandwiched between the sidewall of the filling material and the substrate.
  • the buffer dielectric layer is formed on the surface of the substrate of the pixel area, the buffer dielectric layer has a first opening, and the first opening exposes at least the top sidewall of the trench filling structure
  • the metal grid layer is formed on the buffer dielectric layer, and the metal grid layer fills the first opening so as to be exposed
  • the part of the substrate and/or the trench filling structure is electrically connected.
  • the substrate 20 has a pixel area 21, and the material of the substrate 20 can be any suitable substrate known to those skilled in the art. For details, refer to step S11, which will not be repeated here.
  • the trench filling structure 212 is formed in the substrate 20 of the pixel region 21.
  • the trench filling structure 212 includes a filling material filled in the trench 211 in the substrate 20 and a high-K dielectric layer 2122 sandwiched between the sidewall of the filling material and the substrate 20 .
  • the trench 211 may be a deep trench with a depth of 1 ⁇ m to 5 ⁇ m. It should be noted that the depth of the trench 211 is not limited to this depth range, and a suitable depth may be formed according to the performance requirements of the semiconductor device. ⁇ 211 ⁇ Groove 211.
  • the trench filling structure 212 may play a role in isolating various devices in the substrate 20 of the pixel region 21.
  • the K (dielectric constant) value of the high-K dielectric layer 2122 is preferably greater than 7, and the material of the high-K dielectric layer 2122 may include nitride or metal oxide, such as silicon nitride, silicon oxynitride, or titanium dioxide. , Tantalum pentoxide, etc.
  • the high-K dielectric layer 2122 has different frequency band voltages and charges with different properties, so that the high-K dielectric layer 2122 can change the charge in the substrate 20, thereby reducing dark current and avoiding dark current. The generated noise affects the performance of the semiconductor device.
  • the trench filling structure 212 may include a first isolation oxide layer 2121, a high-K dielectric layer 2122, and a second isolation oxide layer 2123 that sequentially cover the surface of the trench 211 in the substrate 20.
  • the filling material in the trench 211, the first isolation oxide layer 2121, the high-K dielectric layer 2122, and the second isolation oxide layer 2123 are at least located between the sidewall of the filling material and the substrate 20, namely
  • the first isolation oxide layer 2121, the high-K dielectric layer 2122, and the second isolation oxide layer 2123 in the trench 211 may be located only on the sidewalls of the trench 211, or both may be located on the side of the trench 211 On the wall and bottom wall.
  • the filling material may include a dielectric material or a metal material, or both a dielectric material and a metal material; when the filling material is a metal material, as shown in FIG. 3i, the trench filling structure 212 includes The first isolation oxide layer 2121 on the surface of the trench 211, the high-K dielectric layer 2122, the second isolation oxide layer 2123, and the first conductive metal layer 2124 filling the trench 211 (that is, the filling material is the The first conductive metal layer 2124).
  • the dielectric material may include at least one of silicon dioxide, silicon nitride, tetraethyl orthosilicate, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, and silicon oxynitride, and the metal material may include tungsten, At least one of nickel, aluminum, silver, gold, and titanium.
  • top surface of the trench filling structure 212 may be flush with the top surface of the substrate 20, or the top surface of the trench filling structure 212 may be higher than the top surface of the substrate 20, or, Only the top surface of the filling material in the trench filling structure 212 is higher than the top surface of the substrate 20.
  • the buffer medium layer 25 is formed on the surface of the substrate 20 of the pixel region 21, the buffer medium layer 25 has a first opening, and the first opening exposes at least the top sidewall of the trench filling structure 212 A portion of the substrate 20 on the periphery or at least a portion of the top of the trench filling structure 212, or at least a portion of the substrate 20 on the periphery of the top sidewall of the trench filling structure 212 and the trench filling structure 212 are exposed At least part of the top.
  • the first opening exposes at least a portion of the substrate 20 at the periphery of the top sidewall of the trench filling structure 212, that is, the first opening is disposed at least around the top periphery of the trench filling structure 212 , To expose at least a portion of the substrate 20 surrounding the top periphery of the trench filling structure 212.
  • the situation where the first opening exposes at least part of the top of the trench filling structure 212 includes: when the top surface of the trench filling structure 212 is higher than the top surface of the substrate 20, the first opening It is possible to open only around the top sidewall of the trench filling structure 212 to expose the first isolation oxide layer 2121 on the top sidewall of the trench filling structure 212.
  • the first opening also exposes Part of the substrate 20 at the periphery of the top sidewall of the trench filling structure 212; when only the top surface of the filling material in the trench filling structure 212 is higher than the top surface of the substrate 20, the first The opening may only be opened around the top sidewall of the trench filling structure 212 to expose the filling material on the top sidewall of the trench filling structure 212; when the top surface of the trench filling structure 212 is higher than or When equal to the top surface of the substrate 20, the first opening may also be located on the top surface of the trench filling structure 212 to expose part or all of the top surface of the trench filling structure 212, including Expose part or all of the top surface of the filling material, or expose part or all of the top surface of the filling material, and expose the first isolation oxide layer 2121 and/or the high-K dielectric layer 2122 and /Or part or all of the top surface of the second isolation oxide layer 2123; when the top surface of the trench filling structure 212 is higher than
  • the situation where the first opening exposes at least a part of the top of the trench filling structure 212 includes: the first opening surrounds the trench filling structure 212 The top sidewall is opened to expose the first conductive metal layer 2124 on the top sidewall of the trench filling structure 212; or, the first opening is located on the top surface of the trench filling structure 212 to expose Part or all of the top surface of the first conductive metal layer 2124 of the trench filling structure 212; or, the first opening simultaneously exposes the first conductive metal on the top sidewall of the trench filling structure 212 The layer 2124 and part or all of the top surface of the first conductive metal layer 2124 of the trench filling structure 212.
  • the metal grid layer is formed on the buffer dielectric layer 25, and the metal grid layer fills the first opening so as to be electrically connected to the exposed portion of the substrate 20 or the trench filling structure , Or, electrically connected to the exposed portion of the substrate 20 and the trench filling structure 212 at the same time.
  • the metal grid layer can be electrically connected to the exposed portion of the substrate 20 and/or the trench filling structure 212, the electrical performance of the semiconductor device can be optimized and improved, such as optimization and improvement. Dark current of semiconductor devices.
  • the high-K dielectric layer further reduces the dark current of the semiconductor device, thereby further optimizing and improving the electrical performance of the semiconductor device.
  • the metal grid layer is only electrically connected to the exposed part of the substrate 20; when the first opening at least exposes the groove
  • the corresponding situation where the metal grid layer is electrically connected to the underlying structure includes: when the top surface of the trench filling structure 212 is higher than all The top surface of the substrate 20, and the first opening is only opened around the top sidewall of the trench filling structure 212 (that is, exposing the first isolation oxide layer 2121 on the top sidewall), then the metal grid The layer is also only electrically connected to the exposed part of the substrate 20; when only the top surface of the filling material in the trench filling structure 212 is higher than the top surface of the substrate 20, and the first opening It is opened only around the top sidewall of the trench filling structure 212.
  • the filling material is the first conductive metal layer 2124, the metal grid layer and the top sidewall of the trench filling structure 212
  • the first conductive metal layer 2124 is electrically connected; when the top surface of the trench filling structure 212 is higher than or equal to the top surface of the substrate 20, and the first opening is located in the filling of the trench filling structure 212
  • the top surface is electrically connected; when the top surface of the trench filling structure 212 is higher than the top surface of the substrate 20, and the first opening simultaneously exposes the top sidewall of the trench filling structure 212
  • the metal grid layer is simultaneously connected to the part of the substrate 20 and the first conductive metal.
  • the layer 2124 is electrically connected.
  • the metal grid layer 2141 is electrically connected to the The part of the substrate 20 at the periphery of the top sidewall of the trench-filled structure 212 exposed by the first opening 2131 is electrically connected to the entire top surface of the trench-filled structure 212; as shown in FIG. 4e, the metal The grid layer 2142 is electrically connected to the top surface of the portion of the first conductive metal layer 2124 of the trench filling structure 212 exposed by the first opening 2132; as shown in FIG.
  • the metal grid layer 2143 Is electrically connected to a portion of the substrate 20 on the periphery of the top sidewall of the trench filling structure 212 exposed by the first opening 2133; as shown in FIG. 6g, the metal grid layer 2144 is connected to the first opening
  • the part of the substrate 20 at the periphery of the top sidewall of the trench filling structure 212 exposed by 2134 is electrically connected to the entire top surface of the trench filling structure 212, and the metal grid layer 2144 is also connected to the The top sidewall of the first conductive metal layer 2124 is in contact with each other; as shown in FIG.
  • the metal grid layer 2145 is in contact with a portion of the outer periphery of the top sidewall of the trench filling structure 212 exposed by the first opening.
  • the bottom 20 and the top surface of the portion of the first conductive metal layer 2124 of the trench filling structure 212 are electrically connected.
  • the substrate further has a pad area located at the periphery of the pixel area, and a metal interconnect structure and a plug structure located above the metal interconnect structure are formed in the substrate of the pad area.
  • the bottom of the plug structure is electrically connected with the metal interconnection structure, and the top of the plug structure is also electrically connected with a pad structure.
  • other metal structures other than the metal interconnection structure may also be formed in the substrate of the pad area, and the bottom of the plug structure is electrically connected to the metal structure; for example,
  • the metal structure may be a conductive contact plug, and the bottom of the plug structure is electrically connected to the conductive contact plug.
  • the metal structure is a metal interconnection structure.
  • the plug structure includes: a third isolation oxide layer on the sidewall of the through hole exposing a part of the top surface of the metal interconnect structure, and a third conductive metal layer filling the through hole.
  • the buffer dielectric layer is also formed on the substrate surface of the pad region, and the buffer dielectric layer has a second opening exposing the top surface of the portion of the plug structure; the buffer of the pad region A pad structure is also formed on the dielectric layer, and the pad structure fills the second opening to be electrically connected to the exposed top of the plug structure.
  • the capacitance of the device will increase, which will cause serious transmission delay (RC delay), and the performance of the semiconductor device will be affected. Therefore, the The high-K dielectric layer cannot be formed in the plug structure of the pad area.
  • the metal grid layer of the pixel area is electrically connected to the exposed part of the substrate and/or the trench filling structure, please refer to the above description, and will not be repeated here.
  • a portion of the substrate 20 and the outer periphery of the top sidewall of the trench filling structure 212 exposed by the metal grid layer 2144 and the first opening 2134 and the trench filling structure 212 The case where all the top surfaces are electrically connected as an example, the trench filling structure 212 and the metal grid layer 2144 of the pixel region 21 and the plug structure 224 and the pad structure 226 of the pad region 22 are described:
  • the plug structure 224 includes: a third isolation oxide layer 2241 on the sidewall of the through hole 223 exposing a portion of the top surface of the metal interconnect structure 221, and a third conductive oxide layer 2241 filling the through hole 223 Metal layer 2242.
  • the bottom of the third conductive metal layer 2242 in the plug structure 224 is electrically connected to the metal interconnect structure 221.
  • the first buffer medium layer 251, the second buffer medium layer 252 and the third buffer medium layer 253 constitute the buffer medium layer 25.
  • a first opening 2134 is formed in the dielectric layer 253) and a second opening 225 is formed in the buffer dielectric layer 25 (ie, the third buffer dielectric layer 253) of the pad area 22, and the first opening 2134 is exposed A portion of the substrate 20 at the periphery of the top sidewall of the trench filling structure 212 and the entire top surface of the trench filling structure 212 are exposed, and the first opening 2134 also exposes the first conductive metal layer 2124
  • the second opening 225 exposes the top surface of the part of the third conductive metal layer 2242 of the plug structure 224.
  • a metal grid layer 2144 is formed on the buffer medium layer 25 (that is, the third buffer medium layer 253) of the pixel region 21, and a pad structure 226 is formed on the buffer medium layer 25 of the pad region 22.
  • the metal grid layer 2144 fills the first opening 2134 to be electrically connected to the exposed portion of the substrate 20 and the trench filling structure 212; the pad structure 226 fills the second
  • the opening 225 is electrically connected to the exposed top of the plug structure 224.
  • the semiconductor device includes: a substrate having a pixel area; a trench filling structure formed in the substrate of the pixel area, and the trench filling structure includes filling in the substrate The filling material in the trench in the bottom and the high-K dielectric layer sandwiched between the sidewall of the filling material and the substrate; the buffer dielectric layer is formed on the surface of the substrate in the pixel area, so The buffer dielectric layer has a first opening that exposes at least a portion of the substrate surrounding the top sidewall of the trench-filled structure and/or at least a portion of the top of the trench-filled structure; and, a metal gate
  • the grid layer is formed on the buffer dielectric layer, and the metal grid layer fills the first opening to be electrically connected to the exposed portion of the substrate and/or the trench filling structure.
  • the semiconductor device of the present invention electrically connects the metal grid layer with the exposed part of the substrate and/or the trench filling structure, thereby enabling the optimization and improvement of the electrical performance of the semiconductor device.

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Abstract

一种半导体器件及其制造方法，所述半导体器件的制造方法包括：形成沟槽填充结构于像素区的衬底中，且沟槽填充结构中的填充材料的侧壁和衬底之间还夹有高K介质层（S12）；覆盖缓冲介质层于像素区的衬底表面上，且缓冲介质层将沟槽填充结构掩埋在内（S13）；刻蚀缓冲介质层，以形成至少暴露出沟槽填充结构的顶部侧壁外围的部分衬底和/或沟槽填充结构的至少部分顶部的第一开口（S14）；以及，形成金属栅格层于缓冲介质层上且填充第一开口，以与暴露出的部分衬底和/或沟槽填充结构电性连接（S15）。所述半导体器件及其制造方法使得金属栅格层与暴露出的部分衬底和/或沟槽填充结构电性连接，进而使得能够对半导体器件进行电学性能方面的优化和改善。

Description

半导体器件及其制造方法 技术领域
本发明涉及半导体集成电路制造领域，特别涉及一种半导体器件及其制造方法。
背景技术
在背照式CMOS图像传感器(Back-side Illuminated CMOS Image Sensor，简称BSI-CIS)的制作工艺中，深沟槽隔离(Deep Trench Isolation，简称DTI)技术和背面金属栅格(Backside Metal Grid，简称BMG)技术的配合使用能够使得背照式CMOS图像传感器具有更好的光学性能。
但是，在现有的制作背照式CMOS图像传感器的工艺过程中，制作的像素区的金属栅格与下方的衬底和深沟槽填充结构之间存在缓冲介质层，使得金属栅格与下方的衬底和深沟槽填充结构之间仅是物理连接，无法进行电性连接，从而导致无法对背照式CMOS图像传感器进行电学性能方面的优化和改善。
因此，如何对像素区的金属栅格的制作工艺进行改进，以使得金属栅格与下方的衬底和/或沟槽填充结构之间实现电性连接，进而使得能够对半导体器件进行电学性能方面的优化和改善是目前亟需解决的问题。
发明内容
本发明的目的在于提供一种半导体器件及其制造方法，使得金属栅格层与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接，进而使得能够对半导体器件进行电学性能方面的优化和改善。
为实现上述目的，本发明提供了一种半导体器件的制造方法，包括：
提供一具有像素区的衬底；
形成沟槽于所述像素区的衬底中，并在所述沟槽中填充填充材料，且在所述填充材料的侧壁和所述衬底之间形成有高K介质层，以形成沟槽填充结 构；
覆盖缓冲介质层于所述像素区的衬底表面上，且所述缓冲介质层将所述沟槽填充结构掩埋在内；
刻蚀所述缓冲介质层，以形成第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，
形成金属栅格层于所述缓冲介质层上，所述金属栅格层填充所述第一开口，以与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接。
可选的，形成所述沟槽以及所述沟槽填充结构于所述像素区的衬底中的步骤包括：
覆盖垫氧化层于所述像素区的衬底表面上；
形成第一图案化的光刻胶层于所述垫氧化层上，以所述第一图案化的光刻胶层为掩膜，对所述垫氧化层以及至少部分厚度的所述衬底进行刻蚀，以形成沟槽于所述像素区的衬底中；
去除所述第一图案化的光刻胶层和垫氧化层；
依次形成第一隔离氧化层、高K介质层和第二隔离氧化层于所述沟槽和所述衬底的表面上；
填充所述填充材料于所述沟槽中，且所述填充材料还覆盖在所述沟槽外的所述第二隔离氧化层上；以及，
采用刻蚀或者化学机械研磨工艺去除覆盖于所述沟槽外的所述衬底的表面上的所述填充材料、第二隔离氧化层、高K介质层和第一隔离氧化层，或者，仅去除覆盖于所述沟槽外的所述衬底的表面上的所述填充材料，以在所述沟槽中形成沟槽填充结构。
可选的，所述填充材料包括第一导电金属层，所述第一开口至少暴露出所述沟槽填充结构的部分顶部包括：所述第一开口围绕所述沟槽填充结构的顶部侧壁开设，以暴露出所述沟槽填充结构的顶部侧壁上的第一导电金属层，和/或，所述第一开口位于所述沟槽填充结构的顶表面上，以暴露出所述沟槽填充结构的第一导电金属层的部分或全部的顶表面。
可选的，刻蚀所述缓冲介质层，以形成所述第一开口的步骤包括：
形成第二图案化的光刻胶层于所述缓冲介质层上，以所述第二图案化的光刻胶层为掩膜，对所述缓冲介质层进行刻蚀，以在所述像素区的缓冲介质层中形成所述第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，
去除所述第二图案化的光刻胶层。
可选的，形成所述金属栅格层于所述缓冲介质层上的步骤包括：
形成第二导电金属层覆盖于所述缓冲介质层上，且所述第二导电金属层将所述第一开口填满；
形成第三图案化的光刻胶层于所述第二导电金属层上，以所述第三图案化的光刻胶层为掩膜，对所述第二导电金属层进行刻蚀，以在所述像素区形成金属栅格层，所述金属栅格层与所述第一开口暴露出的所述部分衬底和/或所述沟槽填充结构电性连接；以及，
去除所述第三图案化的光刻胶层。
可选的，所述衬底还具有位于所述像素区外围的焊盘区，所述焊盘区的衬底中形成有金属互连结构以及位于所述金属互连结构上方的插栓结构，所述插栓结构的底部与所述金属互连结构电性连接。
可选的，在形成所述沟槽填充结构之后且在覆盖所述缓冲介质层于所述像素区的衬底表面上之前，形成所述插栓结构于所述焊盘区的衬底中。
可选的，在覆盖所述缓冲介质层于所述像素区的衬底表面上的步骤中，所述缓冲介质层还延伸覆盖于所述焊盘区的衬底表面上，以使得所述缓冲介质层将所述插栓结构掩埋在内；在刻蚀所述像素区上的所述缓冲介质层，以形成所述第一开口的同时，还刻蚀所述焊盘区上的所述缓冲介质层，以形成第二开口，所述第二开口暴露出所述插栓结构的部分的顶部表面；以及，在形成所述金属栅格层于所述像素区的所述缓冲介质层上的同时，还形成焊盘结构于所述焊盘区的所述缓冲介质层上，所述焊盘结构填满所述第二开口，以与暴露出的所述插栓结构的顶部电性连接。
本发明还提供了一种半导体器件，包括：
衬底，具有像素区，所述像素区的衬底中形成有沟槽；
沟槽填充结构，形成于所述像素区的衬底中，所述沟槽填充结构包括填充于所述沟槽中的填充材料以及位于所述填充材料的侧壁和所述衬底之间的高K介质层；
缓冲介质层，覆盖于所述像素区的衬底表面上，所述缓冲介质层具有第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，
金属栅格层，形成于所述缓冲介质层上，所述金属栅格层填充所述第一开口，以与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接。
可选的，所述沟槽填充结构包括依次覆盖于所述沟槽的表面上的第一隔离氧化层、所述高K介质层、第二隔离氧化层和填充于所述沟槽中的所述填充材料，所述第一隔离氧化层、高K介质层和第二隔离氧化层至少位于所述填充材料的侧壁和所述衬底之间。
可选的，所述填充材料包括第一导电金属层，所述第一开口至少暴露出所述沟槽填充结构的部分顶部包括：所述第一开口围绕所述沟槽填充结构的顶部侧壁开设，以暴露出所述沟槽填充结构的顶部侧壁上的第一导电金属层，和/或，所述第一开口位于所述沟槽填充结构的顶表面上，以暴露出所述沟槽填充结构的第一导电金属层的部分或全部的顶表面。
可选的，所述高K介质层的K值大于7。
可选的，所述衬底还具有位于所述像素区外围的焊盘区，所述焊盘区的衬底中形成有金属互连结构以及位于所述金属互连结构上方的插栓结构，所述插栓结构的底部与所述金属互连结构电性连接。
可选的，所述焊盘区的衬底中形成有通孔，所述通孔至少暴露出所述金属互连结构的部分顶表面，所述插栓结构包括：位于所述通孔的侧壁上的第三隔离氧化层，以及填满所述通孔的第三导电金属层。
可选的，所述缓冲介质层还延伸覆盖于所述焊盘区的衬底表面上，且所述缓冲介质层具有暴露出所述插栓结构的至少部分顶部的第二开口；所述焊盘区的缓冲介质层上还形成有焊盘结构，所述焊盘结构填满所述第二开口， 以与暴露出的所述插栓结构的顶部电性连接。
与现有技术相比，本发明的技术方案具有以下有益效果：
1、本发明的半导体器件的制造方法，通过形成沟槽填充结构于像素区的衬底中，且所述沟槽填充结构中的填充材料的侧壁和所述衬底之间还夹有高K介质层；覆盖缓冲介质层于所述像素区的衬底表面上，且所述缓冲介质层将所述沟槽填充结构掩埋在内；刻蚀所述缓冲介质层，以形成第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，形成金属栅格层于所述缓冲介质层上，所述金属栅格层填充所述第一开口，以使得所述金属栅格层与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接，进而使得能够对半导体器件进行电学性能方面的优化和改善；并且，所述填充材料的侧壁和所述衬底之间夹有的高K介质层也使得半导体器件的性能得到优化。
2、本发明的半导体器件，由于包括：形成于像素区的衬底中的沟槽填充结构，所述沟槽填充结构包含有填充于所述衬底中的沟槽中的填充材料以及夹设在所述填充材料的侧壁和所述衬底之间的高K介质层；形成于所述像素区的衬底表面上的缓冲介质层，所述缓冲介质层具有第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，形成于所述缓冲介质层上的金属栅格层，所述金属栅格层填充所述第一开口，以使得金属栅格层与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接，进而使得能够对半导体器件进行电学性能方面的优化和改善；并且，所述填充材料的侧壁和所述衬底之间夹有的高K介质层也使得半导体器件的性能得到优化。
附图说明
图1a～1f是一种半导体器件的制造过程中的器件示意图；
图2是本发明一实施例的半导体器件的制造方法的流程图；
图3a～3i是图2所示的半导体器件的制造方法中的实施例一的器件示意图；
图4a～4e是图2所示的半导体器件的制造方法中的实施例二的器件示意图；
图5a～5e是图2所示的半导体器件的制造方法中的实施例三的器件示意图；
图6a～6g是图2所示的半导体器件的制造方法中的实施例四的器件示意图；
图7是图2所示的半导体器件的制造方法中的实施例五的器件示意图；
图8a～8P是图2所示的半导体器件的制造方法中的实施例六的器件示意图。
其中，附图1a～8P的附图标记说明如下：
10-衬底；11-像素区；12-垫氧化层；13-第一图案化的光刻胶层；14-沟槽；15-沟槽填充结构；151-隔离氧化层；152-导电金属层；16-缓冲氧化层；17-金属栅格膜层；18-第二图案化的光刻胶层；19-金属栅格层；
20-衬底；21-像素区；211-沟槽；212-沟槽填充结构；2121-第一隔离氧化层；2122-高K介质层；2123-第二隔离氧化层；2124-第一导电金属层；2131、2132、2133、2134-第一开口；2141、2142、2143、2144、2145-金属栅格层；22-焊盘区；221-金属互连结构；222-第三开口；223-通孔；224-插栓结构；2241-第三隔离氧化层；2242-第三导电金属层；225-第二开口；226-焊盘结构；23-垫氧化层；24-第一图案化的光刻胶层；25-缓冲介质层；251-第一缓冲介质层；252-第二缓冲介质层；253-第三缓冲介质层；261、262、263、264-第二图案化的光刻胶层；27-第二导电金属层；281、282、283、284-第三图案化的光刻胶层；29-第四图案化的光刻胶层；30-第五图案化的光刻胶层。
具体实施方式
一种像素区的金属栅格层的制作工艺如下：
如图1a所示，提供一具有像素区11的衬底10；
如图1a和1b所示，在所述像素区11上形成一垫氧化层12，形成第一图案化的光刻胶层13于所述垫氧化层12上，以所述第一图案化的光刻胶层13 为掩膜，对所述像素区11上的垫氧化层12和部分厚度的所述衬底10进行刻蚀，以在所述像素区11的衬底10中形成沟槽14，去除所述第一图案化的光刻胶层13；
如图1c所示，形成隔离氧化层151于所述沟槽14的表面和所述垫氧化层12的表面，并填充导电金属层152于所述沟槽14中，且所述导电金属层152覆盖于所述垫氧化层12上，可以采用化学机械研磨工艺将覆盖于所述衬底10上的所述导电金属层152、隔离氧化层151和垫氧化层12去除，以得到位于所述沟槽14中的沟槽填充结构15，所述沟槽填充结构15包括所述隔离氧化层151和导电金属层152；
如图1d所示，依次形成缓冲氧化层16和金属栅格膜层17覆盖于所述衬底10上；
如图1e和1f所示，形成第二图案化的光刻胶层18于所述金属栅格膜层17上，以所述第二图案化的光刻胶层18为掩膜，对所述金属栅格膜层17进行刻蚀，以在所述缓冲氧化层16上形成金属栅格层19，去除所述第二图案化的光刻胶层18，其中，所述金属栅格层19对应位于所述沟槽填充结构15的上方。
显然，由上述步骤可知，像素区上的金属栅格层与下方的衬底和沟槽填充结构之间存在缓冲氧化层，使得金属栅格层与下方的衬底和沟槽填充结构之间仅是物理连接，无法进行电性连接，从而导致无法对半导体器件进行电学性能方面的优化和改善。因此，本发明提出了一种半导体器件及其制造方法，能够使得金属栅格层与下方的衬底和沟槽填充结构之间实现电性连接，进而使得能够对半导体器件进行电学性能方面的优化和改善。
为使本发明的目的、优点和特征更加清楚，以下结合附图2～8P对本发明提出的半导体器件及其制造方法作进一步详细说明。需说明的是，附图均采用非常简化的形式且均使用非精准的比例，仅用以方便、明晰地辅助说明本发明实施例的目的。
本发明一实施例提供一种半导体器件的制造方法，参阅图2，图2是本发 明一实施例的半导体器件的制造方法的流程图，所述半导体器件的制造方法包括：
步骤S11、提供一具有像素区的衬底；
步骤S12、形成沟槽于所述像素区的衬底中，并在所述沟槽中填充填充材料，以形成沟槽填充结构，所述填充材料的侧壁和所述衬底之间还夹有高K介质层；
步骤S13、覆盖缓冲介质层于所述像素区的衬底表面上，且所述缓冲介质层将所述沟槽填充结构掩埋在内；
步骤S14、刻蚀所述缓冲介质层，以形成第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；
步骤S15、形成金属栅格层于所述缓冲介质层上，所述金属栅格层填充所述第一开口，以与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接。
下面参阅图3a～8p更为详细的介绍本实施例提供的半导体器件的制造方法，图3a～8p也是半导体器件的纵向截面示意图。
按照步骤S11，提供一具有像素区21的衬底20。所述衬底20的材质可以为本领域技术人员熟知的任意合适的底材，例如可以是以下所提到的材料中的至少一种：硅(Si)、锗(Ge)、锗硅(SiGe)、碳硅(SiC)、碳锗硅(SiGeC)、砷化铟(InAs)、砷化镓(GaAs)、磷化铟(InP)或者其它III/V族化合物半导体。
按照步骤S12，形成沟槽211于所述像素区21的衬底20中，并在所述沟槽211中填充填充材料，以形成沟槽填充结构212，所述填充材料的侧壁和所述衬底20之间还夹有高K介质层2122。其中，所述沟槽211可以是深度为1μm～5μm的深沟槽，需要说明的是，所述沟槽211的深度不仅限于此深度范围，可以根据半导体器件的性能需求形成合适深度的所述沟槽211。所述沟槽填充结构212可以在所述像素区21的衬底20中起到隔离各器件的作用。所述高K介质层2122的K(介电常数)值优选为大于7，所述高K介质层2122的材质可以包括氮化物或者金属氧化物，例如可以为氮化硅、氮氧硅、二氧化钛、五氧化二钽等。所述高K介质层2122具有不同的频带电压且带有不同 性质的电荷，使得所述高K介质层2122能够改变所述衬底20中的电荷，从而减小了暗电流，避免暗电流所产生的噪声影响半导体器件的性能。
其中，形成所述沟槽211以及所述沟槽填充结构212于所述像素区21的衬底20中的步骤包括：首先，如图3a所示，覆盖垫氧化层23于所述像素区21的衬底20表面上，所述垫氧化层23用于在后续光刻形成第一图案化的光刻胶层24时，对所述衬底20的表面进行保护；然后，如图3a和3b所示，形成第一图案化的光刻胶层24于所述垫氧化层23上，以所述第一图案化的光刻胶层24为掩膜，对所述垫氧化层23以及至少部分厚度的所述衬底20进行刻蚀，以形成沟槽211于所述像素区21的衬底20中；接着，去除所述第一图案化的光刻胶层24和垫氧化层23；接着，依次形成第一隔离氧化层2121、高K介质层2122和第二隔离氧化层2123于所述沟槽211和所述衬底20的表面上，所述沟槽211中的第一隔离氧化层2121、高K介质层2122和第二隔离氧化层2123可以仅位于所述沟槽211的侧壁上，也可以均位于所述沟槽211的侧壁和底壁上；接着，填充所述填充材料于所述沟槽211中，且所述填充材料还覆盖在所述沟槽211外围的所述第二隔离氧化层2123上；接着，采用刻蚀或者化学机械研磨工艺去除覆盖于所述沟槽211外围的所述衬底20的表面上的所述填充材料、第二隔离氧化层2123、高K介质层2122和第一隔离氧化层2121(如图3c所示)，或者，仅去除覆盖于所述沟槽211外围的所述衬底20的表面上的所述填充材料(如图6a所示)，以在所述沟槽211中形成沟槽填充结构212。其中，图6a中的所述第一隔离氧化层2121、高K介质层2122和第二隔离氧化层2123仍覆盖于所述衬底20上。
其中，所述填充材料可以包括介质材料或金属材料，或同时包括介质材料和金属材料；当所述填充材料为金属材料时，如图3c所示，所述沟槽填充结构212包括形成于所述沟槽211的表面的第一隔离氧化层2121、高K介质层2122、第二隔离氧化层2123和填满所述沟槽211的第一导电金属层2124(即所述填充材料为所述第一导电金属层2124)。所述介质材料可以包括二氧化硅、氮化硅、正硅酸乙酯、硼硅玻璃、磷硅玻璃、硼磷硅玻璃、氮氧硅中的至少一种，所述金属材料可以包括钨、镍、铝、银、金、钛中的至少一种。
另外，所述沟槽填充结构212的顶表面可以与所述衬底20的顶表面齐平，或者，所述沟槽填充结构212的顶表面高于所述衬底20的顶表面，或者，仅所述沟槽填充结构212中的填充材料的顶表面高于所述衬底20的顶表面。
按照步骤S13，覆盖缓冲介质层25于所述像素区21的衬底20表面上，且所述缓冲介质层25将所述沟槽填充结构212掩埋在内，如图3d所示。所述缓冲介质层25的材质可以包括二氧化硅、氮化硅、正硅酸乙酯、硼硅玻璃、磷硅玻璃、硼磷硅玻璃、氮氧硅中的至少一种。如图6a和6b所示，若仅去除覆盖于所述沟槽211外围的所述衬底20的表面上的所述填充材料，使得所述衬底20的表面上仍覆盖有所述第一隔离氧化层2121、高K介质层2122和第二隔离氧化层2123，那么所述第一隔离氧化层2121、高K介质层2122和第二隔离氧化层2123也可理解为构成了所述缓冲介质层25的一部分。
按照步骤S14，刻蚀所述缓冲介质层25，以形成第一开口，所述第一开口至少暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20或所述沟槽填充结构212的至少部分顶部，或者至少暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的至少部分顶部。
其中，所述第一开口至少暴露出所述沟槽填充结构212的顶部侧壁外围的部分的衬底20，即是指所述第一开口至少环绕所述沟槽填充结构212的顶部外围设置，以至少暴露出环绕所述沟槽填充结构212的顶部外围的部分的衬底20。
所述第一开口至少暴露出所述沟槽填充结构212的部分顶部的情形包括：当所述沟槽填充结构212的顶表面高于所述衬底20的顶表面时，所述第一开口可以仅围绕所述沟槽填充结构212的顶部侧壁开设，以暴露出所述沟槽填充结构212的顶部侧壁上的第一隔离氧化层2121，此时，所述第一开口也暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20；当仅所述沟槽填充结构212中的填充材料的顶表面高于所述衬底20的顶表面时，所述第一开口可以仅围绕所述沟槽填充结构212的顶部侧壁开设，以暴露出所述沟槽填充结构212的顶部侧壁上的填充材料；当所述沟槽填充结构212的顶表面高于或等于所述衬底20的顶表面时，所述第一开口也可以位于所述沟槽填充结 构212的顶表面上，以暴露出所述沟槽填充结构212的部分或全部的顶表面，包括暴露出所述填充材料的部分或全部的顶表面，或者暴露出所述填充材料的部分或全部的顶表面以及暴露出所述第一隔离氧化层2121和/或所述高K介质层2122和/或所述第二隔离氧化层2123的部分或全部的顶表面；当所述沟槽填充结构212的顶表面高于所述衬底20的顶表面时，所述第一开口也可以同时暴露出所述沟槽填充结构212的顶部侧壁上的第一隔离氧化层2121或高K介质层2122或第二隔离氧化层2123或填充材料以及暴露出所述沟槽填充结构212的部分或全部的顶表面。
当所述填充材料包括第一导电金属层2124时，所述第一开口至少暴露出所述沟槽填充结构212的部分顶部的情形包括：所述第一开口围绕所述沟槽填充结构212的顶部侧壁开设，以暴露出所述沟槽填充结构212的顶部侧壁上的第一导电金属层2124；或者，所述第一开口位于所述沟槽填充结构212的顶表面上，以暴露出所述沟槽填充结构212的第一导电金属层2124的部分或全部的顶表面；或者，所述第一开口同时暴露出所述沟槽填充结构212的顶部侧壁上的第一导电金属层2124和所述沟槽填充结构212的第一导电金属层2124的部分或全部的顶表面。
对于上述的所述第一开口暴露出其底部结构的不同情形，形成所述第一开口的不同方法举例如下。其中，图3e～3i、图4a～4e和图5a～5e所示的为所述沟槽填充结构212的顶表面与所述衬底20的顶表面齐平的示例，图6c～6g所示的为所述沟槽填充结构212的顶表面高于所述衬底20的顶表面、且所述第一隔离氧化层2121、高K介质层2122和第二隔离氧化层2123仍覆盖于所述衬底20上的示例。
参阅图3e～3f，形成所述第一开口2131的步骤可以包括：形成第二图案化的光刻胶层261于所述缓冲介质层25上(如图3e所示)，以所述第二图案化的光刻胶层261为掩膜，对所述缓冲介质层25进行刻蚀，以在所述像素区21的缓冲介质层25中形成所述第一开口2131，所述第一开口2131暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部的顶表面，如图3f所示。
或者，参阅图4a～4b，形成所述第一开口2132的步骤可以包括：形成第二图案化的光刻胶层262于所述缓冲介质层25上(如图4a所示)，以所述第二图案化的光刻胶层262为掩膜，对所述缓冲介质层25进行刻蚀，以在所述像素区21的缓冲介质层25中形成所述第一开口2132，所述第一开口2132暴露出所述沟槽填充结构212的部分的顶表面，例如暴露出所述填充材料的部分的顶表面，如图4b所示，所述填充材料为所述第一导电金属层2124，则所述第一开口2132暴露出所述沟槽填充结构212的第一导电金属层2124的部分的顶表面。
或者，参阅图5a～5b，形成所述第一开口2133的步骤可以包括：形成第二图案化的光刻胶层263于所述缓冲介质层25上(如图5a所示)，以所述第二图案化的光刻胶层263为掩膜，对所述缓冲介质层25进行刻蚀，以在所述像素区21的缓冲介质层25中形成所述第一开口2133，如图5b所示，所述第一开口2133暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20。
或者，参阅图6c～6d，形成所述第一开口2134的步骤可以包括：形成第二图案化的光刻胶层264于所述缓冲介质层25上(如图6c所示)，以所述第二图案化的光刻胶层264为掩膜，对覆盖在所述衬底20上的缓冲介质层25、第二隔离氧化层2123、高K介质层2122和第一隔离氧化层2121进行刻蚀，以在所述像素区21的缓冲介质层25中形成所述第一开口2134，所述第一开口2134暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部的顶表面，如图6d所示，刻蚀之后的所述第一导电金属层2124的高度仍高于所述衬底20，使得所述第一开口2134还暴露出所述第一导电金属层2124的顶部的侧壁。
另外，形成所述第一开口之后，去除所述第二图案化的光刻胶层。
按照步骤S15，形成金属栅格层于所述缓冲介质层25上，所述金属栅格层填充所述第一开口，以与暴露出的所述部分衬底20或所述沟槽填充结构212电性连接，或者，同时与暴露出的所述部分衬底20和所述沟槽填充结构212电性连接。
由于所述金属栅格层能够与暴露出的所述部分衬底20和/或所述沟槽填 充结构212电性连接，使得能够对半导体器件进行电学性能方面的优化和改善，例如优化和改善半导体器件的暗电流。并且，所述高K介质层2122使得所述半导体器件的暗电流得到进一步地减小，进而使得所述半导体器件的电学性能得到进一步的优化和改善。
当所述第一开口仅暴露出所述部分衬底20时，所述金属栅格层仅与暴露出的所述部分衬底20电性连接；当所述第一开口至少暴露出所述沟槽填充结构212的部分顶部时，根据上述步骤S14中列出的情形，对应的所述金属栅格层与下方的结构电性连接的情形包括：当所述沟槽填充结构212的顶表面高于所述衬底20的顶表面，且所述第一开口仅围绕所述沟槽填充结构212的顶部侧壁开设(即暴露顶部侧壁上的第一隔离氧化层2121)，则所述金属栅格层也仅与暴露出的所述部分衬底20电性连接；当仅所述沟槽填充结构212中的填充材料的顶表面高于所述衬底20的顶表面，且所述第一开口仅围绕所述沟槽填充结构212的顶部侧壁开设，所述填充材料为所述第一导电金属层2124时，所述金属栅格层与所述沟槽填充结构212的顶部侧壁上的第一导电金属层2124电性连接；当所述沟槽填充结构212的顶表面高于或等于所述衬底20的顶表面，且所述第一开口位于所述沟槽填充结构212的填充材料的顶表面上，所述填充材料为所述第一导电金属层2124时，所述金属栅格层与所述沟槽填充结构212的暴露出的部分或全部的第一导电金属层2124的顶表面电性连接；当所述沟槽填充结构212的顶表面高于所述衬底20的顶表面，且所述第一开口同时暴露出所述沟槽填充结构212的顶部侧壁上的隔离氧化层2121或第一导电金属层2124以及暴露出所述第一导电金属层2124的部分或全部的顶表面时，所述金属栅格层同时与所述部分衬底20和第一导电金属层2124电性连接。
根据步骤S14中的所述第一开口暴露出底部结构的不同情形，与形成所述第一开口的不同方法相对应的，形成所述金属栅格层于所述缓冲介质层25上的方法可以包括：
参阅图3g～3i，形成所述金属栅格层2141于所述缓冲介质层25上的步骤包括：首先，如图3g所示，形成第二导电金属层27覆盖于所述缓冲介质层 25上，且所述第二导电金属层27将所述第一开口2131填满；然后，形成第三图案化的光刻胶层281于所述第二导电金属层27上(如图3h所示)，以所述第三图案化的光刻胶层281为掩膜，对所述第二导电金属层27进行刻蚀，以在所述像素区21形成金属栅格层2141(如图3i所示)，所述金属栅格层2141与所述第一开口2131暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部的顶表面(即所述沟槽填充结构212的全部的导电材质的顶表面)电性连接。
或者，参阅图4c～4e，形成所述金属栅格层2142于所述缓冲介质层25上的步骤包括：首先，如图4c所示，形成第二导电金属层27覆盖于所述缓冲介质层25上，且所述第二导电金属层27将所述第一开口2132填满；然后，形成第三图案化的光刻胶层282于所述第二导电金属层27上(如图4d所示)，以所述第三图案化的光刻胶层282为掩膜，对所述第二导电金属层27进行刻蚀，以在所述像素区21形成金属栅格层2142(如图4e所示)，所述金属栅格层2142与所述第一开口2132暴露出的所述沟槽填充结构212的第一导电金属层2124的部分的顶表面电性连接。
或者，参阅图5c～5e，形成所述金属栅格层2143于所述缓冲介质层25上的步骤包括：首先，如图5c所示，形成第二导电金属层27覆盖于所述缓冲介质层25上，且所述第二导电金属层27将所述第一开口2133填满；然后，形成第三图案化的光刻胶层283于所述第二导电金属层27上(如图5d所示)，以所述第三图案化的光刻胶层283为掩膜，对所述第二导电金属层27进行刻蚀，以在所述像素区21形成金属栅格层2143(如图5e所示)，所述金属栅格层2143与所述第一开口2133暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20电性连接。
或者，参阅图6e～6g，形成所述金属栅格层2144于所述缓冲介质层25上的步骤包括：首先，如图6e所示，形成第二导电金属层27覆盖于所述缓冲介质层25上，且所述第二导电金属层27将所述第一开口2134填满；然后，形成第三图案化的光刻胶层284于所述第二导电金属层27上(如图6f所示)，以所述第三图案化的光刻胶层284为掩膜，对所述第二导电金属层27进行刻 蚀，以在所述像素区21形成金属栅格层2144(如图6g所示)，所述金属栅格层2144与所述第一开口2134暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部的顶表面电性连接，且所述金属栅格层2144也与所述第一导电金属层2124的顶部的侧壁接触。
另外，形成所述金属栅格层之后，去除所述第三图案化的光刻胶层。所述第二导电金属层27的材质可以包括镍、铝、银、金、钛、铜中的至少一种。
另外，如图7所示，所述金属栅格层2145也可以与所述第一开口暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20以及所述沟槽填充结构212的第一导电金属层2124的部分的顶表面电性连接。
另外，所述衬底还具有位于所述像素区外围的焊盘区，所述焊盘区的衬底中形成有金属互连结构以及位于所述金属互连结构上方的插栓结构，所述插栓结构的底部与所述金属互连结构电性连接，所述插栓结构的顶部还电性连接有焊盘结构。需要说明的是，所述焊盘区的衬底中也可以形成有所述金属互连结构之外的其它的金属结构，所述插栓结构的底部与所述金属结构电性连接；例如，所述金属结构可以为导电接触插栓，所述插栓结构的底部与所述导电接触插栓电性连接。下面均以所述金属结构为金属互连结构进行说明。
由于所述高K介质层形成于所述焊盘区的插栓结构中时，会导致器件的电容增大，进而造成传输延迟(RC delay)严重，半导体器件的性能受到影响。因此，所述高K介质层不能形成于所述焊盘区的插栓结构中，那么，所述像素区的沟槽填充结构与所述焊盘区的插栓结构需要分开制作。
所述焊盘区的各个结构的形成步骤可以包括：在形成所述沟槽填充结构之后且在覆盖所述缓冲介质层于所述像素区的衬底表面上之前，形成所述插栓结构于所述焊盘区的衬底中；在覆盖所述缓冲介质层于所述像素区的衬底表面上的同时，还覆盖所述缓冲介质层于所述焊盘区的衬底表面上，以使得所述缓冲介质层将所述插栓结构掩埋在内；在刻蚀所述像素区上的所述缓冲介质层，以形成所述第一开口的同时，还刻蚀所述焊盘区上的所述缓冲介质层，以形成第二开口，所述第二开口暴露出所述插栓结构的部分的顶部表面； 以及，在形成所述金属栅格层于所述像素区的所述缓冲介质层上的同时，还形成焊盘结构于所述焊盘区的所述缓冲介质层上，所述焊盘结构填满所述第二开口，以与暴露出的所述插栓结构的顶部电性连接。
下面参阅图8a～8P对所述像素区的沟槽填充结构和金属栅格层以及所述焊盘区的插栓结构和焊盘结构的制作步骤进行说明，其中，所述像素区的金属栅格层与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接的不同情形参阅上述步骤S11至步骤S15，在此不再赘述。以图6a～6g中所示的所述金属栅格层2144与所述第一开口2134暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部的顶表面电性连接的情形为例，所述像素区21的沟槽填充结构212和金属栅格层2144与所述焊盘区22的插栓结构224和焊盘结构226的制作步骤如下：
参阅图8a，按照步骤S21，提供一具有像素区21和焊盘区22的衬底20，所述焊盘区22位于所述像素区21的外围。所述焊盘区22的衬底20中形成有金属互连结构221。
参阅图8a～8c，按照步骤S22，形成沟槽211于所述像素区21的衬底20中，并在所述沟槽211中填充填充材料，以形成沟槽填充结构212，所述填充材料的侧壁和所述衬底20之间还夹有高K介质层2122。
其中，形成所述沟槽211以及所述沟槽填充结构212于所述像素区21的衬底20中的步骤包括：首先，如图8a所示，覆盖垫氧化层23于所述像素区21和焊盘区22的衬底20表面上，所述垫氧化层23用于在后续光刻形成第一图案化的光刻胶层24时，对所述衬底20的表面进行保护；然后，如图8a和8b所示，形成第一图案化的光刻胶层24于所述垫氧化层23上，以所述第一图案化的光刻胶层24为掩膜，对所述像素区21的垫氧化层23和至少部分厚度的所述衬底20进行刻蚀，以形成沟槽211于所述像素区21的衬底20中；接着，去除所述第一图案化的光刻胶层24和垫氧化层23；接着，依次形成第一隔离氧化层2121、高K介质层2122和第二隔离氧化层2123于所述沟槽211和所述衬底20的表面上，并填充所述第一导电金属层2124(即所述填充材料)于所述沟槽211中，且所述第一导电金属层2124还覆盖在所述沟槽211外围 的所述第二隔离氧化层2123上；接着，采用刻蚀或者化学机械研磨工艺去除覆盖于所述沟槽211外围的所述衬底20的表面上的所述第一导电金属层2124，以在所述沟槽211中形成沟槽填充结构212，如图8c所示，所述第一隔离氧化层2121、高K介质层2122和第二隔离氧化层2123仍覆盖于所述衬底20上，且所述沟槽填充结构212的顶表面高于所述衬底20的顶表面。
参阅图8d～8j，按照步骤S23，形成所述插栓结构224于所述焊盘区22的衬底20中。其步骤可以包括：首先，如图8d所示，覆盖第一缓冲介质层251于所述像素区21和焊盘区22的衬底20的表面上，且所述第一缓冲介质层251将所述沟槽填充结构212掩埋在内；然后，形成第四图案化的光刻胶层29于所述第一缓冲介质层251上(如图8e所示)，以所述第四图案化的光刻胶层29为掩膜，对所述焊盘区22上的第一缓冲介质层251、第二隔离氧化层2123、高K介质层2122和第一隔离氧化层2121进行刻蚀，以在所述焊盘区22上的第一缓冲介质层251中形成第三开口222(如图8f所示)，所述第三开口222暴露出所述金属互连结构221上方的衬底20的部分顶表面；接着，如图8g所示，填充第二缓冲介质层252于所述第三开口222中，且所述第二缓冲介质层252覆盖于所述第一缓冲介质层251上；接着，形成第五图案化的光刻胶层30于所述第二缓冲介质层252上(如图8h所示)，以所述第五图案化的光刻胶层30为掩膜，对所述第三开口222中的第二缓冲介质层252和至少部分厚度的所述衬底20进行刻蚀，以在所述焊盘区22上的第二缓冲介质层252和衬底20中形成通孔223，如图8i所示，所述通孔223至少暴露出所述金属互连结构221的部分顶表面；接着，形成第三隔离氧化层2241于所述通孔223的侧壁上，且所述第三隔离氧化层2241覆盖于所述衬底20上；接着，在所述通孔223中填满第三导电金属层2242，且所述第三导电金属层2242还覆盖在所述通孔223外围的所述第三隔离氧化层2241上；接着，采用刻蚀或者化学机械研磨工艺去除覆盖于所述通孔223外围的所述衬底20上的第三导电金属层2242和第三隔离氧化层2241，以形成插栓结构224，所述插栓结构224中的第三导电金属层2242的底部与所述金属互连结构221电性连接，如图8j所示。
在本申请实施例中，先形成第三开口222以暴露出所述金属互连结构221上方的衬底20的部分顶表面；接着填充第二缓冲介质层252于所述第三开口222中，且所述第二缓冲介质层252覆盖于所述第一缓冲介质层251上；再对所述第三开口222中的第二缓冲介质层252和至少部分厚度的所述衬底20进行刻蚀，以在所述焊盘区22上的第二缓冲介质层252和衬底20中形成通孔223，由此可以提高形成所述通孔223的刻蚀工艺的精度与可靠性。在本申请的其他实施例中，也可以直接刻蚀所述第一缓冲介质层251和至少部分厚度的所述衬底20，以形成所述通孔223，即不再形成所述第三开口222，由此可以简化制造工艺。
参阅图8k，按照步骤S24，覆盖第三缓冲介质层253于所述像素区21和焊盘区22的衬底20的表面上，且所述第三缓冲介质层253将所述插栓结构224掩埋在内。如图8k所示，可以理解的是，覆盖在所述衬底20上的、且将所述沟槽填充结构212和插栓结构224掩埋在内的所述第一隔离氧化层2121、高K介质层2122、第二隔离氧化层2123、第一缓冲介质层251、第二缓冲介质层252和第三缓冲介质层253构成了所述缓冲介质层25。
参阅图8l～8m，按照步骤S25，刻蚀所述缓冲介质层，以在所述像素区21的缓冲介质层中形成第一开口2134和在所述焊盘区22的缓冲介质层中形成第二开口225，所述第一开口2134暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部的顶表面，所述第二开口225暴露出所述插栓结构224的部分的顶部表面。
形成所述第一开口2134和所述第二开口225的步骤可以包括：形成第二图案化的光刻胶层264于所述第三缓冲介质层253上(如图8l所示)，以所述第二图案化的光刻胶层264为掩膜，对所述像素区21上的第三缓冲介质层253、第一缓冲介质层251、第二隔离氧化层2123、高K介质层2122和第一隔离氧化层2121进行刻蚀，以及对所述焊盘区22上的所述第三缓冲介质层253进行刻蚀，以在所述像素区21的缓冲介质层中形成所述第一开口2134以及在所述焊盘区22的缓冲介质层中形成第二开口225，如图8m所示，所述第一开口2134暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20 和所述沟槽填充结构212的全部的顶表面，且所述第一开口2134还暴露出所述第一导电金属层2124的顶部的侧壁，所述第二开口225暴露出所述插栓结构224的第三导电金属层2242的部分的顶部表面。
参阅图8n～8p，按照步骤S26，形成金属栅格层2144于所述像素区21的第三缓冲介质层253上以及形成焊盘结构226于所述焊盘区22的所述第三缓冲介质层253上，所述金属栅格层2144填满所述第一开口2134，以与暴露出的所述部分衬底20和所述沟槽填充结构212电性连接；所述焊盘结构226填满所述第二开口225，以与暴露出的所述插栓结构224的顶部电性连接。
形成金属栅格层2144于所述像素区21的第三缓冲介质层253上以及形成焊盘结构226于所述焊盘区22的所述第三缓冲介质层253上的步骤包括：首先，如图8n所示，形成第二导电金属层27覆盖于所述第三缓冲介质层253上，且所述第二导电金属层27将所述第一开口2134以及所述第二开口225填满；然后，形成第三图案化的光刻胶层284于所述第二导电金属层27上(如图8o所示)，以所述第三图案化的光刻胶层284为掩膜，对所述第二导电金属层27进行刻蚀，以在所述像素区21形成金属栅格层2144以及在所述焊盘区22形成焊盘结构226(如图8p所示)，所述金属栅格层2144与所述第一开口2134暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部的顶表面电性连接，所述焊盘结构226与暴露出的所述插栓结构224的第三导电金属层2242的部分的顶部表面电性连接。
另外，上述的半导体器件的制造方法中的各个步骤不仅限于上述的形成顺序，各个步骤的先后顺序可适应性的进行调整。
综上所述，本发明提供的半导体器件的制造方法，包括：提供一具有像素区的衬底；形成沟槽于所述像素区的衬底中，并在所述沟槽中填充填充材料，以形成沟槽填充结构，所述填充材料的侧壁和所述衬底之间还夹有高K介质层；覆盖缓冲介质层于所述像素区的衬底表面上，且所述缓冲介质层将所述沟槽填充结构掩埋在内；刻蚀所述缓冲介质层，以形成第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，形成金属栅格层于所述缓冲介质层上， 所述金属栅格层填充所述第一开口，以与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接。本发明的半导体器件的制造方法使得金属栅格层与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接，进而使得能够对半导体器件进行电学性能方面的优化和改善。
本发明一实施例提供了一种半导体器件，所述半导体器件包括衬底、沟槽填充结构、缓冲介质层和金属栅格层，所述衬底具有像素区；所述沟槽填充结构形成于所述像素区的衬底中，所述沟槽填充结构包含有填充于所述衬底中的沟槽中的填充材料以及夹设在所述填充材料的侧壁和所述衬底之间的高K介质层；所述缓冲介质层形成于所述像素区的衬底表面上，所述缓冲介质层具有第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；所述金属栅格层形成于所述缓冲介质层上，所述金属栅格层填充所述第一开口，以与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接。
下面参阅图3i、图4e、图5e、图6g、图7和图8p详细描述本实施例提供的半导体器件：
所述衬底20具有像素区21，所述衬底20的材质可以为本领域技术人员熟知的任意合适的底材，具体参见步骤S11，在此不再赘述。
所述沟槽填充结构212形成于所述像素区21的衬底20中。所述沟槽填充结构212包含有填充于所述衬底20中的沟槽211中的填充材料以及夹设在所述填充材料的侧壁和所述衬底20之间的高K介质层2122。其中，所述沟槽211可以是深度为1μm～5μm的深沟槽，需要说明的是，所述沟槽211的深度不仅限于此深度范围，可以根据半导体器件的性能需求形成合适深度的所述沟槽211。所述沟槽填充结构212可以在所述像素区21的衬底20中起到隔离各器件的作用。所述高K介质层2122的K(介电常数)值优选为大于7，所述高K介质层2122的材质可以包括氮化物或者金属氧化物，例如可以为氮化硅、氮氧硅、二氧化钛、五氧化二钽等。所述高K介质层2122具有不同的频带电压且带有不同性质的电荷，使得所述高K介质层2122能够改变所述衬底20中的电荷，从而减小了暗电流，避免暗电流所产生的噪声影响半导体器 件的性能。
所述沟槽填充结构212可以包括依次覆盖于所述衬底20中的沟槽211的表面上的第一隔离氧化层2121、高K介质层2122、第二隔离氧化层2123和填充于所述沟槽211中的所述填充材料，所述第一隔离氧化层2121、高K介质层2122和第二隔离氧化层2123至少位于所述填充材料的侧壁和所述衬底20之间，即所述沟槽211中的第一隔离氧化层2121、高K介质层2122和第二隔离氧化层2123可以仅位于所述沟槽211的侧壁上，也可以均位于所述沟槽211的侧壁和底壁上。
其中，所述填充材料可以包括介质材料或金属材料，或同时包括介质材料和金属材料；当所述填充材料为金属材料时，如图3i所示，所述沟槽填充结构212包括形成于所述沟槽211的表面的第一隔离氧化层2121、高K介质层2122、第二隔离氧化层2123和填满所述沟槽211的第一导电金属层2124(即所述填充材料为所述第一导电金属层2124)。所述介质材料可以包括二氧化硅、氮化硅、正硅酸乙酯、硼硅玻璃、磷硅玻璃、硼磷硅玻璃、氮氧硅中的至少一种，所述金属材料可以包括钨、镍、铝、银、金、钛中的至少一种。
另外，所述沟槽填充结构212的顶表面可以与所述衬底20的顶表面齐平，或者，所述沟槽填充结构212的顶表面高于所述衬底20的顶表面，或者，仅所述沟槽填充结构212中的填充材料的顶表面高于所述衬底20的顶表面。
所述缓冲介质层25形成于所述像素区21的衬底20表面上，所述缓冲介质层25具有第一开口，所述第一开口至少暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20或所述沟槽填充结构212的至少部分顶部，或者，至少暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的至少部分顶部。
其中，所述第一开口至少暴露出所述沟槽填充结构212的顶部侧壁外围的部分的衬底20，即是指所述第一开口至少环绕所述沟槽填充结构212的顶部外围设置，以至少暴露出环绕所述沟槽填充结构212的顶部外围的部分的衬底20。
所述第一开口至少暴露出所述沟槽填充结构212的部分顶部的情形包括： 当所述沟槽填充结构212的顶表面高于所述衬底20的顶表面时，所述第一开口可以仅围绕所述沟槽填充结构212的顶部侧壁开设，以暴露出所述沟槽填充结构212的顶部侧壁上的第一隔离氧化层2121，此时，所述第一开口也暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20；当仅所述沟槽填充结构212中的填充材料的顶表面高于所述衬底20的顶表面时，所述第一开口可以仅围绕所述沟槽填充结构212的顶部侧壁开设，以暴露出所述沟槽填充结构212的顶部侧壁上的填充材料；当所述沟槽填充结构212的顶表面高于或等于所述衬底20的顶表面时，所述第一开口也可以位于所述沟槽填充结构212的顶表面上，以暴露出所述沟槽填充结构212的部分或全部的顶表面，包括暴露出所述填充材料的部分或全部的顶表面，或者暴露出所述填充材料的部分或全部的顶表面以及暴露出所述第一隔离氧化层2121和/或所述高K介质层2122和/或所述第二隔离氧化层2123的部分或全部的顶表面；当所述沟槽填充结构212的顶表面高于所述衬底20的顶表面时，所述第一开口也可以同时暴露出所述沟槽填充结构212的顶部侧壁上的第一隔离氧化层2121或高K介质层2122或第二隔离氧化层2123或填充材料以及暴露出所述沟槽填充结构212的部分或全部的顶表面。
当所述填充材料包括第一导电金属层2124时，所述第一开口至少暴露出所述沟槽填充结构212的部分顶部的情形包括：所述第一开口围绕所述沟槽填充结构212的顶部侧壁开设，以暴露出所述沟槽填充结构212的顶部侧壁上的第一导电金属层2124；或者，所述第一开口位于所述沟槽填充结构212的顶表面上，以暴露出所述沟槽填充结构212的第一导电金属层2124的部分或全部的顶表面；或者，所述第一开口同时暴露出所述沟槽填充结构212的顶部侧壁上的第一导电金属层2124和所述沟槽填充结构212的第一导电金属层2124的部分或全部的顶表面。
所述金属栅格层形成于所述缓冲介质层25上，所述金属栅格层填充所述第一开口，以与暴露出的所述部分衬底20或所述沟槽填充结构电性连接，或者，同时与暴露出的所述部分衬底20和所述沟槽填充结构212电性连接。
由于所述金属栅格层能够与暴露出的所述部分衬底20和/或所述沟槽填 充结构212电性连接，使得能够对半导体器件进行电学性能方面的优化和改善，例如优化和改善半导体器件的暗电流。并且，所述高K介质层使得所述半导体器件的暗电流得到进一步地减小，进而使得所述半导体器件的电学性能得到进一步的优化和改善。
当所述第一开口仅暴露出所述部分衬底20时，所述金属栅格层仅与暴露出的所述部分衬底20电性连接；当所述第一开口至少暴露出所述沟槽填充结构212的部分顶部时，根据上述列出的不同情形，对应的所述金属栅格层与下方的结构电性连接的情形包括：当所述沟槽填充结构212的顶表面高于所述衬底20的顶表面，且所述第一开口仅围绕所述沟槽填充结构212的顶部侧壁开设(即暴露顶部侧壁上的第一隔离氧化层2121)，则所述金属栅格层也仅与暴露出的所述部分衬底20电性连接；当仅所述沟槽填充结构212中的填充材料的顶表面高于所述衬底20的顶表面，且所述第一开口仅围绕所述沟槽填充结构212的顶部侧壁开设，所述填充材料为所述第一导电金属层2124时，所述金属栅格层与所述沟槽填充结构212的顶部侧壁上的第一导电金属层2124电性连接；当所述沟槽填充结构212的顶表面高于或等于所述衬底20的顶表面，且所述第一开口位于所述沟槽填充结构212的填充材料的顶表面上，所述填充材料为所述第一导电金属层2124时，所述金属栅格层与所述沟槽填充结构212的暴露出的部分或全部的第一导电金属层2124的顶表面电性连接；当所述沟槽填充结构212的顶表面高于所述衬底20的顶表面，且所述第一开口同时暴露出所述沟槽填充结构212的顶部侧壁上的隔离氧化层2121或第一导电金属层2124以及暴露出所述第一导电金属层2124的部分或全部的顶表面时，所述金属栅格层同时与所述部分衬底20和第一导电金属层2124电性连接。
所述金属栅格层与暴露出的所述部分衬底20和/或所述沟槽填充结构212电性连接的情形举例如下：如图3i所示，所述金属栅格层2141与所述第一开口2131暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部的顶表面电性连接；如图4e所示，所述金属栅格层2142与所述第一开口2132暴露出的所述沟槽填充结构212的第一导电金 属层2124的部分的顶表面电性连接；如图5e所示，所述金属栅格层2143与所述第一开口2133暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20电性连接；如图6g所示，所述金属栅格层2144与所述第一开口2134暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部的顶表面电性连接，且所述金属栅格层2144也与所述第一导电金属层2124的顶部的侧壁接触；如图7所示，所述金属栅格层2145与所述第一开口暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20以及所述沟槽填充结构212的第一导电金属层2124的部分的顶表面电性连接。
另外，所述衬底还具有位于所述像素区外围的焊盘区，所述焊盘区的衬底中形成有金属互连结构以及位于所述金属互连结构上方的插栓结构，所述插栓结构的底部与所述金属互连结构电性连接，所述插栓结构的顶部还电性连接有焊盘结构。需要说明的是，所述焊盘区的衬底中也可以形成有所述金属互连结构之外的其它的金属结构，所述插栓结构的底部与所述金属结构电性连接；例如，所述金属结构可以为导电接触插栓，所述插栓结构的底部与所述导电接触插栓电性连接。下面均以所述金属结构为金属互连结构进行说明。
其中，所述插栓结构包括：位于暴露出所述金属互连结构的部分顶表面的通孔的侧壁上的第三隔离氧化层，以及填满所述通孔的第三导电金属层。所述缓冲介质层还形成于所述焊盘区的衬底表面上，且所述缓冲介质层具有暴露出所述插栓结构的部分的顶部表面的第二开口；所述焊盘区的缓冲介质层上还形成有焊盘结构，所述焊盘结构填满所述第二开口，以与暴露出的所述插栓结构的顶部电性连接。
由于所述高K介质层形成于所述焊盘区的插栓结构中时，会导致器件的电容增大，进而造成传输延迟(RC delay)严重，半导体器件的性能受到影响，因此，所述高K介质层不能形成于所述焊盘区的插栓结构中。
所述像素区的金属栅格层与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接的不同情形参阅上述的说明，在此不再赘述。如图8p所示，以所 述金属栅格层2144与所述第一开口2134暴露出的所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部的顶表面电性连接的情形为例，对所述像素区21的沟槽填充结构212和金属栅格层2144与所述焊盘区22的插栓结构224和焊盘结构226进行说明：
所述插栓结构224包括：位于暴露出所述金属互连结构221的部分顶表面的通孔223的侧壁上的第三隔离氧化层2241，以及填满所述通孔223的第三导电金属层2242。所述插栓结构224中的第三导电金属层2242的底部与所述金属互连结构221电性连接。
覆盖在所述衬底20上的、且将所述沟槽填充结构212和插栓结构224掩埋在内的所述第一隔离氧化层2121、高K介质层2122、第二隔离氧化层2123、第一缓冲介质层251、第二缓冲介质层252和第三缓冲介质层253构成了所述缓冲介质层25。
在所述像素区21的缓冲介质层25(即衬底20上的所述第一隔离氧化层2121、高K介质层2122、第二隔离氧化层2123、第一缓冲介质层251和第三缓冲介质层253)中形成有第一开口2134以及在所述焊盘区22的缓冲介质层25(即所述第三缓冲介质层253)中形成有第二开口225，所述第一开口2134暴露出所述沟槽填充结构212的顶部侧壁外围的部分衬底20和所述沟槽填充结构212的全部的顶表面，且所述第一开口2134还暴露出所述第一导电金属层2124的顶部的侧壁，所述第二开口225暴露出所述插栓结构224的第三导电金属层2242的部分的顶部表面。
所述像素区21的缓冲介质层25(即所述第三缓冲介质层253)上形成有金属栅格层2144，所述焊盘区22的缓冲介质层25上形成有焊盘结构226，所述金属栅格层2144填满所述第一开口2134，以与暴露出的所述部分衬底20和所述沟槽填充结构212电性连接；所述焊盘结构226填满所述第二开口225，以与暴露出的所述插栓结构224的顶部电性连接。
综上所述，本发明提供的半导体器件，包括：衬底，具有像素区；沟槽填充结构，形成于所述像素区的衬底中，所述沟槽填充结构包含有填充于所述衬底中的沟槽中的填充材料以及夹设在所述填充材料的侧壁和所述衬底之 间的高K介质层；缓冲介质层，形成于所述像素区的衬底表面上，所述缓冲介质层具有第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，金属栅格层，形成于所述缓冲介质层上，所述金属栅格层填充所述第一开口，以与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接。本发明的半导体器件使得金属栅格层与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接，进而使得能够对半导体器件进行电学性能方面的优化和改善。
上述描述仅是对本发明较佳实施例的描述，并非对本发明范围的任何限定，本发明领域的普通技术人员根据上述揭示内容做的任何变更、修饰，均属于权利要求书的保护范围。

Claims (15)

  1. 一种半导体器件的制造方法，其特征在于，包括：
    提供一具有像素区的衬底；
    形成沟槽于所述像素区的衬底中，并在所述沟槽中填充填充材料，且在所述填充材料的侧壁和所述衬底之间形成有高K介质层，以形成沟槽填充结构；
    覆盖缓冲介质层于所述像素区的衬底表面上，且所述缓冲介质层将所述沟槽填充结构掩埋在内；
    刻蚀所述缓冲介质层，以形成第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，
    形成金属栅格层于所述缓冲介质层上，所述金属栅格层填充所述第一开口，以与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接。
  2. 如权利要求1所述的半导体器件的制造方法，其特征在于，形成所述沟槽以及所述沟槽填充结构于所述像素区的衬底中的步骤包括：
    覆盖垫氧化层于所述像素区的衬底表面上；
    形成第一图案化的光刻胶层于所述垫氧化层上，以所述第一图案化的光刻胶层为掩膜，对所述垫氧化层以及至少部分厚度的所述衬底进行刻蚀，以形成沟槽于所述像素区的衬底中；
    去除所述第一图案化的光刻胶层和垫氧化层；
    依次形成第一隔离氧化层、高K介质层和第二隔离氧化层于所述沟槽和所述衬底的表面上；
    填充所述填充材料于所述沟槽中，且所述填充材料还覆盖在所述沟槽外的所述第二隔离氧化层上；以及，
    采用刻蚀或者化学机械研磨工艺去除覆盖于所述沟槽外的所述衬底的表面上的所述填充材料、第二隔离氧化层、高K介质层和第一隔离氧化层，或者，仅去除覆盖于所述沟槽外的所述衬底的表面上的所述填充材料，以在所 述沟槽中形成沟槽填充结构。
  3. 如权利要求2所述的半导体器件的制造方法，其特征在于，所述填充材料包括第一导电金属层，所述第一开口至少暴露出所述沟槽填充结构的部分顶部包括：所述第一开口围绕所述沟槽填充结构的顶部侧壁开设，以暴露出所述沟槽填充结构的顶部侧壁上的第一导电金属层，和/或，所述第一开口位于所述沟槽填充结构的顶表面上，以暴露出所述沟槽填充结构的第一导电金属层的部分或全部的顶表面。
  4. 如权利要求1所述的半导体器件的制造方法，其特征在于，刻蚀所述缓冲介质层，以形成所述第一开口的步骤包括：
    形成第二图案化的光刻胶层于所述缓冲介质层上，以所述第二图案化的光刻胶层为掩膜，对所述缓冲介质层进行刻蚀，以在所述像素区的缓冲介质层中形成所述第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，
    去除所述第二图案化的光刻胶层。
  5. 如权利要求1所述的半导体器件的制造方法，其特征在于，形成所述金属栅格层于所述缓冲介质层上的步骤包括：
    形成第二导电金属层覆盖于所述缓冲介质层上，且所述第二导电金属层将所述第一开口填满；
    形成第三图案化的光刻胶层于所述第二导电金属层上，以所述第三图案化的光刻胶层为掩膜，对所述第二导电金属层进行刻蚀，以在所述像素区形成金属栅格层，所述金属栅格层与所述第一开口暴露出的所述部分衬底和/或所述沟槽填充结构电性连接；以及，
    去除所述第三图案化的光刻胶层。
  6. 如权利要求1至5中任一项所述的半导体器件的制造方法，其特征在于，所述衬底还具有位于所述像素区外围的焊盘区，所述焊盘区的衬底中形成有金属互连结构以及位于所述金属互连结构上方的插栓结构，所述插栓结构的底部与所述金属互连结构电性连接。
  7. 如权利要求6所述的半导体器件的制造方法，其特征在于，在形成所 述沟槽填充结构之后且在覆盖所述缓冲介质层于所述像素区的衬底表面上之前，形成所述插栓结构于所述焊盘区的衬底中。
  8. 如权利要求6所述的半导体器件的制造方法，其特征在于，在覆盖所述缓冲介质层于所述像素区的衬底表面上的步骤中，所述缓冲介质层还延伸覆盖于所述焊盘区的衬底表面上，以使得所述缓冲介质层将所述插栓结构掩埋在内；在刻蚀所述像素区上的所述缓冲介质层，以形成所述第一开口的同时，还刻蚀所述焊盘区上的所述缓冲介质层，以形成第二开口，所述第二开口暴露出所述插栓结构的部分的顶部表面；以及，在形成所述金属栅格层于所述像素区的所述缓冲介质层上的同时，还形成焊盘结构于所述焊盘区的所述缓冲介质层上，所述焊盘结构填满所述第二开口，以与暴露出的所述插栓结构的顶部电性连接。
  9. 一种半导体器件，其特征在于，包括：
    衬底，具有像素区，所述像素区的衬底中形成有沟槽；
    沟槽填充结构，形成于所述像素区的衬底中，所述沟槽填充结构包括填充于所述沟槽中的填充材料以及位于所述填充材料的侧壁和所述衬底之间的高K介质层；
    缓冲介质层，覆盖于所述像素区的衬底表面上，所述缓冲介质层具有第一开口，所述第一开口至少暴露出所述沟槽填充结构的顶部侧壁外围的部分衬底和/或所述沟槽填充结构的至少部分顶部；以及，
    金属栅格层，形成于所述缓冲介质层上，所述金属栅格层填充所述第一开口，以与暴露出的所述部分衬底和/或所述沟槽填充结构电性连接。
  10. 如权利要求9所述的半导体器件，其特征在于，所述沟槽填充结构包括依次覆盖于所述沟槽的表面上的第一隔离氧化层、所述高K介质层、第二隔离氧化层和填充于所述沟槽中的所述填充材料，所述第一隔离氧化层、高K介质层和第二隔离氧化层至少位于所述填充材料的侧壁和所述衬底之间。
  11. 如权利要求10所述的半导体器件，其特征在于，所述填充材料包括第一导电金属层，所述第一开口至少暴露出所述沟槽填充结构的部分顶部包 括：所述第一开口围绕所述沟槽填充结构的顶部侧壁开设，以暴露出所述沟槽填充结构的顶部侧壁上的第一导电金属层，和/或，所述第一开口位于所述沟槽填充结构的顶表面上，以暴露出所述沟槽填充结构的第一导电金属层的部分或全部的顶表面。
  12. 如权利要求9所述的半导体器件，其特征在于，所述高K介质层的K值大于7。
  13. 如权利要求9至12中任一项所述的半导体器件，其特征在于，所述衬底还具有位于所述像素区外围的焊盘区，所述焊盘区的衬底中形成有金属互连结构以及位于所述金属互连结构上方的插栓结构，所述插栓结构的底部与所述金属互连结构电性连接。
  14. 如权利要求13所述的半导体器件，其特征在于，所述焊盘区的衬底中形成有通孔，所述通孔至少暴露出所述金属互连结构的部分顶表面，所述插栓结构包括：位于所述通孔的侧壁上的第三隔离氧化层，以及填满所述通孔的第三导电金属层。
  15. 如权利要求13所述的半导体器件，其特征在于，所述缓冲介质层还延伸覆盖于所述焊盘区的衬底表面上，且所述缓冲介质层具有暴露出所述插栓结构的至少部分顶部的第二开口；所述焊盘区的缓冲介质层上还形成有焊盘结构，所述焊盘结构填满所述第二开口，以与暴露出的所述插栓结构的顶部电性连接。
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