WO2021114711A1 - 一种电压调节方法和电子设备 - Google Patents

一种电压调节方法和电子设备 Download PDF

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Publication number
WO2021114711A1
WO2021114711A1 PCT/CN2020/109898 CN2020109898W WO2021114711A1 WO 2021114711 A1 WO2021114711 A1 WO 2021114711A1 CN 2020109898 W CN2020109898 W CN 2020109898W WO 2021114711 A1 WO2021114711 A1 WO 2021114711A1
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Prior art keywords
processor
power supply
main frequency
voltage
supply voltage
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PCT/CN2020/109898
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English (en)
French (fr)
Inventor
陈忠建
王晓坤
许仕彬
李年兵
张良义
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to IL293774A priority Critical patent/IL293774A/en
Priority to EP20899909.4A priority patent/EP4060454A4/en
Publication of WO2021114711A1 publication Critical patent/WO2021114711A1/zh
Priority to US17/834,710 priority patent/US11886274B2/en
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G06F1/206—Cooling means comprising thermal management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3243—Power saving in microcontroller unit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • This application relates to the field of electronic technology, and in particular to a voltage adjustment method and electronic equipment.
  • Circuit Moore's Law is a law that reveals the speed of information technology progress. Its content is: when the price remains the same, the number of components that can be accommodated on an integrated circuit will double about every 18-24 months. Will also be doubled. In other words, the computer performance that can be bought for every dollar will more than double every 18-24 months.
  • the dynamic voltage frequency scaling (Dynamic Voltage and Frequency Scaling, abbreviated as DVFS) technology is generally used to adjust the power supply voltage of the power supply to the processor, so as to reduce the processor's main frequency and supply voltage when the processor load is light;
  • DVFS Dynamic Voltage and Frequency Scaling
  • the processor is under heavy load, it is a power reduction technology to increase the processor's main frequency and power supply voltage, thereby reducing the processor's power consumption.
  • DVFS technology cannot reduce the power supply voltage of the processor. Therefore, the effect of DVFS technology in reducing power consumption is not obvious.
  • the present application provides a voltage adjustment method and electronic equipment to ensure that the processor can reduce power consumption and improve performance under both light load and heavy load.
  • an embodiment of the present application provides a voltage adjustment method, which is applied to an electronic device having a processor and a power supply for supplying power to the processor.
  • the method includes: the processor sends power supply adjustment information to the power supply according to the main frequency of the next time period, the power supply adjustment information includes the set power supply voltage V of the main frequency of the next time period, and the main frequency of the next time period refers to the prediction based on the current main frequency Main frequency:
  • the power supply provides the processor with the power supply voltage V out according to the set supply voltage V of the main frequency of the next time period and the set voltage slope R of the main frequency of the next time period.
  • the voltage slope refers to the decreasing speed of the supply voltage V out as the load current of the power supply increases.
  • the supply voltage V out decreases as the load current increases.
  • V min ⁇ V out ⁇ V, V min is the lowest power supply voltage for normal operation when the processor is running at the main frequency in the next period of time when the load current increases.
  • the main frequency of the next period refers to the main frequency predicted according to the current main frequency
  • the power supply is based on the set supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period.
  • the supply voltage V out provided by the processor is adapted to the main frequency of the processor in the next time period.
  • the method provided by the present application actively controls the power supply voltage V out output by the power supply to decrease with the increase of the load current, so that when the load current starts to increase, the power supply voltage V out output by the power supply actively decreases with the increase of the load current. .
  • the supply voltage V out is less than the set supply voltage V of the main frequency of the processor in the next period and greater than or equal to the minimum supply voltage V for normal operation when the processor is running at the main frequency in the next period of time. min . It can be seen that, compared with the prior art, the power supply voltage V ou provided by the power supply in the method provided by the present application can ensure that the processor is running normally, reducing the power consumption of the processor, thereby improving the performance of the processor.
  • the method provided in this application can ensure that the load of the processor is high or low, and the power supply can be lower than the current load current when the load current increases.
  • the main frequency setting power supply voltage provides power to the processor, so that the processor has lower power consumption while operating normally.
  • the method before the processor sends the power supply adjustment information to the power supply according to the main frequency of the next period, the method further includes: the processor predicts the load in the next period according to the current load, and determines the load in the next period.
  • the main frequency of the next time period For example: store the corresponding relationship table of load and main frequency in the built-in memory of the motherboard or processor, and query the main frequency of the next period in the corresponding table of load and main frequency according to the predicted load in the next period.
  • the foregoing method further includes: in a case where the processor determines that the main frequency of the next time period is not equal to the current main frequency, setting the current main frequency to be equal to the main frequency of the next time period.
  • setting the current main frequency equal to the main frequency of the next time period includes: the processor determines the next time The main frequency of a period is less than the current main frequency, the processor sets the current main frequency to be equal to the main frequency of the next period before sending the power supply adjustment information to the power supply according to the main frequency of the next period; the processor determines that the main frequency of the next period is greater than the current main frequency, After the power supply provides the supply voltage V out to the processor according to the set supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period, the processor sets the current main frequency to be equal to the main frequency
  • the power supply voltage V out VI * R
  • I is the load current of the power, calculated by the supply voltage V out can be seen
  • the supply voltage V out is set by the processor in a next period
  • the voltage slope R, the set supply voltage V and the load current I for the next period are determined.
  • the voltage slope refers to the decreasing speed of the supply voltage as the load current of the power supply increases
  • the product of the set voltage slope R and the load current I of the main frequency in the next period is essentially: when the load current of the power supply increases, the supply voltage
  • the power supply voltage V out can always be greater than or equal to when the processor is running in the next period.
  • the lowest supply voltage V min for normal operation.
  • the above-mentioned set power supply voltage V of the main frequency in the next period may be provided by the processor, and the set voltage slope R of the main frequency in the next period may exist in the power supply or be provided by the processor.
  • the processor only provides the power supply with the set supply voltage V of the main frequency for the next time period, the processor does not need to use the communication interface between the processor and the power supply to dynamically set the set voltage slope R of the main frequency for the next time period in the power supply, thus Effectively reduce the communication delay and voltage adjustment delay, and improve the voltage adjustment speed.
  • the above-mentioned processor sending power supply adjustment information to the power supply according to the main frequency of the next time period includes: the processor searches for the set supply voltage V of the main frequency of the next time period from the target correspondence relationship according to the main frequency of the next time period. , And send the set supply voltage V of the main frequency for the next period to the power supply.
  • the target correspondence here is the correspondence between the processor's main frequency, the set supply voltage, and the set voltage slope.
  • the target correspondence relationship may also be the correspondence relationship between the processor's main frequency and the set supply voltage.
  • the processor only needs to query the set power supply voltage of the main frequency in the next period from the target correspondence, and send the set power supply voltage of the main frequency in the next period to the power supply, which can reduce the communication delay and the voltage adjustment delay. , Shorten the voltage regulation time.
  • the set voltage slope R of the main frequency for the next period of time may exist in the power supply in the form of a constant voltage slope.
  • the existence method can be the preservation method.
  • the constant voltage slope is the minimum value R min of the voltage slope allowed by the set supply voltage of the processor at each main frequency, R min >0. Since R min >0, it can be ensured that when the processor is working at any load or main frequency, the power supply can always provide a power supply voltage to the processor in a manner that is less than or equal to the set power supply voltage, so that the processor has lower energy consumption.
  • the constant voltage slope is the minimum value R min of the actual measured voltage slope of the processor at each main frequency
  • the constant voltage slope is the set voltage slope R of the main frequency for the next period
  • the main frequency of the next period can be controlled.
  • the product of the voltage slope and the load current is set to make the processor operate normally, and to avoid the situation that the processor cannot operate normally at the supply voltage V out when the constant voltage slope takes a large value when the load current increases.
  • the power supply adjustment information when the set voltage slope R of the main frequency for the next time period is provided by the processor, the power supply adjustment information not only includes the set power supply voltage V of the main frequency for the next time period, but also includes the next time period.
  • the set voltage slope R of the main frequency when the set voltage slope R of the main frequency for the next time period is provided by the processor, the power supply adjustment information not only includes the set power supply voltage V of the main frequency for the next time period, but also includes the next time period.
  • the processor sending power supply adjustment information to the power supply according to the main frequency of the next time period includes: the processor according to the next time period
  • the main frequency searches for the set supply voltage V of the main frequency in the next period and the set voltage slope R of the main frequency in the next period from the target correspondence relationship, and sends the set supply voltage V and the next period of the main frequency to the power supply.
  • the target correspondence relationship is the correspondence relationship between the processor's main frequency, the set supply voltage, and the set voltage slope.
  • the set voltage slope of the processor at each main frequency is the allowable voltage slope of the set supply voltage of the processor at each main frequency.
  • the set voltage slope of each main frequency in the above-mentioned target correspondence relationship is the allowable voltage slope of the set supply voltage of each main frequency of the processor.
  • the set voltage slopes of the above-mentioned processor at all main frequencies are equal to the constant voltage slopes.
  • the constant voltage slope is the minimum value R min of the voltage slope allowed by the set supply voltage of the processor at each main frequency, R min >0.
  • the set voltage slopes of all main frequencies in the above target correspondence relationship are equal to the constant voltage slopes.
  • the power supply essentially saves the set voltage slopes of all the main frequencies in the target correspondence in the form of a constant voltage slope.
  • the processor only needs to query the set power supply voltage R of the main frequency for the next period from the target correspondence relationship, and change the set power supply voltage of the main frequency for the next period V is sent to the power supply, so that the power supply adjusts the reference voltage according to the set supply voltage V of the main frequency of the next time period.
  • the processor only needs to dynamically set the reference voltage in the power supply through the bus interface according to the main frequency of the next time period, so as to reduce the communication delay and the voltage adjustment delay, so that the voltage adjustment time is shortened.
  • the constant voltage slope is the minimum value R min of the voltage slope allowed by the set supply voltage of the processor at each main frequency, R min > 0, it can be ensured that the processor is working at any load or main frequency.
  • the power supply voltage V out provided by the power supply to the processor always satisfies V min ⁇ V out ⁇ V, so that the processor has lower energy consumption while operating normally.
  • the allowable voltage slope R (i) R max(i) - ⁇ R (i) of the above-mentioned processor at the set supply voltage of each main frequency, where R max(i) is the processor The maximum voltage slope of the set supply voltage at each main frequency, ⁇ R (i) is the voltage slope margin of the processor at each main frequency.
  • R max(i) is the maximum voltage slope of the set supply voltage of the processor at each main frequency
  • the supply voltage V out provided by the power supply to the processor can be as full as the load current increases. It may be close to V min , so as to ensure that the processor runs with lower power consumption.
  • the set supply voltage of each main frequency in the above-mentioned processor is V (i) . That is, the set supply voltage of each main frequency in the above-mentioned target correspondence is V (i) .
  • V (i) V min(i) + ⁇ V (i)
  • V min(i) is the lowest supply voltage for normal operation of the processor when the load current increases when the processor is running at each main frequency
  • ⁇ V ( i) is the supply voltage margin of the processor at each main frequency.
  • the set supply voltage V of the main frequency for the next time period searched by the processor is slightly larger than the minimum supply voltage V min for normal operation when the processor is running at the main frequency for the next time period and the load current increases.
  • the power supply voltage V out provided by the power supply to the processor can ensure that the processor runs normally at lower power consumption.
  • the method before the processor sends the power supply adjustment information to the power supply according to the main frequency of the next time period, the method further includes: the processor calibrates the target correspondence relationship according to the performance difference information, so that the calibrated target corresponds to The relationship is matched with the processor included in the electronic device, thereby improving the reliability and accuracy of voltage adjustment.
  • the performance difference information can be detected by a critical path monitor (CPM) circuit built in the processor.
  • the CPM circuit is used to simulate the timing critical path of the reference processor.
  • the delay level (such as the delay time) or the oscillation frequency determined by the CPM circuit is the performance difference information.
  • the processor in order to cooperate with the processor to calibrate the target correspondence based on the performance difference information, it should also pre-store the correspondence between a variety of processor performance differences that do not consider temperature effects and the lowest power supply voltage differences, or consider temperature effects. Correspondence between the performance difference of the various processors in multiple temperature gears and the difference of the lowest power supply voltage.
  • the performance difference of each processor can be expressed by the delay level (such as delay time) or oscillation frequency of that kind of processor, or this kind of processing can also be used The difference in delay or oscillation frequency between the processor and the reference processor at the same voltage is indirectly indicated.
  • the lowest power supply voltage difference corresponding to each processor performance difference refers to the lowest difference between the processor and the reference processor at the same main frequency.
  • the benchmark processor refers to the worst-performing processor among a variety of processors. That is, the reference processor is the processor with the lowest power supply voltage of multiple processors at the same main frequency.
  • the processor calibrates the target correspondence relationship according to the performance difference information, so that the target correspondence relationship matches the processor included in the electronic device includes: the processor according to the performance difference information Find the lowest power supply voltage difference from the correspondence between multiple processor performance differences and the lowest power supply voltage difference, and calibrate the set power supply voltage corresponding to each main frequency in the target correspondence according to the lowest power supply voltage difference, so that the calibrated target The corresponding relationship matches with the processor included in the electronic device.
  • the processor calibrates the target correspondence relationship according to the performance difference information, so that the target correspondence relationship matches the processor included in the electronic device includes: the processor according to the current temperature Find the corresponding relationship between the performance difference of multiple processors at multiple temperature levels and the minimum power supply voltage difference from the corresponding relationship between the performance difference of multiple processors at the current temperature level and the minimum power supply voltage difference, according to the performance difference
  • the information finds the lowest power supply voltage difference matched by the current performance difference information from the correspondence between the performance difference of the various processors at the current temperature range and the lowest power supply voltage difference, and the lowest power supply voltage difference matched by the performance difference information corresponds to the target
  • the set supply voltage corresponding to each main frequency in the relationship is calibrated, so that the target corresponding relationship after calibration matches the processor included in the electronic device.
  • the above-mentioned electronic device contains a storage medium.
  • the storage medium may exist independently of the processor, or may be built in the processor.
  • the foregoing target correspondence relationship may be directly or indirectly stored in the storage medium in a variety of ways.
  • the storage medium may also store the corresponding relationship between the difference in performance of multiple processors and the difference in the lowest power supply voltage, or the corresponding relationship between the difference in performance of multiple processors at multiple temperature levels and the difference in the lowest power supply voltage.
  • the corresponding relationship between the difference in performance of various processors and the difference in the lowest power supply voltage may be stored in the storage medium in the form of a relationship table or a functional relationship.
  • the corresponding relationship between the performance difference of the various processors at multiple temperature levels and the minimum power supply voltage difference is stored in the storage medium in the form of a relationship table or a functional relationship.
  • the foregoing target correspondence relationship is stored in the foregoing storage medium.
  • the target correspondence is the target correspondence of the reference processor.
  • the reference processor is the processor with the lowest power supply voltage of the multiple processors at the same main frequency, that is, the reference processor is the processor with the worst performance among the multiple processors.
  • the set supply voltage and the set voltage slope corresponding to each main frequency in the target correspondence relationship can satisfy the voltage adjustment of various processors. Therefore, the target correspondence relationship of the reference processor has wide applicability. It should be understood that a variety of processors can be distinguished according to production processes, aging degrees, etc., whether they are different production processes or different aging degrees, they will eventually be reflected in the form of performance difference information. For example, for processors of the same model, different batches of processors have slight differences in production processes, resulting in different batches of processors of the same model belonging to different types.
  • the foregoing target correspondence relationship is stored in a storage medium.
  • the foregoing target correspondence is the target correspondence of the processor included in the electronic device where the storage medium is located.
  • the target correspondence can be debugged and determined after the electronic device leaves the factory, and stored in the storage medium.
  • the above electronic device further includes a storage medium.
  • the storage medium stores target correspondences of the reference processor in multiple temperature gears.
  • the above method further includes: the processor searches for the target correspondence from the target correspondence of the reference processor in the multiple temperature gears according to the current temperature.
  • the target correspondence is the target correspondence of the reference processor in the temperature range where the current temperature is located. At this time, if the searched target correspondence is calibrated, the calibrated target correspondence can be better matched with the processor.
  • the electronic device is powered on, the CPM circuit detects the performance difference information, the above-mentioned processor sends the power supply adjustment information to the power supply according to the main frequency of the next time period, the above method It also includes: the processor searches for a target corresponding relationship that matches the processor included in the electronic device from the target corresponding relationship of the multiple types of processors according to the performance difference information.
  • the difference information of the processor corresponding to the target correspondence has a better match with the difference information of the CPM circuit test.
  • the CPM circuit detects the performance difference information, and before the processor sends the power supply adjustment information to the power supply according to the main frequency of the next time period, the method further includes: processing According to the current temperature, the target correspondence relationship of multiple processors in multiple temperature ranges is searched for the target correspondence relationship of multiple processors at the current temperature range; according to the performance difference information, the target correspondence between multiple processors at the current temperature is determined. In the target correspondence of the gears, a target correspondence that matches the processor included in the electronic device is searched.
  • the above-mentioned electronic device in order to cooperate with the processor to find a target correspondence that matches the processor included in the electronic device, includes a storage medium. Regardless of the influence of temperature, the above-mentioned electronic equipment also includes a storage medium.
  • the CPM circuit can be used to determine the performance difference information of multiple processors and the target correspondence between multiple processors before leaving the factory, and establish the relationship between the two And store the performance difference information of the multiple processors and the target correspondences of the multiple processors in the storage medium.
  • the CPM circuit can be used to determine the performance difference information of multiple processors at multiple temperature gears and the target correspondence between multiple processors at multiple temperature gears before leaving the factory, and establish multiple The interdependence between the performance difference information of the processors at multiple temperature gears and the target correspondences of the multiple processors at multiple temperature gears, and then compare the performance difference information of the multiple processors at multiple temperature gears with the multiple The target correspondences of the processor at multiple temperature levels are stored in the storage medium.
  • this application provides an electronic device.
  • the electronic device includes: a processor for sending power supply adjustment information to the power supply according to the main frequency of the next time period; the power supply adjustment information includes the set power supply voltage V of the main frequency of the next time period, and the main frequency of the next time period refers to the current main frequency Predicted main frequency; power supply, used to provide a supply voltage V out to the processor according to the set supply voltage V of the main frequency of the next time period and the set voltage slope R of the main frequency of the next time period.
  • V out Refers voltage slope increases as the load current of the power supply voltage lowering speed V out; a voltage V out of the power supply decreases with increase of the load current of the power supply; V min ⁇ V out ⁇ V, V min to a next processor The lowest power supply voltage for normal operation when the load current is increased during period main frequency operation.
  • the processor is also used to predict the load of the next period according to the current load before sending the power supply adjustment information to the power supply according to the main frequency of the next period of time, and determine the next period of time according to the load of the next period Main frequency.
  • the above-mentioned processor is further configured to set the current main frequency to be equal to the main frequency of the next time period when the processor determines that the main frequency of the next time period is not equal to the current main frequency.
  • the processor is also used to determine that the main frequency of the next time period is less than the current main frequency, and before sending the power supply adjustment information to the power supply according to the main frequency of the next time period, set the current main frequency to be equal to the main frequency of the next time period.
  • the power supply is used to provide the power supply voltage V out to the processor according to the set supply voltage V of the main frequency of the next time period and the set voltage slope R of the main frequency of the next time period, and the processor is specifically used to determine that the main frequency of the next time period is greater than the current Main frequency, set the current main frequency to be equal to the main frequency of the next time period.
  • the above-mentioned power supply voltage V out VI*R, and I is the load current of the power supply.
  • the above-mentioned processor is specifically configured to find the set supply voltage V of the main frequency of the next period from the target correspondence relationship according to the main frequency of the next period, and send the set of the main frequency of the next period to the power supply.
  • Set the supply voltage V is the correspondence relationship between the processor's main frequency, the set supply voltage and the set voltage slope, or the correspondence relationship between the processor's main frequency and the set supply voltage.
  • the above-mentioned set voltage slope of the main frequency for the next period of time exists in the power supply in the form of a constant voltage slope.
  • the constant voltage slope is the minimum value R min of the allowable voltage slope of the set supply voltage of the processor at each main frequency, R min >0.
  • the above-mentioned power supply adjustment information further includes the set voltage slope R of the main frequency in the next time period.
  • the above-mentioned processor is specifically configured to find the set supply voltage V of the main frequency of the next time period and the set voltage slope R of the main frequency of the next time period from the target correspondence relationship according to the main frequency of the next time period. , And send to the power supply the set supply voltage V of the main frequency of the next time period and the set voltage slope R of the main frequency of the next time period.
  • the target correspondence relationship is the correspondence relationship between the processor's main frequency, the set supply voltage, and the set voltage slope.
  • the set voltage slope of the processor at each main frequency is the allowable voltage slope of the set supply voltage of the processor at each main frequency.
  • the set voltage slopes of the above-mentioned processor at all main frequencies are equal to the constant voltage slopes.
  • the constant voltage slope is the minimum value R min of the allowable voltage slope of the set supply voltage of the processor at each main frequency, R min >0.
  • the set supply voltage V (i) V min(i) + ⁇ V (i) of the above-mentioned processor at each main frequency
  • V min(i) is the processor at each main frequency.
  • ⁇ V (i) is the power supply voltage margin of the processor at each main frequency.
  • the above-mentioned processor is further configured to calibrate the target correspondence according to the performance difference information before sending the power supply adjustment information to the power supply according to the main frequency of the next time period, so that the calibrated target correspondence is the same as that of the electronic device.
  • the included processors match.
  • the above-mentioned processor is specifically configured to find the lowest power supply voltage difference from the corresponding relationship between the performance differences of multiple processors and the lowest power supply voltage difference according to the performance difference information,
  • the set supply voltage corresponding to each main frequency in the target correspondence is calibrated according to the minimum power supply voltage difference, so that the calibrated target correspondence matches the processor included in the electronic device.
  • the above-mentioned processor is specifically used for the processor to find the current temperature of the various processors from the corresponding relationship between the performance differences of the various processors at multiple temperature levels and the minimum power supply voltage differences according to the current temperature.
  • the corresponding relationship between the performance difference of the current temperature range and the minimum power supply voltage difference, according to the performance difference information find the current performance difference information match from the corresponding relationship between the performance difference of the various processors at the current temperature range and the minimum power supply voltage difference
  • the set supply voltage corresponding to each main frequency in the target correspondence is calibrated, so that the calibrated target correspondence matches the processor included in the electronic device .
  • the above-mentioned electronic device contains a storage medium.
  • the storage medium may exist independently of the processor, or may be built in the processor.
  • the foregoing target correspondence relationship may be directly or indirectly stored in the storage medium in a variety of ways.
  • the storage medium may also store the corresponding relationship between the difference in performance of multiple processors and the difference in the lowest power supply voltage, or the corresponding relationship between the difference in performance of multiple processors at multiple temperature levels and the difference in the lowest power supply voltage.
  • the corresponding relationship between the difference in performance of various processors and the difference in the lowest power supply voltage may be stored in the storage medium in the form of a relationship table or a functional relationship.
  • the corresponding relationship between the performance difference of the various processors at multiple temperature levels and the minimum power supply voltage difference is stored in the storage medium in the form of a relationship table or a functional relationship.
  • the foregoing target correspondence is stored in a storage medium, and the target correspondence is the target correspondence of the reference processor.
  • the benchmark processor is the processor with the lowest power supply voltage and the largest multiple processors at the same main frequency.
  • the foregoing target correspondence relationship is stored in a storage medium.
  • the foregoing target correspondence is the target correspondence of the processor included in the electronic device where the storage medium is located.
  • the target correspondence can be debugged and determined after the electronic device leaves the factory, and stored in the storage medium.
  • the above electronic device further includes a storage medium.
  • the storage medium stores target correspondences of the reference processor in multiple temperature gears.
  • the benchmark processor is the processor with the lowest power supply voltage and the largest multiple processors at the same main frequency.
  • the processor is further configured to search for the target correspondence from the target correspondence of the reference processor in the multiple temperature gears according to the current temperature before sending the power supply adjustment information to the power supply according to the main frequency of the next time period.
  • the target correspondence is the target correspondence of the reference processor in the temperature range where the current temperature is located.
  • the processor is also used to obtain information from multiple processor targets based on the performance difference information before sending the power supply adjustment information to the power supply according to the main frequency of the next time period.
  • a target correspondence relationship that matches the processor included in the electronic device is searched.
  • the processor is also used to search for multiple target correspondences from multiple processors in multiple temperature gears based on the current temperature before sending power supply adjustment information to the power supply according to the main frequency of the next time period.
  • the target correspondence of the processor in the temperature range where the current temperature is located; according to the performance difference information, the target correspondence relationship that matches the processor included in the electronic device is searched from the target correspondences of the various processors in the temperature range where the current temperature is located.
  • the foregoing electronic device includes a storage medium.
  • the storage medium stores the performance difference information of multiple processors and the target correspondences of multiple processors, and the performance difference information of multiple processors and the target correspondences of multiple processors have Interdependence.
  • the performance difference information of multiple processors at multiple temperature gears and the target correspondences of multiple processors at multiple temperature gears are stored in the storage medium, and the multiple processors are stored in the storage medium.
  • the performance difference information of each temperature gear has a mutual dependence relationship with the target correspondences of multiple processors in the multiple temperature gears.
  • this application also provides a processor.
  • the processor includes one or more modules configured to implement the steps executed by the processor in the first aspect described above, and the one or more modules may correspond to the steps executed by the processor in the method of the first aspect described above.
  • this application provides a power source.
  • the power supply includes one or more modules for implementing the steps performed by the power supply in the first aspect described above, and the one or more modules may correspond to the steps performed by the power supply in the method of the first aspect described above.
  • this application provides a terminal device.
  • the terminal device includes a processor and a power supply.
  • the processor is configured to execute the steps executed by the processor as described in the first aspect or any one of the possible implementation manners of the first aspect, and the power supply is configured to execute any one of the first aspect or the first aspect. The realization of the steps described by the power supply.
  • the foregoing terminal device further includes a storage medium for storing the computer program and the target correspondence.
  • the present application provides a communication device that includes a processor and a power supply, and the processor is configured to execute the process executed by the processor as described in the first aspect or any one of the possible implementation manners of the first aspect.
  • the power supply is used to execute the steps performed by the power supply as described in the first aspect or any one of the possible implementation manners of the first aspect.
  • the aforementioned communication device further includes a storage medium for storing the computer program and the target correspondence.
  • this application also provides a chip.
  • the chip includes a processor and a communication interface coupled with the communication interface.
  • the processor is used to run a computer program or instruction to implement the steps executed by the processor as described in the first aspect or any possible implementation manner of the first aspect.
  • the above-mentioned chip further includes a memory for storing computer programs or instructions and target correspondences.
  • this application also provides a chip.
  • the chip includes a processor and a communication interface coupled with the communication interface.
  • the processor is used to run a computer program or instruction to implement the steps executed by the power supply as described in the first aspect or any possible implementation manner of the first aspect.
  • the above-mentioned chip further includes a memory for storing a computer program.
  • any device or computer storage medium or computer program product or chip or communication system provided above is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the corresponding method provided above The beneficial effects of the corresponding solutions in the method will not be repeated here.
  • FIG. 1 is a schematic structural diagram of an electronic device provided by an embodiment of the application.
  • FIG. 2 is a schematic diagram of the connection structure between the processor and the power supply in an embodiment of the application
  • FIG. 3 is a system architecture diagram of a vehicle communication system provided by an embodiment of this application.
  • FIG. 4 is a first flowchart of a voltage adjustment method provided by an embodiment of this application.
  • FIG. 5 is a second schematic flowchart of a voltage adjustment method provided by an embodiment of this application.
  • Figure 6 is a schematic diagram of the transient process of the power supply load
  • Figure 7 is a schematic diagram of power loadline characteristics
  • Figure 8 is a schematic diagram of the mechanism of DVFS technology to reduce power consumption
  • Figure 9 is a comparison diagram of the application method, DVFS technology, and fixed voltage method for power supply;
  • Figure 10 is the processor's main frequency and voltage slope curve
  • FIG. 11 is a third flowchart of a voltage adjustment method provided by an embodiment of the application.
  • FIG. 12 is a fourth flowchart of a voltage adjustment method provided by an embodiment of this application.
  • FIG. 13 is a fifth schematic flowchart of a voltage adjustment method provided by an embodiment of this application.
  • Figure 14 is a graph of the voltage slope of the supply voltage in the rated mode
  • Figure 15 is a graph of voltage slopes in different power consumption modes
  • FIG. 16 is a schematic structural diagram of a device provided by an embodiment of this application.
  • FIG. 17 is a schematic structural diagram of a voltage adjusting device provided by an embodiment of the application.
  • FIG. 18 is a schematic structural diagram of another voltage adjusting device provided by an embodiment of the application.
  • FIG. 19 is a schematic structural diagram of yet another voltage adjusting device provided by an embodiment of the application.
  • FIG. 20 is a schematic structural diagram of a chip provided by an embodiment of the application.
  • Dynamic voltage and frequency scaling refers to: dynamically adjusting the operating frequency and voltage of the chip according to the different needs of the application program running on the chip for computing power (for the same chip, the higher the frequency, The higher the voltage required), so as to achieve the purpose of energy saving. Specifically, when the processor load is light, the processor clock speed and power supply voltage are reduced; when the processor load is heavy, the processor clock speed and power supply voltage are increased to reduce the power consumption of the processor.
  • Intel Turbo Boost Technology is also known as Turbo Boost Technology, or Turbo Technology for short.
  • Turbo technology is an automatic overclocking (OC) technology for multi-core central processing units. When the core of the central processing unit does not reach the temperature, current, and power consumption specification thresholds, Turbo technology will automatically allow certain active cores of the central processing unit to run beyond the rated frequency, improving processor performance and coping with peak loads.
  • BIOS Basic Input Output System
  • BIOS Basic Input Output System
  • the adaptive voltage scaling (adaptive voltage scaling, abbreviated as AVS) technology is a real-time, closed-loop control power management technology that can continuously adjust the supply voltage.
  • the AVS technology can be implemented by a critical path monitor (CPM) circuit.
  • the CPM circuit is used to simulate the timing critical path of the reference processor, and then determine the performance difference information such as the delay level or the oscillation frequency, so as to adaptively adjust the circuit power supply level according to the performance difference information to ensure that the delay level or the oscillation frequency is satisfied Under the premise of system requirements, reduce the voltage as much as possible.
  • VID Voltage Identification Code
  • VID code refers to a code that represents a voltage value, which is essentially a digitized voltage value.
  • a voltage regulator module (Voltage Regulator Module, VRM) is a device that provides a suitable supply voltage for the microprocessor, also known as a VRM power supply.
  • the VRM power supply can recognize the VID code to adjust the output constant voltage supply voltage, so that the output constant voltage supply voltage is consistent with the voltage value represented by the VID code.
  • the integrated 8bit VID code inside the VRM power supply represents 256 voltage values.
  • the processor sends the 8bit VID code to the VRM power supply.
  • the VRM power supply can use the integrated 8bit VID code to identify the VID code sent by the processor to determine Supply voltage.
  • Load line also known as Loadline
  • Loadline means that the power supply voltage output by the VRM power supply has a characteristic curve that linearly decreases as the load current increases.
  • the voltage drop slope is abbreviated as the voltage slope or Loadline value, which represents the linear drop speed of the supply voltage as the load current of the power supply such as a VRM power supply increases.
  • Loadline value represents the linear drop speed of the supply voltage as the load current of the power supply such as a VRM power supply increases.
  • Phase locked loop Phase Locked Loop
  • PLL Phase Locked Loop
  • It is a typical feedback control circuit that uses an externally input reference signal to control the frequency and phase of the oscillation signal inside the loop, and realizes the automatic tracking of the output signal frequency to the input signal frequency. It is generally used in a closed-loop tracking circuit.
  • a digital-to-analog converter is a device that converts a digital signal into an analog signal (in the form of current, voltage, or charge).
  • the Power Management Bus is a bus that supports an open standard digital power management protocol.
  • Open standard digital power management protocols can facilitate communication with power converters or other devices by defining transmission and physical interfaces and command languages.
  • words such as “first” and “second” are used to distinguish the same items or similar items that have substantially the same function and effect.
  • the first threshold and the second threshold are only for distinguishing different thresholds, and the order of their order is not limited.
  • words such as “first” and “second” do not limit the quantity and execution order, and words such as “first” and “second” do not limit the difference.
  • At least one refers to one or more, and “multiple” refers to two or more.
  • And/or describes the association relationship of the associated objects, indicating that there can be three relationships, for example, A and/or B, which can mean: A alone exists, A and B exist at the same time, and B exists alone, where A, B can be singular or plural.
  • the character “/” generally indicates that the associated objects before and after are in an “or” relationship.
  • the following at least one item (a) or similar expressions refers to any combination of these items, including any combination of a single item (a) or a plurality of items (a).
  • At least one of a, b, or c can mean: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a combination of a, b and c Combination, where a, b, and c can be single or multiple.
  • the method provided in the embodiment of the present application is applied to an electronic device.
  • the electronic device can be applied to a terminal or a communication device.
  • the terminal can be in various terminal devices such as a vehicle-mounted terminal, a mobile phone, a computer, and a server.
  • the communication equipment may be various communication equipment such as base stations and satellites.
  • Fig. 1 shows a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the electronic device 100 includes a processor 101, a power supply 102 and a storage medium 103.
  • the processor 101 and the power supply 102 can be integrated together or can exist independently.
  • the processor 101 can cover various general-purpose processors of terminals and data center equipment. Of course, it can also be a vehicle-mounted processor, but it is not limited to this list.
  • the processor 101 may include one or more CPUs.
  • the storage medium 103 is coupled to the processor, and can store computer-executed instructions and data for executing the solution of the present application, and the processor 101 controls the execution.
  • the processor 101 is configured to execute computer-executable instructions stored in a storage medium, so as to implement the methods provided in the following embodiments of the present application.
  • the computer-executable instructions in the embodiments of the present application may also be referred to as application program codes, which are not specifically limited in the embodiments of the present application.
  • the aforementioned storage medium 103 may exist independently of the processor 101 or may be built in the processor 101.
  • the storage medium 103 may be a built-in memory in the processor 101 or a BIOS memory on the main board.
  • the above-mentioned processor 101 may be a central processing unit (Central Processing Unit, abbreviated as CPU) general-purpose processor, digital signal processing (DSP), ASIC, ready-made programmable gate array (field- programmable gate array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • the memory may be a random access memory (RAM), or may include a non-volatile memory (non-volatile memory), such as a magnetic disk memory, a flash memory (Flash), etc., which will not be listed one by one.
  • the memory may be an external memory such as a memory on the main board (such as a BIOS memory), or may be a built-in memory of the processor.
  • the storage medium 103 may be a built-in memory inside the CPU.
  • the above-mentioned storage medium 103 may be random access memory (Random Access Memory, RAM), flash memory, read only memory (Read Only Memory, ROM), erasable programmable read only memory (Erasable Programmable ROM), EPROM), electrically erasable programmable read-only memory (Electrically EPROM, EEPROM), registers, hard disk, mobile hard disk, CD-ROM, or any other form of storage medium known in the art.
  • RAM Random Access Memory
  • ROM read only memory
  • ROM erasable programmable read only memory
  • EPROM erasable programmable read only memory
  • Electrically erasable programmable read-only memory Electrically erasable programmable read-only memory
  • registers hard disk, mobile hard disk, CD-ROM, or any other form of storage medium known in the art.
  • Fig. 2 shows a schematic diagram of the connection structure between the processor and the power supply in an embodiment of the present application.
  • the processor 101 includes a processor core 1011 and a phase locked loop 1013.
  • the phase-locked loop 1013 adjusts or sets the main frequency of the processor under the control of the processor core 1011.
  • the processor 101 further includes a built-in memory 1012, the built-in memory 1012 can implement the functions of the storage medium 103 described above, thereby reducing unnecessary hardware in the electronic device and making the electronic device more integrated.
  • the aforementioned processor 101 further includes a CPM circuit 1015, and the CPM circuit 1015 is electrically connected to the processor core 1011.
  • the power supply 102 shown in FIG. 1 can be a variety of power supplies with a voltage regulation function, and can provide a power supply voltage to the processor 101.
  • the power supply 102 shown in FIG. 2 is a schematic structural diagram of a VRM power supply as an example.
  • the power supply 102 includes a VRM chip 1021, a logic control circuit 1022 and a buck converter 1023.
  • the VRM chip 1021 is connected to the signal input terminal of the logic control circuit 1022, and the signal output terminal of the logic control circuit 1022 is electrically connected to the buck converter 1023, so that the VRM chip 1021 provides the logic control circuit 1022 with a signal carrying information.
  • the power supply 102 may also include a register 1024 or other devices with a storage function, which can store information for the VRM chip 1021 to retrieve.
  • the buck converter 1023 may also be independent of the power supply 102 and be arranged between the power supply 102 and the processor 101.
  • the buck converter 1023 includes a grounded capacitor C and a plurality of inductances L connected in parallel, and the first end of the inductances L connected in parallel and the signal output end of the logic control circuit 1022 Connected, the second ends of the inductances L connected in parallel are also grounded through the grounding capacitor C.
  • the connection relationship of the buck converter 1023 is a multi-channel interleaved parallel quasisquare-wave (QSW) topology, which has a good ripple cancellation effect, and the more the number of inductances connected in parallel, the ripple mutual The better the elimination effect.
  • QSW quasisquare-wave
  • the number of inductances L connected in parallel is set according to actual needs. However, the number of these inductors L is at least two.
  • the aforementioned processor 101 and the power supply 102 can communicate with each other.
  • the aforementioned processor 101 includes a communication interface 1014.
  • the above-mentioned power supply 102 includes a communication interface 1025 for implementing communication between the processor 101 and the power supply 102.
  • the processor 101 and the power supply 102 are connected via a bus or power line.
  • the bus can be a power management bus (Power Management Bus, abbreviated as PMBus bus), which is an I2C (Inter-Integrated Circuit) bus.
  • PMBus bus Power Management Bus
  • I2C Inter-Integrated Circuit
  • the method provided in the embodiments of the present application can be implemented by any general-purpose processor or application specific circuit (ASIC).
  • ASIC application specific circuit
  • Fig. 3 is a system architecture diagram of a vehicle communication system provided by an embodiment of the present application.
  • similar symbols identify similar components unless the context dictates otherwise.
  • the illustrative system and method embodiments described herein are not intended to be limiting. It can be readily understood that certain aspects of the disclosed systems and methods can be arranged and combined in a variety of different configurations, all of which are contemplated herein.
  • the vehicle communication system 10 includes a vehicle 12, one or more wireless carrier systems 14, a ground communication network 16, a computer 18 and a call center 20. It should be understood that the disclosed method can be used with any number of different systems and is not specifically limited to the operating environment shown here. Likewise, the architecture, construction, setup, and operation of the communication system 10 and its individual components are generally known in the prior art. Therefore, the following paragraphs simply provide an overview of an example communication system 10, and other systems not shown herein can also use the disclosed method.
  • the aforementioned vehicle 12 may be an unmanned vehicle or a manned vehicle.
  • the vehicle 12 may be implemented on a car or may take the form of a car.
  • the example system can also be implemented on other vehicles or take the form of other vehicles, such as cars, trucks, motorcycles, buses, boats, airplanes, helicopters, lawn mowers, snow shovel, RV, amusement park vehicles , Agricultural equipment, construction equipment, trams, golf carts, trains and trams and other vehicles.
  • robotic devices can also be used to perform the methods and systems described herein.
  • the vehicle hardware 28 includes an information communication unit 30, a microphone 32, one or more buttons or other control inputs 34, an audio system 36, a visual display 38, and a GPS (Global Position System, global positioning system) module 40 and multiple VM module 42 (Vehicle Security Module, in order to be different from the previous VSM power supply, here is abbreviated as VM, and the Chinese name is vehicle security unit).
  • VM Vehicle Security Module
  • Some of these devices can be directly connected to the information communication unit, such as the microphone 32 and the button 34, while others use one or more network connections to achieve indirect connection, such as the communication bus 44 or the entertainment bus 46.
  • Suitable network connections include CAN (Controller Area Network), MOST (Media Oriented Systems Transport), LIN (Local Interconnect Network), LAN (Local Area Network, local area network) And other suitable connections, such as Ethernet or conforming to known ISO (International Organization for Standardization), SAE (Society of Automotive Engineers, American Society of Motor Vehicle Engineers) and IEEE (Institute of Electrical and Electronics Engineers, International Organization for Standardization) These are just a few of the other connections specified by the Institute of Electrical and Electronics Engineers) standards and regulations.
  • ISO International Organization for Standardization
  • SAE Society of Automotive Engineers, American Society of Motor Vehicle Engineers
  • IEEE Institute of Electrical and Electronics Engineers, International Organization for Standardization
  • the information communication unit 30 may be an OEM (Original Equipment Manufacturer) installation (embedded) or aftermarket equipment. It is installed in a vehicle and can be installed on the wireless carrier system 14 and via wireless Networking for wireless voice and/or data communication. This enables the vehicle to communicate with the call center 20, other vehicles that enable information communication, or some other entities or devices.
  • the information communication unit preferably uses radio broadcasting to establish a communication channel (sound channel and/or data channel) with the wireless carrier system 14 so that voice and/or data transmission can be sent and received on the channel.
  • a communication channel sound channel and/or data channel
  • the information communication unit 30 enables the vehicle to provide a variety of different services, including those related to navigation, telephone, emergency rescue, diagnosis, infotainment, and the like.
  • Data can be sent via a data connection (for example, via packet data transmission on a data channel, or via a voice channel using techniques known in the art).
  • a data connection for example, via packet data transmission on a data channel, or via a voice channel using techniques known in the art.
  • voice communication for example, live advisors or voice response units at the call center 20
  • data communication for example, providing GPS location data or vehicle diagnostic data to the call center 20
  • SMS short message service
  • SMS can be used to send and receive data (for example, PDP (Packet Data Protocol, packet data protocol));
  • the information communication unit can be configured for mobile termination and/or initiation, or configured for application termination and/or Initiated.
  • the above-mentioned information communication unit 30 utilizes cellular communication in accordance with the GSM (Global System for Mobile Communication) or CDMA (Code Division Multiple Access, Code Division Multiple Access) standards, and therefore includes a voice communication (for example, hands-free call)
  • a cellular chipset 50 standard cellular chipset
  • a wireless modem for data transmission for example, hands-free call
  • the modem can be implemented by software stored in the information communication unit and executed by the processing device 52, or it can be a separate hardware component located inside or outside the information communication unit 30.
  • Modems can use any number of different standards or protocols (such as EVDO (CDMA20001xEV-DO, EVDO), CDMA, GPRS (General Packet Radio Service, General Packet Radio Service) and EDGE (Enhanced Data Rate for GSM Evolution), enhanced data rate GSM evolution technology)) to run.
  • Wireless networking between vehicles and other networked devices can also be performed using the information communication unit 30.
  • the information communication unit 30 can be configured to wirelessly communicate according to one or more wireless protocols (for example, any one of the IEEE 802.11 protocol, WiMAX (Worldwide Interoperability for Microwave Access, Worldwide Interoperability for Microwave Access), or Bluetooth) .
  • the information communication unit can be configured with a static IP address, or can be set to Another device (such as a router) or automatically receives the assigned IP address from a network address server.
  • TCP/IP Transmission Control Protocol/Internet Protocol
  • the information communication unit can be configured with a static IP address, or can be set to Another device (such as a router) or automatically receives the assigned IP address from a network address server.
  • the aforementioned processing device 52 is an on-board processor.
  • the processing device 52 may be any type of device capable of processing electronic instructions, including a microprocessor, a microcontroller, a main processor, a controller, a vehicle communication processor, and an ASIC (Application Specific Integrated Circuit, application specific integrated circuit) . It can be a dedicated processor used only for the information communication unit 30 or can be shared with other vehicle systems.
  • the processing device 52 executes various types of digital storage instructions, such as software or firmware programs stored in the memory 54, which enables the information communication unit to provide a wide variety of services. Specifically, the processing device 52 can execute programs or process data to perform at least a part of the methods discussed herein.
  • the processing device 52 may be an electronic device applying the method of the present application.
  • the above-mentioned information communication unit 30 can be used to provide different range of transportation services, including wireless communication with other parts of the transportation.
  • Such services include: steering guidance turn-by-turn direct 1ns and other navigation-related services provided in conjunction with GPS-based vehicle navigation module 40; airbag deployment notifications and communication with one or more collision sensor interface modules (such as The main body control module (not shown) is combined with other emergency or roadside rescue related services provided.
  • infotainment-related services where music, web pages, movies, TV shows, video games, and/or other information are downloaded by the infotainment module and stored for current or later playback.
  • the services listed above are by no means an exhaustive list of all the capabilities of the information communication unit 30, but merely a list of some services that the information communication unit can provide.
  • the above modules can be implemented in the form of software instructions stored inside or outside the information communication unit 30, they may be hardware components located inside or outside the information communication unit 30, or they may be integrated and integrated with each other. /Or shared, or integrated and/or shared with other systems located throughout the vehicle, to name just a few possibilities.
  • the VM modules 42 located outside the information communication unit 30 are in operation, they can use the vehicle bus 44 to exchange data and commands with the information communication unit 30.
  • the GPS module 40 receives radio signals from GPS satellites 60. From these signals, the GPS module 40 can determine the location of the vehicle, and the location of the vehicle is used to provide navigation and other location-related services to the vehicle driver.
  • the navigation information can be presented on the display 38 (or other display in the vehicle) or can be presented in language, for example when steering navigation is provided.
  • the navigation module (which can be part of the GPS module 40) in a dedicated vehicle can be used to provide navigation services, or some or all of the navigation services can be completed via the information communication unit 30, where the location information is sent to a remote location for convenience Provide navigation maps, map annotations (points of interest, restaurants, etc.), route calculations, etc. for transportation.
  • the location information can be provided to the call center 20 or other remote computer systems, such as the computer 18, for other purposes, such as fleet management.
  • new or updated map data can be downloaded from the call center 20 to the GPS module 40 via the information communication unit 30.
  • the vehicle 12 can include other vehicle safety modules in the form of electronic hardware components, namely the VM module 42, which is located throughout the vehicle and usually receives input from one or more sensors. , And use the sensed input to perform diagnostics, monitoring, control, reporting, and/or other functions.
  • Each of the VM modules 42 is preferably connected to the VM module 42 via a communication bus 44, and also to the information communication unit 30, and can be programmed to run vehicle system and subsystem diagnostic tests.
  • one VM module 42 can be an ECM (Engine Control Module) that controls various aspects of engine operation (for example, fuel ignition and ignition timing), and the other VM module 42 can be one or one that regulates the power train of the vehicle.
  • ECM Engine Control Module
  • a powertrain control module for the operation of multiple components, and another VM module 42 can be a main body control module that manages various electrical components (such as electric door locks and headlights of the vehicle) located in the entire vehicle.
  • the engine control module is equipped with OBD (On Board Diagnostics) features, which provide a large amount of real-time data, such as data received from various sensors (including vehicle emission sensors), and provide standardized series Diagnose fault codes, which allow technicians to quickly identify and repair faults in vehicles.
  • OBD On Board Diagnostics
  • the VM modules mentioned above are only examples of some modules that can be used in the vehicle 12, and many other modules are also possible.
  • the vehicle electronics 28 also includes a plurality of vehicle user interfaces, which provide a device for providing and/or receiving information for vehicle drivers and passengers, including a microphone 32, a button 34, an audio system 36, and a visual display 38.
  • vehicle user interface broadly includes any suitable form of electronic equipment, including hardware and software components, which are located on the vehicle and enable the user of the vehicle to communicate with the components of the vehicle Or communicate through the components of the vehicle.
  • the microphone 32 provides audio input to the information communication unit, so that the driver or other passengers can provide voice commands and perform hands-free protection calls via the wireless carrier system 14. For this purpose, it can be connected to a vehicle-mounted automated sound processing unit, which utilizes HMI (Human Machine Interface) technology known in the prior art.
  • HMI Human Machine Interface
  • the button 34 allows manual user input to the information communication unit 30 to initiate a wireless telephone call and provide other data, response, or control input. Separate buttons can be used to initiate emergency calls and regular service help calls to the call center 20.
  • the audio system 36 provides audio output to vehicle drivers and can be a dedicated stand-alone system or part of the main vehicle audio system. According to the specific embodiment shown here, the audio system 36 is operatively connected to the vehicle bus 44 and the entertainment bus 46, and can provide AM (Amplitude Modulation), FM (Frequency Modulation), satellite broadcasting, DVD (Digital Versatile Disc) and other multimedia functions. This function can be provided in combination with the infotainment module described above or independently.
  • the visual display 38 is preferably a graphic display, such as a touch screen on the dashboard or a head-up display reflecting off the windshield, and can be used to provide a variety of input and output functions.
  • Various other vehicle user interfaces can also be utilized, as the interface in Figure 3 is only an example of a specific implementation.
  • the wireless carrier system 14 is preferably a cellular phone system, including multiple cellular towers 70 (only one is shown), one or more MSC (Mobile Switching Center, mobile switching center) 72, and the wireless carrier system 14 is connected to the ground network 16 Any other networking components required.
  • Each cell tower 70 includes transmitting and receiving antennas and base stations, and base stations from different cell towers are directly connected to the MSC 72 or connected to the MSC 72 via an intermediate device (such as a base station controller).
  • the wireless carrier system 14 can implement any suitable communication technology, including, for example, analog technology (such as AMPS (Advanced Mobile Phone System, analog mobile communication system)) or newer digital technology (such as CDMA (such as CDMA2000) or GSM/GPRS).
  • each base station can respond to a single cell tower or a single base station can serve each cell tower, and each base station can be connected to a single MSC. This is just an example. Give a few possible settings.
  • different wireless carrier systems in the form of satellite communication can be used to provide one-way or two-way communication with the vehicle. This can be done using one or more communication satellites 62 and uplink transmitting stations 64.
  • the one-way communication can be, for example, a satellite broadcast service, where program content (news, music, etc.) is received by a transmitting station 64, packaged for upload, and then sent to a satellite 62, which broadcasts the program to users.
  • the two-way communication can be, for example, a satellite telephone service that uses satellite 62 to relay telephone communications between vehicle 12 and station 64. If used, such a satellite phone can be added to the wireless carrier system 14 or used instead of the wireless carrier system 14.
  • the ground network 16 may be a conventional land-based radio communication network, which is connected to one or more fixed telephones and connects the wireless carrier system 14 to the call center 20.
  • the ground network 16 may include a PSTN (Public Switched Telephone Network), such as the PSTN used to provide wired telephones, packet-switched data communications, and Internet infrastructure.
  • PSTN Public Switched Telephone Network
  • One or more parts of the ground network 16 can use standard wired networks, optical fibers or other optical networks, cable networks, power lines, other wireless networks (such as WLAN (Wireless Local Area Networks, wireless local area networks)), or provide BWA (Broadband Wireless Access, broadband wireless access) network and any combination thereof.
  • WLAN Wireless Local Area Networks, wireless local area networks
  • BWA Broadband Wireless Access, broadband wireless access
  • the ground network 16 may also include one or more SMSC (Short Message Service Center) for storing, uploading, converting, and/or transmitting SMS (Short Message Service, short message) between the sender and the receiver. ).
  • SMSC Short Message Service Center
  • the SMSC may receive an SMS message from the call center 20 or a content provider (for example, an external short message entity or ESME), and the SMSC may transmit the SMS message to the vehicle 12 (for example, a mobile terminal device). SMSCs and their functions are known to the skilled person.
  • the call center 20 does not have to be connected via the ground network 16, but may include wireless telephone equipment so that it can directly communicate with the wireless network (e.g., the wireless carrier system 14).
  • the computer 18 can be one of a plurality of computers, which can be accessed via a private or public network (such as the Internet). Each such computer 18 can be used for one or more purposes. For example, a vehicle can access a web server via the information communication unit 30 and the wireless carrier system 14. Other such accessible computers 18 can be, for example, a service center computer, in which diagnostic information and other vehicle data can be uploaded from the vehicle via the information communication unit 30; a client used by vehicle owners or other users for, for example, the following purposes Computer: Access or receive vehicle data, or set or configure user parameters, or control vehicle functions; or third-party libraries, whether through communication with vehicle 12 or call center 20, or with both, vehicle data Or other information is provided to or from the third-party library.
  • the computer 18 can also be used to provide Internet connection, such as DNS (Domain Name Server, domain name server) service, or as a DHCP (Dynamic host configuration protocol) or other suitable protocol to assign IP addresses to vehicles 12 network address server.
  • DNS Domain Name Server, domain name server
  • the call center 20 is designed to provide a variety of different system back-end functions to the vehicle electronics 28, and according to the exemplary embodiment shown here, the call center 20 generally includes one or more switches 80, servers 82, and databases. 84. On-site consultant 86, and VRS (Automatic Voice Response System) 88, all of which are known in the prior art. These various call center components are preferably connected to each other via a wired or wireless local area network 90.
  • the switch 80 can be a PBX (Private Branch Exchange, dedicated branch exchange), which routes incoming signals so that the voice transmission is usually sent to the on-site consultant 86 through ordinary telephones or sent to the automatic voice response system 88 using VoIP.
  • PBX Primary Branch Exchange, dedicated branch exchange
  • On-site consultant calls can also use VoIP (Voice over Internet Phone), as indicated by the dotted line in Figure 3.
  • VoIP and other data communication through the switch 80 are implemented via a modem (not shown) connected between the switch 80 and the network 90.
  • the data transmission is passed to the server 82 and/or the database 84 via the modem.
  • the database 84 can store account information, such as user authentication information, vehicle identifiers, profile records, behavior patterns, and other related user information.
  • Data transmission can also be performed by wireless systems, such as 802.1lx, GPRS, and so on.
  • SMS short message service
  • PDP personal data packet data
  • the call center 20 may be configured for mobile termination and/or initiation, or configured for application termination and/or initiation.
  • the vehicle-mounted environment temperature of the unmanned Giti tool is high (for example, the internal environment temperature of the car center console can reach 85 degrees). Coupled with the high computing power and high power consumption of the autonomous driving processor itself, the temperature of the processor core has risen sharply, which limits the further increase of the processor's computing power. In order to ensure that the core temperature of the processor in the processing equipment is not too high under high computing power, in addition to improving the cooling system capacity, it is more important to effectively reduce the power consumption of the processor through power reduction technology. The related technology can only reduce power consumption when the processor is under low load.
  • the processor load is relatively high, in order to ensure the processing speed of the processor, the power consumption of the processor is still difficult to reduce. Therefore, the chip integration of the processor in the related technology cannot be further improved, and it limits the Turbo technology in the processor.
  • the further application in the CPU the performance of the processor cannot be further improved.
  • a cooling system is required to cool the processor, which further increases the cooling cost of the processor. For example: when the energy consumption of the data center increases, a cooling system with higher cooling performance is required to cool the data center.
  • an embodiment of the present application provides a voltage adjustment method.
  • the steps executed by the processor in the method provided in the embodiments of the application can also be executed by the chip applied to the processor, and the steps executed by the power supply can also be executed by the chip applied to the power supply.
  • the following embodiments deal with The controller and the power supply are respectively taken as the executive body as examples.
  • FIG. 4 shows a schematic flowchart of a voltage adjustment method provided by an embodiment of the present application.
  • an embodiment of the present application provides a voltage adjustment method.
  • the method is applied to electronic devices with processors and power supplies.
  • the power supply can supply power to the processor.
  • the method includes:
  • Step 101 The processor sends power supply adjustment information to the power supply according to the main frequency of the next time period.
  • the power supply adjustment information includes the set power supply voltage V of the main frequency in the next time period, which is defined as the set power supply voltage determined by the processor according to the main frequency of the next time period when the processor is running at a certain main frequency.
  • V of the main frequency in the next time period which is defined as the set power supply voltage determined by the processor according to the main frequency of the next time period when the processor is running at a certain main frequency.
  • it can be determined by a single DVFS technology. That is, based on the main frequency of the next time period, the corresponding relationship between the main frequency of the processor and the set power supply voltage is searched for the set power supply voltage corresponding to the main frequency of the next time period.
  • the duration of the next period mentioned above can be taken in minutes according to actual conditions.
  • the duration of the next period is 10ms-50ms.
  • the duration of the next period is 50ms.
  • the main frequency of the next period refers to the main frequency predicted according to the current main frequency. That is to say, before step 101, it should also include step 100: the processor predicts the main frequency of the next time period according to the current load.
  • the processor collects the current load in real time, predicts the load in the next period according to the collected current load, and determines the main frequency of the next period according to the load in the next period.
  • the current load can be the processor occupancy rate, the amount of application execution, or the amount of tasks.
  • the frequency switching information is stored in the internal memory of the motherboard or the processor.
  • the preset main frequency is determined according to the predicted load in the next time period, and the main frequency of the next time period is searched from the main frequency switching information according to the preset main frequency.
  • the main frequency switching information includes multiple main frequency frequency points, and the smallest main frequency frequency point is selected as the main frequency of the next period from one or more main frequency frequency points greater than the preset main frequency.
  • the main frequency switching information includes multiple frequency points of 1.0 GHz, 1.5 GHz, and 2.0 GHz.
  • the main frequency of the next period is 1.3GHz, it means that the main frequency of the next period should be switched to 1.5GHz.
  • the main frequency of the next time period is 1.7GHz, it means that the main frequency of the next time period should be switched to 2.0GHz.
  • Step 102 The power supply receives the power supply adjustment information sent by the processor. For example, if the processor and the power supply communicate using the PMBus bus, the power supply uses the PMBus interface to receive power supply adjustment information.
  • Step 103 The power supply provides the power supply voltage V out to the processor according to the set supply voltage V of the main frequency in the next time period and the set voltage slope R of the main frequency in the next time period.
  • the voltage slope here refers to the decreasing speed of the supply voltage V out as the load current of the power supply increases, also known as the loadline value, which is based on the dimension of the resistance.
  • the supply voltage V out decreases as the load current of the power supply increases.
  • V min ⁇ V out ⁇ V, V min is the lowest power supply voltage for normal operation when the load current increases in the next period of time when the main frequency is running.
  • V min refers to the lowest power supply voltage provided by the power supply to the processor when the load current increases to the maximum value, and the lowest power supply voltage can allow the processor to operate normally.
  • the above method further includes: when the processor determines that the main frequency of the next time period is not equal to the current main frequency, setting the current main frequency to be equal to the main frequency of the next time period.
  • the processor frequency is essentially the product of the FSB and the multiplier.
  • the FSB of a CPU is 100MHz
  • the multiplier is 8.5
  • the way to adjust the processor's main frequency should also be determined in conjunction with the model of the processor.
  • the processor is an Intel CPU
  • AMD Advanced Micro Devices, Inc.
  • AMD can modify the multiplier, but modifying the multiplier does not improve the performance of the CPU as well as the external frequency.
  • the PLL inside the processor is used to adjust the clock multiplication, so that the current main frequency of the processor is equal to the main frequency of the next time period determined by the processor core.
  • setting the current main frequency to be equal to the main frequency of the next time period includes:
  • Step 100a The processor determines that the main frequency of the next time period is less than the current main frequency, sets the current main frequency to be equal to the main frequency of the next time period, and executes step 101.
  • Step 100b The processor determines that the main frequency of the next time period is greater than the current main frequency, and executes step 101.
  • Step 104 the processor sets the current main frequency to be equal to the main frequency of the next time period.
  • the main frequency of the next period refers to the main frequency predicted according to the current main frequency
  • the power supply is based on the set supply voltage V of the main frequency of the next period and the set voltage slope of the main frequency of the next period.
  • the supply voltage V out provided by R to the processor is adapted to the main frequency of the processor in the next time period.
  • the load current has the characteristics of periodically increasing from the minimum load current to the maximum load current, when the power supply in the prior art outputs the load terminal voltage in a constant voltage mode, the load terminal voltage is increased during the increase of the load current. Passively drop.
  • the method provided by the embodiment of the present application actively controls the power supply voltage V out output by the power supply to decrease with the increase of the load current, so that when the load current starts to increase, the power supply voltage V out output by the power supply actively increases with the increase of the load current. decline.
  • the supply voltage V out is less than the set supply voltage V of the main frequency of the processor in the next period and greater than or equal to the maximum load current.
  • the load current increases, the normal operation The lowest supply voltage V min .
  • the power supply voltage V out provided by the power supply in the method provided in the embodiments of the present application can ensure that the processor is running normally, reducing the power consumption of the processor, and thereby improving the performance of the processor. Moreover, because the higher the processor's main frequency, the higher the load of the processor. Therefore, the method provided by the embodiment of the present application can ensure that no matter how high or low the load of the processor is, the power supply can lower the load current when the load current increases. Power is supplied to the processor by setting the power supply voltage at the current main frequency to ensure that the processor has low power consumption while operating normally.
  • the method provided by the embodiment of the present application can ensure that the processor is running normally, not only can reduce the power consumption when the processor is lightly loaded, but also can reduce The power consumption when the processor is under heavy load, realizes the reduction of global power consumption, thereby reducing the degree of heat of the processor, and when the load of the processor is relatively high, the degree of heat of the processor is relatively low, so Turbo is used
  • the technology can further increase the main frequency and alleviate the application limitation problem caused by the high degree of processor heat generated by the Turbo technology.
  • the power supply voltage output by the VRM power supply has the characteristic of linearly decreasing with the increase of the load current of the load line.
  • the above-mentioned power supply voltage V out VI*R
  • I is the load current of the power supply
  • the method of the embodiment of the present application is based on the characteristic that the voltage slope decreases with the increase of the load current.
  • the power supply voltage determined by the technology is fine-tuned, so as to achieve a global power consumption reduction.
  • the above-mentioned power supply voltage V out is determined by the set voltage slope R of the processor in the next period, the set power supply voltage V and the load current I in the next period. Since the voltage slope refers to the decreasing speed of the supply voltage as the load current of the power supply increases, the product of the set voltage slope R and the load current I of the main frequency in the next period is essentially: when the load current of the power supply increases, the supply voltage As long as it is ensured that the active drop is greater than or equal to the passive maximum drop of the load terminal voltage under the condition of the load current increase in the prior art, the power supply voltage V out can always be greater than or equal to when the processor is running in the next period. , In the case of increased load current, the lowest supply voltage V min for normal operation.
  • the power supply includes VRM chip, logic control circuit and buck converter.
  • the VRM chip can determine the reference voltage according to the set supply voltage V of the main frequency in the next time period, and determine the voltage slope of the reference voltage according to the set voltage slope R of the main frequency in the next time period.
  • the VRM chip transmits the reference voltage and the voltage slope of the reference voltage to the logic control circuit.
  • the logic control circuit outputs a variable voltage according to the reference voltage and the voltage slope of the reference voltage, and changes the voltage through a Buck converter to output a supply voltage V out that meets the operating requirements of the processor.
  • Figure 6 shows a schematic diagram of the power load transient process.
  • Figure 7 shows a schematic diagram of the power loadline characteristics.
  • V min in Figure 6 is the lowest power supply voltage of the processor.
  • I max is the maximum value of the load current. The following analyzes the principle of the power supply voltage guaranteeing the normal operation of the processor at a lower voltage in the method of this application in conjunction with FIG. 6 and FIG. 7.
  • the power supply provides a supply voltage to the processor in the form of a DC voltage, and the supply voltage does not decrease, that is, the supply voltage V 0 does not change with the load current.
  • the curve a in Fig. 7 is the transient curve of the load current.
  • the power supply voltage provided by the power supply will passively drop due to insufficient capacitance at the output of the buck converter. The drop process lasts from several ⁇ s to tens of ⁇ s. Then gradually return to DC voltage.
  • the oblique line b in Figure 6 when the Loadline value>0, it means that the DC voltage is actively linearly adjusted when the load current increases, and the voltage drop slope is equal to the Loadline value.
  • the c in Fig. 7 is the transient response curve of the power supply voltage when the Loadline value>0. As shown by the curve c in Fig. 7, under the impact of the load current, the power supply actively controls the supply voltage drop. As long as the supply voltage drop ⁇ V is not less than the passive maximum drop voltage ⁇ V max of curve b, the normal operation of the processor can be guaranteed. It can be seen that the method provided in the embodiment of the present application can ensure the normal operation of the processor. If the supply voltage drop ⁇ V is less than the passive maximum drop voltage of curve b, the processor cannot work normally.
  • DVFS technology is a dynamic voltage and frequency adjustment technology that can reduce power consumption to a certain extent. It can reduce the power consumption by reducing the operating voltage and operating frequency of the chip.
  • the formula for calculating the power consumption of the chip is Is the dynamic power consumption of the chip, V cc ⁇ I LEAK is the static power consumption of the chip, V cc is the working voltage of the chip, f is the working frequency of the chip, I LEAK is the leakage current of the chip, and ⁇ is the circuit at the current working frequency of the chip
  • the average turnover rate of, C is the capacitance value of the load capacitor. It should be understood that the power consumption calculation formula of the chip is also applicable to processors or integrated circuits with information processing functions.
  • the dynamic power consumption of the chip has a quadratic relationship with the operating voltage V cc of the chip, and the dynamic power consumption has a linear relationship with the operating frequency f of the chip, and when the operating voltage of the chip The higher the V cc and the operating frequency f of the chip, the higher the dynamic power consumption of the chip. Therefore, the DVFS technology can reduce the power consumption by reducing the power supply voltage and operating frequency of the chip.
  • FIG. 8 shows a schematic diagram of the mechanism of DVFS technology to reduce power consumption.
  • Timing a in FIG. 8 is a voltage timing diagram; timing b in FIG. 8 is a main frequency timing diagram.
  • FIG. 8 when the processor's load is light, the processor's main frequency and power supply voltage are relatively low. When the processor is under heavy load, the processor's main frequency and power supply voltage are relatively high and at the rated value.
  • Figure 9 shows a comparison diagram of the method of the present application, DVFS technology, and fixed voltage method for power supply.
  • the horizontal axis is the load current (can be regarded as the maximum load current)
  • the vertical axis is the supply voltage.
  • the straight line a in Fig. 9 is a graph of voltage changes when the fixed voltage method is used for power supply. It can be seen from the straight line a that no matter how the main frequency of the processor changes, the power supply voltage of the processor is a fixed rated power supply voltage.
  • the broken line b in Fig. 9 is a graph of voltage changes when a single DVFS is used for power supply.
  • the broken line b From the broken line b, it can be seen that in the low power mode, the main frequency of the CPU is F1, and the power supply voltage of the CPU is V11; in the rated mode, the main frequency of the CPU is F2, and the power supply voltage of the CPU is V12; In the first overclocking mode, the main frequency of the CPU is F3, and the power supply voltage of the CPU is V13; in the second overclocking mode, the main frequency of the CPU is F4, and the power supply voltage of the CPU is the power supply voltage V14.
  • the broken line c in FIG. 9 is a graph of the voltage change of the power supply using the method of the present application.
  • the CPU's main frequency is F1, and the CPU's power supply voltage is V21; in the rated mode, the CPU's main frequency is F2, and the CPU's power supply voltage is V22; In the first overclocking mode, the main frequency of the CPU is F3, and the power supply voltage of the CPU is V23; in the second overclocking mode, the main frequency of the CPU is F4, and the power supply voltage of the CPU is V24. It should be understood that as the power consumption increases, the main frequency of the CPU also increases, therefore, F1 ⁇ F2 ⁇ F3 ⁇ F4.
  • the first shaded area P1 in FIG. 9 is the power consumption gain area of the DVFS technology compared with the fixed voltage method. It can be seen that when the CPU frequency is high, DVFS technology cannot reduce the power consumption of the CPU processor. It can be seen that the DVFS technology can reduce the power consumption when the processor load is relatively light, but the DVFS technology cannot reduce the power consumption when the processor load is relatively heavy.
  • V21 ⁇ V22 ⁇ V23 ⁇ V24 When using the method of the embodiment of the application to supply power, V21 ⁇ V22 ⁇ V23 ⁇ V24.
  • the power supply voltage of the CPU increases stepwise with the increase in the main frequency and power consumption, the power supply voltage in each power consumption mode is less than Power supply voltage using DVFS technology.
  • the second shaded area P2 in FIG. 9 is the power consumption gain area of the method of the embodiment of the application compared with the DVFS technology. It has been verified that compared with the DVFS technology, the method of the embodiment of the present application can ensure that the overall power consumption gain of the CPU is more than 10%.
  • the method of this application can further reduce the power consumption of the processor regardless of the main frequency. Therefore, compared with the DVFS technology, the method provided by the embodiments of this application can not only further reduce the power consumption of the processor, but also make the processing
  • the processor runs normally at the lowest power supply voltage in multiple power consumption modes such as low power mode, rated mode, and overclocking mode (first overclocking mode, second overclocking mode), realizing the overall power reduction of the processor, thereby reducing heavy load Under the circumstances, the degree of heat generated by the processor enables the processor to work at a higher main frequency or even overclock, which improves the performance of the processor.
  • the above-mentioned set power supply voltage V of the main frequency in the next period can be provided by the processor, and the set voltage slope R of the main frequency in the next period can exist in the power supply or be provided by the processor. .
  • the stored set voltage slope can be stored in the storage medium of the electronic device or in the storage of the power supply. In the medium.
  • the above-mentioned set voltage slope exists in the power supply in the form of a constant voltage slope.
  • the processor does not need to use the communication interface between the processor and the power supply to dynamically set the set voltage slope R of the main frequency in the next period of time in the power supply, thereby effectively reducing the communication delay and voltage regulation delay, and improving the voltage regulation speed.
  • the foregoing processor sending power supply adjustment information to the power supply according to the main frequency of the next time period includes:
  • Step 1011A The processor searches for the set supply voltage V of the main frequency of the next time period from the target correspondence relationship according to the main frequency of the next time period.
  • Step 1012A The processor sends the set supply voltage V of the main frequency for the next period to the power supply.
  • the processor finds the set supply voltage of the main frequency for the next period of time according to the main frequency of the next period of time from the target corresponding relationship, it is sent to the power supply through the PMBus interface of the processor, and the PMBus interface of the power supply receives the setting of the main frequency for the next period of time. Set the supply voltage.
  • the foregoing target correspondence relationship may be the correspondence relationship between the processor's main frequency, the set supply voltage, and the voltage slope.
  • the target correspondence relationship may also be the correspondence relationship between the main frequency of the processor and the set supply voltage determined by the DVFS technology.
  • the above-mentioned power supply saves the set voltage slope R of the main frequency for the next period in the form of a constant voltage slope.
  • the constant voltage slope is the minimum value R min of the allowable voltage slope of the set supply voltage of the processor at each main frequency, R min >0. Since R min >0, it can be ensured that when the processor is working at any load or main frequency, the power supply can always provide a power supply voltage to the processor in a manner that is less than or equal to the set power supply voltage, so that the processor has lower energy consumption.
  • the constant voltage slope is the set voltage slope R of the main frequency for the next period
  • the product of the main frequency set voltage slope and the load current for the next period can be controlled, so that the processor runs normally and avoids the constant voltage slope from taking a comparatively high value.
  • the processor cannot operate normally at the power supply voltage V out when the load current increases.
  • the processor sending power supply adjustment information to the power supply according to the main frequency of the next time period includes:
  • Step 1011B The processor searches for the set supply voltage V of the main frequency of the next period and the set voltage slope R of the main frequency of the next period from the target correspondence relationship according to the main frequency of the next period.
  • Step 1012B The processor sends the set supply voltage V of the main frequency for the next time period and the set voltage slope R of the main frequency for the next time period to the power supply.
  • the processor finds the set supply voltage of the main frequency of the next period and the set voltage slope of the main frequency of the next period from the target correspondence relationship according to the main frequency of the next period, it is sent to the power supply through the PMBus interface of the processor.
  • the PMBus interface receives the set supply voltage of the main frequency in the next period and the set voltage slope of the main frequency in the next period.
  • the processor sends the set power supply voltage of the main frequency of the next period to the power supply in the form of VID encoding, and uses 8-16bit data as the set voltage slope of the next period of time, and sets the main frequency of the next period of time to the power supply.
  • the set supply voltage and the set voltage slope for the next period are sent to the power supply.
  • VID encoding the VID encoding used in DVFS technology can be directly used for transmission.
  • the set voltage slope for the next time period can be obtained.
  • the VRM chip can determine the power supply voltage V for the main frequency of the next period and the main frequency of the next period according to the VID code and 8-16bit data Voltage slope R.
  • the set supply voltage V of the main frequency in the next period is used as the reference voltage
  • the set voltage slope R of the main frequency in the next period is used as the voltage slope of the reference voltage.
  • the VRM chip sends the reference voltage and the voltage slope of the reference voltage to the logic control circuit.
  • the logic control circuit adjusts the voltage according to the voltage slope of the reference voltage and the reference voltage, and performs voltage conversion through a buck converter to obtain the supply voltage V out , and then use the power supply
  • the power interface of the power supply provides power to the processor.
  • the above-mentioned target correspondence is the correspondence between the processor's main frequency, the set supply voltage, and the set voltage slope.
  • the set voltage slopes of all the main frequencies can be completely unequal, and can also be partially equal or all equal.
  • the set voltage slope of the above-mentioned processor at each main frequency is the allowable voltage slope of the set supply voltage of the processor at each main frequency.
  • the set voltage slope of each main frequency in the above-mentioned target correspondence relationship is the allowable voltage slope of the set supply voltage of each main frequency of the processor.
  • the power supply voltage V out determined by the power supply can ensure that the power consumption of the processor is optimized when it meets the normal operation of the processor.
  • Table 1 shows the target correspondence relationship of the CPU when the set voltage slopes of part of the main frequency are equal. It should be understood that the power consumption modes shown in Table 1 are only examples, and in actual applications, there may be other various power consumption modes.
  • the CPU sets the reference voltage in the power supply to 1.0V through communication interfaces such as PMBus, and the voltage slope of the reference voltage is 0.1mohm.
  • the set supply voltage V of the main frequency of the next time period that the CPU searches for is 1.2V
  • the set operating voltage slope R of the main frequency of the next time period is 0.2mOhm.
  • the CPU sets the reference voltage in the power supply to 1.2V through communication interfaces such as PMBus, and the voltage slope of the reference voltage is 0.2mOhm.
  • the set voltage slope of the processor at all main frequencies is equal to the constant voltage slope.
  • the set voltage slopes corresponding to all the main frequencies in the target correspondence relationship are equal to the constant voltage slopes.
  • the constant voltage slope is suitable for power supply voltage regulation of various main frequencies, and it is the minimum value R min of the allowable voltage slope of the set power supply voltage of the processor at each main frequency, R min >0.
  • R min 0.1mOhm selected from Table 1.
  • the set voltage slope in Table 2 can be stored in the register of the power supply of the electronic device in advance.
  • the power supply adjustment information provided by the processor may only contain the set power supply voltage V of the main frequency of the next time period.
  • the processor provides the power supply with the set supply voltage V for the main frequency of the next period and the set voltage slope of the main frequency for the next period for the first time.
  • the power supply can save the set voltage slope R of the main frequency of the next period in the storage medium of the electronic device or the register of the power supply in the form of a constant voltage slope. For example: statically configure the set voltage slope R of the main frequency of the next period into the register at one time. Since the set voltage slopes of all the main frequencies in the target correspondence are equal to the constant voltage slope, the power supply essentially saves the set voltage slopes of all the main frequencies in the target correspondence in the form of a constant voltage slope.
  • the processor only needs to dynamically set the internal reference voltage of the power supply through the communication interface, thereby reducing the communication delay and the voltage adjustment delay, making the adjustment
  • the pressing time is shortened.
  • the set supply voltage of the main frequency of the next period determined by the CPU is 1.1V, and the next The set operating voltage slope R of the period main frequency is 0.1mOhm.
  • the CPU sets the reference voltage in the power supply to 1.0V through communication interfaces such as PMBus, and the voltage slope of the reference voltage is 0.1mohm.
  • the CPU only needs to query the set power supply of the main frequency for the next period from the target correspondence shown in Table 2 according to the main frequency of the next period.
  • the voltage V is 1.1V
  • the reference voltage in the power supply is set to 1.1V through a communication interface such as PMBus, and the power supply provides a power supply voltage V out to the processor according to the set voltage slope of 0.1mohm and the reference voltage of 1.1V.
  • the CPU's main frequency for the next period is 2.5GHz
  • the set supply voltage V of the main frequency for the next period found by the CPU is 1.2V
  • the set operating voltage slope R of the main frequency in the next period is 0.1mOhm.
  • the CPU sets the reference voltage in the power supply to 1.2V through communication interfaces such as PMBus, and the voltage slope of the reference voltage is 0.1mohm.
  • the power supply saves the set voltage slope in Table 2 in the form of a constant voltage slope
  • the CPU only needs to determine the set power supply voltage V of the main frequency for the next period of time to be 1.2V, and set the power supply voltage through a communication interface such as PMBus.
  • the reference voltage of is 1.2V
  • the power supply provides the power supply voltage V out to the processor according to the set voltage slope of 0.1mohm and the reference voltage of 1.2V.
  • the target correspondence relationship may not only be the target correspondence relationship shown in Table 1 and Table 2, but also Table 3 shows the corresponding relationship between the main frequency and the set supply voltage. It should be understood that the power consumption modes shown in Table 3 are only examples, and in actual applications, there may be other various power consumption modes.
  • the corresponding relationship between the main frequency and the set power supply voltage shown in Table 3 can directly refer to the corresponding relationship between the main frequency and the set power supply voltage of the processor used in the DVFS technology in the prior art. Of course, it can also be rebuilt by the user himself.
  • the storage medium includes but is not limited to the BIOS memory of the motherboard or the built-in memory of the processor.
  • the first storage method the target correspondence relationship is stored in the storage medium in the form of the correspondence relationship between the processor's main frequency frequency, the set supply voltage, and the set voltage slope or a correspondence relationship table.
  • the target correspondence essentially includes two sub-correspondences.
  • the two sub-correspondences include the corresponding relationship between the processor's main frequency and the set supply voltage, and the corresponding relationship between the processor's main frequency and the set voltage slope.
  • the two sub-correspondences include the correspondence between the set voltage slope and the set supply voltage, and the correspondence between the processor's main frequency and the processor's set supply voltage.
  • the two sub-correspondences include the correspondence between the set voltage slope and the set supply voltage, and the correspondence between the processor's main frequency and the processor's set voltage slope.
  • the foregoing target correspondence relationship may be stored in a storage medium before or after leaving the factory.
  • the target correspondence or the relationship table formed by the target correspondence are measured and stored in the storage medium. It should be understood that after the electronic device leaves the factory, the performance of the processor inside the electronic device is determined. Therefore, after the electronic device leaves the factory, the target correspondence obtained by directly debugging the electronic device is the target correspondence relationship of the processor in the electronic device where the storage medium is located. . At this time, the target correspondence relationship has the best adaptability to the processor included in the electronic device.
  • the target correspondence or the relationship table formed by the target correspondence is stored in the storage medium.
  • the target correspondence may not match the processor included in the electronic device.
  • the target correspondence stored in the storage medium before leaving the factory has wide applicability, so that different processors can use the same target correspondence.
  • the above target correspondence is the target correspondence of the benchmark processor.
  • the reference processor is the processor with the lowest power supply voltage and the largest multiple processors at the same main frequency.
  • the benchmark processor is the worst-performing processor among various processors. If you use the CPM circuit to measure multiple processors, you will find that when multiple processors work at the same main frequency, the CPM circuit corresponding to the reference processor has the longest delay time and the highest oscillation frequency.
  • the target correspondence of the reference processor may be applicable to any processor of a variety of processors. Therefore, when the target correspondence of the reference processor is taken as the target correspondence, the target correspondence has wide applicability.
  • the lowest power supply voltage for each type of processor operating at a given main frequency may determine the performance of the processor. For a processor or chip with good performance, the minimum power supply voltage operating at a given main frequency is relatively low, and for a processor or chip with poor performance, the minimum power supply voltage operating at a given main frequency is relatively high.
  • the performance difference of different processors is mainly introduced by the process or aging of the processors. For the same type of processor, different batches of processors may have differences.
  • the processor or chip with poor performance is defined as slow film, and the processor or chip with better performance is defined as slow film.
  • the difference between the extreme fast film and the extreme slow film All processors are divided into n processor gears.
  • a processor from each processor gear can be selected as the processor of the gear.
  • the reference processor should be calibrated. For example: using AVS technology to calibrate the reference processor. Specifically, as shown in FIG. 10, before the processor finds the set supply voltage of the main frequency of the next time period from the target correspondence relationship according to the main frequency of the next time period, the above method further includes:
  • Step 100c The processor calibrates the target correspondence relationship according to the performance difference information, so that the calibrated target correspondence relationship matches the processor included in the electronic device.
  • the performance difference information is determined by the CPM circuit.
  • the performance difference information may be a delay level such as a delay time or an oscillation frequency.
  • the performance difference information is the process performance difference information, the operating temperature performance difference information or the aging performance difference information. For example: the same batch of processors, due to process differences, the lowest power supply voltage at a given main frequency is different. Another example: under a given main frequency, the same processor has different minimum power supply voltages in different temperature ranges. Another example: under a given main frequency, the same processor has different minimum power supply voltages for different aging degrees.
  • the storage medium should also pre-store the correspondence relationship between a variety of processor performance differences that do not consider temperature differences and the lowest power supply voltage difference.
  • the correspondence between various processor performance differences and minimum power supply voltage differences is referred to as multiple processor difference correspondences in the following.
  • the performance difference of each type of processor can be expressed by the delay level (such as delay time) or oscillation frequency of the type of processor, or the type of processor and the reference processor.
  • the delay difference or the oscillation frequency difference under the same voltage is indirectly expressed.
  • the lowest power supply voltage difference corresponding to each processor performance difference refers to the lowest power supply voltage difference between the processor and the reference processor at the same main frequency.
  • the performance difference information detected by the CPM circuit and the processor calibrating the target correspondence relationship according to the performance difference information so that the target correspondence relationship matches the processor includes:
  • the processor finds the lowest power supply voltage difference from the various processor difference correspondences, and calibrates the set power supply voltage corresponding to each main frequency in the target correspondence according to the lowest power supply voltage difference, so that the calibrated target The corresponding relationship matches the processor included in the electronic device. Since the performance difference information can reflect the current state of the processor included in the electronic device (such as performance, aging degree, process deviation, use environment), etc., the processor finds the lowest value from the correspondence between multiple processor differences according to the performance difference information The power supply voltage difference can ensure that after the processor calibrates the set power supply voltage of each main frequency included in the target correspondence relationship according to the minimum power supply voltage difference, the target correspondence relationship is better matched with the processor included in the electronic device.
  • the storage medium should also pre-store the correspondence between the performance difference of multiple processors at multiple temperature gears and the minimum power supply voltage difference.
  • the corresponding relationship between the performance difference of various processors at multiple temperature gears and the difference of the lowest power supply voltage is referred to as the difference corresponding relationship of multiple processors at multiple temperature gears in the following.
  • the performance difference information detected by the CPM circuit and the processor calibrate the target correspondence relationship according to the performance difference information so that the target correspondence relationship matches the processor included in the electronic device includes:
  • the processor finds the correspondence between the performance difference of multiple processors at multiple temperature gears and the lowest power supply voltage difference from the correspondence between the performance differences of multiple processors at the current temperature and the lowest power supply voltage difference
  • the performance difference information find the minimum power supply voltage difference matched by the current performance difference information from the corresponding relationship between the performance difference of the various processors at the current temperature range and the minimum power supply voltage difference, and the minimum power supply matched according to the performance difference information
  • the voltage difference calibrates the set supply voltage corresponding to each main frequency in the target correspondence relationship, so that the calibrated target correspondence relationship matches the processor included in the electronic device, so as to consider the influence of the current temperature on the target correspondence relationship Come in, so as to further improve the matching between the target correspondence and the processor included in the electronic device.
  • the different correspondences of multiple processors in multiple temperature gears can be divided into multiple processor differences corresponding to n temperature gears according to operating temperature, and multiple processor differences corresponding to each temperature gear Including a variety of processor differences corresponding to the temperature range.
  • the target correspondences of multiple processors can also be divided into a variety of processor differences corresponding to n processor gears according to different processor gears; multiple processor differences corresponding to each processor gear
  • the relationship includes the difference correspondence between the processors of the processor gears in multiple temperature gears.
  • the performance difference information measured by the built-in CPM circuit of the processor will be different. If the effect of temperature on the performance difference information is not considered, the accuracy of the minimum power supply voltage difference found is not very high.
  • the storage medium stores the difference correspondence between multiple processors measured at 25°C and the target correspondence relationship of the benchmark processor
  • the built-in CPM circuit of the processor measures the performance difference information at 45°C
  • the deviation of the lowest power supply voltage difference found from the difference correspondence relationship measured by various processors at 25°C is relatively large.
  • the accuracy of the minimum power supply voltage difference found is relatively high.
  • the storage medium stores the differential correspondences of multiple processors at multiple temperature levels (including 45°C) and the target correspondences of the benchmark processor
  • the built-in CPM circuit of the processor Measure the performance difference information at 45°C, so that compared to the solution that does not consider the influence of temperature on the performance difference information, the performance difference information measured at 45°C can be found from a variety of processors at multiple temperature levels (including 45°C) The deviation of the minimum supply voltage difference is relatively small.
  • the found minimum power supply voltage difference essentially includes the processor operating at multiple main frequencies.
  • the minimum power supply voltage difference between these main frequencies and the main frequencies included in the target correspondence relationship are one-to-one correspondence.
  • the set power supply voltages of the multiple primary frequencies in the target correspondence relationship are calibrated according to the difference of the lowest power supply voltages of the multiple primary frequencies of the processor.
  • the minimum power supply voltage difference found essentially includes the minimum power supply voltage difference of the processor at a certain main frequency.
  • the voltage difference calibrates the set supply voltage of all main frequencies in the target correspondence. Refer to the description of whether to consider the main frequency in the following related to the calibration of the target correspondence.
  • the method for the processor to calibrate the target correspondence relationship according to the performance difference information is defined as a table look-up method.
  • the specific process of the look-up table method is explained in the case of the processor built-in CPM circuit.
  • the first step is to test the target correspondence table of the benchmark processor with the benchmark processor as the test object before leaving the factory.
  • the target correspondence of the reference processor is stored in the storage medium.
  • the second step before leaving the factory, divide the operating temperature range into multiple temperature gears, select a temperature from each temperature gear, and determine the difference correspondence table of the various processors in the corresponding temperature gears. And save the target correspondence relationship of multiple temperature gears in the storage medium.
  • the operating temperature range is 0°C ⁇ 100°C.
  • the first processor ⁇ X1 ⁇ v1
  • the second processor ⁇ X2 ⁇ v2
  • the third processor ⁇ X3 ⁇ v3
  • ⁇ X1 is the delay difference between the built-in CPM circuit of the first type of processor and the reference processor
  • ⁇ X 2 is the delay difference between the built-in CPM circuit of the second type of processor and the reference processor
  • ⁇ X3 is the difference between the third type of processor and the reference
  • ⁇ v1 is the minimum supply voltage difference between the first type of processor and the reference processor.
  • ⁇ v2 is the lowest power supply voltage difference between the second type of processor and the reference processor
  • ⁇ v3 is the lowest power supply voltage difference between the third type of processor and the reference processor.
  • Step 3 After leaving the factory, when the electronic device is in use, the CPM circuit measures the current delay time, and the processor searches for multiple processors from the table of differences between multiple processors in multiple temperature gears according to the current temperature. Correspondence table of the difference in the temperature range where the current temperature is located. Determine the current delay difference according to the current delay time measured by the CPM circuit built into the processor and the current delay time measured by the CPM circuit built into the reference processor.
  • the minimum power supply voltage difference corresponding to the delay time is calibrated for the set power supply voltage of each main frequency in the target correspondence relationship of the reference processor according to the searched minimum power supply voltage difference.
  • the current operating temperature is 45°C
  • the delay time measured by the CPM circuit at 45°C according to the delay time measured by the built-in CPM circuit of the processor at 45°C and the delay time of the built-in CPM circuit of the reference processor at 50°C Time to obtain the current delay difference.
  • the temperature range of 45°C is 41°C ⁇ 60°C
  • the current delay difference find out from Table 4 that it is close to the current delay difference (the proximity of the delay difference can be set according to the actual situation) or The same delay difference, and then find the lowest power supply voltage difference from Table 4 according to the found delay difference. If the set power supply voltage of a certain main frequency in the target correspondence of the reference processor is V, and the determined minimum power supply voltage difference is ⁇ v3, the calibrated set power supply voltage is equal to V+ ⁇ v3.
  • the method for the processor to calibrate the target correspondence according to the performance difference information is defined as a mathematical deduction method.
  • the specific process of the mathematical deduction method is explained in the case of the processor built-in CPM circuit.
  • the first step is to test the target correspondence table of the benchmark processor with the benchmark processor as the test object before leaving the factory.
  • the target correspondence of the reference processor is stored in the storage medium.
  • the second step before leaving the factory, divide the operating temperature range into multiple temperature ranges, select a temperature from each temperature range, determine the delay difference of the various processors at that temperature and the minimum power supply voltage difference, and compare them Fitting is performed to determine the functional relationship between the delay difference of various processors and the difference of the lowest power supply voltage at this temperature.
  • the operating temperature range is 0°C ⁇ 100°C.
  • the five mathematical function equations correspond to the mathematical function relationship equations of the five temperature gears.
  • the third step after leaving the factory, when the electronic device is in use, the CPM circuit measures the current delay time, and the processor selects the mathematical function relationship according to the current temperature range, and according to the current delay time of the built-in CPM circuit of the processor Time and the delay time of the CPM circuit built in the reference processor at the current temperature, obtain the current delay difference, and substitute the current delay difference into the selected mathematical function relationship to calculate the minimum power supply voltage difference, and then according to the minimum The power supply voltage difference calibrates the target correspondence of the reference processor.
  • the current operating temperature is 45°C
  • the CPM circuit built in the CPM circuit measures the current delay time at 45°C
  • the current delay time measured at 45°C by the CPM circuit built in the processor is compared with the CPM built in the reference processor.
  • the circuit obtains the current delay difference at a delay time of 45°C, and substitutes the current delay difference into the mathematical function relationship of the temperature range at 50°C fitted by 50°C to obtain the minimum power supply voltage difference. If the set power supply voltage of a certain main frequency in the target correspondence of the reference processor is V, and the determined minimum power supply voltage difference is ⁇ v3, the calibrated set power supply voltage is equal to V+ ⁇ v3.
  • the determined correspondences of various processor differences can be regarded as the correspondences of multiple processor differences under one temperature gear, but the difference is only for the temperature gear.
  • the range is relatively wide.
  • the operating temperature of 0°C ⁇ 100°C is divided into five temperature ranges, which are 0°C ⁇ 20°C, 21°C ⁇ 40°C, 41°C ⁇ 60°C, 61°C ⁇ 80 °C, 81°C ⁇ 100°C. If the temperature effect is neglected, it can be considered that the various processor difference corresponding relationships are the various processor difference corresponding relationships measured at a temperature range of 0°C to 100°C.
  • the storage medium stores the target correspondences of the aforementioned reference processors in multiple temperature gears or the target correspondences of multiple processors.
  • the aforementioned method also include:
  • Step 100d The processor searches for the target correspondence from the target correspondence of the reference processor in the multiple temperature gears according to the current temperature.
  • the target correspondence is the target correspondence of the reference processor in the temperature range where the current temperature is located.
  • the determined target correspondence of the reference processor takes into account the influence of temperature on the target correspondence, so that the calibrated target correspondence has a better match with the processor included in the electronic device.
  • the operating temperature range of the reference processor is 0°C to 100°C. Divide 0°C ⁇ 100°C into five temperature ranges: 0°C ⁇ 20°C, 21°C ⁇ 40°C, 41°C ⁇ 60°C, 61°C ⁇ 80°C, 81°C ⁇ 100°C at 20°C intervals, starting from 0°C Select 15°C from -20°C, select 28°C from 21°C to 40°C, select 50°C from 41°C to 60°C, select 75°C from 61°C to 80°C, and select 90°C from 81°C to 100°C °C. Then test the target correspondences of the benchmark processor at 15°C, 28°C, 50°C, 75°C, and 90°C, and obtain the target correspondences of the processor at the five temperature levels.
  • the delay time and minimum power supply voltage of the CPM circuits built in various processors and benchmark processors at 15°C, 28°C, 50°C, 75°C, and 90°C. According to the difference between the delay time of the built-in CPM circuit of multiple processors and the reference processor and the difference of the lowest power supply voltage, the difference correspondences of multiple processors at 15°C, 28°C, 50°C, 75°C and 90°C are obtained.
  • the relationship table that is, the difference correspondence between multiple processors at multiple temperature levels.
  • Step 3 After leaving the factory, when the electronic device is in use, the current operating temperature is 45°C, and the processor finds that the reference processor is at 45°C from the target correspondence table of the reference processor in the five temperature ranges according to the current temperature.
  • the target corresponding relationship of the temperature range that is, the target corresponding relationship of various processors at 50°C.
  • the processor obtains the current delay difference according to the delay time measured by the built-in CPM circuit of the processor at 45°C and the delay time of the reference processor built-in CPM circuit at 45°C, and then finds the difference between the current delay time and the current delay time from Table 4. When the time difference is close to or the same as the delay difference, look up the lowest power supply voltage difference from Table 4 according to the found delay difference. If the set supply voltage of a main frequency in the detected target correspondence relationship is V, and the determined minimum supply voltage difference is ⁇ v3, then the set supply voltage after calibration is equal to V+ ⁇ v3.
  • the electronic device When the target correspondence relationship of multiple processors is stored in the storage medium, the electronic device is powered on, and the CPM circuit detects the performance difference information without considering the influence of temperature.
  • the above method further includes:
  • Step 100e The processor searches for a target correspondence that matches the processor included in the electronic device from the target correspondences of multiple types of processors according to the performance difference information.
  • each processor has a built-in CPM circuit.
  • the CPM circuit built in each processor can be used to determine the performance difference information such as the oscillation frequency or delay time of a variety of processors before leaving the factory, and establish The performance difference information of the multiple processors is linked to the target correspondence of the multiple processors.
  • the performance difference information of the multiple processors and the target correspondence relationship of the multiple processors are stored in the storage medium.
  • the performance difference information of each type of processor is the delay time of that type of processor.
  • the method further includes:
  • Step 100f According to the current temperature, the processor searches for the target correspondences of the various processors in the temperature range of the current temperature from the target correspondences of the various processors in the multiple temperature ranges; The target corresponding relationship of the temperature range where the current temperature is located is searched for a target corresponding relationship that matches the processor included in the electronic device.
  • the target correspondences of the above-mentioned various processors in the multiple temperature gears can be divided into n temperature gear target correspondences according to the operating temperature.
  • the target correspondence of each temperature gear includes the target correspondence of multiple processors in the temperature gear.
  • the target correspondences of multiple processors can also be divided into n processor gear target correspondences according to different processor gears.
  • the target correspondence of each processor gear includes the target correspondence of the processors of the same gear in n temperature gears. It should be understood that the target correspondence between processors of the same gear in n temperature gears refers to: selecting a processor from all processors in the processor gear as the test object, and testing that the processor is in n temperature gears The target correspondence of bits.
  • n 1
  • the target correspondences of multiple processors have only one temperature gear. At this time, it can be considered that the target correspondences of multiple processors without considering the temperature.
  • n is an integer greater than or equal to 2
  • the storage medium should also pre-store the performance difference information of the various processors at multiple temperature levels.
  • the performance difference information of multiple processors at multiple temperature gears should be interdependent with the target correspondences of multiple processors at multiple temperature gears, and then the multiple processors at multiple temperature gears. The performance difference information and the target correspondences of the various processors at the multiple temperature levels are stored in the storage medium.
  • the performance difference information of the various processors at the multiple temperature gears can be classified according to the temperature gears, and multiple types of performance difference information corresponding to the multiple temperature gears one-to-one can be obtained.
  • Each type of performance difference information includes performance difference information (such as delay time or oscillation frequency) of a variety of processors in the temperature range.
  • the performance difference information of multiple types of processors at multiple temperature gears can be classified according to the processor gears, and multiple types of performance difference information corresponding to the multiple processor gears one-to-one can be obtained.
  • Each type of performance difference information includes performance difference information (such as delay time or oscillation frequency) of the same gear processor at multiple temperature gears.
  • the operating temperature of the processor ranges from 0°C to 100°C. Divide 0°C ⁇ 100°C into five temperature ranges: 0°C ⁇ 20°C, 21°C ⁇ 40°C, 41°C ⁇ 60°C, 61°C ⁇ 80°C, 81°C ⁇ 100°C at 20°C intervals, starting from 0°C Select 15°C from -20°C, select 28°C from 21°C to 40°C, select 50°C from 41°C to 60°C, select 75°C from 61°C to 80°C, and select 90°C from 81°C to 100°C °C.
  • the CPM circuit built into the processor detects the current delay time at 45°C. Search for similar or the same delay time from the delay time of various processors at the temperature range of 45°C (that is, the delay time of various processors at 50°C), and determine the corresponding delay time according to the found delay time The target correspondence.
  • each target The set power supply voltage and the set voltage slope in the corresponding relationship are determined in the following manner, which can ensure that the power supply voltage V out provided by the power supply to the processor can reliably and stably reduce the power consumption of the processor.
  • the set power supply voltage in the above target correspondence can be determined according to the following relationship: the processor’s set power supply voltage for each main frequency is V (i) , that is, the set power supply voltage of each main frequency in the target correspondence is V ( i) .
  • V (i) V min(i) + ⁇ V (i)
  • V min(i) is the lowest supply voltage for normal operation of the processor when the load current increases when the processor is running at each main frequency
  • ⁇ V ( i) is the supply voltage margin of the processor at each main frequency.
  • ⁇ V (i) 20mV ⁇ 60mV. For example: 40mV or 50mV, of course it can also be set according to the actual situation.
  • the allowable voltage slope of the set supply voltage of the processor at each main frequency can be determined according to the following relationship: the allowable voltage slope of the set supply voltage of the processor at each main frequency is R (i) .
  • R (i) R max(i) - ⁇ R (i) .
  • R max (i) is the maximum voltage slope of the set supply voltage of the processor at each main frequency
  • ⁇ R (i) is the voltage slope margin of the processor at each main frequency.
  • ⁇ R (i) 0.03mOhm ⁇ 0.08mOhm. For example: 0.05mOhm or 0.07mOhm.
  • the setting of each main frequency should also be determined. Select the minimum value of the allowable voltage slope R (i) of the supply voltage and ensure that the minimum value is greater than zero. The minimum value is used as the set voltage slope that can be shared by multiple main frequencies, that is, the constant voltage slope described above.
  • the first step the process of generating the corresponding relationship between the processor's main frequency and the set supply voltage: Before the CPU leaves the factory, use the CPU evaluation board to measure the relationship between the CPU's main frequency and the minimum supply voltage. During the test, set the voltage slope of the power supply to 0Ohm, the test samples cover typical slices (typical slices are also called TT slices), process deviation slices (also called corner slices), and the test temperature covers the ambient temperature (ie operating temperature) declared by the CPU , Measure the main frequency and minimum supply voltage curve of a set of processors. The minimum power supply voltage should be able to guarantee the minimum power supply voltage that the processor can operate normally.
  • the supply voltage margin is added to the minimum supply voltage of each main frequency to obtain the set supply voltage of the processor's main frequency to prevent the supply voltage from being unable to ensure the normal operation of the processor when the load current increases.
  • the power supply voltage margin refers to the allowable voltage deviation value that allows the lowest supply voltage to deviate.
  • Figure 13 shows the processor's main frequency and supply voltage curve. The X axis is the main frequency, and the Y axis is the power supply voltage. Among them, the curve a in FIG. 13 is the main frequency and the lowest supply voltage curve of the processor, and the b in FIG. 13 is the main frequency and the set supply voltage curve of the processor. The minimum operating voltage included in the curve a in FIG. 13 is increased by a margin of 50 mV, and the curve b in FIG. 13 can be obtained.
  • the curve b in Fig. 13 covers the frequency and the set supply voltage in many typical modes such as the low power consumption mode, the rated mode, and the two overclocking modes.
  • Table 3 shown above shows the correspondence between the main frequency and the set supply voltage of the curve b in FIG. 13 in different modes. As shown in Table 3, when the CPU is working in low-power mode, the CPU frequency is lower at 0.5GHz, and the power supply voltage is set to 0.9V; when the CPU is working in the rated mode, the CPU frequency is 1.5GHz, and the CPU frequency is set to 1.5GHz.
  • the power supply voltage is 1.1V; when the CPU works in the first overclocking mode, the CPU main frequency exceeds the rated frequency, which is 2.5GHz, and the power supply voltage is set to 1.2V; when the CPU works in the second overclocking mode, the CPU main frequency is further increased to 3.0GHz, set the power supply voltage to 1.3V.
  • the corresponding relationship between the main frequency of the processor and the set power supply voltage of the method of the present application can also be formed based on the table of correspondence between the main frequency of the processor used in the existing DVFS technology and the set power supply voltage.
  • the second step is the process of generating the corresponding relationship between the processor's main frequency, set supply voltage, and set voltage slope: According to the settings of the CPU's main frequency and voltage in each mode, determine the maximum that can ensure the normal operation of the processor in each mode Voltage slope, and reserve a certain voltage slope margin.
  • the voltage slope margin refers to the allowable error of the maximum voltage slope.
  • Figure 14 shows the voltage slope diagram of the set supply voltage in the rated mode.
  • the oblique line a in FIG. 14 is a graph of the maximum voltage slope of the set supply voltage in the rated mode.
  • the processor When the processor is in the rated mode, set the supply voltage to 1.1V.
  • the control and set supply voltage When the load current rises, the control and set supply voltage will actively fall to the minimum value according to different voltage slopes, and the maximum voltage slope that guarantees the normal operation of the processor is selected from it, and a certain voltage slope margin is subtracted on this basis.
  • the set voltage slope cannot be too large, otherwise the processor will fail to work when the load current of the power supply increases.
  • the set voltage slope cannot be too small, otherwise the effect of reducing the power consumption of the processor will not be obvious.
  • the set voltage slope of each mode or each main frequency should be determined through repeated tests and cannot be set with a unified standard.
  • the determination process of the set voltage slope of the low power consumption mode, the first overclocking mode, and the second overclocking mode refer to the process of determining the set voltage slope of the rated mode.
  • Figure 15 shows the voltage loadline curves under different power consumption modes.
  • the X coordinate is the load current
  • the Y coordinate is the set power supply constant voltage.
  • the curve a in FIG. 15 is the voltage slope curve in the low power consumption mode
  • the curve b in FIG. 15 is the voltage slope curve in the rated mode
  • the curve c in FIG. 15 is the voltage slope curve in the first overclocking mode.
  • the curve d in FIG. 15 is the voltage slope curve of the second overclocking mode. According to the curve b in FIG. 13 and the curves a to d in FIG. 15, the target correspondence relationship shown in Table 1 can be determined.
  • the set voltage slopes corresponding to all main frequencies in the above-mentioned target correspondence relationship are equal to the constant voltage slopes
  • the second step the smallest set voltage slopes corresponding to all main frequencies should be found.
  • Set the voltage slope and ensure that the set voltage slope>0.
  • the set voltage slope is the voltage slope common to all main frequencies, that is, the constant voltage slope. For example: in the low power consumption mode, rated mode, first overclocking mode and second overclocking mode in Table 1, the minimum set voltage slope that is not equal to 0 is 0.1V. Therefore, 0.1V is used as the low power consumption mode and rated The set voltage slope shared by the mode, the first overclocking mode and the second overclocking mode.
  • each network element such as a processor and a power supply
  • each network element includes a hardware structure and/or software module corresponding to each function.
  • the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed by hardware or computer software-driven hardware depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered as going beyond the scope of the embodiments of the present application.
  • FIG. 16 shows a device provided in an embodiment of the present application.
  • the equipment is used in communication equipment or terminal equipment, but is not limited to this.
  • the device 200 includes a processor 201 and a power supply 202.
  • the processor 201 is configured to support the electronic device to execute step 101 executed by the processor in the above-mentioned embodiment.
  • the power supply 202 is used to support the electronic device to perform step 102 and step 103 performed by the power supply in the foregoing embodiment.
  • the above-mentioned processor 201 is further configured to execute step 100 executed by the processor in the above-mentioned embodiment.
  • the above-mentioned processor 201 is further configured to support the electronic device to execute step 100a executed by the processor in the above-mentioned embodiment.
  • the above-mentioned processor 201 is also used to support the electronic device to execute step 100b and step 104 executed by the processor in the above-mentioned embodiment.
  • the above-mentioned device 200 further includes a storage medium 203 for storing the correspondence between the computer program and the target.
  • the above-mentioned power supply 202 stores the set voltage slope in the form of a constant voltage slope.
  • the foregoing processor 201 is specifically configured to execute steps 1011A and 1012A executed by the processor in the foregoing embodiment.
  • the above-mentioned device 200 further includes a storage medium 203 for storing the correspondence between the computer program and the target.
  • the foregoing processor 201 is specifically configured to execute steps 1011B and 1012B executed by the processor in the foregoing embodiment.
  • the device 200 further includes a storage medium 203 for storing the target correspondence between the computer program and the reference processor, and the processor 201 is also used to support the electronic device to execute such as Step 100c executed by the processor in the above embodiment.
  • the storage medium 203 is also used to store a variety of different processor correspondences, or a variety of different processor correspondences at multiple temperature levels.
  • the above-mentioned device 200 further includes a storage medium 203 for storing the target correspondence between the computer program and the reference processor at multiple temperature levels, and the above-mentioned processor 201 also It is used to support the electronic device to execute step 100d executed by the processor in the above-mentioned embodiment.
  • the storage medium 203 is also used to store the differential correspondences of various processors at multiple temperature levels.
  • the above-mentioned device 200 further includes a storage medium 203, which is used to store the target correspondence between the computer program and various processors, and the above-mentioned processor 201 is also used to support electronic devices.
  • Step 100e executed by the processor in the above-mentioned embodiment is executed.
  • the storage medium 203 is also used to store various types of processor performance difference information.
  • the above-mentioned device 200 further includes a storage medium 203, which is used to store the computer program and the target correspondence between the various processors at multiple temperature levels, and the above-mentioned processor 201 It is also used to support the electronic device to execute step 100f executed by the processor in the above-mentioned embodiment.
  • the storage medium 203 is also used to store performance difference information of various processors at multiple temperature levels.
  • the embodiment of the present application may divide the processor and the power supply into functional modules according to the foregoing method examples.
  • each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module.
  • the above-mentioned integrated modules can be implemented in the form of hardware or software functional modules. It should be noted that the division of modules in the embodiments of the present application is illustrative, and is only a logical function division, and there may be other division methods in actual implementation.
  • FIG. 17 shows a schematic structural diagram of a voltage adjusting device involved in the above-mentioned embodiment.
  • the voltage regulating device is a processor or a chip applied to the processor.
  • the voltage adjusting device 300 includes a sending module 303, which is used to support the voltage adjusting device to execute step 101 executed by the processor in the foregoing embodiment.
  • the above-mentioned voltage adjusting device 300 further includes: a prediction module 301, which is used to support the voltage adjusting device to execute step 100 executed by the processor in the above-mentioned embodiment.
  • the above-mentioned voltage adjustment device 300 further includes a frequency synthesis module 304, which is used to support the voltage adjustment device to perform step 100a, or step 100b and step 100b and Step 104.
  • the above-mentioned voltage adjustment device 300 further includes a selection module 302 and a storage module 305.
  • the storage module 305 is used to store the target correspondence.
  • the aforementioned selection module 302 is also used to support the voltage adjustment device to execute step 1011A executed by the processor in the aforementioned embodiment, and the aforementioned sending module 303 is further used to support the voltage adjustment device to execute step 1012A executed by the processor in the aforementioned embodiment.
  • the above-mentioned voltage adjustment device 300 further includes a selection module 302 and a storage module 305.
  • the storage module 305 is used to store the target correspondence.
  • the aforementioned selection module 302 is also used to support the voltage adjustment device to execute step 1011B executed by the processor in the aforementioned embodiment
  • the aforementioned sending module 303 is also used to support the voltage adjustment device to execute step 1012B executed by the processor in the aforementioned embodiment.
  • the above-mentioned voltage adjustment device 400 further includes a relationship correction module 306.
  • the storage module 305 is used to store the target correspondence of the reference processor.
  • the relationship correction module 306 is configured to support the voltage adjustment device to execute step 100c executed by the processor in the above-mentioned embodiment.
  • the storage module 305 is also used to store a variety of different processor correspondences, or a variety of different processor correspondences at multiple temperature levels.
  • the storage module 305 is configured to store the target correspondences of the reference processor at multiple temperature gears and the difference correspondences of the multiple processors at multiple temperature gears. relationship.
  • the relationship correction module 306 is configured to support the voltage adjustment device to execute step 100d executed by the processor in the foregoing embodiment.
  • the storage module 305 is configured to store target correspondences of multiple types of processors and multiple types of processor performance difference information.
  • the relationship correction module 306 is configured to support the voltage adjustment device to execute step 100e executed by the processor in the foregoing embodiment.
  • the storage module 305 is configured to store target correspondences of multiple processors and performance difference information of multiple processors at multiple temperature levels.
  • the relationship correction module 306 is configured to support the voltage adjustment device to execute step 100f executed by the processor in the foregoing embodiment.
  • FIG. 18 shows a schematic structural diagram of another voltage adjusting device involved in the above-mentioned embodiment.
  • the voltage regulating device is a power supply or a chip applied to the power supply.
  • the voltage regulation device includes a receiving module 401 and a power supply module 402.
  • the receiving module 401 is used to support the voltage regulation device to execute step 102 executed by the power supply in the above-mentioned embodiment.
  • the power supply module 402 is used to support the voltage regulation device to execute step 103 executed by the power supply in the above-mentioned embodiment.
  • the voltage adjustment device 400 when the voltage adjustment information includes the set supply voltage V of the main frequency of the next time period and the set voltage slope R of the next time period, the voltage adjustment device 400 further includes The voltage identification module 404 and the slope identification single module 405.
  • the voltage identification module 404 is used to support the voltage regulation device to execute the set supply voltage V of the main frequency of the next time period identified by the power supply in the above-mentioned embodiment, thereby determining the reference voltage.
  • the slope recognition unit 405 is used to support the voltage regulation device to execute the set voltage slope R for the next period of time performed by the power supply in the foregoing embodiment, so as to determine the voltage slope of the reference voltage.
  • the above-mentioned voltage adjusting device 400 further includes a storage medium 403, and the storage medium 403 is used to store the set voltage slope existing with a constant voltage slope.
  • the above-mentioned voltage regulation device 400 further includes a voltage identification module 404, which is used to support the voltage regulation device to execute the set supply voltage V of the main frequency of the next time period identified by the power supply in the above-mentioned embodiment, so as to determine the reference voltage.
  • FIG. 19 shows that an embodiment of the present application provides a voltage adjusting device.
  • the voltage adjusting device 500 may include: a communication unit 501.
  • the voltage adjustment device 500 may further include a processing unit 502.
  • the above-mentioned voltage adjusting device 500 is a processor, or a chip applied in a processor.
  • the processing unit 502 is configured to support the voltage regulation device to execute step 100 executed by the processor in the foregoing embodiment.
  • the communication unit 501 is configured to support the voltage regulation device to execute step 101 by the processor in the foregoing embodiment.
  • the above-mentioned processing unit 502 is further configured to support the voltage adjusting device to execute step 100a or step 100b and step 104 executed by the processor in the above-mentioned embodiment.
  • the above-mentioned voltage adjustment device further includes a storage unit 503 for storing the target correspondence.
  • the above-mentioned processing unit 502 is further configured to support the voltage adjusting device to execute step 1011A executed by the processor in the above-mentioned embodiment.
  • the aforementioned communication unit 501 is further configured to support the voltage adjustment device to execute step 1012A executed by the processor in the aforementioned embodiment.
  • the above-mentioned voltage adjusting device 500 further includes a storage unit 503 for storing the target correspondence relationship.
  • the above-mentioned processing unit 502 is further configured to support the voltage regulating device to execute step 1011B executed by the processor in the above-mentioned embodiment
  • the above-mentioned communication unit 501 is also configured to support the voltage regulating device to execute step 1012B executed by the processor in the above-mentioned embodiment.
  • the storage unit 503 is configured to store the target correspondence of the reference processor.
  • the processing unit 502 is further configured to support the voltage regulation device to execute step 100c executed by the processor in the foregoing embodiment.
  • the storage unit 503 is also used to store a variety of different processor correspondences, or a variety of different processors at multiple temperature levels.
  • the storage unit 503 is configured to store target correspondences of the reference processor in multiple temperature gears.
  • the processing unit 502 is further configured to support the voltage adjustment device to execute step 100d executed by the processor in the above-mentioned embodiment.
  • the storage unit 503 is also used to store the differential correspondences of various processors at multiple temperature levels.
  • the storage unit 503 is configured to store target correspondences of various processors.
  • the processing unit 502 is further configured to support the voltage adjustment device to execute step 100e executed by the processor in the above-mentioned embodiment.
  • the storage unit 503 is also used to store various types of processor performance difference information.
  • the storage unit 503 is configured to store target correspondences of various processors at multiple temperature levels.
  • the processing unit 502 is further configured to support the voltage adjustment device to execute step 100f executed by the processor in the foregoing embodiment.
  • the storage unit 503 is also used to store performance difference information of various processors at multiple temperature levels.
  • the voltage regulating device 500 is a power supply, or a chip applied in a power supply.
  • the communication unit 501 is used to support the voltage regulation device to execute step 102 executed by the power supply in the above-mentioned embodiment.
  • the processing unit 502 is configured to support the voltage regulation device to execute step 103 executed by the power supply in the foregoing embodiment.
  • the above-mentioned voltage adjustment device 500 may further include a storage unit 503 for storing data such as a set voltage slope existing at a constant voltage slope and program codes executable by the voltage adjustment device. .
  • the processing unit 502 may be a processor or a controller, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (Digital Signal Processor, DSP), and an application-specific integrated circuit (Application-Specific Integrated Circuit). Integrated Circuit, ASIC), Field Programmable Gate Array (FPGA) or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logical blocks, modules, and circuits described in conjunction with the disclosure of the present invention.
  • the processing unit may also be a combination of computing functions, for example, a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and so on.
  • the communication unit may be a transceiver, a transceiver circuit, or a communication interface.
  • the storage unit may be a memory.
  • the above communication unit may be a communication interface of the device for receiving signals from other devices.
  • the communication unit is a communication interface for the chip to receive signals or send signals from other chips or devices.
  • the processing unit 502 shown in FIG. 19 includes a VRM chip, a logic control circuit, and a Buck converter
  • the communication unit 501 includes a communication interface and a power interface
  • the storage unit 503 is a memory
  • the voltage regulation device involved in the embodiment of the present invention 500 may be the power supply shown in FIG. 2.
  • the processing unit 502 shown in FIG. 19 is a processor
  • the communication unit 501 is a communication interface
  • the storage unit 503 is a memory
  • the voltage adjustment apparatus 500 involved in the embodiment of the present invention may be the processor shown in FIG. 2.
  • FIG. 20 shows a schematic diagram of the structure of a chip.
  • the chip 600 includes one or more than two (including two) processors 601 and a communication interface 602.
  • the chip further includes a memory 603.
  • the memory 603 may include a read-only memory and a random access memory, and provides operation instructions and data to the processor 602.
  • a part of the memory 603 may also include a non-volatile random access memory (NVRAM).
  • NVRAM non-volatile random access memory
  • the memory 603 stores the following elements, execution modules or data structures, or their subsets, or their extended sets.
  • the processor 601 executes corresponding operations by calling the target correspondence stored in the memory 603.
  • the structure of the chip used by the processor and the power supply is similar, and different devices can use different chips to realize their respective functions.
  • the processor 601 controls the processing operations of any one of the processor and the power supply included in the electronic device in the embodiment of the present application.
  • the processor 601 may also be referred to as a central processing unit (CPU).
  • the memory 603 includes a read-only memory and a random access memory, and provides instructions and data to the processor 603.
  • a part of the memory 603 may also include NVRAM.
  • the memory, the communication interface 602, and the memory 603 are coupled together through a bus system 604, where the bus system 604 may include a power bus, a control bus, and a status signal bus in addition to a data bus.
  • various buses are marked as the bus system 604 in FIG. 20.
  • the communication interface 602 is used to support the above-mentioned chip to execute the steps of receiving and sending the processor and the power supply in the above-mentioned embodiment.
  • the processor 601 is used to support the above-mentioned chip to execute the processing steps of the processor and the power supply in the above-mentioned embodiment.
  • a computer-readable storage medium is provided, and instructions are stored in the computer-readable storage medium. When the instructions are executed, it realizes the operation of the processor as shown in any one of FIGS. 4, 5, and 10-12. Features.
  • a computer-readable storage medium is provided, and instructions are stored in the computer-readable storage medium.
  • the power supply as shown in any one of FIGS. 4, 5 and 10-12 is realized.
  • a computer program product including instructions.
  • the computer program product includes instructions. When the instructions are executed, the function of the processor shown in any one of FIGS. 4, 5, and 10-12 is realized.
  • a computer program product including instructions.
  • the computer program product includes instructions. When the instructions are executed, the function of the power supply as shown in any one of FIGS. 4, 5, and 10-12 is realized.
  • a chip is provided.
  • the chip is applied to a processor.
  • the chip includes at least one processor and a communication interface.
  • the communication interface is coupled to the at least one processor.
  • the function of the processor shown in any one of Figures 10-12.
  • a chip is provided.
  • the chip is applied to a power supply.
  • the chip includes at least one processor and a communication interface, and the communication interface is coupled to the at least one processor.
  • the function of the power supply shown in any one of Figures 10-12.
  • the disclosed system, device, and method may be implemented in other ways.
  • the device embodiments described above are merely illustrative, for example, the division of units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components can be combined or integrated. To another system, or some features can be ignored, or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.
  • the functional units in the various embodiments of the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.
  • the function is realized in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.
  • the technical solutions of the embodiments of the present application are essentially or the part that contributes to the prior art or the part of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium.
  • Including several instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods in the various embodiments of the present application.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disks or optical disks and other media that can store program codes. .

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Abstract

本申请公开了一种电压调节方法和电子设备，涉及电子技术领域，以保证处理器在负载轻和负载重的情况下均能够实现功耗降低和性能提升。该方法应用于具有处理器以及向处理器供电的电源的电子设备。该方法包括：该处理器根据下一时段主频向电源发送供电调节信息；电源根据供电调节信息确定用于向该处理器供电的供电电压V out。该供电电压V out随着电源的负载电流的增加减小。V min≤V out≤V，V min为处理器在下一时段主频的最低供电电压，V为处理器在下一时段主频的设定供电电压。

Description

一种电压调节方法和电子设备
本申请要求于2019年12月09日提交国家知识产权局、申请号为201911252945.1、申请名称为“一种电压调节方法和电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电子技术领域，特别涉及一种电压调节方法和电子设备。
背景技术
电路摩尔定律是一种揭示信息技术进步速度的定律，其内容为：当价格不变时，集成电路上可容纳的元器件的数目，约每隔18-24个月便会增加一倍，性能也将提升一倍。换言之，每一美元所能买到的电脑性能将每隔18-24个月翻一倍以上。
近年来，随着集成电路工作频率、集成度的不断提高，集成电路的功耗快速增加，使得集成电路难以继续适用电路摩尔定律，导致处理器性能和集成度无法提升，冷却成本增加等问题。
为了解决上述问题，一般采用动态电压频率调整(Dynamic Voltage and Frequency Scaling，缩写为DVFS)技术调节电源向处理器供电的供电电压，以在处理器负载轻时，降低处理器主频和供电电压；在处理器负载重时，提升处理器主频和供电电压，从而降低处理器功耗的一种降功耗技术。但是，在处理器负载重的情况下，DVFS技术无法降低处理器的供电电压，因此，DVFS技术在降低功耗方面的效果并不明显。
发明内容
本申请提供一种电压调节方法和电子设备，以保证处理器在负载轻和负载重的情况下均能够实现功耗降低和性能提升。
为了解决上述技术问题，本申请实施例提供如下技术方案：
第一方面，本申请实施例提供一种电压调节方法，应用于具有处理器以及向处理器供电的电源的电子设备。该方法包括：该处理器根据下一时段主频向电源发送供电调节信息，该供电调节信息包括下一时段主频的设定供电电压V，下一时段主频是指根据当前主频预测的主频；电源根据下一时段主频的设定供电电压V和下一时段主频的设定电压斜率R向该处理器供提供给你供电电压V out。电压斜率是指随着电源的负载电流增加供电电压V out的下降速度。该供电电压V out随着负载电流的增加减小。V min≤V out≤V，V min为处理器在下一时段主频运行时，在负载电流增大的情况下，正常运行的最低供电电压。
本申请提供的方法中，下一时段主频是指根据当前主频预测的主频，而电源根据下一时段主频的设定供电电压V和下一时段主频的设定电压斜率R向处理器提供的供电电压V out与处理器的下一时段主频相适应。并且，由于负载电流具有周期性的从最小值增加到最大负载电流的特点，使得现有技术中电源以恒压的方式输出负载端电压时，在负载电流增大的过程中，负载端电压被动下降。而本申请提供的方法主动控制电源输出的供电电压V out随着负载电流的增加而减小，使得在负载电流开始升高时电 源所输出的供电电压V out主动随着负载电流的增加而下降。此时供电电压V out小于处理器在下一时段主频的设定供电电压V且大于或等于处理器在下一时段主频运行时，在负载电流增大的情况下，正常运行的最低供电电压V min。由此可见，与现有技术相比，本申请提供的方法中电源所提供的供电电压V ou能够保证处理器正常运行的情况下，降低处理器功耗，从而提升处理器性能。而且，由于处理器的主频越高，处理器的负载量越高，因此，本申请提供的方法能够保证处理器的负载量无论高低，电源均能够在负载电流增大时，以低于当前主频设定供电电压的方式向处理器供电，使得处理器在正常运行的同时，具有较低功耗。
在一些可能的实现方式中，上述处理器根据下一时段主频向电源发送供电调节信息前，上述方法还包括：处理器根据当前负载量预测下一时段负载量，根据下一时段负载量确定下一时段主频。例如：在主板或处理器的内置存储器内存储负载量与主频的对应关系表，根据预测的下一时段负载量在负载量与主频的对应关系表中查询下一时段主频。
在一些可能的实现方式中，上述方法还包括：处理器确定下一时段主频与所述当前主频不相等的情况下，设定当前主频等于下一时段主频。鉴于供电电压调节与主频调节是相互依存的关系，上述处理器确定下一时段主频与当前主频不相等的情况下，设定当前主频等于下一时段主频包括：处理器确定下一时段主频小于当前主频，处理器根据下一时段主频向电源发送供电调节信息前，设定当前主频等于下一时段主频；处理器确定下一时段主频大于当前主频，电源根据下一时段主频的设定供电电压V和下一时段主频的设定电压斜率R向处理器提供供电电压V out后，处理器设定当前主频等于下一时段主频。
在一些可能的实现方式中，上述供电电压V out＝V-I*R，I为电源的负载电流，由供电电压V out的计算公式可以看出，供电电压V out由处理器在下一时段的设定电压斜率R、下一时段的设定供电电压V和负载电流I确定。由于电压斜率是指随着电源的负载电流增加供电电压的下降速度，因此，下一时段主频的设定电压斜率R和负载电流I的乘积实质为：电源的负载电流增大时，供电电压的主动下降量，只要保证该主动下降量大于或等于现有技术中负载电流增大情况下负载端电压被动最大下降量，就能够使得供电电压V out始终大于或等于处理器在下一时段运行时，在负载电流增大的情况下，正常运行的最低供电电压V min。
在一些可能的实现方式中，上述下一时段主频的设定供电电压V可以由处理器提供，而下一时段主频的设定电压斜率R可以存在于电源中，也可以由处理器提供。当处理器仅向电源提供下一时段主频的设定供电电压V时，处理器无需利用处理器与电源的通信接口动态设定电源内的下一时段主频的设定电压斜率R，从而有效减小通信延时和调压延时，提高调压速度。
在一些可能的实现方式中，上述处理器根据下一时段主频向电源发送供电调节信息包括：处理器根据下一时段主频从目标对应关系中查找下一时段主频的设定供电电压V，并向电源发送下一时段主频的设定供电电压V。此处目标对应关系为处理器的主频、设定供电电压和设定电压斜率的对应关系。当然，目标对应关系也可以是处理器的主频和设定供电电压的对应关系。此时处理器只需从目标对应关系中查询下一时 段主频的设定供电电压，向电源发送下一时段主频的设定供电电压，这样就能够减小通信延时和调压延时，缩短电压调节时间。
在一些可能的实现方式中，当处理器仅向电源提供下一时段主频的设定供电电压V时，上述下一时段主频的设定电压斜率R可以以恒定电压斜率的形式存在于电源中。存在方式可以为保存方式。恒定电压斜率为处理器在各个主频的设定供电电压所允许的电压斜率的最小值R min，R min＞0。由于R min＞0，可以保证处理器在任何负载量或主频工作时，电源始终能够以小于或等于设定供电电压的方式向处理器提供供电电压，使得处理器具有较低的能耗。并且，由于恒定电压斜率为处理器在各个主频的实测电压斜率的最小值R min，因此，以恒定电压斜率为下一时段主频的设定电压斜率R时，可以控制下一时段主频设定电压斜率与负载电流的乘积，使得处理器正常运行，避免恒定电压斜率取值较大时，在负载电流增大时处理器在供电电压V out无法正常运行的情况发生。
在一些可能的实现方式中，当上述下一时段主频的设定电压斜率R由处理器提供时，上述供电调节信息不仅包括下一时段主频的设定供电电压V，还包括下一时段主频的设定电压斜率R。
在一些可能的实现方式中，当上述下一时段主频的设定电压斜率R由处理器提供时，上述处理器根据下一时段主频向电源发送供电调节信息包括：处理器根据下一时段主频从目标对应关系中查找下一时段主频的设定供电电压V和下一时段主频的设定电压斜率R，并向电源发送下一时段主频的设定供电电压V和下一时段主频的设定电压斜率R。目标对应关系为处理器的主频、设定供电电压和设定电压斜率的对应关系。
在一种可能的实现方式中，上述处理器在每个主频的设定电压斜率为处理器在每个主频的设定供电电压所允许的电压斜率。换句话说，上述目标对应关系中每个主频的设定电压斜率为处理器在每个主频的设定供电电压所允许的电压斜率。此时，下一时段的设定供电电压V与下一时段的设定电压斜率R具有良好的匹配性，使得电源向处理器提供的供电电压V out在满足处理器正常运行的情况下，保证处理器的功耗最优化。
在一种可能的实现方式中，上述处理器在所有主频的设定电压斜率均等于恒定电压斜率。恒定电压斜率为处理器在各个主频的设定供电电压所允许的电压斜率的最小值R min，R min＞0。换句话说，上述目标对应关系中所有主频的设定电压斜率均等于恒定电压斜率。当处理器第一次向电源发送下一时段主频的设定供电电压V和下一时段主频的设定电压斜率R时，电源可以以恒定电压斜率的形式保存下一时段主频的设定电压斜率R。而由于目标对应关系中所有主频的设定电压斜率均等于恒定电压斜率，因此，电源实质是以恒定电压斜率的形式保存目标对应关系中所有主频的设定电压斜率。当电源需要再次调节向处理器提供的供电电压V out时，处理器只需从目标对应关系中查询下一时段主频的设定供电电压R，并将下一时段主频的设定供电电压V发送至电源，使得电源根据下一时段主频的设定供电电压V调整基准电压。这个过程中，处理器只需根据下一时段主频通过总线接口动态设定电源内的基准电压，以减小通信延时和调压延时，使得调压时长缩短。另外，由于恒定电压斜率为处理器在各主频的设定供电电压所允许的电压斜率的最小值R min，R min＞0，可以保证处理器处理器在任 何负载量或主频工作时，电源向处理器提供的供电电压V out始终满足V min≤V out≤V，从而使得处理器在正常运行的同时，具有较低的能耗。
在一些可能的实现方式中，上述处理器在每个主频的设定供电电压所允许的电压斜率R (i)＝R max(i)-ΔR (i)，R max(i)为处理器在每个主频的设定供电电压的最大电压斜率，ΔR (i)为处理器在每个主频的电压斜率裕量。此时，由于R max(i)为处理器在每个主频的设定供电电压的最大电压斜率，因此，在负载电流增大的情况下，电源向处理器提供的供电电压V out能够尽可能的接近V min，从而保证处理器以更低的功耗运行。并且，当R (i)＝R max(i)时，在负载电流增大的情况下，容易导致供电电压V out略低于V min，使得处理器无法正常运行。基于此，可以在R max(i)的基础上减去电压斜率裕量，从而保证处理器以较低的功耗正常运行。
在一种可能的实现方式中，上述处理器中每个主频的设定供电电压为V (i)。即上述目标对应关系中每个主频的设定供电电压为V (i)。V (i)＝V min(i)+ΔV (i)，V min(i)为处理器在每个主频运行时，在负载电流增大的情况下，正常运行的最低供电电压，ΔV (i)为处理器在每个主频的供电电压裕量。此时，处理器所查找的下一时段主频的设定供电电压V比处理器在下一时段主频运行时，在负载电流增大的情况下，正常运行的最低供电电压V min略大，使得电源向处理器提供的供电电压V out能够保证处理器在较低功耗下正常运行。
在一种可能的实现方式中，上述处理器根据下一时段主频向电源发送供电调节信息前，上述方法还包括：处理器根据性能差异信息对目标对应关系进行校准，使得校准后的目标对应关系与电子设备所包括的处理器匹配，进而提高电压调整的可靠性和准确性，这些性能差异信息可以由内置在处理器中的关键路径检测(critical path monitor，缩写为CPM)电路检测。CPM电路用于模拟基准处理器的时序关键路径。利用CPM电路所确定的延时水平(如延时时间)或振荡频率即为性能差异信息。当处理器在不同环境下延迟水平或振荡频率会有所不同，使得处理器在给定的主频下，最低供电电压会也会有所不同。
在一种可能的实现方式中，为了配合处理器根据性能差异信息对目标对应关系进行校准，还应当预存不考虑温度影响的多种处理器性能差异与最低供电电压差异的对应关系或者考虑温度影响的多种处理器在多个温度档位的性能差异与最低供电电压差异的对应关系。例如：当目标对应关系为基准处理器的目标对应关系时，每种处理器的性能差异可以用该种处理器的延时水平(如延时时间)或振荡频率表示，也可以用该种处理器与基准处理器在同一电压下的延时差值或者振荡频率差值间接表示，每种处理器性能差异对应的最低供电电压差异是指该种处理器与基准处理器在同一主频的最低供电电压差异。基准处理器是指多种处理器中性能最差的处理器。即基准处理器是多种处理器在同一主频的最低供电电压最大的处理器。
当不考虑温度影响时，CPM电路检测到的性能差异信息，处理器根据性能差异信息对目标对应关系进行校准，使得目标对应关系与电子设备所包括的处理器匹配包括：处理器根据性能差异信息从多种处理器性能差异与最低供电电压差异的对应关系中查找最低供电电压差异，根据最低供电电压差异对目标对应关系中每个主频对应的设定供电电压进行校准，使得校准后的目标对应关系与所述电子设备所包括的处理器匹配。
当考虑温度影响的情况下，CPM电路检测到的性能差异信息，处理器根据性能差异信息对目标对应关系进行校准，使得目标对应关系与电子设备所包括的处理器匹配包括：处理器根据当前温度从多种处理器在多个温度档位的性能差异与最低供电电压差异的对应关系中查找多种处理器在当前温度所在温度档位的性能差异与最低供电电压差异的对应关系，根据性能差异信息从多种处理器在当前温度所在温度档位的性能差异与最低供电电压差异的对应关系中查找当前性能差异信息匹配的最低供电电压差异，根据性能差异信息匹配的最低供电电压差异对目标对应关系中每个主频对应的设定供电电压进行校准，使得校准后的所述目标对应关系与电子设备所包括的处理器匹配。
在一种可能的实现方式中，上述电子设备含有存储介质。该存储介质可以独立于处理器存在，也可以内置于处理器内。上述目标对应关系可以多种方式形式直接或间接的保存在该存储介质内。当然，该存储介质还可以保存多种处理器性能差异与最低供电电压差异的对应关系，或者多种处理器在多个温度档位的性能差异与最低供电电压差异的对应关系。例如：多种处理器性能差异与最低供电电压差异的对应关系可以以关系表或函数关系式的形式存储在存储介质中。多种处理器在多个温度档位的性能差异与最低供电电压差异的对应关系以关系表或函数关系式的形式存储在存储介质中。
在一种可能的实现方式中，上述目标对应关系存储在上述存储介质中。该目标对应关系为基准处理器的目标对应关系。该基准处理器为多种处理器在同一主频的最低供电电压最大的处理器，即基准处理器是多种处理器中性能最差的处理器。此时，目标对应关系中每个主频对应的设定供电电压和设定电压斜率可以满足多种处理器的电压调节，因此，基准处理器的目标对应关系具有广泛的适用性。应理解，多种处理器可以按照生产工艺、老化程度等区分，不管是生产工艺不同还是老化程度不同，最终都会以性能差异信息的方式体现出。例如：对于同一型号的处理器来说，不同批次的处理器在生产工艺上存在细微差异，导致不同批次的同一型号处理器属于不同种类。
在一种可能的实现方式中，上述目标对应关系存储在存储介质中。上述目标对应关系为存储介质所在电子设备包括的处理器的目标对应关系。该目标对应关系可以在电子设备出厂后经过调试测定，并保存在存储介质中。
在一种可能的实现方式中，上述电子设备还包括存储介质。该存储介质存储有基准处理器在多个温度档位的目标对应关系。基准处理器的定义参考前文，此处不再详述。此时，处理器根据下一时段主频向电源发送供电调节信息前，上述方法还包括：处理器根据当前温度从基准处理器在多个温度档位的目标对应关系查找目标对应关系。该目标对应关系为基准处理器在当前温度所在温度档位的目标对应关系。此时，如果对所查找的目标对应关系进行校准，可以使得校准后的目标对应关系与处理器的匹配性更好。
在一种可能的实现方式中，在不考虑温度影响的前提下，电子设备上电，CPM电路检测到性能差异信息，上述处理器根据下一时段主频向电源发送供电调节信息前，上述方法还包括：处理器根据性能差异信息从多种处理器的目标对应关系查找与电子设备包括的处理器匹配的目标对应关系。该目标对应关系所对应的处理器的差异性信息与CPM电路测试的差异性信息匹配性比较好。
当考虑温度影响的情况下，在电子设备上电的情况下，CPM电路检测到性能差异信息，上述处理器根据下一时段主频向所述电源发送供电调节信息前，上述方法还包括：处理器根据当前温度从多种处理器在多个温度档位的目标对应关系查找多种处理器在当前温度所在温度档位的目标对应关系；根据性能差异信息从多种处理器在当前温度所在温度档位的目标对应关系中查找与电子设备包括的处理器匹配的目标对应关系。
在一种可能的实现方式中，为了配合处理器查找与电子设备包括的处理器匹配的目标对应关系，上述电子设备包括存储介质。在不考虑温度影响的情况下，上述电子设备还包括存储介质，可以在出厂前利用CPM电路测定多种处理器的性能差异信息和多种处理器的目标对应关系，并建立二者之间的关系，并将多种处理器的性能差异信息和多种处理器的目标对应关系保存在存储介质中。在考虑温度影响的前提下，可以在出厂前利用CPM电路测定多种处理器在多个温度档位的性能差异信息和多种处理器在多个温度档位的目标对应关系，并建立多种处理器在多个温度档位的性能差异信息与多种处理器在多个温度档位的目标对应关系的相互依赖关系，然后将多种处理器在多个温度档位的性能差异信息与多种处理器在多个温度档位的目标对应关系保存在存储介质中。
第二方面，本申请提供一种电子设备。该电子设备包括：处理器，用于根据下一时段主频向电源发送供电调节信息；供电调节信息包括下一时段主频的设定供电电压V，下一时段主频是指根据当前主频预测的主频；电源，用于根据下一时段主频的设定供电电压V和下一时段主频的设定电压斜率R向处理器提供供电电压V out。电压斜率是指随着电源的负载电流增加供电电压V out的下降速度；该供电电压V out随着电源的负载电流的增加减小；V min≤V out≤V，V min为处理器在下一时段主频运行时，在负载电流增大的情况下，正常运行的最低供电电压。
在一种可能的实现方式中，上述处理器还用于根据下一时段主频向电源发送供电调节信息前，根据当前负载量预测下一时段负载量，根据下一时段负载量确定下一时段主频。
在一些可能的实现方式中，上述处理器还用于处理器确定下一时段主频与所述当前主频不相等的情况下，设定当前主频等于下一时段主频。例如：处理器还用于确定下一时段主频小于当前主频，根据下一时段主频向电源发送供电调节信息前，设定当前主频等于下一时段主频。电源用于根据下一时段主频的设定供电电压V和下一时段主频的设定电压斜率R向处理器提供供电电压V out后，处理器具体用于确定下一时段主频大于当前主频，设定当前主频等于下一时段主频。
在一种可能的实现方式中，上述供电电压V out＝V-I*R，I为电源的负载电流。
在一种可能的实现方式中，上述处理器具体用于根据下一时段主频从目标对应关系中查找下一时段主频的设定供电电压V，并向电源发送下一时段主频的设定供电电压V。该目标对应关系为处理器的主频、设定供电电压和设定电压斜率的对应关系或处理器的主频和设定供电电压的对应关系。
在一种可能的实现方式中，上述下一时段主频的设定电压斜率以恒定电压斜率的形式存在于电源中。该恒定电压斜率为处理器在各个主频的设定供电电压所允许的电 压斜率的最小值R min，R min＞0。
在一种可能的实现方式中，上述供电调节信息还包括下一时段主频的设定电压斜率R。
在一种可能的实现方式中，上述处理器具体用于根据下一时段主频从目标对应关系中查找下一时段主频的设定供电电压V和下一时段主频的设定电压斜率R，并向电源发送由下一时段主频的设定供电电压V和下一时段主频的设定电压斜率R。目标对应关系为处理器的主频、设定供电电压和设定电压斜率的对应关系。
在一种可能的实现方式中，上述处理器在每个主频的设定电压斜率为处理器在每个主频的设定供电电压所允许的电压斜率。
在一种可能的实现方式中，上述处理器在所有主频的设定电压斜率均等于恒定电压斜率。该恒定电压斜率为处理器在各个主频的设定供电电压所允许的电压斜率的最小值R min，R min＞0。
在一种可能的实现方式中，上述处理器在每个主频的设定供电电压所允许电压斜率为R (i)，R (i)＝R max(i)-ΔR (i)，R max(i)为述处理器在每个主频的设定供电电压的最大电压斜率，ΔR (i)为处理器在每个主频的电压斜率裕量。
在一种可能的实现方式中，上述处理器在每个主频的设定供电电压V (i)＝V min(i)+ΔV (i)，V min(i)为处理器在每个主频运行时，在负载电流增大的情况下，正常运行的最低供电电压，ΔV (i)为处理器在每个主频的供电电压裕量。
在一种可能的实现方式中，上述处理器还用于根据下一时段主频向电源发送供电调节信息前，根据性能差异信息对目标对应关系进行校准，使得校准后的目标对应关系与电子设备所包括的处理器匹配。
在一种可能的实现方式中，在不考虑温度影响的前提下，上述处理器具体用于根据性能差异信息从多种处理器性能差异与最低供电电压差异的对应关系中查找最低供电电压差异，根据最低供电电压差异对目标对应关系中每个主频对应的设定供电电压进行校准，使得校准后的目标对应关系与电子设备所包括的处理器匹配。
在考虑温度影响的前提下，上述处理器具体用于处理器根据当前温度从多种处理器在多个温度档位的性能差异与最低供电电压差异的对应关系中查找多种处理器在当前温度所在温度档位的性能差异与最低供电电压差异的对应关系，根据性能差异信息从多种处理器在当前温度所在温度档位的性能差异与最低供电电压差异的对应关系中查找当前性能差异信息匹配的最低供电电压差异，根据性能差异信息匹配的最低供电电压差异对目标对应关系中每个主频对应的设定供电电压进行校准，使得校准后的目标对应关系与电子设备所包括的处理器匹配。
在一种可能的实现方式中，上述电子设备含有存储介质。该存储介质可以独立于处理器存在，也可以内置于处理器内。上述目标对应关系可以多种方式形式直接或间接的保存在该存储介质内。当然，该存储介质还可以保存多种处理器性能差异与最低供电电压差异的对应关系，或者多种处理器在多个温度档位的性能差异与最低供电电压差异的对应关系。例如：多种处理器性能差异与最低供电电压差异的对应关系可以以关系表或函数关系式的形式存储在存储介质中。多种处理器在多个温度档位的性能差异与最低供电电压差异的对应关系以关系表或函数关系式的形式存储在存储介质中。
在一种可能的实现方式中，上述目标对应关系存储在存储介质中，目标对应关系为基准处理器的目标对应关系。该基准处理器为多种处理器在同一主频的最低供电电压最大的处理器。
在一种可能的实现方式中，上述目标对应关系存储在存储介质中。上述目标对应关系为存储介质所在电子设备包括的处理器的目标对应关系。该目标对应关系可以在电子设备出厂后经过调试测定，并保存在存储介质中。
在一种可能的实现方式中，上述电子设备还包括存储介质。该存储介质存储有基准处理器在多个温度档位的目标对应关系。该基准处理器为多种处理器在同一主频的最低供电电压最大的处理器。处理器还用于根据下一时段主频向电源发送供电调节信息前，根据当前温度从基准处理器在多个温度档位的目标对应关系查找目标对应关系。该目标对应关系为基准处理器在当前温度所在温度档位的目标对应关系。
在一种可能的实现方式中，在不考虑温度影响的前提下，处理器还用于根据下一时段主频向所述电源发送供电调节信息前，根据性能差异信息从多种处理器的目标对应关系中查找与电子设备包括的处理器匹配的目标对应关系。在考虑温度影响的前提下，处理器还用于根据下一时段主频向所述电源发送供电调节信息前，根据当前温度从多种处理器在多个温度档位的目标对应关系查找多种处理器在当前温度所在温度档位的目标对应关系；根据性能差异信息从多种处理器在当前温度所在温度档位的目标对应关系中查找与电子设备包括的处理器匹配的目标对应关系。
在一种可能的实现方式中，上述电子设备包括存储介质。在不考虑温度影响的情况下，存储介质存储有多种处理器的性能差异信息和多种处理器的目标对应关系，且多种处理器的性能差异信息和多种处理器的目标对应关系具有相互依赖关系。在考虑温度影响的前提下，多种处理器在多个温度档位的性能差异信息与多种处理器在多个温度档位的目标对应关系保存在存储介质中，并且多种处理器在多个温度档位的性能差异信息与多种处理器在多个温度档位的目标对应关系具有相互依赖关系。
第三方面，本申请还提供了一种处理器。该处理器包括一个或者多个模块，用于实现上述第一方面由处理器执行的步骤，该一个或者多个模块可以与上述第一方面的方法中的由处理器执行的各个步骤相对应。
第四方面，本申请提供一种电源。该电源包括一个或者多个模块，用于实现上述第一方面由电源执行的步骤，该一个或者多个模块可以与上述第一方面的方法中的由电源执行的各个步骤相对应。
第五方面，本申请提供一种终端设备。该终端设备包括处理器和电源。所述处理器用于执行如第一方面或第一方面的任一种可能的实现方式描述的由处理器执行的步骤，所述电源用于执行如第一方面或第一方面的任一种可能的实现方式描述的由电源执行的步骤。
在一些可能的实现方式中，上述终端设备还包括存储介质，用于存储计算机程序和目标对应关系。
第六方面，本申请提供一种通信设备，该通讯设备包括处理器和电源，所述处理器用于执行如第一方面或第一方面的任一种可能的实现方式描述的由处理器执行的步骤，所述电源用于执行如第一方面或第一方面的任一种可能的实现方式描述的由电源 执行的步骤。
在一些可能的实现方式中，上述通信设备还包括存储介质，用于存储计算机程序和目标对应关系。
第七方面，本申请还提供一种芯片。该芯片包括处理器以及与通信接口耦合的通信接口。该处理器用于运行计算机程序或指令，以实现如第一方面或第一方面任一可能的实现方式所描述的由处理器执行的步骤。
在一种可能的实现方式中，上述芯片还包括存储器，用于存储计算机程序或指令以及目标对应关系。
第八方面，本申请还提供一种芯片。该芯片包括处理器以及与通信接口耦合的通信接口。该处理器用于运行计算机程序或指令，以实现如第一方面或第一方面任一可能的实现方式所描述的由电源执行的步骤。
在一种可能的实现方式中，上述芯片还包括存储器，用于存储计算机程序。
上述提供的任一种装置或计算机存储介质或计算机程序产品或芯片或通信系统均用于执行上文所提供的对应的方法，因此，其所能达到的有益效果可参考上文提供的对应的方法中对应方案的有益效果，此处不再赘述。
附图说明
图1为本申请实施例提供的电子设备的结构示意图；
图2为本申请实施例中处理器和电源的连接结构示意图；
图3为本申请实施例提供的一种交通工具通信系统的系统架构图；
图4为本申请实施例提供的电压调节方法的流程示意图一；
图5为本申请实施例提供的电压调节方法的流程示意图二；
图6为电源负载瞬态过程示意图；
图7为电源loadline特性示意图；
图8为DVFS技术降低功耗的机理示意图；
图9为本申请方法、DVFS技术、固定电压法供电的对比图；
图10为处理器的主频和电压斜率曲线；
图11为本申请实施例提供的电压调节方法的流程示意图三；
图12为本申请实施例提供的电压调节方法的流程示意图四；
图13为本申请实施例提供的电压调节方法的流程示意图五；
图14为额定模式下供电电压的电压斜率图；
图15为不同功耗模式下的电压斜率图；
图16为本申请实施例提供的一种设备的结构示意图；
图17为本申请实施例提供的一种电压调节装置的结构示意图；
图18为本申请实施例提供的另一种电压调节装置的结构示意图；
图19为本申请实施例提供的再一种电压调节装置的结构示意图；
图20为本申请实施例提供的芯片的结构示意图。
具体实施方式
在介绍本申请实施例之前首先对本申请实施例中涉及到的相关名词作如下释义：
动态电压频率调整(Dynamic Voltage and Frequency Scaling，缩写为DVFS)技术 是指：根据芯片所运行的应用程序对计算能力的不同需要，动态调节芯片的运行频率和电压(对于同一芯片，频率越高，需要的电压也越高)，从而达到节能的目的。具体来说，在处理器负载轻时，降低处理器主频和供电电压；在处理器负载重时，提升处理器主频和供电电压，从而降低处理器功耗的一种降功耗技术。
英特尔睿频加速技术又称Turbo Boost技术，简称为Turbo技术。Turbo技术是一种多核中央处理器的自动超频(Over Clocking，缩写为OC)技术。当中央处理器的内核未达到温度、电流和功耗规格阈值，Turbo技术将自动允许中央处理器的某些活动内核超出额定主频运行，提升处理器性能，应对峰值负载。
基本输入输出系统(Basic Input Output System，缩写为BIOS)是一组固化到计算机内主板上一个只读内存镜像芯片上的程序，它保存着计算机最重要的基本输入输出的程序、开机后自检程序和系统自启动程序。
自适应电压调节(adaptive voltage scaling，缩写为AVS)技术是一种实时、供电电压可连续调节的闭环控制电源管理技术。AVS技术可以通过关键路径检测(critical path monitor，缩写为CPM)电路实现。CPM电路用于模拟基准处理器的时序关键路径，进而确定延迟水平或振荡频率等性能差异信息，从而根据性能差异信息自适应地对电路供电电平进行调整，以保证在延迟水平或振荡频率满足系统要求的前提下，并尽量多地降低电压。
电压识别码(Voltage Identification，缩写为VID)又称VID编码，是指代表电压值的编码，其实质为数字化的电压值。
电压调整模块(Voltage Regulator Module，VRM)是为微处理器提供合适的供电电压的一项装置，也称VRM电源。VRM电源可以识别VID编码调整输出恒压供电电压，使输出的恒压供电电压与VID编码所代表的电压值一致。具体来说，VRM电源内部集成8bit的VID编码，分别代表256种电压值，处理器发送8bit的VID编码给VRM电源，VRM电源可以利用集成的8bit VID编码识别处理器发送的VID编码，从而确定供电电压。
负载线又称Loadline，是指VRM电源所输出的供电电压具有随着负载电流增大而线性下降的特性曲线。
电压下降斜率简称电压斜率或Loadline值，其表示供电电压随着VRM电源等电源的负载电流增加而线性下降速度。当Loadline值越大，说明VRM电源所输出的供电电压随着负载电流增大而线性下降速度比较快。当Loadline值越小，说明VRM电源所输出的供电电压随着负载电流增大而线性下降速度比较慢。
锁相环(Phase Locked Loop，缩写为PLL)又称锁定相位的环路。它这是一种典型的反馈控制电路，利用外部输入的参考信号控制环路内部振荡信号的频率和相位，实现输出信号频率对输入信号频率的自动跟踪，一般用于闭环跟踪电路。
数字模拟转换器(Digital to analog converter，缩写为DAC)是一种将数字信号转换为模拟信号(以电流、电压或电荷的形式)的设备。
电源管理总线(Power Management Bus，缩写为PMBus)是一种支持开放标准的数字电源管理协议的总线。开放标准的数字电源管理协议可通过定义传输和物理接口以及命令语言来促进与电源转换器或其他设备的通信。
为了便于清楚描述本申请实施例的技术方案，在本申请的实施例中，采用了“第一”、“第二”等字样对功能和作用基本相同的相同项或相似项进行区分。例如，第一阈值和第二阈值仅仅是为了区分不同的阈值，并不对其先后顺序进行限定。本领域技术人员可以理解“第一”、“第二”等字样并不对数量和执行次序进行限定，并且“第一”、“第二”等字样也并不限定一定不同。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b的结合，a和c的结合，b和c的结合，或a、b和c的结合，其中a，b，c可以是单个，也可以是多个。
本申请实施例提供的方法应用于电子设备中。该电子设备可以应用于终端或通信设备中。终端可以为车载终端、手机、电脑、服务器等各种终端设备中。通信设备可以为基站、卫星等各种通信设备。
图1示出一种本申请实施例提供的电子设备的结构示意图。如图1所示，该电子设备100包括处理器101、电源102和存储介质103。处理器101和电源102可以集成在一起，也可以独立存在。该处理器101可以覆盖终端、数据中心设备的各类通用处理器，当然也可以为车载处理器，但不仅限于此所列。该处理器101可以包括一个或多个CPU。存储介质103耦合至处理器，并可存储执行本申请方案的计算机执行指令和数据，并由处理器101来控制执行。处理器101用于执行存储介质中存储的计算机执行指令，从而实现本申请下述实施例提供的方法。可选的，本申请实施例中的计算机执行指令也可以称之为应用程序代码，本申请实施例对此不作具体限定。
如图1所示，上述存储介质103可以为独立于处理器101存在，也可以内置于处理器101内。例如：存储介质103可以为处理器101内的内置存储器，也可以为主板上的BIOS存储器。
如图1所示，上述处理器101可以为中央处理器(Central Processing Unit，缩写为CPU)通用处理器、数字信号处理器(digital signal processing，DSP)、ASIC、现成可编程门阵列(field-programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。存储器可以为随机存储器(RAM)，也可以包括非易失性存储器(non-volatile memory)，例如磁盘存储器，闪存(Flash)等，不再一一列举。具体的，存储器可以为主板上的存储器(如BIOS存储器)等外部存储器，也可以为处理器的内置存储器。例如：当处理器101为CPU时，存储介质103可以为CPU内部的内置存储器。
如图1所示，上述存储介质103可以为随机存取存储器(Random Access Memory， RAM)、闪存、只读存储器(Read Only Memory，ROM)、可擦除可编程只读存储器(Erasable Programmable ROM，EPROM)、电可擦可编程只读存储器(Electrically EPROM，EEPROM)、寄存器、硬盘、移动硬盘、只读光盘(CD-ROM)或者本领域熟知的任何其它形式的存储介质中。
图2示出了本申请实施例中处理器和电源的连接结构示意图。如图2所示，处理器101包括处理器内核1011和锁相环1013。锁相环1013在处理器内核1011的控制下调节或设置处理器的主频。并且在处理器101还包括内置存储器1012时，该内置存储器1012可以实现上述存储介质103的功能，从而可以减少电子设备中不必要的硬件，使得电子设备的集成度比较高。
在一种示例中，如图2所示，上述处理器101还包括CPM电路1015，CPM电路1015与处理器内核1011电连接。
图1所示的电源102可以为各种具有电压调节功能的电源，可向处理器101提供供电电压。图2所示出的电源102是以VRM电源为例的结构示意图。如图2所示，电源102包括VRM芯片1021、逻辑控制电路1022和buck变换器1023。VRM芯片1021与逻辑控制电路1022的信号输入端连接，逻辑控制电路1022的信号输出端与buck变换器1023电连接，使得VRM芯片1021向逻辑控制电路1022提供载有信息的信号。当然，该电源102还可以包括寄存器1024或其他具有存储功能的器件，可以存储供VRM芯片1021调取的信息。在一些时候，buck变换器1023也可以独立于电源102，设在电源102与处理器101之间。
示例性的，如图2所示，该buck变换器1023包括接地电容C和多个并联在一起的电感L，多个并联在一起的电感L的第一端与逻辑控制电路1022的信号输出端连接，多个并联在一起的电感L的第二端还通过接地电容C接地。由此可见，buck变换器1023的连接关系为多通道交错并联准方波(quasisquare-wave，缩写为QSW)拓扑，具有良好的纹波互消作用，且并联的电感数目越多，纹波互消作用越好。至于并联的电感L的数量则根据实际需要设定。但这些电感L的数量至少为2个。例如：当Buck变换器1023中并联的电感数量为4个，此时，当多通道交错并联QSW拓扑的占空比为0.25、0.5或0.75时，电源102所输出的供电电压的纹波才可以完全互消。如果占空比不等于以上值，只能实现部分纹波互消。
如图2所示，上述处理器101与电源102之间可以通信。在实际应用中，上述处理器101包括通信接口1014。上述电源102包括通信接口1025，用以实现处理器101和电源102之间的通信。例如：处理器101与电源102通过总线或电力线连接。总线可以电源管理总线(Power Management Bus，缩写为PMBus总线)，为I2C(Inter-Integrated Circuit)总线。例如：处理器101与电源102通过PMBus总线通信。此时，处理器101的通信接口和电源102的通信接口均为PMBus接口。
本申请实施例提供的方法可以由任何通用处理器或专用电路(ASIC)等。下面以车载处理器应用于交通工具为应用场景进行描述。以下描述仅用于理解，不作为限定。
图3是本申请实施例提供的一种交通工具通信系统的系统架构图。在图3中，除非上下文另外指出，否则相似的符号标识相似的组件。本文中所描述的说明性系统和方法实施例并非意图进行限制。可容易理解，所公开的系统和方法的某些方面可以按 多种不同的配置进行布置和组合，所有这些都在本文中被设想到。
如图3所示，该交通工具通信系统10包括交通工具12、一个或多个无线载波系统14、地面通信网络16、计算机18以及呼叫中心20。应该理解的是，所公开的方法能够与任何数量的不同系统一起使用，并不特定地限于此处示出的运行环境。同样，通信系统10的架构、构造、设置和运行以及它的单独部件在现有技术中通常是已知的。因此，以下的段落仅仅简单地提供了一个示例通信系统10的概述，本文没有示出的其它系统也能够使用所公开的方法。
上述交通工具12可以为无人驾驶交通工具，也可以为有人驾驶的交通工具。交通工具12可实现在汽车上或可采取汽车的形式。然而，示例系统还可实现在其它车辆上或采取其它车辆的形式，诸如轿车、卡车、摩托车、公交车、船、飞机、直升机、割草机、铲雪车、休旅车、游乐园车辆、农业设备、施工设备、有轨电车、高尔夫球车、火车和电车等其它车辆。此外，机器人装置也可用于执行本文描述的方法和系统。
在图3中示出一些交通工具硬件28。这些交通工具硬件28包括信息通讯单元30、麦克风32、一个或多个按钮或者其它控制输入34、音频系统36、可视显示器38、以及GPS(Global Position System，全球定位系统)模块40和多个VM模块42(Vehicle Security Module，为了与前文VSM电源区别，此处缩写为VM，中文名称为交通工具安全单元)。这些设备中的一些能够直接连接到信息通讯单元，例如麦克风32和按钮34，而其它的使用一个或多个网络连接实现间接连接，例如通信总线44或者娱乐总线46。合适的网络连接的实例包括CAN(Controller Area Network，控制器局域网)、MOST(Media Oriented Systems Transport，媒体导向系统转移)、LIN(Local Interconnect Network，局部互联网络)、LAN(Local Area Network，局域网)以及其它合适的连接，例如以太网或者符合已知的ISO(International Organization for Standardization，国际标准化组织)、SAE(Society of Automotive Engineers，美国机动车工程师学会)和IEEE(Institute of Electrical and Electronics Engineers，国际电气与电子工程师学会)标准和规定的其它连接，这仅仅列举一小部分。
如图3所示，信息通讯单元30可以是OEM(Original Equipment Manufacturer，原始设备制造商)安装(嵌入)或者配件市场设备，它安装在交通工具中，且能够在无线载波系统14上且经无线联网进行无线声音和/或数据通信。这能使交通工具与呼叫中心20、其它启用信息通讯的交通工具、或者一些其它实体或者设备通信。信息通讯单元优选地使用无线电广播来与无线载波系统14建立通信信道(声音信道和/或数据信道)，使得声音和/或数据传输能够在信道上被发送和接收。通过提供声音和数据通信，信息通讯单元30能使交通工具提供多种不同的服务，包括与导航、电话、紧急救援、诊断、信息娱乐等相关联的那些服务。数据能够经数据连接(例如经数据信道上的分组数据传输，或者经使用现有技术中已知技术的声音信道)被发送。对于包括声音通信(例如，在呼叫中心20处具有现场顾问live advisor或者声音响应单元)和数据通信(例如，提供GPS位置数据或者车辆诊断数据至呼叫中心20)两者的组合服务，系统可利用在声音信道上的单个呼叫，并根据需要在声音信道上在声音和数据传输之间切换，这可以使用本领域技术人员已知的技术来完成。此外，可使用短消息服务SMS发送和接收数据(例如，PDP(Packet Data Protocol，分组数据协议))；信息通讯单元可被配 置为移动终止和/或发起，或者被配置为应用终止和/或发起。
上述信息通讯单元30根据GSM(Global System for Mobile Communication，全球移动通信系统)或者CDMA(Code Division Multiple Access，码分多址)标准利用蜂窝通信，因此包括用于声音通信(例如免提呼叫)的蜂窝芯片集50(标准蜂窝芯片集)、用于数据传输的无线调制解调器、处理设备52、一个或多个数字存储器54以及双天线56。应该明白，调制解调器能够通过存储在信息通讯单元内的软件实施且由处理设备52执行，或者它能够是位于信息通讯单元30内部或者外部的分开的硬件部件。调制解调器能够使用任何数量的不同标准或者协议(例如EVDO(CDMA20001xEV-DO，EVDO)、CDMA、GPRS(General Packet Radio Service，通用分组无线服务技术)和EDGE(Enhanced Data Rate for GSM Evolution，增强型数据速率GSM演进技术))来运行。交通工具和其它联网设备之间的无线联网也能够使用信息通讯单元30来执行。为此目的，信息通讯单元30能够被配置为根据一个或多个无线协议(例如，IEEE 802.11协议、WiMAX(Worldwide Interoperability for Microwave Access，全球微波互联接入)或者蓝牙中的任何一种)无线通信。当用于例如TCP/IP(Transmission Control Protocol/Internet Protocol，传输控制协议/因特网互联协议)的分组交换数据通信时，信息通讯单元能够被配置具有静态IP地址，或者能够被设置以从网络上的另一个设备(例如路由器)或者从网络地址服务器自动接收所分配的IP地址。
上述处理设备52为车载处理器。该处理设备52可以是能够处理电子指令的任何类型的设备，包括微处理器、微控制器、主处理器、控制器、交通工具通信处理器、以及ASIC(Application Specific Integrated Circuit，专用集成电路)。它能够是仅用于信息通讯单元30的专用处理器或者能够与其它交通工具系统共享。处理设备52执行各种类型的数字存储指令，例如存储在存储器54中的软件或者固件程序，它能使信息通讯单元提供较宽的多种服务。具体的，处理设备52能够执行程序或者处理数据，以执行本文讨论的方法的至少一部分。处理设备52可以为应用本申请方法的电子设备。
上述信息通讯单元30能够被用于提供不同范围的交通工具服务，包括与来自交通工具其他部分的无线通信。这样的服务包括:转向指引turn-by-turn direct 1ns以及与基于GPS的交通工具导航模块40结合提供的其它导航相关联的服务；安全气囊部署通知以及与一个或多个碰撞传感器接口模块(例如主体控制模块(未图示))结合提供的其它紧急或路边救援相关联的服务。使用一个或多个诊断模块的诊断报告。以及信息娱乐相关联的服务，其中音乐、网页、电影、电视节目、视频游戏和/或其它信息被信息娱乐模块下载，并被存储用于当前或稍后回放。以上列出的服务决不是信息通讯单元30的所有能力的详尽列表，而仅仅是信息通讯单元能够提供的一些服务的列举。此外，应该理解，至少一些上述模块能够以存储在信息通讯单元30内部或外部的软件指令的形式实施，它们可以是位于信息通讯单元30内部或外部的硬件部件，或者它们可以是彼此集成的和/或共享的，或者与位于整个交通工具中的其它系统集成和/或共享，这仅列举几种可能性。位于信息通讯单元30外部的VM模块42在工作的情况下，它们可利用交通工具总线44与信息通讯单元30交换数据和命令。
GPS模块40从GPS卫星60接收无线电信号。从这些信号，GPS模块40能够确定交通工具的位置，该交通工具的位置被用于给交通工具驾驶者提供导航和其它位置 相关联的服务。导航信息能够被呈现在显示器38上(或者交通工具内的其它显示器)或者能够用语言呈现，例如当提供转向导航时完成。能够使用专用的交通工具内的导航模块(可以是GPS模块40的一部分)来提供导航服务，或者一些或全部导航服务可以经信息通讯单元30来完成，其中位置信息被发送到远程位置，以便于为交通工具提供导航地图、地图标注(感兴趣的点、餐馆等)、路线计算等等。位置信息能够被提供给呼叫中心20或者其它远程计算机系统，例如计算机18，以用于其它的目的，例如车队管理。并且，新的或者更新的地图数据能够经信息通讯单元30从呼叫中心20下载至GPS模块40。
除了音频系统36和GPS模块40之外，交通工具12能够包括电子硬件部件形式的其它交通工具安全模块，即VM模块42，VM模块42位于整个交通工具中，通常从一个或多个传感器接收输入，并使用所感测到的输入来执行诊断、监测、控制、报告和/或其它功能。VM模块42中的每一个优选地通过通信总线44连接到VM模块42，也连接到信息通讯单元30，并且能够被编程以运行交通工具系统和子系统诊断测试。例如，一个VM模块42能够是控制发动机运行的各方面(例如，燃料点火和点火时间)的ECM(EngineControlModule，发动机控制模块)，另一个VM模块42能够是调节交通工具的动力传动系的一个或多个部件的运行的动力传动系控制模块，且另一个VM模块42能够是管理位于整个交通工具中的各个电部件(如同交通工具的电动门锁和前灯)的主体控制模块。根据一个实施例，发动机控制模块装备有OBD(On Board Diagnostics，车载诊断)特征，车载诊断特征提供大量实时数据，例如从各种传感器(包括交通工具排放传感器)接收的数据，并提供标准化系列的诊断故障代码，诊断故障代码允许技术人员快速地识别和维修交通工具内的故障。如本领域的技术人员所明白的，以上提及的VM模块仅仅是可以在交通工具12内使用的一些模块的实例，许多其它的模块也是可能的。
交通工具电子件28还包括多个交通工具用户接口，为交通工具司乘人员提供了提供和/或接收信息的装置，包括麦克风32、按钮34、音频系统36和可视显示器38。如在本文所使用的，术语“交通工具用户接口”广泛地包括任何合适形式的电子设备，包括硬件和软件部件，该电子设备位于交通工具上，且能使交通工具用户与交通工具的部件通信或者通过交通工具的部件通信。麦克风32提供了至信息通讯单元的音频输入，以能使驾驶者或者其他司乘人员提供声音命令，并执行经无线载波系统14的免提护叫。为此目的，它能够连接到车载自动化声音处理单元，车载自动化声音处理单元利用现有技术中已知的HMI(Human Machine Interface，人机接口)技术。按钮34允许手动用户输入至信息通讯单元30，以发起无线电话呼叫和提供其它数据、响应或者控制输入。分开的按钮能够被用于发起紧急呼叫以及常规服务求助呼叫至呼叫中心20。音频系统36提供音频输出至交通工具司乘人员且能够是专用的单机系统或者主交通工具音频系统的一部分。根据此处所示的具体实施例，音频系统36可运行地联接到交通工具总线44和娱乐总线46，且能够提供AM(Amplitude Modulation，调幅)、FM(Frequency Modulation，调频)和卫星广播、DVD(Digital Versatile Disc，数字多功能光盘)和其它多媒体功能。这个功能能够与以上描述的信息娱乐模块结合提供或者独立提供。可视显示器38优选地是图形显示器，例如仪表板上的触摸屏或者从挡风玻璃反射的抬 头显示器，且能够被用于提供多种输入和输出功能。各种其它交通工具用户接口也能够被利用，因为图3中的接口仅仅是一种具体实施方案的实例。
无线载波系统14优选地是蜂窝电话系统，包括多个蜂窝塔70(仅示出一个)、一个或多个MSC(Mobile Switching Center，移动交换中心)72以及将无线载波系统14与地面网络16连接所要求的任何其它的联网部件。每个蜂窝塔70包括发送和接收天线以及基站，来自不同蜂窝塔的基站直接连接到MSC 72或者经中间装置(例如基站控制器)连接到MSC 72。无线载波系统14可实施任何合适的通信技术，包括例如模拟技术(例如AMPS(Advanced Mobile Phone System，模拟移动通信系统))或者更新的数字技术(例如CDMA(例如CDMA2000)或GSM/GPRS)。如本领域的技术人员将会明白的，各种蜂窝塔/基站/MSC设置都是可能的，且可与无线载波系统14一起使用。例如，基站和蜂窝塔能够共同位于相同的地点，或者它们能够彼此定位较远，每个基站能够响应单个的蜂窝塔或者单个基站能够服务各个蜂窝塔，各个基站能够联接到单个MSC，这仅仅例举一小部分可能的设置。
除了使用无线载波系统14之外，卫星通信形式的不同无线载波系统能够被用于提供与交通工具的单向或者双向通信。这能够使用一个或多个通信卫星62和上行链路发射站64来完成。单向通信能够是例如卫星广播服务，其中节目内容(新闻、音乐等)被发射站64接收、打包用于上传、且接下来发送到卫星62，卫星62将节目广播到用户。双向通信能够是例如使用卫星62在交通工具12和站64之间中继电话通信的卫星电话服务。如果使用，这种卫星电话能够被附加到无线载波系统14或者代替无线载波系统14使用。
地面网络16可以是常规的陆基无线电通信网络，它连接到一个或多个固定电话，并将无线载波系统14连接到呼叫中心20。例如，地面网络16可包括PSTN(Public Switched Telephone Network，公共交换电话网络)，例如被用于提供有线电话、分组交换数据通信以及互联网基础设施的PSTN。地面网络16的一个或多个部分能够通过使用标准的有线网络、光纤或者其它光学网络、电缆网络、电力线、其它无线网络(例如WLAN(Wireless Local Area Networks，无线局域网))、或者提供BWA(Broadband Wireless Access，宽带无线访问)的网络及其任何组合来实施。地面网络16还可以包括用于存储、上传、转换和/或在发送者和接收者之间传输SMS(Short Message Service，短消息)的一个或多个SMSC(Short Message Service Center，短消息服务中心)。例如，SMSC可以从呼叫中心20或者内容提供商(例如，外部短消息实体或者ESME)接收SMS消息，且SMSC可以将SMS消息传输给交通工具12(例如，移动终端设备)。SMSC和它们的功能对于技术人员来说是已知的。此外，呼叫中心20不必经地面网络16连接，但是可以包括无线电话设备，使得它能够直接与无线网络(例如无线载波系统14)通信。
计算机18能够是多个计算机中的一个，这多个计算机可经私人或者公共网络(例如互联网)访问。每个这样的计算机18都能够被用于一个或多个目的，例如交通工具可经信息通讯单元30和无线载波系统14访问网页服务器。其它这样的可访问计算机18能够是例如:服务中心计算机，其中诊断信息和其它交通工具数据能够经信息通讯单元30从交通工具上传；交通工具所有者或者其他用户为例如如下目的而使用的客户端 计算机:访问或者接收交通工具数据，或者设置或配置用户参数，或者控制交通工具的功能；或者第三方库，无论是通过与交通工具12还是呼叫中心20通信，或者与两者通信，交通工具数据或者其它信息被提供至或者来自该第三方库。计算机18还能够被用于提供互联网连接，例如DNS(Domain Name Server，域名服务器)服务，或者作为使用DHCP(Dynamic host configuration protocol，动态主机配置协议)或者其它合适的协议来分配IP地址给交通工具12的网络地址服务器。
呼叫中心20被设计以提供多种不同的系统后端功能给交通工具电子件28，并且根据在此示出的示例性实施例，呼叫中心20通常包括一个或多个交换机80、服务器82、数据库84、现场顾问86、以及VRS(Automatic voice response system，自动声音响应系统)88，它们在现有技术中全部都是已知的。这些各种呼叫中心部件优选地经有线或者无线局域网90彼此联接。交换机80能够是PBX(Private branch exchange，专用交换分机)，路由进入的信号，使得声音传输通常通过普通电话发送到现场顾问86或者使用VoIP发送到自动声音响应系统88。现场顾问电话也能够使用VoIP(Voice over Internet Phone，网络语音电话业务)，如图3中的虚线所指示。VoIP和通过交换机80的其它的数据通信经连接在交换机80和网络90之间的调制解调器(未图示)来实施。数据传输经调制解调器传递到服务器82和/或数据库84。数据库84能够存储账户信息，例如用户身份验证信息、交通工具标识符、数据图表(profile)记录、行为模式以及其它有关的用户信息。数据传输也可以由无线系统来执行，例如802.1lx,GPRS等等。此外，可使用短消息服务(SMS)发送和/或接收数据(例如，PDP)；且呼叫中心20可被配置为移动终止和/或发起，或者被配置为应用终止和/或发起。虽然所阐述的实施例已经被描述为它将会与使用现场顾问86的有人控制的呼叫中心20一起使用，但是将会明白呼叫中心可代替使用VRS 88作为自动顾问，或者VRS 88和现场顾问86的组合可以被使用。
目前，对于无人驾驶交通工具来说，要求处理设备具有高算力、高可靠性，无人驾驶佳通工具的车载环境温度高(如汽车中控台内部环境温度可达85度)，再加上自动驾驶处理器本身的高算力高功耗发热，处理器内核温度急剧升高，限制了处理器算力的进一步提升。为确保处理设备内的处理器在高算力运行下内核温度不过高，除了提升冷却系统能力外，更重要的是需要通过降功耗技术有效降低处理器的功耗。相关技术仅能够在处理器低负载量时进行功耗降低。当处理器负载量比较高的时候，为了保证处理器的处理速度，处理器的功耗仍然难以降低，因此，相关技术中处理器的芯片集成度无法进一步提升，并限制了Turbo技术在处理器中的进一步应用，导致处理器的性能无法进一步提升。不仅如此，由于处理器负载量比较高的时候，处理器运行产生大量热量，需要冷却系统对处理器进行降温，这也进一步增加了处理器的冷却成本。例如：当数据中心的能耗增加时，需要配备冷却性能比较高的冷却系统对数据中心进行降温。又例如：由于能耗较高，终端设备待机时间减少，无法长时间工作。
为了解决上述情况，本申请实施例提供一种电压调节方法。本申请实施例提供的方法中由处理器执行的步骤，也可以由应用于处理器中的芯片执行，由电源执行的步骤，也可以由应用于电源中的芯片执行，下述实施例以处理器和电源分别作为执行主体为例。
图4示出了本申请实施例提供的电压调节方法的流程示意图。如图4所示，本申请实施例提供一种电压调节方法。该方法应用于具有处理器和电源的电子设备。电源可以向处理器供电。该方法包括：
步骤101：处理器根据下一时段主频向电源发送供电调节信息。该供电调节信息包括下一时段主频的设定供电电压V，定义为处理器在一定主频频率运行时，处理器根据下一时段主频所确定的设定供电电压。一般可以采用单一DVFS技术确定。即以下一时段主频为依据，从处理器的主频和设定供电电压的对应关系中查找下一时段主频对应的设定供电电压。
上述下一时段的时长可以以分钟为单位根据实际情况取值。示例性的，下一时段的时长为10ms～50ms。例如：下一时段的时长为50ms。在实际应用中，下一时段主频是指根据当前主频预测的主频。也就是说，在步骤101之前，还应当包括步骤100：处理器根据当前负载量预测下一时段主频。
示例性的，处理器实时收集当前负载量，根据所采集的当前负载量预测下一时段负载量，根据下一时段负载量确定下一时段主频。当前负载量可以为处理器占有率、应用程序执行量或任务量等。
例如：在主板或处理器的内置存储器内存储负载量与主频的对应关系表。在负载量与主频的对应关系表中，可以设置同一主频对应一个区间的负载量。此时，根据预测的下一时段负载量在负载量与主频的对应关系表中先确定预测的下一时段负载量所在负载量区间，然后根据该负载量区间确定下一时段主频。
又例如：在主板或处理器的内置存储器内存储频切换信息。根据预测的下一时段负载量确定预设主频，根据预设主频从主频切换信息查找下一时段主频。在实际应用中，主频切换信息包括多个主频频点，从大于预设主频的一个或多个主频频点中选择最小的主频频点作为下一时段主频。例如：主频切换信息包括1.0GHz、1.5GHz、2.0GHz多个频点。当下一时段主频为1.3GHz，则说明应当将下一时段主频切换至1.5GHz。当下一时段主频为1.7GHz，则说明应当将下一时段主频切换至2.0GHz。
步骤102：电源接收处理器发送的供电调节信息。例如：处理器与电源采用PMBus总线的方式通信，则电源采用PMBus接口接收供电调节信息。
步骤103：电源根据下一时段主频的设定供电电压V和下一时段主频的设电压斜率R向该处理器提供供电电压V out。此处电压斜率是指随着电源的负载电流增加供电电压V out的下降速度，又称loadline值，以电阻的量纲为单位。该供电电压V out随着电源的负载电流的增加减小。V min≤V out≤V，V min为在下一时段主频运行时，在负载电流增大的情况下，正常运行的最低供电电压。例如：V min指当负载电流增大到最大值时，电源向处理器所提供的最低供电电压，该最低供电电压可以处理器正常运行。
为了配合供电定压调整，上述方法还包括：处理器确定下一时段主频与所述当前主频不相等的情况下，设定当前主频等于下一时段主频。处理器主频实质是外频和倍频的乘积。例如一块CPU的外频为100MHz，倍频为8.5，CPU的主频＝外频×倍频＝100MHz×8.5＝850MHz。由此可见，可以改变处理器的倍频或者外频来调节处理器主频。并且，调节处理器主频的方式，还应当结合处理器的型号决定。例如：若处理器为Intel CPU，由于Intel CPU阻止修改倍频，因此，只能采用修改外频的方式修改Intel  CPU的主频。又例如：美国超威半导体公司(Advanced Micro Devices,Inc.，缩写为AMD)的CPU可以修改倍频，但修改倍频对CPU性能的提升不如外频好。
例如：在切换处理器主频时，利用处理器内部的PLL调整时钟倍频，使得处理器的当前主频频率等于处理器内核所确定的下一时段主频频率。
在切换处理器主频时，需按照当前主频与下一时段主频的大小关系，决定处理器主频的切换时机。如图5所示，上述处理器确定下一时段主频与当前主频不相等的情况下，设定当前主频等于下一时段主频包括：
步骤100a：处理器确定下一时段主频小于当前主频，设定当前主频等于下一时段主频，执行步骤101。
步骤100b：处理器确定下一时段主频大于当前主频，执行步骤101。
当处理器确定下一时段主频大于当前主频的情况下，上述步骤103后，上述方法还包括：步骤104：处理器设定当前主频等于下一时段主频。
本申请实施例提供的方法中，下一时段主频是指根据当前主频预测的主频，而电源根据下一时段主频的设定供电电压V和下一时段主频的设定电压斜率R向处理器提供的供电电压V out与处理器的下一时段主频相适应。并且，由于负载电流具有周期性的从最小负载电流增加到最大负载电流的特点，使得现有技术中电源以恒压的方式输出负载端电压时，在负载电流增大的过程中，负载端电压被动下降。本申请实施例提供的方法主动控制电源输出的供电电压V out随着负载电流的增加而减小，使得在负载电流开始升高时电源所输出的供电电压V out主动随着负载电流的增加而下降。此时供电电压V out小于处理器在下一时段主频的设定供电电压V且大于或等于负载电流最大时处理器在下一时段主频运行时，在负载电流增大的情况下，正常运行的最低供电电压V min。由此可见，与现有技术相比，本申请实施例提供的方法中电源所提供的供电电压V out能够保证处理器正常运行的情况下，降低处理器功耗，从而提升处理器性能。而且，由于处理器的主频越高，处理器的负载量越高，因此，本申请实施例提供的方法能够保证处理器的负载量无论高低，电源均能够在负载电流增大时，以低于当前主频设定供电电压的方式向处理器供电，保证处理器在正常运行的同时，具有较低功耗。
由上可见，相对于单一DVFS技术降低处理器功耗来说，本申请实施例提供的方法能够保证处理器正常运行的情况下，不仅可以降低处理器负载轻的时候的功耗，还可以降低处理器负载重的时候的功耗，实现全域功耗降低，进而降低处理器的发热程度，并且，当处理器在负载量比较高的时候，处理器的发热程度相对比较低，因此，采用Turbo技术可以进一步提升主频频率，缓解Turbo技术因为处理器发热程度比较高所导致的应用受限问题。
作为一种可能的实现方式，基于VRM电源所输出的供电电压具有随着负载线的负载电流增大而线性下降的特性，上述供电电压V out＝V-I*R，I为电源的负载电流，由该公式可以看出，本申请实施例方法在现有技术中DVFS技术降功耗的基础上，基于电压斜率随着负载电流增加下降这一特性，利用设定电压斜率和负载电流的乘积对DVFS技术所确定的供电电压进行细调，从而实现全域降功耗。
另外，上述供电电压V out由处理器在下一时段的设定电压斜率R、下一时段的设定供电电压V和负载电流I确定。由于电压斜率是指随着电源的负载电流增加供电电 压的下降速度，因此，下一时段主频的设定电压斜率R和负载电流I的乘积实质为：电源的负载电流增大时，供电电压的主动下降量，只要保证该主动下降量大于或等于现有技术中负载电流增大情况下负载端电压被动最大下降量，就能够使得供电电压V out始终大于或等于处理器在下一时段运行时，在负载电流增大的情况下，正常运行的最低供电电压V min。
当电源包括VRM芯片、逻辑控制电路和buck变换器。VRM芯片可以根据下一时段主频的设定供电电压V确定基准电压，根据下一时段主频的设定电压斜率R确定基准电压的电压斜率。VRM芯片将基准电压和基准电压的电压斜率传输至逻辑控制电路。逻辑控制电路根据基准电压和基准电压的电压斜率输出可变电压，并经过Buck变换器进行电压变化，输出符合处理器运行要求的供电电压V out。
图6示出了电源负载瞬态过程示意图。图7示出了电源loadline特性示意图。图6中V min为处理器的最低供电电压。I max为负载电流的最大值。下面结合图6和图7分析本申请方法供电电压保证处理器在较低电压下正常运行的原理。
如图6中的直线a所示，当Loadline值＝0时，表示电源以直流电压的形式向处理器提供供电电压，且供电电压不下调，即供电电压V 0不会随着负载电流变化。图7中的曲线a为负载电流的瞬态曲线。图7中的曲线b表示电源电压在Loadline值＝0时的瞬态响应曲线。如图7中的曲线a和曲线b所示，在负载电流冲击下，由于buck变换器输出端的电容不够多，导致电源所提供的供电电压被动跌落，跌落过程持续几个μs到几十μs，然后逐渐恢复到直流电压。
具体的，结合图7中的曲线a和曲线b可以看出：当负载电流为最小值时，供电电压为V 0，并保持恒定不变。当负载电流从最小值上升到最大值的过程中，供电电压从V 0被动下降到最小值V min，然后逐渐上升。当负载电流从最大值下降到最小值的过程中时，供电电压又迅速上升到最大值V max，然后又逐渐下降，直到供电电压等于V 0。整个过程中，供电电压的最小值与最大值之间的差值可以达到V max-V min。并且，当供电电压从V 0被动下降到最小值V min时，处理器仍然能够正常运行，因此，供电电压的被动最大跌落电压ΔV max＝V 0-V min。
如图6中的斜线b所示，当Loadline值＞0时，表示直流电压在负载电流增加时主动线性下调，电压下降斜率等于Loadline值。图7中的c为电源电压在Loadline值＞0时瞬态响应曲线。如图7中的曲线c所示，在负载电流冲击下，电源主动控制供电电压下降，只要供电电压下降幅度ΔV不低于曲线b的被动最大跌落电压ΔV max，就能保证处理器正常工作。由此可见，本申请实施例提供的方法可以保证处理器正常工作。如果供电电压下降幅度ΔV小于曲线b的被动最大跌落电压的情况下，处理器无法正常工作。
由上可见，本申请实施例提供的方法中，只要保证在负载电流等于最小值时，供电电压V out等于下一时段主频的设定供电电压V，在负载电流增大的情况下，始终保持R*I小于或等于下一时段主频的设定供电电压V的被动最大跌落电压，就可以保证供电电压V out大于或等于下一时段主频的最低供电电压。
为了验证本申请实施例提供的方法可以在重负载下降低处理器功耗。下面结合DVFS技术和进行分析。
DVFS技术是一种动态电压频率调整技术，可以在一定程度上降功耗。其可以通过降低芯片的工作电压和工作频率实现功耗降低。
以芯片为例：芯片的功耗计算公式为
Figure PCTCN2020109898-appb-000001
是芯片的动态功耗，V cc·I LEAK是芯片的静态功耗，V cc为芯片的工作电压，f为芯片的工作频率，I LEAK为芯片的漏电流，α为芯片当前工作频率下电路的平均翻转率，C为负载电容的容值。应理解，芯片的功耗计算公式同样适用于处理器或具有信息处理功能的集成电路。
由芯片的功耗计算公式可以看出：芯片的动态功耗与芯片的工作电压V cc呈二次方关系，动态功耗与芯片的工作频率f呈一次线性关系，并且，当芯片的工作电压V cc和芯片的工作频率f越高，芯片的动态功耗也就越高，因此，DVFS技术通过降低芯片供电电压和工作频率可以实现功耗降低。
图8示出了DVFS技术降低功耗的机理示意图。图8中的时序a为电压时序图；图8中的时序b为主频时序图。如图8所示，在处理器的负载轻时，处理器的主频频率和供电电压都比较低。在处理器负载重时，处理器的主频频率和供电电压都比较高，且处在额定值。
图9示出了本申请方法、DVFS技术、固定电压法供电的对比图。其中，横轴是负载电流(可以视为最大负载电流)、纵轴是供电电压。图9中的直线a是采用固定电压法供电的电压变化图。由该直线a可以看出：不管处理器的主频频率如何变化，处理器的供电电压均是固定的额定供电电压。图9中的折线b是采用单一DVFS供电的电压变化图。由该折线b可以看出：在低功耗模式时，CPU的主频为F1，CPU的供电电压为V11；在额定模式时，CPU的主频为F2，CPU的供电电压为V12；在第一超频模式时，CPU的主频为F3，CPU的供电电压为V13；在第二超频模式时，CPU的主频为F4，CPU的供电电压为供电电压V14。图9中的折线c是采用本申请方法供电的电压变化图。由该折线c可以看出：在低功耗模式时，CPU的主频为F1，CPU的供电电压为V21；在额定模式时，CPU的主频为F2，CPU的供电电压为V22；在第一超频模式时，CPU的主频为F3，CPU的供电电压为V23；在第二超频模式时，CPU的主频为F4，CPU的供电电压为V24。应理解，随着功耗的增加，CPU的主频也在增加，因此，F1＜F2＜F3＜F4。
由图9可知，采用单一DVFS供电时，V11＜V12＜V13＜V14，CPU的供电电压随着主频和功耗的增加变化呈现阶梯式增高，直到等于供电电压V14。图9中的第一阴影区域P1为DVFS技术与固定电压法相比的功耗收益区。由此可见，在CPU主频较高时，DVFS技术并不能降低CPU处理器的功耗。由此可见，DVFS技术可以降低处理器负载比较轻的时候的功耗，但是DVFS技术并不能降低处理器负载比较重的时候的功耗。
采用本申请实施例方法供电时，V21＜V22＜V23＜V24，CPU的供电电压虽然随着主频和功耗的增加变化呈现阶梯式增高，但在每个功耗模式下的供电电压均小于采用DVFS技术供电的供电电压。图9中的第二阴影区域P2为本申请实施例方法与DVFS技术相比的功耗收益区。经验证：与DVFS技术相比，本申请实施例方法可以保证CPU整体功耗收益在10％以上。
由上此可见，本申请方法不管主频高低，均能够进一步降低处理器的功耗，因此，相对于DVFS技术，本申请实施例提供的方法不仅可以进一步降低处理器功耗，而且还使得处理器在低功耗模式、额定模式、超频模式(第一超频模式、第二超频模式)等多种功耗模式下在最低供电电压正常运行，实现处理器的全域降功耗，从而降低重载情况下的处理器发热的程度，使处理器能工作在更高的主频甚至超频，提升处理器性能。
作为一种可能的实现方式，上述下一时段主频的设定供电电压V可以由处理器提供，而下一时段主频的设定电压斜率R可以存在于电源中，也可以由处理器提供。
当处理器仅向电源提供下一时段主频的设定供电电压V时，在实际应用中，存储的设定电压斜率可以存储在电子设备的存储介质内，也可以存储在电源所具有的存储介质内。
示例性的，上述设定电压斜率以恒定电压斜率的形式存在在电源中。处理器无需利用处理器与电源的通信接口动态设定电源内的下一时段主频的设定电压斜率R，从而有效减小通信延时和调压延时，提高调压速度。举例说明，上述处理器根据下一时段主频向电源发送供电调节信息包括：
步骤1011A：处理器根据下一时段主频从目标对应关系中查找下一时段主频的设定供电电压V。
步骤1012A：处理器向电源发送下一时段主频的设定供电电压V。
当处理器根据下一时段主频从目标对应关系中查询到下一时段主频的设定供电电压后，通过处理器的PMBus接口发送至电源，电源的PMBus接口接收下一时段主频的设定供电电压。
上述目标对应关系可以为处理器的主频、设定供电电压和电压斜率的对应关系。当然，目标对应关系也可以为采用DVFS技术所确定的处理器的主频和设定供电电压的对应关系。
在实际应用中，上述电源中以恒定电压斜率的形式保存下一时段主频的设定电压斜率R。该恒定电压斜率为处理器在各个主频的设定供电电压所允许的电压斜率的最小值R min，R min＞0。由于R min＞0，可以保证处理器在任何负载量或主频工作时，电源始终能够以小于或等于设定供电电压的方式向处理器提供供电电压，使得处理器具有较低的能耗。并且，以恒定电压斜率为下一时段主频的设定电压斜率R时，可以控制下一时段主频设定电压斜率与负载电流的乘积，使得处理器正常运行，避免恒定电压斜率取值较大时，在负载电流增大时处理器在供电电压V out无法正常运行的情况发生。
当处理器向电源提供下一时段主频的设定供电电压V和下一时段主频的设定电压斜率R时，上述供电调节信息还包括下一时段主频的设定电压斜率R。此时，处理器根据下一时段主频向电源发送供电调节信息包括：
步骤1011B：处理器根据下一时段主频从目标对应关系中查找下一时段主频的设定供电电压V和下一时段主频的设定电压斜率R。
步骤1012B：处理器向电源发送下一时段主频的设定供电电压V和下一时段主频的设定电压斜率R。
当处理器根据下一时段主频从目标对应关系中查询到下一时段主频的设定供电电压和下一时段主频的设定电压斜率后，通过处理器的PMBus接口发送至电源，电源的PMBus接口接收下一时段主频的设定供电电压和下一时段主频的设定电压斜率。
在实际应用中，处理器以VID编码的形式将下一时段主频的设定供电电压发送至电源，以8～16bit的数据作为下一时段的设定电压斜率，将下一时段主频的设定供电电压和下一时段的设定电压斜率发送至电源。对于VID编码来说，可以直接以DVFS技术中所使用的VID编码进行传输。对于8～16bit的数据来说，电源接收到8～16bit的数据后经过简单的数据处理，可以获得下一时段的设定电压斜率。例如：电源包括VRM芯片、逻辑控制电路和Buck转换器时，VRM芯片可以根据VID编码和8～16bit的数据，确定下一时段主频的设定供电电压V和下一时段主频的设定电压斜率R，此时将下一时段主频的设定供电电压V作为基准电压，将下一时段主频的设定电压斜率R作为基准电压的电压斜率。VRM芯片将基准电压和基准电压的电压斜率发送至逻辑控制电路，逻辑控制电路根据基准电压和基准电压的电压斜率调节电压，并通过buck转换器进行电压转换，获得供电电压V out，然后利用电源的电源接口向处理器供电。
上述目标对应关系为处理器的主频、设定供电电压和设定电压斜率的对应关系。其中，所有主频的设定电压斜率可以完全不等，也可以部分相等或者全部相等。
当所有主频的设定电压斜率完全不等或部分相等时，上述处理器在每个主频的设定电压斜率为处理器在每个主频的设定供电电压所允许的电压斜率。此时，上述目标对应关系中每个主频的设定电压斜率为处理器在每个主频的设定供电电压所允许的电压斜率。电源确定的供电电压V out在满足处理器正常运行的情况下，保证处理器的功耗最优化。表1出了CPU在部分主频的设定电压斜率相等时的目标对应关系。应理解，表1所示出的功耗模式只是举例说明，在实际应用中，还有可能存在其他各种功耗模式。
表1部分主频的设定电压斜率相等的目标对应关系
Figure PCTCN2020109898-appb-000002
如表1所示，当CPU的下一时段主频为1.5GHz，则CPU所查找的的下一时段主频的设定供电电压V为1.1V，下一时段主频的设定运行电压斜率R为0.1mOhm。此时CPU通过PMBus等通信接口设置电源内的基准电压为1.0V，基准电压的电压斜率为0.1mohm。当CPU的下一时段主频为2.5GHz，则CPU所查找的下一时段主频的设定供电电压V为1.2V，下一时段主频的设定运行电压斜率R为0.2mOhm。此时CPU通过PMBus等通信接口设置电源内的基准电压为1.2V，基准电压的电压斜率为0.2mOhm。
当所有主频的设定电压斜率完全相等时，设定电压斜率需要适用于所有主频下的供电电压调节。也就是说，处理器在所有主频的设定电压斜率均等于恒定电压斜率。 此时，上述目标对应关系中所有主频对应的设定电压斜率均等于恒定电压斜率。该恒定电压斜率适用于各种主频的供电电压调节，其为处理器在各个主频的设定供电电压所允许的电压斜率的最小值R min，R min＞0。例如：从表1中选出的R min＝0.1mOhm。将表1中所有的设定电压斜率均设置为0.1mOhm时，可以得到表2所示的所有主频的设定电压斜率相等的目标对应关系。应理解，表2所示出的功耗模式只是举例说明，在实际应用中，还有可能存在其他各种功耗模式。
表2所有主频的设定电压斜率相等的目标对应关系
Figure PCTCN2020109898-appb-000003
表2中的设定电压斜率可以提前保存电子设备的在电源的寄存器内。此时，处理器所提供的供电调节信息可以仅含有下一时段主频的设定供电电压V。当然，如果设定电压斜率没有提前保存电子设备的在电源的寄存器内，那么处理器第一次向电源提供下一时段主频的设定供电电压V和下一时段主频的设定电压斜率R后，电源可以以恒定电压斜率的形式将下一时段主频的设定电压斜率R保存在电子设备的存储介质内或电源的寄存器内。例如：将下一时段主频的设定电压斜率R一次性静态配置到寄存器中。由于目标对应关系中所有主频的设定电压斜率均等于恒定电压斜率，因此，电源实质是以恒定电压斜率的形式保存目标对应关系中所有主频的设定电压斜率。
在此之后，电源需要再次调节向处理器提供的供电电压V out时，处理器只需通过通信接口动态设定电源内部的基准电压，从而减小通信延时和调压延时时，使得调压时长缩短。例如：在电源中没有保存表2中设定电压斜率的情况下，当CPU的下一时段主频为1.5GHz，CPU所确定的下一时段主频的设定供电电压为1.1V，下一时段主频的设定运行电压斜率R为0.1mOhm。CPU通过PMBus等通信接口设置电源内的基准电压为1.0V，基准电压的电压斜率为0.1mohm。在电源以恒定电压斜率的形式保存表2中设定电压斜率的情况下，CPU只需根据下一时段主频从表2所示的目标对应关系中查询到下一时段主频的设定供电电压V为1.1V，并通过PMBus等通信接口设置电源内的基准电压为1.1V，而电源则根据设定电压斜率为0.1mohm和基准电压1.1V向处理器提供供电电压V out。
又例如：在电源中没有保存表2中设定电压斜率的情况下，CPU的下一时段主频为2.5GHz，则CPU所查找到的下一时段主频的设定供电电压V为1.2V，下一时段主频的设定运行电压斜率R为0.1mOhm。CPU通过PMBus等通信接口设置电源内的基准电压为1.2V，基准电压的电压斜率为0.1mohm。在电源以恒定电压斜率的形式保存该表2中设定电压斜率的情况下，CPU只需确定的下一时段主频的设定供电电压V为1.2V，并通过PMBus等通信接口设置电源内的基准电压为1.2V，而电源则根据设定电压斜率为0.1mohm和基准电压1.2V向处理器提供供电电压V out。
需要说明的是，当上述下一时段主频的设定电压斜率R以恒定电压斜率的形式存 在于电源内，上述目标对应关系除了可以为表1和表2所示的目标对应关系，也可以为表3所示的主频和设定供电电压的对应关系。应理解，表3所示出的功耗模式只是举例说明，在实际应用中，还有可能存在其他各种功耗模式。
表3主频和设定供电电压的对应关系
Figure PCTCN2020109898-appb-000004
表3所示的主频和设定供电电压的对应关系可以直接引用现有技术中DVFS技术所使用的处理器的主频和设定供电电压的对应关系。当然，也可以由用户自己重新构建。
需要说明的是，当上述目标对应关系为处理器的主频、设定供电电压和设定电压斜率的对应关系时，不管目标对应关系中的设定电压斜率是否完全相等，其均采用如下几种方式中的一种保存在存储介质中。存储介质包括但不仅限于主板的BIOS存储器或处理器的内置存储器。
第一种保存方式：目标对应关系以处理器的主频频率、设定供电电压、设定电压斜率的对应关系或对应关系表的形式被保存在存储介质中。
第二种保存方式：目标对应关系实质包括两个子对应关系。例如：这两个子对应关系包括处理器的主频和设定供电电压的对应关系，以及处理器的主频和设定电压斜率的对应关系。又例如：这两个子对应关系包括设定电压斜率的对应关系和设定供电电压的对应关系，以及处理器的主频和处理器的设定供电电压的对应关系。再例如：这两个子对应关系包括设定电压斜率的对应关系和设定供电电压的对应关系，以及处理器的主频和处理器的设定电压斜率的对应关系。
作为一种可能的实现方式，上述目标对应关系可以在出厂前或出厂后存储在存储介质中。
在电子设备出厂后测定目标对应关系或目标对应关系形成的关系表，并存储在存储介质中。应理解，电子设备出厂后，电子设备内部的处理器的性能确定，因此，在电子设备出厂后，直接调试电子设备所获得的目标对应关系为存储介质所在电子设备内的处理器的目标对应关系。此时，目标对应关系与电子设备所包括的处理器的适配性最佳。
又例如：在电子设备出厂前，将目标对应关系或目标对应关系形成的关系表存储在存储介质中。
在实际应用中，对于不同性能的处理器来说，如果采用同样的目标对应关系，会出现目标对应关系与电子设备所包括的处理器不匹配的问题。在批量化生产的情况下，应当保证出厂前保存在存储介质中的目标对应关系具有广泛的适用性，从而使得不同处理器可以使用同一目标对应关系。例如：上述目标对应关系为基准处理器的目标对 应关系。基准处理器是多种处理器在同一主频的最低供电电压最大的处理器。此时，该基准处理器为多种处理器中性能最差的处理器。如果利用CPM电路测定多种处理器，会发现多种处理器在同一主频工作时，基准处理器对应的CPM电路的延时时间最长，振荡频率最高。此时，基准处理器的目标对应关系可以适用于多种处理器中任一处理器，因此，以基准处理器的目标对应关系为目标对应关系时，该目标对应关系具有广泛的适用性。应理解，每种处理器在给定主频工作的最低供电电压可决定处理器的性能优劣。对于性能好的处理器或芯片来说，在给定主频工作的最低供电电压比较低，对于性能比较差的处理器或芯片来说，在给定主频工作的最低供电电压比较高。不同处理器的性能差异主要由处理器的工艺或老化引入。对于同一型号的处理器来说，不同批次的处理器都有可能出现差异。
下面举例说明多种处理器的分类方式和基准处理器的选择原则，以下说明用于解释，不作为限定。
将性能比较差的处理器或芯片定义为慢片，将性能比较好的处理器或芯片定义为慢片。综合考虑极限快片(性能最好的快片)和极限慢片(性能最差的慢片)各个方面的差异(如老化差异和工艺偏差差异)，将极限快片和极限慢片之间的所有处理器分为n个处理器档位。可以从每个处理器档位内选出一个处理器作为该档位处理器。在给定主频(如0.9GHz～1.5GHz)测定n个档位处理器的最低供电电压，从其中选出最低供电电压最小的一个处理器或芯片作为基准处理器，然后测定该基准处理器的目标对应关系，并将其存储在存储介质中。
需要说明的是，慢片可以是一种，也可以是多种。当慢片为多种时，多种慢片之间的区别主要体现在工艺差异。同理，快片可以是一种，也可以是多种。当快片为多种时，多种快片之间的区别主要体现在工艺差异。
鉴于电子设备所包括的处理器与基准处理器的差异性(工艺、性能等各个方面)，如果直接使用基准处理器的目标对应关系查找下一时段主频的设定供电电压V和下一时段主频的设定电压斜率R，虽然在一定程度上仍然能够降低处理器功耗，但是所查找的结果偏差比较大，导致降低功耗的效果和可靠性均不理想。
为了保证目标对应关系与电子设备所包括的处理器具有良好的适配性比较好，应当对基准处理器进行校准。例如：采用AVS技术对基准处理器的校准。具体的，如图10所示，上述处理器根据下一时段主频从目标对应关系中查找下一时段主频的设定供电电压前，上述方法还包括：
步骤100c：处理器根据性能差异信息对目标对应关系进行校准，使得校准后的目标对应关系与电子设备所包括的处理器匹配。性能差异信息由CPM电路测定。按照性能差异信息表征方式不同，该性能差异信息可以为延时时间等延时水平或振荡频率。按照差异性来源，性能差异信息为工艺性能差异信息、工作温度性能差异信息或老化性能差异信息。例如：同一批次处理器，由于工艺差异，在给定主频下的最低供电电压不同。又例如：在给定主频下，同一处理器在不同温度范围内的最低供电电压不同，再例如：在给定主频下，同一处理器在不同老化程度的最低供电电压不同。
在不考虑温度差异的情况下，为了配合处理器对目标对应关系进行校准，存储介质还应当预存不考虑温度差异的多种处理器性能差异与最低供电电压差异的对应关系。 为了方便描述，下文将多种处理器性能差异与最低供电电压差异的对应关系简称为多种处理器差异性对应关系。
在多种处理器差异性对应关系中，每种处理器的性能差异可以用该种处理器的延时水平(如延时时间)或振荡频率表示，也可以用该种处理器与基准处理器在同一电压下的延时差值或者振荡频率差值间接表示。每种处理器性能差异对应的最低供电电压差异是指该种处理器与基准处理器在同一主频的最低供电电压差异。
在不考虑温度影响的情况下，CPM电路检测到的性能差异信息，处理器根据性能差异信息对目标对应关系进行校准，使得目标对应关系与所述处理器匹配包括：
处理器根据性能差异信息从多种处理器差异性对应关系中查找最低供电电压差异，根据最低供电电压差异对目标对应关系中每个主频对应的设定供电电压进行校准，使得校准后的目标对应关系与电子设备所包括的处理器匹配。由于性能差异信息可以反映电子设备所包括的处理器的当前状态(如性能、老化程度、工艺偏差、使用环境)等，因此，处理器根据性能差异信息从多种处理器差异性对应关系查找最低供电电压差异，可以保证处理器根据最低供电电压差异对目标对应关系所包括的每个主频的设定供电电压进行校准后，目标对应关系与电子设备所包括的处理器的匹配性更好。
在考虑温度影响的情况下，为了配合处理器对目标对应关系进行校准，存储介质还应当预存多种处理器在多个温度档位的性能差异与最低供电电压差异的对应关系。为了方便描述，下文将多种处理器在多个温度档位的性能差异与最低供电电压差异的对应关系简称为多种处理器在多种温度档位的差异性对应关系。
在考虑温度影响的情况下，CPM电路检测到的性能差异信息，处理器根据性能差异信息对目标对应关系进行校准，使得目标对应关系与电子设备所包括的处理器匹配包括：
处理器根据当前温度从多种处理器在多个温度档位的性能差异与最低供电电压差异的对应关系中查找多种处理器在当前温度所在温度档位的性能差异与最低供电电压差异的对应关系，根据性能差异信息从多种处理器在当前温度所在温度档位的性能差异与最低供电电压差异的对应关系中查找当前性能差异信息匹配的最低供电电压差异，根据性能差异信息匹配的最低供电电压差异对目标对应关系中每个主频对应的设定供电电压进行校准，使得校准后的所述目标对应关系与电子设备所包括的处理器匹配，以将当前温度对目标对应关系的影响考虑进来，从而进一步提高目标对应关系与电子设备所包括的处理器的匹配性。
多种处理器在多个温度档位的差异性对应关系可以按照操作温度分为n个温度档位的多种处理器差异性对应关系，每个温度档位的多种处理器差异性对应关系包括在该温度档位下多种处理器差异性对应关系。当然，多种处理器的目标对应关系还可以按照处理器档位不同分为n个处理器档位的多种处理器差异性对应关系；每个处理器档位的多种处理器差异性对应关系包括该处理器档位的处理器在多个温度档位的差异性对应关系。
对于同一处理器来说，操作温度不同，该处理器内置的CPM电路所测定的性能差异信息就会有所不同。如果不考虑温度对性能差异信息的影响，所查找出的最低供电电压差异偏差准确度不是很高。例如：当存储介质保存多种处理器在25℃测定的差异 性对应关系和基准处理器的目标对应关系，在电子设备出厂后上电时，处理器内置的CPM电路在45℃测定性能差异信息，根据45℃测定性能差异信息从多种处理器在25℃测定的差异性对应关系查找出的最低供电电压差异的偏差比较大。
如果考虑温度对性能差异信息的影响，所查找出的最低供电电压差异偏差准确度比较高。例如：当存储介质保存多种处理器在多个温度档位(包括45℃)的差异性对应关系和基准处理器的目标对应关系，在电子设备出厂后上电时，处理器内置的CPM电路在45℃测定性能差异信息，使得相对于不考虑温度对性能差异信息的影响的方案来说，根据45℃测定性能差异信息从多种处理器在多个温度档位(包括45℃)查找出的最低供电电压差异的偏差比较小。
需要说明的是，不管是考虑温度差异的情况，还是不考虑温度差异的情况，如果考虑主频对最低供电电压差异的影响，所查找出的最低供电电压差异实质包括处理器在多个主频的最低供电电压差异，这些主频与目标对应关系所包括的主频一一对应。此时，根据处理器在多个主频的最低供电电压差异对目标对应关系中多个主频的设定供电电压进行校准。如果不考虑主频对最低供电电压差异的影响，所查找出的最低供电电压差异实质包括处理器在某个主频的最低供电电压差异，此时，根据处理器在某个主频的最低供电电压差异对目标对应关系中所有主频的设定供电电压进行校准。下文涉及到对目标对应关系的校准均可参考此处是否考虑主频的描述。
当存储介质中以对应关系表的形式保存差异性对应关系时，将处理器根据性能差异信息对目标对应关系进行校准的方法定义为查表法。下面以处理器内置CPM电路的情况下说明查表法的具体过程。
第一步，出厂前，以基准处理器为测试对象，测试基准处理器的目标对应关系表。将基准处理器的目标对应关系保存在存储介质中。
第二步，出厂前，将操作温度范围分成多个温度档位，从每个温度档位选出一个温度，确定多种处理器在对应温度档位的差异性对应关系表。并将多个温度档位的目标对应关系保存在存储介质中。
例如：操作温度范围为0℃～100℃。将0℃～100℃以20℃为间隔分成0℃～20℃、21℃～40℃、41℃～60℃、61℃～80℃、81℃～100℃五个温度档位，从0℃～20℃选出15℃，从21℃～40℃选出28℃，从41℃～60℃选出50℃，从61℃～80℃选出75℃，从81℃～100℃选出90℃。然后分别在15℃、28℃、50℃、75℃和90℃测试多种处理器和基准处理器内置的CPM电路的延时时间以及最低供电电压。根据多种处理器和基准处理器内置的CPM电路的延时时间的差值和最低供电电压差异，获得多种处理器在五个温度档位的差异性对应关系表。表4示出了三种处理器在50℃所在温度档位的差异性对应关系。
表4三种处理器在50℃所在温度档位的差异性对应关系
处理器种类 延时差值/ns 最低供电电压差异/V
第一种处理器 ΔX1 Δv1
第二种处理器 ΔX2 Δv2
第三种处理器 ΔX3 Δv3
ΔX1为第一种处理器与基准处理器内置的CPM电路延时差值，ΔX 2为第二种处理器与基准处理器内置的CPM电路延时差值，ΔX3为第三种处理器与基准处理器内 置的CPM电路延时差值，Δv1为第一种处理器与基准处理器的最低供电电压差异。Δv2为第二种处理器与基准处理器的最低供电电压差异，Δv3为第三种处理器与基准处理器的最低供电电压差异。
第三步：出厂后，在电子设备使用的情况下，CPM电路测定当前延时时间，处理器根据当前温度从多个温度档位下多种处理器差异性对应关系表中查找多种处理器在当前温度所在温度档位的差异性对应关系表。根据处理器内置的CPM电路测得的当前延时时间和基准处理器内置的CPM电路测得的当前延时时间，确定当前延时差值。根据当前延时差值从多种处理器在当前温度所在温度档位的差异性对应关系表中查找与当前延时差值接近(延时差值接近程度可以根据实际情况设定)或相同的延时时间对应的最低供电电压差异，根据所查找的最低供电电压差异对基准处理器的目标对应关系中每个主频的设定供电电压进行校准。
举例说明：当前操作温度为45℃，CPM电路在45℃测得延时时间，根据处理器内置的CPM电路在45℃测得的延时时间与基准处理器内置的CPM电路在50℃的延时时间获得当前延时差值。由于45℃所在温度档位为41℃～60℃，因此，根据当前延时差值从表4中找出与当前延时差值接近(延时差值接近程度可以根据实际情况设定)或相同的延时差值，然后根据所查找出的延时差值从表4中查找最低供电电压差异。若基准处理器的目标对应关系中某个主频的设定供电电压为V，所确定的最低供电电压差异为Δv3，则校准后的设定供电电压等于V+Δv3。
当存储介质中以数学函数表达式的形式保存差异性对应关系时，将处理器根据性能差异信息对目标对应关系进行校准的方法定义为数学推演法。下面以处理器内置CPM电路的情况下说明数学推演法的具体过程。
第一步，出厂前，以基准处理器为测试对象，测试基准处理器的目标对应关系表。将基准处理器的目标对应关系保存在存储介质中。
第二步，出厂前，将操作温度范围分成多个温度档位，从每个温度档位选出一个温度，确定该温度下多种处理器延时差值与最低供电电压差异，并对其进行拟合，确定该温度下多种处理器延时差值与最低供电电压差异的函数关系式。该函数关系式为Δv＝kΔX+a。k为系数、a是固定常数，ΔX为延时差值，Δv为最低工作电压差异。并将该数学函数表达式保存在存储介质中。
例如：操作温度范围为0℃～100℃。将0℃～100℃以20℃为间隔分成0℃～20℃、21℃～40℃、41℃～60℃、61℃～80℃、81℃～100℃五个温度档位，从0℃～20℃选出15℃，从21℃～40℃选出28℃，从41℃～60℃选出50℃，从61℃～80℃选出75℃，从81℃～100℃选出90℃。然后分别在15℃、28℃、50℃、75℃和90℃拟合出五个数学函数关系式，五个数学函数式分别对应五个温度档位的数学函数关系式。
第三步，出厂后，在电子设备使用的情况下，CPM电路测定当前延时时间，处理器根据当前温度所在温度档位选出数学函数关系式，根据处理器内置的CPM电路在当前延时时间与基准处理器内置的CPM电路在当前温度的延时时间，获得当前延时差值，将当前延时差值代入所选出的数学函数关系式，计算出最低供电电压差异，然后根据最低供电电压差异对基准处理器的目标对应关系进行校准。
举例说明：当前操作温度为45℃，CPM电路内置的CPM电路在45℃测得当前延 时时间，根据处理器内置的CPM电路在45℃测得的当前延时时间与基准处理器内置的CPM电路在45℃的延时时间获得当前延时差值，将当前延时差值代入50℃拟合出的50℃所在温度档位的数学函数关系式，获得最低供电电压差异。若基准处理器的目标对应关系中某个主频的设定供电电压为V，所确定的最低供电电压差异为Δv3，则校准后的设定供电电压等于V+Δv3。
需要说明的是，不考虑温度影响的情况下，所确定的多种处理器差异性对应关系可以看做是在一个温度档位下的多种处理器差异性对应关系，只是该温度档位的范围比较宽。例如：当考虑温度影响的情况下，0℃～100℃的操作温度分为五个温度档位，分别为0℃～20℃、21℃～40℃、41℃～60℃、61℃～80℃、81℃～100℃。如果忽略温度影响，则可以认为多种处理器差异性对应关系是在0℃～100℃的温度档位测定的多种处理器差异性对应关系。
作为一种可能的实现方式，在电子设备出厂前写入多个目标对应关系，出厂后经过调试确定最终的目标对应关系。此时存储介质中存储有前文所述基准处理器在多个温度档位的目标对应关系或多种处理器的目标对应关系。
当存储介质中存储有前文所述基准处理器在多个温度档位的目标对应关系时，如图10所示，上述处理器根据下一时段主频向电源发送供电调节信息前，上述方法还包括：
步骤100d：处理器根据当前温度从基准处理器在多个温度档位的目标对应关系查找目标对应关系。该目标对应关系为基准处理器在当前温度所在温度档位的目标对应关系。此时，所确定的基准处理器的目标对应关系考虑了温度对目标对应关系的影响，使得校准后的目标对应关系与电子设备所包括的处理器的匹配性更好。
下面以前文所述查表法为例，描述上述基准处理器的目标对应关系的确定和校准过程。
第一步，出厂前，基准处理器的操作温度范围为0℃～100℃。将0℃～100℃以20℃为间隔分成0℃～20℃、21℃～40℃、41℃～60℃、61℃～80℃、81℃～100℃五个温度档位，从0℃～20℃选出15℃，从21℃～40℃选出28℃，从41℃～60℃选出50℃，从61℃～80℃选出75℃，从81℃～100℃选出90℃。然后分别测试基准处理器在15℃、28℃、50℃、75℃和90℃的目标对应关系，获得处理器在五个温度档位的目标对应关系。
第二步，出厂前，分别在15℃、28℃、50℃、75℃和90℃测试多种处理器和基准处理器内置的CPM电路的延时时间以及最低供电电压。根据多种处理器和基准处理器内置的CPM电路的延时时间的差值和最低供电电压差异，获得多种处理器在15℃、28℃、50℃、75℃和90℃的差异性对应关系表，即多种处理器在多个温度档位的差异性对应关系。
第三步：出厂后，在电子设备使用的情况下，当前操作温度为45℃，处理器根据当前温度从基准处理器在五个温度档位的目标对应关系表查找出基准处理器在45℃所在温度档位的目标对应关系(即多种处理器在50℃的目标对应关系)。处理器根据处理器内置的CPM电路在45℃测得的延时时间与基准处理器内置的CPM电路在45℃的延时时间获得当前延时差值，然后从表4中找出与当前延时差值接近或相同的延时差值，根据所查找出的延时差值从表4中查找最低供电电压差异。若所查出的目标对 应关系中某个主频的设定供电电压为V，所确定的最低供电电压差异为Δv3，则校准后的设定供电电压等于V+Δv3。
当存储介质中存储有多种处理器的目标对应关系时，在不考虑温度影响的情况下，电子设备上电，CPM电路检测到性能差异信息。如图11所示，上述处理器根据下一时段主频从目标对应关系中查找下一时段主频的设定供电电压前，上述方法还包括：
步骤100e：处理器根据性能差异信息从多种处理器的目标对应关系查找与电子设备包括的处理器匹配的目标对应关系。
当不考虑温度的情况下，每种处理器中内置有CPM电路。为了配合处理器查找与电子设备包括的处理器匹配的目标对应关系，可以在出厂前，利用每种处理器内置的CPM电路测定多种处理器的振荡频率或延迟时间等性能差异信息，并建立多种处理器的性能差异信息与多种处理器的目标对应关系联系。将多种处理器的性能差异信息和多种处理器的目标对应关系保存在存储介质中。示例性的，每种处理器的性能差异信息为该种处理器的延时时间。电子设备在出厂上电时，处理器内置的CPM电路根据延时时间确定目标对应关系。
在考虑温度的情况下，如图12所示，上述处理器根据下一时段主频向所述电源发送供电调节信息前，上述方法还包括：
步骤100f：处理器根据当前温度从多种处理器在多个温度档位的目标对应关系查找多种处理器在当前温度所在温度档位的目标对应关系；根据性能差异信息从多种处理器在当前温度所在温度档位的目标对应关系中查找与电子设备包括的处理器匹配的目标对应关系。
上述多种处理器在多个温度档位的目标对应关系可以按照操作温度分为n个温度档位目标对应关系。每个温度档位目标对应关系包括在该温度档位多种处理器的目标对应关系。当然，多种处理器的目标对应关系还可以按照处理器档位不同分为n个处理器档位目标对应关系。每个处理器档位目标对应关系包括同一档位的处理器在n个温度档位的目标对应关系。应理解，同一档位的处理器在n个温度档位的目标对应关系是指：从该处理器档位所有处理器中选取一个处理器作为测试对象，并测试该处理器在n个温度档位的目标对应关系。并且，当n等于1时，多种处理器的目标对应关系只有一个温度档位，此时可以认为不考虑温度的情况下的多种处理器的目标对应关系。当n为大于或等于2的整数，多种处理器的目标对应关系有两个或两个以上的温度档位。并且，n越大，温度档位越多，处理器最终所确定的目标对应关系也就越接近真实的目标对应关系。
为了配合根据性能差异信息从多种处理器的目标对应关系查找与电子设备包括的处理器匹配的目标对应关系，存储介质中还应当预存多种处理器在多个温度档位的性能差异信息。并且，多种处理器在多个温度档位的性能差异信息应当与多种处理器在多个温度档位的目标对应关系具有相互依赖关系，然后将多种处理器在多个温度档位的性能差异信息与多种处理器在多个温度档位的目标对应关系保存在存储介质中。
在一种情况下，多种处理器在多个温度档位的性能差异信息可以按照温度档位进行分类，获得与多个温度档位一一对应的多类性能差异信息。每类性能差异信息包括多种处理器在该温度档位的性能差异信息(如延时时间或者振荡频率)。
在另一种情况下，多种处理器在多个温度档位的性能差异信息可以按照处理器档位进行分类，获得与多种处理器档位一一对应的多类性能差异信息。每类性能差异信息包括同一档位处理器在多个温度档位的性能差异信息(如延时时间或者振荡频率)。
示例性的，处理器的操作温度范围为0℃～100℃。将0℃～100℃以20℃为间隔分成0℃～20℃、21℃～40℃、41℃～60℃、61℃～80℃、81℃～100℃五个温度档位，从0℃～20℃选出15℃，从21℃～40℃选出28℃，从41℃～60℃选出50℃，从61℃～80℃选出75℃，从81℃～100℃选出90℃。然后分别在15℃、28℃、50℃、75℃和90℃下测定多种处理器的目标对应关系和多种处理器的延时时间，获得多种处理器在五个温度档位的目标对应关系和多种处理器在五个温度档位的延时时间，并建立多种处理器在每个温度档位的目标对应关系与多种处理器在每个温度档位的延时时间依赖关系。在电子设备上电时，处理器内置的CPM电路在45℃检测到当前延时时间。从多种处理器在45℃所在温度档位的延时时间(即多种处理器在50℃的延时时间)中查找接近或相同的延时时间，并根据查找到的延时时间确定对应的目标对应关系。
作为一种可能的实现方式，不管上述存储介质所存储的目标对应关系在何时存入存储介质，也不管存储介质内所存储的目标对应关系包括多少种处理器的目标存储关系，每个目标对应关系中的设定供电电压和设定电压斜率按照如下方式确定，可以保证电源向处理器提供的供电电压V out能够可靠稳定的降低处理器功耗。
上述目标对应关系中设定供电电压可以按照如下关系确定：处理器在每个主频的设定供电电压为V (i)，即目标对应关系中每个主频的设定供电电压为V (i)。
V (i)＝V min(i)+ΔV (i)，V min(i)为处理器在每个主频运行时，在负载电流增大的情况下，正常运行的最低供电电压，ΔV (i)为处理器在每个主频的供电电压裕量。ΔV (i)＝20mV～60mV。例如：40mV或50mV，当然也可以根据实际情况设定。
上文处理器在每个主频的设定供电电压所允许的电压斜率可以按照如下关系确定：处理器在每个主频的设定供电电压的允许电压斜率为R (i)。R (i)＝R max(i)-ΔR (i)。R max(i)为处理器在每个主频的设定供电电压的最大电压斜率，ΔR (i)为处理器在每个主频的电压斜率裕量。其中，ΔR (i)＝0.03mOhm～0.08mOhm。例如：0.05mOhm或0.07mOhm。应理解，对于所有主频的设定电压斜率相等的目标对应关系来说，确定在每个主频的设定供电电压的允许电压斜率R (i)后，还应当从各个主频的设定供电电压的允许电压斜率R (i)选出最小值，并保证该最小值大于0。将该最小值作为多个主频可以共用的设定电压斜率，即前文所述恒定电压斜率。
下面举例说明本申请实施例提供的方法所涉及的目标对应关系的确定过程，以下举例仅用于说明，不在于限定。
第一步：处理器的主频和设定供电电压对应关系产生过程：在CPU出厂前，使用CPU评估板对CPU的主频和最低供电电压关系进行实测。测试时，将电源的电压斜率设成0Ohm，测试样本覆盖典型片(典型片又称TT片)、工艺偏差片(又称Corner片)，测试温度覆盖CPU宣称规格的环境温度(即操作温度)，测得一组处理器的主频和最低供电电压曲线。最低供电电压应当能够保证处理器能够正常运行的最小供电电压。同时，对每个主频的最低供电电压增加供电电压裕量，获得处理器的主频的设定供电电压，以防止在负载电流增大时，供电电压无法保证处理器正常运行。供电电 压裕量是指允许最低供电电压出现偏差的容许电压偏差值。图13示出了处理器的主频和供电电压曲线。X轴为主频，Y轴为供电电压。其中，图13中的曲线a为处理器的主频和最低供电电压曲线，图13中的b为处理器的主频和设定供电电压曲线。图13中的曲线a所包括的最低运行电压增加50mV裕量，可获得图13中的曲线b。
由图13中的曲线b可以看出：图13的曲线b覆盖低功耗模式、额定模式、两种超频模式等多种典型模式下的频率、设定供电电压。前文示出的表3表示了图13中的曲线b在不同模式的主频和设定供电电压的对应关系。如表3所示，当CPU工作在低功耗模式时，CPU主频较低为0.5GHz，设定供电电压为0.9V；当CPU工作在额定模式时，CPU主频为1.5GHz，设定供电电压为1.1V；当CPU工作在第一超频模式时，CPU主频超过额定频率，为2.5GHz，设定供电电压1.2V；当CPU工作在第二超频模式时，CPU主频进一步提高到3.0GHz，设定供电电压为1.3V。
需要说明的是，也可以基于现有DVFS技术所使用的处理器的主频和设定供电电压对应关系表形成本申请方法的处理器的主频和设定供电电压对应关系。
第二步，处理器的主频、设定供电电压和设定电压斜率对应关系产生过程：按照CPU每种模式下主频和电压的设置，测定每种模式下能够保证处理器正常工作的最大电压斜率，并保留一定的电压斜率裕量，电压斜率裕量是指允许最大电压斜率的容许误差。
例如：图14示出额定模式下的设定供电电压的电压斜率图。图14中的斜线a为额定模式下的设定供电电压的最大电压斜率图。当处理器在额定模式下，设定供电电压为1.1V。在负载电流升高时，控制设定供电电压按照不同的电压斜率主动下降到最小值，从中选出保证处理器正常运行的最大电压斜率，并在此基础上减去一定的电压斜率裕量，获得额定模式下的设定供电电压的设定电压斜率，即图14中的斜线b。
应当理解的是，设定电压斜率不能太大，否则电源在负载电流增大时，处理器将会出现无法工作的问题。设定电压斜率也不能太小，否则处理器功耗降低效果不明显。基于此，每种模式或者说每种主频的设定电压斜率应当经过反复测试确定，无法用统一的标准设定。至于低功耗模式、第一超频模式和第二超频模式的设定电压斜率的确定过程参照额定模式的设定电压斜率确定过程。
图15示出了不同功耗模式下的电压loadline曲线。其中，X坐标为负载电流，Y坐标为设定供电定压。其中，图15中的曲线a为低功耗模式的电压斜率曲线，图15中的曲线b为额定模式的电压斜率曲线，图15中的曲线c为第一超频模式的电压斜率曲线。图15中的曲线d为第二超频模式的电压斜率曲线。根据图13中的曲线b与图15中的曲线a～曲线d，可以确定表1所示的目标对应关系。
需要说明的是，当上述目标对应关系中所有主频对应的设定电压斜率均等于恒定电压斜率时，在第二步后，还应当从所有主频对应的设定电压斜率中找出最小的设定电压斜率，并确保该设定电压斜率＞0。以该设定电压斜率为所有主频共用的电压斜率，即恒定电压斜率。例如：表1中低功耗模式、额定模式、第一超频模式和第二超频模式中，不等于0的最小的设定电压斜率为0.1V，因此，以0.1V作为低功耗模式、额定模式、第一超频模式和第二超频模式共用的设定电压斜率。
上述主要从各个网元之间交互的角度对本申请实施例提供的方案进行了介绍。可 以理解的是，各个网元，例如处理器和电源，为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，本申请实施例能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请实施例的范围。
在采用实体硬件的情况下，图16示出了本申请实施例提供一种设备。该设备应用于通信设备或终端设备，但不仅限于此。如图16所示，该设备200包括处理器201和电源202，处理器201用于支持电子设备执行如上述实施例中由处理器执行的步骤101。电源202用于支持电子设备执行如上述实施例中由电源执行的步骤102和步骤103。
在一种可能的实现方式中，如图16所示，上述处理器201还用于执行如上述实施例中由处理器执行的步骤100。
在一种可能的实现方式中，如图16所示，上述处理器201还用于支持电子设备执行如上述实施例中由处理器执行的步骤100a。
上述处理器201还用于支持电子设备执行如上述实施例中由处理器执行的步骤100b和步骤104。
在一种可能的实现方式中，如图16所示，上述设备200还包括存储介质203，用于存储计算机程序和目标对应关系。上述电源202以恒定电压斜率形式保存有设定电压斜率。上述处理器201具体用于执行如上述实施例中由处理器执行的步骤1011A和1012A。
在另一种可能的实现方式中，如图16所示，上述设备200还包括存储介质203，用于存储计算机程序和目标对应关系。上述处理器201具体用于执行如上述实施例中由处理器执行的步骤1011B和1012B。
在一种可能的实现方式中，如图16所示，上述设备200还包括存储介质203，用于存储计算机程序和基准处理器的目标对应关系，上述处理器201还用于支持电子设备执行如上述实施例中由处理器执行的步骤100c。
为了配合处理器执行相应的步骤，如图16所示，存储介质203还用于存储多种处理器差异性对应关系，或多种处理器在多个温度档位的差异性对应关系。
在另一种可能的实现方式中，如图16所示，上述设备200还包括存储介质203，用于存储计算机程序和基准处理器在多个温度档位的目标对应关系，上述处理器201还用于支持电子设备执行如上述实施例中由处理器执行的步骤100d。为了配合处理器执行相应的步骤，存储介质203还用于存储多种处理器在多个温度档位的差异性对应关系。
在又一种可能的实现方式中，如图16所示，上述设备200还包括存储介质203，用于存储计算机程序和多种处理器的目标对应关系，上述处理器201还用于支持电子设备执行如上述实施例中由处理器执行的步骤100e。为了配合处理器执行相应的步骤，存储介质203还用于存储多种处理器性能差异信息。
在又一种可能的实现方式中，如图16所示，上述设备200还包括存储介质203，用于存储计算机程序和多种处理器在多个温度档位的目标对应关系，上述处理器201还用于支持电子设备执行如上述实施例中由处理器执行的步骤100f。为了配合处理器执行相应的步骤，存储介质203还用于存储多种处理器在多个温度档位的性能差异信息。
本申请实施例可以根据上述方法示例对处理器和电源进行功能模块的划分，例如，可以对应各个功能划分各个功能模块，也可以将两个或两个以上的功能集成在一个处理模块中。上述集成的模块既可以采用硬件的形式实现，也可以采用软件功能模块的形式实现。需要说明的是，本申请实施例中对模块的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
在采用对应各个功能划分各个功能模块的情况下，图17示出了上述实施例中所涉及的一种电压调节装置的结构示意图。该电压调节装置为处理器或应用于处理器的芯片。如图17所示，该电压调节装置300包括：发送模块303，用于支持电压调节装置执行上述实施例中由处理器执行的步骤101。
在一种可能的实现方式中，如图17所示，上述电压调节装置300还包括：预测模块301，用于支持电压调节装置执行上述实施例中由处理器执行的步骤100。
在一种可能的实现方式中，如图17所示，上述电压调节装置300还包括频率合成模块304，用于支持电压调节装置执行上述实施例中由处理器执行的步骤100a，或者步骤100b和步骤104。
在一种可能的实现方式中，如图17所示，上述电压调节装置300还包括选择模块302和存储模块305。存储模块305用于存储目标对应关系。上述选择模块302还用于支持电压调节装置执行上述实施例中由处理器执行的步骤1011A，上述发送模块303还用于支持电压调节装置执行上述实施例中由处理器执行的步骤1012A。
在另一种可能的实现方式中，如图17所示，上述电压调节装置300还包括选择模块302和存储模块305。存储模块305用于存储目标对应关系。上述选择模块302还用于支持电压调节装置执行上述实施例中由处理器执行的步骤1011B，上述发送模块303还用于支持电压调节装置执行上述实施例中由处理器执行的步骤1012B。
在一种可能的实现方式中，如图17所示，上述电压调节装置400还包括关系校正模块306。
在一种示例中，如图17所示，存储模块305用于存储基准处理器的目标对应关系。关系校正模块306用于支持电压调节装置执行上述实施例中由处理器执行的步骤100c。
为了配合处理器执行相应的步骤，存储模块305还用于存储多种处理器差异性对应关系，或多种处理器在多个温度档位的差异性对应关系。
在另一种可能的实现方式中，如图17所示，存储模块305用于存储基准处理器在多个温度档位的目标对应关系和多种处理器在多个温度档位的差异性对应关系。关系校正模块306用于支持电压调节装置执行上述实施例中由处理器执行的步骤100d。
在又一种示例中，如图17所示，存储模块305用于存储多种处理器的目标对应关系和多种处理器性能差异信息。关系校正模块306用于支持电压调节装置执行上述实施例中由处理器执行的步骤100e。
在又一种示例中，如图17所示，存储模块305用于存储多种处理器的目标对应关系和多种处理器在多个温度档位的性能差异信息。关系校正模块306用于支持电压调节装置执行上述实施例中由处理器执行的步骤100f。
在采用对应各个功能划分各个功能模块的情况下，图18示出了上述实施例中所涉及的另一种电压调节装置的结构示意图。该电压调节装置为电源或应用于电源的芯片。如图18所示，该电压调节装置包括接收模块401和供电模块402。接收模块401用于支持该电压调节装置执行上述实施例中由电源执行的步骤102。供电模块402用于支持该电压调节装置执行上述实施例中由电源执行的步骤103。
在一种可能的实现方式中，如图18所示，当上述电压调节信息包括下一时段主频的设定供电电压V和下一时段的设定电压斜率R，上述电压调节装置400还包括电压识别模块404和斜率识别单模块405。电压识别模块404用于支持电压调节装置执行上述实施例中由电源执行识别下一时段主频的设定供电电压V，从而确定基准电压。斜率识别单模块405用于支持该电压调节装置执行上述实施例中由电源执行下一时段的设定电压斜率R，从而确定基准电压的电压斜率。
在一种可能的实现方式中，如图18所示，上述电压调节装置400还包括存储介质403，该存储介质403用于保存以恒定电压斜率存在的设定电压斜率。上述电压调节装置400还包括电压识别模块404，用于支持电压调节装置执行上述实施例中由电源执行识别下一时段主频的设定供电电压V，从而确定基准电压。
上述方法实施例涉及的各步骤的所有相关内容均可以援引到对应功能模块的功能描述，在此不再赘述。
在采用集成单元的情况下，图19示出了本申请实施例提供一种电压调节装置。如图19所示，该电压调节装置500可以包括：通信单元501。可选的，该电压调节装置500还可以包括处理单元502。
在一种示例中，如图19所示，上述电压调节装置500为处理器，或者为应用于处理器中的芯片。在这种情况下，处理单元502用于支持该电压调节装置执行上述实施例中由处理器执行的步骤100。通信单元501，用于支持该电压调节装置执行上述实施例中由处理器执行步骤101。
在一种可能的实现方式中，如图19所示，上述处理单元502还用于支持该电压调节装置执行上述实施例中由处理器执行的步骤100a或步骤100b和步骤104。
在一种可能的实现方式中，如图19所示，上述电压调节装置还包括存储单元503，用于存储目标对应关系。上述处理单元502还用于支持电压调节装置执行上述实施例中由处理器执行的步骤1011A。上述通信单元501还用于支持电压调节装置执行上述实施例中由处理器执行的步骤1012A。
在另一种可能的实现方式中，如图19所示，上述电压调节装置500还包括存储单元503，用于存储目标对应关系。上述处理单元502还用于支持电压调节装置执行上述实施例中由处理器执行的步骤1011B，上述通信单元501还用于支持电压调节装置执行上述实施例中由处理器执行的步骤1012B。
在一种可能的实现方式中，如图19所示，存储单元503用于存储基准处理器的目标对应关系。处理单元502还用于支持电压调节装置执行上述实施例中由处理器执行 的步骤100c。
为了配合处理单元502执行相应的步骤，存储单元503还用于存储多种处理器差异性对应关系，或者多种处理器在多个温度档位的差异性对应关系。
在另一种可能的实现方式中，如图19所示，存储单元503用于存储基准处理器在多个温度档位的目标对应关系。处理单元502还用于支持电压调节装置执行上述实施例中由处理器执行的步骤100d。为了配合处理单元502执行相应的步骤，存储单元503还用于存储多种处理器在多个温度档位的差异性对应关系。
在又一种可能的实现方式中，如图19所示，存储单元503用于存储多种处理器的目标对应关系。处理单元502还用于支持电压调节装置执行上述实施例中由处理器执行的步骤100e。为了配合处理单元502执行相应的步骤，存储单元503还用于存储多种处理器性能差异信息。
在又一种可能的实现方式中，如图19所示，存储单元503用于存储多种处理器在多个温度档位的目标对应关系。处理单元502还用于支持电压调节装置执行上述实施例中由处理器执行的步骤100f。为了配合处理单元502执行相应的步骤，存储单元503还用于存储多种处理器在多个温度档位的性能差异信息。
在另一种示例中，如图19所示，该电压调节装置500为电源，或者为应用于电源中的芯片。在这种情况下，通信单元501，用于支持该电压调节装置执行上述实施例中由电源执行的步骤102。处理单元502用于支持该电压调节装置执行上述实施例中由电源执行的步骤103。
在一种可能的实现方式，如图19所示，上述电压调节装置500还可以包括存储单元503，用于存储以恒定电压斜率存在的设定电压斜率等数据和电压调节装置可执行的程序代码。
其中，处理单元502可以是处理器或控制器，例如可以是中央处理器(Central Processing Unit，CPU)，通用处理器，数字信号处理器(Digital Signal Processor，DSP)，专用集成电路(Application-Specific Integrated Circuit，ASIC)，现场可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。其可以实现或执行结合本发明公开内容所描述的各种示例性的逻辑方框，模块和电路。所述处理单元也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，DSP和微处理器的组合等等。通信单元可以是收发器、收发电路或通信接口等。存储单元可以是存储器。
以上通信单元可以是该装置的一种通信接口，用于从其它装置接收信号。例如，当该装置以芯片的方式实现时，该通信单元是该芯片用于从其它芯片或装置接收信号或发送信号的通信接口。
当图19所示的处理单元502为包括VRM芯片、逻辑控制电路和Buck变换器时，通信单元501包括通信接口和电源接口，存储单元503为存储器时，本发明实施例所涉及的电压调节装置500可以为图2中所示的电源。
当图19所示的处理单元502为处理器，通信单元501为通信接口，存储单元503为存储器时，本发明实施例所涉及的电压调节装置500可以为图2中所示的处理器。
图20示出一种芯片的结构示意图。如图20所示，该芯片600包括一个或两个以 上(包括两个)处理器601和通信接口602。
可选的，如图20所示，该芯片还包括存储器603。存储器603可以包括只读存储器和随机存取存储器，并向处理器602提供操作指令和数据。存储器603的一部分还可以包括非易失性随机存取存储器(non-volatile random access memory，NVRAM)。
在一些实施方式中，存储器603存储了如下的元素，执行模块或者数据结构，或者他们的子集，或者他们的扩展集。
在本申请实施例中，如图20所示，处理器601通过调用存储器603存储的目标对应关系，执行相应的操作。
一种可能的实现方式中，处理器和电源所用的芯片的结构类似，不同的装置可以使用不同的芯片以实现各自的功能。
如图20所示，处理器601控制本申请实施例中电子设备包括的处理器和电源中任一个的处理操作，处理器601还可以称为中央处理单元(central processing unit，CPU)。
如图20所示，存储器603包括只读存储器和随机存取存储器，并向处理器603提供指令和数据。存储器603的一部分还可以包括NVRAM。例如应用中存储器、通信接口602以及存储器603通过总线系统604耦合在一起，其中总线系统604除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图20中将各种总线都标为总线系统604。
一种可能的实现方式中，如图20所示，通信接口602用于支持上述芯片执行上述实施例中的处理器、电源的接收和发送的步骤。处理器601用于支持上述芯片执行上述实施例中的处理器、电源的处理的步骤。
一方面，提供一种计算机可读存储介质，计算机可读存储介质中存储有指令，当指令被运行时，实现如图4、图5和图10-图12中任一图示的处理器的功能。
另一方面，提供一种计算机可读存储介质，计算机可读存储介质中存储有指令，当指令被运行时，实现如图4、图5和图10-图12中任一图示的电源的功能。
一方面，提供一种包括指令的计算机程序产品，计算机程序产品中包括指令，当指令被运行时，实现如图4、图5和图10-图12中任一图示的处理器的功能。
又一方面，提供一种包括指令的计算机程序产品，计算机程序产品中包括指令，当指令被运行时，实现如图4、图5和图10-图12中任一图示的电源的功能。
一方面，提供一种芯片，该芯片应用于处理器中，芯片包括至少一个处理器和通信接口，通信接口和至少一个处理器耦合，处理器用于运行指令，以实现如图4、图5和图10-图12中任一图示的处理器的功能。
又一方面，提供一种芯片，该芯片应用于电源中，芯片包括至少一个处理器和通信接口，通信接口和至少一个处理器耦合，处理器用于运行指令，以实现如图4、图5和图10-图12中任一图示的电源的功能。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请实施例的范围。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统、装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请实施例所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请实施例各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。
以上，仅为本申请实施例的具体实施方式，但本申请实施例的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请实施例揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (30)

  1. 一种电压调节方法，其特征在于，应用于具有处理器和电源的电子设备，该方法包括：
    所述处理器根据下一时段主频向所述电源发送供电调节信息；所述供电调节信息包括所述下一时段主频的设定供电电压V，所述下一时段主频是指根据当前主频预测的主频；
    所述电源根据所述下一时段主频的设定供电电压V和所述下一时段主频的设定电压斜率R向所述处理器提供供电电压V out；
    其中，所述电压斜率是指随着所述电源的负载电流增加所述供电电压V out的下降速度；所述供电电压V out随着所述负载电流的增加减小；V min≤V out≤V，V min为所述处理器在所述下一时段主频运行时，在所述负载电流增大的情况下，正常运行的最低供电电压。
  2. 根据权利要求1所述的方法，其特征在于，所述供电电压V out＝V-I*R，I为所述电源的负载电流。
  3. 根据权利要求1或2所述的方法，其特征在于，所述处理器根据下一时段主频向所述电源发送所述处理器在下一时段主频的设定供电电压V包括：
    所述处理器根据所述下一时段主频从目标对应关系中查找下一时段主频的设定供电电压V，并向所述电源发送所述下一时段主频的设定供电电压V；
    其中，所述目标对应关系为所述处理器的主频、设定供电电压和设定电压斜率的对应关系或所述处理器的主频和设定供电电压的对应关系。
  4. 根据权利要求1～3任一项所述的方法，其特征在于，所述下一时段主频的设定电压斜率R以恒定电压斜率的形式存在在所述电源内，所述恒定电压斜率为所述处理器在各个主频的设定供电电压所允许的电压斜率的最小值R min，R min＞0。
  5. 根据权利要求1或2所述的方法，其特征在于，所述供电调节信息包括还包括所述下一时段主频的设定电压斜率R。
  6. 根据权利要求5所述的方法，其特征在于，所述处理器根据下一时段主频向所述电源发送供电调节信息包括：
    所述处理器根据所述下一时段主频从目标对应关系中查找所述下一时段主频的设定供电电压V和所述下一时段主频的设定电压斜率R，并向所述电源发送所述下一时段主频的设定供电电压V和所述下一时段主频的设定电压斜率R；
    其中，所述目标对应关系为所述处理器的主频、设定供电电压和设定电压斜率的对应关系。
  7. 根据权利要求3或6所述的方法，其特征在于，所述处理器根据下一时段主频向所述电源发送供电调节信息前，所述方法还包括：
    所述处理器根据性能差异信息对所述目标对应关系进行校准，使得校准后的所述目标对应关系与所述电子设备所包括的处理器匹配，其中，所述性能差异信息包括延时时间或振荡频率。
  8. 根据权利要求7所述的方法，其特征在于，所述处理器根据性能差异信息对所 述目标对应关系进行校准，使得校准后的所述目标对应关系与所述处理器匹配包括：
    所述处理器根据所述性能差异信息从多种处理器性能差异与最低供电电压差异的对应关系中查找所述性能差异信息匹配的最低供电电压差异；根据所述性能差异信息匹配的最低供电电压差异对所述目标对应关系中每个主频的设定供电电压进行校准，使得校准后的所述目标对应关系与所述电子设备所包括的处理器匹配；或，
    所述处理器根据当前温度从多种处理器在多个温度档位的性能差异与最低供电电压差异的对应关系中查找多种处理器在所述当前温度所在温度档位的性能差异与最低供电电压差异的对应关系；根据所述性能差异信息从所述当前温度所在温度档位的多种处理器性能差异与最低供电电压差异的对应关系中查找所述性能差异信息匹配的最低供电电压差异；根据所述性能差异信息匹配的最低供电电压差异对所述目标对应关系中每个主频的设定供电电压进行校准，使得校准后的所述目标对应关系与所述电子设备所包括的处理器匹配。
  9. 根据权利要求3、6～8任一项所述的方法，其特征在于，所述目标对应关系为基准处理器的目标对应关系，所述基准处理器是多种处理器在同一主频的最低供电电压最大的处理器。
  10. 根据权利要求3、6～9任一项所述的方法，其特征在于，所述处理器根据下一时段主频向所述电源发送供电调节信息前，所述方法还包括：
    所述处理器根据当前温度从基准处理器在多个温度档位的目标对应关系中查找目标对应关系；所述目标对应关系为所述基准处理器在所述当前温度所在温度档位的目标对应关系，所述基准处理器是多种处理器在同一主频的最低供电电压最大的处理器。
  11. 根据权利要求3或6所述的方法，其特征在于，所述处理器根据下一时段主频向所述电源发送供电调节信息前，所述方法还包括：
    所述处理器根据性能差异信息从多种处理器的目标对应关系中查找与所述电子设备包括的处理器匹配的目标对应关系；所述性能差异信息包括延时时间或振荡频率；或，
    所述处理器根据当前温度从多种处理器在多个温度档位的目标对应关系查找所述多种处理器在所述当前温度所在温度档位的目标对应关系；根据性能差异信息从所述多种处理器在所述当前温度所在温度档位的目标对应关系中查找与所述电子设备包括的处理器匹配的目标对应关系；所述性能差异信息包括延时时间或振荡频率。
  12. 根据权利要求1～11任一项所述的方法，其特征在于，所述处理器在每个所述主频的设定电压斜率为所述处理器在每个所述主频的设定供电电压所允许的电压斜率；或，
    所述处理器在所有主频的设定电压斜率均等于恒定电压斜率；所述恒定电压斜率为所述处理器在各个主频的设定供电电压所允许的电压斜率的最小值R min，R min＞0。
  13. 根据权利要求4或12所述的方法，其特征在于，所述处理器在每个所述主频的设定供电电压所允许的电压斜率为R (i)，R (i)＝R max(i)-ΔR (i)，R max(i)为所述处理器在每个所述主频的设定供电电压的最大电压斜率，ΔR (i)为所述处理器在每个所述主频的电压斜率裕量。
  14. 根据权利要求1～13任一项所述的方法，其特征在于，所述处理器在每个所述 主频的设定供电电压为V (i)，V (i)＝V min(i)+ΔV (i)，V min(i)为所述处理器在每个所述主频运行时，在所述负载电流增大的情况下，正常运行的最低供电电压，ΔV (i)为所述处理器在每个所述主频的供电电压裕量。
  15. 根据权利要求1～14任一项所述的方法，其特征在于，所述方法还包括：
    所述处理器确定所述下一时段主频与所述当前主频不相等的情况下，设定所述当前主频等于所述下一时段主频。
  16. 一种电子设备，其特征在于，包括：
    处理器，用于根据下一时段主频向电源发送供电调节信息；所述供电调节信息包括所述下一时段主频的设定供电电压V，所述下一时段主频是指根据当前主频预测的主频；
    电源，用于根据所述下一时段主频的设定供电电压V和所述下一时段主频的设定电压斜率R向所述处理器提供供电电压V out；
    其中，所述电压斜率是指随着所述电源的负载电流增加所述供电电压V out的下降速度；所述供电电压V out随着所述负载电流的增加减小；V min≤V out≤V，V min为所述处理器在所述下一时段主频运行时，在所述负载电流增大的情况下，正常运行的最低供电电压。
  17. 根据权利要求16所述的设备，其特征在于，所述供电电压V out＝V-I*R，I为所述电源的负载电流。
  18. 根据权利要求16或17所述的设备，其特征在于，所述处理器具体用于根据所述下一时段主频从目标对应关系中查找所述下一时段主频的设定供电电压V，并向所述电源发送所述下一时段的设定供电电压V；
    其中，所述目标对应关系为所述处理器的主频、设定供电电压和设定电压斜率的对应关系或所述处理器的主频和设定供电电压的对应关系。
  19. 根据权利要求16～18任一项所述的设备，其特征在于，所述下一时段主频的设定电压斜率R以恒定电压斜率的形式存在在所述电源中，所述恒定电压斜率为所述处理器在各个主频的设定供电电压所允许电压斜率的最小值R min，R min＞0。
  20. 根据权利要求16或17所述的设备，其特征在于，所述供电调节信息包括下一时段主频的设定电压斜率R。
  21. 根据权利要求20所述的设备，其特征在于，所述处理器具体用于根据所述下一时段主频从目标对应关系中查找所述下一时段主频的设定供电电压V和所述下一时段主频的设定电压斜率R，并向所述电源发送所述下一时段主频的设定供电电压V和所述下一时段主频的设定电压斜率R；
    其中，所述目标对应关系为所述处理器的主频、设定供电电压和设定电压斜率的对应关系。
  22. 根据权利要求18或21所述的设备，其特征在于，所述处理器还用于根据下一时段主频向电源发送供电调节信息前，根据性能差异信息对所述目标对应关系进行校准，使得校准后的所述目标对应关系与所述电子设备所包括的处理器匹配，其中，所述性能差异信息包括延时时间或振荡频率。
  23. 根据权利要求22所述的设备，其特征在于，所述处理器具体用于根据所述性 能差异信息从多种处理器性能差异与最低供电电压差异的对应关系中查找所述性能差异信息匹配的最低供电电压差异；根据所述性能差异信息匹配的最低供电电压差异对所述目标对应关系中每个主频的设定供电电压进行校准，使得校准后的所述目标对应关系与所述电子设备所包括的处理器匹配；或，
    所述处理器具体用于根据当前温度从多种处理器在多个温度档位的性能差异与最低供电电压差异的对应关系中查找多种处理器在所述当前温度所在温度档位的性能差异与最低供电电压差异的对应关系；根据所述性能差异信息从所述当前温度所在温度档位的多种处理器性能差异与最低供电电压差异的对应关系中查找所述性能差异信息匹配的最低供电电压差异；根据所述性能差异信息匹配的最低供电电压差异对所述目标对应关系中每个主频的设定供电电压进行校准，使得校准后的所述目标对应关系与所述电子设备所包括的处理器匹配。
  24. 根据权利要求18、21～23任一项所述的设备，其特征在于，所述目标对应关系为基准处理器的目标对应关系，所述基准处理器是多种处理器在同一主频的最低供电电压最大的处理器。
  25. 根据权利要求18、21～24任一项所述的设备，其特征在于，所述处理器还用于根据下一时段主频向电源发送供电调节信息前，根据当前温度从基准处理器在多个温度档位的目标对应关系中查找目标对应关系；所述目标对应关系为所述基准处理器在所述当前温度所在温度档位的目标对应关系，所述基准处理器是多种处理器在同一主频的最低供电电压最大的处理器。
  26. 根据权利要求18或21所述的设备，其特征在于，所述处理器还用于根据下一时段主频向电源发送供电调节信息前，根据性能差异信息从多种处理器的目标对应关系中查找与所述电子设备包括的处理器匹配的目标对应关系；所述性能差异信息包括延时时间或振荡频率；或，
    所述处理器还用于根据下一时段主频向电源发送供电调节信息前，根据当前温度从多种处理器在多个温度档位的目标对应关系中查找所述多种处理器在所述当前温度所在温度档位的目标对应关系；根据性能差异信息从所述多种处理器在所述当前温度所在温度档位的目标对应关系查找与所述电子设备包括的处理器匹配的目标对应关系；所述性能差异信息包括延时时间或振荡频率。
  27. 根据权利要求16～26任一项所述的设备，其特征在于，所述处理器在每个所述主频的设定电压斜率为所述处理器在每个所述主频的设定供电电压所允许的电压斜率；或，
    所述处理器在所有主频的设定电压斜率均等于恒定电压斜率；所述恒定电压斜率为所述处理器在各个主频的设定供电电压所允许的电压斜率的最小值R min，R min＞0。
  28. 根据权利要求19或27所述的设备，其特征在于，所述处理器在每个所述主频的设定供电电压所允许的电压斜率为R (i)，R (i)＝R max(i)-ΔR (i)，R max(i)为所述处理器在每个所述主频的最低供电电压的最大电压斜率，ΔR (i)为所述处理器在每个所述主频的电压斜率裕量。
  29. 根据权利要求16～27任一项所述的设备，其特征在于，所述处理器在每个所述主频的设定供电电压为V (i)，V (i)＝V min(i)+ΔV (i)，V min(i)为所述处理器在每个所述主频 运行时，在所述负载电流增大的情况下，正常运行的最低供电电压，ΔV (i)为所述处理器在每个所述主频的供电电压裕量。
  30. 根据权利要求16～29任一项所述的设备，其特征在于，所述处理器还用于确定所述下一时段主频与所述当前主频不相等的情况下，设定所述当前主频等于所述下一时段主频。
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