WO2021128653A1 - 逆导型igbt的元胞结构及逆导型igbt - Google Patents

逆导型igbt的元胞结构及逆导型igbt Download PDF

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Publication number
WO2021128653A1
WO2021128653A1 PCT/CN2020/084136 CN2020084136W WO2021128653A1 WO 2021128653 A1 WO2021128653 A1 WO 2021128653A1 CN 2020084136 W CN2020084136 W CN 2020084136W WO 2021128653 A1 WO2021128653 A1 WO 2021128653A1
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Prior art keywords
conductivity type
source region
gate
region
reverse
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English (en)
French (fr)
Inventor
罗海辉
肖强
朱利恒
覃荣震
刘鹏飞
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Zhuzhou CRRC Times Semiconductor Co Ltd
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Zhuzhou CRRC Times Semiconductor Co Ltd
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Priority to EP20907435.0A priority Critical patent/EP4084084A4/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/491—Vertical IGBTs having both emitter contacts and collector contacts in the same substrate side
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H10D62/142—Anode regions of thyristors or collector regions of gated bipolar-mode devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/141—Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs
    • H10D62/145—Emitter regions of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/232—Emitter electrodes for IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations

Definitions

  • the present disclosure relates to the technical field of semiconductor devices, and in particular to a cell structure of a reverse-conducting IGBT and a reverse-conducting IGBT.
  • Insulated Gate Bipolar Transistor is a composite fully controlled voltage-driven power semiconductor device composed of BJT (Bipolar Transistor) and MOSFET (Metal Oxide Semiconductor Field Effect Transistor), which has become The most extensive semiconductor device in high voltage, high current, and high frequency power electronics applications.
  • BJT Bipolar Transistor
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • FRD anti-parallel fast recovery diode
  • IGBT and FRD can be integrated in the same chip, namely reverse conducting IGBT (Reverse Conducting IGBT, RC-IGBT).
  • the cell structure of the traditional reverse-conducting IGBT integrates the functions of the IGBT and FRD devices.
  • the reverse-conducting IGBT works in the FRD mode, the change of the gate voltage has an effect on the FRD. Performance has a strong impact.
  • the gate voltage of the reverse-conducting IGBT is less than or equal to 0V, the reverse-conducting IGBT does not form an inverse carrier channel, the anode of the FRD is not short-circuited, the anode injection efficiency of the FRD is high, and the forward voltage drop of the FRD is low .
  • the present disclosure provides a cell structure of a reverse-conducting IGBT and a reverse-conducting IGBT.
  • the present disclosure provides a cell structure of a reverse-conducting IGBT, including:
  • a second conductivity type well region located in the center of the cell structure and arranged in the surface of the drift layer;
  • the source region of the second conductivity type is higher than the source region of the second conductivity type, so that part of the bottom of the source region of the first conductivity type covers part of the surface on both sides of the source region of the second conductivity type, and makes the source of the first conductivity type
  • the side surface of the region and the surface of the second conductivity type source region not covered by the first conductivity type source region together form a main trench;
  • a gate structure arranged on both sides of the main trench and in contact with the well region and the first conductivity type source region;
  • An emitter metal layer arranged above the gate structure and in the main trench;
  • the gate in the gate structure between the gate in the gate structure and the source region of the first conductivity type, between the gate in the gate structure and part of the conductive layer on the sidewall of the main trench, the gate In the structure, the gate, the first conductivity type source region, and a part of the conductive layer on the sidewall of the main trench are isolated from the emitter metal layer by an interlayer dielectric layer. A part of the conductive layer on the bottom is in contact with the emitter metal layer, and is used to derive the current of the first conductivity type source region.
  • the surface of the second conductivity type source region is lower than the surface of the first conductivity type source region by more than 0.3um.
  • the conductive layer is a metal layer or a silicon alloy layer.
  • it further includes:
  • a storage region of the first conductivity type disposed in the drift layer and under the well region.
  • the doping concentration of the storage region is one to two orders of magnitude higher than the doping concentration of the substrate.
  • it further includes:
  • a lifetime control region arranged in the well region and located below the second conductivity type source region.
  • the gate structure includes a gate insulating layer located above the drift layer and simultaneously in contact with the surfaces of the first conductivity type source region, the well region, and the drift layer , And a gate located above the gate insulating layer.
  • the gate structure includes a gate trench disposed in the drift layer and adjacent to the well region, and a gate disposed on the sidewall and bottom of the gate trench.
  • it further includes:
  • a second conductivity type collector area located under the substrate and a first conductivity type short-circuit area adjacent to the collector area;
  • a collector metal layer located under the current collecting area and the short-circuit area and forming an electrical connection with the current collecting area and the short-circuit area.
  • the cell structure is a honeycomb cell structure or a striped cell structure.
  • the present disclosure provides a reverse-conducting IGBT device, which includes several cell structures of the reverse-conducting IGBT as described in any one of the first aspect.
  • the present disclosure provides a cell structure of a reverse-conducting IGBT and a reverse-conducting IGBT.
  • the source region of the first conductivity type and the emitter metal layer are connected through the conductive layer, and the source region of the first conductivity type and the source of the second conductivity type are eliminated.
  • the coupling relationship between the regions, and the current of the source region of the first conductivity type is derived through the conductive layer, so that the reverse-conducting IGBT works in FRD mode and the gate voltage of the reverse-conducting IGBT is greater than or equal to the threshold voltage.
  • the short-circuit effect of the source region reduces the influence of the FRD anode injection, thereby reducing the influence of the gate voltage on the FRD forward voltage drop, so that the FRD can obtain a lower forward voltage drop.
  • FIG. 1 is a schematic cross-sectional structure diagram of a cell structure of a conventional planar gate structure of a reverse conducting IGBT;
  • FIG. 2 is a schematic cross-sectional structure diagram of a cell structure of a conventional reverse-conducting IGBT with a trench gate structure;
  • FIG. 3 is a schematic cross-sectional structure diagram of a cell structure of a reverse-conducting IGBT with a planar gate structure according to an exemplary embodiment of the present disclosure
  • FIG. 4 is a schematic cross-sectional structure diagram of a cell structure of another reverse-conducting IGBT with a planar gate structure according to an exemplary embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional structure diagram of a cell structure of another reverse-conducting IGBT with a planar gate structure according to an exemplary embodiment of the present disclosure
  • FIG. 6 is a schematic cross-sectional structure diagram of a cell structure of a reverse-conducting IGBT with a trench gate structure according to an exemplary embodiment of the present disclosure
  • FIG. 7 is a schematic cross-sectional structure diagram of a cell structure of another reverse-conducting IGBT with a trench gate structure according to an exemplary embodiment of the present disclosure
  • FIG. 8 is a schematic cross-sectional structure diagram of a cell structure of another reverse-conducting IGBT with a trench gate structure according to an exemplary embodiment of the present disclosure.
  • first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections are not Should be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or section discussed below may be represented as a second element, component, region, layer or section.
  • spatial relationship terms such as “above”, “above”, “below”, “below”, etc., may be used here for the convenience of description to describe The relationship between one element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship term is intended to also include different orientations of the device in use and operation. For example, if the figure is attached The device in is turned over, and then elements or features described as “below other elements” will be oriented “on” the other elements or features. Therefore, the exemplary terms “under” and “under” “Can include both top and bottom orientations. The device can be otherwise oriented (rotated by 90 degrees or other orientations) and the space descriptors used here are interpreted accordingly.
  • the embodiments of the present disclosure are described here with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the present disclosure. In this way, changes from the shown shape due to, for example, manufacturing techniques and/or tolerances can be expected. Therefore, the embodiments of the present disclosure should not be limited to the specific shape of the area shown here, but include shape deviations due to, for example, preparation. For example, an implanted area shown as a rectangle usually has rounded or curved features and/or an implanted concentration gradient at its edges, rather than a binary change from an implanted area to a non-implanted area. Likewise, the buried region formed by the implantation can result in some implantation in the region between the buried region and the surface through which the implantation proceeds. Therefore, the regions shown in the figure are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the present disclosure.
  • an embodiment of the present disclosure provides a cell structure 300 of a reverse conducting IGBT with a planar gate structure, including a substrate 301, a drift layer 302, a well region 303, a second conductivity type source region 304, and a first Conductive type source region 305, gate insulating layer 306, gate 307, conductive layer 308, interlayer dielectric layer 309, emitter metal layer 310, collector region 311, short circuit region 312, collector metal layer 313.
  • the substrate 301 is a silicon-based substrate of the first conductivity type.
  • the drift layer 302 is a drift layer of the first conductivity type and is located above the substrate 301.
  • the thickness of the drift layer 302 is selected according to the voltage withstand capability of the device.
  • the well region 303 is a well region of the second conductivity type, located in the center of the cell structure and disposed on the surface of the drift layer 302, and the surface of the well region 303 is flush with the surface of the drift layer 302.
  • the source region of the second conductivity type 304 is a source region of the second conductivity type, and is disposed in the surface of the well region 303.
  • the source region of the first conductivity type 305 is a source region of the first conductivity type.
  • the source region of the first conductivity type 305 is disposed in the surface of the well region 303 and located on both sides of the source region 304 of the second conductivity type.
  • the first conductivity type source region 305 is higher than the second conductivity type source region 304, so that the bottom portion of the first conductivity type source region 305 covers part of the surface on both sides of the second conductivity type source region 304, and makes the first conductivity type source region
  • the side surface of 305 and the surface of the second conductivity type source region 304 not covered by the first conductivity type source region 305 together form a main trench (not marked in the figure).
  • the above-mentioned main trench is formed by forming the first conductivity type source region 305 and the second conductivity type source region 304 in the surface of the well region 303, and then is formed by etching between the two first conductivity type source regions 305 Part of the second conductivity type source region 304 is obtained. After etching, the second conductivity type source region 304 is only left under the first conductivity type source region 305 and below the main trench.
  • the surface of the second conductivity type source region 304 is lower than the surface of the first conductivity type source region 305 by more than 0.3 um. This structure can increase the carrier injection level in the vertical direction.
  • the gate insulating layer 306 and the gate 307 constitute a gate structure.
  • the gate structure is a planar gate structure.
  • the gate insulating layer 306 is located on both sides of the main trench and above the drift layer 302.
  • the gate insulating layer 306 is in contact with the surface of the first conductivity type source region 305, the well region 303 and the drift layer 302 at the same time, but not with the conductive layer 308 contact.
  • the gate insulating layer 306 isolates the gate 307 from the first conductivity type source region 305, the well region 303, and the drift layer 302.
  • the gate 307 is a polysilicon gate and is disposed above the gate insulating layer 306.
  • the conductive layer 308 is disposed on the bottom and sidewalls of the above-mentioned main trench, and even extends above the first conductivity type source region 305.
  • the thickness of the conductive layer 308 is 50 nm to 200 nm, and the conductive layer 308 is a metal layer or a silicon alloy layer.
  • the interlayer dielectric layer 309 is located above the gate 307 and simultaneously covers a part of the conductive layer located above the first conductivity type source region 305 and located on the sidewall of the main trench.
  • the interlayer dielectric layer 309 isolates the gate 307, the source region of the first conductivity type 305, and a part of the conductive layer above the source region of the first conductivity type 305 and on the sidewalls of the main trench from the emitter metal layer 310, and also separates the gate
  • the pole 307 is separated from the first conductivity type source region 305 and the conductive layer 308.
  • the emitter metal layer 310 is located above the interlayer dielectric layer 309 and fills the above-mentioned main trench.
  • the emitter metal layer 310 is in contact with a part of the conductive layer located at the bottom of the main trench, and is used to derive the short-circuit current of the source region 305 of the first conductivity type.
  • the emitter metal layer 310 may be a metal with low contact resistivity, such as aluminum.
  • This structure enables the reverse-conducting IGBT to work in the FRD mode and the gate voltage of the reverse-conducting IGBT is greater than or equal to the threshold voltage.
  • the impact of the injection of the conductive type source region 304 is reduced, and the impact of the short-circuit effect of the first conductive type source region 305 on the FRD anode injection is reduced, thereby achieving the purpose of reducing the FRD forward voltage drop.
  • the collector region 311 is a collector region of the second conductivity type, and the collector region 311 is located under the substrate 301.
  • the short-circuit area 312 is a short-circuit area of the second conductivity type, and the short-circuit area 312 is located under the substrate 301 and adjacent to the collector area 311.
  • the collector metal layer 313 is located under the collector region 311 and the short-circuit region 312 and forms an electrical connection with the collector region 311 and the short-circuit region 312.
  • the cell structure 300 may further include a storage area 314.
  • the storage area 314 is a carrier storage area of the first conductivity type disposed in the drift layer 302 and located under the well area 303.
  • the doping concentration of the storage region 314 is higher than the doping concentration of the substrate 301 by one to two orders of magnitude.
  • the storage area 314 can reduce the turn-on voltage drop of the IGBT.
  • the cell structure 300 may further include a lifetime control region 315, which is disposed in the well region 303 and below the second conductivity type source region 304, and the lifetime control region 315 is a low lifetime control region.
  • the life span of few births is lower than in other nearby areas, generally three to four orders of magnitude lower.
  • the lifetime control region 315 is obtained by implanting other types of impurities in the well region to reduce the minority carrier lifetime, which can reduce the switching loss of the FRD. This cell structure can simultaneously obtain lower FRD forward voltage drop and lower FRD switching loss.
  • the shape of the cell structure 300 may be a honeycomb shape, a short strip shape (cell length ⁇ 200um) or a long strip shape.
  • the first conductivity type is opposite to the second conductivity type.
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is N-type.
  • the present disclosure provides a cell structure of a reverse-conducting IGBT with a planar gate structure.
  • the first conductivity type source region 305 and the emitter metal layer 310 are connected through the conductive layer 308, and the first conductivity type source region 305 and the second conductivity type are eliminated.
  • the coupling relationship between the conductivity type source regions 304, and the current of the first conductivity type source region 305 is derived through the conductive layer 308, so that the reverse-conducting IGBT works in the FRD mode and the gate voltage of the reverse-conducting IGBT is greater than or equal to the threshold voltage At this time, the short-circuit effect of the first conductivity type source region 305 has a reduced influence on the FRD anode injection, thereby reducing the influence of the gate voltage on the FRD forward voltage drop, so that the FRD can obtain a lower forward voltage drop.
  • an embodiment of the present disclosure provides a cell structure 400 of a reverse-conducting IGBT with a trench gate structure, which includes a substrate 401, a drift layer 402, a gate insulating layer 403, a gate 404, and a well region 405. ,
  • the substrate 401 is a silicon-based substrate of the first conductivity type.
  • the drift layer 402 is a drift layer of the first conductivity type, and is located above the substrate 401.
  • the thickness of the drift layer 402 is selected according to the voltage withstand capability of the device.
  • the gate trench (not marked in the figure), the gate insulating layer 403 and the gate 404 constitute a gate structure.
  • the gate structure is a trench gate structure.
  • the gate trenches are arranged on both sides of the cell structure and located in the drift layer 402 and adjacent to the well region 405.
  • the depth of the gate trench is greater than the depth of the well region 405.
  • the gate insulating layer 403 is disposed on the sidewall and bottom of the gate trench to isolate the gate 404 from the source region 407 of the first conductivity type, the well region 405 and the drift layer 402.
  • the gate 404 is a polysilicon gate, which is filled in the above-mentioned gate trench.
  • the well region 405 is a well region of the second conductivity type, which is disposed in the surface of the drift layer 402 and is located at the center of the cell structure and between the two gate trenches.
  • the surface of the well region 405 is flush with the surface of the drift layer 402, and both ends of the well region 405 are respectively in contact with the gate trenches on both sides, that is, in contact with the gate insulating layers on both sides.
  • the source region of the second conductivity type 406 is a source region of the second conductivity type, which is disposed in the surface of the well region 405, and the surface of the source region of the second conductivity type 406 is flush with the surface of the drift layer 402.
  • the source region of the first conductivity type 407 is a source region of the first conductivity type, and the source region of the first conductivity type 407 is disposed in the surface of the well region 405 and located on both sides of the source region 406 of the second conductivity type.
  • the first conductivity type source region 407 is higher than the second conductivity type source region 406, so that the bottom portion of the first conductivity type source region 407 covers part of the surface on both sides of the second conductivity type source region 406, and the first conductivity type source region
  • the side surface of 407 and the surface of the second conductivity type source region 406 not covered by the first conductivity type source region 407 together form a main trench (not marked in the figure).
  • the above-mentioned main trench is formed by forming the first conductivity type source region 407 and the second conductivity type source region 406 in the surface of the well region 405, and is formed by etching between the two first conductivity type source regions 407. Part of the source region of the second conductivity type 406 is obtained. After etching, the source region of the second conductivity type 406 is only left under the source region of the first conductivity type 407 and below the main trench.
  • the surface of the second conductivity type source region 406 is lower than the surface of the first conductivity type source region 407 by more than 0.3 um. This structure can increase the carrier injection level in the vertical direction.
  • the conductive layer 408 is disposed on the bottom and sidewalls of the main trench and even extends above the first conductivity type source region 407.
  • the thickness of the conductive layer 408 is 50 nm to 200 nm, and the conductive layer 408 is a metal layer or a silicon alloy layer.
  • the interlayer dielectric layer 409 is located above the gate 404 and simultaneously covers the first conductivity type source region 407, a portion of the conductive layer located above the first conductivity type source region 407 and the sidewall of the main trench.
  • the interlayer dielectric layer 409 isolates the gate 404, the first conductivity type source region 407, and a part of the conductive layer above the first conductivity type source region 407 and on the sidewall of the main trench from the emitter metal layer 410, and also separates the gate
  • the pole 404 is separated from the first conductivity type source region 407 and the conductive layer 408.
  • the emitter metal layer 410 is located above the interlayer dielectric layer 409 and fills the above-mentioned trench.
  • the emitter metal layer 410 is in contact with the conductive layer located at the bottom of the main trench, and is used for deriving the short-circuit current of the source region 407 of the first conductivity type.
  • the emitter metal layer 410 may be a metal with low contact resistivity such as aluminum.
  • This structure enables the reverse-conducting IGBT to work in the FRD mode and the gate voltage of the reverse-conducting IGBT is greater than or equal to the threshold voltage.
  • the impact of the injection of the conductive type source region 406 is reduced, and the impact of the short-circuit effect of the first conductive type source region 407 on the FRD anode injection is reduced, thereby achieving the purpose of reducing the FRD forward voltage drop.
  • the collector region 411 is a collector region of the second conductivity type, and the collector region 411 is located under the substrate 401.
  • the short-circuit area 412 is a short-circuit area of the second conductivity type, and the short-circuit area 412 is located under the substrate 401 and adjacent to the collector area 411.
  • the collector metal layer 413 is located under the collector region 411 and the short-circuit region 412 and forms an electrical connection with the collector region 411 and the short-circuit region 412.
  • the cell structure 400 may further include a storage area 414, which is a carrier storage area of the first conductivity type, which is disposed in the drift layer 402 and located under the well area 405.
  • the doping concentration of the storage region 414 is higher than the doping concentration of the substrate 401 by one to two orders of magnitude.
  • the storage area 414 can reduce the turn-on voltage drop of the IGBT.
  • the cell structure 400 may further include a lifetime control region 415, which is disposed in the well region 405 and below the second conductivity type source region 406, and the lifetime control region 415 is a low lifetime control region.
  • the life span of few births is lower than in other nearby areas, generally three to four orders of magnitude lower.
  • the lifetime control region 415 is obtained by implanting other types of impurities in the well region to reduce the minority carrier lifetime, which can reduce the switching loss of the FRD. This cell structure can simultaneously obtain lower FRD forward voltage drop and lower FRD switching loss.
  • the shape of the cell structure 400 may be a honeycomb shape, a short strip shape (cell length ⁇ 200um) or a long strip shape.
  • the first conductivity type is opposite to the second conductivity type.
  • the second conductivity type is P-type
  • the first conductivity type is P-type
  • the second conductivity type is N-type.
  • the present disclosure provides a cell structure of a reverse conducting IGBT with a planar gate structure.
  • the first conductivity type source region 407 and the emitter metal layer 410 are connected through the conductive layer 408, thereby eliminating the first conductivity type source region 407 and the second conductivity type.
  • the coupling relationship between the conductivity type source regions 406, and the current of the first conductivity type source region 407 is derived through the conductive layer 408, so that the reverse-conducting IGBT works in the FRD mode and the gate voltage of the reverse-conducting IGBT is greater than or equal to the threshold voltage At this time, the short-circuit effect of the first conductivity type source region 407 has a reduced influence on the FRD anode injection, thereby reducing the influence of the gate voltage on the FRD forward voltage drop, so that the FRD can obtain a lower forward voltage drop.

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

提供一种逆导型IGBT的元胞结构(300)及逆导型IGBT。该元胞结构(300)包括位于元胞结构中心的第二导电类型阱区(303)；设置于所述阱区表面内的第一导电类型源区(305)和第二导电类型源区(304)；其中，所述第一导电类型源区(305)位于所述第二导电类型源区(304)两侧并且部分底部覆盖所述第二导电类型源区(304)两侧的部分表面，并使得所述第一导电类型源区(305)的侧面与所述第二导电类型源区(304)未被所述第一导电类型源区(305)覆盖的表面一起合围成一主沟槽；覆盖在所述主沟槽的侧壁和底部上的导电层(308)；设置在栅结构上和所述主沟槽中的发射极金属层(310)；其中，所述主沟槽的底部上的部分导电层(308)与所述发射极金属层(310)接触。这种结构可以降低栅极电压对逆导型IGBT内FRD正向导通压降的影响，使FRD获得更低的正向压降。

Description

逆导型IGBT的元胞结构及逆导型IGBT
本公开要求享有2019年12月26日提交的名称为“逆导型IGBT的元胞结构及逆导型IGBT”的中国专利申请201911366131.0的优先权，其全部内容通过引用并入本文中。
技术领域
本公开涉及半导体器件技术领域，具体涉及一种逆导型IGBT的元胞结构及逆导型IGBT。
背景技术
绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，IGBT)，是由BJT(双极性晶体管)和MOSFET(金属氧化物半导体场效应晶体管)组成的复合全控型电压驱动式功率半导体器件，已经成为大电压，大电流，高频电力电子应用中最广泛的半导体器件。通常在IGBT的应用中，需要反并联相应规格的快速恢复二极管(Fast Recovery Diode,FRD)作为关断时的电流泄放回路，来保护IGBT芯片。为降低成本以及减少封装带来的各种寄生效应的考虑，可将IGBT与FRD集成在同一个芯片中，即逆导型IGBT(Reverse Conducting IGBT,RC-IGBT)。
传统的逆导型IGBT的元胞结构，如图1和图2所示，集成了IGBT与FRD两种器件的功能，当逆导型IGBT工作在FRD模式时，栅极电压的变化对FRD的性能产生强烈的影响。当逆导型IGBT的栅极电压小于或等于0V时，逆导型IGBT没有形成反型载流子通道，FRD的阳极未短路，FRD的阳极注入效率高，FRD的正向导通压降较低。但是，当逆导IGBT栅极电压大于或等于阈值电压时，逆导型IGBT内，导电类型相反的两源区之间形成反型载流子通道，使FRD的阳极短路，导致FRD阳极注入效率降低，FRD的正向导通压降上升，使FRD无法正常工作。
发明内容
针对上述问题，本公开提供了一种逆导型IGBT的元胞结构及逆导型IGBT。
第一方面，本公开提供一种逆导型IGBT的元胞结构，包括：
第一导电类型衬底；
位于所述衬底上方的第一导电类型漂移层；
位于元胞结构中心且在所述漂移层表面内设置的第二导电类型阱区；
设置于所述阱区表面内的第一导电类型源区和第二导电类型源区；其中，所述第一导 电类型源区位于所述第二导电类型源区两侧并且所述第一导电类型源区高于所述第二导电类型源区，使得所述第一导电类型源区的部分底部覆盖所述第二导电类型源区两侧的部分表面，并使得所述第一导电类型源区的侧面与所述第二导电类型源区未被所述第一导电类型源区覆盖的表面一起合围成一主沟槽；
覆盖在所述主沟槽的侧壁和底部上的导电层；
设置于所述主沟槽两侧且与所述阱区和所述第一导电类型源区接触的栅结构；
设置在所述栅结构上方和所述主沟槽中的发射极金属层；
其中，所述栅结构中的栅极与所述第一导电类型源区之间，所述栅结构中的栅极与所述主沟槽的侧壁上的部分导电层之间，所述栅结构中的栅极、所述第一导电类型源区和所述主沟槽的侧壁上的部分导电层与所述发射极金属层之间通过层间介质层隔离，所述主沟槽的底部上的部分导电层与所述发射极金属层接触，用于导出所述第一导电类型源区的电流。
根据本公开的实施例，优选地，所述第二导电类型源区的表面比所述第一导电类型源区的表面低0.3um以上。
根据本公开的实施例，优选地，所述导电层为金属层或硅合金层。
根据本公开的实施例，优选地，还包括：
设置于所述漂移层内且位于所述阱区下方的第一导电类型存储区。
根据本公开的实施例，优选地，所述存储区的掺杂浓度比所述衬底的掺杂浓度高一个数量级至两个数量级。
根据本公开的实施例，优选地，还包括：
设置于所述阱区内且位于所述第二导电类型源区下方的寿命控制区。
根据本公开的实施例，优选地，所述栅结构包括位于所述漂移层上方并同时与所述第一导电类型源区、所述阱区和所述漂移层的表面接触的栅极绝缘层，以及位于所述栅极绝缘层上方的栅极。
根据本公开的实施例，优选地，所述栅结构包括设置于所述漂移层内并与所述阱区邻接的栅极沟槽、设置于所述栅极沟槽侧壁和底部的栅极绝缘层以及填充于所述栅极沟槽内的栅极，其中，所述栅极沟槽还与所述第一导电类型源区远离元胞结构中心的一端接触。
根据本公开的实施例，优选地，还包括：
位于所述衬底下方的第二导电类型集电区和与所述集电区相邻接的第一导电类型短路区；
位于所述集电区和所述短路区下方并与所述集电区和所述短路区形成电连接的集电极金属层。
根据本公开的实施例，优选地，所述元胞结构为蜂窝状元胞结构或条形元胞结构。
第二方面，本公开提供一种逆导型IGBT器件，包括若干如第一方面任一项所述的逆导型IGBT的元胞结构。
采用上述技术方案，至少能够达到如下技术效果：
本公开提供一种逆导型IGBT的元胞结构及逆导型IGBT，将第一导电类型源区与发射极金属层通过导电层连接，消除了第一导电类型源区与第二导电类型源区之间的耦合关系，并将第一导电类型源区的电流通过导电层导出，使逆导型IGBT工作在FRD模式且逆导型IGBT栅极电压大于或等于阈值电压时，第一导电类型源区的短路效应对FRD阳极注入影响降低，从而降低栅极电压对FRD正向导通压降的影响，使FRD获得更低的正向压降。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1是传统的平面栅结构的逆导型IGBT的元胞结构的剖面结构示意图；
图2是传统的沟槽栅结构的逆导型IGBT的元胞结构的剖面结构示意图；
图3是本公开一示例性实施例示出的一种平面栅结构的逆导型IGBT的元胞结构的剖面结构示意图；
图4是本公开一示例性实施例示出的另一种平面栅结构的逆导型IGBT的元胞结构的剖面结构示意图；
图5是本公开一示例性实施例示出的另一种平面栅结构的逆导型IGBT的元胞结构的剖面结构示意图；
图6是本公开一示例性实施例示出的一种沟槽栅结构的逆导型IGBT的元胞结构的剖面结构示意图；
图7是本公开一示例性实施例示出的另一种沟槽栅结构的逆导型IGBT的元胞结构的剖面结构示意图；
图8是本公开一示例性实施例示出的另一种沟槽栅结构的逆导型IGBT的元胞结构的剖面结构示意图。
具体实施方式
以下将结合附图及实施例来详细说明本公开的实施方式，借此对本公开如何应用技术手段来解决技术问题，并达到相应技术效果的实现过程能充分理解并据以实施。本公开实施例以及实施例中的各个特征，在不相冲突前提下可以相互结合，所形成的技术方案均在本公开的保护范围之内。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大。 自始至终相同附图标记表示相同的元件。
应理解，尽管可使用术语“第一”、“第二”、“第三”等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
应理解，空间关系术语例如“在...上方”、位于...上方”、“在...下方”、“位于...下方”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下方”的元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下方”和“在...下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本公开的理想实施例(和中间结构)的示意图的横截面图来描述本公开的实施例。这样，可以预期由于例如制备技术和/或容差导致的从所示形状的变化。因此，本公开的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制备导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不意图显示器件的区的实际形状且并不意图限定本公开的范围。
为了彻底理解本公开，将在下列的描述中提出详细的结构以及步骤，以便阐释本公开提出的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
实施例一
如图3所示，本公开实施例提供一种平面栅结构的逆导型IGBT的元胞结构300，包括衬底301、漂移层302、阱区303、第二导电类型源区304、第一导电类型源区305、栅 极绝缘层306、栅极307、导电层308、层间介质层309、发射极金属层310、集电区311、短路区312、集电极金属层313。
示例性地，衬底301为第一导电类型的硅基衬底。
漂移层302为第一导电类型的漂移层，位于衬底301上方，漂移层302的厚度根据器件的耐压能力不同来进行选择。
阱区303为第二导电类型的阱区，位于元胞结构中心且设置在漂移层302表面内，阱区303的表面与漂移层302的表面相平齐。
第二导电类型源区304，为第二导电类型的源区，设置于阱区303表面内。
第一导电类型源区305，为第一导电类型的源区，第一导电类型源区305设置于阱区303表面内且位于第二导电类型源区304两侧。第一导电类型源区305高于第二导电类型源区304，使得第一导电类型源区305的底部部分覆盖第二导电类型源区304两侧的部分表面，并使得第一导电类型源区305的侧面与第二导电类型源区304未被第一导电类型源区305覆盖的表面一起合围成一主沟槽(图中未标注)。
本实施例中，上述主沟槽是在阱区303的表面内形成第一导电类型源区305和第二导电类型源区304之后，通过刻蚀两个第一导电类型源区305之间的部分第二导电类型源区304得到的，刻蚀之后，第二导电类型源区304仅剩下位于第一导电类型源区305下方和主沟槽下方的部分。
本实施例中，第二导电类型源区304的表面比第一导电类型源区305的表面低0.3um以上。这种结构可以提高载流子在垂直方向的注入水平。
栅极绝缘层306和栅极307构成栅结构，本实施例中，栅结构为平面栅结构。
栅极绝缘层306位于主沟槽两侧且位于漂移层302上方，栅极绝缘层306同时与第一导电类型源区305、阱区303和漂移层302的表面接触，但不与导电层308接触。栅极绝缘层306使栅极307与第一导电类型源区305、阱区303和漂移层302隔离开。
栅极307为多晶硅栅极，设置于栅极绝缘层306上方。
导电层308设置于上述主沟槽的底部和侧壁，甚至延伸至第一导电类型源区305上方，导电层308的厚度为50nm至200nm，导电层308为金属层或硅合金层。
层间介质层309位于栅极307上方，同时覆盖位于第一导电类型源区305上方和位于主沟槽侧壁的部分导电层。层间介质层309将栅极307、第一导电类型源区305、位于第一导电类型源区305上方和位于主沟槽侧壁的部分导电层与发射极金属层310隔离开，还将栅极307与第一导电类型源区305和导电层308隔离开。
发射极金属层310位于层间介质层309上方并填充上述主沟槽，发射极金属层310与位于主沟槽底部的部分导电层接触，用于导出第一导电类型源区305的短路电流。发射极金属层310可以为铝等具有低接触电阻率的金属。
这种结构使逆导型IGBT工作在FRD模式且逆导型IGBT栅极电压大于或等于阈值电压时，第一导电类型源区305的短路电流通过导电层308导出，使该短路电流对第二导电类型源区304的注入影响降低，降低了第一导电类型源区305的短路效应对FRD阳极注入的影响，从而达到降低FRD正向导通压降的目的。
集电区311为第二导电类型的集电区，集电区311位于衬底301下方。
短路区312为第二导电类型的短路区，短路区312位于衬底301下方，与集电区311邻接。
集电极金属层313位于集电区311和短路区312下方并与集电区311和短路区312形成电连接。
本实施例中，如图4所示，元胞结构300还可以包括存储区314，存储区314为第一导电类型的载流子存储区，设置于漂移层302内且位于阱区303下方，存储区314的掺杂浓度比衬底301的掺杂浓度高一个数量级至两个数量级。存储区314可以降低IGBT的导通压降。
如图5所示，元胞结构300还可以包括寿命控制区315，寿命控制区315设置于阱区303内且位于第二导电类型源区304下方，寿命控制区315为低寿命控制区，其少子寿命低于附近其他区域，一般低三个量级到四个量级。寿命控制区315通过在阱区内注入其它类型的杂质来降低少子寿命得到，可以降低FRD的开关损耗。这种元胞结构可以同时获得较低的FRD正向导通压降和较低的FRD开关损耗。
需要说明的是，元胞结构300的形状可以为蜂窝状、短条形(元胞长度≤200um)或长条形。
在本实施例中，第一导电类型和所述第二导电类型相反。例如，第一导电类型为N型时，第二导电类型为P型；第一导电类型为P型时，第二导电类型为N型。具体地，根据实际需要制备的器件类型进行合理选择即可。
本公开提供一种平面栅结构的逆导型IGBT的元胞结构，将第一导电类型源区305与发射极金属层310通过导电层308连接，消除了第一导电类型源区305与第二导电类型源区304之间的耦合关系，并将第一导电类型源区305的电流通过导电层308导出，使逆导型IGBT工作在FRD模式且逆导型IGBT栅极电压大于或等于阈值电压时，第一导电类型源区305的短路效应对FRD阳极注入影响降低，从而降低栅极电压对FRD正向导通压降的影响，使FRD获得更低的正向压降。
实施例二
如图6所示，本公开实施例提供一种沟槽栅结构的逆导型IGBT的元胞结构400，包括衬底401、漂移层402、栅极绝缘层403、栅极404、阱区405、第二导电类型源区406、 第一导电类型源区407、导电层408、层间介质层409、发射极金属层410、集电区411、短路区412、集电极金属层413。
示例性地，衬底401为第一导电类型的硅基衬底。
漂移层402为第一导电类型的漂移层，位于衬底401上方，漂移层402的厚度根据器件的耐压能力不同来进行选择。
栅极沟槽(图中未标注)、栅极绝缘层403和栅极404构成栅结构，本实施例中，栅结构为沟槽栅结构。
栅极沟槽设置于元胞结构两侧且位于漂移层402内并与阱区405邻接，栅极沟槽的深度大于阱区405的深度。
栅极绝缘层403设置于上述栅极沟槽的侧壁和底部，使栅极404与第一导电类型源区407、阱区405和漂移层402隔离开。
栅极404为多晶硅栅极，填充于上述栅极沟槽内。
阱区405为第二导电类型的阱区，设置在漂移层402表面内，且位于元胞结构中心位置、两个栅极沟槽之间。阱区405的表面与漂移层402的表面相平齐，阱区405的两端分别与两侧的栅极沟槽接触，即与两侧的栅极绝缘层接触。
第二导电类型源区406，为第二导电类型的源区，设置于阱区405表面内，第二导电类型源区406的表面与漂移层402的表面相平齐。
第一导电类型源区407，为第一导电类型的源区，第一导电类型源区407设置于阱区405表面内且位于第二导电类型源区406两侧。第一导电类型源区407高于第二导电类型源区406，使得第一导电类型源区407的底部部分覆盖第二导电类型源区406两侧的部分表面，并使得第一导电类型源区407的侧面与第二导电类型源区406未被第一导电类型源区407覆盖的表面一起合围成一主沟槽(图中未标注)。
本实施例中，上述主沟槽是在阱区405的表面内形成第一导电类型源区407和第二导电类型源区406之后，通过刻蚀两个第一导电类型源区407之间的部分第二导电类型源区406得到的，刻蚀之后，第二导电类型源区406仅剩下位于第一导电类型源区407下方和主沟槽下方的部分。
本实施例中，第二导电类型源区406的表面比第一导电类型源区407的表面低0.3um以上。这种结构可以提高载流子在垂直方向的注入水平。
导电层408设置于上述主沟槽的底部和侧壁甚至延伸至第一导电类型源区407的上方，导电层408的厚度为50nm至200nm，导电层408为金属层或硅合金层。
层间介质层409位于栅极404上方，同时覆盖第一导电类型源区407、位于第一导电类型源区407上方和位于主沟槽侧壁的部分导电层。层间介质层409将栅极404、第一导电类型源区407、位于第一导电类型源区407上方和位于主沟槽侧壁的部分导电层与发射 极金属层410隔离开，还将栅极404与第一导电类型源区407和导电层408隔离开。
发射极金属层410位于层间介质层409上方并填充上述沟槽，发射极金属层410与位于主沟槽底部的导电层接触，用于导出第一导电类型源区407的短路电流。发射极金属层410可以为铝等具有低接触电阻率的金属。
这种结构使逆导型IGBT工作在FRD模式且逆导型IGBT栅极电压大于或等于阈值电压时，第一导电类型源区407的短路电流通过导电层408导出，使该短路电流对第二导电类型源区406的注入影响降低，降低了第一导电类型源区407的短路效应对FRD阳极注入的影响，从而达到降低FRD正向导通压降的目的。
集电区411为第二导电类型的集电区，集电区411位于衬底401下方。
短路区412为第二导电类型的短路区，短路区412位于衬底401下方，与集电区411邻接。
集电极金属层413位于集电区411和短路区412下方并与集电区411和短路区412形成电连接。
本实施例中，如图7所示，元胞结构400还可以包括存储区414，存储区414为第一导电类型的载流子存储区，设置于漂移层402内且位于阱区405下方，存储区414的掺杂浓度比衬底401的掺杂浓度高一个数量级至两个数量级。存储区414可以降低IGBT的导通压降。
如图8所示，元胞结构400还可以包括寿命控制区415，寿命控制区415设置于阱区405内且位于第二导电类型源区406下方，寿命控制区415为低寿命控制区，其少子寿命低于附近其他区域，一般低三个量级到四个量级。寿命控制区415通过在阱区内注入其它类型的杂质来降低少子寿命得到，可以降低FRD的开关损耗。这种元胞结构可以同时获得较低的FRD正向导通压降和较低的FRD开关损耗。
需要说明的是，元胞结构400的形状可以为蜂窝状、短条形(元胞长度≤200um)或长条形。
在本实施例中，第一导电类型和所述第二导电类型相反。例如，第一导电类型为N型时，第二导电类型为P型；第一导电类型为P型时，第二导电类型为N型。具体地，根据实际需要制备的器件类型进行合理选择即可。
本公开提供一种平面栅结构的逆导型IGBT的元胞结构，将第一导电类型源区407与发射极金属层410通过导电层408连接，消除了第一导电类型源区407与第二导电类型源区406之间的耦合关系，并将第一导电类型源区407的电流通过导电层408导出，使逆导型IGBT工作在FRD模式且逆导型IGBT栅极电压大于或等于阈值电压时，第一导电类型源区407的短路效应对FRD阳极注入影响降低，从而降低栅极电压对FRD正向导通压降的影响，使FRD获得更低的正向压降。
以上仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。虽然本公开所公开的实施方式如上，但的内容只是为了便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属技术领域内的技术人员，在不脱离本公开所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本公开的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (11)

  1. 一种逆导型IGBT的元胞结构，其中，包括：
    第一导电类型衬底位于所述衬底上方的第一导电类型漂移层；
    位于元胞结构中心且在所述漂移层表面内设置的第二导电类型阱区；
    设置于所述阱区表面内的第一导电类型源区和第二导电类型源区；其中，所述第一导电类型源区位于所述第二导电类型源区两侧并且所述第一导电类型源区高于所述第二导电类型源区，使得所述第一导电类型源区的部分底部覆盖所述第二导电类型源区两侧的部分表面，并使得所述第一导电类型源区的侧面与所述第二导电类型源区未被所述第一导电类型源区覆盖的表面一起合围成一主沟槽；
    覆盖在所述主沟槽的侧壁和底部上的导电层；
    设置于所述主沟槽两侧且与所述阱区和所述第一导电类型源区接触的栅结构；
    设置在所述栅结构上方和所述主沟槽中的发射极金属层；
    其中，所述栅结构中的栅极与所述第一导电类型源区之间，所述栅结构中的栅极与所述主沟槽的侧壁上的部分导电层之间，所述栅结构中的栅极、所述第一导电类型源区和所述主沟槽的侧壁上的部分导电层与所述发射极金属层之间通过层间介质层隔离，所述主沟槽的底部上的部分导电层与所述发射极金属层接触，用于导出所述第一导电类型源区的电流。
  2. 根据权利要求1所述的逆导型IGBT的元胞结构，其中，所述第二导电类型源区的表面比所述第一导电类型源区的表面低0.3um以上。
  3. 根据权利要求1所述的逆导型IGBT的元胞结构，其特征在于，所述导电层为金属层或硅合金层。
  4. 根据权利要求1所述的逆导型IGBT的元胞结构，其中，还包括：
    设置于所述漂移层内且位于所述阱区下方的第一导电类型存储区。
  5. 根据权利要求4所述的逆导型IGBT的元胞结构，其中，所述存储区的掺杂浓度比所述衬底的掺杂浓度高一个数量级至两个数量级。
  6. 根据权利要求1所述的逆导型IGBT的元胞结构，其中，还包括：
    设置于所述阱区内且位于所述第二导电类型源区下方的寿命控制区。
  7. 根据权利要求1所述的逆导型IGBT的元胞结构，其中，所述栅结构包括位于所述漂移层上方并同时与所述第一导电类型源区、所述阱区和所述漂移层的表面接触的栅极绝缘层，以及位于所述栅极绝缘层上方的栅极。
  8. 根据权利要求1所述的逆导型IGBT的元胞结构，其中，所述栅结构包括设置于所述漂移层内并与所述阱区邻接的栅极沟槽、设置于所述栅极沟槽侧壁和底部的栅极绝缘层以及填充于所述栅极沟槽内的栅极，其中，所述栅极沟槽还与所述第一导电类型源区远离元胞结构中心的一端接触。
  9. 如权利要求1所述的逆导型IGBT的元胞结构，其中，还包括：
    位于所述衬底下方的第二导电类型集电区和与所述集电区相邻接的第一导电类型短路区；
    位于所述集电区和所述短路区下方并与所述集电区和所述短路区形成电连接的集电极金属层。
  10. 如权利要求1所述的逆导型IGBT的元胞结构，其中，所述元胞结构为蜂窝状元胞结构或条形元胞结构。
  11. 一种逆导型IGBT器件，其中，包括若干如权利要求1至10任一项所述的逆导型IGBT的元胞结构。
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