WO2021164637A1 - 集成接口电路以及接口电路的制作方法 - Google Patents

集成接口电路以及接口电路的制作方法 Download PDF

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Publication number
WO2021164637A1
WO2021164637A1 PCT/CN2021/076175 CN2021076175W WO2021164637A1 WO 2021164637 A1 WO2021164637 A1 WO 2021164637A1 CN 2021076175 W CN2021076175 W CN 2021076175W WO 2021164637 A1 WO2021164637 A1 WO 2021164637A1
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WIPO (PCT)
Prior art keywords
resistor
interface circuit
capacitor
functional interface
triode
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Ceased
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PCT/CN2021/076175
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English (en)
French (fr)
Inventor
张海波
湛康
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Bosch Automotive Products Suzhou Co Ltd
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Bosch Automotive Products Suzhou Co Ltd
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Priority to EP21757503.4A priority Critical patent/EP4109284B1/en
Publication of WO2021164637A1 publication Critical patent/WO2021164637A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Program-control systems
    • G05B19/02—Program-control systems electric
    • G05B19/04—Program control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Program control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output

Definitions

  • the present invention relates to interface circuit design, and more specifically, to an integrated interface circuit, a manufacturing method of the interface circuit, an electronic control unit, a vehicle, and a computer storage medium.
  • the processing unit in the existing electric vehicle ECU generally has multiple ports with different functions, such as ADC (Analog-to-Digital Converter) ports, input pin ports, output pin ports, ground ports, and so on.
  • ADC Analog-to-Digital Converter
  • Each functional port has certain requirements for the specifications of the input signal or output signal, for example, the input voltage must not be higher than 4V.
  • the available external port resources of the ECU will be very tight, and more ports with customized requirements cannot be set.
  • an integrated interface circuit includes: a plurality of functional interface circuits connected between an external port and a processor and corresponding to different functions, wherein the plurality of functions
  • the interface circuit includes a first functional interface circuit corresponding to a first function and a second functional interface circuit corresponding to a second function, and the circuit elements in the second functional interface circuit are at least Partially coincide.
  • the multiple functional interface circuits further include a third functional interface circuit corresponding to a third function, wherein the circuit elements in the third functional interface circuit and the first function Neither the interface circuit nor the circuit elements in the second functional interface circuit overlap.
  • the external port is an external input port for receiving external input signals or an external output interface for transmitting signals to the outside.
  • the processor is a single-chip microcomputer.
  • the third functional interface circuit includes: a first filter element, configured to filter an external input signal received from an external port; a voltage dividing element, and the first filter element Connected in series for reducing the voltage of the external input signal filtered by the first filter element; and a voltage limiting element, one end of the voltage limiting element is connected in series with the voltage dividing element, and the other of the voltage limiting element One end is connected in series with the corresponding terminal of the processor, and the voltage limiting element is configured to limit the voltage output to the corresponding terminal of the processor.
  • the third functional interface circuit further includes: a second filter element, and the second filter element is connected in series with the voltage dividing element and the voltage limiting element for pairing The external input signal after voltage division by the voltage dividing element is subjected to secondary filtering.
  • the third functional interface circuit includes: the first filter element including a first inductor and a first capacitor, wherein the first end of the first inductor is connected to The external port is connected, the second end of the first inductor is connected to the first end of the first capacitor, and the second end of the first capacitor is grounded; including a first resistor and a second resistor The voltage dividing element, wherein the first end of the first resistor is connected to the second end of the first inductor, and the second end of the first resistor is connected to the second end of the second resistor.
  • the second filter element including a second capacitor, wherein the first end of the second capacitor is connected to the second end of the first resistor Connected, and the second end of the second capacitor is grounded; a voltage limiting element including a first diode, the first end of the first diode is connected to the first end of the second capacitor, the The second end of the first diode is connected to a first reference power source, and the first port of the processor is connected to the first end of the first diode.
  • the first functional interface circuit includes: a third capacitor, wherein the first end of the third capacitor is connected to the external port, and the second end of the third capacitor Connected to the first end of the sixth resistor; a fifth resistor, wherein the first end of the fifth resistor is connected to the external port, and the second end of the fifth resistor is connected to the sixth resistor A sixth resistor; and a tenth resistor, the first end of the tenth resistor is connected to the second end of the fifth resistor, and the second end of the tenth resistor is connected The terminal is connected to the second port of the processor.
  • the overlapping elements of the second functional interface circuit and the first functional interface circuit include the third capacitor, the sixth resistor, and the tenth resistor.
  • the second functional interface circuit includes: a third capacitor, wherein the first end of the third capacitor is connected to the external port, and the second terminal of the third capacitor is connected to the external port.
  • the first end of the third resistor is connected to the first end of the sixth resistor; the third resistor, wherein the first end of the third resistor is connected to a second reference power source, and the second end of the third resistor is connected to the external Port connection; a first triode, the collector of the first triode is connected to the second end of the third resistor, and the base of the first triode is connected to the sixth resistor
  • the second end is connected, the emitter of the first triode is connected to the first end of the fourth resistor; the fourth resistor, the second end of the fourth resistor is connected to the second end of the third capacitor A sixth resistor; and a tenth resistor, the first end of the tenth resistor is connected to the base of the first triode, and the second end of the tenth resistor
  • the overlapping elements of the second functional interface circuit and the first functional interface circuit include the third capacitor, the fifth resistor, and the sixth resistor.
  • the second functional interface circuit includes: a third capacitor, wherein the first end of the third capacitor is connected to the external port, and the second end of the third capacitor Connected to the first end of the sixth resistor; a fifth resistor, wherein the first end of the fifth resistor is connected to the external port, and the second end of the fifth resistor is connected to the sixth resistor The second end is connected; the sixth resistor; the seventh resistor, the first end of the seventh resistor is connected to the third reference power source, the second end of the seventh resistor is connected to the emission of the second triode Pole connection; an eighth resistor, the first end of the eighth resistor is connected to the third reference power source, the second end of the eighth resistor is connected to the base of the second triode; the second triode Tube, the collector of the second triode is connected to the second end of the sixth resistor; a third triode, the collector of the third triode is connected to the second end of the second triode The base is connected, the base of
  • the above-mentioned integrated interface circuit further includes: a selector for selecting a corresponding functional interface circuit from the plurality of functional interface circuits according to the control signal.
  • a method for manufacturing an interface circuit comprising: determining a function corresponding to the interface circuit; and selecting a corresponding function from the integrated interface circuit according to the determined function The interface circuit is filled.
  • an electronic control unit including the integrated interface circuit as described above.
  • a vehicle including the above-mentioned electronic control unit.
  • a computer storage medium including instructions that execute the aforementioned method at runtime.
  • the integrated interface circuit of the present invention includes a plurality of functional interface circuits connected between the external port and the processor and respectively corresponding to different functions.
  • a single external port it can correspond to multiple functional interface circuits. That is to say, a single external port can obtain multiple functions (integrated functions) provided by the functional interface circuit or the processor through the adaptation of the multiple functional interface circuits, which advantageously saves limited port resources (that is, has more Multiple port resources to meet customer customization needs).
  • different functional interface circuits may have circuit elements that are at least partially overlapped, so that the entire integrated interface circuit is more streamlined and the manufacturing cost is reduced.
  • Fig. 1 shows a schematic diagram of an integrated interface circuit according to an embodiment of the present invention
  • Figure 2 shows a schematic structural diagram of a third functional interface circuit according to an embodiment of the present invention
  • Fig. 3 shows a schematic structural diagram of a first functional interface circuit according to an embodiment of the present invention
  • Fig. 4 shows a schematic structural diagram of a second functional interface circuit according to an embodiment of the present invention
  • Fig. 5 shows a schematic structural diagram of a second functional interface circuit according to another embodiment of the present invention.
  • Figure 6 shows a schematic structural diagram of an integrated interface circuit according to an embodiment of the present invention.
  • Fig. 7 shows a schematic diagram of a manufacturing method of an interface circuit according to an embodiment of the present invention.
  • vehicle or other similar terms used herein includes various motor vehicles and non-motor vehicles, such as passenger vehicles (including sport utility vehicles, buses, trucks, etc.), various commercial vehicles, Ships, airplanes, motorcycles, bicycles, etc., including hybrid vehicles, electric vehicles, etc.
  • a hybrid vehicle is a vehicle with two or more power sources, such as gasoline-powered and electric vehicles.
  • control logic of the present invention may be included on a computer-readable medium as executable program instructions, which are implemented by a processor or the like.
  • Examples of computer readable media include, but are not limited to, ROM, RAM, optical disks, magnetic tapes, floppy disks, flash drives, smart cards, and optical data storage devices.
  • the computer-readable recording medium may also be distributed in a computer system connected to a network, so that the computer-readable medium is stored and implemented in a distributed manner, for example, through an in-vehicle telecommunication service or a controller area network (CAN).
  • CAN controller area network
  • Fig. 1 shows a schematic diagram of an integrated interface circuit 1000 according to an embodiment of the present invention.
  • the integrated interface circuit 1000 includes a plurality of functional interface circuits connected between the external port 140 and the processor 150 and respectively corresponding to different functions.
  • the multiple functional interface circuits include a first functional interface circuit 110 corresponding to a first function and a second functional interface circuit 120 corresponding to a second function, and the circuit elements in the second functional interface circuit 120 are the same as those in the first functional interface circuit.
  • the circuit elements in the functional interface circuit 110 at least partially overlap.
  • interface circuit refers to a logic circuit that connects an external device/external port and an internal processor, and is a bridge for information interaction between the processor and the external device.
  • the functions of the interface circuit include, but are not limited to, level connection, impedance matching, signal processing or “maintenance”, electrostatic protection, AC and DC isolation, and so on.
  • the interface circuit can be further subdivided into different functional interface circuits, that is, the first functional interface circuit, the second functional interface circuit, and so on.
  • different functions implemented by the interface circuit classify the interface circuit.
  • the interface circuits are classified according to different ports matched with the processor.
  • the interface circuits are classified according to different functions that are adapted or implemented.
  • the term “external port” refers to a port connected to an external device, which may be an external input port for receiving external input signals or an external output interface for transmitting signals to the outside.
  • the "processor” can be any unit that performs a processing function, such as a single-chip microcomputer. Those skilled in the art can understand that the processor may provide multiple functions, such as various signal processing and analog-to-digital conversion functions. In addition, the processor may have multiple ports, and the different ports have certain specifications for input or output signals.
  • the external port 140 may be a port that connects the ECU to the outside, and the processor 150 may be a microprocessor of the ECU.
  • the integrated interface circuit 1000 includes multiple functional interface circuits corresponding to different functions, such as the first functional interface circuit 110 and the second functional interface circuit 120. In this way, for the external port 140, it can correspond to multiple functional interface circuits. In other words, the external port 140 can obtain multiple integrated functions through (adaptation) of the multiple functional interface circuits, which advantageously saves limited port resources. In other words, by providing the integrated interface circuit 1000 in the electronic control unit ECU, the electronic control unit ECU can have more port resources to meet customer customization requirements. In addition, the circuit elements in the second functional interface circuit 120 and the circuit elements in the first functional interface circuit 110 at least partially overlap, so that the entire integrated interface circuit 1000 is simplified and the manufacturing cost is reduced.
  • the multiple functional interface circuits may further include a third functional interface circuit 130 (shown by a dotted line) for implementing a third function.
  • the circuit elements in the third functional interface circuit 130 and the circuit elements in the first functional interface circuit 110 or the second functional interface circuit 120 do not overlap.
  • Those skilled in the art can understand that more or fewer functional interface circuits can be provided in the integrated interface circuit 1000 as required, and these functional interface circuits are connected to the first functional interface circuit 110, the second functional interface circuit 120, and the third functional interface.
  • the circuit 130 may be at least partially overlapped or not overlapped at all.
  • the third functional interface circuit 130 corresponds to an ADC (Analog to Digital Conversion) input port of the processor 150.
  • the third functional interface circuit 130 may include a first filter element, a voltage dividing element, and a voltage limiting element.
  • the first filter element is used to filter the external input signal received from the external port;
  • the voltage divider element is used in series with the first filter element to reduce the external input filtered by the first filter element The voltage of the signal; one end of the voltage limiting element is connected in series with the voltage dividing element, and the other end of the voltage limiting element is connected in series with the corresponding terminal of the processor, configured to limit the voltage output to the corresponding terminal of the processor.
  • the third functional interface circuit may further include: a second filter element, the second filter element is connected in series with the voltage dividing element and the voltage limiting element, and configured to The external input signal after the component is voltage-divided is subjected to secondary filtering.
  • FIG. 2 shows a schematic structural diagram of the third functional interface circuit 130 for adapting the ADC input port of the processor 150.
  • the third functional interface circuit 130 includes: a first filter element composed of a first inductor L1 and a first capacitor C1, a voltage dividing element composed of a first resistor R1 and a second resistor R2, A second filter unit composed of a second capacitor C2 and a voltage limiting element composed of a first diode D1.
  • the aforementioned filter element, voltage divider element, and voltage limiting element may include more circuit elements according to actual needs, and are not limited to the specific circuit in FIG. 2.
  • the first end of the first inductor L1 is connected to the external port P1, the second end of the first inductor L1 is connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is grounded to GND1 ,
  • the first end of the first resistor R1 is connected to the second end of the first inductor L1, the second end of the first resistor R1 is connected to the first end of the second resistor R2, and the second end of the second resistor R2
  • the two ends are grounded to GND2
  • the first end of the second capacitor C2 is connected to the second end of the first resistor R1, the second end of the second capacitor C2 is grounded to GND3
  • the first end of the first diode D1 is connected to the second capacitor
  • the first end of C2 is connected, the second end of the first diode D1 is connected to the first reference power source REF1, and the port P2 of the processor (ie, the ADC input port) is connected to the first end of the first diode D1.
  • the first inductor L1 and the first capacitor C1 form an LC filter element (ie, the first filter element).
  • LC filter element ie, the first filter element
  • a smooth direct current can be obtained, and the ripple voltage can be reduced.
  • this kind of filtering can also play a very good filtering effect when the current changes and fluctuates.
  • the voltage dividing element composed of the first resistor R1 and the second resistor R2 can reduce the voltage of the external input signal filtered by the LC. According to needs, the resistance of the first resistor R1 and the second resistor R2 can be set appropriately to obtain the ideal output voltage at the P2 port.
  • the second filter element composed of C2 is used to perform capacitive filtering (ie, secondary filtering) on the signal output to the P2 port, which can further reduce clutter interference.
  • capacitive filtering ie, secondary filtering
  • the voltage of the port P2 is clamped below 4V.
  • the voltage of the port P2 can be clamped below the corresponding different voltage values.
  • the first functional interface circuit 110 is configured to adapt to the input port of the processor 150.
  • FIG. 3 shows a schematic diagram of a structure in which the first functional interface circuit 110 is used as an adaptive input port.
  • the first functional interface circuit 110 includes a third capacitor C3, a fifth resistor R5, a sixth resistor R6, and a tenth resistor R10.
  • the first end of the third capacitor C3 is connected to the external port P1
  • the second end of the third capacitor C3 is connected to the first end of the sixth resistor R6, and the The first end is connected to the external port P1
  • the second end of the fifth resistor R5 is connected to the second end of the sixth resistor R6, and the first end of the tenth resistor R10 is connected to the The second end of the fifth resistor R5 is connected, and the second end of the tenth resistor R10 is connected to the second port P3 of the processor (for example, a general input and output interface GPIO).
  • the first functional interface circuit 110 shown in FIG. 3 can play a good current limiting effect by setting the capacitance and resistance values of each circuit element reasonably.
  • the direct current will not pass through the branch formed by the third capacitor C3 and the sixth resistor R6, but only flows through the fifth resistor R5 and the tenth resistor R10. Assuming that the fifth resistor is a large resistance, the current output to the P3 port is well limited.
  • the second functional interface circuit 120 is configured to realize the function of “reverse output” and adapt to the output port of the processor 150.
  • FIG. 4 shows a schematic structural diagram of the second functional interface circuit 120.
  • the second functional interface circuit 120 includes a third capacitor C3, a third resistor R3, a first transistor T1, a fourth resistor R4, a sixth resistor R6, and a tenth resistor R10.
  • the first end of the third capacitor C3 is connected to the external port P1
  • the second end of the third capacitor C3 is connected to the first end of the sixth resistor R6, and the The first end is connected to the second reference power source REF2
  • the second end of the third resistor R3 is connected to the external port P1
  • the collector of the first transistor T1 is connected to the third resistor R3.
  • the second end is connected, the base of the first triode T1 is connected to the second end of the sixth resistor R6, and the emitter of the first triode T1 is connected to the first end of the fourth resistor R4.
  • the second end of the fourth resistor R4 is connected to the second end of the third capacitor C3 and grounded to GND5, and the first end of the tenth resistor R10 is connected to the first transistor T1.
  • the second end of the tenth resistor R10 is connected to the second port P3 of the processor (for example, a general input and output interface GPIO).
  • the level of the external port P1 will change inversely with the level of the output port P3 of the processor. That is, when the port P3 is at a high level, the external port P1 is displayed as a low level, and when the port P3 is at a low level, the external port P1 is displayed as a high level. For example, when the port P3 is at a low level, the first transistor T1 is turned off, and the voltage at the P1 terminal is approximately equal to the second reference voltage REF2 (ie, approximately 5V), and therefore is at a high level.
  • the second reference voltage REF2 ie, approximately 5V
  • the first transistor T1 When the port P3 is at a high level, the first transistor T1 is turned on, and the fourth resistor R4 is connected in parallel with the sixth resistor R6, and its equivalent resistance value is incomparable with the third resistor R3 and the tenth resistor R10 , So the voltage divided on the external port P1 is very low (ie, low level).
  • the second functional interface circuit shown in FIG. 4 partially overlaps with the circuit elements in the first functional interface circuit shown in FIG. 3.
  • the overlapping elements include the third capacitor C3, the sixth resistor R6, and the tenth resistor R10.
  • the second functional interface circuit 120 is configured to realize the function of “forward output” and adapt to the output port of the processor 150.
  • FIG. 5 shows another schematic diagram of the structure of the second functional interface circuit 120.
  • the second functional interface circuit 120 includes a third capacitor C3, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a second transistor T2, a The triode T3 and the ninth resistor R9.
  • the first end of the third capacitor C3 is connected to the external port P1
  • the second end of the third capacitor C3 is connected to the first end of the sixth resistor R6 and is grounded to GND5
  • the fifth resistor The first end of the resistor R5 is connected to the external port P1
  • the second end of the fifth resistor R5 is connected to the second end of the sixth resistor R6, and the first end of the seventh resistor R7 is connected to the second end of the sixth resistor R6.
  • the three reference power sources REF3 are connected, the second end of the seventh resistor R7 is connected to the emitter of the second transistor T2, the first end of the eighth resistor R8 is connected to the third reference power source REF3, and the The second end of the eighth resistor R8 is connected to the base of the second triode T2, the collector of the second triode T2 is connected to the second end of the sixth resistor R6, and the third The collector of the triode T3 is connected to the base of the second triode T2, the base of the third triode T3 is connected to the first end of the ninth resistor R9, and the third triode is connected to the first end of the ninth resistor R9.
  • the emitter of the tube T3 is grounded to GND4, the second end of the ninth resistor R9 is connected to the second end of the sixth resistor R6, and the second end of the ninth resistor R9 is also connected to the processor
  • the second port P3 (for example, a general-purpose input and output interface GPIO) is connected.
  • the level of the external port P1 will change in the same direction with the level of the output port P3 of the processor. That is, when the port P3 is at a high level, the external port P1 is displayed as a high level, and when the port P3 is at a low level, the external port P1 is displayed as a low level.
  • the second transistor T2 and the third transistor T3 are turned off, and the voltage at the P1 terminal is approximately equal to the voltage at the P3 terminal, and therefore is also at a low level.
  • the second transistor T2 and the third transistor T3 are turned on, and the voltage on the external port P1 is approximately equal to the voltage of the P3 port (ie, high level).
  • the second functional interface circuit shown in FIG. 5 partially overlaps with the circuit elements in the first functional interface circuit shown in FIG. 3.
  • the overlapping elements include the third capacitor C3, the fifth resistor R5, and the sixth resistor R6.
  • FIG. 6 shows a schematic structural diagram of an integrated interface circuit according to an embodiment of the present invention.
  • the integrated interface circuit covers the third functional interface circuit 130 shown in FIG. 2, the first functional interface circuit 110 shown in FIG.
  • the integrated interface circuit includes multiple functional interface circuits corresponding to different functions, such as a first functional interface circuit 110, a second functional interface circuit 120, and a third functional interface circuit 130.
  • the external port P1 it can correspond to multiple functional interface circuits.
  • the external port P1 can obtain multiple integrated functions through (adaptation) of the multiple functional interface circuits, which advantageously saves limited port resources.
  • the integrated interface circuit reuses circuit elements in different functional interface circuits, so that the entire integrated interface circuit is more streamlined and the manufacturing cost is reduced.
  • the above-mentioned integrated interface circuit may further include a selector for selecting a corresponding functional interface circuit from a plurality of functional interface circuits according to a control signal.
  • FIG. 7 shows a schematic diagram of a manufacturing method 7000 of an interface circuit according to an embodiment of the present invention. As shown in FIG. 7, the manufacturing method 7000 of the interface circuit includes the following steps:
  • step S710 determine the function corresponding to the interface circuit
  • step S720 according to the determined function, a corresponding functional interface circuit is selected from the above-mentioned integrated interface circuits for filling.
  • the function corresponding to the determining interface circuit in step S710 can be implemented by receiving an external control signal. Further, after the function is determined, the corresponding function interface circuit is selected to be filled. For example, when it is determined that the interface circuit corresponds to the ADC function, the circuit elements of the third functional interface circuit (that is, the first inductor L1, the first resistor R1, the first diode D1, and the first diode shown in FIG. 2 A capacitor C1, a second resistor R2, and a second capacitor C2) are selectively filled.
  • the integrated interface circuit can be located in the electronic control unit ECU as an example.
  • the external port may be a port that connects the ECU to the outside, and the processor may be the microprocessor of the ECU.
  • the integrated interface circuit includes multiple functional interface circuits corresponding to different functions, such as a first functional interface circuit, a second functional interface circuit, and so on. In this way, for the external port, it can correspond to multiple functional interface circuits.
  • the external port can obtain multiple integrated functions through (adaptation) of the multiple functional interface circuits, which advantageously saves limited port resources.
  • the electronic control unit ECU can have more port resources to meet customer customization requirements.

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Abstract

一种集成接口电路（1000）、接口电路的制作方法（7000）、电子控制单元、车辆以及计算机存储介质。所述集成接口电路（1000）包括：连接在外接端口（140）与处理器（150）之间、用于分别实现不同功能的多个功能接口电路，其中，所述多个功能接口电路包括用于实现第一功能的第一功能接口电路（110）以及用于实现第二功能的第二功能接口电路（120），并且所述第二功能接口电路（120）中的电路元件与所述第一功能接口电路（110）中的电路元件至少部分重合。

Description

集成接口电路以及接口电路的制作方法 技术领域
本发明涉及接口电路设计，更具体地，涉及一种集成接口电路、接口电路的制作方法、电子控制单元、车辆以及计算机存储介质。
背景技术
现有的电动车ECU(电子控制单元)内的处理单元一般具有多个不同功能的端口，例如ADC(模数转换器)端口、输入引脚端口、输出引脚端口、接地端口等等。每个功能端口对输入信号或输出信号的规格都有一定的要求，例如要求输入电压不得高于4V等。
如果按功能来分配ECU的外接端口(即每一外接端口对应单个功能)，则ECU的可用外接端口资源会十分紧张，无法设置更多客户定制需求的端口。
发明内容
根据本发明的一方面，提供了一种集成接口电路，所述集成接口电路包括：连接在外接端口与处理器之间、分别对应不同功能的多个功能接口电路，其中，所述多个功能接口电路包括对应第一功能的第一功能接口电路以及对应第二功能的第二功能接口电路，并且所述第二功能接口电路中的电路元件与所述第一功能接口电路中的电路元件至少部分重合。
可选地，在上述集成接口电路中，所述多个功能接口电路还包括对应第三功能的第三功能接口电路，其中，所述第三功能接口电路中的电路元件与所述第一功能接口电路或所述第二功能接口电路中的电路元件均不重合。
可选地，在上述集成接口电路中，所述外接端口为用于接收外部输入信号的外接输入端口或者用于向外部传送信号的外接输出接口。
可选地，在上述集成接口电路中，所述处理器为单片机。
可选地，在上述集成接口电路中，所述第三功能接口电路包括：第一滤波元件，用于对从外接端口接收的外部输入信号进行滤波；分压元件，与所述第一滤波元件相串联，用于降低经所述第一滤波元件滤波后的外部输入信号的电压；以及限压元件，所述限压元件的一端与所述分压元件相串联，所述限压元件的另一端与所述处理器的对应端子相串联，所述限压元件配置成限制输出到所述处理器的对应端子的电压。
可选地，在上述集成接口电路中，所述第三功能接口电路还包括：第二滤波元件，所述第二滤波元件与所述分压元件、所述限压元件相串联，用于对经由所述分压元件进行分压后的外部输入信号进行二级滤波。
可选地，在上述集成接口电路中，所述第三功能接口电路包括：包含第一电感器和第一电容器的所述第一滤波元件，其中，所述第一电感器的第一端与所述外接端口连接，所述第一电感器的第二端与所述第一电容器的第一端连接，并且所述第一电容器的第二端接地；包含第一电阻器和第二电阻器的所述分压元件，其中所述第一电阻器的第一端与所述第一电感器的第二端连接，所述第一电阻器的第二端与所述第二电阻器的第一端连接，所述第二电阻器的第二端接地；包含第二电容器的所述第二滤波元件，其中，所述第二电容器的第一端与所述第一电阻器的第二端连接，并且所述第二电容器的第二端接地；包含第一二极管的限压元件，所述第一二极管的第一端与所述第二电容器的第一端连接，所述第一二极管的第二端与第一参考电源连接，并且所述处理器的第一端口与所述第一二极管的第一端连接。
可选地，在上述集成接口电路中，所述第一功能接口电路包括：第三电容器，其中所述第三电容器的第一端与所述外接端口连接，所述第三电容器的第二端与第六电阻器的第一端连接；第五电阻器，其中所述第五电阻器的第一端与所述外接端口连接，所述第五电阻器的第二端与所述第六电阻器的第二端连接；第六电阻器；以及第十电阻器，所述第十电阻器的第一端与所述第五电阻器的第二端连接，所述第十电阻器的第二端与所述处理器的第二端口连接。
可选地，在上述集成接口电路中，所述第二功能接口电路与所述第一功能接口电路重合的元件包括所述第三电容器、所述第六电阻器以及所述第十电阻器。
可选地，在上述集成接口电路中，所述第二功能接口电路包括：第三电容器，其中，所述第三电容器的第一端与所述外接端口连接，所述第三电容器的第二端与第六电阻器的第一端连接；第三电阻器，其中，所述第三电阻器的第一端与第二参考电源连接，所述第三电阻器的第二端与所述外接端口连接；第一三极管，所述第一三极管的集电极与所述第三电阻器的第二端连接，所述第一三级管的基极与所述第六电阻器的第二端连接，所述第一三极管的发射极与第四电阻器的第一端连接；第四电阻器，所述第四电阻器的第二端与所述第三电容器的第二端连接并接地；第六电阻器；以及第十电阻器，所述第十电阻器的第一端与所述第一三极管的基极连接，所述第十电阻器的第二端与所述处理器的第二端口连接。
可选地，在上述集成接口电路中，所述第二功能接口电路与所述第一功能接口电路重合的元件包括所述第三电容器、所述第五电阻器以及所述第六电阻器。
可选地，在上述集成接口电路中，所述第二功能接口电路包括：第三电容器，其中所述第三电容器的第一端与所述外接端口连接，所述第三电容器的第二端与第六电阻器的第一端连接；第五电阻器，其中所述第五电阻器的第一端与所述外接端口连接，所述第五电阻器的第二端与第六电阻器的第二端连接；第六电阻器；第七电阻器，所述第七电阻器的第一端与第三参考电源连接，所述第七电阻器的第二端与第二三极管的发射极连接；第八电阻器，所述第八电阻器的第一端与第三参考电源连接，所述第八电阻器的第二端与第二三极管的基极连接；第二三极管，所述第二三极管的集电极与所述第六电阻器的第二端连接；第三三极管，所述第三三极管的集电极与所述第二三极管的基极连接，所述第三三极管的基极与第九电阻器的第一端连接，所述第三三极管的发射极接地；以及第九电阻器，所述第九电阻器的第二端与所述第六电阻器的第二端连接，所述第九电阻器的第二端还与 所述处理器的第二端口连接。
可选地，上述集成接口电路还包括：选择器，用于根据控制信号从所述多个功能接口电路中选择对应的功能接口电路。
根据本发明的另一个方面，提供了一种接口电路的制作方法，所述方法包括：确定所述接口电路所对应的功能；以及根据所确定的功能，从上述集成接口电路中选择对应的功能接口电路进行填充。
根据本发明的又一个方面，提供了一种电子控制单元，包括如前所述的集成接口电路。
根据本发明的又一个方面，提供了一种车辆，包括上述电子控制单元。
根据本发明的又一个方面，提供了一种计算机存储介质，所述介质包括指令，所述指令在运行时执行如前所述的方法。
本发明的集成接口电路包括连接在外接端口与处理器之间、分别对应不同功能的多个功能接口电路。这样，对于单个外接端口而言，其可对应多个功能接口电路。也就是说，单个外接端口通过该多个功能接口电路的适配，可获得功能接口电路或处理器所提供的多个功能(集成功能)，有利地节省了有限的端口资源(即，具有更多的端口资源来满足客户定制化的需求)。另外，不同的功能接口电路之间可具有至少部分重合的电路元件，使得整个集成接口电路更精简，降低了制作成本。
附图说明
从结合附图的以下详细说明中，将会使本发明的上述和其他目的及优点更加完整清楚，其中，相同或相似的要素采用相同的标号表示。
图1示出了根据本发明的一个实施例的集成接口电路的示意图；
图2示出了根据本发明的一个实施例的第三功能接口电路的结构示意图；
图3示出了根据本发明的一个实施例的第一功能接口电路的结构示意图；
图4示出了根据本发明的一个实施例的第二功能接口电路的结构 示意图；
图5示出了根据本发明的另一个实施例的第二功能接口电路的结构示意图；
图6示出了根据本发明的一个实施例的集成接口电路的结构示意图；以及
图7示出了根据本发明的一个实施例的接口电路的制作方法的示意图。
具体实施方式
应理解，这里所使用的术语“车辆”或者其他类似的术语包括各种机动车辆和非机动车辆，例如乘用车(包括运动型多用途车、公共汽车、卡车等)、各种商用车、船舶、飞机、摩托车、自行车等等，并包括混合动力汽车、电动车等。混合动力汽车是一种具有两个或更多个功率源的车辆，例如汽油动力和电动车辆。
虽然将示例性实施例描述为使用多个单元来执行示例性过程，但是应理解，这些示例性过程也可由一个或多个模块来执行。
而且，本发明的控制逻辑可作为可执行程序指令而包含在计算机可读介质上，该可执行程序指令由处理器等实施。计算机可读介质的实例包括，但不限于，ROM、RAM、光盘、磁带、软盘、闪盘驱动器、智能卡和光学数据存储装置。计算机可读记录介质也可分布在连接有网络的计算机系统中，使得例如通过车载远程通信服务或者控制器局域网(CAN)以分布式方式储存并实施计算机可读介质。
除非具体地提到或者从上下文中显而易见，否则如这里使用的，将术语“大约”理解为在本领域中的正常公差的范围内，例如在平均值的2个标准差内。
在下文中，将参考附图详细地描述根据本发明的各示例性实施例的集成接口电路。
图1示出了根据本发明的一个实施例的集成接口电路1000的示意图。如图1所示，集成接口电路1000包括连接在外接端口140与处理器150之间、分别对应不同功能的多个功能接口电路。其中，多 个功能接口电路包括对应第一功能的第一功能接口电路110以及对应第二功能的第二功能接口电路120，并且所述第二功能接口电路120中的电路元件与所述第一功能接口电路110中的电路元件至少部分重合。
在本发明的上下文中，术语“接口电路”表示在外部设备/外接端口与内部处理器之间起连接作用的逻辑电路，是处理器与外部设备进行信息交互的桥梁。接口电路的功能包括但不限于，电平衔接、阻抗匹配、信号处理或“保养”、静电保护、交直流隔离等等。
根据所对应的功能不同，可将接口电路进一步细分为不同的功能接口电路，即第一功能接口电路、第二功能接口电路等。例如，根据接口电路所实现的功能不同，对接口电路进行分类。又例如，根据与处理器所匹配的端口不同，对接口电路进行分类。再例如，根据接口电路所实现的功能以及处理器所实现的功能两者，按所适配或实现的功能不同而对接口电路进行分类。
在本发明的上下文中，术语“外接端口”是与外部设备连接的端口，其可以是用于接收外部输入信号的外接输入端口或者用于向外部传送信号的外接输出接口。“处理器”可以是起到处理功能的任何单元，例如单片机。本领域技术人员可以理解，处理器可提供多个功能，例如各种信号处理、模数转换功能等。另外，处理器可具有多个端口，该不同端口对于输入或输出信号各自具有一定的规格要求。在将集成接口电路1000应用在电子控制单元ECU中时，外接端口140可以是该ECU与外部连接的端口，处理器150可以是该ECU的微处理器。
由于集成接口电路1000包括分别对应不同功能的多个功能接口电路，例如第一功能接口电路110、第二功能接口电路120。这样，对于外接端口140而言，其可对应多个功能接口电路。也就是说，外接端口140通过该多个功能接口电路(的适配)，可获得集成的多个功能，有利地节省了有限的端口资源。换言之，通过在电子控制单元ECU中设置集成接口电路1000，可使该电子控制单元ECU具有更多的端口资源来满足客户定制化的需求。另外，第二功能接口电路120中的电路元件与第一功能接口电路110中的电路元件至少部分重合， 使得整个集成接口电路1000更精简，降低了制作成本。
在一些实施例中，继续参考图1，在上述集成接口电路1000中，多个功能接口电路还可包括用于实现第三功能的第三功能接口电路130(用虚线示出)。其中，第三功能接口电路130中的电路元件与所述第一功能接口电路110或所述第二功能接口电路120中的电路元件均不重合。本领域技术人员可以理解，在集成接口电路1000中可根据需要设置更多或更少的功能接口电路，这些功能接口电路与第一功能接口电路110、第二功能接口电路120和第三功能接口电路130可至少部分重合或完全不重合。
在一个实施例中，第三功能接口电路130对应于处理器150的ADC(模数转换)输入端口。该第三功能接口电路130可包括第一滤波元件、分压元件以及限压元件。其中，第一滤波元件用于对从外接端口接收的外部输入信号进行滤波；分压元件用于与所述第一滤波元件相串联，用于降低经所述第一滤波元件滤波后的外部输入信号的电压；限压元件的一端与所述分压元件相串联，其另一端与所述处理器的对应端子相串联，配置成限制输出到所述处理器的对应端子的电压。在一些实施例中，该第三功能接口电路还可包括：第二滤波元件，所述第二滤波元件与所述分压元件、所述限压元件相串联，用于对经由所述分压元件进行分压后的外部输入信号进行二级滤波。
图2示出了用于适配处理器150的ADC输入端口的第三功能接口电路130的一种结构示意图。如图2所示，第三功能接口电路130包括：由第一电感器L1和第一电容器C1组成的第一滤波元件、由第一电阻器R1和第二电阻器R2组成的分压元件、由第二电容器C2组成的第二滤波单元以及由第一二极管D1组成的限压元件。当然，本领域技术人员可以理解，上述滤波元件、分压元件以及限压元件可根据实际需要包括更多的电路元件，而不限于图2中的具体电路。
继续参考图2，第一电感器L1的第一端与外接端口P1连接，第一电感器L1的第二端与第一电容器C1的第一端连接，第一电容器C1的第二端接地GND1，第一电阻器R1的第一端与第一电感器L1的第二端连接，第一电阻器R1的第二端与第二电阻器R2的第一端连 接，第二电阻器R2的第二端接地GND2，第二电容器C2的第一端与第一电阻器R1的第二端连接，第二电容器C2的第二端接地GND3，第一二极管D1的第一端与第二电容器C2的第一端连接，第一二极管D1的第二端与第一参考电源REF1连接，并且处理器的端口P2(即ADC输入端口)与第一二极管D1的第一端连接。
通过如图2所示的功能接口电路，由第一电感器L1和第一电容器C1组成LC滤波元件(即第一滤波元件)。经过第一电感器L1、第一电容器C1滤波后可得到平滑的直流电，减小纹波电压。而且，这种滤波在电流变化波动变化时候也能起到很好的滤波效果。由第一电阻器R1和第二电阻器R2组成的分压元件能够降低经LC滤波后的外部输入信号的电压。根据需要，设置合适的第一电阻器R1和第二电阻器R2的阻值，可获得在P2端口的理想输出电压。另外，由C2构成的第二滤波元件用于对输出到P2端口的信号进行电容滤波(即二次滤波)，可进一步降低杂波干扰。此外，由于第一参考电源的电压为3.3V，第一二极管D1的导通电压为0.7V，因此端口P2的电压被钳制在4V以下。本领域技术人员可以理解的是，通过将第一参考电源的电压设置在不同值，端口P2的电压可被钳制在相应的不同电压值以下。
在一个实施例中，第一功能接口电路110配置为适配处理器150的输入端口。图3示出了第一功能接口电路110作为适配输入端口的一种结构示意图。如图3所示，所述第一功能接口电路110包括第三电容器C3、第五电阻器R5、第六电阻器R6、第十电阻器R10。其中，所述第三电容器C3的第一端与所述外接端口P1连接，所述第三电容器C3的第二端与第六电阻器R6的第一端连接，所述第五电阻器R5的第一端与所述外接端口P1连接，所述第五电阻器R5的第二端与所述第六电阻器R6的第二端连接，所述第十电阻器R10的第一端与所述第五电阻器R5的第二端连接，所述第十电阻器R10的第二端与所述处理器的第二端口P3(例如通用的输入输出接口GPIO)连接。图3所示的第一功能接口电路110通过合理设置各个电路元件的电容值和电阻值后能起到很好的限流作用，例如对于P1端输入为低频信号 (例如直流信号)时，由于第三电容器C3的存在，因此直流电流不会通过由第三电容器C3与第六电阻器R6组成分支，而仅流经第五电阻器R5以及第十电阻器R10。假定第五电阻器为大电阻，则输出到P3端口的电流被很好地限制。
在一个实施例中，第二功能接口电路120配置为实现“反向输出”的功能，并适配处理器150的输出端口。
图4示出了第二功能接口电路120的一个结构示意图。如图4所示，第二功能接口电路120包括第三电容器C3、第三电阻器R3、第一三极管T1、第四电阻器R4、第六电阻器R6以及第十电阻器R10。其中，所述第三电容器C3的第一端与所述外接端口P1连接，所述第三电容器C3的第二端与第六电阻器R6的第一端连接，所述第三电阻器R3的第一端与第二参考电源REF2连接，所述第三电阻器R3的第二端与所述外接端口P1连接，所述第一三极管T1的集电极与所述第三电阻器R3的第二端连接，所述第一三级管T1的基极与所述第六电阻器R6的第二端连接，所述第一三极管T1的发射极与第四电阻器R4的第一端连接，所述第四电阻器R4的第二端与所述第三电容器C3的第二端连接并接地GND5，所述第十电阻器R10的第一端与所述第一三极管T1的基极连接，所述第十电阻器R10的第二端与所述处理器的第二端口P3(例如通用的输入输出接口GPIO)连接。
通过图4的电路，外接端口P1的电平将随着处理器的输出端口P3的电平而反向变化。即，当端口P3为高电平时，外接端口P1显示为低电平，而当端口P3为低电平时，外接端口P1显示为高电平。例如，当端口P3为低电平时，第一三极管T1关断，P1端的电压约等于第二参考电压REF2(即约为5V)，因此为高电平。而当端口P3为高电平时，第一三极管T1导通，第四电阻器R4与第六电阻器R6并联，其等效电阻值与第三电阻器R3、第十电阻器R10不可比拟，因此在外接端口P1上所分的电压很低(即低电平)。
另外，需要指出的是，图4所示出的第二功能接口电路与图3示出的第一功能接口电路中的电路元件存在部分重合。重合的元件包括第三电容器C3、第六电阻器R6以及第十电阻器R10。
在一个实施例中，第二功能接口电路120配置为实现“正向输出”的功能，并适配处理器150的输出端口。
图5示出了第二功能接口电路120的另一个结构示意图。如图5所示，第二功能接口电路120包括第三电容器C3、第五电阻器R5、第六电阻器R6、第七电阻器R7、第八电阻器R8、第二三极管T2、第三三极管T3以及第九电阻器R9。其中，所述第三电容器C3的第一端与所述外接端口P1连接，所述第三电容器C3的第二端与第六电阻器R6的第一端连接并接地GND5，所述第五电阻器R5的第一端与所述外接端口P1连接，所述第五电阻器R5的第二端与第六电阻器R6的第二端连接，所述第七电阻器R7的第一端与第三参考电源REF3连接，所述第七电阻器R7的第二端与第二三极管T2的发射极连接，所述第八电阻器R8的第一端与第三参考电源REF3连接，所述第八电阻器R8的第二端与第二三极管T2的基极连接，所述第二三极管T2的集电极与所述第六电阻器R6的第二端连接，所述第三三极管T3的集电极与所述第二三极管T2的基极连接，所述第三三极管T3的基极与第九电阻器R9的第一端连接，所述第三三极管T3的发射极接地GND4，所述第九电阻器R9的第二端与所述第六电阻器R6的第二端连接，所述第九电阻器R9的第二端还与所述处理器的第二端口P3(例如通用的输入输出接口GPIO)连接。
通过图5的电路，外接端口P1的电平将随着处理器的输出端口P3的电平而同向变化。即，当端口P3为高电平时，外接端口P1显示为高电平，而当端口P3为低电平时，外接端口P1显示为低电平。例如，当端口P3为低电平时，第二三极管T2以及第三三极管T3关断，P1端的电压约等于P3端的电压，因此也为低电平。而当端口P3为高电平时，第二三极管T2以及第三三极管T3导通，在外接端口P1上的电压约等于P3端口的电压(即高电平)。
另外，需要指出的是，图5所示出的第二功能接口电路与图3示出的第一功能接口电路中的电路元件存在部分重合。重合的元件包括第三电容器C3、第五电阻器R5以及第六电阻器R6。
图6示出了根据本发明的一个实施例的集成接口电路的结构示意 图，该集成接口电路涵盖了图2所示的第三功能接口电路130、图3所示的第一功能接口电路110、图4和图5所示的第二功能接口电路120。该集成接口电路包括了分别对应不同功能的多个功能接口电路，例如第一功能接口电路110、第二功能接口电路120以及第三功能接口电路130。这样，对于外接端口P1而言，其可对应多个功能接口电路。也就是说，外接端口P1通过该多个功能接口电路(的适配)，可获得集成的多个功能，有利地节省了有限的端口资源。另外，该集成接口电路通过复用不同功能接口电路中的电路元件，使得整个集成接口电路更精简，降低了制作成本。
尽管图6中未示出，在一些实施例中，上述集成接口电路还可包括选择器，该选择器用于根据控制信号从多个功能接口电路中选择对应的功能接口电路。
图7示出了根据本发明的一个实施例的接口电路的制作方法7000的示意图。如图7所示，接口电路的制作方法7000包括如下步骤：
在步骤S710中，确定所述接口电路所对应的功能；以及
在步骤S720中，根据所确定的功能，从上述集成接口电路中选择对应的功能接口电路进行填充。
在一些实施例中，步骤S710中的确定接口电路所对应的功能可通过接收外部控制信号而实现。进一步，在确定功能后，则选择填充对应的功能接口电路。例如，当确定接口电路对应的是ADC功能后，第三功能接口电路的电路元件(即图2中所示出的第一电感器L1、第一电阻器R1、第一二极管D1、第一电容器C1、第二电阻器R2以及第二电容器C2)被选择填充。
集成接口电路作为示例可位于电子控制单元ECU中。所谓“电子控制单元”，又称“行车电脑”、“车载电脑”等，从用途上说，是车辆专用微机控制器。在将集成接口电路应用在电子控制单元ECU中时，外接端口可以是该ECU与外部连接的端口，处理器可以是该ECU的微处理器。由于集成接口电路包括分别对应不同功能的多个功能接口电路，例如第一功能接口电路、第二功能接口电路等。这样，对于外接端口而言，其可对应多个功能接口电路。也就是说，外接端 口通过该多个功能接口电路(的适配)，可获得集成的多个功能，有利地节省了有限的端口资源。换言之，通过在电子控制单元ECU中设置集成接口电路1000，可使该电子控制单元ECU具有更多的端口资源来满足客户定制化的需求。
以上例子主要说明了本发明的集成接口电路。尽管只对其中一些本发明的实施方式进行了描述，但是本领域普通技术人员应当了解，本发明可以在不偏离其主旨与范围内以许多其他的形式实施，例如参考电源根据实际需要而设置为不同的电压值。因此，所展示的例子与实施方式被视为示意性的而非限制性的，在不脱离如各权利要求所定义的本发明精神及范围的情况下，本发明可能涵盖各种的修改与替换。

Claims (17)

  1. 一种集成接口电路，其特征在于，所述集成接口电路包括：
    连接在外接端口与处理器之间、分别对应不同功能的多个功能接口电路，
    其中，所述多个功能接口电路包括对应第一功能的第一功能接口电路以及对应第二功能的第二功能接口电路，并且所述第二功能接口电路中的电路元件与所述第一功能接口电路中的电路元件至少部分重合。
  2. 如权利要求1所述的集成接口电路，其中，所述多个功能接口电路还包括用于对应第三功能的第三功能接口电路，其中，所述第三功能接口电路中的电路元件与所述第一功能接口电路或所述第二功能接口电路中的电路元件均不重合。
  3. 如权利要求1所述的集成接口电路，其中，所述外接端口为用于接收外部输入信号的外接输入端口或者用于向外部传送信号的外接输出接口。
  4. 如权利要求1所述的集成接口电路，其中，所述处理器为单片机。
  5. 如权利要求2所述的集成接口电路，其中，所述第三功能接口电路包括：
    第一滤波元件，用于对从外接端口接收的外部输入信号进行滤波；
    分压元件，与所述第一滤波元件相串联，用于降低经所述第一滤波元件滤波后的外部输入信号的电压；以及
    限压元件，所述限压元件的一端与所述分压元件相串联，所述限压元件的另一端与所述处理器的对应端子相串联，所述限压元件配置成限制输出到所述处理器的对应端子的电压。
  6. 如权利要求5所述的集成接口电路，其中，所述第三功能接口电路还包括：
    第二滤波元件，所述第二滤波元件与所述分压元件、所述限压元 件相串联，用于对经由所述分压元件进行分压后的外部输入信号进行二级滤波。
  7. 如权利要求6所述的集成接口电路，其中，所述第三功能接口电路包括：
    包含第一电感器和第一电容器的所述第一滤波元件，其中，所述第一电感器的第一端与所述外接端口连接，所述第一电感器的第二端与所述第一电容器的第一端连接，并且所述第一电容器的第二端接地；
    包含第一电阻器和第二电阻器的所述分压元件，其中所述第一电阻器的第一端与所述第一电感器的第二端连接，所述第一电阻器的第二端与所述第二电阻器的第一端连接，所述第二电阻器的第二端接地；
    包含第二电容器的所述第二滤波元件，其中，所述第二电容器的第一端与所述第一电阻器的第二端连接，并且所述第二电容器的第二端接地；
    包含第一二极管的限压元件，所述第一二极管的第一端与所述第二电容器的第一端连接，所述第一二极管的第二端与第一参考电源连接，并且所述处理器的第一端口与所述第一二极管的第一端连接。
  8. 如权利要求1所述的集成接口电路，其中，所述第一功能接口电路包括：
    第三电容器，其中所述第三电容器的第一端与所述外接端口连接，所述第三电容器的第二端与第六电阻器的第一端连接；
    第五电阻器，其中所述第五电阻器的第一端与所述外接端口连接，所述第五电阻器的第二端与所述第六电阻器的第二端连接；
    第六电阻器；以及
    第十电阻器，所述第十电阻器的第一端与所述第五电阻器的第二端连接，所述第十电阻器的第二端与所述处理器的第二端口连接。
  9. 如权利要求8所述的集成接口电路，其中，所述第二功能接口电路与所述第一功能接口电路重合的元件包括所述第三电容器、所述第六电阻器以及所述第十电阻器。
  10. 如权利要求9所述的集成接口电路，其中，所述第二功能接口电路包括：
    第三电容器，其中，所述第三电容器的第一端与所述外接端口连接，所述第三电容器的第二端与第六电阻器的第一端连接；
    第三电阻器，其中，所述第三电阻器的第一端与第二参考电源连接，所述第三电阻器的第二端与所述外接端口连接；
    第一三极管，所述第一三极管的集电极与所述第三电阻器的第二端连接，所述第一三级管的基极与所述第六电阻器的第二端连接，所述第一三极管的发射极与第四电阻器的第一端连接；
    第四电阻器，所述第四电阻器的第二端与所述第三电容器的第二端连接并接地；
    第六电阻器；以及
    第十电阻器，所述第十电阻器的第一端与所述第一三极管的基极连接，所述第十电阻器的第二端与所述处理器的第二端口连接。
  11. 如权利要求8所述的集成接口电路，其中，所述第二功能接口电路与所述第一功能接口电路重合的元件包括所述第三电容器、所述第五电阻器以及所述第六电阻器。
  12. 如权利要求11所述的集成接口电路，其中，所述第二功能接口电路包括：
    第三电容器，其中所述第三电容器的第一端与所述外接端口连接，所述第三电容器的第二端与第六电阻器的第一端连接；
    第五电阻器，其中所述第五电阻器的第一端与所述外接端口连接，所述第五电阻器的第二端与第六电阻器的第二端连接；
    第六电阻器；
    第七电阻器，所述第七电阻器的第一端与第三参考电源连接，所述第七电阻器的第二端与第二三极管的发射极连接；
    第八电阻器，所述第八电阻器的第一端与第三参考电源连接，所述第八电阻器的第二端与第二三极管的基极连接；
    第二三极管，所述第二三极管的集电极与所述第六电阻器的第二端连接；
    第三三极管，所述第三三极管的集电极与所述第二三极管的基极连接，所述第三三极管的基极与第九电阻器的第一端连接，所述第三三极管的发射极接地；以及
    第九电阻器，所述第九电阻器的第二端与所述第六电阻器的第二端连接，所述第九电阻器的第二端还与所述处理器的第二端口连接。
  13. 如权利要求1或2所述的集成接口电路，其中，所述集成接口电路还包括：
    选择器，用于根据控制信号从所述多个功能接口电路中选择对应的功能接口电路。
  14. 一种接口电路的制作方法，其特征在于，所述方法包括：
    确定所述接口电路对应的功能；以及
    根据所确定的功能，从如权利要求1至13中任一项所述的集成接口电路中选择对应的功能接口电路进行填充。
  15. 一种电子控制单元，包括如权利要求1至13中任一项所述的集成接口电路。
  16. 一种车辆，包括如权利要求15所述的电子控制单元。
  17. 一种计算机存储介质，其特征在于，所述介质包括指令，所述指令在运行时执行如权利要求14所述的方法。
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