WO2021179504A1 - 电路板结构和电子设备 - Google Patents

电路板结构和电子设备 Download PDF

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Publication number
WO2021179504A1
WO2021179504A1 PCT/CN2020/101905 CN2020101905W WO2021179504A1 WO 2021179504 A1 WO2021179504 A1 WO 2021179504A1 CN 2020101905 W CN2020101905 W CN 2020101905W WO 2021179504 A1 WO2021179504 A1 WO 2021179504A1
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WO
WIPO (PCT)
Prior art keywords
area
pad
pads
circuit board
chip mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/101905
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English (en)
French (fr)
Inventor
史洪宾
陈曦
涂海生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to EP20924183.5A priority Critical patent/EP4096371A4/en
Publication of WO2021179504A1 publication Critical patent/WO2021179504A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09381—Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch or thickness; Using different connections on the pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09409—Multiple rows of pads, lands, terminals or dummy patterns; Multiple rows of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09418—Special orientation of pads, lands or terminals of component, e.g. radial or polygonal orientation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/303—Assembling printed circuits with electric components, e.g. with resistors with surface mounted components
    • H05K3/305—Affixing by adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts

Definitions

  • This application relates to the technical field of circuit boards, and in particular to circuit board structures and electronic equipment used for welding chips.
  • the present application provides a circuit board structure, which solves the problem of mechanical reliability of the connection between the circuit board structure and the chip through the pad design of the circuit board structure.
  • the present application provides a circuit board structure including a main body and a plurality of pads, the surface of the main body is provided with a chip mounting area, and the plurality of pads includes at least one first pad and a plurality of second solder pads. Disk, the at least one first pad is located at a corner position close to the chip mounting area, and the plurality of second pads are distributed in the central area of the chip mounting area and the at least one first pad Around, the area of the first pad is greater than twice the area of the second pad, and the first pad is used for welding at least two independent pads on the chip side.
  • the present application solves the mechanical reliability of the connection between the large-size chip and the circuit board structure by arranging the first pad in the edge area of the chip mounting area, and the area of the first pad is larger than twice the area of the second pad.
  • the problem specifically, when the circuit board structure is dropped, the edge area pad is subjected to greater stress, the reliability is poor, and the pad is prone to cracking. Therefore, arranging the large-size first pad in the edge area increases the bonding of the pad and the pad.
  • the bonding area of the main body of the chip and the circuit board structure prevents the pad from cracking when it is dropped, which is beneficial to improve the mechanical reliability of the connection between the chip and the circuit board structure.
  • the amount of glue between the chip and the circuit board structure can be reduced or even no glue can be dispensed, which effectively avoids the presence of glue component solder joint repair and dewetting in the pad dispensing between the chip and the circuit board structure Wetness, adhesive failure of sensitive components, increased cost and process complexity.
  • the at least one first pad is electrically connected to the ground layer of the main body; or, the at least one first pad is a non-functional pad; or, the at least one first pad is The pad is a network function pad.
  • the at least one first pad can be a ground pad, or a non-functional pad or a network functional pad.
  • the ground pad is connected to the ground layer of the main body, and the non-functional pads are usually arranged at the four corners of the chip mounting area.
  • the position of the outer ring and the outer ring play the purpose of physically connecting the chip and the circuit board structure, which is used to protect the functional pads inside the chip from breaking first when subjected to mechanical and environmental stress, which affects the product function. Multiple devices with the same network function
  • the independent pads can be combined to form a large-sized first pad.
  • the chip mounting area includes a first side area, a second side area, a third side area, and a fourth side area that are located at the periphery of the central area and connected in sequence.
  • the first side area and the third side area are oppositely arranged on both sides of the central area, and the second side area and the fourth side area are oppositely arranged on both sides of the central area,
  • the first pads that are electrically connected to the ground layer of the main body are distributed in the first side area and the third side area, and the network function pads are distributed in the second side area and the third side area.
  • the fourth side area is a first side area, a second side area, a third side area, and a fourth side area that are located at the periphery of the central area and connected in sequence.
  • the first side area and the third side area are oppositely arranged on both sides of the central area
  • the second side area and the fourth side area are oppositely arranged on both sides of the central area
  • the network function pad is electrically connected to the signal layer of the main body.
  • the chip mounting area has a square shape
  • the first pads are distributed at four corners of the chip mounting area
  • the size of each first pad is the same as that of the second pad. Two to four times the size of the pad.
  • the corner pads are prone to cracking when subjected to mechanical and environmental stress.
  • the large-size first pads are distributed in the four corner positions to improve the mechanical reliability of the connection between the chip and the circuit board structure.
  • the chip mounting area is square, the chip mounting area is divided into N*N matrix areas, the first pads are located at four corners of the chip mounting area, and The first pads are distributed in an 8*8 matrix area. Since the pads in the 8*8 matrix area at the corner position are prone to cracking, the large-size first pads distributed in the matrix area at each corner position 8*8 can improve the mechanical connection between the chip and the circuit board structure. reliability.
  • the chip mounting area includes the central area and an edge area
  • the edge area is frame-shaped and surrounds the central area
  • multiple circles of the pads are distributed in the edge area
  • the second A pad is distributed in the edge area
  • a solder resist layer is provided around the pad located on the outermost circle, and the solder resist layer covers the edge of the pad.
  • the chip mounting area is provided with a glue dispensing opening
  • the glue dispensing opening is located at a corner of the chip mounting region
  • glue is dispensed in a partial area of the chip mounting region.
  • the arrangement of the first pad improves the mechanical reliability of the connection between the chip and the circuit board structure. In order to achieve higher mechanical reliability, it can be performed in an area where the size of the first pad is small or the number of first pads is small. A small amount of local dispensing.
  • glue is dispensed in the area between the three corner positions of the chip mounting area and two adjacent corner positions along the side length direction of the chip mounting area.
  • the shape of the first pad is one or more of a long strip, a triangle, a square, a parallelogram, a trapezoid, a polygon, a circle, an L shape, and a V shape.
  • the shape of the pad can be set as required.
  • the present application provides an electronic device, including a chip and the circuit board structure described in any one of the above implementations, and the chip is mounted at the plurality of pads in the chip mounting area.
  • the circuit board structure provided by the present application solves the mechanical reliability problem of the connection between the large-size chip and the circuit board structure, and can reduce the amount of glue between the chip and the circuit board structure or even no glue, which effectively avoids the chip
  • the bonding pads between the printed circuit board structure and the circuit board structure have problems such as rework and wetting of the solder joints of the dispensing components, adhesive failure of sensitive components, short circuit of the dendrites of the solder joints with high temperature and high humidity, capacitor whistling, increased cost and process complexity.
  • FIG. 1 is a schematic diagram of an application environment of a circuit board structure provided by an implementation manner of the present application
  • FIG. 2 is a schematic structural diagram of a chip soldered to a circuit board provided by an implementation manner of the present application
  • FIG. 3a is a schematic diagram of a circuit board structure provided by an implementation manner of the present application.
  • FIG. 3b is a schematic diagram of a structure in which the pads on the chip side and the first pads of the circuit board provided in an implementation manner of the present application are arranged correspondingly;
  • FIG. 4 is a schematic structural diagram of a ground pad connected to a ground layer provided by an implementation manner of the present application
  • FIG. 5 is a schematic diagram of a non-functional pad distribution structure provided by an implementation manner of the present application.
  • FIG. 6 is a schematic diagram of a distribution structure of a network function pad provided by an implementation manner of the present application.
  • FIG. 7 is a schematic diagram of the distribution structure of different types of pads provided by an implementation manner of the present application.
  • FIG. 8 is a schematic diagram of a circuit board structure provided by another implementation manner of the present application.
  • FIG. 9 is a schematic diagram of the structure of a first pad distribution area provided by an implementation manner of the present application.
  • FIG. 10 is a schematic diagram of the structure of the first pad distribution area provided by another implementation manner of the present application.
  • FIG. 11 is a schematic diagram of a partial glue dispensing structure of a circuit board structure provided by an implementation manner of the present application.
  • FIG. 12 is a schematic diagram of the structure of a pad provided with a solder resist layer provided by an implementation manner of the present application.
  • FIG. 13 is a schematic diagram of the structure of a solder mask provided by an implementation manner of the present application.
  • the electronic device 10 includes a chip 20 and a circuit board structure 30.
  • the electronic device 10 can be a mobile phone, a watch, a tablet computer, etc.
  • the chip 20 can be a packaged chip, a power management chip, and the like.
  • One side of the chip 20 is provided with a chip pad 210, and one side of the circuit board structure 30 is provided with a large-sized first pad 311 and a small-sized second pad 312.
  • each independent small-sized second pad 312 in the center area of the circuit board structure 30 corresponds to the die pad 210 of the chip 20 one-to-one, and the large-sized first pads in the edge area of the circuit board structure 30
  • the disk 311 corresponds to at least two die pads 210.
  • the area of the large-sized first pad 311 in the edge area is larger than the area of the small-sized second pad 312 in the central area, which enhances the mechanical reliability of the connection between the chip 20 and the circuit board structure 30, so that the chip 20 is in the circuit board structure.
  • the installation of 30 is more stable, preventing the pad 310 from cracking when dropped, and the chip 20 is disconnected from the circuit board structure 30, which affects the function of the electronic device 10.
  • the chip 20 is soldered to the circuit board structure 30 by solder. After the chip 20 is mounted on the circuit board structure 30, the solder forms solder balls (refer to FIG. 2, large-size solder balls 317 and small-size solder balls 318).
  • the solder balls 317 on the side adjacent to the chip 20 correspond to at least two chip pads 210, and each large-sized solder ball 317 is adjacent to a large-sized first pad 311 in the edge area on the side of the circuit board structure 30, and each small-sized solder ball 317
  • the solder balls 318 adjacent to the chip 20 correspond to a chip pad 210, and each small solder ball 318 adjacent to the circuit board structure 30 corresponds to a small second pad 312 in the central area (see FIG. 1).
  • the circuit board structure 30 includes a main body 320 and a plurality of pads 310.
  • the surface of the main body 320 is provided with a chip mounting area 330.
  • the chip mounting area 330 is square.
  • the chip mounting area 330 includes a central area 331 and an edge area 332 (that is, at the edge position).
  • the edge area 332 is frame-shaped and surrounds the central area 331.
  • a plurality of pads 310 are distributed in the area 332, and the plurality of pads 310 include at least one first pad 311 and a plurality of second pads 312, and at least one first pad 311 is located in the edge area 332 of the chip mounting area 330.
  • a plurality of second pads 312 are distributed around the central area 331 of the chip mounting area 330 and at least one first pad 311, and the area of the first pad 311 is larger than twice the area of the second pad 312, the first The bonding pads 311 are used for bonding at least two independent chip bonding pads 210 on the chip side.
  • the first bonding pad 311 may correspond to the two independent chip bonding pads 210 (see FIG. 3b, that is, the rectangular second in FIG. 3b).
  • One pad 311), the first pad 311 may also correspond to four independent die pads 210 (refer to FIG. 3b, that is, the triangular first pad 311 in FIG. 3b).
  • the chip 20 is mounted and fixed on the circuit board structure 30.
  • the pad 310 on the edge area 332 is affected by Larger stress, poor reliability, and susceptibility to cracking, cause the connection between the large-size chip 20 and the circuit board structure 30 to be disconnected, which affects the function of the product.
  • the large-sized first pad 311 is arranged in the edge area 332, which increases the bonding area of the pad and the chip mounting area 330 on the surface of the chip 20 and the main body 320 of the circuit board structure 30, making the pads in the edge area difficult.
  • the cracking is beneficial to improve the mechanical reliability of the connection between the chip 20 and the circuit board structure 30, and effectively avoids the cracking of the bonding pads and the disconnection between the large-sized chip 20 and the circuit board structure 30 when dropped.
  • the area of the first pad 311 is greater than twice the area of the second pad 312.
  • increasing the area of the first pad 311 is beneficial to improve the mechanical reliability of the connection between the chip 20 and the circuit board structure 30.
  • At least one first pad may be a ground pad 313, and the ground pad 313 is electrically connected to the ground layer 321 of the main body 320 (see FIG. 4); at least one first pad may be non-functional
  • the pads 314 and the non-functional pads 314 are usually arranged at the four corner positions and the outer ring position of the chip mounting area 330 to physically connect the chip 20 and the circuit board structure 30 to protect the functional pads inside the chip 20 It will not be the first to break when subjected to mechanical and environmental stress, which will affect the product function (see FIG. 5); at least one of the first pads can be the network function pad 315, which is electrically connected to the signal layer 322 of the main body 320 , The pads with the same network function can be combined to form a large-size first pad (see Figure 6).
  • multiple independent ground pads 313, or multiple independent non-functional pads 314, or multiple independent network functional pads 315 with the same network function can be combined into one large
  • the size of the first pad 311 it can be understood that, compared to the use of multiple independent pads, the combination reduces the number of pads on the circuit board structure 30.
  • the processing cost of the circuit board structure 30 is usually lower than that of the pads. The quantity is related. The more the number of pads, the higher the cost. Therefore, reducing the number of pads after merging (that is, using a large-sized first pad) is beneficial to reducing the processing cost of the circuit board structure 30.
  • the first pads are mainly distributed in the edge area 332.
  • Multiple independent ground pads can be combined into a large-size ground pad 313 (that is, the first pad is the ground pad 313), and multiple independent pads of the same functional network can be combined into a large-size same network
  • the functional pad 315 (that is, the first pad is the same network functional pad 315).
  • the chip mounting area 330 includes a first side area 3321, a second side area 3322, a third side area 3323 and a fourth side area 3324 which are located at the periphery of the central area 331 and are connected in sequence.
  • the three side regions 3323 are relatively disposed on both sides of the central region 331, the second side region 3322 and the fourth side region 3324 are relatively disposed on both sides of the center region 331, and are electrically connected to the first pad ( That is, the large-sized ground pads 313) are mainly distributed in the first side area 3321 and the third side area 3323, and the same network function pads 315 are mainly distributed in the second side area 3322 and the fourth side area 3324.
  • the chip mounting area 330 with a square structure is divided into N*N matrix areas, and the first pads 311 are located at the four corners of the chip mounting area 330. Due to the corner positions of the 8*8 matrix The pads in area C1, 8*8 matrix area C2, 8*8 matrix area C3, 8*8 matrix area C4 are prone to cracking, so the large-size first pads 311 are mainly distributed in four corner positions
  • the 8*8 matrix area C1, 8*8 matrix area C2, 8*8 matrix area C3, 8*8 matrix area C4 can improve the mechanical reliability of the connection between the chip 20 and the circuit board structure 30 (see Figure 8).
  • the first pads 311 are distributed in four corner positions of the square chip mounting area 330, and the size of each first pad 311 is two to four times the size of the second pad 312.
  • the flow direction of the solder during the soldering process is uncontrollable, resulting in poor soldering effect consistency, and poor soldering such as separation of solder and device-side pads.
  • the pads at the corners are prone to cracking when subjected to mechanical and environmental stress.
  • the first pads 311 distributed in the four corners are formed by combining two to four second pads 312, and the first pads 311 are distributed on The four corner positions are beneficial to improve the mechanical reliability of the connection between the chip 20 and the circuit board structure 30 and enhance the connection strength between the chip 20 and the circuit board structure 30.
  • the size of the chip when the size of the chip is large, independent pads need to be combined to form a first pad with a larger size.
  • the length of the chip is L and the width is W.
  • the chip mounting area 330 is divided into N*N matrix areas.
  • L*W>11mm*11mm the outermost 3 circles and the outermost corners of the edge area of the N*N matrix 5 Rows of pads are used to merge to form a large-size first pad (refer to FIG. 9, that is, the first pad can be located at the boundary B1, boundary B2, and boundary B3 between the octagonal dashed frame 335 and the chip mounting area 330 in FIG.
  • the area between the boundary B4) when 11mm*11mm ⁇ L*W>8mm*8mm, the outermost 2 circles of the edge area of the N*N matrix and the outermost 3 rows of pads at the corners are used to merge to form a large size
  • the first pad (refer to FIG. 10, that is, the first pad can be located in the area between the octagonal dashed box 335 and the boundary B1, boundary B2, boundary B3, and boundary B4 of the chip mounting area 330 in FIG. 10), when L*W ⁇ 8mm*8mm, since the size of the chip 20 is small (that is, the size of the chip mounting area is small), the first pad may not be provided, that is, multiple independent pads may not be combined.
  • arranging a large-sized first pad 311 in the edge area improves the mechanical reliability of the connection between the chip 20 and the circuit board structure 30.
  • a small amount of local glue is applied to an area where the size of the pad 311 is small or the number of the first pads 311 is small (refer to FIG. 11, that is, the glue area 333) to further enhance the mechanical reliability.
  • the chip mounting area 330 Dispensing ports 334 are provided. The dispensing ports 334 are located at the corners of the chip mounting area 330, the three corners of the chip mounting area 330 and the neighbors along the side length direction of the chip mounting area (that is, the boundary B1 and the boundary B2) Dispense glue in the area between the two corner positions.
  • the vertical distance between the inner boundary A1 of the glue area 333 and the boundary B1 of the chip mounting area 330 is less than half the length of the boundary B2, and the vertical distance between the inner boundary A2 of the glue area 333 and the boundary B2 of the chip mounting area 330 is less than Half the length of boundary B1.
  • this application passes the A large-size first pad 311 is provided in the edge area, so that the connection strength between the chip 20 and the circuit board structure 30 is significantly enhanced (that is, the mechanical reliability is increased).
  • the distance between the chip 20 and the circuit board structure 30 is greater than 50%. % Or even smaller area is filled with glue to ensure the mechanical reliability when falling, effectively reducing the difficulty of realizing the glue dispensing effect.
  • the specific dispensing position should also consider the results of pad drop stress simulation and pad slicing. The area where the simulation stress is higher and the slicing has found that the functional pad is completely broken should be given priority.
  • the shape of the first pad 311 may be one or more of a long strip, a triangle, a square, a parallelogram, a trapezoid, a polygon, a circle, an L shape, and a V shape.
  • the shape of the pad 311 can be arranged in the edge area of the chip mounting area as required.
  • the first pads 311 are distributed in the edge area 332, and are located in independent pads on the outer circle (the circles in Figure 12 all indicate the pads, and the large circles on the outside indicate the solder masks.
  • Pad (SMD, solder mask define) 3121 the small circle on the inside represents an independent pad (NSMD, non-solder mask define) without a solder mask layer (NSMD, non-solder mask define), that is, the second pad 312) and the surroundings of the first pad 311 With a solder mask 316.
  • NSMD solder mask define
  • the solder resist layer 316 covers the upper surface of the edge of the first pad 311, and the solder resist layer 316 and the upper surface of the first pad 311 together form a limit.
  • the position space that is, a groove structure is formed
  • the solder ball 317 is located in the limit space, and the solder fills the limit space when the solder ball 317 is soldered, so as to enhance the bonding force between the solder ball 317 and the first pad 311.
  • the setting of the solder resist layer around the independent pads of the outer ring is the same as the setting of the solder resist layer around the first pad 311.
  • the solder resist layer is formed around the independent pads of the outer ring to form a solder resist layer. Land 3121.
  • the height of the solder ball 317 corresponding to the first pad 311 that is, the multiple independent pads 310 are combined into a large-sized first pad 311), for example, 80um (the solder ball 317 is The chip 20 is soldered to the solder on the pad of the circuit board structure 30.
  • the height of the solder ball 317 refers to the solder size of the solder ball 317 in the direction perpendicular to the main body of the circuit board structure).
  • the height of the solder ball in the pad is, for example, 180 um, and the height of the solder ball 317 can also be set according to specific requirements.
  • the large-size first pad 311 is provided on the edge area 332, and the solder resist layer 316 is provided on the outer ring and corners to effectively improve the mechanical reliability, so that the chip and the circuit board can not be used.
  • Dispensing can meet the mechanical reliability requirements of the product, and it can effectively avoid the solder joints of the dispensing components between the chip and the circuit board structure from being reworked and dewetting, the adhesive failure of sensitive components, and high temperature and high humidity solder joints. Crystal short circuit, capacitor whistling, increased cost, and process complexity. Specifically, because there is no glue, there is no glue with high thermal expansion coefficient during heating and repair, which will not cause the chip to melt.
  • the humidity is lower than that in the dispensing cavity scene, so the growth rate of dendrites can be reduced, and there is no problem of short circuit of high temperature and high humidity solder joints; simulation shows that the vibration amplitude of a certain capacitor before dispensing is only dispensing In the case of 1/3500, so the degree of capacitive howling can usually be achieved without glue is not enough for the human ear to perceive.
  • the present application solves the mechanical reliability problem of the connection between the large-size chip and the circuit board structure by arranging the first pad in the edge area of the chip mounting area, and the size of the first pad is larger than the size of the second pad.
  • the enhancement of mechanical reliability can reduce the amount of glue between the chip and the circuit board structure or even no glue, which effectively avoids the solder joints between the chip and the circuit board structure from being reworked and wetting. , Sensitive components adhesive failure, high-temperature and high-humidity solder joint dendritic short circuit, capacitor whistling, increased cost and process complexity and other issues.

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Abstract

一种电路板结构（30），包括主体（320）和多个焊盘（310），主体（320）表面设有芯片安装区（330），多个焊盘（310）包括至少一个第一焊盘（311）和多个第二焊盘（312），至少一个第一焊盘（311）位于靠近芯片安装区（330）的边角位置处，多个第二焊盘（312）分布在芯片安装区（330）的中心区域（331）及至少一个第一焊盘（311）的周围，第一焊盘（311）的面积大于第二焊盘（312）的面积的二倍，第一焊盘（311）用于焊接芯片（20）侧的至少两个独立的焊盘（310）。该电路板设置第一焊盘（311）于芯片安装区（330）的边缘区域（332），且第一焊盘（311）的面积大于第二焊盘（312）的面积的二倍，该设计增加了焊盘（310）与芯片（20）的结合面积，解决了芯片（20）与电路板结构（30）之间连接的机械可靠性问题，可以减少芯片（20）与电路板结构（30）之间的点胶量甚至不点胶，避免了点胶存在点胶元件焊点返修退润湿、敏感元件粘胶失效、增加成本等问题。

Description

电路板结构和电子设备
本申请要求在2020年3月13日提交中国国家知识产权局、申请号为202020317937.2的中国专利申请的优先权，发明名称为“电路板结构和电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及电路板技术领域，特别涉及用于焊接芯片的电路板结构和电子设备。
背景技术
为解决AP(Application Processor,应用处理器)和UFS(Universal Flash Storage,通用闪存存储)等大尺寸芯片的焊点机械可靠性问题，而在芯片和PCB之间的焊点点胶存在点胶元件焊点返修退润湿、敏感元件粘胶失效、增加成本和工艺复杂性等问题。需要开发替代点胶的芯片与电路板结构处的机械可靠性提升技术。
实用新型内容
本申请提供一种电路板结构，通过电路板结构的焊盘设计，解决了电路板结构与芯片之间连接的机械可靠性的问题。
第一方面，本申请提供一种电路板结构，包括主体和多个焊盘，所述主体表面设有芯片安装区，所述多个焊盘包括至少一个第一焊盘和多个第二焊盘，所述至少一个第一焊盘位于靠近所述芯片安装区的边角位置处，所述多个第二焊盘分布在所述芯片安装区的中心区域及所述至少一个第一焊盘的周围，所述第一焊盘的面积大于所述第二焊盘的面积的二倍，所述第一焊盘用于焊接芯片侧的至少两个独立的焊盘。
本申请通过设置第一焊盘于芯片安装区的边缘区域，且第一焊盘的面积大于第二焊盘的面积的二倍，解决了大尺寸芯片与电路板结构之间连接的机械可靠性问题，具体而言，在电路板结构跌落时，边缘区域焊盘受到较大的应力，可靠性差，焊盘易于开裂，因此，将大尺寸的第一焊盘设置在边缘区域增加了焊盘与芯片及电路板结构的主体的结合面积，防止跌落时，焊盘开裂，有利于提高芯片与电路板结构连接的机械可靠性。由于机械可靠性的增强，可以减少芯片与电路板结构之间的点胶量甚至不点胶，有效的避免了在芯片和电路板结构之间的焊盘点胶存在点胶元件焊点返修退润湿、敏感元件粘胶失效、增加成本和工艺复杂性等问题。
一种可能的实现方式中，所述至少一个第一焊盘电连接至所述主体的接地层；或者，所述至少一个第一焊盘为非功能焊盘；或者，所述至少一个第一焊盘为网络功能焊盘。换言之，至少一个第一焊盘可以为接地焊盘，或非功能焊盘或网络功能焊盘，接地焊盘连接至主体的接地层，非功能焊盘通常设置在芯片安装区的四个角落位置和外圈位置，起到物理连接芯片和电路板结构的目的，用来保护芯片内部的功能焊盘在受到机械和环境应力时不会最先断裂，影响产品功能，具有相同网络功能的多个独立的焊盘可以合并形成大尺寸的第一焊盘。
一种可能的实现方式中，所述芯片安装区包括位于所述中心区域外围且依次连接的第一侧边区，第二侧边区，第三侧边区和第四侧边区，所述第一侧边区和所述第三侧边区相对设 置在所述中心区域的两侧，所述第二侧边区和所述第四侧边区相对设置在所述中心区域的两侧，电连接所述主体的接地层的所述第一焊盘分布在所述第一侧边区和所述第三侧边区，所述网络功能焊盘分布于所述第二侧边区和所述第四侧边区。
一种可能的实现方式中，所述网络功能焊盘电连接至所述主体的信号层。
一种可能的实现方式中，所述芯片安装区呈方形，所述第一焊盘分布在所述芯片安装区的四个角落位置，每个所述第一焊盘的尺寸为所述第二焊盘尺寸的两倍至四倍。角落位置的焊盘在受到机械和环境应力时易于开裂，大尺寸的第一焊盘分布在四个角落位置有利于提高芯片与电路板结构之间连接的机械可靠性。
一种可能的实现方式中，所述芯片安装区呈方形，所述芯片安装区划分为N*N的矩阵区域，所述第一焊盘位于所述芯片安装区的四个角落位置，且所述第一焊盘分布在8*8的矩阵区域内。由于角落位置8*8的矩阵区域内的焊盘易于出现开裂，所以大尺寸的第一焊盘分布在每个角落位置8*8的矩阵区域内可以提高芯片与电路板结构之间连接的机械可靠性。
一种可能的实现方式中，所述芯片安装区包括所述中心区域和边缘区域，边缘区域呈框形，环绕所述中心区域，所述边缘区域内分布多圈所述焊盘，所述第一焊盘分布在边缘区域内，位于最外圈的焊盘的周围设有阻焊层，且所述阻焊层遮盖所述焊盘的边缘。通过设置阻焊层，可以实现更高的机械可靠性，增强芯片与电路板结构的连接强度。通过设置阻焊层使得芯片与电路板之间可以不用点胶即可实现较高的机械可靠性，能够有效避免在芯片和电路板结构之间的焊盘点胶存在点胶元件焊点返修退润湿、敏感元件粘胶失效、增加成本和工艺复杂性等问题。
一种可能的实现方式中，所述芯片安装区设有点胶口，所述点胶口位于所述芯片安装区的角落位置，所述芯片安装区的局部区域点胶。第一焊盘的设置提高了芯片与电路板结构之间连接的机械可靠性，为了实现更高的机械可靠性，可以在第一焊盘尺寸较小或第一焊盘数量较少的区域进行少量的局部点胶。
一种可能的实现方式中，所述芯片安装区的三个角落位置及沿着所述芯片安装区的边长方向的相邻的两个角落位置之间的区域点胶。
一种可能的实现方式中，所述第一焊盘的形状为长条形、三角形、正方形、平行四边形、梯形、多边形、圆形、L形、V形中的一种或多种，第一焊盘的形状可以根据需要设置。
第二方面，本申请提供一种电子设备，包括芯片和上述任一项实现方式所述的电路板结构，所述芯片安装在所述芯片安装区的所述多个焊盘处。
本申请提供的电路板结构解决了大尺寸芯片与电路板结构之间连接的机械可靠性问题，并可以减少芯片与电路板结构之间的点胶量甚至不点胶，有效的避免了在芯片和电路板结构之间的焊盘点胶存在点胶元件焊点返修退润湿、敏感元件粘胶失效、高温高湿焊点枝晶短路、电容啸叫、增加成本和工艺复杂性等问题。
附图说明
图1是本申请一种实现方式提供的电路板结构的应用环境示意图；
图2是本申请一种实现方式提供的芯片焊接至电路板的结构示意图；
图3a是本申请一种实现方式提供的电路板结构示意图；
图3b是本申请一种实现方式提供的芯片侧的焊盘与电路板的第一焊盘对应设置的结构示意图；
图4是本申请一种实现方式提供的接地焊盘连接至接地层的结构示意图；
图5是本申请一种实现方式提供的非功能焊盘分布结构示意图；
图6是本申请一种实现方式提供的网络功能焊盘分布结构示意图；
图7是本申请一种实现方式提供的不同种类的焊盘的分布结构示意图；
图8是本申请另一种实现方式提供的电路板结构示意图；
图9是本申请一种实现方式提供的第一焊盘分布区域结构示意图；
图10是本申请另一种实现方式提供的第一焊盘分布区域结构示意图；
图11是本申请一种实现方式提供的电路板结构局部点胶结构示意图；
图12是本申请一种实现方式提供的设有阻焊层的焊盘的结构示意图；
图13是本申请一种实现方式提供的阻焊层的结构示意图。
具体实施方式
下面将结合附图，对本申请的具体实施方式进行清楚地描述。
本申请提供一种电路板结构和电子设备。如图1和图2所示，电子设备10包括芯片20和电路板结构30，电子设备10可以为手机、手表、平板电脑等产品，芯片20可以为封装形式的芯片，电源管理芯片等。芯片20的一侧设有芯片焊盘210，电路板结构30的一侧设有大尺寸的第一焊盘311和小尺寸的第二焊盘312，芯片20安装在电路板结构30上，具体而言，电路板结构30的中心区域内的每个独立的小尺寸的第二焊盘312与芯片20的芯片焊盘210一一对应，电路板结构30的边缘区域的大尺寸的第一焊盘311对应至少两个芯片焊盘210。边缘区域大尺寸的第一焊盘311的面积大于中心区域小尺寸的第二焊盘312的面积，增强了芯片20与电路板结构30之间连接的机械可靠性，使得芯片20在电路板结构30安装更稳固，避免跌落时，焊盘310开裂，芯片20与电路板结构30连接断开，影响电子设备10的功能。
芯片20通过焊料焊接至电路板结构30，芯片20安装至电路板结构30后，焊料形成焊球(参阅图2，大尺寸的焊球317，小尺寸的焊球318)，每个大尺寸的焊球317邻近芯片20一侧对应至少两个芯片焊盘210，每个大尺寸的焊球317邻近电路板结构30一侧对应边缘区域的一个大尺寸的第一焊盘311，每个小尺寸的焊球318邻近芯片20一侧对应一个芯片焊盘210，每个小尺寸的焊球318邻近电路板结构30一侧对应中心区域的一个小尺寸的第二焊盘312(参阅图1)。
如图1和图3a所示，电路板结构30包括主体320和多个焊盘310。主体320的表面设有芯片安装区330，芯片安装区330呈方形，芯片安装区330包括中心区域331和边缘区域332(即边缘位置处)，边缘区域332呈框形，环绕中心区域331，边缘区域332内分布多圈焊盘310，多个焊盘310包括至少一个第一焊盘311和多个第二焊盘312，至少一个第一焊盘311位于芯片安装区330的边缘区域332内，多个第二焊盘312分布在芯片安装区330的中心区域331和至少一个第一焊盘311的周围，且第一焊盘311的面积大于第二焊盘312的面积的二倍，第一焊盘311用于焊接芯片侧的至少两个独立的芯片焊盘210，例如，第一焊盘311可以对应于两个独立的芯片焊盘210(参阅图3b，即图3b中的长方形的第一焊盘311)，第一焊盘311也可以对应于四个独立的芯片焊盘210(参阅图3b，即图3b中三角形的第一焊盘311)。芯片20安装固定于电路板结构30上，芯片20的尺寸较大时(即芯片安装区330的尺寸较大)，在电路板结构30跌落的过程中，由于边缘区域332上的焊盘310受到较大的应 力，可靠性差，易于开裂，使得大尺寸的芯片20与电路板结构30之间的连接断开，影响产品功能。本申请将大尺寸的第一焊盘311设置在边缘区域332内，增加了焊盘与芯片20及电路板结构30的主体320表面的芯片安装区330的结合面积，使得边缘区域的焊盘不易开裂，有利于提高芯片20与电路板结构30之间连接的机械可靠性，有效避免了在跌落时，焊盘开裂，大尺寸的芯片20与电路板结构30之间的连接断开。
一种可能的实现方式中，第一焊盘311的面积大于第二焊盘312的面积的二倍。第一焊盘311的面积大于第二焊盘312的面积的二倍时，通过增加第一焊盘311的面积有利于提高芯片20与电路板结构30之间连接的机械可靠性。
一种可能的实现方式中，至少一个第一焊盘可以为接地焊盘313，接地焊盘313电连接至主体320的接地层321(参阅图4)；至少一个第一焊盘可以为非功能焊盘314，非功能焊盘314通常设置在芯片安装区330的四个角落位置和外圈位置，起到物理连接芯片20和电路板结构30的目的，用来保护芯片20内部的功能焊盘在受到机械和环境应力时不会最先断裂，影响产品功能(参阅图5)；至少一个第一焊盘可以为网络功能焊盘315，网络功能焊盘315电连接至主体320的信号层322，具有相同网络功能的焊盘可以合并形成大尺寸的第一焊盘(参阅图6)。
一种可能的实现方式中，可以通过将多个独立的接地焊盘313，或多个独立的非功能焊盘314，或多个独立的具有相同网络功能的网络功能焊盘315合并成一个大尺寸的第一焊盘311，可以理解的，相比于全部采用多个独立的焊盘，合并后降低了电路板结构30上焊盘的数量，电路板结构30的加工成本通常与焊盘的数量相关，焊盘数量越多，成本越高，因此，合并后减少了焊盘的数量(即采用大尺寸的第一焊盘)则有利于降低电路板结构30的加工成本。
一种可能的实现方式中，在芯片安装区330内(参阅图7)，第一焊盘主要分布于边缘区域332内。可以将多个独立的接地焊盘合并为大尺寸的接地焊盘313(即第一焊盘为接地焊盘313)，可以将多个独立的相同功能网络的焊盘合并为大尺寸的同网络功能焊盘315(即第一焊盘为同网络功能焊盘315)。芯片安装区330包括位于中心区域331外围且依次连接的第一侧边区3321，第二侧边区3322，第三侧边区3323和第四侧边区3324，第一侧边区3321和第三侧边区3323相对设置在中心区域331的两侧，第二侧边区3322和第四侧边区3324相对设置在中心区域331的两侧，电连接主体的接地层的第一焊盘(即大尺寸的接地焊盘313)主要分布在第一侧边区3321和第三侧边区3323，同网络功能焊盘315主要分布于第二侧边区3322和第四侧边区3324。
一种可能的实现方式中，将呈方形结构的芯片安装区330划分为N*N的矩阵区域，第一焊盘311位于芯片安装区330的四个角落位置，由于角落位置8*8的矩阵区域C1、8*8的矩阵区域C2、8*8的矩阵区域C3、8*8的矩阵区域C4内的焊盘易于出现开裂，所以大尺寸的第一焊盘311主要分布在四个角落位置8*8的矩阵区域C1、8*8的矩阵区域C2、8*8的矩阵区域C3、8*8的矩阵区域C4内可以提高芯片20与电路板结构30之间连接的机械可靠性(参阅图8)。
一种可能的实现方式中，第一焊盘311分布在方形的芯片安装区330的四个角落位置，每个第一焊盘311的尺寸为第二焊盘312尺寸的二倍到四倍，大于四个以上的焊盘合并焊接过程中的焊锡流动方向不可控，导致的焊接效果一致性差，容易出现焊锡和器件侧焊盘分离等焊接不良。角落位置的焊盘在受到机械和环境应力时易于开裂，因此，分布于四个角落的 第一焊盘311为两个到四个第二焊盘312合并而成，第一焊盘311分布在四个角落位置有利于提高芯片20与电路板结构30之间连接的机械可靠性，增强芯片20与电路板结构30的连接强度。
一种可能的实现方式中，芯片的尺寸较大时需要将独立的焊盘合并形成尺寸较大的第一焊盘。芯片的长度为L，宽度为W，芯片安装区330划分为N*N的矩阵区域，当L*W>11mm*11mm，N*N的矩阵的边缘区域的最外3圈和角落最外5行的焊盘用于合并形成大尺寸的第一焊盘(参阅图9，即第一焊盘可以位于图9中八边形虚线框335与芯片安装区330的边界B1、边界B2、边界B3、边界B4之间的区域)，当11mm*11mm≥L*W>8mm*8mm，N*N的矩阵的边缘区域的最外2圈和角落最外3行的焊盘用于合并形成大尺寸的第一焊盘(参阅图10，即第一焊盘可以位于图10中八边形虚线框335与芯片安装区330的边界B1、边界B2、边界B3、边界B4之间的区域)，当L*W≤8mm*8mm，由于芯片20的尺寸较小(即芯片安装区的尺寸较小)，可以不设置第一焊盘，即多个独立的焊盘可以不合并。
一种可能的实现方式中，在边缘区域设置大尺寸的第一焊盘311提高了芯片20与电路板结构30之间连接的机械可靠性，为了满足更高的机械可靠性需求，可以在第一焊盘311尺寸较小或第一焊盘311数量较少的区域(参阅图11，即点胶区333)进行少量的局部点胶，进一步增强机械可靠性，具体而言，芯片安装区330设有点胶口334，点胶口334位于芯片安装区330的角落位置，芯片安装区330的三个角落位置及沿着芯片安装区的边长方向(即边界B1和边界B2)的相邻的两个角落位置之间的区域点胶。点胶区333的内部边界A1与芯片安装区330的边界B1之间的垂直距离小于边界B2长度的一半，点胶区333的内部边界A2与芯片安装区330的边界B2之间的垂直距离小于边界B1长度的一半。相比于采用多个独立焊盘需要大面积点胶(传统点胶要求芯片20和电路板结构30之间大于80％的区域要被胶填充以保障跌落等机械可靠性)，本申请通过在边缘区域设置大尺寸的第一焊盘311，使得芯片20与电路板结构30之间的连接强度明显增强(即机械可靠性增加)，因此，只要求芯片20与电路板结构30之间大于50％甚至更小的区域被胶填充即可保障跌落时的机械可靠性，有效降低了实现点胶效果的难度。具体的点胶位置还要考虑焊盘跌落应力仿真和焊盘切片的结果，对仿真应力较高和切片已发现功能焊盘完全断裂的区域优先进行点胶。
一种可能的实现方式中，第一焊盘311的形状可以为长条形、三角形、正方形、平行四边形、梯形、多边形、圆形、L形、V形中的一种或多种，第一焊盘311的形状可以根据需要设置于芯片安装区的边缘区域。
如图12和图13所示，第一焊盘311分布于边缘区域332内，位于外圈的独立焊盘(图12中的圆圈均表示焊盘，外侧的大圆圈表示设有阻焊层的焊盘(SMD,solder mask define)3121，内侧的小圆圈表示独立的没有设置阻焊层的焊盘(NSMD,non-solder mask define)即第二焊盘312)和第一焊盘311的周围设有阻焊层316。以第一焊盘311周围的阻焊层为例(参阅图13)，阻焊层316遮盖第一焊盘311边缘的上表面，阻焊层316与第一焊盘311的上表面共同形成限位空间(即形成凹槽结构)，焊球317位于限位空间内，焊球317焊接时焊锡填满限位空间，用于增强焊球317与第一焊盘311的结合力。外圈的独立焊盘周围的阻焊层的设置与上述第一焊盘311周围的阻焊层的设置相同，外圈的独立焊盘的周围设置阻焊层后即形成设有阻焊层的焊盘3121。通过设置阻焊层316，可以实现更高的机械可靠性，增强芯片20与电路板结构30的连接强度。
一种可能的实现方式中，第一焊盘311(即将多个独立的焊盘310合并为一个大尺寸的 第一焊盘311)对应的焊球317的高度，例如80um(焊球317是将芯片20焊接到电路板结构30的焊盘上的焊料，焊球317的高度是指，焊球317在垂直于电路板结构的主体的方向上的焊料尺寸)可以低于只设置多个独立的焊盘中的焊球的高度，例如180um，焊球317的高度也可以根据具体的需求设置。
一种可能的实现方式中，通过在边缘区域332设置大尺寸的第一焊盘311，并在外圈和角落位置设置阻焊层316有效提高了机械可靠性，使得芯片与电路板之间可以不用点胶即可达到产品的机械可靠性要求，能够有效避免在芯片和电路板结构之间的焊盘点胶存在点胶元件焊点返修退润湿、敏感元件粘胶失效、高温高湿焊点枝晶短路、电容啸叫、增加成本和工艺复杂性等问题，具体而言，由于没有点胶，在加热返修的时候没有高热膨胀系数的胶挤压融化或接近融化的焊盘，不会导致芯片和焊盘发生分离，因此不会发生返修焊点退润湿失效的问题；由于没有点胶，点胶元件附近的粘胶敏感元件(如WLCSP、电感等)的侧壁在机械或温度变化的情况下就不会受到胶的拉扯力，因此不会发生敏感元件粘胶失效的问题；由于没有点胶，就不存在点胶空洞，焊点之间的温度和外界保持一致不能形成凝露，即湿度相对点胶空洞场景下更低，因此可降低枝晶的生长速度，也就不存在高温高湿焊点枝晶短路的问题；仿真显示某电容在点胶前的振动幅度仅为点胶情况下的1/3500，因此不点胶通常可以实现电容啸叫的程度不足以为人耳感知到。
本申请通过设置第一焊盘于芯片安装区的边缘区域，且第一焊盘的尺寸大于第二焊盘的尺寸，解决了大尺寸芯片与电路板结构之间连接的机械可靠性问题，由于机械可靠性的增强，可以减少芯片与电路板结构之间的点胶量甚至不点胶，有效的避免了在芯片和电路板结构之间的焊盘点胶存在点胶元件焊点返修退润湿、敏感元件粘胶失效、高温高湿焊点枝晶短路、电容啸叫、增加成本和工艺复杂性等问题。
以上，仅为本申请的部分实施例和实施方式，本申请的保护范围不局限于此，任何熟知本领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。

Claims (11)

  1. 一种电路板结构，其特征在于，包括主体和多个焊盘，所述主体表面设有芯片安装区，所述多个焊盘包括至少一个第一焊盘和多个第二焊盘，所述至少一个第一焊盘位于靠近所述芯片安装区的边缘位置处，所述多个第二焊盘分布在所述芯片安装区的中心区域及所述至少一个第一焊盘的周围，所述第一焊盘的面积大于所述第二焊盘的面积的二倍，所述第一焊盘用于焊接芯片侧的至少两个独立的焊盘。
  2. 如权利要求1所述的电路板结构，其特征在于，所述至少一个第一焊盘电连接至所述主体的接地层；或者，所述至少一个第一焊盘为非功能焊盘；或者，所述至少一个第一焊盘为网络功能焊盘。
  3. 如权利要求2所述的电路板结构，其特征在于，所述芯片安装区包括位于所述中心区域外围且依次连接的第一侧边区，第二侧边区，第三侧边区和第四侧边区，所述第一侧边区和所述第三侧边区相对设置在所述中心区域的两侧，所述第二侧边区和所述第四侧边区相对设置在所述中心区域的两侧，电连接所述主体的接地层的所述第一焊盘分布在所述第一侧边区和所述第三侧边区，所述网络功能焊盘分布于所述第二侧边区和所述第四侧边区。
  4. 如权利要求2所述的电路板结构，其特征在于，所述网络功能焊盘电连接至所述主体的信号层。
  5. 如权利要求1所述的电路板结构，所述芯片安装区呈方形，所述第一焊盘分布在所述芯片安装区的四个角落位置，每个所述第一焊盘的尺寸为所述第二焊盘尺寸的两倍至四倍。
  6. 如权利要求1所述的电路板结构，所述芯片安装区呈方形，所述芯片安装区划分为N*N的矩阵区域，所述第一焊盘位于所述芯片安装区的四个角落位置，且所述第一焊盘分布在8*8的矩阵区域内。
  7. 如权利要求5或6所述的电路板结构，所述芯片安装区包括所述中心区域和边缘区域，所述边缘区域呈框形，环绕所述中心区域，所述边缘区域内分布多圈所述焊盘，所述第一焊盘分布在所述边缘区域内，位于最外圈的所述焊盘的周围设有阻焊层，且所述阻焊层遮盖所述焊盘的边缘。
  8. 如权利要求5或6所述的电路板结构，所述芯片安装区设有点胶口，所述点胶口位于所述芯片安装区的角落位置，所述芯片安装区的局部区域点胶。
  9. 如权利要求8所述的电路板结构，所述芯片安装区的三个角落位置及沿着所述芯片安装区的边长方向的相邻的两个角落位置之间的区域点胶。
  10. 如权利要求5或6所述的电路板结构，所述第一焊盘的形状为长条形、三角形、正方形、平行四边形、梯形、多边形、圆形、L形、V形中的一种或多种。
  11. 一种电子设备，其特征在于，包括芯片和如权利要求1至10任一项所述的电路板结构，所述芯片安装在所述芯片安装区的所述多个焊盘处。
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