WO2021189323A1 - 显示面板及其制作方法、显示装置 - Google Patents

显示面板及其制作方法、显示装置 Download PDF

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Publication number
WO2021189323A1
WO2021189323A1 PCT/CN2020/081195 CN2020081195W WO2021189323A1 WO 2021189323 A1 WO2021189323 A1 WO 2021189323A1 CN 2020081195 W CN2020081195 W CN 2020081195W WO 2021189323 A1 WO2021189323 A1 WO 2021189323A1
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WIPO (PCT)
Prior art keywords
signal line
sub
substrate
transistor
line pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/081195
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English (en)
French (fr)
Other versions
WO2021189323A9 (zh
Inventor
杨慧娟
刘庭良
姜晓峰
李慧君
张顺
王予
代洁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US17/258,851 priority Critical patent/US11875752B2/en
Priority to JP2021572435A priority patent/JP7566796B2/ja
Priority to PCT/CN2020/081195 priority patent/WO2021189323A1/zh
Priority to EP20897672.0A priority patent/EP4131391B1/en
Priority to KR1020217036961A priority patent/KR102926382B1/ko
Priority to CN202080000372.8A priority patent/CN114080688B/zh
Publication of WO2021189323A1 publication Critical patent/WO2021189323A1/zh
Publication of WO2021189323A9 publication Critical patent/WO2021189323A9/zh
Anticipated expiration legal-status Critical
Priority to JP2024173040A priority patent/JP7772295B2/ja
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, and a display device.
  • the screen-to-body ratio of the OLED display device is the ratio of the effective display area (English: Active Area, AA area for short) in the front panel of the display device, and the resolution of the OLED display device is the number of pixel structures included in the AA area.
  • the larger the screen-to-body ratio of the OLED display device the better the consumer experience.
  • the higher the resolution of the OLED display device the clearer the image displayed.
  • the purpose of the present disclosure is to provide a display panel, a manufacturing method thereof, and a display device.
  • a first aspect of the present disclosure provides a display panel, including: a substrate, a functional film layer disposed on the substrate; and further including a plurality of sub-pixel regions arranged in an array;
  • the functional film layer includes: a reset signal line layer, an initialization signal line layer, and a conductive connection layer;
  • the reset signal line layer includes: a reset signal line pattern arranged in each of the sub-pixel regions, the reset signal line pattern extending along a first direction;
  • the initialization signal line layer includes: an initialization signal line pattern disposed in each of the sub-pixel regions, the initialization signal line pattern includes a first body portion and a first protruding portion that are coupled to each other, the first body portion Extending along the first direction, in the same sub-pixel area, the orthographic projection of the first body portion on the substrate is located between the orthographic projection of the first protruding portion on the substrate and the reset signal line Between the orthographic projections of the graphics on the substrate;
  • the conductive connection portion layer includes: a conductive connection portion pattern arranged in each of the sub-pixel regions, in the same sub-pixel area, the orthographic projection of the first end portion of the conductive connection portion pattern on the substrate, There is a first overlap area with the orthographic projection of the first protruding portion on the substrate. In the first overlap area, the first end portion is coupled to the first protruding portion, and the conductive connecting portion The second end of the pattern is coupled to the target coupling portion in the sub-pixel area where it is located, the orthographic projection of the reset signal line pattern on the substrate, and the orthographic projection of the target coupling portion on the substrate And the initial projection of the initialization signal line pattern on the substrate.
  • the display panel further includes:
  • a plurality of light-emitting elements corresponding to the plurality of sub-pixel regions one-to-one, and the plurality of light-emitting elements are located on a side of the functional film layer facing away from the substrate;
  • each of the sub-pixel driving circuits includes a seventh transistor, and the gate of the seventh transistor is coupled to the corresponding reset signal line pattern ,
  • the first electrode of the seventh transistor serves as the target coupling portion, and the second electrode of the seventh transistor extends along the second direction and is coupled to the anode of the corresponding light-emitting element;
  • the conductive connecting portion pattern further includes a second body portion connected between the first end portion and the second end portion, the second body portion extending in a second direction; in the same sub-pixel area, Along the first direction, the first end portion of the conductive connecting portion pattern protrudes from the second body portion in a direction away from the second electrode of the seventh transistor.
  • the functional film layer further includes a data line pattern located in each sub-pixel area, and the data line pattern includes a portion extending along the second direction;
  • a fourth overlapping area exists between the orthographic projection of the initialization signal line pattern on the substrate and the orthographic projection of the data line pattern on the substrate;
  • the width of the initialization signal line pattern in the fourth overlap area along the second direction is smaller than the width of the initialization signal line pattern in the third overlap area along the second direction.
  • the first gap is greater than the threshold.
  • the display panel further includes:
  • each of the sub-pixel driving circuits includes a driving transistor and a second transistor;
  • the gate of the second transistor is coupled to the reset signal line pattern in the previous sub-pixel region adjacent in the second direction, and the first electrode of the second transistor serves as the previous sub-pixel In the target coupling portion in the region, the second electrode of the second transistor is coupled to the gate of the driving transistor;
  • the second transistor includes two semiconductor parts spaced apart along the first direction, and a first conductor part respectively connecting the two semiconductor parts, an orthographic projection of the first conductor part on the substrate, It does not overlap with the orthographic projection of the first protrusion in the previous sub-pixel area on the substrate.
  • the orthographic projection of the first conductor portion on the substrate overlaps the orthographic projection of the first end portion of the conductive connecting portion pattern in the previous sub-pixel area on the substrate .
  • each of the initialization signal line patterns further includes a second protruding portion coupled with the first main body portion, and in the same sub-pixel area, the orthographic projection of the second protruding portion on the substrate Located between the orthographic projection of the first main body portion on the substrate and the orthographic projection of the reset signal line pattern on the substrate, the orthographic projection of the first conductor portion on the substrate and the The orthographic projections of the second protrusions on the base overlap.
  • the conductive connecting portion pattern further includes a second body portion connected between the first end portion and the second end portion, and the second body portion extends in a second direction;
  • One end of the first conductor portion close to the conductive connection portion pattern in the previous sub-pixel area extends along the second direction, and the orthographic projection of this end on the substrate is similar to the conductive connection portion pattern
  • the second body portion of the substrate has a second gap between the orthographic projections on the substrate, and the second gap is greater than a threshold.
  • the orthographic projection of the first end portion of the conductive connection portion pattern on the substrate is also similar to the projection of the first main body portion of the initialization signal line pattern on the substrate.
  • Orthographic projection forms the second overlapping area
  • the functional film layer further includes a first connection hole located in each of the sub-pixel areas.
  • the orthographic projections of the first connection holes on the substrate are respectively aligned with the first intersections.
  • the overlap area and the second overlap area overlap, and the first end portion of the conductive connection portion pattern is coupled to the initialization signal line pattern through the first connection hole.
  • the orthographic projection of the first conductor portion of the second transistor on the substrate is different from the orthographic projection of the first connection hole in the previous sub-pixel area on the substrate. overlap.
  • the functional film layer further includes a power signal line layer, the power signal line layer includes a power signal line pattern arranged in each of the sub-pixel regions, and at least part of the power signal line pattern is along the second Direction extension
  • One end of the first conductor portion away from the conductive connecting portion pattern in the previous sub-pixel area extends along the second direction, and the orthographic projection of this end on the substrate is located in the same sub-pixel area
  • the orthographic projection of the power signal line pattern on the substrate completely covers.
  • the display panel further includes:
  • each of the sub-pixel driving circuits includes a driving transistor and a storage capacitor, and the storage capacitor includes a first electrode plate and a second electrode plate arranged oppositely , The first plate is multiplexed as the gate of the driving transistor, and the second plate is located on the side of the first substrate away from the base;
  • the functional film layer further includes a power signal line layer, the power signal line layer includes a power signal line pattern disposed in each of the sub-pixel regions, and at least a part of the power signal line pattern extends along a second direction, so The power signal line pattern includes a first power source part and a second power source part;
  • the orthographic projection of the first power supply portion on the substrate overlaps the orthographic projection of the reset signal line patterns located in the same sub-pixel area on the substrate, and overlaps with the orthographic projections of the reset signal line patterns located in the same sub-pixel area.
  • the orthographic projection of the grid pattern on the substrate overlaps; the orthographic projection of the second power supply portion on the substrate and the orthographic projection of the corresponding second plate of the storage capacitor on the substrate Overlap; the width of the first power supply part along the first direction is smaller than the width of the second power supply part.
  • the functional film layer further includes a power signal line layer, the power signal line layer includes a power signal line pattern arranged in each of the sub-pixel regions, and at least part of the power signal line pattern is along the second Direction extension
  • the functional film layer further includes an auxiliary power supply layer, the auxiliary power supply layer includes an auxiliary power supply pattern disposed in each of the sub-pixel regions, and the orthographic projection of the auxiliary power supply pattern on the substrate is the same as that located in the same sub-pixel region. There is an overlap area in the orthographic projection of the power signal line pattern in the substrate on the substrate, and the auxiliary power source pattern and the power signal line pattern are coupled in the overlap area.
  • the display panel further includes: a plurality of sub-pixel driving circuits corresponding to the plurality of sub-pixel regions one-to-one, each of the sub-pixel driving circuits includes a driving transistor and a second transistor;
  • the gate of the second transistor is coupled to the reset signal line pattern in the previous sub-pixel region adjacent in the second direction, and the first electrode of the second transistor serves as the previous sub-pixel Area in the target coupling portion
  • the second electrode of the second transistor includes a first electrode portion and a second electrode portion that are coupled to each other, the first electrode portion extends in a second direction, and the second electrode portion
  • the electrode portion extends in a third direction, the third direction intersects both the first direction and the second direction, and the first electrode portion is located between the semiconductor portion of the second transistor and the second electrode portion In between, the second electrode portion is coupled to the gate of the driving transistor;
  • the orthographic projection of the first electrode portion on the substrate and the orthographic projection of the second electrode portion on the substrate are both covered by the orthographic projection of the corresponding auxiliary power supply pattern on the substrate.
  • the auxiliary power supply pattern includes a first auxiliary sub-graphic and a second auxiliary sub-graphic that are coupled to each other, the first auxiliary sub-graphic extending in a second direction, and at least part of the second auxiliary sub-graphic Extending in the first direction;
  • the orthographic projection of the first auxiliary sub-pattern on the substrate covers the orthographic projection of the first electrode portion on the substrate and the orthographic projection of the second electrode portion on the substrate.
  • the width of the first auxiliary sub-pattern is greater than the width of the corresponding power signal line pattern.
  • the orthographic projection of the first electrode portion on the substrate and the orthographic projection of the second electrode portion on the substrate are both projected on the substrate by the corresponding power signal line pattern. Orthographic coverage.
  • the functional film layer includes: a gate line pattern and a light emission control signal line pattern located in each sub-pixel area; in the same sub-pixel area, along the second direction, the gate line pattern, the The light-emitting control signal line pattern, the reset signal line pattern, and the initialization signal line pattern are arranged in sequence;
  • the functional film layer further includes a power signal line pattern and a data line pattern located in each sub-pixel area, and the power signal line pattern and the data line pattern both include a portion extending along the second direction;
  • the display panel also includes:
  • each sub-pixel driving circuit includes: a driving transistor, a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor ;
  • the gate of the driving transistor is coupled to the second electrode of the first transistor, the first electrode of the driving transistor is coupled to the second electrode of the fifth transistor, and the The second electrode of the driving transistor is coupled to the first electrode of the first transistor;
  • the gate of the first transistor is coupled to the gate line pattern
  • the gate of the second transistor is coupled to the reset signal line pattern in the previous sub-pixel region adjacent in the second direction, and the first electrode of the second transistor serves as the previous sub-pixel In the target coupling portion in the region, the second electrode of the second transistor is coupled to the gate of the driving transistor;
  • the gate of the fourth transistor is coupled to the gate line pattern, the first electrode of the fourth transistor is coupled to the data line pattern, and the second electrode of the fourth transistor is connected to the driving transistor.
  • the gate of the fifth transistor is coupled to the light emission control signal line pattern, and the first electrode of the fifth transistor is coupled to the power signal line pattern;
  • the gate of the sixth transistor is coupled to the light emission control signal line pattern, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the The corresponding light-emitting element is coupled;
  • the second electrode of the seventh transistor is coupled to the light-emitting element, the gate of the seventh transistor is coupled to the reset signal line pattern, and the first electrode of the seventh transistor is coupled to the second initialization signal line Graphics coupling.
  • a second aspect of the present disclosure provides a display device including the above-mentioned display panel.
  • a third aspect of the present disclosure provides a manufacturing method of a display panel, including:
  • the functional film layer includes: a reset signal line layer, an initialization signal line layer, and a conductive connection layer;
  • the reset signal line layer includes: a reset signal line pattern arranged in each of the sub-pixel regions, the reset signal line pattern extending along a first direction;
  • the initialization signal line layer includes: an initialization signal line pattern disposed in each of the sub-pixel regions, the initialization signal line pattern includes a first body portion and a first protruding portion that are coupled to each other, the first body portion Extending along the first direction, in the same sub-pixel area, the orthographic projection of the first body portion on the substrate is located between the orthographic projection of the first protruding portion on the substrate and the reset signal line Between the orthographic projections of the graphics on the substrate;
  • the conductive connection portion layer includes: a conductive connection portion pattern arranged in each of the sub-pixel regions, in the same sub-pixel area, the orthographic projection of the first end portion of the conductive connection portion pattern on the substrate, There is a first overlap area with the orthographic projection of the first protruding portion on the substrate. In the first overlap area, the first end portion is coupled to the first protruding portion, and the conductive connecting portion The second end of the pattern is coupled to the target coupling portion in the sub-pixel area where it is located, the orthographic projection of the reset signal line pattern on the substrate, and the orthographic projection of the target coupling portion on the substrate And the initial projection of the initialization signal line pattern on the substrate.
  • FIG. 1 is a schematic diagram of the layout of sub-pixels in the prior art
  • FIG. 2 is a schematic diagram of the layout of the active layer in FIG. 1;
  • FIG. 3 is a schematic diagram of the layout of the first gate metal layer in FIG. 1;
  • FIG. 4 is a schematic diagram of the layout of the second gate metal layer in FIG. 1;
  • FIG. 5 is a schematic diagram of the layout of the source and drain metal layers in FIG. 1;
  • FIG. 6 is a circuit diagram of a sub-pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 7 is a driving timing diagram of a sub-pixel driving circuit provided by an embodiment of the disclosure.
  • FIG. 8 is a schematic diagram of a first layout of a sub-pixel area provided by an embodiment of the disclosure.
  • FIG. 9 is a schematic diagram of a second layout of a sub-pixel area provided by an embodiment of the disclosure.
  • FIG. 10 is a schematic diagram of the layout of the active layer in FIG. 8;
  • FIG. 11 is a schematic diagram of the layout of the first gate metal layer in FIG. 8;
  • FIG. 12 is a schematic diagram of the layout of the second gate metal layer in FIG. 8;
  • FIG. 13 is a schematic diagram of the layout of the source and drain metal layers in FIG. 8;
  • Fig. 14 is a schematic cross-sectional view along the A1A2 direction in Fig. 8;
  • 15 is a schematic diagram of a third layout of sub-pixel areas provided by an embodiment of the present disclosure.
  • Fig. 16 is a first enlarged schematic diagram of part X1 in Fig. 15;
  • Fig. 17 is a second enlarged schematic diagram of part X1 in Fig. 15;
  • Fig. 18 is a schematic cross-sectional view along the direction B1B2 in Fig. 17;
  • FIG. 19 is a schematic diagram of the layout of the active layer in FIG. 15;
  • FIG. 20 is a schematic diagram of the layout of the first gate metal layer in FIG. 15;
  • FIG. 21 is a schematic diagram of the layout of the second gate metal layer in FIG. 15;
  • FIG. 22 is a schematic diagram of the layout of the source and drain metal layers in FIG. 15;
  • FIG. 23 is a schematic diagram of a fourth layout of a sub-pixel area provided by an embodiment of the disclosure.
  • 24 is a schematic structural diagram of a power signal line pattern provided by an embodiment of the disclosure.
  • FIG. 25 is a schematic diagram of a fifth layout of a sub-pixel area provided by an embodiment of the disclosure.
  • FIG. 27 is a schematic diagram of the layout of the first gate metal layer in FIG. 25;
  • FIG. 28 is a schematic diagram of the layout of the second gate metal layer in FIG. 25;
  • FIG. 29 is a schematic diagram of the layout of the source and drain metal layers in FIG. 25;
  • FIG. 30 is a schematic diagram of a layout of a second source and drain metal layer provided by an embodiment of the present disclosure.
  • FIG. 31 is a schematic diagram of the layout of the second source/drain metal layer and the anode layer provided by an embodiment of the disclosure.
  • FIG. 32 is a schematic diagram of the sixth-fifth layout of the sub-pixel area provided by an embodiment of the present disclosure.
  • FIG. 33 is a schematic diagram of the layout of the second gate metal layer and the second source/drain metal layer in FIG. 32;
  • Fig. 34 is a schematic cross-sectional view taken along the direction C1C2 in Fig. 32.
  • the structure of the AMOLED display panel includes: a substrate, a plurality of sub-pixel driving circuits arranged on the substrate, and a plurality of light-emitting elements arranged on the side of the sub-pixel driving circuit away from the substrate, the light-emitting elements and the
  • the sub-pixel drive circuits have a one-to-one correspondence, and the sub-pixel drive circuits are used to drive the corresponding light-emitting elements to emit light, so as to realize the display function of the display panel.
  • the sub-pixel driving circuit generally includes a plurality of thin film transistors, as shown in FIG. 1, which shows that when the sub-pixel driving circuit includes 7 thin film transistors M1 to M7, the 7 thin film transistors
  • FIG. 1 shows that when the sub-pixel driving circuit includes 7 thin film transistors M1 to M7, the 7 thin film transistors
  • the sub-pixel drive circuit includes an active layer as shown in FIG. 2, a first metal layer as shown in FIG. 3, and a second metal layer as shown in FIG. , And a third metal layer as shown in FIG. 5; the active layer includes an active pattern used to form the channel region of each thin film transistor (the part within the dashed frame in FIG.
  • the first metal layer includes the gate of each thin film transistor, and the gate is coupled to the scan A signal line GATE, a plate CE1 of a storage capacitor in the sub-pixel drive circuit, a reset signal line RST, and an emission control signal line EM;
  • the second metal layer includes an initialization signal line VINT, and the sub-pixel drive circuit
  • the third metal layer includes a data line DATA, a power signal line VDD, and some conductive connections (such as marks 341-343).
  • the present disclosure provides a display panel that includes a plurality of sub-pixel driving circuits, and also includes a power signal line pattern 901, a data line pattern 908, a gate line pattern 902, and a light-emitting control
  • the control signal line pattern 903, the reset signal line pattern 905, and the initialization signal line pattern 904 all extend along a first direction, and the first direction intersects the second direction.
  • the first direction includes the X direction
  • the second direction includes the Y direction.
  • the plurality of sub-pixel drive circuits can be divided into multiple rows of sub-pixel drive circuits arranged in sequence along the second direction, and multiple columns of sub-pixel drive circuits arranged in sequence along the first direction, which are located in the same
  • the initialization signal line patterns 904 corresponding to the sub-pixel drive circuits in the row are electrically connected in sequence to form an integrated structure;
  • the gate line patterns 902 corresponding to the sub-pixel drive circuits in the same row are electrically connected in sequence to form an integrated structure;
  • the light emission control signal line patterns 903 corresponding to the sub-pixel drive circuits in the same row are electrically connected in sequence to form an integrated structure;
  • the reset signal line patterns 905 corresponding to the sub-pixel drive circuits in the same row are electrically connected in sequence to form an integrated structure Structure;
  • the data line patterns 908 corresponding to the sub-pixel drive circuits in the same column are electrically connected in order to form an integrated structure;
  • each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits sequentially arranged along the X direction.
  • the initialization signal line pattern 904, the gate line pattern 902, the light emission control signal line pattern 903, and the reset signal line pattern 905 are all Extending along the X direction, the multiple sub-pixel driving circuits included in each row of sub-pixel driving circuits can respectively correspond to the initialization signal line pattern 904, the gate line pattern 902, the light emission control signal line pattern 903, and the reset signal line pattern 905.
  • Each column of sub-pixel drive circuits includes a plurality of sub-pixel drive circuits arranged in sequence along the Y direction, the data line pattern 908 and the power signal line pattern 901 both extend along the Y direction, and each column of sub-pixel drive circuit includes multiple sub-pixel drive circuits
  • the pixel driving circuits can be respectively coupled to the corresponding data line pattern 908 and power signal line pattern 901.
  • the first division method can be the first transistor T1, the second transistor T2 located at the top of FIG. 8, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the The seventh transistor T7 at the top of FIG. 8, and the gate line pattern 902, the light emission control signal line pattern 903, the reset signal line pattern 905' at the top of FIG. 8 and the initialization signal line pattern 904' at the top of FIG. 8 are divided into one sub-pixel Area (that is, the current sub-pixel area).
  • the second transistor T2 at the bottom of FIG. 8 the seventh transistor T7 at the bottom of FIG. 8, the reset signal line pattern 905 at the bottom of FIG. 8, and the initialization signal line pattern 904 at the bottom of FIG.
  • the pixel area is in the next sub-pixel area adjacent to the Y direction.
  • the second division method can also be the first transistor T1, the second transistor T2 located at the bottom of Figure 8, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and The seventh transistor T7 at the bottom of FIG. 8, as well as the gate line pattern 902, the light emission control signal line pattern 903, the reset signal line pattern 905 at the bottom of FIG. 8, and the initialization signal line pattern 904 at the bottom of FIG. 8, are divided into one sub-pixel Area (that is, the current sub-pixel area).
  • the seventh transistor T7 at the top in FIG. 8 the reset signal line pattern 905' at the top of FIG. 8, and the initialization signal line pattern 904' at the top of FIG. 8 are all divided into and The current sub-pixel area is adjacent to the previous sub-pixel area along the Y direction.
  • the division method of the sub-pixel area described in the present disclosure adopts the above-mentioned second division method.
  • the sub-pixel driving circuit corresponding to the current sub-pixel area includes: a first transistor T1, a second transistor T2 located at the top of FIG. 8
  • the reset signal line pattern 905' in the previous sub-pixel area adjacent in the direction is coupled, the source S2 of the second transistor T2 is coupled to the initialization signal line pattern 904' in the previous sub-pixel area, and the first The drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3.
  • the sub-pixel driving circuit includes 7 thin film transistors and 1 capacitor.
  • Each transistor included in the sub-pixel driving circuit adopts a P-type transistor, wherein the first transistor T1 has a double-gate structure, the gate 201g of the first transistor T1 is coupled to the gate line pattern 902, and the source S1 of the first transistor T1 It is coupled to the drain D3 of the third transistor T3 (ie, the driving transistor), and the drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3.
  • the second transistor T2 has a double-gate structure.
  • the gate 202g of the second transistor T2 is coupled to the reset signal line pattern 905' in the previous sub-pixel area adjacent to the second direction.
  • the source S2 is coupled to the initialization signal line pattern 904' in the previous sub-pixel area, and the drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3.
  • the gate 204g of the fourth transistor T4 is coupled to the gate line pattern 902, the source S4 of the fourth transistor T4 is coupled to the data line pattern 908, and the drain D4 of the fourth transistor T4 is coupled to the source of the third transistor T3. S3 is coupled.
  • the gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern 903, the source S5 of the fifth transistor T5 is coupled to the power signal line pattern 901, and the drain D5 of the fifth transistor T5 is coupled to the source of the third transistor T3 ⁇ S3 is coupled.
  • the gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern 905, the drain D7 of the seventh transistor T7 is coupled to the anode of the corresponding light emitting element EL, and the source S7 of the seventh transistor T7 is coupled to the initialization
  • the signal line pattern 904 is coupled.
  • the first plate Cst1 of the storage capacitor Cst is multiplexed as the gate 203g of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern 901.
  • each work cycle includes a reset period P1, a write compensation period P2, and a light emitting period P3.
  • E1 represents the emission control signal transmitted on the emission control signal line pattern 903 in the current sub-pixel area
  • R1 represents the reset signal transmitted on the reset signal line pattern 905 in the current sub-pixel area
  • D1 represents the current sub-pixel area
  • G1 represents the gate scan signal transmitted on the gate line pattern 902 in the current sub-pixel area
  • R1' represents the previous adjacent one in the current sub-pixel area along the second direction.
  • the reset signal is transmitted on the reset signal line pattern 905' in the sub-pixel.
  • the reset signal input by the reset signal line pattern 905' is at an active level
  • the second transistor T2 is turned on
  • the initialization signal transmitted by the initialization signal line pattern 904' is input to the third
  • the gate 203g of the transistor T3 makes the gate-source voltage Vgs held on the third transistor T3 in the previous frame cleared to reset the gate 203g of the third transistor T3.
  • the reset signal input from the reset signal line pattern 905' is at an inactive level
  • the second transistor T2 is turned off
  • the gate scanning signal input from the gate line pattern 902 is at an active level, controlling the first transistor T1 and the fourth transistor T4 are turned on
  • the data line pattern 908 writes a data signal, and is transmitted to the source S3 of the third transistor T3 through the fourth transistor T4, and at the same time, the first transistor T1 and the fourth transistor T4 are turned on
  • the third transistor T3 is formed into a diode structure, so the first transistor T1, the third transistor T3, and the fourth transistor T4 work together to realize the threshold voltage compensation of the third transistor T3.
  • the potential of the gate 203g of the third transistor T3 is controlled to finally reach Vdata+Vth, where Vdata represents the voltage value of the data signal, and Vth represents the threshold voltage of the third transistor T3.
  • the reset signal input by the reset signal line pattern 905 is at an active level
  • the seventh transistor T7 is controlled to be turned on
  • the initialization signal transmitted by the initialization signal line pattern 904 is input to the anode of the light emitting element EL , Control the light-emitting element EL to not emit light.
  • the light emission control signal written in the light emission control signal line pattern 903 is at an effective level, and the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on, so that the power signal transmitted by the power signal line pattern 901 is input to the third The source S3 of the transistor T3, and the gate 203g of the third transistor T3 is kept at Vdata+Vth, so that the third transistor T3 is turned on.
  • the corresponding gate-source voltage of the third transistor T3 is Vdata+Vth-VDD, where VDD is According to the voltage value corresponding to the power signal, the leakage current generated based on the gate-source voltage flows to the anode of the corresponding light-emitting element EL to drive the corresponding light-emitting element EL to emit light.
  • each film layer corresponding to the display sub-pixel drive circuit is as follows:
  • the active film layer, the gate insulating layer, the first gate metal layer, the first interlayer insulating layer, the second gate metal layer, the second interlayer insulating layer, the first source and drain are stacked in sequence in the direction away from the substrate The metal layer and the third interlayer insulating layer.
  • the active film layer is used to form the channel region (e.g. 101pg ⁇ 107pg), source formation area (e.g. 101ps ⁇ 107ps) and drain formation area of each transistor in the display sub-pixel driving circuit.
  • the active film layer corresponding to the source formation region and drain formation region will have better conductivity than the active film layer corresponding to the channel region due to the doping effect;
  • the active film layer can be amorphous Production of silicon, polysilicon, oxide semiconductor materials, etc.
  • the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the active film layer corresponding to the source electrode formation region and the drain electrode formation region can be directly used as the corresponding source electrode or drain electrode, or metal materials can also be used to make contact with the source electrode formation region.
  • a metal material is used to make the drain electrode in contact with the drain electrode formation region.
  • the first gate metal layer is used to form the gates of the transistors in the display sub-pixel driving circuit (e.g., 201g to 207g), and the gate line pattern 902, the light emission control signal line pattern 903, and the display substrate included in the display substrate.
  • the reset signal line pattern 905 and other structures, the gate 203g of the third transistor T3 in each display sub-pixel driving circuit is multiplexed as the first plate Cst1 of the second storage capacitor Cst in the display sub-pixel driving circuit.
  • the second gate metal layer is used to form the second plate Cst2 of the second storage capacitor Cst and the initialization signal line pattern 904 included in the display substrate.
  • the first source/drain metal layer is used to form the source (such as S1 to S7) and drain (such as D1 to D7) of each transistor in the display sub-pixel driving circuit, and
  • the display substrate includes a data line pattern 908, a power signal line pattern 901 and some conductive connections.
  • the gate 201g of the first transistor T1 covers the first channel region 101pg, the source S1 of the first transistor T1 is located in the first source formation region 101ps, and the first transistor T1 The drain D1 of is located in the first drain formation region 101pd.
  • the gate 202g of the second transistor T2 covers the second channel region 102pg, the source S2 of the second transistor T2 is located in the second source formation region 102ps, and the drain D2 of the second transistor T2 is located in the second drain formation region 102pd.
  • the gate 203g of the third transistor T3 covers the third channel region 103pg, the source S3 of the third transistor T3 is located in the third source formation region 103ps, and the drain D3 of the third transistor T3 is located in the third drain formation region 103pd.
  • the gate 204g of the fourth transistor T4 covers the fourth channel region 104pg, the source S4 of the fourth transistor T4 is located in the fourth source formation region 104ps, and the drain D4 of the fourth transistor T4 is located in the fourth drain formation region 104pd.
  • the gate 205g of the fifth transistor T5 covers the fifth channel region 105pg, the source S5 of the fifth transistor T5 is located in the fifth source formation region 105ps, and the drain D5 of the fifth transistor T5 is located in the fifth drain formation region 105pd.
  • the gate 206g of the sixth transistor T6 covers the sixth channel region 106pg, the source S6 of the sixth transistor T6 is located in the sixth source formation region 106ps, and the drain D6 of the sixth transistor T6 is located in the sixth drain formation region 106pd.
  • the gate 207g of the seventh transistor T7 covers the seventh channel region 107pg, the source S7 of the seventh transistor T7 is located in the seventh source formation region 107ps, and the drain D7 of the seventh transistor T7 is located in the seventh drain formation region 107pd.
  • the gate 203g of the third transistor T3 is multiplexed as the first plate Cst1 of the storage capacitor Cst, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern 901.
  • the gate 204g of the fourth transistor T4 in the second direction (such as the Y direction), the gate 204g of the fourth transistor T4, the gate 201g of the first transistor T1 and the gate of the second transistor T2
  • the gate 202g is located on the first side of the gate of the driving transistor (that is, the gate 203g of the third transistor T3), the gate of the seventh transistor T7, the gate 206g of the sixth transistor T6, and the gate of the fifth transistor T5 They are all located on the second side of the gate of the driving transistor.
  • the first side and the second side of the gate of the driving transistor are two opposite sides along the second direction. Further, the first side of the gate of the driving transistor may be the upper side of the gate of the driving transistor.
  • the second side of the gate of the driving transistor may be the lower side of the gate of the driving transistor.
  • the lower side for example, the side of the display substrate for bonding the IC is the lower side of the display substrate, and the lower side of the gate of the driving transistor is the side of the gate of the driving transistor closer to the IC.
  • the upper side is the opposite side of the lower side, for example, the side of the gate of the driving transistor further away from the IC.
  • the gate 204g of the fourth transistor T4 and the gate 205g of the fifth transistor T5 are both located on the third side of the gate of the driving transistor, and the gate 201g of the first transistor T1 and the second transistor T1
  • the gates 206g of the six transistors T6 are all located on the fourth side of the gate of the driving transistor.
  • the third side and the fourth side of the gate of the driving transistor are opposite sides along the first direction; further, the third side of the gate of the driving transistor may be the right side of the gate of the driving transistor, The fourth side of the gate of the driving transistor may be the left side of the gate of the driving transistor.
  • the left and right sides for example, in the same sub-pixel area, the data line pattern 908 is located on the right side of the power signal line pattern 901, and the power signal line pattern 901 is located on the right side of the data line pattern 908.
  • the above-mentioned display panel can improve the resolution, the improvement effect is limited.
  • FIG. 8 it can be seen from FIG. 8 that when the second transistor T2 and the seventh transistor T7 are coupled to the initialization signal line pattern 904 (904') through a via via the conductive portion 909, for a high-resolution display panel, due to the layout The space is small, and the space that can be punched is small. When the punching process is performed, it is easy to bias the via hole to the nearby reset signal line pattern 905 when the process fluctuates, causing signal disturbance.
  • the pixel structure in the above-mentioned display panel needs to be further optimized to solve the above-mentioned problems.
  • an embodiment of the present disclosure provides a display panel, including: a substrate, a functional film layer disposed on the substrate, and a plurality of sub-pixel regions arranged in an array;
  • the functional film layer includes: a reset signal line layer, an initialization signal line layer, and a conductive connection layer;
  • the reset signal line layer includes: a reset signal line pattern 905 arranged in each of the sub-pixel regions, and the reset signal line pattern 905 extends along a first direction;
  • the initialization signal line layer includes: an initialization signal line pattern 904 arranged in each of the sub-pixel regions.
  • the initialization signal line pattern 904 includes a first body portion 9041 and a first protruding portion 9042 that are coupled to each other.
  • the first body portion 9041 extends along the first direction.
  • the orthographic projection of the first body portion 9041 on the substrate is located on the orthographic projection of the first protruding portion 9042 on the substrate. Between the projection and the orthographic projection of the reset signal line pattern 905 on the substrate;
  • the conductive connection portion layer includes: a conductive connection portion pattern 909 arranged in each of the sub-pixel areas, and in the same sub-pixel area, the first end portion 9091 of the conductive connection portion pattern 909 is on the substrate Orthographic projection, and the orthographic projection of the first protruding portion 9042 on the substrate has a first overlapping area F1, in the first overlapping area F1, the first end 9091 and the first protruding portion 9042
  • the second end 9092 of the conductive connecting portion pattern 909 is coupled to the target coupling portion in the sub-pixel area where it is located, and the orthographic projection of the reset signal line pattern 905 on the substrate is located on the target Between the orthographic projection of the coupling portion on the substrate and the orthographic projection of the initialization signal line pattern 904 on the substrate.
  • the plurality of sub-pixel regions arranged in an array can be divided into multiple rows of sub-pixel regions sequentially arranged along the second direction, and multiple columns of sub-pixel regions sequentially arranged along the first direction.
  • Each row of sub-pixel regions includes a plurality of sub-pixel regions spaced along the first direction
  • each column of sub-pixel regions includes a plurality of sub-pixel regions spaced along the second direction.
  • the first direction intersects the second direction.
  • the first direction includes the X direction
  • the second direction includes the Y direction.
  • the reset signal line layer includes a reset signal line pattern 905 arranged in each of the sub-pixel regions, and the reset signal line pattern 905 extends along the first direction.
  • the reset signal line pattern 905 corresponds to the sub-pixel area one-to-one, the reset signal line pattern 905 is located in the corresponding sub-pixel area, and each of the reset signal line patterns corresponding to the sub-pixel areas in the same row 905 is electrically connected in sequence to form an integral structure.
  • the initialization signal line layer includes: initialization signal line patterns 904 arranged in each of the sub-pixel regions, the initialization signal line patterns 904 correspond to the sub-pixel regions one-to-one, and the initialization signal line patterns 904 are located in the corresponding sub-pixel regions. In the sub-pixel areas, the initialization signal line patterns 904 corresponding to the sub-pixel areas in the same row are electrically connected in sequence to form an integral structure.
  • each of the initialization signal line patterns 904 includes a first body portion 9041 and a first protruding portion 9042 that are coupled to each other.
  • the first body portion 9041 extends along the first direction and is located in the same direction.
  • the first body portion 9041 in each initialization signal line pattern 904 corresponding to the sub-pixel area of the row is electrically connected in sequence to form an integral structure. It is worth noting that, considering the error of the manufacturing process, the first main body part is not necessarily a straight line extending along the first direction.
  • the specific shapes of the first protruding portion 9042 are various, and it is sufficient that the first protruding portion 9042 protrudes from the first body portion 9041 to which it is coupled in the second direction.
  • the orthographic projection of the first main body portion 9041 on the substrate is positioned where the orthographic projection of the first protruding portion 9042 on the substrate and the reset signal line pattern 905 are located.
  • the first protruding portion 9042 can be set back to the reset signal line pattern 905, so that the first protruding portion 9042 can be located between the reset signal line pattern 905 Longer distance.
  • the first body portion 9041 and the first protruding portion 9042 may be formed as an integral structure, but it is not limited to this.
  • the conductive connecting portion layer includes: conductive connecting portion patterns 909 arranged in each of the sub-pixel regions, the conductive connecting portion patterns 909 and the sub-pixel regions are in one-to-one correspondence, and the conductive connecting portion patterns 909 are located in the corresponding sub-pixel regions. In the sub-pixel area.
  • the orthographic projection of the first end 9091 of the conductive connecting portion pattern 909 on the substrate and the orthographic projection of the first protruding portion 9042 on the substrate have a first overlapping area F1, and the first end The portion 9091 and the first protruding portion 9042 can be coupled by punching a hole (such as the first connecting hole 70) in the first overlapping area F1.
  • the second end portion 9092 of the conductive connection portion pattern 909 is coupled to the target coupling portion in the sub-pixel area where it is located, and the target coupling portion may include the first electrode of the seventh transistor corresponding to the current sub-pixel area, and The first pole of the second transistor corresponding to the next sub-pixel area adjacent to the current sub-pixel area in the second direction.
  • the display panel also includes an interlayer dielectric layer (ie, the aforementioned second interlayer insulating layer ILD), and the interlayer dielectric layer is located between the second gate metal layer and the first source in the display panel.
  • the initialization signal line pattern 904 can be arranged in the same layer as the second gate metal layer and can be formed in the same patterning process.
  • the conductive connection portion pattern 909 can be the same as the first source The drain metal layer is arranged in the same layer and can be formed in the same patterning process.
  • a hole is punched in the first overlapping area F1 to realize that the first end 9091 of the conductive connection portion pattern 909 is coupled to the first protruding portion 9042, and the produced via is a via that penetrates the ILD layer.
  • the distance between the position of the via hole and the reset signal line pattern 905 is farther.
  • the side where the initialization signal line pattern 904 is facing away from the reset signal line pattern 905 includes a first protruding portion 9042 and is provided with
  • the orthographic projection of the first end 9091 of the conductive connecting portion pattern 909 on the substrate and the orthographic projection of the first protruding portion 9042 on the substrate have a first overlapping area F1, and the first The end 9091 and the first protruding portion 9042 can be coupled by punching in the first overlapping area F1; this arrangement makes it possible to couple the conductive connection portion and the initialization signal line pattern 904
  • the problem of disturbance in turn, better guarantees the yield rate of the display panel.
  • the first protruding portion 9042 is used to couple the conductive connection portion and the initialization signal line pattern 904.
  • a hole is formed in the first protruding portion 9042, so that the orthographic projection of the via on the substrate can be wrapped by the orthographic projection of the initialization signal line pattern 904 on the substrate, thereby improving the The reliability of the coupling between the initial signal line pattern 904 and the conductive connecting portion pattern 909 better ensures the stability of the display panel during operation.
  • the display panel further includes:
  • a plurality of light-emitting elements corresponding to the plurality of sub-pixel regions one-to-one, and the plurality of light-emitting elements are located on a side of the functional film layer facing away from the substrate;
  • each of the sub-pixel driving circuits includes a seventh transistor T7, and the gate 207g of the seventh transistor T7 is connected to the corresponding reset signal line
  • the pattern 905 is coupled, the first electrode of the seventh transistor T7 serves as the target coupling portion, and the second electrode of the seventh transistor T7 (formed in the 107pd region) extends along the second direction and corresponds to The anode of the light-emitting element is coupled;
  • the conductive connecting portion pattern 909 also includes a second body portion 9093 connected between the first end portion 9091 and the second end portion 9092, the second body portion 9093 extends in a second direction; In each sub-pixel area, along the first direction, the first end portion 9091 of the conductive connection portion pattern 909 protrudes from the second body portion 9093 in a direction away from the second electrode of the seventh transistor.
  • the display panel further includes a plurality of light-emitting elements located on a side of the functional film layer facing away from the substrate, and the plurality of light-emitting elements correspond to the plurality of sub-pixel regions in a one-to-one manner.
  • Each of the light-emitting elements includes: an anode, a light-emitting pattern, and a cathode that are sequentially stacked in a direction away from the substrate; when the display panel is working, a driving signal is provided to the anode and a common signal is provided to the cathode, An electric field is generated between the anode and the cathode, thereby controlling the light-emitting pattern to emit light of a corresponding color; for example, the light-emitting element includes a red light-emitting element capable of emitting red light, and a green light-emitting element capable of emitting green light. Elements and blue light-emitting elements that emit blue light, etc.
  • the display panel further includes a plurality of sub-pixel driving circuits corresponding to the plurality of sub-pixel regions one-to-one, and each of the sub-pixel driving circuits is configured to provide a driving signal for the anode of its corresponding light-emitting element.
  • each of the sub-pixel driving circuits includes a seventh transistor, the gate of the seventh transistor is coupled to the corresponding reset signal line pattern 905, and the first electrode of the seventh transistor serves as the
  • the target coupling portion can be coupled to the corresponding initialization signal line pattern 904 through a corresponding conductive connection portion pattern 909, and the second electrode of the seventh transistor T7 extends along the second direction, and corresponds to The anode of the light-emitting element is coupled.
  • the seventh transistor is mainly used to reset the N2 node before the pixel is charged.
  • the detailed reset process is: the initialization signal line of the seventh transistor coupled through the conductive connection portion pattern 909
  • the graph 904 provides an initialization signal, and the seventh transistor transmits the initialization signal to the N2 node to reset the N2 node.
  • the conductive connection portion pattern 909 is used as an intermediate layer to realize jumpers, and the connection between the conductive connection portion pattern 909 and the seventh transistor and the connection with the initialization signal line pattern 904 can be connected with Punching is achieved.
  • the conductive connection portion pattern 909 further includes a connection between the first end portion 9091 and the second end portion 9092. Between the second body portion 9093, the second body portion 9093 can extend along the second direction, and in the same sub-pixel area, along the first direction, the first end of the conductive connecting portion pattern 909 The portion 9091 protrudes from the second body portion 9093 in a direction away from the second electrode of the seventh transistor.
  • the conductive connecting portion pattern 909 of this structure has a long distance between the first end 9091 and the second electrode of the seventh transistor, so that the ILD is formed on the ILD for coupling to the
  • the via hole is formed at a position farther from the second electrode of the seventh transistor, which is more conducive to avoiding the During the manufacturing process of the via hole, it is easy to bias the via hole to the second electrode of the seventh transistor when the process fluctuates, which causes the problem of signal disturbance, thereby better ensuring the yield rate of the display panel.
  • the second electrode of the seventh transistor is made of a poly layer (that is, an active layer), and the conductive connection portion pattern 909 is formed into the above-mentioned structure, which can better avoid During the manufacturing process of the via hole, it is easy to bias the via hole to the poly layer corresponding to the second pole of the seventh transistor when the process fluctuates, which leads to the problem of signal disturbance, thereby better ensuring the display The yield of the panel.
  • the functional film layer further includes a data line pattern 908 located in each sub-pixel area, and the data line pattern 908 includes a portion extending along the second direction;
  • the width L5 of the initialization signal line pattern 904 along the second direction in the fourth overlap area F4 is smaller than that of the initialization signal line pattern 904 along the second direction in the third overlap area F3. Width L6.
  • the data line pattern 908 has a one-to-one correspondence with the sub-pixel area, the data line pattern 908 is located in the corresponding sub-pixel area, and the data line pattern 908 includes a pattern extending along the second direction.
  • the data line patterns 908 corresponding to the sub-pixel regions in the same column are electrically connected in sequence to form an integral structure.
  • the initialization signal line pattern 904 must at least partially overlap the data line pattern 908.
  • the third overlapping area F3 between the orthographic projection of the initialization signal line pattern 904 on the substrate and the orthographic projection of the conductive connecting portion pattern 909 on the substrate.
  • the width in the two directions is smaller than the width of the initialization signal line pattern 904 in the third overlapping area F3 along the second direction; so that the initialization signal line pattern 904 can be in some areas (for example:
  • the third overlap area F3) has a narrower width along the second direction, which not only helps to reduce the overlap area between the initialization signal line pattern 904 and the data line pattern 908, but also reduces parasitics.
  • the capacitance value of the capacitor and can effectively reduce the layout space of the initialization signal line pattern 904, which is more conducive to saving pixel space, and is conducive to the development of high resolution of the
  • the orthographic projection of the second body portion 9093 on the substrate is in line with the second electrode of the seventh transistor T7.
  • the above-mentioned arrangement of the orthographic projection of the second body portion 9093 on the substrate has a first gap L1 between the orthographic projection of the second electrode of the seventh transistor T7 on the substrate and avoids In the direction perpendicular to the substrate, there is an overlap between the second body portion 9093 and the second electrode of the seventh transistor T7.
  • the threshold value can be set according to actual needs.
  • the threshold value is between 8 ⁇ m and 35 ⁇ m, which may include an endpoint value.
  • the display panel further includes:
  • each of the sub-pixel driving circuits includes a driving transistor and a second transistor T2;
  • the gate 202g of the second transistor T2 is coupled to the reset signal line pattern 905' in the previous sub-pixel area adjacent to the second direction, and the first electrode of the second transistor T2 serves as the In the above-mentioned target coupling portion in the sub-pixel region, the second electrode of the second transistor T2 is coupled to the gate of the driving transistor (that is, the third transistor T3);
  • the second transistor T2 includes two semiconductor parts arranged at intervals along the first direction (as shown in FIG. 19, located in the area marked 102pg), and a first conductor part 80 respectively connecting the two semiconductor parts, so The orthographic projection of the first conductor portion 80 on the substrate does not overlap with the orthographic projection of the first protruding portion 9042 in the previous sub-pixel area on the substrate.
  • each of the sub-pixel driving circuits includes a driving transistor and a second transistor, and the driving transistor is used to generate a driving signal for driving the light-emitting element to emit light.
  • the gate of the second transistor is coupled to the reset signal line pattern 905 in the previous sub-pixel area adjacent in the second direction, and the first electrode of the second transistor serves as the previous sub-pixel In the target coupling portion in the region, the second electrode of the second transistor is coupled to the gate of the driving transistor, and the second transistor is used to couple the initialization signal line to the pixel before it is charged.
  • the initialization signal provided by the graph 904 is transmitted to the N1 node (coupled to the gate of the driving transistor) to realize the reset of the N1 node.
  • the second transistor may be a double gate structure, and the second transistor specifically includes two semiconductor parts spaced apart along the first direction, and a first conductor respectively connected to the two semiconductor parts Part 80, the two semiconductor parts respectively correspond to the channel region of the second transistor.
  • the two semiconductor parts and the first conductor part 80 may be formed as an integral structure.
  • the two semiconductor parts and the third semiconductor part corresponding to the first conductor part 80 may be formed first, and then the The third semiconductor portion is doped to form the third semiconductor portion as the first conductor portion 80.
  • the above-mentioned arrangement of the orthographic projection of the first conductor portion 80 on the substrate does not overlap with the orthographic projection of the first protruding portion 9042 in the previous sub-pixel area on the substrate, so that the via hole is used to couple the initialization signal line pattern 904 and the conductive connection portion pattern 909, it can better prevent the via hole from being biased onto the first conductor portion 80 during process fluctuations, resulting in signal The problem of disturbance, in turn, better guarantees the yield rate of the display panel.
  • the orthographic projection of the first conductor portion 80 on the substrate is the same as that of the first conductive connecting portion pattern 909 in the previous sub-pixel area.
  • the orthographic projections of one end 9091 on the base overlap.
  • the above-mentioned arrangement of the orthographic projection of the first conductor portion 80 on the substrate is similar to that of the first end 9091 of the conductive connecting portion pattern 909 in the previous sub-pixel area on the substrate.
  • the overlap of the orthographic projection not only enables the first end 9091 of the conductive connecting portion pattern 909 to have a larger area to cover the connection via hole between it and the initialization signal line pattern 904; moreover,
  • the layout positions of the first end 9091 of the conductive connecting portion pattern 909 and the first conductor portion 80 are more compact, which is more conducive to saving pixel space, and is conducive to achieving high resolution development of the display panel.
  • each initialization signal line pattern 904 further includes a second protruding portion 9043 coupled to the first body portion 9041.
  • the orthographic projection of the second protruding portion 9043 on the substrate is located between the orthographic projection of the first body portion 9041 on the substrate and the orthographic projection of the reset signal line pattern 905 on the substrate, The orthographic projection of the first conductor portion 80 on the substrate overlaps the orthographic projection of the second protruding portion 9043 and/or the first body portion 9041 on the substrate.
  • each initialization signal line pattern 904 may further include a second protruding portion 9043, and the second protruding portion 9043 may be specifically located between the first body portion 9041 and the reset signal line pattern 905.
  • the second protruding portion 9043, the first protruding portion 9042 and the first main body portion 9041 may be formed as an integral structure.
  • the signal on the part 80 is stable, which avoids the problem of unstable signal of the first conductor part 80 due to capacitive coupling when the external data signal changes due to the floating of the first conductor part 80.
  • the conductive connecting portion pattern 909 further includes a second body portion 9093 connected between the first end portion 9091 and the second end portion 9092, The second body portion 9093 extends along the second direction;
  • One end 801 of the first conductor portion 80 close to the conductive connecting portion pattern 909 in the previous sub-pixel area extends along the second direction, and the orthographic projection of the one end 801 on the substrate is similar to the
  • the second body portion 9093 of the conductive connecting portion pattern 909 has a second gap L2 between the orthographic projections on the substrate, and the second gap L2 is greater than a threshold.
  • the shape of the first conductor portion 80 is various.
  • the first conductor portion 80 has a "gate-shaped" structure, that is, the first conductor portion 80 is close to the previous sub-pixel.
  • One end 801 of the conductive connecting portion pattern 909 in the area extends along the second direction, and one end 802 of the first conductor portion 80 close to the power signal line pattern 901 extends along the second direction.
  • the portion of the first conductor portion 80 between these two ends extends in the first direction.
  • the above-mentioned arrangement of the orthographic projection of one end 801 of the first conductor portion 80 close to the conductive connecting portion pattern 909 in the previous sub-pixel area on the substrate is in contrast to the second main body of the conductive connecting portion pattern 909
  • the portion 9093 has a second gap L2 between the orthographic projections on the substrate to avoid overlap between the second body portion 9093 and the first conductor portion 80 in the direction perpendicular to the substrate .
  • the orthographic projection of the second body portion 9093 on the substrate has a greater difference from the orthographic projection of the first conductor portion 80 on the substrate.
  • the large distance avoids damage to the first conductor part 80 during the manufacturing process of the second main body part 9093.
  • the threshold value can be set according to actual needs.
  • the threshold value is between 8 ⁇ m and 35 ⁇ m, which may include an endpoint value.
  • the orthographic projection of the first end 9091 of the conductive connection portion pattern 909 on the substrate is also related to the initialization signal
  • the orthographic projection of the first body portion 9041 of the line pattern 904 on the substrate forms a second overlapping area F2;
  • the functional film layer further includes a first connecting hole 70 located in each of the sub-pixel regions. In the same sub-pixel region, the orthographic projection of the first connecting hole 70 on the substrate is different from the first connecting hole 70 on the substrate.
  • An overlap area F1 overlaps the second overlap area F2, and the first end 9091 of the conductive connection portion pattern 909 is coupled to the initialization signal line pattern 904 through the first connection hole 70.
  • the orthographic projection of the first end 9091 of the conductive connecting portion pattern 909 on the substrate can be the same as the orthographic projection of the first protruding portion 9042 of the initialization signal line pattern 904 on the substrate.
  • the overlapping area F1 can also have a second overlapping area F2 with the orthographic projection of the first body portion 9041 of the initialization signal line pattern 904 on the substrate.
  • an orthographic projection of the first connecting hole 70 on the substrate can be provided, respectively It overlaps with the first overlap area F1 and the second overlap area F2, so that the layout space of the first connection hole 70 is relatively large, which can ensure that the conductive connection portion pattern 909 and the initialization pattern Good connection performance.
  • the orthographic projection of the first conductor portion 80 of the second transistor T2 on the substrate 40 is the same as that of the first conductor portion 80 in the previous sub-pixel area.
  • the orthographic projection of the connecting hole 70 on the substrate 40 does not overlap.
  • the above-mentioned orthographic projection of the first conductor portion 80 where the second transistor is provided on the substrate 40 is similar to the first connection hole 70 in the previous sub-pixel area on the substrate 40.
  • the orthographic projections on the upper part do not overlap, which can better avoid the problem of the via hole being biased to the first conductor part 80 during process fluctuations during the manufacturing process of the first connecting hole, which may cause signal disturbance. , Thereby better ensuring the yield of the display panel.
  • the functional film layer further includes a power signal line layer, and the power signal line layer includes a power signal line pattern 901 arranged in each of the sub-pixel regions, At least part of the power signal line pattern 901 extends along the second direction;
  • One end 802 of the first conductor portion 80 away from the conductive connecting portion pattern 909 in the previous sub-pixel area extends along the second direction, and the orthographic projection of this end 802 on the substrate is located
  • the orthographic projection of the power signal line pattern 901 in the same sub-pixel area on the substrate completely covers.
  • the power signal line pattern 901 has a one-to-one correspondence with the sub-pixel area, and the power signal line pattern 901 is located in the corresponding sub-pixel area.
  • the power signal line patterns 901 arranged in each column of sub-pixel regions are sequentially coupled along the second direction, and can be formed as an integral structure.
  • the one end 802 of the first conductor portion 80 that is away from the conductive connecting portion pattern 909 in the previous sub-pixel area is extended along the second direction, and the orthographic projection of the one end 802 on the substrate, Is completely covered by the orthographic projection of the power signal line pattern 901 in the same sub-pixel area on the substrate; so that the power signal line pattern 901 can be far away from the previous one in the first conductor portion 80
  • One end of the conductive connecting portion pattern 909 in the sub-pixel area is shielded. Since the power signal transmitted on the power signal line pattern 901 is a stable signal, this shielding can ensure that all data signals change when the external data signal changes.
  • the signal on the first conductor part 80 is stable, which avoids the problem of unstable signal of the first conductor part 80 due to capacitive coupling when the external data signal changes due to the floating of the first conductor part 80.
  • the above arrangement method effectively reduces the layout space occupied by the first conductive portion and the power signal line pattern 901, reduces the pixel structure very well, and is more conducive to the development of high resolution of the display panel.
  • the power signal line pattern 901 has various structures, as shown in FIG. 22.
  • the power signal line pattern 901 can be arranged to extend along the second direction, and the power signal line pattern 901 has a substantially uniform width along the second direction perpendicular to the second direction.
  • the display panel further includes:
  • each of the sub-pixel driving circuits includes a driving transistor and a storage capacitor, and the storage capacitor includes a first electrode plate and a second electrode plate arranged oppositely , The first plate is multiplexed as the gate of the driving transistor, and the second plate is located on the side of the first substrate away from the base;
  • the functional film layer further includes a power signal line layer, the power signal line layer includes a power signal line pattern 901 arranged in each of the sub-pixel regions, and at least part of the power signal line pattern 901 extends along the second direction ,
  • the power signal line pattern 901 includes a first power source part 9011 and a second power source part 9012;
  • the orthographic projection of the first power supply portion 9011 on the substrate overlaps the orthographic projection of the reset signal line patterns 905 located in the same sub-pixel area on the substrate, and overlaps the orthographic projections of the reset signal line patterns 905 located in the same sub-pixel area on the substrate.
  • the orthographic projection of each of the gate line patterns 902 on the substrate overlap; the orthographic projection of the second power supply portion 9012 on the substrate and the corresponding second plate Cts2 of the storage capacitor Cts are in the The orthographic projections on the substrate overlap; the width L3 of the first power supply portion 9011 along the first direction is smaller than the width L4 of the second power supply portion 9012.
  • each of the sub-pixel driving circuits may include a driving transistor and a storage capacitor Cts.
  • the first plate Cts1 of the storage capacitor Cts is multiplexed with the gate of the driving transistor that is coupled to the storage capacitor Cts.
  • the second electrode plate Cts2 is located on the side of the first electrode plate Cts1 facing away from the substrate, and can form a direct area with the first electrode plate.
  • the power signal line pattern 901 may specifically include a first power source part 9011 and a second power source part 9012.
  • the first power source part 9011 and the second power source part 9012 are alternately arranged along the second direction, The adjacent first part and the second part are coupled together.
  • the first power source part 9011 and the second power source part 9012 are formed as an integral structure.
  • the specific layout positions of the first power supply unit 9011 and the second power supply unit 9012 are various.
  • the orthographic projection of the first power supply unit 9011 on the substrate is located in the same sub-pixel area.
  • the orthographic projection of each reset signal line pattern 905 on the substrate overlaps, and overlaps the orthographic projection of each gate line pattern 902 in the same sub-pixel area on the substrate;
  • the orthographic projection of the two power supply units 9012 on the substrate overlaps the orthographic projection of the corresponding second plate of the storage capacitor on the substrate.
  • the width of the first power supply portion 9011 in the first direction is effectively narrowed, so that The overlap area between the first power supply portion 9011 and the reset signal line pattern 905 is reduced, and the overlap area with the gate line pattern 902 is reduced, thereby effectively reducing the power supply signal.
  • the width of the first power supply portion 9011 in the first direction refers to the maximum distance or the minimum distance between two opposite boundaries of the first power supply portion 9011 along the first direction;
  • the width of the second power supply portion 9012 in the first direction refers to the maximum distance or the minimum distance between two opposite boundaries of the second power supply portion 9012 in the first direction.
  • FIG. 25 shows a schematic diagram corresponding to eight sub-pixel regions when the power supply signal line pattern 901 adopts the structure of the first power supply portion 9011 and the second power supply portion 9012.
  • the first connecting hole 70 shown in FIG. 25 only indicates the approximate formation position of the first connecting hole.
  • the actual diameter of the first connecting hole may be larger than that shown in FIG. 25.
  • the specific formation position of a connecting hole can be located at the orthographic projection of the first end 9091 of the conductive connecting portion pattern 909 on the substrate, which overlaps with the orthographic projection of the initialization signal line pattern 904 on the substrate. area.
  • FIG. 26 is a schematic diagram of the active layer in FIG. 25, and FIG. 27 is a schematic diagram of the first gate metal layer in FIG. 25; FIG. 28 is a schematic diagram of the second gate metal layer in FIG. 25; A schematic diagram of a source-drain metal layer; FIG. 30 is a schematic diagram of eight sub-pixel regions corresponding to the second source-drain metal layer when the display panel includes a second source-drain metal layer.
  • the second source-drain metal layer may specifically include: a power compensation pattern 300 and a transfer pattern 310; the power compensation pattern 300 includes a horizontal connection portion 3001 and a vertical connection portion 3002
  • the power compensation pattern 300 is coupled to the power signal line pattern included in the display panel to reduce IR Drop on the power signal line pattern;
  • the switching pattern 310 is one-to-one with the anodes included in the display panel
  • the transfer pattern 310 is used to connect the corresponding anode 320 and the sub-pixel driving circuit for providing driving signals for the anode 320.
  • a second transfer pattern 906 may be further provided between the transfer pattern 310 and the anode included in the display panel, and the second transfer pattern 906 is located in the first source-drain metal layer.
  • a passivation layer may be further provided on the first source/drain metal layer and/or the second source/drain metal layer, such as using inorganic materials such as silicon nitride, silicon oxide, etc., which are not limited in this embodiment.
  • the display panel further includes a pixel defining layer, the pixel defining layer forms pixel openings 330, the pixel openings 330 and the anode 320 are in one-to-one correspondence, and each pixel opening 330 is used for At least part of the corresponding anode 320 is exposed, and the organic light-emitting material layer included in the display panel is formed in each corresponding pixel opening 330.
  • the display panel may include sub-pixels of multiple colors, and the light emitted by the light-emitting elements corresponding to the sub-pixels of different colors has different colors.
  • each pixel unit of the display panel includes a red color.
  • Figures 31 and 32 show the layout of sub-pixel units of various colors in one pixel unit, that is, the arrangement of GGRB pixels.
  • the pixel unit in the display panel may also include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B.
  • the pixel unit of this structure may specifically adopt a strip (strip) RGB arrangement. That is, the one red sub-pixel R, the one green sub-pixel G, and the one blue sub-pixel B are sequentially arranged along the same direction (such as the X direction).
  • the pixel unit of this structure can also specifically adopt a fret-like RGB arrangement.
  • the one red sub-pixel R and one blue sub-pixel B are located in the same row along the X direction, and the one green sub-pixel G is located in the extension. Another row in the X direction.
  • FIG. 33 shows the second gate metal layer and the second source/drain metal layer corresponding to FIG. 32.
  • sub-pixels corresponding to different colors may be set, and the overlap area between the orthographic projection of the transfer pattern 310 on the substrate and the orthographic projection of the corresponding second plate Cst2 of the storage capacitor on the substrate different.
  • the orthographic projection of the transfer pattern 310 on the substrate and the orthographic projection of the corresponding second plate Cst2 of the storage capacitor on the substrate are formed The first overlap area J1.
  • the orthographic projection of the transfer pattern 310 on the substrate and the orthographic projection of the corresponding second electrode plate Cst2 of the storage capacitor on the substrate form a second overlapping area J2.
  • the orthographic projection of the transfer pattern 310 on the substrate and the orthographic projection of the corresponding second plate Cst2 of the storage capacitor on the substrate form a third overlapping area J3.
  • the second overlapping area J2 is smaller than the first overlapping area J1, and the first overlapping area J1 is smaller than the third overlapping area J3.
  • the above arrangement can better balance the RC (resistance-capacitance) loading on the power signal line pattern 901 corresponding to the pixel units of different colors.
  • FIG. 34 is a cross-sectional view of FIG. 32 along the C1C2 direction.
  • the substrate 40 and the sixth drain formation region 106pd that is, the active layer in this region is used to form the drain of the sixth transistor T6
  • the space also includes other film layers such as a buffer layer, which are not shown in FIG. 34.
  • FIG. 34 also shows a first gate insulating layer 41, a second gate insulating layer 42, an interlayer insulating layer 43, a first flat layer 44, and a second flat layer 45.
  • the functional film layer further includes a power signal line layer, and the power signal line layer includes a power signal line pattern 901 arranged in each of the sub-pixel regions, At least part of the power signal line pattern 901 extends along the second direction;
  • the functional film layer also includes an auxiliary power supply layer.
  • the auxiliary power supply layer includes an auxiliary power supply pattern 60 arranged in each of the sub-pixel regions.
  • the orthographic projection of the power signal line pattern 901 in the pixel area on the substrate has an overlapping area, and the auxiliary power source pattern 60 and the power signal line pattern 901 are coupled in the overlapping area.
  • the auxiliary power supply pattern 60 corresponds to the sub-pixel area one-to-one, and the auxiliary power supply pattern 60 is located in the corresponding sub-pixel area.
  • the auxiliary power supply pattern 60 can be formed in the same layer and the same material as the second plate of the storage capacitor, that is, can be formed in the same patterning process.
  • the orthographic projection of the auxiliary power supply pattern 60 on the substrate can be set to overlap with the orthographic projection of the power signal line pattern 901 located in the same sub-pixel area on the substrate.
  • the auxiliary power supply pattern 60 and the power signal line pattern 901 can be coupled through vias provided in the overlapping region.
  • the auxiliary power supply pattern 60 is coupled to the power signal line pattern 901, the RC (resistance-capacitance) loading on the power signal line pattern 901 is well reduced, and the power signal is reduced.
  • the IR drop (voltage drop) on the line pattern 901 better guarantees the stability of the display panel.
  • the display panel further includes: a plurality of sub-pixel driving circuits corresponding to the plurality of sub-pixel regions one-to-one, and each of the sub-pixel driving circuits includes driving A transistor and a second transistor;
  • the gate of the second transistor is coupled to the reset signal line pattern 905 in the previous sub-pixel region adjacent in the second direction, and the first electrode of the second transistor serves as the previous sub-pixel.
  • the second electrode of the second transistor includes a first electrode portion 51 and a second electrode portion 52 that are coupled to each other, and the first electrode portion 51 extends along the second direction, The second electrode portion 52 extends along a third direction, the third direction intersects both the first direction and the second direction, and the first electrode portion 51 is located between the semiconductor portion of the second transistor and the second direction. Between the second electrode portions 52, the second electrode portion 52 is coupled to the gate of the driving transistor;
  • the orthographic projection of the first electrode portion 51 on the substrate and the orthographic projection of the second electrode portion 52 on the substrate are both the corresponding orthographic projection of the auxiliary power supply pattern 60 on the substrate cover.
  • the second electrode of the second transistor is used for coupling with the gate of the driving transistor.
  • the second electrode may specifically include: a first electrode portion 51 and a second electrode that are coupled to each other.
  • the first electrode portion 51 is located between the semiconductor portion of the second transistor and the second electrode portion 52, and the second electrode portion 52 is coupled to the gate of the driving transistor.
  • the specific layout of the first electrode portion 51 and the second electrode portion 52 is various.
  • the first electrode portion 51 extends along the second direction
  • the second electrode portion 52 extends along the third direction.
  • the direction extends, and the third direction intersects both the first direction and the second direction.
  • the above-mentioned orthographic projection of the first electrode portion 51 on the substrate and the orthographic projection of the second electrode portion 52 on the substrate are both provided on the substrate by the corresponding auxiliary power supply pattern 60
  • the orthographic projection coverage not only ensures the stability of the potential of the N1 node, but also effectively reduces the layout space required by the second pole of the second transistor and the power signal line pattern 901, thereby providing a good
  • the reduced pixel structure is more conducive to the development of high resolution of the display panel.
  • the auxiliary power supply pattern 60 includes a first auxiliary sub-graphic 601 and a second auxiliary sub-graphic 602 that are coupled to each other. Extending in two directions, at least part of the second auxiliary sub-pattern 602 extends along the first direction; the orthographic projection of the first auxiliary sub-pattern 601 on the substrate covers the first electrode portion 51 in the The orthographic projection on the substrate and the orthographic projection of the second electrode portion 52 on the substrate.
  • the auxiliary power supply graphic 60 includes a first auxiliary sub-graphic 601 and a second auxiliary sub-graphic 602 that are coupled to each other.
  • the sub-graphic 601 and the second auxiliary sub-graphic 602 may be formed as an integral structure.
  • the first auxiliary sub-pattern 601 extends in the second direction, and at least a part of the second auxiliary sub-pattern 602 extends in the first direction, so that the auxiliary power supply pattern 60 is formed into an L-like shape.
  • the auxiliary power source pattern 60 Since the auxiliary power source pattern 60 is coupled to the power signal line pattern 901, the auxiliary power source pattern 60 has a stable electric potential, and the orthographic projection of the first auxiliary sub-pattern 601 on the substrate is covered
  • the orthographic projection of the first electrode portion 51 on the substrate and the orthographic projection of the second electrode portion 52 on the substrate not only ensure the potential stability of the N1 node, but also effectively reduce the The layout space required by the second pole of the second transistor, the power signal line pattern 901, and the auxiliary power pattern 60, which greatly reduces the pixel structure, and is more conducive to the high resolution of the display panel develop.
  • the width of the first auxiliary sub-pattern 601 is greater than the width of the corresponding power signal line pattern 901.
  • the above-mentioned setting of the width of the first auxiliary sub-pattern 601 is greater than the width of the corresponding power signal line pattern 901, so that the auxiliary power pattern 60 has a larger area, which is not only conducive to reducing the power signal line pattern 901
  • the IR drop is also more conducive to the realization of the coupling between the auxiliary power supply pattern 60 and the power signal line pattern 901.
  • the orthographic projection of the first electrode portion 51 on the substrate and the orthographic projection of the second electrode portion 52 on the substrate, All are covered by the orthographic projection of the corresponding power signal line pattern 901 on the substrate.
  • the above-mentioned orthographic projection of the first electrode portion 51 on the substrate and the orthographic projection of the second electrode portion 52 on the substrate are both formed on the substrate by the corresponding power signal line pattern 901
  • the orthographic projection coverage not only ensures the stability of the potential of the N1 node, but also effectively reduces the layout space required by the second pole of the second transistor and the power signal line pattern 901, thereby providing a good
  • the reduced pixel structure is more conducive to the development of high resolution of the display panel.
  • the functional film layer includes: a gate line pattern 902 and a light emission control signal line pattern 903 located in each sub-pixel area; in the same sub-pixel area, along the second direction, the gate line
  • the pattern 902, the light-emitting control signal line pattern 903, the reset signal line pattern 905, and the initialization signal line pattern 904 are arranged in sequence;
  • the functional film layer also includes a power signal line pattern 901 and a power signal line pattern located in each sub-pixel area.
  • the data line pattern 908, the power signal line pattern 901 and the data line pattern 908 all include a portion extending along the second direction.
  • the display panel further includes: light-emitting elements corresponding to the plurality of sub-pixel regions one-to-one; sub-pixel driving circuits corresponding to the plurality of sub-pixel regions one-to-one, each sub-pixel driving circuit includes: a driving transistor, a first Transistor, second transistor, fourth transistor, fifth transistor, sixth transistor, and seventh transistor.
  • the gate of the driving transistor is coupled to the second electrode of the first transistor, the first electrode of the driving transistor is coupled to the second electrode of the fifth transistor, and the The second electrode of the driving transistor is coupled to the first electrode of the first transistor; the gate of the first transistor is coupled to the gate line pattern 902;
  • the gate of the second transistor is coupled to the reset signal line pattern 905 in the previous sub-pixel region adjacent in the second direction, and the first electrode of the second transistor serves as the previous sub-pixel.
  • the second electrode of the second transistor is coupled to the gate of the driving transistor;
  • the gate of the fourth transistor is coupled to the gate line pattern 902, the first electrode of the fourth transistor is coupled to the data line pattern 908, and the second electrode of the fourth transistor is coupled to the driver The first pole of the transistor is coupled;
  • the gate of the fifth transistor is coupled to the light emission control signal line pattern 903, and the first electrode of the fifth transistor is coupled to the power signal line pattern 901;
  • the gate of the sixth transistor is coupled to the light emission control signal line pattern 903, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is Coupled with the corresponding light-emitting element;
  • the second electrode of the seventh transistor is coupled to the light-emitting element, the gate of the seventh transistor is coupled to the reset signal line pattern 905, and the first electrode of the seventh transistor is coupled to a second initialization signal
  • the line pattern 904 is coupled.
  • each of the sub-pixel driving circuits includes: 7 thin film transistors and 1 capacitor.
  • Each transistor included in the sub-pixel driving circuit adopts a P-type transistor.
  • the driving transistor is the third transistor.
  • the first electrode of each transistor is the source, and the second electrode of each transistor is the drain.
  • the first transistor T1 has a double-gate structure, the gate 201g of the first transistor T1 is coupled to the gate line pattern 902, and the source S1 of the first transistor T1 is coupled to the first transistor T1.
  • the drain D3 of the three transistor T3 ie, the driving transistor
  • the drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3.
  • the second transistor T2 has a double-gate structure.
  • the gate 202g of the second transistor T2 is coupled to the reset signal line pattern 905' in the previous sub-pixel area adjacent to the second direction.
  • the source electrode S2 serves as the target coupling portion in the previous sub-pixel area and is coupled to the initialization signal line pattern 904' in the previous sub-pixel area.
  • the drain electrode D2 of the second transistor T2 is connected to the third The gate 203g of the transistor T3 is coupled.
  • the gate 204g of the fourth transistor T4 is coupled to the gate line pattern 902, the source S4 of the fourth transistor T4 is coupled to the data line pattern 908, and the drain D4 of the fourth transistor T4 is coupled to the source of the third transistor T3. S3 is coupled.
  • the gate 205g of the fifth transistor T5 is coupled to the light emission control signal line pattern 903, the source S5 of the fifth transistor T5 is coupled to the power signal line pattern 901, and the drain D5 of the fifth transistor T5 is coupled to the source of the third transistor T3 ⁇ S3 is coupled.
  • the gate 206g of the sixth transistor T6 is coupled to the light emission control signal line pattern 903, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the corresponding light emission
  • the anode of the element EL is coupled.
  • the gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern 905, the drain D7 of the seventh transistor T7 is coupled to the anode of the corresponding light emitting element EL, and the source S7 of the seventh transistor T7 is coupled to the initialization
  • the signal line pattern 904 is coupled.
  • the pixel driving circuit further includes a storage capacitor Cst, the first plate Cst1 of the storage capacitor Cst is multiplexed as the gate 203g of the third transistor T3, the second plate Cst2 of the storage capacitor Cst and the power signal line pattern 901 coupled.
  • the sub-pixel driving circuit provided by the above-mentioned embodiment, it not only avoids the problem that the via hole is easily deflected to the nearby reset signal line pattern 905 when the process fluctuates during the punching process, and the signal is disturbed, which is better. This ensures the yield rate of the display panel; moreover, the pixel structure adopting the sub-pixel driving circuit has a smaller size, which is more conducive to the realization of high resolution of the display panel.
  • the embodiments of the present disclosure also provide a display device, including the display panel provided in the above-mentioned embodiments.
  • the side where the initialization signal line pattern 904 is disposed facing away from the reset signal line pattern 905 includes a first protruding portion 9042, and the conductive connecting portion pattern 909 is disposed.
  • the orthographic projection of the first end 9091 on the substrate and the orthographic projection of the first protruding portion 9042 on the substrate have a first overlapping area F1, and the first end 9091 is connected to the first
  • the protruding portion 9042 can be coupled by punching a hole in the first overlap area F1; this arrangement makes the via hole for coupling the conductive connection portion and the initialization signal line pattern 904 and the reset signal line
  • the yield rate of the display panel is guaranteed.
  • the first protruding portion 9042 is used to couple the conductive connection portion and the initialization signal line pattern 904.
  • a hole is formed in the first protruding portion 9042, so that the orthographic projection of the via on the substrate can be wrapped by the orthographic projection of the initialization signal line pattern 904 on the substrate, thereby improving the The reliability of the coupling between the initial signal line pattern 904 and the conductive connecting portion pattern 909 better ensures the stability of the display panel during operation.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned display panel, it also has the above-mentioned beneficial effects, which will not be repeated here.
  • the display device may be any product or component with a display function, such as a TV, a monitor, a digital photo frame, a mobile phone, a tablet computer, and the like.
  • the embodiment of the present disclosure also provides a manufacturing method of a display panel, which is used to manufacture the display panel provided in the above embodiment, and the manufacturing method includes:
  • the functional film layer includes: a reset signal line layer, an initialization signal line layer, and a conductive connection layer;
  • the reset signal line layer includes: a reset signal line pattern 905 arranged in each of the sub-pixel regions, and the reset signal line pattern 905 extends along a first direction;
  • the initialization signal line layer includes: an initialization signal line pattern 904 arranged in each of the sub-pixel regions.
  • the initialization signal line pattern 904 includes a first body portion 9041 and a first protruding portion 9042 that are coupled to each other.
  • the first body portion 9041 extends along the first direction.
  • the orthographic projection of the first body portion 9041 on the substrate is located on the orthographic projection of the first protruding portion 9042 on the substrate. Between the projection and the orthographic projection of the reset signal line pattern 905 on the substrate;
  • the conductive connection portion layer includes: a conductive connection portion pattern 909 arranged in each of the sub-pixel areas, and in the same sub-pixel area, the first end portion 9091 of the conductive connection portion pattern 909 is on the substrate Orthographic projection, and the orthographic projection of the first protruding portion 9042 on the substrate has a first overlapping area F1, in the first overlapping area F1, the first end 9091 and the first protruding portion 9042
  • the second end 9092 of the conductive connecting portion pattern 909 is coupled to the target coupling portion in the sub-pixel area where it is located, and the orthographic projection of the reset signal line pattern 905 on the substrate is located on the target Between the orthographic projection of the coupling portion on the substrate and the orthographic projection of the initialization signal line pattern 904 on the substrate.
  • the plurality of sub-pixel regions arranged in an array can be divided into multiple rows of sub-pixel regions sequentially arranged along the second direction, and multiple columns of sub-pixel regions sequentially arranged along the first direction.
  • Each row of sub-pixel regions includes a plurality of sub-pixel regions spaced along the first direction
  • each column of sub-pixel regions includes a plurality of sub-pixel regions spaced along the second direction.
  • the first direction intersects the second direction.
  • the first direction includes the X direction
  • the second direction includes the Y direction.
  • the reset signal line layer includes a reset signal line pattern 905 arranged in each of the sub-pixel regions, and the reset signal line pattern 905 extends along the first direction.
  • the reset signal line pattern 905 corresponds to the sub-pixel area one-to-one, the reset signal line pattern 905 is located in the corresponding sub-pixel area, and each of the reset signal line patterns corresponding to the sub-pixel areas in the same row 905 is electrically connected in sequence to form an integral structure.
  • the initialization signal line layer includes: initialization signal line patterns 904 arranged in each of the sub-pixel regions, the initialization signal line patterns 904 correspond to the sub-pixel regions one-to-one, and the initialization signal line patterns 904 are located in the corresponding sub-pixel regions. In the sub-pixel areas, the initialization signal line patterns 904 corresponding to the sub-pixel areas in the same row are electrically connected in sequence to form an integral structure.
  • Each of the initialization signal line patterns 904 includes a first body portion 9041 and a first protruding portion 9042 that are coupled to each other.
  • the first body portion 9041 extends along the first direction and corresponds to the sub-pixel regions in the same row.
  • the first body portion 9041 in each of the initialization signal line patterns 904 is electrically connected in sequence to form an integral structure. It is worth noting that, considering the error of the manufacturing process, the first main body part is not necessarily a straight line extending along the first direction.
  • the specific shapes of the first protruding portion 9042 are various, and it is sufficient that the first protruding portion 9042 protrudes from the first body portion 9041 to which it is coupled in the second direction.
  • the orthographic projection of the first main body portion 9041 on the substrate is positioned where the orthographic projection of the first protruding portion 9042 on the substrate and the reset signal line pattern 905 are located.
  • the first protruding portion 9042 can be set back to the reset signal line pattern 905, so that the first protruding portion 9042 can be located between the reset signal line pattern 905 Longer distance.
  • the first body portion 9041 and the first protruding portion 9042 may be formed as an integral structure, but it is not limited to this.
  • the conductive connecting portion layer includes: conductive connecting portion patterns 909 arranged in each of the sub-pixel regions, the conductive connecting portion patterns 909 and the sub-pixel regions are in one-to-one correspondence, and the conductive connecting portion patterns 909 are located in the corresponding sub-pixel regions. In the sub-pixel area.
  • the orthographic projection of the first end 9091 of the conductive connecting portion pattern 909 on the substrate and the orthographic projection of the first protruding portion 9042 on the substrate have a first overlapping area F1, and the first end The portion 9091 and the first protruding portion 9042 can be coupled by punching a hole in the first overlapping area F1.
  • the second end portion 9092 of the conductive connection portion pattern 909 is coupled to the target coupling portion in the sub-pixel area where it is located, and the target coupling portion may include the first electrode of the seventh transistor corresponding to the current sub-pixel area, and The first pole of the second transistor corresponding to the next sub-pixel area adjacent to the current sub-pixel area in the second direction.
  • the target coupling portion can be arranged in various positions. For example, it can be arranged in the same sub-pixel area.
  • the orthographic projection of the reset signal line pattern 905 on the substrate is located at the target coupling portion. Between the orthographic projection on the substrate and the orthographic projection of the initialization signal line pattern 904 on the substrate.
  • the display panel also includes an interlayer dielectric layer (ie, the aforementioned second interlayer insulating layer ILD), and the interlayer dielectric layer is located between the second gate metal layer and the first source in the display panel.
  • the initialization signal line pattern 904 can be arranged in the same layer as the second gate metal layer, and can be formed in the same patterning process.
  • the conductive connection pattern 909 can be the same as the first source The drain metal layer is arranged in the same layer and can be formed in the same patterning process.
  • a hole is punched in the first overlapping area F1 to realize that the first end 9091 of the conductive connection portion pattern 909 is coupled to the first protruding portion 9042, and the produced via is a via that penetrates the ILD layer.
  • the distance between the position of the via hole and the reset signal line pattern 905 is farther.
  • the side where the initialization signal line pattern 904 is located away from the reset signal line pattern 905 includes a first protruding portion 9042, and the conductive connection is provided.
  • the orthographic projection of the first end 9091 of the part pattern 909 on the substrate and the orthographic projection of the first protruding portion 9042 on the substrate have a first overlapping area F1, and the first end 9091 and The first protruding portion 9042 can be coupled by punching a hole in the first overlapping area F1; this arrangement makes it possible to couple the conductive connecting portion and the via hole of the initialization signal line pattern 904 with the
  • the first protruding portion 9042 is used to couple the conductive connection portion and the initialization signal line pattern 904.
  • a hole is formed in the first protruding portion 9042, so that the orthographic projection of the via on the substrate can be wrapped by the orthographic projection of the initialization signal line pattern 904 on the substrate, thereby improving the The reliability of the coupling between the initial signal line pattern 904 and the conductive connecting portion pattern 909 better ensures the stability of the display panel during operation.

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Abstract

一种显示面板及其制作方法、显示装置。显示面板包括：多个子像素区，以及位于各子像素区中的复位信号线图形（905）、初始化信号线图形（904）和导电连接部图形（909）；初始化信号线图形（904）包括相耦接的第一主体部分（9041）和第一突出部分（9042），第一主体部分（9041）在基底上的正投影位于第一突出部分（9042）在基底上的正投影与复位信号线图形（905）在基底上的正投影之间；导电连接部图形（909）的第一端部（9091）在基底上的正投影，与第一突出部分（9042）在基底上的正投影具有第一交叠区域（F1），在第一交叠区域（F1），第一端部（9091）与第一突出部分（9042）耦接，导电连接部图形（909）的第二端部（9092）与目标耦接部耦接，复位信号线图形（905）在基底上的正投影，位于目标耦接部在基底上的正投影与初始化信号线图形（904）在基底上的正投影之间。

Description

显示面板及其制作方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其制作方法、显示装置。
背景技术
随着有机发光二极管(英文：Organic Light-Emitting Diode；简称：OLED)显示技术的迅速发展，消费者对OLED显示装置的屏占比和分辨率的要求越来越高。OLED显示装置的屏占比即有效显示区(英文：Active Area，简称：AA区)在显示装置前面板中占的比例，OLED显示装置的分辨率即AA区中包括的像素结构的数量。OLED显示装置的屏占比越大，消费者的体验越好。OLED显示装置的分辨率越高，其显示的图像越清晰。
发明内容
本公开的目的在于提供一种显示面板及其制作方法、显示装置。
本公开的第一方面提供一种一种显示面板，包括：基底、设置在所述基底上的功能膜层；还包括阵列排布的多个子像素区；
所述功能膜层包括：复位信号线层、初始化信号线层、导电连接部层；
所述复位信号线层包括：设置于各所述子像素区中的复位信号线图形，所述复位信号线图形沿第一方向延伸；
所述初始化信号线层包括：设置于各所述子像素区中的初始化信号线图形，所述初始化信号线图形包括相耦接的第一主体部分和第一突出部分，所述第一主体部分沿所述第一方向延伸，在同一子像素区中，所述第一主体部分在所述基底上的正投影位于所述第一突出部分在所述基底上的正投影与所述复位信号线图形在所述基底上的正投影之间；
所述导电连接部层包括：设置于各所述子像素区中的导电连接部图形，在同一子像素区中，所述导电连接部图形的第一端部在所述基底上的正投影， 与所述第一突出部分在所述基底上的正投影具有第一交叠区域，在所述第一交叠区域，该第一端部与该第一突出部分耦接，所述导电连接部图形的第二端部与其所在子像素区中的目标耦接部耦接，所述复位信号线图形在所述基底上的正投影，位于所述目标耦接部在所述基底上的正投影与所述初始化信号线图形在所述基底上的正投影之间。
可选的，所述显示面板还包括：
与所述多个子像素区一一对应的多个发光元件，所述多个发光元件位于所述功能膜层背向所述基底的一侧；
与所述多个子像素区一一对应的多个子像素驱动电路，每个所述子像素驱动电路均包括第七晶体管，所述第七晶体管的栅极与对应的所述复位信号线图形耦接，所述第七晶体管的第一极作为所述目标耦接部，所述第七晶体管的第二极沿所述第二方向延伸，且与对应的发光元件的阳极耦接；
所述导电连接部图形还包括连接在所述第一端部和所述第二端部之间的第二主体部分，所述第二主体部分沿第二方向延伸；在同一个子像素区中，沿所述第一方向，所述导电连接部图形的第一端部，向远离所述第七晶体管的第二极的方向突出于所述第二主体部分。
可选的，所述功能膜层还包括位于各子像素区中的数据线图形，所述数据线图形包括沿所述第二方向延伸的部分；
所述初始化信号线图形在所述基底上的正投影与所述导电连接部图形在所述基底上的正投影存在第三交叠区域；
所述初始化信号线图形在所述基底上的正投影与所述数据线图形在所述基底上的正投影存在第四交叠区域；
在所述第四交叠区域所述初始化信号线图形沿所述第二方向的宽度，小于在所述第三交叠区域所述初始化信号线图形沿所述第二方向的宽度。
可选的，在同一个子像素区中，所述第二主体部分在所述基底上的正投影，与所述第七晶体管的第二极在所述基底上的正投影之间具有第一间隙，所述第一间隙大于阈值。
可选的，所述显示面板还包括：
与所述多个子像素区一一对应的多个子像素驱动电路，每个所述子像素 驱动电路均包括驱动晶体管和第二晶体管；
所述第二晶体管的栅极与沿所述第二方向相邻的上一个子像素区中的所述复位信号线图形耦接，所述第二晶体管的第一极作为所述上一个子像素区中的所述目标耦接部，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接；
所述第二晶体管包括沿所述第一方向间隔设置的两个半导体部分，以及分别连接所述两个半导体部分的第一导体部分，所述第一导体部分在所述基底上的正投影，与所述上一个子像素区中的所述第一突出部分在所述基底上的正投影不交叠。
可选的，所述第一导体部分在所述基底上的正投影，与所述上一个子像素区中的所述导电连接部图形的第一端部在所述基底上的正投影交叠。
可选的，每个所述初始化信号线图形还包括与所述第一主体部分耦接的第二突出部分，在同一子像素区中，所述第二突出部分在所述基底上的正投影位于所述第一主体部分在所述基底上的正投影与所述复位信号线图形在所述基底上的正投影之间，所述第一导体部分在所述基底上的正投影与所述第二突出部分在所述基底上的正投影交叠。
可选的，所述导电连接部图形还包括连接在所述第一端部和所述第二端部之间的第二主体部分，该第二主体部分沿第二方向延伸；
所述第一导体部分中靠近所述上一个子像素区中的所述导电连接部图形的一端沿所述第二方向延伸，该一端在所述基底上的正投影，与该导电连接部图形的第二主体部分在所述基底上的正投影之间具有第二间隙，所述第二间隙大于阈值。
可选的，在同一子像素区中，所述导电连接部图形的第一端部在所述基底上的正投影，还与所述初始化信号线图形的第一主体部分在所述基底上的正投影形成第二交叠区域；
所述功能膜层还包括位于各所述子像素区中的第一连接孔，在同一子像素区中，所述第一连接孔在所述基底上的正投影，分别与所述第一交叠区域和所述第二交叠区域交叠，所述导电连接部图形的第一端部通过所述第一连接孔与所述初始化信号线图形耦接。
可选的，所述第二晶体管的所述第一导体部分在所述基底上的正投影，与所述上一个子像素区中的所述第一连接孔在所述基底上的正投影不交叠。
可选的，所述功能膜层还包括电源信号线层，所述电源信号线层包括设置于各所述子像素区中的电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸；
所述第一导体部分中远离所述上一个子像素区中的所述导电连接部图形的一端沿所述第二方向延伸，该一端在所述基底上的正投影，被位于同一子像素区中的所述电源信号线图形在所述基底上的正投影完全覆盖。
可选的，所述显示面板还包括：
与所述多个子像素区一一对应的多个子像素驱动电路，每个所述子像素驱动电路均包括驱动晶体管和存储电容，所述存储电容包括相对设置的第一极板和第二极板，所述第一极板复用为所述驱动晶体管的栅极，所述第二极板位于所述第一基板背向所述基底的一侧；
所述功能膜层还包括电源信号线层，所述电源信号线层包括设置于各所述子像素区中的电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸，所述电源信号线图形包括第一电源部和第二电源部；
所述第一电源部在所述基底上的正投影与位于同一子像素区中的各所述复位信号线图形在所述基底上的正投影交叠，并与位于同一子像素区中的各所述栅线图形在所述基底上的正投影交叠；所述第二电源部在所述基底上的正投影与对应的所述存储电容的第二极板在所述基底上的正投影交叠；沿所述第一方向所述第一电源部的宽度小于所述第二电源部的宽度。
可选的，所述功能膜层还包括电源信号线层，所述电源信号线层包括设置于各所述子像素区中的电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸；
所述功能膜层还包括辅助电源层，所述辅助电源层包括设置于各所述子像素区中的辅助电源图形，所述辅助电源图形在所述基底上的正投影与位于同一子像素区中的电源信号线图形在所述基底上的正投影存在交叠区域，所述辅助电源图形与该电源信号线图形在该交叠区域耦接。
可选的，所述显示面板还包括：与所述多个子像素区一一对应的多个子 像素驱动电路，每个所述子像素驱动电路均包括驱动晶体管和第二晶体管；
所述第二晶体管的栅极与沿所述第二方向相邻的上一个子像素区中的所述复位信号线图形耦接，所述第二晶体管的第一极作为所述上一个子像素区中的所述目标耦接部，所述第二晶体管的第二极包括相耦接的第一电极部和第二电极部，所述第一电极部沿第二方向延伸，所述第二电极部沿第三方向延伸，所述第三方向与所述第一方向和所述第二方向均相交，所述第一电极部位于所述第二晶体管的半导体部分与所述第二电极部之间，所述第二电极部与所述驱动晶体管的栅极耦接；
所述第一电极部在所述基底上的正投影和所述第二电极部在所述基底上的正投影，均被对应的所述辅助电源图形在所述基底上的正投影覆盖。
可选的，所述辅助电源图形包括相耦接的第一辅助子图形和第二辅助子图形，所述第一辅助子图形沿第二方向延伸，所述第二辅助子图形的至少部分沿所述第一方向延伸；
所述第一辅助子图形在所述基底上的正投影覆盖所述第一电极部在所述基底上的正投影和所述第二电极部在所述基底上的正投影。
可选的，沿所述第一方向，所述第一辅助子图形的宽度大于对应的所述电源信号线图形的宽度。
可选的，所述第一电极部在所述基底上的正投影和所述第二电极部在所述基底上的正投影，均被对应的所述电源信号线图形在所述基底上的正投影覆盖。
可选的，所述功能膜层包括：位于各子像素区中的栅线图形、发光控制信号线图形；在同一所述子像素区中，沿第二方向，所述栅线图形、所述发光控制信号线图形、所述复位信号线图形和所述初始化信号线图形依次排列；
所述功能膜层还包括位于各子像素区中的电源信号线图形和数据线图形，所述电源信号线图形和所述数据线图形均包括沿所述第二方向延伸的部分；
所述显示面板还包括：
与所述多个子像素区一一对应的发光元件；
与所述多个子像素区一一对应的子像素驱动电路，每个子像素驱动电路均包括：驱动晶体管、第一晶体管、第二晶体管、第四晶体管、第五晶体管、 第六晶体管和第七晶体管；
在同一子像素区中，所述驱动晶体管的栅极与所述第一晶体管的第二极耦接，所述驱动晶体管的第一极与所述第五晶体管的第二极耦接，所述驱动晶体管的第二极与所述第一晶体管的第一极耦接；
所述第一晶体管的栅极与所述栅线图形耦接；
所述第二晶体管的栅极与沿所述第二方向相邻的上一个子像素区中的所述复位信号线图形耦接，所述第二晶体管的第一极作为所述上一个子像素区中的所述目标耦接部，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接；
所述第四晶体管的栅极与所述栅线图形耦接，所述第四晶体管的第一极与所述数据线图形耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
所述第五晶体管的栅极与所述发光控制信号线图形耦接，所述第五晶体管的第一极与所述电源信号线图形耦接；
所述第六晶体管的栅极与所述发光控制信号线图形耦接，所述第六晶体管的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管的第二极与对应的所述发光元件耦接；
所述第七晶体管的第二极与所述发光元件耦接，所述第七晶体管的栅极与所述复位信号线图形耦接，所述第七晶体管的第一极与第二初始化信号线图形耦接。
基于上述显示面板的技术方案，本公开的第二方面提供一种显示装置，包括上述显示面板。
基于上述显示面板的技术方案，本公开的第三方面提供一种显示面板的制作方法，包括：
在基底上制作功能膜层，并形成阵列排布的多个子像素区；
所述功能膜层包括：复位信号线层、初始化信号线层、导电连接部层；
所述复位信号线层包括：设置于各所述子像素区中的复位信号线图形，所述复位信号线图形沿第一方向延伸；
所述初始化信号线层包括：设置于各所述子像素区中的初始化信号线图 形，所述初始化信号线图形包括相耦接的第一主体部分和第一突出部分，所述第一主体部分沿所述第一方向延伸，在同一子像素区中，所述第一主体部分在所述基底上的正投影位于所述第一突出部分在所述基底上的正投影与所述复位信号线图形在所述基底上的正投影之间；
所述导电连接部层包括：设置于各所述子像素区中的导电连接部图形，在同一子像素区中，所述导电连接部图形的第一端部在所述基底上的正投影，与所述第一突出部分在所述基底上的正投影具有第一交叠区域，在所述第一交叠区域，该第一端部与该第一突出部分耦接，所述导电连接部图形的第二端部与其所在子像素区中的目标耦接部耦接，所述复位信号线图形在所述基底上的正投影，位于所述目标耦接部在所述基底上的正投影与所述初始化信号线图形在所述基底上的正投影之间。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为现有技术中子像素布局示意图；
图2为图1中有源层的布局示意图；
图3为图1中第一栅金属层的布局示意图；
图4为图1中第二栅金属层的布局示意图；
图5为图1中源漏金属层的布局示意图；
图6为本公开实施例提供的子像素驱动电路的电路图；
图7为本公开实施例提供的子像素驱动电路的驱动时序图；
图8为本公开实施例提供的子像素区的第一布局示意图；
图9为本公开实施例提供的子像素区的第二布局示意图；
图10为图8中有源层的布局示意图；
图11为图8中第一栅金属层的布局示意图；
图12为图8中第二栅金属层的布局示意图；
图13为图8中源漏金属层的布局示意图；
图14为图8中沿A1A2方向的截面示意图；
图15为本公开实施例提供的子像素区的第三布局示意图；
图16为图15中X1部分的第一放大示意图；
图17为图15中X1部分的第二放大示意图；
图18为图17中沿B1B2方向的截面示意图；
图19为图15中有源层的布局示意图；
图20为图15中第一栅金属层的布局示意图；
图21为图15中第二栅金属层的布局示意图；
图22为图15中源漏金属层的布局示意图；
图23为本公开实施例提供的子像素区的第四布局示意图；
图24为本公开实施例提供的电源信号线图形的结构示意图；
图25为本公开实施例提供的子像素区的第五布局示意图；
图26为图25中有源层的布局示意图；
图27为图25中第一栅金属层的布局示意图；
图28为图25中第二栅金属层的布局示意图；
图29为图25中源漏金属层的布局示意图；
图30为本公开实施例提供的第二源漏金属层的布局示意图；
图31为本公开实施例提供的第二源漏金属层和阳极层的布局示意图；
图32为本公开实施例提供的子像素区的第六五布局示意图；
图33为图32中的第二栅金属层和第二源漏金属层的布局示意图；
图34为图32中沿C1C2方向的截面示意图。
具体实施方式
为了进一步说明本公开实施例提供的显示面板及其制作方法、显示装置，下面结合说明书附图进行详细描述。
AMOLED显示面板的结构包括：基底，设置在基底上的多个子像素驱动电路，以及设置在所述子像素驱动电路背向所述基底的一侧的多个发光元件， 所述发光元件与所述子像素驱动电路一一对应，所述子像素驱动电路用于驱动对应的发光元件发光，从而实现显示面板的显示功能。
相关技术中，所述子像素驱动电路一般包括多个薄膜晶体管，如图1所示，图1中示出了所述子像素驱动电路包括7个薄膜晶体管M1～M7时，该7个薄膜晶体管的具体布局方式，按照这种方式布局时，所述子像素驱动电路包括如图2所示的有源层，如图3所示的第一金属层，如图4所示的第二金属层，以及如图5所示的第三金属层；所述有源层包括用于形成各薄膜晶体管的沟道区的有源图形(如图2中的虚线框内的部分)，以及与所述有源图形耦接，具有导电性能的掺杂有源图形(如图2中的虚线框外的部分)；所述第一金属层包括各薄膜晶体管的栅极，所述栅极耦接的扫描信号线GATE，所述子像素驱动电路中存储电容的一个极板CE1，复位信号线RST，以及发光控制信号线EM；所述第二金属层包括初始化信号线VINT，以及所述子像素驱动电路中存储电容的另一个电极板CE2；所述第三金属层包括数据线DATA，电源信号线VDD，以及一些导电连接部(如标记341～343)。
值得注意，如图1所示，在布局子像素驱动电路时，为了实现异层设置的功能图形之间的耦接，还可设置一些过孔(如标记：381～388)
如图6、图8和图14所示，本公开提供一种显示面板，该显示面板包括多个子像素驱动电路，还包括电源信号线图形901、数据线图形908、栅线图形902、发光控制信号线图形903、复位信号线图形905和初始化信号线图形904；所述电源信号线图形901的至少部分和所述数据线图形908沿第二方向延伸；所述栅线图形902、所述发光控制信号线图形903、所述复位信号线图形905、所述初始化信号线图形904均沿第一方向延伸，所述第一方向与所述第二方向相交。示例性的，所述第一方向包括X方向，所述第二方向包括Y方向。
如图9所示，所述多个子像素驱动电路能够划分为沿所述第二方向依次排列的多行子像素驱动电路，以及沿所述第一方向依次排列的多列子像素驱动电路，位于同一行的子像素驱动电路对应的所述初始化信号线图形904依次电连接，形成为一体结构；位于同一行的子像素驱动电路对应的所述栅线图形902依次电连接，形成为一体结构；位于同一行的子像素驱动电路对应 的所述发光控制信号线图形903依次电连接，形成为一体结构；位于同一行的子像素驱动电路对应的所述复位信号线图形905依次电连接，形成为一体结构；位于同一列的子像素驱动电路对应的所述数据线图形908依次电连接，形成为一体结构；位于同一列的子像素驱动电路对应的所述电源信号线图形901依次电连接，形成为一体结构。
示例性的，每行子像素驱动电路均包括沿X方向依次排列的多个子像素驱动电路，所述初始化信号线图形904、栅线图形902、发光控制信号线图形903和复位信号线图形905均沿所述X方向延伸，每行子像素驱动电路中包括的多个子像素驱动电路均能够分别与对应的初始化信号线图形904，栅线图形902，发光控制信号线图形903和复位信号线图形905耦接；每列子像素驱动电路均包括沿Y方向依次排列的多个子像素驱动电路，数据线图形908和电源信号线图形901均沿所述Y方向延伸，每列子像素驱动电路中包括的多个子像素驱动电路均能够分别与对应的数据线图形908和电源信号线图形901耦接。
值得注意，在所述显示面板中，关于子像素区的物理划分形式多种多样，下面示例性的给出两种具体的划分方式。
第一种划分方式，如图8所示，可以将第一晶体管T1、位于图8顶部的第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和位于图8顶部的第七晶体管T7，以及栅线图形902、发光控制信号线图形903、位于图8顶部的复位信号线图形905'和位于图8顶部的初始化信号线图形904'划分在一个子像素区(即当前子像素区)。对于图8中底部的第二晶体管T2，图8中底部的第七晶体管T7，位于图8底部的复位信号线图形905，以及位于图8底部的初始化信号线图形904，均划分至与当前子像素区沿Y方向相邻的下一个子像素区中。
第二种划分方式，如图8所示，也可以将第一晶体管T1、位于图8底部的第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和位于图8底部的第七晶体管T7，以及栅线图形902、发光控制信号线图形903、位于图8底部的复位信号线图形905和位于图8底部的初始化信号线图形904，划分在一个子像素区(即当前子像素区)。对于图8中顶 部的第二晶体管T2，图8中顶部的第七晶体管T7，位于图8顶部的复位信号线图形905'，以及位于图8顶部的初始化信号线图形904'，均划分至与当前子像素区沿Y方向相邻的上一个子像素区中。
需要说明，本公开中描述的子像素区的划分方式，为采用上述第二种划分方式。对于上述第二种划分方式，当前子像素区对应的子像素驱动电路中(即对应图6结构的子像素驱动电路中)，包括：第一晶体管T1、位于图8顶部的第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和位于图8底部的第七晶体管T7；该位于图8顶部的第二晶体管T2的栅极202g与沿所述第二方向相邻的上一个子像素区中的所述复位信号线图形905'耦接，第二晶体管T2的源极S2与所述上一个子像素区中的初始化信号线图形904'耦接，第二晶体管T2的漏极D2与第三晶体管T3的栅极203g耦接。
如图6和图8所示，以一个子像素驱动电路为例，该子像素驱动电路包括7个薄膜晶体管和1个电容。该子像素驱动电路包括的各晶体管均采用P型晶体管，其中，第一晶体管T1为双栅结构，第一晶体管T1的栅极201g与栅线图形902耦接，第一晶体管T1的源极S1与第三晶体管T3(即驱动晶体管)的漏极D3耦接，第一晶体管T1的漏极D1与第三晶体管T3的栅极203g耦接。
第二晶体管T2为双栅结构，第二晶体管T2的栅极202g与沿所述第二方向相邻的上一个子像素区中的所述复位信号线图形905'耦接，第二晶体管T2的源极S2与所述上一个子像素区中的初始化信号线图形904'耦接，第二晶体管T2的漏极D2与第三晶体管T3的栅极203g耦接。
第四晶体管T4的栅极204g与所述栅线图形902耦接，第四晶体管T4的源极S4与数据线图形908耦接，第四晶体管T4的漏极D4与第三晶体管T3的源极S3耦接。
第五晶体管T5的栅极205g与发光控制信号线图形903耦接，第五晶体管T5的源极S5与电源信号线图形901耦接，第五晶体管T5的漏极D5与第三晶体管T3的源极S3耦接。
第六晶体管T6的栅极206g与发光控制信号线图形903耦接，第六晶体 管T6的源极S6与第三晶体管T3的漏极D3耦接，第六晶体管T6的漏极D6与发光元件EL的阳极耦接。
第七晶体管T7的栅极207g与所述复位信号线图形905耦接，第七晶体管T7的漏极D7与对应的发光元件EL的阳极耦接，第七晶体管T7的源极S7与所述初始化信号线图形904耦接。
存储电容Cst的第一极板Cst1复用为第三晶体管T3的栅极203g，存储电容Cst的第二极板Cst2与所述电源信号线图形901耦接。
如图7所示，上述结构的显示子像素驱动电路在工作时，每个工作周期均包括复位时段P1、写入补偿时段P2和发光时段P3。图7中，E1代表当前子像素区中的发光控制信号线图形903上传输的发光控制信号，R1代表当前子像素区中的复位信号线图形905上传输的复位信号，D1代表当前子像素区中的数据线图形908上传输的数据信号，G1代表当前子像素区中的栅线图形902上传输的栅极扫描信号，R1'代表当前子像素区沿所述第二方向相邻的上一个子像素中的复位信号线图形905'上传输的复位信号。
在所述第一复位时段P1，所述复位信号线图形905’输入的复位信号处于有效电平，第二晶体管T2导通，将由所述初始化信号线图形904’传输的初始化信号输入至第三晶体管T3的栅极203g，使得前一帧保持在第三晶体管T3上的栅源电压Vgs被清零，实现对第三晶体管T3的栅极203g复位。
在写入补偿时段P2，所述复位信号线图形905’输入的复位信号处于非有效电平，第二晶体管T2截止，栅线图形902输入的栅极扫描信号处于有效电平，控制第一晶体管T1和第四晶体管T4导通，数据线图形908写入数据信号，并经所述第四晶体管T4传输至第三晶体管T3的源极S3，同时，第一晶体管T1和第四晶体管T4导通，使得第三晶体管T3形成为二极管结构，因此通过第一晶体管T1、第三晶体管T3和第四晶体管T4配合工作，实现对第三晶体管T3的阈值电压补偿，当补偿的时间足够长时，可控制第三晶体管T3的栅极203g电位最终达到Vdata+Vth，其中，Vdata代表数据信号电压值，Vth代表第三晶体管T3的阈值电压。
在写入补偿时段P2，所述复位信号线图形905输入的复位信号处于有效电平，控制第七晶体管T7导通，由所述初始化信号线图形904传输的初始化 信号输入至发光元件EL的阳极，控制发光元件EL不发光。
在发光时段P3，发光控制信号线图形903写入的发光控制信号处于有效电平，控制第五晶体管T5和第六晶体管T6导通，使得由电源信号线图形901传输的电源信号输入至第三晶体管T3的源极S3，同时由于第三晶体管T3的栅极203g保持在Vdata+Vth，使得第三晶体管T3导通，第三晶体管T3对应的栅源电压为Vdata+Vth-VDD，其中VDD为电源信号对应的电压值，基于该栅源电压产生的漏电流流向对应的发光元件EL的阳极，驱动对应的发光元件EL发光。
如图10～13所示，在制作上述显示子像素驱动电路时，显示子像素驱动电路对应的各膜层的布局如下：
沿远离基底的方向上依次层叠设置的有源膜层、栅极绝缘层、第一栅金属层、第一层间绝缘层、第二栅金属层、第二层间绝缘层、第一源漏金属层和第三层间绝缘层。
如图10所示，有源膜层用于形成显示子像素驱动电路中各晶体管的沟道区(如：101pg～107pg)，源极形成区(如：101ps～107ps)和漏极形成区(如：101pd～107pd)，源极形成区和漏极形成区对应的有源膜层由于掺杂作用，导电性能会优于沟道区对应的有源膜层；有源膜层可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
另外，值得注意，所述源极形成区和漏极形成区对应的有源膜层可直接作为对应的源极或漏极，或者，也可以采用金属材料制作与所述源极形成区接触的源极，采用金属材料制作与所述漏极形成区接触的漏极。
如图11所示，第一栅金属层用于形成显示子像素驱动电路中各晶体管的栅极(如：201g～207g)，以及显示基板包括的栅线图形902、发光控制信号线图形903、复位信号线图形905等结构，每个显示子像素驱动电路中的第三晶体管T3的栅极203g均复用为该显示子像素驱动电路中的第二存储电容Cst的第一极板Cst1。
如图12所示，第二栅金属层用于形成第二存储电容Cst的第二极板Cst2，以及显示基板包括的初始化信号线图形904。
如图6、图8和13所示，第一源漏金属层用于形成显示子像素驱动电路中各晶体管的源极(如：S1～S7)和漏极(如：D1～D7)，以及显示基板包括的数据线图形908、电源信号线图形901和一些导电连接部。
更详细地说，请继续参阅图10～13，第一晶体管T1的栅极201g覆盖第一沟道区101pg，第一晶体管T1的源极S1位于第一源极形成区101ps，第一晶体管T1的漏极D1位于第一漏极形成区101pd。
第二晶体管T2的栅极202g覆盖第二沟道区102pg，第二晶体管T2的源极S2位于第二源极形成区102ps，第二晶体管T2的漏极D2位于第二漏极形成区102pd。
第三晶体管T3的栅极203g覆盖第三沟道区103pg，第三晶体管T3的源极S3位于第三源极形成区103ps，第三晶体管T3的漏极D3位于第三漏极形成区103pd。
第四晶体管T4的栅极204g覆盖第四沟道区104pg，第四晶体管T4的源极S4位于第四源极形成区104ps，第四晶体管T4的漏极D4位于第四漏极形成区104pd。
第五晶体管T5的栅极205g覆盖第五沟道区105pg，第五晶体管T5的源极S5位于第五源极形成区105ps，第五晶体管T5的漏极D5位于第五漏极形成区105pd。
第六晶体管T6的栅极206g覆盖第六沟道区106pg，第六晶体管T6的源极S6位于第六源极形成区106ps，第六晶体管T6的漏极D6位于第六漏极形成区106pd。
第七晶体管T7的栅极207g覆盖第七沟道区107pg，第七晶体管T7的源极S7位于第七源极形成区107ps，第七晶体管T7的漏极D7位于第七漏极形成区107pd。
第三晶体管T3的栅极203g复用为存储电容Cst的第一极板Cst1，存储电容Cst的第二极板Cst2与电源信号线图形901耦接。
另外，如图8所示，本公开提供的显示面板中，在第二方向(如Y方向)上，第四晶体管T4的栅极204g、第一晶体管T1的栅极201g和第二晶体管T2的栅极202g均位于驱动晶体管的栅极(即第三晶体管T3的栅极203g) 的第一侧，第七晶体管T7的栅极、第六晶体管T6的栅极206g、第五晶体管T5的栅极均位于驱动晶体管的栅极的第二侧。示例性的，所述驱动晶体管的栅极的第一侧和第二侧为沿第二方向相对的两侧，进一步地，驱动晶体管的栅极的第一侧可以为驱动晶体管的栅极的上侧，驱动晶体管的栅极的第二侧可以为驱动晶体管的栅极的下侧。所述下侧，例如显示基板的用于绑定IC的一侧为显示基板的下侧，驱动晶体管的栅极的下侧，为驱动晶体管的栅极的更靠近IC的一侧。所述上侧为下侧的相对侧，例如为驱动晶体管的栅极的更远离IC的一侧。
在第一方向(如X方向)上，第四晶体管T4的栅极204g和第五晶体管T5的栅极205g均位于驱动晶体管的栅极的第三侧，第一晶体管T1的栅极201g和第六晶体管T6的栅极206g均位于驱动晶体管的栅极的第四侧。示例性的，驱动晶体管的栅极的第三侧和第四侧为沿第一方向相对的两侧；进一步地，驱动晶体管的栅极的第三侧可以为驱动晶体管的栅极的右侧，驱动晶体管的栅极的第四侧可以为驱动晶体管的栅极的左侧。所述左侧和右侧，例如在同一子像素区中，数据线图形908位于电源信号线图形901右侧，电源信号线图形901位于数据线图形908右侧。
上述显示面板虽然能够提升分辨率，但是提升效果有限。而且从图8中能够看出，第二晶体管T2和第七晶体管T7在通过导电部909与初始化信号线图形904(904’)通过过孔耦接时，对于高分辨率的显示面板，由于布局空间较小，能够打孔的空间较小，在进行打孔工艺时，容易在工艺波动时将过孔打偏到附近的复位信号线图形905上，导致信号扰乱。
因此，对于高分辨的显示面板，上述显示面板中的像素结构还需要进一步优化，以解决上述问题。
请参阅图15和图16，本公开实施例提供了一种显示面板，包括：基底、设置在所述基底上的功能膜层；还包括阵列排布的多个子像素区；
所述功能膜层包括：复位信号线层、初始化信号线层、导电连接部层；
所述复位信号线层包括：设置于各所述子像素区中的复位信号线图形905，所述复位信号线图形905沿第一方向延伸；
所述初始化信号线层包括：设置于各所述子像素区中的初始化信号线图 形904，所述初始化信号线图形904包括相耦接的第一主体部分9041和第一突出部分9042，所述第一主体部分9041沿所述第一方向延伸，在同一子像素区中，所述第一主体部分9041在所述基底上的正投影位于所述第一突出部分9042在所述基底上的正投影与所述复位信号线图形905在所述基底上的正投影之间；
所述导电连接部层包括：设置于各所述子像素区中的导电连接部图形909，在同一子像素区中，所述导电连接部图形909的第一端部9091在所述基底上的正投影，与所述第一突出部分9042在所述基底上的正投影具有第一交叠区域F1，在所述第一交叠区域F1，该第一端部9091与该第一突出部分9042耦接，所述导电连接部图形909的第二端部9092与其所在子像素区中的目标耦接部耦接，所述复位信号线图形905在所述基底上的正投影，位于所述目标耦接部在所述基底上的正投影与所述初始化信号线图形904在所述基底上的正投影之间。
具体地，阵列排布的多个子像素区能够划分为沿第二方向依次排列的多行子像素区，和沿第一方向依次排列的多列子像素区。每行子像素区均包括沿第一方向间隔设置的多个子像素区，每列子像素区均包括沿所述第二方向间隔设置的多个子像素区。所述第一方向与所述第二方向相交，示例性的，所述第一方向包括X方向，所述第二方向包括Y方向。
所述复位信号线层包括设置于各所述子像素区中的复位信号线图形905，所述复位信号线图形905沿所述第一方向延伸。所述复位信号线图形905与所述子像素区一一对应，所述复位信号线图形905位于对应的所述子像素区中，位于同一行的子像素区对应的各所述复位信号线图形905依次电连接，形成为一体结构。
所述初始化信号线层包括：设置于各所述子像素区中的初始化信号线图形904，所述初始化信号线图形904与所述子像素区一一对应，所述初始化信号线图形904位于对应的所述子像素区中，位于同一行的子像素区对应的各所述初始化信号线图形904依次电连接，形成为一体结构。
如图16所示，每个所述初始化信号线图形904均包括相耦接的第一主体部分9041和第一突出部分9042，所述第一主体部分9041沿所述第一方向延 伸，位于同一行的子像素区对应的各所述初始化信号线图形904中的所述第一主体部分9041依次电连接，形成为一体结构。值得注意，考虑到制作工艺的误差，所述第一主体部不一定是沿所述第一方向延伸的直线型。
所述第一突出部分9042的具体形状多种多样，能够满足在所述第二方向上，所述第一突出部分9042突出于其耦接的所述第一主体部分9041即可。通过设置在同一子像素区中，所述第一主体部分9041在所述基底上的正投影位于所述第一突出部分9042在所述基底上的正投影与所述复位信号线图形905在所述基底上的正投影之间，使得所述第一突出部分9042能够背向所述复位信号线图形905设置，从而使得所述第一突出部分9042能够与所述复位信号线图形905之间具有较远的距离。
需要说明，在一个初始化信号线图形904中，所述第一主体部分9041和所述第一突出部分9042可以形成为一体结构，但不仅限于此。
所述导电连接部层包括：设置于各所述子像素区中的导电连接部图形909，所述导电连接部图形909与所述子像素区一一对应，所述导电连接部图形909位于对应的所述子像素区中。
所述导电连接部图形909的第一端部9091在所述基底上的正投影，与所述第一突出部分9042在所述基底上的正投影具有第一交叠区域F1，该第一端部9091与该第一突出部分9042能够通过在所述第一交叠区域F1打孔(如第一连接孔70)耦接。所述导电连接部图形909的第二端部9092与其所在子像素区中的目标耦接部耦接，所述目标耦接部可以包括当前子像素区对应的第七晶体管的第一极，以及沿所述第二方向与当前子像素区相邻的下一个子像素区对应的第二晶体管的第一极。
所述目标耦接部的设置位置多种多样，示例性的，可设置同一子像素区中，所述复位信号线图形905在所述基底上的正投影，位于所述目标耦接部在所述基底上的正投影与所述初始化信号线图形904在所述基底上的正投影之间。
需要说明，所述显示面板还包括层间介质层(即前面提到的第二层间绝缘层ILD)，所述层间介质层位于所述显示面板中的第二栅金属层和第一源漏金属层之间，所述初始化信号线图形904可以与所述第二栅金属层同层设置， 并能够在同一次构图工艺中形成，所述导电连接部图形909可以与所述第一源漏金属层同层设置，并能够在同一次构图工艺中形成。上述在该第一交叠区域F1打孔以实现所述导电连接部图形909的第一端部9091与所述第一突出部分9042耦接，所制作的过孔为贯穿ILD层的过孔，该过孔的位置与所述复位信号线图形905之间的距离更远。
根据上述显示面板的具体结构可知，本公开实施例提供的显示面板中，设置了所述初始化信号线图形904背向所述复位信号线图形905的一侧包括第一突出部分9042，并设置了所述导电连接部图形909的第一端部9091在所述基底上的正投影，与所述第一突出部分9042在所述基底上的正投影具有第一交叠区域F1，所述第一端部9091与所述第一突出部分9042能够通过在所述第一交叠区域F1打孔耦接；这种设置方式使得用于耦接所述导电连接部和所述初始化信号线图形904的过孔与所述复位信号线图形905之间具有较远的距离，从而避免了在进行打孔工艺时，容易在工艺波动时将过孔打偏到附近的复位信号线图形905上，导致信号扰乱的问题，进而更好的保证了所述显示面板的良率。
另外，由于设置了所述初始化信号线图形904背向所述复位信号线图形905的一侧包括第一突出部分9042，用于耦接所述导电连接部和所述初始化信号线图形904的过孔形成在所述第一突出部分9042，使得该过孔在所述基底上的正投影能够被所述初始化信号线图形904在所述基底上的正投影包裹，从而很好的提升了所述初始化信号线图形904与所述导电连接部图形909耦接的信赖性，更好的保证了显示面板工作时的稳定性。
如图15和图16所示，在一些实施例中，所述显示面板还包括：
与所述多个子像素区一一对应的多个发光元件，所述多个发光元件位于所述功能膜层背向所述基底的一侧；
与所述多个子像素区一一对应的多个子像素驱动电路，每个所述子像素驱动电路均包括第七晶体管T7，所述第七晶体管T7的栅极207g与对应的所述复位信号线图形905耦接，所述第七晶体管T7的第一极作为所述目标耦接部，所述第七晶体管T7的第二极(形成在107pd区)沿所述第二方向延伸，且与对应的发光元件的阳极耦接；
所述导电连接部图形909还包括连接在所述第一端部9091和所述第二端部9092之间的第二主体部分9093，所述第二主体部分9093沿第二方向延伸；在同一个子像素区中，沿所述第一方向，所述导电连接部图形909的第一端部9091，向远离所述第七晶体管的第二极的方向突出于所述第二主体部分9093。
具体地，所述显示面板还包括位于所述功能膜层背向所述基底的一侧的多个发光元件，所述多个发光元件与所述多个子像素区一一对应。每个所述发光元件均包括：沿远离所述基底的方向上，依次层叠设置的阳极、发光图形和阴极；显示面板工作时，向所述阳极提供驱动信号，向所述阴极提供公共信号，使得在所述阳极和所述阴极之间产生电场，从而控制所述发光图形发出对应颜色的光；示例性的，所述发光元件包括能够发出红光红色发光元件，能够发出绿光的绿色发光元件和能够发出蓝光的蓝色发光元件等。
所述显示面板还包括与所述多个子像素区一一对应的多个子像素驱动电路，每个所述子像素驱动电路均用于为其对应的发光元件的阳极提供驱动信号。示例性的，每个所述子像素驱动电路均包括第七晶体管，所述第七晶体管的栅极与对应的所述复位信号线图形905耦接，所述第七晶体管的第一极作为所述目标耦接部，能够通过对应的导电连接部图形909与对应的所述初始化信号线图形904耦接，所述第七晶体管T7的第二极沿所述第二方向延伸，且与对应的发光元件的阳极耦接。
如图6所示，所述第七晶体管主要用于在像素充电之前对N2节点进行复位，详细复位过程为：所述第七晶体管通过所述导电连接部图形909耦接的所述初始化信号线图形904提供初始化信号，所述第七晶体管将所述初始化信号传输至N2节点，实现对所述N2节点的复位。值得注意，所述导电连接部图形909作为中间层实现跳线，所述导电连接部图形909与所述第七晶体管的耦接，以及与所述初始化信号线图形904的耦接均可与通过打孔实现。
所述导电连接部图形909的具体结构多种多样，示例性的，如图16所示，所述导电连接部图形909还包括连接在所述第一端部9091和所述第二端部9092之间的第二主体部分9093，所述第二主体部分9093能够沿所述第二方向延伸，在同一个子像素区中，沿所述第一方向，所述导电连接部图形909 的第一端部9091，向远离所述第七晶体管的第二极的方向突出于所述第二主体部分9093。这种结构的所述导电连接部图形909，使得其包括的第一端部9091与所述第七晶体管的第二极之间具有较远的距离，这样在ILD上形成用于耦接所述导电连接部图形909的第一端部9091和所述初始化信号线图形904的过孔时，过孔的形成位置与所述第七晶体管的第二极更远，从而更有利于避免在所述过孔的制作过程中，容易在工艺波动时将过孔打偏到所述第七晶体管的第二极上，导致信号扰乱的问题，进而更好的保证了所述显示面板的良率。
更详细地说，如图15所示，所述第七晶体管的第二极采用ploy层(即有源层)制作，将所述导电连接部图形909形成为上述结构，能够更好的避免在所述过孔的制作过程中，容易在工艺波动时将过孔打偏到所述第七晶体管的第二极对应的ploy层上，导致信号扰乱的问题，进而更好的保证了所述显示面板的良率。
如图15所示，在一些实施例中，所述功能膜层还包括位于各子像素区中的数据线图形908，所述数据线图形908包括沿所述第二方向延伸的部分；
所述初始化信号线图形904在所述基底上的正投影与所述导电连接部图形909在所述基底上的正投影存在第三交叠区域F3；
所述初始化信号线图形904在所述基底上的正投影与所述数据线图形908在所述基底上的正投影存在第四交叠区域F4；
在所述第四交叠区域F4所述初始化信号线图形904沿所述第二方向的宽度L5，小于在所述第三交叠区域F3所述初始化信号线图形904沿所述第二方向的宽度L6。
具体地，所述数据线图形908与所述子像素区一一对应，所述数据线图形908位于对应的所述子像素区中，所述数据线图形908包括沿所述第二方向延伸的部分，位于同一列的子像素区对应的各所述数据线图形908依次电连接，形成为一体结构。
由于所述数据线图形908沿所述第二方向延伸，所述初始化信号线图形904的第一主体部分9041沿所述第一方向延伸，且所述第一方向与所述第二方向相交，因此，在垂直于所述基底的方向，所述初始化信号线图形904一 定存在至少部分与所述数据线图形908交叠。
上述设置所述初始化信号线图形904在所述基底上的正投影与所述导电连接部图形909在所述基底上的正投影存在第三交叠区域F3；所述初始化信号线图形904在所述基底上的正投影与所述数据线图形908在所述基底上的正投影存在第四交叠区域F4；以及在所述第四交叠区域F4所述初始化信号线图形904沿所述第二方向的宽度，小于在所述第三交叠区域F3所述初始化信号线图形904沿所述第二方向的宽度；使得所述初始化信号线图形904能够在一些区域中(具体如：所述第三交叠区域F3)，沿所述第二方向的宽度有缩窄，这样不仅有利于减小所述初始化信号线图形904与所述数据线图形908之间的交叠面积，减小寄生电容的容值；而且能够有效减小所述初始化信号线图形904的布局空间，从而更有利于节省像素空间，有利于所述显示面板的高分辨率发展。
如图15～图17所示，在一些实施例中，在同一个子像素区中，所述第二主体部分9093在所述基底上的正投影，与所述第七晶体管T7的第二极在所述基底上的正投影之间具有第一间隙L1，所述第一间隙大于阈值。
具体地，上述设置所述第二主体部分9093在所述基底上的正投影，与所述第七晶体管T7的第二极在所述基底上的正投影之间具有第一间隙L1，避免了在垂直于所述基底的方向上，所述第二主体部分9093与所述第七晶体管T7的第二极之间有交叠。
另外，通过设置所述第一间隙L1大于阈值，使得所述第二主体部分9093在所述基底上的正投影，与所述第七晶体管的第二极在所述基底上的正投影之间具有较大的距离，很好的避免了制作所述第二主体部分9093的工艺过程中，对所述第七晶体管的第二极产生损伤。需要说明，所述阈值可以根据实际需要设置，示例性的，所述阈值在8μm～35μm之间，可以包括端点值。
如图15和图16所示，在一些实施例中，所述显示面板还包括：
与所述多个子像素区一一对应的多个子像素驱动电路，每个所述子像素驱动电路均包括驱动晶体管和第二晶体管T2；
所述第二晶体管T2的栅极202g与沿所述第二方向相邻的上一个子像素区中的所述复位信号线图形905'耦接，所述第二晶体管T2的第一极作为所述 上一个子像素区中的所述目标耦接部，所述第二晶体管T2的第二极与所述驱动晶体管(即第三晶体管T3)的栅极耦接；
所述第二晶体管T2包括沿所述第一方向间隔设置的两个半导体部分(如图19所示，位于标记102pg区域)，以及分别连接所述两个半导体部分的第一导体部分80，所述第一导体部分80在所述基底上的正投影，与所述上一个子像素区中的所述第一突出部分9042在所述基底上的正投影不交叠。
具体地，每个所述子像素驱动电路均包括驱动晶体管和第二晶体管，所述驱动晶体管用于产生驱动所述发光元件发光的驱动信号。所述第二晶体管栅极与沿所述第二方向相邻的上一个子像素区中的所述复位信号线图形905耦接，所述第二晶体管的第一极作为所述上一个子像素区中的所述目标耦接部，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接，所述第二晶体管用于在像素充电之前，将其耦接的初始化信号线图形904提供的初始化信号传输至N1节点(与所述驱动晶体管的栅极耦接)，实现对所述N1节点的复位。
示例性的，所述第二晶体管可选为双栅结构，所述第二晶体管具体包括沿所述第一方向间隔设置的两个半导体部分，以及分别连接所述两个半导体部分的第一导体部分80，所述两个半导体部分分别对应所述第二晶体管的沟道区。所述两个半导体部分和所述第一导体部分80可以形成为一体结构，制作时，可以先形成所述两个半导体部分和与所述第一导体部分80对应的第三半导体部分，然后对该第三半导体部分进行掺杂，将所述第三半导体部分形成为所述第一导体部分80。
上述设置所述第一导体部分80在所述基底上的正投影，与所述上一个子像素区中的所述第一突出部分9042在所述基底上的正投影不交叠，使得在形成用于耦接所述初始化信号线图形904和所述导电连接部图形909的过孔时，能够更好的避免在工艺波动时将过孔打偏到所述第一导体部分80上，导致信号扰乱的问题，进而更好的保证了所述显示面板的良率。
如图15和图16所示，在一些实施例中，所述第一导体部分80在所述基底上的正投影，与所述上一个子像素区中的所述导电连接部图形909的第一端部9091在所述基底上的正投影交叠。
具体地，上述设置所述第一导体部分80在所述基底上的正投影，与所述上一个子像素区中的所述导电连接部图形909的第一端部9091在所述基底上的正投影交叠，不仅使得所述导电连接部图形909的第一端部9091能够有更大的面积，来包覆其与所述初始化信号线图形904之间的连接过孔；而且，还使得所述导电连接部图形909的第一端部9091和所述第一导体部分80的布局位置更加紧凑，从而更有利于节省像素空间，有利于实现显示面板的高分辨率发展。
如图15和图16所示，在一些实施例中，每个所述初始化信号线图形904还包括与所述第一主体部分9041耦接的第二突出部分9043，在同一子像素区中，所述第二突出部分9043在所述基底上的正投影位于所述第一主体部分9041在所述基底上的正投影与所述复位信号线图形905在所述基底上的正投影之间，所述第一导体部分80在所述基底上的正投影与所述第二突出部分9043和/或第一主体部分9041在所述基底上的正投影交叠。
具体地，每个所述初始化信号线图形904还可以包括第二突出部分9043，该第二突出部分9043可具体位于所述第一主体部分9041与所述复位信号线图形905之间。示例性的，所述第二突出部分9043、所述第一突出部分9042和所述第一主体部分9041可以形成为一体结构。
上述设置所述第一导体部分80在所述基底上的正投影与所述第二突出部分9043/或第一主体部分9041在所述基底上的正投影交叠，使得所述初始化信号线图形904能够对所述第一导体部分80进行遮挡，由于所述初始化信号线图形904上传输的初始化信号都是稳定的信号，这种遮挡能够使得在外界数据信号变化时，保证所述第一导体部分80上的信号稳定，避免了由于第一导体部分80浮接，外界数据信号变化时，因为电容耦合作用，导致的所述第一导体部分80信号不稳定问题。
如图15～图17所示，在一些实施例中，所述导电连接部图形909还包括连接在所述第一端部9091和所述第二端部9092之间的第二主体部分9093，该第二主体部分9093沿第二方向延伸；
所述第一导体部分80中靠近所述上一个子像素区中的所述导电连接部图形909的一端801沿所述第二方向延伸，该一端801在所述基底上的正投 影，与该导电连接部图形909的第二主体部分9093在所述基底上的正投影之间具有第二间隙L2，所述第二间隙L2大于阈值。
具体地，所述第一导体部分80的形状多种多样，示例性的，所述第一导体部分80呈“门字形”结构，即所述第一导体部分80中靠近所述上一个子像素区中的所述导电连接部图形909的一端801沿所述第二方向延伸，所述第一导体部分80中靠近所述电源信号线图形901的一端802沿所述第二方向延伸，所述第一导体部分80位于这两端之间的部分沿所述第一方向延伸。
上述设置所述第一导体部分80中靠近所述上一个子像素区中的所述导电连接部图形909的一端801在所述基底上的正投影，与该导电连接部图形909的第二主体部分9093在所述基底上的正投影之间具有第二间隙L2，避免了在垂直于所述基底的方向上，所述第二主体部分9093与所述第一导体部分80之间有交叠。
另外，通过设置所述第二间隙L2大于阈值，使得所述第二主体部分9093在所述基底上的正投影，与所述第一导体部分80在所述基底上的正投影之间具有较大的距离，很好的避免了制作所述第二主体部分9093的工艺过程中，对所述第一导体部分80产生损伤。需要说明，所述阈值可以根据实际需要设置，示例性的，所述阈值在8μm～35μm之间，可以包括端点值。
如图15和图16所示，在一些实施例中，在同一子像素区中，所述导电连接部图形909的第一端部9091在所述基底上的正投影，还与所述初始化信号线图形904的第一主体部分9041在所述基底上的正投影形成第二交叠区域F2；
所述功能膜层还包括位于各所述子像素区中的第一连接孔70，在同一子像素区中，所述第一连接孔70在所述基底上的正投影，分别与所述第一交叠区域F1和所述第二交叠区域F2交叠，所述导电连接部图形909的第一端部9091通过所述第一连接孔70与所述初始化信号线图形904耦接。
具体地，所述导电连接部图形909的第一端部9091在所述基底上的正投影能够与所述初始化信号线图形904的第一突出部分9042在所述基底上的正投影具有第一交叠区域F1，还能够与所述初始化信号线图形904第一主体部分9041在所述基底上的正投影具有第二交叠区域F2。
所述导电连接部的第一端部9091通过所述第一连接孔70与所述初始化信号线图形904耦接时，可设置所述第一连接孔70在所述基底上的正投影，分别与所述第一交叠区域F1和所述第二交叠区域F2交叠，这样所述第一连接孔70的可布局空间较大，能够保证所述导电连接部图形909与所述初始化图形良好的连接性能。
如图18所示，在一些实施例中，所述第二晶体管T2的所述第一导体部分80在所述基底40上的正投影，与所述上一个子像素区中的所述第一连接孔70在所述基底40上的正投影不交叠。
具体地，上述设置所述第二晶体管的所述第一导体部分80在所述基底40上的正投影，与所述上一个子像素区中的所述第一连接孔70在所述基底40上的正投影不交叠，能够更好的避免在所述第一连接孔的制作过程中，容易在工艺波动时将过孔打偏到所述第一导体部分80上，导致信号扰乱的问题，进而更好的保证了所述显示面板的良率。
如图15和图16所示，在一些实施例中，所述功能膜层还包括电源信号线层，所述电源信号线层包括设置于各所述子像素区中的电源信号线图形901，所述电源信号线图形901的至少部分沿第二方向延伸；
所述第一导体部分80中远离所述上一个子像素区中的所述导电连接部图形909的一端802沿所述第二方向延伸，该一端802在所述基底上的正投影，被位于同一子像素区中的所述电源信号线图形901在所述基底上的正投影完全覆盖。
具体地，所述电源信号线图形901与所述子像素区一一对应，所述电源信号线图形901位于对应的所述子像素区中。每一列子像素区中设置的各所述电源信号线图形901沿所述第二方向依次耦接，且能够形成为一体结构。
上述设置所述第一导体部分80中远离所述上一个子像素区中的所述导电连接部图形909的一端802沿所述第二方向延伸，该一端802在所述基底上的正投影，被位于同一子像素区中的所述电源信号线图形901在所述基底上的正投影完全覆盖；使得所述电源信号线图形901，能够对所述第一导体部分80中远离所述上一个子像素区中的所述导电连接部图形909的一端进行遮挡，由于所述电源信号线图形901上传输的电源信号都是稳定的信号，这 种遮挡能够使得在外界数据信号变化时，保证所述第一导体部分80上的信号稳定，避免了由于第一导体部分80浮接，外界数据信号变化时，因为电容耦合作用，导致的所述第一导体部分80信号不稳定问题。
另外，上述设置方式有效缩小了所述第一导电部和所述电源信号线图形901占用的布局空间，很好的缩小了像素结构，更有利于所述显示面板的高分辨率发展。
所述电源信号线图形901的结构多种多样，如图22所示。在一些实施例中，可设置所述电源信号线图形901沿所述第二方向延伸，所述电源信号线图形901沿垂直于所述第二方向上的宽度基本均匀。
如图23和图24所示，在另外一些实施例中，所述显示面板还包括：
与所述多个子像素区一一对应的多个子像素驱动电路，每个所述子像素驱动电路均包括驱动晶体管和存储电容，所述存储电容包括相对设置的第一极板和第二极板，所述第一极板复用为所述驱动晶体管的栅极，所述第二极板位于所述第一基板背向所述基底的一侧；
所述功能膜层还包括电源信号线层，所述电源信号线层包括设置于各所述子像素区中的电源信号线图形901，所述电源信号线图形901的至少部分沿第二方向延伸，所述电源信号线图形901包括第一电源部9011和第二电源部9012；
所述第一电源部9011在所述基底上的正投影与位于同一子像素区中的各所述复位信号线图形905在所述基底上的正投影交叠，并与位于同一子像素区中的各所述栅线图形902在所述基底上的正投影交叠；所述第二电源部9012在所述基底上的正投影与对应的所述存储电容Cts的第二极板Cts2在所述基底上的正投影交叠；沿所述第一方向所述第一电源部9011的宽度L3小于所述第二电源部9012的宽度L4。
具体地，每个所述子像素驱动电路均可以包括驱动晶体管和存储电容Cts，所述存储电容Cts的第一极板Cts1复用为其耦接的驱动晶体管的栅极，所述存储电容的第二极板Cts2位于所述第一极板Cts1背向所述基底的一侧，能够与所述第一极板形成正对面积。
所述电源信号线图形901可具体包括第一电源部9011和第二电源部9012， 示例性的，所述第一电源部9011与所述第二电源部9012沿所述第二方向交替排列，相邻的所述第一部分与所述第二部分耦接在一起。示例性的，所述第一电源部9011和第二电源部9012形成为一体结构。
所述第一电源部9011和所述第二电源部9012的具体布局位置多种多样，示例性的，设置所述第一电源部9011在所述基底上的正投影与位于同一子像素区中的各所述复位信号线图形905在所述基底上的正投影交叠，并与位于同一子像素区中的各所述栅线图形902在所述基底上的正投影交叠；所述第二电源部9012在所述基底上的正投影与对应的所述存储电容的第二极板在所述基底上的正投影交叠。上述通过设置沿所述第一方向所述第一电源部9011的宽度小于所述第二电源部9012的宽度，有效缩窄了所述第一电源部9011沿所述第一方向的宽度，使得所述第一电源部9011与所述复位信号线图形905之间的交叠面积减小，以及与所述栅线图形902之间的交叠面积减小，从而有效减小了所述电源信号线图形901与所述复位信号线之间产生的耦合电容。
需要说明，所述第一电源部9011沿所述第一方向上的宽度是指：沿所述第一方向，所述第一电源部9011相对的两个边界之间的最大距离或者最小距离；同样的，所述第二电源部9012沿所述第一方向上的宽度是指：沿所述第一方向，所述第二电源部9012相对的两个边界之间的最大距离或者最小距离。
值得注意，图25中示出了当所述电源信号线图形901采用所述第一电源部9011和所述第二电源部9012的结构时，对应八个子像素区的示意图。图25中示出的第一连接孔70，只是示意了所述第一连接孔的大致形成位置，实际制作的第一连接孔的孔径可能会比图25中示意的孔径要大，所述第一连接孔的具体形成位置可以位于所述导电连接部图形909的第一端部9091在所述基底上的正投影，与所述初始化信号线图形904在所述基底上的正投影的交叠区域。
此外，图26为图25中有源层的示意图，图27为图25中第一栅金属层的示意图；图28为图25中第二栅金属层的示意图；图29为图25中第一源漏金属层的示意图；图30为所述显示面板中包括第二源漏金属层时，第二源漏金属层对应八个子像素区的示意图。
需要说明，如图30和图31所示，所述第二源漏金属层可具体包括：电源补偿图形300和转接图形310；所述电源补偿图形300包括横向连接部3001和纵向连接部3002，所述电源补偿图形300与所述显示面板中包括的电源信号线图形耦接，以降低所述电源信号线图形上的IR Drop；所述转接图形310与显示面板中包括的阳极一一对应，所述转接图形310用于连接对应的阳极320和用于为该阳极320提供驱动信号的子像素驱动电路。
具体实施例中，参考图34，所述转接图形310与显示面板中包括的阳极之间还可以设置第二转接图形906，该第二转接图形906位于第一源漏金属层中。
需要说明的是，所述第一源漏金属层，和/或第二源漏金属层上还可以设置钝化层，如采用氮化硅，氧化硅等无机材料，本实施例不做限定。
继续参见图30～图32，所述显示面板中还包括像素界定层，所述像素界定层形成像素开口330，所述像素开口330与所述阳极320一一对应，每个像素开口330用于暴露对应的阳极320的至少部分，显示面板中包括的有机发光材料层形成在对应的各所述像素开口330中。
值得注意，所述显示面板中可包括多种颜色的子像素，不同颜色的子像素对应的发光元件发出的光具有不同的颜色，示例性的，所述显示面板的每个像素单元包括一个红色子像素R、两个绿色子像素G和一个蓝色子像素B，图31和图32中示出了一个像素单元中，各种不同颜色的子像素单元的布局方式，即GGRB像素排列方式。
当然，所述显示面板中的像素单元也可以包括一个红色子像素R、一个绿色子像素G和一个蓝色子像素B，这种结构的像素单元可具体采用strip(条状)RGB排列方式，即该一个红色子像素R、一个绿色子像素G和一个蓝色子像素B沿同一个方向(如X方向)依次排列。或者，这种结构的像素单元也可以具体采用类似品字形的RGB排列方式，如该一个红色子像素R和一个蓝色子像素B位于沿X方向的同一行，该一个绿色子像素G位于延X方向的另一行。
如图33所示，图33中示出了对应图32中的第二栅金属层和第二源漏金属层。在一些实施例中，可设置对应不同颜色的子像素，转接图形310在所 述基底上的正投影与对应的存储电容的第二极板Cst2在所述基底上的正投影的交叠面积不同。
更详细地说，参见图32和图33，对应红色子像素R，转接图形310在所述基底上的正投影与对应的存储电容的第二极板Cst2在所述基底上的正投影形成第一交叠面积J1。对应绿色子像素G，转接图形310在所述基底上的正投影与对应的存储电容的第二极板Cst2在所述基底上的正投影形成第二交叠面积J2。对应蓝色子像素B，转接图形310在所述基底上的正投影与对应的存储电容的第二极板Cst2在所述基底上的正投影形成第三交叠面积J3。所述第二交叠面积J2小于所述第一交叠面积J1，所述第一交叠面积J1小于所述第三交叠面积J3。
上述设置方式能够更好的平衡不同颜色的像素单元对应的电源信号线图形901上的RC(阻容)loading(负载)。
请参阅图34，图34为图32沿C1C2方向的截面图，图34中基底40与第六漏极形成区106pd(即该区域的有源层用于形成第六晶体管T6的漏极)之间还包括缓冲层等其他膜层，图34中未示出。图34中还示出了第一栅极绝缘层41，第二栅极绝缘层42，层间绝缘层43，第一平坦层44和第二平坦层45。
如图15和图21所示，在一些实施例中，所述功能膜层还包括电源信号线层，所述电源信号线层包括设置于各所述子像素区中的电源信号线图形901，所述电源信号线图形901的至少部分沿第二方向延伸；
所述功能膜层还包括辅助电源层，所述辅助电源层包括设置于各所述子像素区中的辅助电源图形60，所述辅助电源图形60在所述基底上的正投影与位于同一子像素区中的电源信号线图形901在所述基底上的正投影存在交叠区域，所述辅助电源图形60与该电源信号线图形901在该交叠区域耦接。
具体的，所述辅助电源图形60与所述子像素区一一对应，所述辅助电源图形60位于对应的子像素区中。示例性的，所述辅助电源图形60可以与所述存储电容的第二极板同层同材料设置，即能够在同一次构图工艺中形成。
在布局所述辅助电源图形60时，可设置所述辅助电源图形60在所述基底上的正投影与位于同一子像素区中的电源信号线图形901在所述基底上的 正投影存在交叠区域，所述辅助电源图形60与该电源信号线图形901能够通过设置在所述交叠区域的过孔实现耦接。
上述通过设置所述辅助电源图形60与所述电源信号线图形901耦接，很好的降低了所述电源信号线图形901上的RC(阻容)loading(负载)，降低了所述电源信号线图形901上的IR drop(压降)，从而更好的保证了所述显示面板工作的稳定性。
如图15和图19所示，在一些实施例中，所述显示面板还包括：与所述多个子像素区一一对应的多个子像素驱动电路，每个所述子像素驱动电路均包括驱动晶体管和第二晶体管；
所述第二晶体管的栅极与沿所述第二方向相邻的上一个子像素区中的所述复位信号线图形905耦接，所述第二晶体管的第一极作为所述上一个子像素区中的所述目标耦接部，所述第二晶体管的第二极包括相耦接的第一电极部51和第二电极部52，所述第一电极部51沿第二方向延伸，所述第二电极部52沿第三方向延伸，所述第三方向与所述第一方向和所述第二方向均相交，所述第一电极部51位于所述第二晶体管的半导体部分与所述第二电极部52之间，所述第二电极部52与所述驱动晶体管的栅极耦接；
所述第一电极部51在所述基底上的正投影和所述第二电极部52在所述基底上的正投影，均被对应的所述辅助电源图形60在所述基底上的正投影覆盖。
具体地，所述第二晶体管的第二极用于与所述驱动晶体管的栅极耦接，示例性的，该第二电极可具体包括：相耦接的第一电极部51和第二电极部52，所述第一电极部51位于所述第二晶体管的半导体部分与所述第二电极部52之间，所述第二电极部52与所述驱动晶体管的栅极耦接。
所述第一电极部51与所述第二电极部52的具体布局方式多种多样，示例性的，所述第一电极部51沿第二方向延伸，所述第二电极部52沿第三方向延伸，所述第三方向与所述第一方向和所述第二方向均相交。上述通过设置所述第一电极部51在所述基底上的正投影和所述第二电极部52在所述基底上的正投影，均被对应的所述辅助电源图形60在所述基底上的正投影覆盖，不仅很好的保证了N1节点的电位稳定性，还有效缩小了所述第二晶体管的 第二极与所述电源信号线图形901所需要占用的布局空间，从而很好的缩小了像素结构，更有利于所述显示面板的高分辨率发展。
如图15和图21所示，在一些实施例中，所述辅助电源图形60包括相耦接的第一辅助子图形601和第二辅助子图形602，所述第一辅助子图形601沿第二方向延伸，所述第二辅助子图形602的至少部分沿所述第一方向延伸；所述第一辅助子图形601在所述基底上的正投影覆盖所述第一电极部51在所述基底上的正投影和所述第二电极部52在所述基底上的正投影。
具体地，所述辅助电源图形60的具体结构多种多样，示例性的，所述辅助电源图形60包括相耦接的第一辅助子图形601和第二辅助子图形602，所述第一辅助子图形601和所述第二辅助子图形602可形成为一体结构。
示例性的，所述第一辅助子图形601沿第二方向延伸，所述第二辅助子图形602的至少部分沿所述第一方向延伸，使得所述辅助电源图形60形成为类似L形状。
由于所述辅助电源图形60与所述电源信号线图形901耦接，因此所述辅助电源图形60上具有稳定的电位，上述设置所述第一辅助子图形601在所述基底上的正投影覆盖所述第一电极部51在所述基底上的正投影和所述第二电极部52在所述基底上的正投影，不仅很好的保证了N1节点的电位稳定性，还有效缩小了所述第二晶体管的第二极、所述电源信号线图形901和所述辅助电源图形60所需要占用的布局空间，从而很好的缩小了像素结构，更有利于所述显示面板的高分辨率发展。
在一些实施例中，沿所述第一方向，所述第一辅助子图形601的宽度大于对应的所述电源信号线图形901的宽度。
上述设置所述第一辅助子图形601的宽度大于对应的所述电源信号线图形901的宽度，使得所述辅助电源图形60具有更大的面积，这样不仅有利于降低所述电源信号线图形901的IR drop，也更有利于实现所述辅助电源图形60与所述电源信号线图形901之间的耦接。
如图15、图19和图22所示，在一些实施例中，所述第一电极部51在所述基底上的正投影和所述第二电极部52在所述基底上的正投影，均被对应的所述电源信号线图形901在所述基底上的正投影覆盖。
上述设置所述第一电极部51在所述基底上的正投影和所述第二电极部52在所述基底上的正投影，均被对应的所述电源信号线图形901在所述基底上的正投影覆盖，不仅很好的保证了N1节点的电位稳定性，还有效缩小了所述第二晶体管的第二极和所述电源信号线图形901所需要占用的布局空间，从而很好的缩小了像素结构，更有利于所述显示面板的高分辨率发展。
在一些实施例中，所述功能膜层包括：位于各子像素区中的栅线图形902、发光控制信号线图形903；在同一所述子像素区中，沿第二方向，所述栅线图形902、所述发光控制信号线图形903、所述复位信号线图形905和所述初始化信号线图形904依次排列；所述功能膜层还包括位于各子像素区中的电源信号线图形901和数据线图形908，所述电源信号线图形901和所述数据线图形908均包括沿所述第二方向延伸的部分。
所述显示面板还包括：与所述多个子像素区一一对应的发光元件；与所述多个子像素区一一对应的子像素驱动电路，每个子像素驱动电路均包括：驱动晶体管、第一晶体管、第二晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管。
在同一子像素区中，所述驱动晶体管的栅极与所述第一晶体管的第二极耦接，所述驱动晶体管的第一极与所述第五晶体管的第二极耦接，所述驱动晶体管的第二极与所述第一晶体管的第一极耦接；所述第一晶体管的栅极与所述栅线图形902耦接；
所述第二晶体管的栅极与沿所述第二方向相邻的上一个子像素区中的所述复位信号线图形905耦接，所述第二晶体管的第一极作为所述上一个子像素区中的所述目标耦接部，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接；
所述第四晶体管的栅极与所述栅线图形902耦接，所述第四晶体管的第一极与所述数据线图形908耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
所述第五晶体管的栅极与所述发光控制信号线图形903耦接，所述第五晶体管的第一极与所述电源信号线图形901耦接；
所述第六晶体管的栅极与所述发光控制信号线图形903耦接，所述第六 晶体管的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管的第二极与对应的所述发光元件耦接；
所述第七晶体管的第二极与所述发光元件耦接，所述第七晶体管的栅极与所述复位信号线图形905耦接，所述第七晶体管的第一极与第二初始化信号线图形904耦接。
示例性的，每个所述子像素驱动电路均包括：7个薄膜晶体管和1个电容。该子像素驱动电路包括的各晶体管均采用P型晶体管。所述驱动晶体管即为所述第三晶体管。各晶体管的第一极即为源极，各晶体管的第二极即为漏极。
如图6、图15、图19～图22所示，第一晶体管T1为双栅结构，第一晶体管T1的栅极201g与栅线图形902耦接，第一晶体管T1的源极S1与第三晶体管T3(即驱动晶体管)的漏极D3耦接，第一晶体管T1的漏极D1与第三晶体管T3的栅极203g耦接。
第二晶体管T2为双栅结构，第二晶体管T2的栅极202g与沿所述第二方向相邻的上一个子像素区中的所述复位信号线图形905'耦接，第二晶体管T2的源极S2作为所述上一个子像素区中的所述目标耦接部，与所述上一个子像素区中的初始化信号线图形904'耦接，第二晶体管T2的漏极D2与第三晶体管T3的栅极203g耦接。
第四晶体管T4的栅极204g与所述栅线图形902耦接，第四晶体管T4的源极S4与数据线图形908耦接，第四晶体管T4的漏极D4与第三晶体管T3的源极S3耦接。
第五晶体管T5的栅极205g与发光控制信号线图形903耦接，第五晶体管T5的源极S5与电源信号线图形901耦接，第五晶体管T5的漏极D5与第三晶体管T3的源极S3耦接。
第六晶体管T6的栅极206g与发光控制信号线图形903耦接，第六晶体管T6的源极S6与第三晶体管T3的漏极D3耦接，第六晶体管T6的漏极D6与对应的发光元件EL的阳极耦接。
第七晶体管T7的栅极207g与所述复位信号线图形905耦接，第七晶体管T7的漏极D7与对应的发光元件EL的阳极耦接，第七晶体管T7的源极 S7与所述初始化信号线图形904耦接。
所述像素驱动电路还包括存储电容Cst，所述存储电容Cst的第一极板Cst1复用为第三晶体管T3的栅极203g，存储电容Cst的第二极板Cst2与所述电源信号线图形901耦接。
上述实施例提供的子像素驱动电路中，不仅避免了在进行打孔工艺时，容易在工艺波动时将过孔打偏到附近的复位信号线图形905上，导致信号扰乱的问题，进而更好的保证了所述显示面板的良率；而且，采用该子像素驱动电路的像素结构尺寸较小，更有利于所述显示面板实现高分辨率。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示面板。
由于上述公开实施例提供的显示面板中，设置了所述初始化信号线图形904背向所述复位信号线图形905的一侧包括第一突出部分9042，并设置了所述导电连接部图形909的第一端部9091在所述基底上的正投影，与所述第一突出部分9042在所述基底上的正投影具有第一交叠区域F1，所述第一端部9091与所述第一突出部分9042能够通过在所述第一交叠区域F1打孔耦接；这种设置方式使得用于耦接所述导电连接部和所述初始化信号线图形904的过孔与所述复位信号线图形905之间具有较远的距离，从而避免了在进行打孔工艺时，容易在工艺波动时将过孔打偏到附近的复位信号线图形905上，导致信号扰乱的问题，进而更好的保证了所述显示面板的良率。
另外，由于设置了所述初始化信号线图形904背向所述复位信号线图形905的一侧包括第一突出部分9042，用于耦接所述导电连接部和所述初始化信号线图形904的过孔形成在所述第一突出部分9042，使得该过孔在所述基底上的正投影能够被所述初始化信号线图形904在所述基底上的正投影包裹，从而很好的提升了所述初始化信号线图形904与所述导电连接部图形909耦接的信赖性，更好的保证了显示面板工作时的稳定性。
因此，本公开实施例提供的显示装置在包括上述显示面板时，同样具有上述有益效果，此处不再赘述。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件等。
本公开实施例还提供了一种显示面板的制作方法，用于制作上述实施例 提供的显示面板，所述制作方法包括：
在基底上制作功能膜层，并形成阵列排布的多个子像素区；
所述功能膜层包括：复位信号线层、初始化信号线层、导电连接部层；
所述复位信号线层包括：设置于各所述子像素区中的复位信号线图形905，所述复位信号线图形905沿第一方向延伸；
所述初始化信号线层包括：设置于各所述子像素区中的初始化信号线图形904，所述初始化信号线图形904包括相耦接的第一主体部分9041和第一突出部分9042，所述第一主体部分9041沿所述第一方向延伸，在同一子像素区中，所述第一主体部分9041在所述基底上的正投影位于所述第一突出部分9042在所述基底上的正投影与所述复位信号线图形905在所述基底上的正投影之间；
所述导电连接部层包括：设置于各所述子像素区中的导电连接部图形909，在同一子像素区中，所述导电连接部图形909的第一端部9091在所述基底上的正投影，与所述第一突出部分9042在所述基底上的正投影具有第一交叠区域F1，在所述第一交叠区域F1，该第一端部9091与该第一突出部分9042耦接，所述导电连接部图形909的第二端部9092与其所在子像素区中的目标耦接部耦接，所述复位信号线图形905在所述基底上的正投影，位于所述目标耦接部在所述基底上的正投影与所述初始化信号线图形904在所述基底上的正投影之间。
具体地，阵列排布的多个子像素区能够划分为沿第二方向依次排列的多行子像素区，和沿第一方向依次排列的多列子像素区。每行子像素区均包括沿第一方向间隔设置的多个子像素区，每列子像素区均包括沿所述第二方向间隔设置的多个子像素区。所述第一方向与所述第二方向相交，示例性的，所述第一方向包括X方向，所述第二方向包括Y方向。
所述复位信号线层包括设置于各所述子像素区中的复位信号线图形905，所述复位信号线图形905沿所述第一方向延伸。所述复位信号线图形905与所述子像素区一一对应，所述复位信号线图形905位于对应的所述子像素区中，位于同一行的子像素区对应的各所述复位信号线图形905依次电连接，形成为一体结构。
所述初始化信号线层包括：设置于各所述子像素区中的初始化信号线图形904，所述初始化信号线图形904与所述子像素区一一对应，所述初始化信号线图形904位于对应的所述子像素区中，位于同一行的子像素区对应的各所述初始化信号线图形904依次电连接，形成为一体结构。
每个所述初始化信号线图形904均包括相耦接的第一主体部分9041和第一突出部分9042，所述第一主体部分9041沿所述第一方向延伸，位于同一行的子像素区对应的各所述初始化信号线图形904中的所述第一主体部分9041依次电连接，形成为一体结构。值得注意，考虑到制作工艺的误差，所述第一主体部不一定是沿所述第一方向延伸的直线型。
所述第一突出部分9042的具体形状多种多样，能够满足在所述第二方向上，所述第一突出部分9042突出于其耦接的所述第一主体部分9041即可。通过设置在同一子像素区中，所述第一主体部分9041在所述基底上的正投影位于所述第一突出部分9042在所述基底上的正投影与所述复位信号线图形905在所述基底上的正投影之间，使得所述第一突出部分9042能够背向所述复位信号线图形905设置，从而使得所述第一突出部分9042能够与所述复位信号线图形905之间具有较远的距离。
需要说明，在一个初始化信号线图形904中，所述第一主体部分9041和所述第一突出部分9042可以形成为一体结构，但不仅限于此。
所述导电连接部层包括：设置于各所述子像素区中的导电连接部图形909，所述导电连接部图形909与所述子像素区一一对应，所述导电连接部图形909位于对应的所述子像素区中。
所述导电连接部图形909的第一端部9091在所述基底上的正投影，与所述第一突出部分9042在所述基底上的正投影具有第一交叠区域F1，该第一端部9091与该第一突出部分9042能够通过在所述第一交叠区域F1打孔耦接。所述导电连接部图形909的第二端部9092与其所在子像素区中的目标耦接部耦接，所述目标耦接部可以包括当前子像素区对应的第七晶体管的第一极，以及沿所述第二方向与当前子像素区相邻的下一个子像素区对应的第二晶体管的第一极。
所述目标耦接部的设置位置多种多样，示例性的，可设置同一子像素区 中，所述复位信号线图形905在所述基底上的正投影，位于所述目标耦接部在所述基底上的正投影与所述初始化信号线图形904在所述基底上的正投影之间。
需要说明，所述显示面板还包括层间介质层(即前面提到的第二层间绝缘层ILD)，所述层间介质层位于所述显示面板中的第二栅金属层和第一源漏金属层之间，所述初始化信号线图形904可以与所述第二栅金属层同层设置，并能够在同一次构图工艺中形成，所述导电连接部图形909可以与所述第一源漏金属层同层设置，并能够在同一次构图工艺中形成。上述在该第一交叠区域F1打孔以实现所述导电连接部图形909的第一端部9091与所述第一突出部分9042耦接，所制作的过孔为贯穿ILD层的过孔，该过孔的位置与所述复位信号线图形905之间的距离更远。
采用本公开实施例提供的制作方法制作的显示面板中，设置了所述初始化信号线图形904背向所述复位信号线图形905的一侧包括第一突出部分9042，并设置了所述导电连接部图形909的第一端部9091在所述基底上的正投影，与所述第一突出部分9042在所述基底上的正投影具有第一交叠区域F1，所述第一端部9091与所述第一突出部分9042能够通过在所述第一交叠区域F1打孔耦接；这种设置方式使得用于耦接所述导电连接部和所述初始化信号线图形904的过孔与所述复位信号线图形905之间具有较远的距离，从而避免了在进行打孔工艺时，容易在工艺波动时将过孔打偏到附近的复位信号线图形905上，导致信号扰乱的问题，进而更好的保证了所述显示面板的良率。
另外，由于设置了所述初始化信号线图形904背向所述复位信号线图形905的一侧包括第一突出部分9042，用于耦接所述导电连接部和所述初始化信号线图形904的过孔形成在所述第一突出部分9042，使得该过孔在所述基底上的正投影能够被所述初始化信号线图形904在所述基底上的正投影包裹，从而很好的提升了所述初始化信号线图形904与所述导电连接部图形909耦接的信赖性，更好的保证了显示面板工作时的稳定性。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实 施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种显示面板，包括：基底、设置在所述基底上的功能膜层；还包括阵列排布的多个子像素区；
    所述功能膜层包括：复位信号线层、初始化信号线层、导电连接部层；
    所述复位信号线层包括：设置于各所述子像素区中的复位信号线图形，所述复位信号线图形沿第一方向延伸；
    所述初始化信号线层包括：设置于各所述子像素区中的初始化信号线图形，所述初始化信号线图形包括相耦接的第一主体部分和第一突出部分，所述第一主体部分沿所述第一方向延伸，在同一子像素区中，所述第一主体部分在所述基底上的正投影位于所述第一突出部分在所述基底上的正投影与所述复位信号线图形在所述基底上的正投影之间；
    所述导电连接部层包括：设置于各所述子像素区中的导电连接部图形，在同一子像素区中，所述导电连接部图形的第一端部在所述基底上的正投影，与所述第一突出部分在所述基底上的正投影具有第一交叠区域，在所述第一交叠区域，该第一端部与该第一突出部分耦接，所述导电连接部图形的第二端部与其所在子像素区中的目标耦接部耦接，所述复位信号线图形在所述基底上的正投影，位于所述目标耦接部在所述基底上的正投影与所述初始化信号线图形在所述基底上的正投影之间。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    与所述多个子像素区一一对应的多个发光元件，所述多个发光元件位于所述功能膜层背向所述基底的一侧；
    与所述多个子像素区一一对应的多个子像素驱动电路，每个所述子像素驱动电路均包括第七晶体管，所述第七晶体管的栅极与对应的所述复位信号线图形耦接，所述第七晶体管的第一极作为所述目标耦接部，所述第七晶体管的第二极沿所述第二方向延伸，且与对应的发光元件的阳极耦接；
    所述导电连接部图形还包括连接在所述第一端部和所述第二端部之间的第二主体部分，所述第二主体部分沿第二方向延伸；在同一个子像素区中，沿所述第一方向，所述导电连接部图形的第一端部，向远离所述第七晶体管 的第二极的方向突出于所述第二主体部分。
  3. 根据权利要求2所述的显示面板，其中，所述功能膜层还包括位于各子像素区中的数据线图形，所述数据线图形包括沿所述第二方向延伸的部分；
    所述初始化信号线图形在所述基底上的正投影与所述导电连接部图形在所述基底上的正投影存在第三交叠区域；
    所述初始化信号线图形在所述基底上的正投影与所述数据线图形在所述基底上的正投影存在第四交叠区域；
    在所述第四交叠区域所述初始化信号线图形沿所述第二方向的宽度，小于在所述第三交叠区域所述初始化信号线图形沿所述第二方向的宽度。
  4. 根据权利要求2所述的显示面板，其中，在同一个子像素区中，所述第二主体部分在所述基底上的正投影，与所述第七晶体管的第二极在所述基底上的正投影之间具有第一间隙，所述第一间隙大于阈值。
  5. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    与所述多个子像素区一一对应的多个子像素驱动电路，每个所述子像素驱动电路均包括驱动晶体管和第二晶体管；
    所述第二晶体管的栅极与沿所述第二方向相邻的上一个子像素区中的所述复位信号线图形耦接，所述第二晶体管的第一极作为所述上一个子像素区中的所述目标耦接部，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接；
    所述第二晶体管包括沿所述第一方向间隔设置的两个半导体部分，以及分别连接所述两个半导体部分的第一导体部分，所述第一导体部分在所述基底上的正投影，与所述上一个子像素区中的所述第一突出部分在所述基底上的正投影不交叠。
  6. 根据权利要求5所述的显示面板，其中，所述第一导体部分在所述基底上的正投影，与所述上一个子像素区中的所述导电连接部图形的第一端部在所述基底上的正投影交叠。
  7. 根据权利要求5所述的显示面板，其中，每个所述初始化信号线图形还包括与所述第一主体部分耦接的第二突出部分，在同一子像素区中，所述第二突出部分在所述基底上的正投影位于所述第一主体部分在所述基底上的 正投影与所述复位信号线图形在所述基底上的正投影之间，所述第一导体部分在所述基底上的正投影与所述第二突出部分在所述基底上的正投影交叠。
  8. 根据权利要求5所述的显示面板，其中，所述导电连接部图形还包括连接在所述第一端部和所述第二端部之间的第二主体部分，该第二主体部分沿第二方向延伸；
    所述第一导体部分中靠近所述上一个子像素区中的所述导电连接部图形的一端沿所述第二方向延伸，该一端在所述基底上的正投影，与该导电连接部图形的第二主体部分在所述基底上的正投影之间具有第二间隙，所述第二间隙大于阈值。
  9. 根据权利要求5所述的显示面板，其中，在同一子像素区中，所述导电连接部图形的第一端部在所述基底上的正投影，还与所述初始化信号线图形的第一主体部分在所述基底上的正投影形成第二交叠区域；
    所述功能膜层还包括位于各所述子像素区中的第一连接孔，在同一子像素区中，所述第一连接孔在所述基底上的正投影，分别与所述第一交叠区域和所述第二交叠区域交叠，所述导电连接部图形的第一端部通过所述第一连接孔与所述初始化信号线图形耦接。
  10. 根据权利要求9所述的显示面板，其中，所述第二晶体管的所述第一导体部分在所述基底上的正投影，与所述上一个子像素区中的所述第一连接孔在所述基底上的正投影不交叠。
  11. 根据权利要求5所述的显示面板，其中，所述功能膜层还包括电源信号线层，所述电源信号线层包括设置于各所述子像素区中的电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸；
    所述第一导体部分中远离所述上一个子像素区中的所述导电连接部图形的一端沿所述第二方向延伸，该一端在所述基底上的正投影，被位于同一子像素区中的所述电源信号线图形在所述基底上的正投影完全覆盖。
  12. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    与所述多个子像素区一一对应的多个子像素驱动电路，每个所述子像素驱动电路均包括驱动晶体管和存储电容，所述存储电容包括相对设置的第一极板和第二极板，所述第一极板复用为所述驱动晶体管的栅极，所述第二极 板位于所述第一基板背向所述基底的一侧；
    所述功能膜层还包括电源信号线层，所述电源信号线层包括设置于各所述子像素区中的电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸，所述电源信号线图形包括第一电源部和第二电源部；
    所述第一电源部在所述基底上的正投影与位于同一子像素区中的各所述复位信号线图形在所述基底上的正投影交叠，并与位于同一子像素区中的各所述栅线图形在所述基底上的正投影交叠；所述第二电源部在所述基底上的正投影与对应的所述存储电容的第二极板在所述基底上的正投影交叠；沿所述第一方向所述第一电源部的宽度小于所述第二电源部的宽度。
  13. 根据权利要求1所述的显示面板，其中，所述功能膜层还包括电源信号线层，所述电源信号线层包括设置于各所述子像素区中的电源信号线图形，所述电源信号线图形的至少部分沿第二方向延伸；
    所述功能膜层还包括辅助电源层，所述辅助电源层包括设置于各所述子像素区中的辅助电源图形，所述辅助电源图形在所述基底上的正投影与位于同一子像素区中的电源信号线图形在所述基底上的正投影存在交叠区域，所述辅助电源图形与该电源信号线图形在该交叠区域耦接。
  14. 根据权利要求13所述的显示面板，其中，所述显示面板还包括：与所述多个子像素区一一对应的多个子像素驱动电路，每个所述子像素驱动电路均包括驱动晶体管和第二晶体管；
    所述第二晶体管的栅极与沿所述第二方向相邻的上一个子像素区中的所述复位信号线图形耦接，所述第二晶体管的第一极作为所述上一个子像素区中的所述目标耦接部，所述第二晶体管的第二极包括相耦接的第一电极部和第二电极部，所述第一电极部沿第二方向延伸，所述第二电极部沿第三方向延伸，所述第三方向与所述第一方向和所述第二方向均相交，所述第一电极部位于所述第二晶体管的半导体部分与所述第二电极部之间，所述第二电极部与所述驱动晶体管的栅极耦接；
    所述第一电极部在所述基底上的正投影和所述第二电极部在所述基底上的正投影，均被对应的所述辅助电源图形在所述基底上的正投影覆盖。
  15. 根据权利要求14所述的显示面板，其中，所述辅助电源图形包括相 耦接的第一辅助子图形和第二辅助子图形，所述第一辅助子图形沿第二方向延伸，所述第二辅助子图形的至少部分沿所述第一方向延伸；
    所述第一辅助子图形在所述基底上的正投影覆盖所述第一电极部在所述基底上的正投影和所述第二电极部在所述基底上的正投影。
  16. 根据权利要求15所述的显示面板，其中，沿所述第一方向，所述第一辅助子图形的宽度大于对应的所述电源信号线图形的宽度。
  17. 根据权利要求14所述的显示面板，其中，所述第一电极部在所述基底上的正投影和所述第二电极部在所述基底上的正投影，均被对应的所述电源信号线图形在所述基底上的正投影覆盖。
  18. 根据权利要求1所述的显示面板，其中，所述功能膜层包括：位于各子像素区中的栅线图形、发光控制信号线图形；在同一所述子像素区中，沿第二方向，所述栅线图形、所述发光控制信号线图形、所述复位信号线图形和所述初始化信号线图形依次排列；
    所述功能膜层还包括位于各子像素区中的电源信号线图形和数据线图形，所述电源信号线图形和所述数据线图形均包括沿所述第二方向延伸的部分；
    所述显示面板还包括：
    与所述多个子像素区一一对应的发光元件；
    与所述多个子像素区一一对应的子像素驱动电路，每个子像素驱动电路均包括：驱动晶体管、第一晶体管、第二晶体管、第四晶体管、第五晶体管、第六晶体管和第七晶体管；
    在同一子像素区中，所述驱动晶体管的栅极与所述第一晶体管的第二极耦接，所述驱动晶体管的第一极与所述第五晶体管的第二极耦接，所述驱动晶体管的第二极与所述第一晶体管的第一极耦接；
    所述第一晶体管的栅极与所述栅线图形耦接；
    所述第二晶体管的栅极与沿所述第二方向相邻的上一个子像素区中的所述复位信号线图形耦接，所述第二晶体管的第一极作为所述上一个子像素区中的所述目标耦接部，所述第二晶体管的第二极与所述驱动晶体管的栅极耦接；
    所述第四晶体管的栅极与所述栅线图形耦接，所述第四晶体管的第一极 与所述数据线图形耦接，所述第四晶体管的第二极与所述驱动晶体管的第一极耦接；
    所述第五晶体管的栅极与所述发光控制信号线图形耦接，所述第五晶体管的第一极与所述电源信号线图形耦接；
    所述第六晶体管的栅极与所述发光控制信号线图形耦接，所述第六晶体管的第一极与所述驱动晶体管的第二极耦接，所述第六晶体管的第二极与对应的所述发光元件耦接；
    所述第七晶体管的第二极与所述发光元件耦接，所述第七晶体管的栅极与所述复位信号线图形耦接，所述第七晶体管的第一极与第二初始化信号线图形耦接。
  19. 一种显示装置，包括如权利要求1～18中任一项所述的显示面板。
  20. 一种显示面板的制作方法，包括：
    在基底上制作功能膜层，并形成阵列排布的多个子像素区；
    所述功能膜层包括：复位信号线层、初始化信号线层、导电连接部层；
    所述复位信号线层包括：设置于各所述子像素区中的复位信号线图形，所述复位信号线图形沿第一方向延伸；
    所述初始化信号线层包括：设置于各所述子像素区中的初始化信号线图形，所述初始化信号线图形包括相耦接的第一主体部分和第一突出部分，所述第一主体部分沿所述第一方向延伸，在同一子像素区中，所述第一主体部分在所述基底上的正投影位于所述第一突出部分在所述基底上的正投影与所述复位信号线图形在所述基底上的正投影之间；
    所述导电连接部层包括：设置于各所述子像素区中的导电连接部图形，在同一子像素区中，所述导电连接部图形的第一端部在所述基底上的正投影，与所述第一突出部分在所述基底上的正投影具有第一交叠区域，在所述第一交叠区域，该第一端部与该第一突出部分耦接，所述导电连接部图形的第二端部与其所在子像素区中的目标耦接部耦接，所述复位信号线图形在所述基底上的正投影，位于所述目标耦接部在所述基底上的正投影与所述初始化信号线图形在所述基底上的正投影之间。
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KR102926382B1 (ko) 2026-02-11
JP7772295B2 (ja) 2025-11-18
JP2025011164A (ja) 2025-01-23
CN114080688A (zh) 2022-02-22
EP4131391B1 (en) 2025-12-17
US20210358420A1 (en) 2021-11-18
EP4131391A1 (en) 2023-02-08
JP2023528549A (ja) 2023-07-05
EP4131391A4 (en) 2023-10-25
CN114080688B (zh) 2026-01-13
JP7566796B2 (ja) 2024-10-15
KR20220158597A (ko) 2022-12-01
US11875752B2 (en) 2024-01-16

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