WO2021189887A1 - 半导体结构及其预热方法 - Google Patents

半导体结构及其预热方法 Download PDF

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Publication number
WO2021189887A1
WO2021189887A1 PCT/CN2020/131414 CN2020131414W WO2021189887A1 WO 2021189887 A1 WO2021189887 A1 WO 2021189887A1 CN 2020131414 W CN2020131414 W CN 2020131414W WO 2021189887 A1 WO2021189887 A1 WO 2021189887A1
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Prior art keywords
chip
memory
temperature
detection unit
temperature detection
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Ceased
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PCT/CN2020/131414
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English (en)
French (fr)
Inventor
寗树梁
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to EP20926529.7A priority Critical patent/EP3955295B1/en
Priority to US17/396,686 priority patent/US11862223B2/en
Publication of WO2021189887A1 publication Critical patent/WO2021189887A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/284—Configurations of stacked chips characterised by structural arrangements for measuring or testing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips

Definitions

  • the present invention relates to the field of memory, in particular to a semiconductor structure and a preheating method thereof.
  • Dynamic random access memory (Dynamic Random Access Memory, DRAM) is a semiconductor memory device commonly used in computers, and its memory array area is composed of many repeated memory cells. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line Read the data information stored in the capacitor, or write the data information into the capacitor through the bit line for storage.
  • DRAM Dynamic Random Access Memory
  • the technical problem to be solved by the present invention is how to reduce the writing time when writing data to the memory in a low temperature environment and improve the stability of writing.
  • the present invention provides a semiconductor structure, including:
  • the temperature detection unit is used to detect the temperature of the memory chip before the memory chip is started
  • the control chip is used to heat the memory chip before the memory chip is started, and determine whether the temperature detected by the temperature detection unit reaches a set threshold, and if it reaches the set threshold, control the memory chip to start.
  • the number of the memory chips is 1 or greater than or equal to 2, and when the number of memory chips is greater than or equal to 2, several memory chips are sequentially stacked upwards.
  • the storage chip is located on a control chip, and the storage chip is electrically connected to the control chip.
  • circuit substrate has connection lines
  • the memory chip and the control chip are both located on the circuit substrate, and the memory chip and the control chip are connected through the connection lines in the circuit substrate.
  • the temperature detection unit is electrically connected to the control chip, the number of the temperature detection unit is 1 or greater than or equal to 2, and the temperature detection unit is located in the control chip or in the memory chip, or in On the circuit board between the memory chip and the control chip.
  • control chip determines that the temperature detected by the one temperature detection unit reaches a set threshold, it controls all the memory chips to start.
  • the control chip first controls when it determines that the temperature of the one temperature detection unit reaches a set threshold The memory chip closest to the control chip is started, and then the other memory chips above are controlled to start sequentially.
  • each storage chip has a temperature detection unit, and the control chip sequentially determines all the storage chips.
  • the control chip sequentially determines all the storage chips.
  • control chip controls the storage chip to start
  • control chip also controls the storage chip to perform write, read, and erase operations.
  • control chip before the control chip heats the memory chip, the control chip first starts up, and the control chip heats the memory chip by using heat generated by itself after starting up.
  • control chip has an additional heating circuit for heating the memory chip.
  • the control chip determines whether the temperature of the memory chip detected by the temperature detection unit reaches a set threshold, and if it does not reach the set threshold, then The heating circuit is controlled to heat the memory chip, and if the set threshold is reached, the heating circuit is controlled to stop heating the memory chip.
  • the memory chip is a DRAM memory chip.
  • the present invention also provides a method for preheating a semiconductor structure, including:
  • a semiconductor structure including a memory chip, a control chip electrically connected to the memory chip, and a temperature detection unit;
  • the control chip determines whether the temperature detected by the temperature detection unit reaches the set threshold, and if it reaches the set threshold, the storage chip is controlled to start.
  • the number of the temperature detection units is 1 or greater than or equal to 2
  • the number of memory chips is 1 or greater than or equal to 2
  • the plurality of memory chips are sequentially upward Stacked.
  • control chip determines that the temperature detected by the one temperature detection unit reaches a set threshold, it controls all the memory chips to start.
  • the control chip first controls when it determines that the temperature of the one temperature detection unit reaches a set threshold The memory chip closest to the control chip is started, and then the other memory chips above are controlled to start sequentially.
  • each storage chip has a temperature detection unit, and the control chip sequentially determines all the storage chips.
  • the control chip sequentially determines all the storage chips.
  • control chip controls the storage chip to start
  • control chip also controls the storage chip to perform write, read, and erase operations.
  • the semiconductor structure of the present invention includes: a memory chip; a temperature detection unit for detecting the temperature of the memory chip before the memory chip is started; a control chip for heating the memory chip before the memory chip is started, and judging the temperature detection Whether the temperature detected by the unit reaches the set threshold, and if it reaches the set threshold, the memory chip is controlled to start.
  • the control chip heats the storage chip before the storage chip is started
  • the temperature detection unit detects the temperature of the storage chip before the storage chip is started
  • the control chip judges the temperature detection Whether the temperature detected by the unit reaches the set threshold, if it reaches the set threshold, the memory chip is controlled to start.
  • the temperature of the memory chip can be raised to the set threshold by controlling the chip. This can prevent the bit lines, word lines, and metal connections (metal contacts) in the memory chip from increasing resistance due to low ambient temperature, thereby reducing the time when data is written to the memory in a low-temperature environment.
  • the writing time improves the stability of the memory writing.
  • the number of the temperature detection unit is one.
  • the one temperature precision measurement unit can be located in the control chip, or the one temperature detection unit can also be located in the memory chip, or the one The temperature detection unit may also be located on the circuit substrate between the storage chip and the control chip.
  • the control chip determines that the temperature detected by the one temperature detection unit reaches a set threshold, it controls all the storage chips to start.
  • the aforementioned control structure and control method are relatively simple, and can reduce the writing time when writing data to the memory chip in a low-temperature environment, and improve the writing time of the memory chip. stability.
  • the control chip first controls the exit when it determines that the temperature of the one temperature detection unit reaches the set threshold.
  • the most recent memory chip of the control chip is started, and then the other memory chips above are controlled to start sequentially.
  • the aforementioned control structure and control method can enable each memory chip to start after reaching the set threshold temperature, which improves the accuracy of the startup timing of each memory chip and reduces The writing time when writing data to each memory chip in a low temperature environment improves the stability of writing to each memory chip.
  • each memory chip has a temperature detection unit, and the control chip sequentially determines all the temperatures When the temperature detected by the detection unit reaches the set threshold, if the temperature detected by a certain temperature detection unit reaches the set threshold, the memory chip corresponding to the temperature detection unit is controlled to start.
  • the aforementioned control structure and control method can further improve the accuracy of the startup timing of each memory chip and each memory chip, and can further reduce the impact on each memory chip in a low-temperature environment.
  • the writing time during data writing further improves the stability of writing to each memory chip.
  • control chip before the control chip heats the memory chip, the control chip first starts up, and the control chip uses the heat generated by itself after starting to heat the memory chip without requiring an additional heating circuit, thereby simplifying the semiconductor The structure of the structure.
  • control chip may have an additional heating circuit for heating the memory chip. Before or after the control chip heats the memory chip, the control chip determines whether the temperature of the memory chip detected by the temperature detection unit reaches a set threshold, and if it does not reach the set threshold, controls the heating The circuit heats the memory chip, and if the set threshold is reached, the heating circuit is controlled to stop heating the memory chip. In this way, precise control of the heating process is realized, so that the temperature of the memory chip can be kept near the set threshold, and the temperature of the memory chip is prevented from being too high or too low, so that the writing time to the memory can always be kept short.
  • the non-activated memory chip is heated by the control chip; the temperature of the memory chip is detected by the temperature detection unit; the temperature detection is determined by the control chip Whether the temperature detected by the unit reaches the set threshold, and if it reaches the set threshold, the memory chip is controlled to start. Therefore, when the semiconductor structure of the present invention is working in a low temperature environment, the memory chip can be heated to a set threshold by controlling the chip, thereby preventing the bit lines, word lines, and metal connections (metal contacts) in the memory chip from being affected by the environment.
  • the increase in resistance caused by the low temperature reduces the writing time when writing data to the memory in a low-temperature environment, and improves the stability of the memory writing.
  • FIGS. 1-7 are structural schematic diagrams of the semiconductor structure in the embodiment of the present invention.
  • FIG. 8 is a schematic flowchart of a preheating method for a semiconductor structure in an embodiment of the present invention.
  • the present invention provides a semiconductor structure and a preheating method thereof, wherein the semiconductor structure includes: a storage chip; a temperature detection unit for detecting the temperature of the storage chip before the storage chip is started; The storage chip is heated before the storage chip is started, and it is determined whether the temperature detected by the temperature detection unit reaches a set threshold, and if it reaches the set threshold, the storage chip is controlled to start.
  • the control chip heats the storage chip before the storage chip is started
  • the temperature detection unit detects the temperature of the storage chip before the storage chip is started
  • the control chip judges the temperature detection Whether the temperature detected by the unit reaches the set threshold, if it reaches the set threshold, the memory chip is controlled to start.
  • the temperature of the memory chip can be raised to the set threshold by controlling the chip. This can prevent the bit lines, word lines, and metal connections (metal contacts) in the memory chip from increasing resistance due to low ambient temperature, thereby reducing the time when data is written to the memory in a low-temperature environment.
  • the writing time improves the stability of the memory writing.
  • FIG. 1-7 are schematic diagrams of the structure of the semiconductor structure in the embodiment of the present invention.
  • FIG. 8 is a schematic flowchart of the preheating method of the semiconductor structure in the embodiment of the present invention.
  • an embodiment of the present invention provides a semiconductor structure, including:
  • the temperature detection unit 203 is configured to detect the temperature of the storage chip 201 before the storage chip 201 is started;
  • the control chip 301 is used to heat the memory chip 201 before the memory chip 201 is started, and determine whether the temperature detected by the temperature detection unit 203 reaches a set threshold, and if it reaches the set threshold, control the memory chip 201 to start .
  • the memory chip 201 is an existing memory capable of data writing, data reading and/or data deletion.
  • the memory chip 201 is formed through a semiconductor integrated manufacturing process.
  • the specific memory chip 201 may include a memory array and A peripheral circuit connected to a storage array.
  • the storage array includes a number of memory cells and bit lines, word lines, and metal connections (metal contacts) connected to the memory cells.
  • the memory cells are used to store data, and the peripheral The circuit is the relevant circuit when operating the memory array.
  • the memory chip 201 is a DRAM memory chip.
  • the DRAM memory chip includes a number of memory cells.
  • the memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to the word line and the drain is connected to the word line. The bit line is connected, and the source is connected to the capacitor.
  • the memory chip 201 may be other types of memory chips.
  • the number of the storage chip 201 is at least one. Specifically, the number of the storage chip 201 may be one or greater than or equal to two. When the number of the storage chips is greater than or equal to two, a plurality of storage chips are sequentially stacked upward to form a storage chip stack structure. In this embodiment, referring to FIG. 2, the number of the memory chips 201 is 4 as an example. The 4 memory chips 201 are sequentially stacked from bottom to top to form a memory chip stack structure. Adjacent memory chips 201 are bonded by bonding Process or bonding process to fit together.
  • a through silicon via interconnect structure is formed in the memory chip 201, and the memory chip 201 and the control chip 301 are electrically connected through the through silicon via interconnect structure (TSV).
  • TSV through silicon via interconnect structure
  • each memory chip 201 may be connected to the control chip 201 through a different through silicon via interconnect structure (TSV).
  • TSV through silicon via interconnect structure
  • the memory chip 201 may also be connected to the control chip 301 through metal wires (formed by a wire bonding process).
  • the storage chip 201 is located on the control chip 301, and the storage chip 201 is electrically connected to the control chip 301. Specifically, when there is only one memory chip 201, the control chip 301 and the memory chip 201 are bonded together. When there are multiple memory chips 201 forming a memory chip stack structure, the control chip 301 and the stack structure are the most The bottom memory chips 201 are bonded together.
  • the semiconductor structure further includes a circuit substrate 401.
  • connection lines in 401 the memory chip 201 and the control chip 301 are both located on the circuit substrate 104, and the memory chip 201 and the control chip 301 are connected by the connection line in the circuit substrate 104.
  • the specific circuit 401 may basically be PCB substrate.
  • the control chip 301 is formed by a semiconductor integrated manufacturing process.
  • the control chip 301 can be used to heat the memory chip 201 so that the temperature of the memory chip 201 can reach a set threshold (the set threshold can be set in the control chip 301, and the specific size of the threshold is set It can be set according to actual needs or experience), the control chip 301 is also used to control the startup of the storage chip 201 (the startup of the storage chip includes power-on and self-test) and perform related operations on the storage chip 201 (the related Operations include writing data to the memory chip 201, reading data from the memory chip 201, and deleting data accessed in the memory chip 201, etc.).
  • the semiconductor structure further includes a temperature detection unit 203, which is used to measure the temperature of the storage chip 201 before the storage chip 201 is started, and the temperature detection unit 203 is electrically connected to the control chip 301.
  • the temperature detection unit 203 is electrically connected to the control chip 301.
  • the temperature detected by the detection unit 203 is transmitted to the control chip, and the temperature measured by the temperature detection unit 203 serves as a basis for the control chip 301 to control the activation of the storage chip 201.
  • the control chip 301 heats the storage chip 201 before the storage chip 201 is started, and the temperature detection unit 203 detects the storage chip 201 before the storage chip 201 is started.
  • the control chip 30 determines whether the temperature detected by the temperature detection unit 203 reaches the set threshold, and if it reaches the set threshold, controls the memory chip 201 to start, so when the semiconductor structure of the present invention is working in a low temperature environment
  • the memory chip 201 can be heated to a set threshold, which can prevent the bit lines, word lines, and metal connections (metal contacts) in the memory chip from increasing resistance due to low ambient temperature. , Thereby reducing the writing time when writing data to the memory in a low temperature environment, and improving the stability of the memory writing.
  • the temperature detection unit 203 includes a temperature sensor, which is used to sense temperature and convert the sensed temperature into an electrical signal.
  • the temperature sensor is a PN junction temperature sensor or a capacitive temperature sensor.
  • the temperature sensor can be formed in the memory chip 201 or the control chip 301 through a semiconductor integrated manufacturing process, or located in the memory chip 201 and the control chip 301.
  • the number of the temperature detection unit 203 may be one or greater than or equal to two, and the temperature detection unit 203 may be located in the control chip 301 or in the memory chip 201.
  • the number of the temperature detection unit 203 is one.
  • the one temperature precision measurement unit 203 may be located in the control chip 203 (refer to FIG. 1 or FIG. 4), or the one The temperature detection unit 203 may also be located in the memory chip 201 (when there is only one memory chip 201, the one temperature detection unit 203 is directly located in the memory chip 201; when a plurality of memory chips 201 form a stacked structure, the one temperature The detection unit 203 is located in one of the storage chips 201, preferably located in the storage chip 201 at the bottom of the stack structure (refer to FIG. 2 or FIG.
  • the one temperature detection unit 203 may also be located in the storage chip 201 and the control On the circuit substrate 104 (refer to FIG. 5) between the chips 301, when the control chip 301 determines that the temperature detected by the one temperature detection unit reaches a set threshold, it controls all the memory chips 201 to start.
  • the control chip 301 determines that the temperature detected by the one temperature detection unit reaches a set threshold, it controls all the memory chips 201 to start.
  • the aforementioned control structure and control method are relatively simple, and can reduce the writing time when writing data to the memory chip in a low-temperature environment, and improve the writing of the memory chip. The stability.
  • the control chip 301 determines that the temperature of the one temperature detection unit reaches the set threshold, it first controls the memory chip 201 closest to the control chip 301 to start, and then controls the other memory chips 201 above to start sequentially. Specifically, referring to FIG. 1 (or FIG. 2, or FIG. 4 to FIG. 6), when the number of the temperature detection unit 203 is one, and the number of the memory chip 201 is greater than or equal to two,
  • the control chip 301 determines that the temperature of the one temperature detection unit reaches the set threshold, it first controls the memory chip 201 closest to the control chip 301 to start, and then controls the other memory chips 201 above to start sequentially. Specifically, referring to FIG.
  • the control chip 301 determines that the temperature of the one temperature detection unit reaches a set threshold, first control the memory chip 201 closest to the control chip 301 (The bottom memory chip in the stack structure) is started, and then the other three memory chips 201 on the upper layer are controlled to start sequentially.
  • the aforementioned control structure and control method can enable each memory chip 201 to start after reaching the set threshold temperature, which improves the accuracy of the startup timing of each memory chip 201. And it can reduce the writing time when writing data to each memory chip in a low temperature environment, and improve the stability of writing to each memory chip.
  • each memory chip 201 there is a temperature detection unit 203.
  • the control chip 301 sequentially determines whether the temperatures detected by all the temperature detection units 203 reach a set threshold, if the temperature detected by a certain temperature detection unit 203 reaches the set threshold, control the The memory chip corresponding to the temperature detection unit 203 is activated.
  • the temperature detected by the temperature detection unit 203 obtains four temperature detection values.
  • the control unit 301 will sequentially determine whether the temperature detected by the temperature detection unit 203 reaches the set threshold. If the temperature detected by a certain temperature detection unit 203 reaches The threshold is set, and the memory chip corresponding to the temperature detection unit 203 is controlled to start. For example, when the temperature detected by the temperature detection unit 203 in the memory chip 201 at the bottom of the stack structure first reaches the set threshold, the control chip 301 controls all the chips first.
  • the memory chip 201 at the bottom of the stack structure is activated, and then, when the temperature detected by the corresponding temperature detection unit 203 in the memory chip 201 in the penultimate layer of the stack structure also reaches the set threshold, the control unit 301 then controls The memory chip 201 of the penultimate layer in the stack structure is activated, and the activation of the memory chips 201 of the upper two layers can be deduced by analogy.
  • the aforementioned control structure and control method can further improve the accuracy of the startup timing of each memory chip 201 and each memory chip 201, and can further reduce the impact of each memory chip 201 in a low temperature environment.
  • the writing time when a memory chip writes data further improves the stability of writing to each memory chip.
  • control chip 301 before the control chip 301 heats the memory chip 201, the control chip 301 needs to be started, such as powering on the control chip 301 and self-checking.
  • the control chip 301 When the control chip 301 is started, the control chip 301 301 will not issue instructions to the memory chip 201. Only when the temperature detected by the temperature detection unit reaches the set threshold value, the control chip 301 will control the memory chip 201 to start. The self-generated heat heats the memory chip, so no additional heating circuit is needed, thereby simplifying the structure of the semiconductor structure.
  • control chip 301 controls the storage chip 201 to start
  • the control chip 301 also controls the storage chip 201 to perform writing, reading, and erasing operations.
  • the control chip 301 has a control circuit, and the control circuit is used to control the storage chip 201 to start and control the storage chip 201 to perform writing, reading, and erasing operations.
  • control chip 301 may have an additional heating circuit for heating the memory chip 201. Before or after the control chip 301 heats the memory chip 201, the control chip determines whether the temperature of the memory chip detected by the temperature detection unit reaches a set threshold, and if it does not reach the set threshold, it controls all The heating circuit heats the memory chip, and if the set threshold is reached, the heating circuit is controlled to stop heating the memory chip. In this way, precise control of the heating process is achieved, so that the temperature of the memory chip 201 can be maintained near the set threshold, and the temperature of the memory chip 201 is prevented from being too high or too low, so that the writing time to the memory can always be kept short.
  • the present invention also provides a method for preheating a semiconductor structure, including the steps:
  • Step S101 providing a semiconductor structure, the semiconductor structure including a memory chip, a control chip electrically connected to the memory chip, and a temperature detection unit;
  • Step S102 start the control chip
  • Step S103 heating the memory chip that is not activated by the control chip
  • Step S104 detecting the temperature of the memory chip by a temperature detecting unit
  • step S105 the control chip determines whether the temperature detected by the temperature detection unit reaches a set threshold, and if it reaches the set threshold, control the storage chip to start.
  • the number of the temperature detection units is 1 or greater than or equal to 2
  • the number of memory chips is 1 or greater than or equal to 2
  • when the number of memory chips is greater than or equal to 2 several memory chips are sequentially stacked upwards .
  • control chip determines that the temperature detected by the one temperature detection unit reaches a set threshold, it controls all the memory chips to start.
  • the control chip determines that the temperature of the one temperature detection unit reaches the set threshold, the memory chip closest to the control chip is controlled to start, and then the other memory chips above are controlled to start sequentially.
  • each memory chip has a temperature detection unit, and the control chip sequentially determines all When the temperature detected by the temperature detection unit reaches the set threshold, if the temperature detected by a certain temperature detection unit reaches the set threshold, the memory chip corresponding to the temperature detection unit is controlled to start.
  • control chip controls the storage chip to start
  • control chip also controls the storage chip to perform write, read, and erase operations.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

一种半导体结构及其预热方法，其中所述半导体结构包括：存储芯片；温度检测单元，用于在存储芯片启动之前检测存储芯片的温度；控制芯片，用于在存储芯片启动之前对存储芯片进行加热，并判断所述温度检测单元检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片启动。当本发明的半导体结构工作在低温环境时，通过控制芯片可以使得存储芯片升温到设定阈值，从而可以防止存储芯片中的位线、字线、以及金属连线（金属接触部）由于环境温度过低带来的电阻的增大，从而减小了低温环境下的对存储器进行数据写入时的写入时间，提高了存储器写入的稳定性。

Description

半导体结构及其预热方法
相关申请引用说明
本申请要求于2020年03月25日递交的中国专利申请号202010216794.0，申请名为“半导体结构及其预热方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本发明涉及存储器领域，尤其涉及一种半导体结构及其预热方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，其存储阵列区由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
现有在低温环境中，对存储器进行写入时，存在写入时间较长，写入的稳定性仍需要提高的问题。
发明内容
本发明所要解决的技术问题是怎样减小在低温环境中对存储器进行数据写入时的写入时间，提高写入的稳定性。
为此，本发明提供了一种半导体结构，包括：
存储芯片；
温度检测单元，用于在存储芯片启动之前检测存储芯片的温度；
控制芯片，用于在存储芯片启动之前对存储芯片进行加热，并判断所述温度检测单元检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片启动。
可选的，所述存储芯片的数量为1个或者大于等于2个，所述存储芯片的数量大于等于2个时，若干存储芯片依次向上堆叠。
可选的，所述存储芯片位于控制芯片上，所述存储芯片与所述控制芯片电连接。
可选的，还包括线路基板，所述线路基板中具有连接线路，所述存储芯片以及控制芯片均位于线路基板上，所述存储芯片和控制芯片通过线路基板中的连接线路连接。
可选的，所述温度检测单元与所述控制芯片电连接，所述温度检测单元的数量为1个或者大于等于2个，所述温度检测单元位于控制芯片中或者位于存储芯片中，或者位于存储芯片和控制芯片之间的线路基板上。
可选的，所述温度检测单元数量为1个时，所述控制芯片判断所述1个温度检测单元检测的温度达到设定阈值时，则控制所有所述存储芯片启动。
可选的，所述温度检测单元数量为1个，且所述存储芯片的数量为大于等于2个时，所述控制芯片判断所述1个温度检测单元的温度达到设定阈值时，先控制离所述控制芯片最近的存储芯片启动，然后再控制上面的其他存储芯片依次启动。
可选的，所述温度检测单元数量为大于等于2个时，且所述存储芯片的数量大于等于2个时，每一个存储芯片中具有一个温度检测单元，所述控制芯片依次判断所有的所述温度检测单元检测的温度是否达到设定阈值时，若某一个温度检测单元检测的温度达到设定阈值，则控制该温度检测单元对应的存储芯片启动。
可选的，所述控制芯片控制所述存储芯片启动后，所述控制芯片还控制所述存储芯片进行写入、读取和擦除操作。
可选的，所述控制芯片对所述存储芯片进行加热之前，所述控制芯片先进行启动，所述控制芯片利用启动后自生产生的热量对存储芯片进行加热。
可选的，所述控制芯片中具有额外的加热电路，用于对所述存储芯片进行加热。
可选的，所述控制芯片在对所述存储芯片进行加热之前或之后，所述控制芯片判断所述温度检测单元检测的存储芯片的温度是否达到设定阈值，若未达到设定阈值，则控制所述加热电路对存储芯片进行加热，如达到设定阈值，则控制所述加热电路停止对存储芯片进行加热。
可选的，所述存储芯片为DRAM存储芯片。
本发明还提供了一种对半导体结构进行预热的方法，包括：
提供半导体结构，所述半导体结构包括存储芯片，与所述存储芯片电连接的控制芯片，以及温度检测单元；
启动控制芯片；
通过控制芯片对未启动的存储芯片进行加热；
通过温度检测单元检测所述存储芯片的温度；
通过控制芯片判断所述温度检测单元检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片启动。
可选的，所述温度检测单元的数量为1个或者大于等于2个，所述存储芯片的数量为1个或大于等于2个，所述存储芯片大于等于2个时，若干存储芯片依次向上堆叠。
可选的，所述温度检测单元数量为1个时，所述控制芯片判断所述1个温度检测单元检测的温度达到设定阈值时，则控制所有所述存储芯片启动。
可选的，所述温度检测单元数量为1个，且所述存储芯片的数量为大于等于2个时，所述控制芯片判断所述1个温度检测单元的温度达到设定阈值时，先控制离所述控制芯片最近的存储芯片启动，然后再控制上面的其他存储芯片依次启动。
可选的，所述温度检测单元数量为大于等于2个时，且所述存储芯片的数量大于等于2个时，每一个存储芯片中具有一个温度检测单元，所述控制芯片依次判断所有的所述温度检测单元检测的温度是否达到设定阈值时，若某一个温度检测单元检测的温度达到设定阈值，则控制该温度检测单元对应的存储芯片启动。
可选的，所述控制芯片控制所述存储芯片启动后，所述控制芯片还控制所述存储芯片进行写入、读取和擦除操作。
与现有技术相比，本发明技术方案具有以下优点：
本发明的半导体结构，包括：存储芯片；温度检测单元，用于在存储芯片启动之前检测存储芯片的温度；控制芯片，用于在存储芯片启动之前对存储芯片进行加热，并判断所述温度检测单元检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片启动。通过控制芯片和温度检测单元的配合，所述控制芯片在存储芯片启动之前对存储芯片进行加热，所述温度检测单元在 存储芯片启动之前检测存储芯片的温度，所述控制芯片判断所述温度检测单元检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片启动，因而当本发明的半导体结构工作在低温环境时，通过控制芯片可以使得存储芯片升温到设定阈值，从而可以防止存储芯片中的位线、字线、以及金属连线(金属接触部)由于环境温度过低带来的电阻的增大，从而减小了低温环境下的对存储器进行数据写入时的写入时间，提高了存储器写入的稳定性。
进一步，所述温度检测单元的数量为1个，具体的，所述1个温度精测单元可以位于控制芯片中，或者所述1个温度检测单元也可以位于存储芯片中，或者所述1个温度检测单元也可以位于存储芯片和控制芯片之间的线路基板上，所述控制芯片判断所述1个温度检测单元检测的温度达到设定阈值时，则控制所有所述存储芯片启动。对于半导体结构存在多个存储芯片时，前述的这种控制结构和控制方式相对简单，并能减小低温环境下的对存储芯片进行数据写入时的写入时间，提高了存储芯片写入的稳定性。
进一步，所述温度检测单元数量为1个，且所述存储芯片的数量为大于等于2个时，所述控制芯片判断所述1个温度检测单元的温度达到设定阈值时，先控制离所述控制芯片最近的存储芯片启动，然后再控制上面的其他存储芯片依次启动。对于半导体结构存在多个存储芯片时，前述的这种控制结构和控制方式能使得每一个存储芯片均能在达到设定阈值温度后启动，提高了每一个存储芯片启动时机的精度，并能减小低温环境下的对每一个存储芯片进行数据写入时的写入时间，提高了对每一个存储芯片写入的稳定性。
进一步，所述温度检测单元数量为大于等于2个时，且所述存储芯片的数量大于等于2个时，每一个存储芯片中具有一个温度检测单元，所述控制芯片依次判断所有的所述温度检测单元检测的温度是否达到设定阈值时，若某一个温度检测单元检测的温度达到设定阈值，则控制该温度检测单元对应的存储芯片启动。对于半导体结构存在多个存储芯片时，前述的这种控制结构和控制方式能使得每一个存储芯片每一个存储芯片启动时机的精度进一步提高，并能进一步减小低温环境下的对每一个存储芯片进行数据写入时的写入时间，进一步提高了对每一个存储芯片写入的稳定性。
进一步，所述控制芯片对所述存储芯片进行加热之前，所述控制芯片先进 行启动，所述控制芯片利用启动后自生产生的热量对存储芯片进行加热，无需额外的加热电路，从而简化了半导体结构的结构。
进一步，所述控制芯片中可以具有额外的加热电路，用于对所述存储芯片进行加热。所述控制芯片在对所述存储芯片进行加热之前或之后，所述控制芯片判断所述温度检测单元检测的存储芯片的温度是否达到设定阈值，若未达到设定阈值，则控制所述加热电路对存储芯片进行加热，如达到设定阈值，则控制所述加热电路停止对存储芯片进行加热。从而实现对加热过程的精确控制，使得存储芯片的温度能保持在设定阈值附近，防止存储芯片的温度过高或过低，从而使得对存储器的写入时间始终能保持较短。
本发明对半导体结构进行预热的方法，在存储芯片未启动之前，通过控制芯片对未启动的存储芯片进行加热；通过温度检测单元检测所述存储芯片的温度；通过控制芯片判断所述温度检测单元检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片启动。因而当本发明的半导体结构工作在低温环境时，通过控制芯片可以使得存储芯片升温到设定阈值，从而可以防止存储芯片中的位线、字线、以及金属连线(金属接触部)由于环境温度过低带来的电阻的增大，从而减小了低温环境下的对存储器进行数据写入时的写入时间，提高了存储器写入的稳定性。
附图说明
图1-7为本发明实施例中半导体结构的结构示意图；
图8为本发明实施例中半导体结构预热方法的流程示意图。
具体实施方式
如背景技术所言，现有在低温环境中对存储器进行写入时，存在写入时间较长，写入的稳定性仍需要提高的问题。
研究发现，现有的存储器工作在低温环境中时，由于温度下降会使得存储器中的位线、字线、以及金属连线(金属接触部)等的电阻会增大，电阻的增大，会使得向存储器中写入数据时的时间会变化或加长，影响了存储器写入的稳定性。
为此，本发明提供了一种半导体结构及其预热方法，其中所述半导体结构包括：存储芯片；温度检测单元，用于在存储芯片启动之前检测存储芯片的温 度；控制芯片，用于在存储芯片启动之前对存储芯片进行加热，并判断所述温度检测单元检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片启动。通过控制芯片和温度检测单元的配合，所述控制芯片在存储芯片启动之前对存储芯片进行加热，所述温度检测单元在存储芯片启动之前检测存储芯片的温度，所述控制芯片判断所述温度检测单元检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片启动，因而当本发明的半导体结构工作在低温环境时，通过控制芯片可以使得存储芯片升温到设定阈值，从而可以防止存储芯片中的位线、字线、以及金属连线(金属接触部)由于环境温度过低带来的电阻的增大，从而减小了低温环境下的对存储器进行数据写入时的写入时间，提高了存储器写入的稳定性。
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。在详述本发明实施例时，为便于说明，示意图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明的保护范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
图1-7为本发明实施例中半导体结构的结构示意图；图8为本发明实施例中半导体结构预热方法的流程示意图。
参考图1，本发明实施例提供了一种半导体结构，包括：
存储芯片201；
温度检测单元203，用于在存储芯片201启动之前检测存储芯片201的温度；
控制芯片301，用于在存储芯片201启动之前对存储芯片201进行加热，并判断所述温度检测单元203检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片201启动。
所述存储芯片201为现有能进行数据写入、数据读取和/或数据删除的的存储器，所述存储芯片201通过半导体集成制作工艺形成，具体的所述存储芯片201可以包括存储阵列和与存储阵列连接的外围电路，所述存储阵列包括若干存储单元和与存储单元连接的位线、字线、以及金属连线(金属接触部)，所述存储单元用于存储数据，所述外围电路为在对存储阵列进行操作时的相关 电路。本实施例中，所述存储芯片201为DRAM存储芯片，所述DRAM存储芯片中包括若干存储单元，所述存储单元通常包括电容器和晶体管，所述晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连。在其他实施例中所述存储芯片201可以为其他类型的存储芯片。
所述存储芯片201的数量至少为一个，具体的，所述存储芯片201的数量可以为1个或者大于等于2个。当所述存储芯片的数量大于等于2个时，若干存储芯片依次向上堆叠形成存储芯片堆叠结构。本实施例中，请参考图2，以所述存储芯片201的数量为4个作为示例，所述4个存储芯片201从下向上依次堆叠形成存储芯片堆叠结构，相邻存储芯片201通过键合工艺或者粘合工艺贴合在一起。在一实施例中，所述存储芯片201中形成有硅通孔互连结构(TSV)，通过硅通孔互连结构(TSV)将存储芯片201与控制芯片301进行电连接。当存在多个存储芯片201堆叠时，每一个存储芯片201可以通过不同的硅通孔互连结构(TSV)与控制芯片201连接。在其他实施例中，所述存储芯片201还可以通过金属引线(通过引线键合工艺形成)与所述控制芯片301连接。
本实施例中，所述存储芯片201位于控制芯片301上，所述存储芯片201与所述控制芯片301电连接。具体的，当只有一个存储芯片201时，所述控制芯片301与该存储芯片201键合在一起，当有多个存储芯片201形成存储芯片堆叠结构时，所述控制芯片301与堆叠结构中最底层的存储芯片201键合在一起。
在其他实施例中，所述存储芯片201和控制芯片301可以采用不同的连接方式，请参考图4(或者参考图4-图7)，所述半导体结构还包括线路基板401，所述线路基板401中具有连接线路，所述存储芯片201以及控制芯片301均位于线路基板104上，所述存储芯片201和控制芯片301通过线路基板104中的连接线路连接，具体的所述线路基本401可以为PCB基板。
参考图1或图4，所述控制芯片301通过半导体集成制作工艺形成。所述控制芯片301能用于对所述存储芯片201进行加热，以使得存储芯片201的温度能够达到设定阈值(所述设定阈值可以设定在控制芯片301中，设定阈值的具体大小可以根据实际需要或者经验进行设定)，所述控制芯片301还用于控 制存储芯片201的启动(存储芯片的启动包括上电以及自检测)以及对存储芯片201进行相关的操作(所述相关操作包括向存储芯片201中写入数据，从存储芯片201读取数据，以及将存储芯片201中存取的数据删除等)。
所述半导体结构还包括温度检测单元203，所述温度检测单元203用于在存储芯片201启动之前测量所述存储芯片201的温度，所述温度检测单元203与控制芯片301电连接，所述温度检测单元203检测的温度传送给控制芯片，所述温度检测单元203测量的温度作为控制芯片301控制所述存储芯片201启动的依据。具体的，通过控制芯片301和温度检测单元203的配合，所述控制芯片301在存储芯片201启动之前对存储芯片201进行加热，所述温度检测单元203在存储芯片201启动之前检测存储芯片201的温度，所述控制芯片30判断所述温度检测单元203检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片201启动，因而当本发明的半导体结构工作在低温环境时，通过控制芯片301可以使得存储芯片201升温到设定阈值，从而可以防止存储芯片中的位线、字线、以及金属连线(金属接触部)由于环境温度过低带来的电阻的增大，从而减小了低温环境下的对存储器进行数据写入时的写入时间，提高了存储器写入的稳定性。
所述温度检测单元203中包括温度传感器，所述温度传感器用于感应温度，将感应的温度转化为电信号。在具体的实施例中，所述温度传感器为PN结温度传感器或者电容式温度传感器，所述温度传感器可以通过半导体集成制作工艺形成在存储芯片201中或者控制芯片301中，或者位于存储芯片201和控制芯片301之间的线路基板104(参考图5)上
所述温度检测单元203的数量可以为1个或者大于等于2个，所述温度检测单元203可以位于控制芯片301中或者位于存储芯片201中。
在一实施例中，所述温度检测单元203的数量为1个，具体的，所述1个温度精测单元203可以位于控制芯片203中(参考图1或图4)，或者所述1个温度检测单元203也可以位于存储芯片201中(当只有一个存储芯片201中，所述一个温度检测单元203直接位于该存储芯片201中；当多个存储芯片201形成堆叠结构时，所述一个温度检测单元203位于其中一个存储芯片201，优选的位于堆叠结构中最底层的存储芯片201中(参考图2或图6))，或者所述 1个温度检测单元203也可以位于存储芯片201和控制芯片301之间的线路基板104(参考图5)上，所述控制芯片301判断所述1个温度检测单元检测的温度达到设定阈值时，则控制所有所述存储芯片201启动。对于半导体结构存在多个存储芯片201时，前述的这种控制结构和控制方式相对简单，并能减小低温环境下的对存储芯片进行数据写入时的写入时间，提高了存储芯片写入的稳定性。
在另一实施例中，参考图1(或者图2，或者图4-图6)，所述温度检测单元203数量为1个，且所述存储芯片201的数量为大于等于2个时，所述控制芯片301判断所述1个温度检测单元的温度达到设定阈值时，先控制离所述控制芯片301最近的存储芯片201启动，然后再控制上面的其他存储芯片201依次启动。具体的，参考图2，当存在4个存储芯片201时，所述控制芯片301判断所述1个温度检测单元的温度达到设定阈值时，先控制离所述控制芯片301最近的存储芯片201(堆叠结构中最底层的一个存储芯片)启动，然后再控制上面的其他3个存储芯片201依次启动。对于半导体结构存在多个存储芯片201时，前述的这种控制结构和控制方式能使得每一个存储芯片201均能在达到设定阈值温度后启动，提高了每一个存储芯片201启动时机的精度，并能减小低温环境下的对每一个存储芯片进行数据写入时的写入时间，提高了对每一个存储芯片写入的稳定性。
在另一实施例中，参考图3(或者图7)，所述温度检测单元203数量为大于等于2个时，且所述存储芯片201的数量大于等于2个时，每一个存储芯片201中具有一个温度检测单元203，所述控制芯片301依次判断所有的所述温度检测单元203检测的温度是否达到设定阈值时，若某一个温度检测单元203检测的温度达到设定阈值，则控制该温度检测单元203对应的存储芯片启动。具体的图3(或者图7)所示的堆叠结构中有4个存储芯片201，每一个存储芯片201中对应具有一个温度检测单元203，因而每一个温度检测单元203会对对应的存储芯片201的温度进行检测，获得四个温度检测值，所述控制单片301会依次判断4个所述温度检测单元203检测的温度是否达到设定阈值时，若某一个温度检测单元203检测的温度达到设定阈值，则控制该温度检测单元203对应的存储芯片启动，比如堆叠结构中最底层的存储芯片201中的温度检测单 元203检测的温度先达到设定阈值时，则控制芯片301先控制所述堆叠结构最底层的那一个存储芯片201启动，接着，堆叠结构中倒数第二层中那个存储芯片201中对应的温度检测单元203检测的温度也达到设定阈值时，则控制单元301接着控制堆叠结构中倒数第二层的那个存储芯片201启动，上面两层的存储芯片201的启动以此类推。对于半导体结构存在多个存储芯片201时，前述的这种控制结构和控制方式能使得每一个存储芯片201每一个存储芯片201启动时机的精度进一步提高，并能进一步减小低温环境下的对每一个存储芯片进行数据写入时的写入时间，进一步提高了对每一个存储芯片写入的稳定性。
在一实施例中，所述控制芯片301对所述存储芯片201进行加热之前，所述控制芯片301需要先进行启动，比如对控制芯片301上电以及自检测，控制芯片301启动时，控制芯片301不会给存储芯片201下达指令，只有当所述温度检测单元检测的温度是达到设定阈值值，所述控制芯片301才会控制所述存储芯片201启动，所述控制芯片301利用启动后自生产生的热量对存储芯片进行加热，因而无需额外的加热电路，从而简化了半导体结构的结构。
在一实施例中，所述控制芯片301控制所述存储芯片201启动后，所述控制芯片301还控制所述存储芯片201进行写入、读取和擦除操作。具体的，所述控制芯片301中具有控制电路，所述控制电路用于控制所述存储芯片201启动并控制所述存储芯片201进行写入、读取和擦除操作。
在另一实施例中，所述控制芯片301中可以具有额外的加热电路，用于对所述存储芯片201进行加热。所述控制芯片301在对所述存储芯片201进行加热之前或之后，所述控制芯片判断所述温度检测单元检测的存储芯片的温度是否达到设定阈值，若未达到设定阈值，则控制所述加热电路对存储芯片进行加热，如达到设定阈值，则控制所述加热电路停止对存储芯片进行加热。从而实现对加热过程的精确控制，使得存储芯片201的温度能保持在设定阈值附近，防止存储芯片201的温度过高或过低，从而使得对存储器的写入时间始终能保持较短。
参考图8，本发明还提供了一种对半导体结构进行预热的方法，包括步骤：
步骤S101，提供半导体结构，所述半导体结构包括存储芯片，与所述存储芯片电连接的控制芯片，以及温度检测单元；
步骤S102，启动控制芯片；
步骤S103，通过控制芯片对未启动的存储芯片进行加热；
步骤S104，通过温度检测单元检测所述存储芯片的温度；
步骤S105，通过控制芯片判断所述温度检测单元检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片启动。
具体的，所述温度检测单元的数量为1个或者大于等于2个，所述存储芯片的数量为1个或大于等于2个，所述存储芯片大于等于2个时，若干存储芯片依次向上堆叠。
在一实施例中，所述温度检测单元数量为1个时，所述控制芯片判断所述1个温度检测单元检测的温度达到设定阈值时，则控制所有所述存储芯片启动。
在一实施例中，所述温度检测单元数量为1个，且所述存储芯片的数量为大于等于2个时，所述控制芯片判断所述1个温度检测单元的温度达到设定阈值时，先控制离所述控制芯片最近的存储芯片启动，然后再控制上面的其他存储芯片依次启动。
在一实施例中，所述温度检测单元数量为大于等于2个时，且所述存储芯片的数量大于等于2个时，每一个存储芯片中具有一个温度检测单元，所述控制芯片依次判断所有的所述温度检测单元检测的温度是否达到设定阈值时，若某一个温度检测单元检测的温度达到设定阈值，则控制该温度检测单元对应的存储芯片启动。
在一实施例中，所述控制芯片控制所述存储芯片启动后，所述控制芯片还控制所述存储芯片进行写入、读取和擦除操作。
需要说明的是，本实施例与前述实施例中相同或者相似部分的限定或描述在本实施例中不再赘述，具体请参考前述半导体结构实施例中的相应部分的限定或描述。
本发明虽然已以较佳实施例公开如上，但其并不是用来限定本发明，任何本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法和技术内容对本发明技术方案做出可能的变动和修改，因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化及修饰，均属于本发明技术方案的保护范围。

Claims (19)

  1. 一种半导体结构，其特征在于，包括：
    存储芯片；
    温度检测单元，用于在存储芯片启动之前检测存储芯片的温度；
    控制芯片，用于在存储芯片启动之前对存储芯片进行加热，并判断所述温度检测单元检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片启动。
  2. 如权利要求1所述的半导体结构，其特征在于，所述存储芯片的数量为1个或者大于等于2个，所述存储芯片的数量大于等于2个时，若干存储芯片依次向上堆叠。
  3. 如权利要求2所述的半导体结构，其特征在于，所述存储芯片位于控制芯片上，所述存储芯片与所述控制芯片电连接。
  4. 如权利要求2所述的半导体结构，其特征在于，还包括线路基板，所述线路基板中具有连接线路，所述存储芯片以及控制芯片均位于线路基板上，所述存储芯片和控制芯片通过线路基板中的连接线路连接。
  5. 如权利要求3或4所述的半导体结构，其特征在于，所述温度检测单元与所述控制芯片电连接，所述温度检测单元的数量为1个或者大于等于2个，所述温度检测单元位于控制芯片中或者位于存储芯片中，或者位于存储芯片和控制芯片之间的线路基板上。
  6. 如权利要求5所述的半导体结构，其特征在于，所述温度检测单元数量为1个时，所述控制芯片判断所述1个温度检测单元检测的温度达到设定阈值时，则控制所有所述存储芯片启动。
  7. 如权利要求5所述的半导体结构，其特征在于，所述温度检测单元数量为1个，且所述存储芯片的数量为大于等于2个时，所述控制芯片判断所述1个温度检测单元的温度达到设定阈值时，先控制离所述控制芯片最近的存储芯片启动，然后再控制上面的其他存储芯片依次启动。
  8. 如权利要求5所述的半导体结构，其特征在于，所述温度检测单元数量为大于等于2个时，且所述存储芯片的数量大于等于2个时，每一个存储芯片中具有一个温度检测单元，所述控制芯片依次判断所有的所述温度检测 单元检测的温度是否达到设定阈值时，若某一个温度检测单元检测的温度达到设定阈值，则控制该温度检测单元对应的存储芯片启动。
  9. 如权利要求1所述的半导体结构，其特征在于，所述控制芯片控制所述存储芯片启动后，所述控制芯片还控制所述存储芯片进行写入、读取和擦除操作。
  10. 如权利要求9所述的半导体结构，其特征在于，所述控制芯片对所述存储芯片进行加热之前，所述控制芯片先进行启动，所述控制芯片利用启动后自生产生的热量对存储芯片进行加热。
  11. 如权利要求1所述的半导体结构，其特征在于，所述控制芯片中具有额外的加热电路，用于对所述存储芯片进行加热。
  12. 如权利要求11所述的半导体结构，其特征在于，所述控制芯片在对所述存储芯片进行加热之前或之后，所述控制芯片判断所述温度检测单元检测的存储芯片的温度是否达到设定阈值，若未达到设定阈值，则控制所述加热电路对存储芯片进行加热，如达到设定阈值，则控制所述加热电路停止对存储芯片进行加热。
  13. 如权利要求1所述的半导体结构，其特征在于，所述存储芯片为DRAM芯片。
  14. 一种对半导体结构进行预热的方法，其特征在于，包括：
    提供半导体结构，所述半导体结构包括存储芯片，与所述存储芯片电连接的控制芯片，以及温度检测单元；
    启动控制芯片；
    通过控制芯片对未启动的存储芯片进行加热；
    通过温度检测单元检测所述存储芯片的温度；
    通过控制芯片判断所述温度检测单元检测的温度是否达到设定阈值，若达到设定阈值，则控制所述存储芯片启动。
  15. 如权利要求14所述的预热的方法，其特征在于，所述温度检测单元的数量为1个或者大于等于2个，所述存储芯片的数量为1个或大于等于2个，所述存储芯片大于等于2个时，若干存储芯片依次向上堆叠。
  16. 如权利要求15所述的预热的方法，其特征在于，所述温度检测单元数量为1个时，所述控制芯片判断所述1个温度检测单元检测的温度达到设定阈值时，则控制所有所述存储芯片启动。
  17. 如权利要求15所述的预热的方法，其特征在于，所述温度检测单元数量为1个，且所述存储芯片的数量为大于等于2个时，所述控制芯片判断所述1个温度检测单元的温度达到设定阈值时，先控制离所述控制芯片最近的存储芯片启动，然后再控制上面的其他存储芯片依次启动。
  18. 如权利要求15所述的预热的方法，其特征在于，所述温度检测单元数量为大于等于2个时，且所述存储芯片的数量大于等于2个时，每一个存储芯片中具有一个温度检测单元，所述控制芯片依次判断所有的所述温度检测单元检测的温度是否达到设定阈值时，若某一个温度检测单元检测的温度达到设定阈值，则控制该温度检测单元对应的存储芯片启动。
  19. 如权利要求14所述的预热的方法，其特征在于，所述控制芯片控制所述存储芯片启动后，所述控制芯片还控制所述存储芯片进行写入、读取和擦除操作。
PCT/CN2020/131414 2020-03-25 2020-11-25 半导体结构及其预热方法 Ceased WO2021189887A1 (zh)

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