WO2021190409A1 - 像素驱动电路、显示面板及电子设备 - Google Patents

像素驱动电路、显示面板及电子设备 Download PDF

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Publication number
WO2021190409A1
WO2021190409A1 PCT/CN2021/081767 CN2021081767W WO2021190409A1 WO 2021190409 A1 WO2021190409 A1 WO 2021190409A1 CN 2021081767 W CN2021081767 W CN 2021081767W WO 2021190409 A1 WO2021190409 A1 WO 2021190409A1
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Prior art keywords
circuit
pixel
line
type data
data line
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PCT/CN2021/081767
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English (en)
French (fr)
Inventor
陈彩琴
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Vivo Mobile Communication Co Ltd
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Vivo Mobile Communication Co Ltd
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Application filed by Vivo Mobile Communication Co Ltd filed Critical Vivo Mobile Communication Co Ltd
Priority to EP21774254.3A priority Critical patent/EP4131229A4/en
Priority to JP2022557878A priority patent/JP7489482B2/ja
Priority to KR1020227036597A priority patent/KR102718977B1/ko
Publication of WO2021190409A1 publication Critical patent/WO2021190409A1/zh
Priority to US17/951,198 priority patent/US11961472B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Definitions

  • This application relates to the field of display technology, and in particular to a pixel drive circuit, a display panel, and an electronic device.
  • each pixel circuit includes multiple Thin Film Transistor (TFT) drive switches and an Organic Light-Emitting Diode (Organic Light-Emitting Diode) display circuit.
  • TFT Thin Film Transistor
  • Organic Light-Emitting Diode Organic Light-Emitting Diode
  • Emitting Diode, OLED usually adopts 7T1C (7 TFT transistors and 1 capacitor) pixel compensation circuit, and drive circuit to drive and light up each display device unit.
  • 7T1C drive circuit input signal includes: OLED light-emitting control signal (Emission, EM), Scan[n], Scan[n-1], Vini (initial reset signal), Vdata (data signal), Vdd (high signal);
  • the drive circuit usually includes Scan GOA (Gate Driver On Array, array substrate row drive scanning circuit) circuit and EM array substrate row drive circuit (Emit Gate Driver On Array, EM GOA), used in Scan GOA and EM GOA (EOA) circuits CK (clock signal) ⁇ XCK (external clock signal) ⁇ VGL (low potential) ⁇ VGH (high potential) ⁇ STV (initial signal) and other input signals, after passing through the sequential circuit MOS switch unit (multiple TFTs and multiple capacitors) ), the drive timing of each row after the output stage is passed to the pixel circuit in the display area, as shown in Figure 1.
  • RGBG pixel arrangement is usually used (every two pixels share a green sub-pixel, which makes the area of blue OLED larger, and at the same time brings a higher panel aperture ratio, so that This reduces the current required to achieve a considerable luminous intensity, thereby delaying the attenuation speed and increasing the life of the display panel).
  • this arrangement has 2 display colors on a column of pixels.
  • the GOA integrated circuit is prone to waveform delay caused by R (resistance) and C (capacitance) during the stage transfer process, and the scanning signal Gate output waveform delay occurs, and the Vdata voltage of the pixel circuit unit is written In the process of the stage, it is easy to write the Vdata voltage of the previous frame, resulting in a pure color display color shift, for example, the red screen is bluish, and the blue screen is reddish.
  • the embodiments of the present application provide a pixel driving circuit, a display panel, and an electronic device to solve the problem of the color shift of the pure color display caused by the delay of the output waveform in the prior art.
  • an embodiment of the present application provides a pixel driving circuit, including:
  • At least four gate lines are arranged along the first direction of the pixel array, a row of pixel circuits is arranged between two adjacent gate lines, and each row of pixel circuits corresponds to one gate line;
  • At least eight data lines arranged along a second direction perpendicular to the first direction and intersecting each gate line, each data line being connected to the pixel circuits corresponding to the same color sub-pixels in a column of pixel circuits; as well as
  • a demultiplexer circuit connected to the data line, and the demultiplexer circuit is used to control the data line to communicate with an integrated circuit IC chip.
  • an embodiment of the present application provides a display panel including the above-mentioned pixel driving circuit.
  • an embodiment of the present application provides an electronic device including the above-mentioned display panel.
  • the sub-pixels of the same color in the unit column are inputted by the same data line to input the data signal, so that the pure color screen will not cause Wrong writing of signals of different colors in the previous frame caused color shift, which ensures the consistency of the picture display and improves the color shift of the display panel.
  • Figure 1 shows a schematic diagram of a prior art AMOLED display panel driving architecture
  • FIG. 2 shows a schematic diagram of a pixel driving circuit according to an embodiment of the present application
  • Figure 3 shows a schematic diagram of the arrangement of RGBG pixels
  • Figure 4 shows a sequence diagram of an embodiment of the present application
  • FIG. 5 shows a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present application.
  • An embodiment of the present application provides a pixel driving circuit, as shown in FIG. 2, including:
  • At least four gate lines 2 are arranged along the first direction of the pixel array, a row of pixel circuits 1 is arranged between two adjacent gate lines 2, and each row of pixel circuits 1 corresponds to one gate line 2;
  • At least eight data lines 3 arranged in a second direction perpendicular to the first direction and intersecting each gate line 2, and each data line 3 corresponds to the sub-pixels of the same color in a column of pixel circuits 1 Pixel circuit 1 is connected;
  • the pixel driving circuit provided by the embodiment of the present invention includes a pixel array located in a display area, at least four gate lines 2 and at least eight data lines 3 arranged in the pixel array, and a demultiplexer circuit 4 arranged in a non-display area.
  • the pixel array adopts RGBG pixel arrangement, and the RGBG pixel arrangement can be seen in Figure 3.
  • the pixel array includes a plurality of pixel circuits 1 arranged in an array manner, each pixel circuit 1 and a corresponding organic light emitting diode form a pixel unit, and the plurality of pixel units form a pixel array.
  • At least four gate lines 2 are arranged along the first direction of the pixel array, a row of pixel circuits 1 is arranged between two adjacent gate lines 2, and each row of pixel circuits 1 corresponds to one gate line 2.
  • At least eight data lines 3 are sequentially arranged along the second direction, and form a form of intersecting each gate line 2.
  • Each data line 3 is connected to the pixel circuits 1 corresponding to the same color sub-pixels in a column of pixel circuits 1, which can ensure the consistency of the picture display and improve the problem of the color shift of the display panel.
  • Each data line 3 is connected to the demultiplexer circuit 4, through the demultiplexer circuit 4, the data line 3 can be connected to an integrated circuit (IC) chip, so that the data line 3 can control the pixel circuit 1 connected to it.
  • IC integrated circuit
  • the sub-pixels of the same color in the unit column use the same data line to input data signals, which ensures the display of the screen. Consistency improves the color cast problem of the display panel.
  • the pixel driving circuit further includes:
  • the array substrate row connected to the output terminal of the IC chip drives the GOA unit 5;
  • the GOA unit 5 includes a first clock signal line 51, a second clock signal line 52, a third clock signal line 53, and a fourth clock signal line 54 and a plurality of first GOA circuits 55 connected to odd-numbered rows of gate lines 2 and a plurality of second GOA circuits 56 connected to even-numbered rows of gate lines 2;
  • the first GOA circuit 55 is connected to the first clock signal line 51 and the second clock signal line 52, and the second GOA circuit 56 is connected to the third clock signal line 53 and the fourth clock signal line 54;
  • the timings of the first clock signal line 51 and the second clock signal line 52 are opposite, and the timings of the third clock signal line 53 and the fourth clock signal line 54 are opposite.
  • the GOA unit 5 is connected to the output terminal of the IC chip and includes four clock signal lines. Two additional clock signal lines are added to the original circuit. It also includes a plurality of first GOA circuits 55 and a plurality of second GOA circuits 56.
  • the number of GOA circuits 55 is equal to the number of odd rows of gate lines 2 in the pixel array
  • the number of second GOA circuits 56 is equal to the number of even rows of gate lines 2 in the pixel array, that is, each odd row of gate lines 2 corresponds to A first GOA circuit 55, and each gate line 2 of an even-numbered row corresponds to a second GOA circuit 56.
  • the timings of the first clock signal line 51 and the second clock signal line 52 are opposite, and the first clock signal line 51 and the second clock signal line 52 are used as input signal lines to be connected to each first GOA circuit 55 for The first GOA circuit 55 inputs a clock signal.
  • the timings of the third clock signal line 53 and the fourth clock signal line 54 are reversed, and the third clock signal line 53 and the fourth clock signal line 54 are used as input signal lines to be connected to each second GOA circuit 56 for connecting to each second GOA circuit.
  • the GOA circuit 56 inputs a clock signal.
  • the GOA unit 5 since the GOA unit 5 is connected to the output terminal of the IC chip, the specific connection form is: the first clock signal line 51 is connected to the first clock port of the IC chip output terminal, and the second clock signal line 52 is connected to the first clock port of the IC chip output terminal.
  • the second clock port is connected, the third clock signal line 53 is connected to the third clock port of the output end of the IC chip, and the fourth clock signal line 54 is connected to the fourth clock port of the output end of the IC chip; the first GOA circuit corresponding to the odd row gate line 2 55.
  • the second GOA circuits 56 corresponding to the even rows of gate lines 2 are respectively connected to different driving ports of the output terminals of the IC chip.
  • the adjacent first GOA circuits 55 are connected to each other and form a stage transmission of odd rows of gate lines 2
  • the adjacent second GOA circuits 56 are connected to each other and form a stage transmission of even-numbered rows of gate lines 2;
  • the output terminal of the first GOA circuit 55 of each stage is connected to the input terminal of the first GOA circuit 55 of the next next stage; except for the last stage In addition to the second GOA circuit 56, the output terminal of the second GOA circuit 56 of each stage is connected to the input terminal of the second GOA circuit 56 of the adjacent next stage.
  • the connection between the first GOA circuit 55 of the previous stage and the first GOA circuit 55 of the subsequent stage is realized, and then A stage pass of odd-numbered rows of gate lines 2 is formed.
  • the connection between the second GOA circuit 56 of the previous stage and the second GOA circuit 56 of the subsequent stage is realized. Connect, and then form the even-numbered row of the gate line 2 level transmission.
  • the output terminal of the first GOA circuit 55 connected to the gate line 2 of the first row is connected to the input terminal of the first GOA circuit 55 connected to the gate line 2 of the third row, and the first GOA circuit 55 connected to the gate line 2 of the third row is connected.
  • the output terminal of the GOA circuit 55 is connected to the input terminal of the first GOA circuit 55 connected to the fifth row of gate lines 2; the output terminal of the second GOA circuit 56 connected to the second row of gate lines 2 is connected to the fourth row of gate lines 2
  • the input end of the connected second GOA circuit 56 is connected, and the output end of the second GOA circuit 56 connected to the fourth row of gate lines 2 is connected to the input end of the second GOA circuit 56 connected to the sixth row of gate lines 2.
  • the odd-numbered row-level transmission can be made to correspond to the first clock signal line and the second clock signal line
  • the even-numbered row-level transmission corresponds to the third clock signal line and the fourth clock signal.
  • the miswriting of data signals of different colors caused by time delay can be improved, thereby improving the color shift of the panel.
  • the pixel array shown in FIG. 2 is a minimum driving unit, and a plurality of minimum driving units can be combined into a driving circuit corresponding to the display panel. For example, for the display panel corresponding to 1080 columns and 2400 rows of pixel circuits, 270 minimum drive units are required in the column direction and 600 minimum drive units are required in the row direction.
  • the waveform corresponding to the first clock signal line (CK1) is the superposition of the waveform of the first grid line (the first row of grid lines) and the inverse waveform of the third grid line (the third row of grid lines)
  • the second clock signal line (XCK1) has the opposite waveform to the first clock signal line
  • the waveform corresponding to the third clock signal line (CK2) is the waveform of the second gate line (the second row of gate lines) and the first The waveform generated by superimposing the inverse waveforms of the four gate lines (the fourth row of gate lines).
  • the fourth clock signal line (XCK2) and the third clock signal line have opposite waveforms
  • the third clock signal line (CK2) is opposite to the first The clock signal line (CK1) is delayed by half a pulse.
  • the second GOA circuit corresponding to the even-numbered row gate line 2 is provided for the adjacent odd-numbered row gate line 2 and even-numbered row gate line 2
  • the clock signal of 56 is delayed by half a pulse of the clock signal of the first GOA circuit 55 corresponding to the odd-numbered row gate line 2, and can be coordinated with the data line 3 to realize that in a continuous period of time, the pixel circuit 1 corresponding to each column can be controlled
  • the pixel circuits 1 of the same color sub-pixels work in sequence according to the pulse signal.
  • the data line 3 includes a first type data line 31, a second type data line 32, and a third type data line 33;
  • Each column of pixel circuits 1 is a circuit group, the circuit group corresponding to the same color sub-pixels is the first circuit group, and the circuit group corresponding to the two color sub-pixels is the second circuit group;
  • the first type data line 31 is connected to the pixel circuit 1 corresponding to the first color sub-pixel in the second circuit group, and the second type data line 32 corresponds to the second color in the second circuit group
  • the pixel circuit 1 of the sub-pixel is connected; the third type data line 33 is connected to the pixel circuit 1 in the first circuit group.
  • the data lines 3 arranged along the second direction correspond to three types, and each type of data line 3 can be respectively connected to the corresponding pixel circuit 1 and control the working state of the pixel circuit 1.
  • a circuit group can be formed for each column of pixel circuits 1, and the circuit group can be determined as two different types of circuit groups according to different sub-pixels corresponding to the circuit group. If the pixel circuits 1 in the circuit group correspond to the same color sub-pixels, the circuit group is the first circuit group, and if the pixel circuits 1 in the circuit group correspond to two color sub-pixels, the circuit group is the second circuit group.
  • the data line 3 it is determined that the data line 3 connected to the pixel circuit 1 in the first circuit group is the third type data line 33, and the data line 3 connected to the pixel circuit 1 corresponding to the first color sub-pixel in the second circuit group is determined.
  • the data line 3 is a first type data line 31, and it is determined that the data line 3 connected to the pixel circuit 1 corresponding to the second color sub-pixel in the second circuit group is the second type data line 32.
  • the pixel circuit 1 in the first circuit group corresponds to the green sub-pixel
  • the first color sub-pixel can be red or blue sub-pixel
  • the corresponding second-color sub-pixel can be blue or Red sub pixel.
  • the sum of the number of the first type data line 31, the second type data line 32, and the third type data line 33 is determined by
  • the pixel circuit 1 corresponds to twice the number of columns; the first type data line 31, the second type data line 32, the two third type data lines 33, and the second type data line 32.
  • the first type data line 31 and the two third type data lines 33 are sequentially arranged in the second direction; wherein, each third type data line 33 is connected to the first circuit group Half of the pixel circuits 1 are connected, and at least two of the pixel circuits 1 connected to one third-type data line 33 are arranged adjacently or spaced apart.
  • the two data lines 3 are respectively a first type data line 31 and a second type data line 32 ;
  • the two data lines 3 are the third type data lines 33. Therefore, the sum of the numbers of the first type data lines 31, the second type data lines 32, and the third type data lines 33 is twice the number of circuit groups.
  • the first type data line 31, the second type data line 32, the two third type data lines 33, the second type data line 32, the first type data line 31, and the two third type data lines 33 are in the second direction Arranged on top.
  • the data lines D1, D1-1, D2, D2-1, D3, D3-1, D4, and D4-1 are arranged in sequence in the second direction.
  • the pixel circuit 1 corresponding to the R (red) sub-pixel in the first column of pixel circuits 1 is driven by D1 (first type data line), and the pixel circuit 1 corresponding to the B (blue) sub-pixel in the first column of pixel circuits 1 Driven by D1-1 (the second type data line); similarly, the pixel circuit 1 corresponding to the B sub-pixel in the third column of pixel circuit 1 is driven by D3 (the second type data line), and the third column of pixel circuit 1 and
  • the pixel circuit 1 corresponding to the R sub-pixel is driven by D3-1 (first type data line); the pixel circuit 1 corresponding to the G (green) sub-pixel in the second column of pixel circuit 1 also uses odd rows and even rows with D2 ( The third type data line) and D2-1 (the third type data line) are driven, and the driving mode
  • each third type data line 33 is connected to half of the pixel circuits 1 in the first circuit group, and may be connected to adjacent or spaced pixel circuits 1. Since there are at least four pixel circuits 1 in the first circuit group, at least two pixel circuits 1 connected to one third-type data line 33 may be arranged adjacently or spaced apart. Shown in FIG. 2 is an example in which one third-type data line 33 is connected to two spaced apart pixel circuits 1.
  • the demultiplexer circuit 4 includes:
  • the first driving line 41 and the second driving line 42 are connected to the output terminal of the IC chip;
  • the first type data line 31 and one of the third type data lines 33 in each of the first circuit groups correspond to the first switch 43, the second type data line 32 and each of the first circuit groups
  • the other third type data line 33 in the circuit group corresponds to the second switch 44;
  • the control end of the first switch 43 is connected to the first drive line 41, and is used to connect the first type data line 31 and the corresponding port data line, half of all data lines under the control of the first drive line 41.
  • the control end of the second switch 44 is connected to the second drive line 42 for connecting the second type data line 32 and the corresponding port data line, and the remaining half of the data line under the control of the second drive line 42
  • each of the port data lines is connected to the output terminal of the IC chip.
  • the first driving line 41 and the second driving line 42 included in the demultiplexer circuit 4 are respectively connected to different driving ports of the output terminal of the IC chip, and the timings of the first driving line 41 and the second driving line 42 are opposite.
  • the first driving line 41 is used to connect the first switch 43 to control the on or off of the first switch 43.
  • the first switch 43 is connected to the first type data line 31 and a third type data line in each first circuit group.
  • the second drive line 44 is used to connect the second switch 44 to control the on or off of the second switch 44.
  • the second switch 44 is connected to the second type data line 32 and the other one in each first circuit group.
  • the three types of data lines 33 correspond.
  • the first switch 43 and the second switch 44 are TFT switches, the control pole of the first switch 43 is connected to the first drive line 41, and the control pole of the second switch 44 is connected to the second drive line 42. Under the control of the first drive line 41, each first switch 43 is closed. At this time, the first type data line 31 is connected to the corresponding port data line, and half of the third type data line 33 is connected to the corresponding port data line. The type data line 31 and half of the third type data line 33 can obtain data signals output by the IC chip. Under the control of the second drive line 42, each second switch 44 is closed. At this time, the second type data line 32 is connected to the corresponding port data line, and the remaining half of the third type data line 33 is connected to the corresponding port data line. The second type data line 32 and the remaining half of the third type data line 33 can obtain data signals output by the IC chip.
  • the number of port data lines is the same as the number of columns of the pixel circuit 1
  • the two first type data lines 31 can be connected to the corresponding data port of the IC chip output terminal through the same port data line
  • the two second type data lines 32 can pass through
  • the same port data line is connected to the corresponding data port of the IC chip output end
  • two non-adjacent third type data lines 33 can be connected to the corresponding data port of the IC chip output end through the same port data line.
  • the data lines D3-1 and data Line D1 can be connected to the IC chip output terminal through the port data line data1
  • the data line D1-1 and data line D3 are connected to the IC chip output terminal through the port data line data3
  • the data line D4-1 and data line D2 are through the port data line data2 Connected to the output terminal of the IC chip
  • the data line D2-1 and the data line D4 are connected to the output terminal of the IC chip through the port data line data4.
  • the connection of the third type data line 33 to the first switch 43 and the second switch 44 may be the same or different.
  • the different situations are illustrated in FIG. 2.
  • the third type data line 33 on the left side of the two first circuit groups are both connected to the first switch 43 or the second switch 44.
  • it may be the second column pixel circuit 1 shown in FIG.
  • the third-type data line 33 on the left is connected to the second switch 44, and the third-type data line 33 on the left of the fourth column of pixel circuits 1 is connected to the first switch 43.
  • Other situations are also possible, which will not be listed here.
  • the pixel circuit 1 connected to the second type data line 32 is in an operating state within the operating pulse corresponding to each gate line 2,
  • the pixel circuit 1 connected to the third type data line 33 corresponding to the second switch 44 is in an operating state.
  • the first switch 43 and the second switch 44 are controlled at a low potential. Down conduction.
  • the first drive line 41 is at a low level to control the first switch 43 to be turned on.
  • the pixel circuit 1 corresponding to the sub-pixel and the pixel circuit 1 corresponding to the G5 (position in the first row and fourth column) sub-pixel operate.
  • the second half of the pulse corresponding to the gate line 2 in the first row the second drive line 42 is at a low level to control the second switch 44 to turn on, which corresponds to the sub-pixel G1 (the position in the first row and the second column)
  • the pixel circuit 1, and the pixel circuit 1 corresponding to the sub-pixel of B3 works.
  • the second drive line 42 is at a low level to control the second switch 44 to turn on.
  • the pixel circuit 1 corresponding to the sub-pixel and the pixel circuit 1 corresponding to the sub-pixel G6 operate.
  • the first drive line 41 is at a low level to control the first switch 43 to turn on, which corresponds to the G2 (the position in the second row and the second column) sub-pixel
  • the pixel circuit 1, and the pixel circuit 1 corresponding to the sub-pixel of R3 (the position of the second row and the third column) works.
  • the first drive line 41 is low level to control the first switch 43 to turn on.
  • the pixel circuit 1 corresponding to the sub-pixel and the pixel circuit 1 corresponding to the G7 (position in the third row and fourth column) sub-pixel operate.
  • the second drive line 42 is at a low level to control the second switch 44 to turn on, which corresponds to the G3 (the position in the third row and the second column) sub-pixel
  • the pixel circuit 1, and the pixel circuit 1 corresponding to the sub-pixel of B4 (the position of the third row and the third column) works.
  • the second drive line 42 is low level to control the second switch 44 to turn on. At this time, it is connected with B2 (the fourth row and first column). Position)
  • the pixel circuit 1 corresponding to the sub-pixel and the pixel circuit 1 corresponding to the G8 (position in the fourth row and fourth column) sub-pixel operate.
  • the first drive line 41 is at a low level to control the first switch 43 to turn on, which corresponds to the G4 (the position in the fourth row and the second column) sub-pixel
  • the pixel circuit 1, and the pixel circuit 1 corresponding to the sub-pixel of R4 (the position of the fourth row and the third column) works.
  • the corresponding organic light emitting diode can be controlled to emit light through the operation of the pixel circuit 1.
  • An embodiment of the present application also provides a display panel including the above-mentioned pixel driving circuit.
  • FIG. 5 is a schematic diagram of the hardware structure of an electronic device implementing various embodiments of the present application.
  • the electronic device 500 includes but is not limited to: a radio frequency unit 501, a network module 502, an audio output unit 503, an input unit 504, a sensor 505, and a display unit 506, a user input unit 507, an interface unit 508, a memory 509, a processor 510, and a power supply 511 and other components.
  • the structure of the electronic device shown in FIG. 5 does not constitute a limitation on the electronic device.
  • the electronic device may include more or fewer components than those shown in the figure, or a combination of certain components, or different components. Layout.
  • electronic devices include, but are not limited to, mobile phones, tablet computers, notebook computers, palmtop computers, vehicle-mounted terminals, wearable devices, and pedometers.
  • the radio frequency unit 501 can be used for receiving and sending signals during information transmission or communication. Specifically, the downlink data from the base station is received and processed by the processor 510; in addition, Uplink data is sent to the base station.
  • the radio frequency unit 501 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, and the like.
  • the radio frequency unit 501 can also communicate with the network and other devices through a wireless communication system.
  • the electronic device provides users with wireless broadband Internet access through the network module 502, such as helping users to send and receive emails, browse web pages, and access streaming media.
  • the audio output unit 503 can convert the audio data received by the radio frequency unit 501 or the network module 502 or stored in the memory 509 into an audio signal and output it as sound. Moreover, the audio output unit 503 may also provide audio output related to a specific function performed by the electronic device 500 (for example, call signal reception sound, message reception sound, etc.).
  • the audio output unit 503 includes a speaker, a buzzer, a receiver, and the like.
  • the input unit 504 is used to receive audio or video signals.
  • the input unit 504 may include a graphics processing unit (GPU) 5041 and a microphone 5042.
  • the graphics processor 5041 is configured to monitor images of still pictures or videos obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. Data is processed.
  • the processed image frame may be displayed on the display unit 506.
  • the image frame processed by the graphics processor 5041 may be stored in the memory 509 (or other storage medium) or sent via the radio frequency unit 501 or the network module 502.
  • the microphone 5042 can receive sound, and can process such sound into audio data.
  • the processed audio data can be converted into a format that can be sent to a mobile communication base station via the radio frequency unit 501 for output in the case of a telephone call mode.
  • the electronic device 500 further includes at least one sensor 505, such as a light sensor, a motion sensor, and other sensors.
  • the light sensor includes an ambient light sensor and a proximity sensor.
  • the ambient light sensor can adjust the brightness of the display panel 5061 according to the brightness of the ambient light.
  • the proximity sensor can close the display panel 5061 and the display panel 5061 when the electronic device 500 is moved to the ear. / Or backlight.
  • the accelerometer sensor can detect the magnitude of acceleration in various directions (usually three axes), and can detect the magnitude and direction of gravity when stationary, and can be used to identify the posture of electronic devices (such as horizontal and vertical screen switching, related games) , Magnetometer posture calibration), vibration recognition related functions (such as pedometer, percussion), etc.; sensor 505 can also include fingerprint sensors, pressure sensors, iris sensors, molecular sensors, gyroscopes, barometers, hygrometers, thermometers, Infrared sensors, etc., will not be repeated here.
  • the display unit 506 is used to display information input by the user or information provided to the user.
  • the display unit 506 may include a display panel 5061, and the display panel 5061 may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), and the like.
  • LCD liquid crystal display
  • OLED organic light-emitting diode
  • the display panel 5061 includes a pixel driving circuit, and the pixel driving circuit includes:
  • At least four gate lines are arranged along the first direction of the pixel array, a row of pixel circuits is arranged between two adjacent gate lines, and each row of pixel circuits corresponds to one gate line;
  • At least eight data lines arranged along a second direction perpendicular to the first direction and intersecting each gate line, each data line being connected to a pixel circuit corresponding to the same color sub-pixel in a column of pixel circuits; and to the data line
  • the connected demultiplexer circuit the demultiplexer circuit is used to control the data line to communicate with the integrated circuit IC chip.
  • the pixel driving circuit further includes:
  • the array substrate row connected to the output terminal of the IC chip drives the GOA unit;
  • the GOA unit includes a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a plurality of first GOA circuits connected to odd-numbered row gate lines, and a plurality of even-numbered row gate lines.
  • the second GOA circuit ;
  • the first GOA circuit is connected to the first clock signal line and the second clock signal line, and the second GOA circuit is connected to the third clock signal line and the fourth clock signal line;
  • the first clock signal line and the second clock signal line have opposite timings
  • the third clock signal line and the fourth clock signal line have opposite timings.
  • each adjacent first GOA circuit is connected to form an odd-numbered row of gate lines
  • each adjacent second GOA circuit is connected to form an even-numbered row of gate lines. ⁇ ;
  • the output terminal of the first GOA circuit of each stage is connected to the input terminal of the first GOA circuit of the next next stage; except for the second GOA circuit of the last stage, each stage The output terminal of the second GOA circuit is connected to the input terminal of the next second GOA circuit of the next stage.
  • the clock signal of the second GOA circuit corresponding to the even-numbered gate lines is delayed.
  • the second half of the pulse is delayed.
  • the data line includes a first type data line, a second type data line, and a third type data line;
  • Each column of pixel circuits is a circuit group, the circuit group corresponding to the same color sub-pixels is the first circuit group, and the circuit group corresponding to the two color sub-pixels is the second circuit group;
  • the data line of the first type is connected to the pixel circuit corresponding to the sub-pixel of the first color in the second circuit group, and the data line of the second type is connected to the pixel circuit corresponding to the sub-pixel of the second color in the second circuit group;
  • the third type data line is connected to the pixel circuit in the first circuit group.
  • the sum of the numbers of the first type data line, the second type data line, and the third type data line is twice the number of columns corresponding to the pixel circuit;
  • the first type data line, the second type data line, the two third type data lines, the second type data line, the first type data line, and the two third type data lines are sequentially arranged in the second direction;
  • each third type data line is connected to half of the pixel circuits in the first circuit group, and at least two pixel circuits connected to one third type data line are arranged adjacently or spaced apart.
  • the demultiplexer circuit includes:
  • a first drive line a second drive line whose timing is opposite to that of the first drive line, at least four first switches, and at least four second switches;
  • the first driving line and the second driving line are connected to the output terminal of the IC chip;
  • the first type data line and one third type data line in each first circuit group correspond to the first switch, and the second type data line and the other third type data line in each first circuit group correspond to the second switch ;
  • the control terminal of the first switch is connected to the first drive line, and is used to connect the first type data line and the corresponding port data line, half of the third type data line and the corresponding port data line under the control of the first drive line;
  • the control terminal of the second switch is connected to the second drive line, and is used to connect the second type data line and the corresponding port data line, and the remaining half of the third type data line and the corresponding port data line under the control of the second drive line;
  • each port data line is connected to the output terminal of the integrated circuit.
  • the pixel circuit connected to the first type data line is in the working state, and the third switch corresponding to the first switch is in the working state.
  • the pixel circuit connected to the type data line is in working state;
  • the pixel circuit connected to the second type data line is in working state, and is connected to the third type data line corresponding to the second switch The pixel circuit is in working condition.
  • the user input unit 507 can be used to receive inputted numeric or character information, and generate key signal input related to user settings and function control of the electronic device.
  • the user input unit 507 includes a touch panel 5071 and other input devices 5072.
  • the touch panel 5071 also known as a touch screen, can collect the user's touch operations on or near it (for example, the user uses any suitable objects or accessories such as fingers, stylus, etc.) on the touch panel 5071 or near the touch panel 5071. operate).
  • the touch panel 5071 may include two parts: a touch detection device and a touch controller.
  • the touch detection device detects the user's touch position, detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into contact coordinates, and then sends it To the processor 510, the command sent by the processor 510 is received and executed.
  • the touch panel 5071 can be implemented in multiple types such as resistive, capacitive, infrared, and surface acoustic wave.
  • the user input unit 507 may also include other input devices 5072.
  • other input devices 5072 may include, but are not limited to, a physical keyboard, function keys (such as volume control buttons, switch buttons, etc.), trackball, mouse, and joystick, which will not be repeated here.
  • the touch panel 5071 can be overlaid on the display panel 5061.
  • the touch panel 5071 detects a touch operation on or near it, it is transmitted to the processor 510 to determine the type of touch event, and then the processor 510 determines the type of the touch event according to the touch.
  • the type of event provides corresponding visual output on the display panel 5061.
  • the touch panel 5071 and the display panel 5061 are used as two independent components to implement the input and output functions of the electronic device, in some embodiments, the touch panel 5071 and the display panel 5061 can be integrated
  • the implementation of the input and output functions of the electronic device is not specifically limited here.
  • the interface unit 508 is an interface for connecting an external device and the electronic device 500.
  • the external device may include a wired or wireless headset port, an external power source (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device with an identification module, audio input/output (I/O) port, video I/O port, headphone port, etc.
  • the interface unit 508 can be used to receive input (for example, data information, power, etc.) from an external device and transmit the received input to one or more elements in the electronic device 500 or can be used to connect the electronic device 500 to an external device. Transfer data between devices.
  • the memory 509 can be used to store software programs and various data.
  • the memory 509 may mainly include a storage program area and a storage data area.
  • the storage program area may store an operating system, an application program required by at least one function (such as a sound playback function, an image playback function, etc.), etc.; Data created by the use of mobile phones (such as audio data, phone book, etc.), etc.
  • the memory 509 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other volatile solid-state storage devices.
  • the processor 510 is the control center of the electronic device. It uses various interfaces and lines to connect the various parts of the entire electronic device, runs or executes software programs and/or modules stored in the memory 509, and calls data stored in the memory 509 , Perform various functions of electronic equipment and process data, so as to monitor the electronic equipment as a whole.
  • the processor 510 may include one or more processing units; preferably, the processor 510 may integrate an application processor and a modem processor, where the application processor mainly processes the operating system, user interface, application programs, etc., and the modem The processor mainly deals with wireless communication. It can be understood that the foregoing modem processor may not be integrated into the processor 510.
  • the electronic device 500 may also include a power source 511 (such as a battery) for supplying power to various components.
  • a power source 511 such as a battery
  • the power source 511 may be logically connected to the processor 510 through a power management system, so as to manage charging, discharging, and power consumption management through the power management system. And other functions.
  • the electronic device 500 includes some functional modules not shown, which will not be repeated here.
  • the technical solution of this application essentially or the part that contributes to the existing technology can be embodied in the form of a software product, and the computer software product is stored in a storage medium (such as ROM/RAM, magnetic disk, The optical disc) includes several instructions to make a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) execute the methods described in the various embodiments of the present application.
  • a terminal which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.

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Abstract

一种像素驱动电路、显示面板（5061）及电子设备（500），其中像素驱动电路包括：包括多个像素电路（1）的像素阵列，像素阵列采用RGBG像素排列方式；沿像素阵列的第一方向排列的至少四条栅线（2），相邻两条栅线（2）之间设置一行像素电路（1），每行像素电路（1）对应一条栅线（2）；沿与第一方向垂直的第二方向排列、且与每条栅线（2）交叉设置的至少八条数据线（3），每条数据线（3）与一列像素电路（1）中对应于同一颜色子像素的像素电路（1）连接；以及与数据线（3）连接的多路分配器电路（4），多路分配器电路（4）用于控制数据线（3）连通集成电路IC芯片。

Description

像素驱动电路、显示面板及电子设备
相关申请的交叉引用
本申请主张在2020年3月24日在中国提交的中国专利申请No.202010211246.9的优先权，其全部内容通过引用包含于此。
技术领域
本申请涉及显示技术领域，尤其涉及一种像素驱动电路、显示面板及电子设备。
背景技术
有源矩阵有机发光二极体面板(Active Matrix/Organic Light Emitting Diode，AMOLED)显示电路，每个像素电路包括多个薄膜晶体管(Thin Film Transistor，TFT)驱动开关和一个有机发光二极管(Organic Light-Emitting Diode，OLED)，通常采用7T1C(7个TFT晶体管和1个电容组成)像素补偿电路，以及驱动点亮各个显示器件单元的驱动电路。其中：7T1C驱动电路输入信号包含：OLED发光控制信号(Emission，EM)、Scan[n]、Scan[n-1]、Vini(初始复位信号)、Vdata(数据信号)、Vdd(高位信号)；驱动电路通常包括Scan GOA(Gate Driver On Array，阵列基板行驱动扫描电路)电路和EM阵列基板行驱动电路(Emit Gate Driver On Array，EM GOA)，Scan GOA和EM GOA(简称EOA)电路中采用CK(时钟信号)\XCK(外部时钟信号)\VGL(低电位)\VGH(高电位)\STV(初始信号)等输入信号，通过时序电路MOS开关单元后(多个TFT和多个电容组成)，输出级传后的每行驱动时序给显示区的像素电路，如图1所示。
在AMOLED显示模组中，通常采用RGBG像素排列方式(每两个像素共享一个绿色的子像素，这使得蓝色OLED的面积可以更大，同时带来更高的面板开口率，这样一来就使得达到相当发光强度所需要的电流降低，从而延缓衰减速度使得显示面板寿命提高)，此种排列方式和传统RGB条形排列方式相比，一列像素上有2种显示颜色，因Gate(栅线)GOA集成电路在 级传过程中，容易因级传过程中的R(电阻)和C(电容)引起的波形延时，发生扫描信号Gate输出波形延时，在像素电路单元的Vdata电压写入阶段的过程中，容易写入上一帧的Vdata电压，导致纯色显示色偏，例如红色画面偏蓝，蓝色画面偏红。
发明内容
本申请实施例提供一种像素驱动电路、显示面板及电子设备，以解决现有技术中由于输出波形延时导致的纯色显示色偏的问题。
为了解决上述问题，本申请实施例是这样实现的：
第一方面，本申请实施例提供一种像素驱动电路，包括：
包括多个像素电路的像素阵列，所述像素阵列采用RGBG像素排列方式；
沿所述像素阵列的第一方向排列的至少四条栅线，相邻两条栅线之间设置一行像素电路，每行像素电路对应一条栅线；
沿与所述第一方向垂直的第二方向排列、且与每条栅线交叉设置的至少八条数据线，每条数据线与一列像素电路中对应于同一颜色子像素的所述像素电路连接；以及
与所述数据线连接的多路分配器电路，所述多路分配器电路用于控制所述数据线连通集成电路IC芯片。
第二方面，本申请实施例提供一种显示面板，所述显示面板包括上述的像素驱动电路。
第三方面，本申请实施例提供一种电子设备，包括上述的显示面板。
本申请技术方案，通过在显示区域增设数据线，在非显示区域增设多路分配器电路，将单元列的同种颜色子像素采用同一数据线输入数据信号，使得纯色画面显示时，不会造成上一帧不同颜色的信号错写入而引起色偏，保证了画面显示的一致性，改善了显示面板色偏的问题。
附图说明
图1表示现有技术AMOLED显示面板驱动架构示意图；
图2表示本申请实施例像素驱动电路示意图；
图3表示RGBG像素排布方式示意图；
图4表示本申请实施例的时序图；
图5表示本申请实施例电子设备硬件结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请实施例提供一种像素驱动电路，如图2所示，包括：
包括多个像素电路1的像素阵列，所述像素阵列采用RGBG像素排列方式；
沿所述像素阵列的第一方向排列的至少四条栅线2，相邻两条栅线2之间设置一行像素电路1，每行像素电路1对应一条栅线2；
沿与所述第一方向垂直的第二方向排列、且与每条栅线2交叉设置的至少八条数据线3，每条数据线3与一列像素电路1中对应于同一颜色子像素的所述像素电路1连接；以及
与所述数据线3连接的多路分配器电路4，所述多路分配器电路4用于控制所述数据线3连通集成电路IC芯片。
本发明实施例提供的像素驱动电路包括位于显示区域的像素阵列，设置于像素阵列中的至少四条栅线2和至少八条数据线3，以及设置于非显示区域的多路分配器电路4。其中像素阵列采用RGBG像素排列方式，RGBG像素排列可参见图3。
像素阵列包括多个以阵列方式排布的像素电路1，每一个像素电路1与对应的有机发光二极体形成一像素单元，多个像素单元组成像素阵列。
至少四条栅线2沿像素阵列的第一方向排列，相邻两条栅线2之间设置一行像素电路1，每一行像素电路1对应一条栅线2。至少八条数据线3沿第二方向依次排列，且与每条栅线2形成交叉设置的形式。每条数据线3与一列像素电路1中对应于同一颜色子像素的像素电路1连接，可以保证画面显 示的一致性，改善了显示面板色偏的问题。
各数据线3均连接至多路分配器电路4，通过多路分配器电路4可以使得数据线3连通集成电路(Integrated Circuit，IC)芯片，进而可以使得数据线3控制与之连接的像素电路1的工作状态。
本申请实施例的像素驱动电路，通过在显示区域增设数据线，在非显示区域增设多路分配器电路，将单元列的同种颜色子像素采用同一数据线输入数据信号，保证了画面显示的一致性，改善了显示面板色偏的问题。
可选的，在本申请一实施例中，如图2所示，像素驱动电路还包括：
与所述IC芯片的输出端连接的阵列基板行驱动GOA单元5；所述GOA单元5包括第一时钟信号线51、第二时钟信号线52、第三时钟信号线53、第四时钟信号线54以及与奇数行栅线2连接的多个第一GOA电路55和与偶数行栅线2连接的多个第二GOA电路56；
所述第一GOA电路55连接所述第一时钟信号线51和所述第二时钟信号线52，所述第二GOA电路56连接所述第三时钟信号线53和所述第四时钟信号线54；
所述第一时钟信号线51和所述第二时钟信号线52的时序相反，所述第三时钟信号线53和所述第四时钟信号线54的时序相反。
GOA单元5与IC芯片的输出端连接，包括四条时钟信号线，在原有电路的基础上增设了两条时钟信号线，还包括多个第一GOA电路55以及多个第二GOA电路56，第一GOA电路55的数量与像素阵列中奇数行栅线2的数量相等，第二GOA电路56的数量与像素阵列中偶数行栅线2的数量相等，即每一条奇数行的栅线2对应于一个第一GOA电路55，每一条偶数行的栅线2对应于一个第二GOA电路56。
其中，第一时钟信号线51和第二时钟信号线52的时序相反，且第一时钟信号线51和第二时钟信号线52作为输入信号线与各第一GOA电路55连接，用于向各第一GOA电路55输入时钟信号。
第三时钟信号线53和第四时钟信号线54的时序相反，且第三时钟信号线53和第四时钟信号线54作为输入信号线与各第二GOA电路56连接，用于向各第二GOA电路56输入时钟信号。
其中，由于GOA单元5与IC芯片的输出端连接，其具体的连接形式为：第一时钟信号线51与IC芯片输出端的第一时钟端口连接，第二时钟信号线52与IC芯片输出端的第二时钟端口连接，第三时钟信号线53与IC芯片输出端的第三时钟端口连接，第四时钟信号线54与IC芯片输出端的第四时钟端口连接；奇数行栅线2对应的第一GOA电路55、偶数行栅线2对应的第二GOA电路56分别连接IC芯片输出端的不同驱动端口。通过增设两条时钟信号线，可以改善由于时延造成的不同颜色数据信号的误写入，从而改善面板色偏。
可选的，在本申请一实施例中，如图2所示，按照行数递增的排列顺序，各相邻的所述第一GOA电路55之间连接且形成奇数行栅线2的级传、各相邻的所述第二GOA电路56之间连接且形成偶数行栅线2的级传；
其中，除最后一级所述第一GOA电路55外，每一级所述第一GOA电路55的输出端与相邻下一级所述第一GOA电路55的输入端连接；除最后一级所述第二GOA电路56外，每一级所述第二GOA电路56的输出端与相邻下一级所述第二GOA电路56的输入端连接。
与奇数行栅线2连接的多个第一GOA电路55之间，按照行数依次递增的顺序，实现前一级第一GOA电路55与后一级第一GOA电路55之间的连接，进而形成奇数行栅线2的级传。相应的，与偶数行栅线2连接的多个第二GOA电路56之间，按照行数依次递增的顺序，实现前一级第二GOA电路56与后一级第二GOA电路56之间的连接，进而形成偶数行栅线2的级传。例如，与第一行栅线2连接的第一GOA电路55的输出端和与第三行栅线2连接的第一GOA电路55的输入端连接，与第三行栅线2连接的第一GOA电路55的输出端和与第五行栅线2连接的第一GOA电路55的输入端连接；与第二行栅线2连接的第二GOA电路56的输出端和与第四行栅线2连接的第二GOA电路56的输入端连接，与第四行栅线2连接的第二GOA电路56的输出端和与第六行栅线2连接的第二GOA电路56的输入端连接。
通过实现奇数行级传和偶数行级传的区分，可以使得奇数行极传对应于第一时钟信号线和第二时钟信号线，偶数行极传对应于第三时钟信号线和第四时钟信号线，进而可以改善由于时延造成的不同颜色数据信号的误写入， 从而改善面板色偏。
需要说明的是，图2中所示的像素阵列为最小驱动单元，通过多个最小驱动单元可组合为与显示面板对应的驱动电路。如针对显示面板对应1080列、2400行像素电路的情况，此时在列方向上需要有270个最小驱动单元，在行方向上需要有600个最小驱动单元。
其中，如图4所示，第一时钟信号线(CK1)对应的波形为第一栅线(第一行栅线)的波形和第三栅线(第三行栅线)的反向波形叠加后生成的波形，第二时钟信号线(XCK1)与第一时钟信号线的波形相反，第三时钟信号线(CK2)对应的波形为第二栅线(第二行栅线)的波形和第四栅线(第四行栅线)的反向波形叠加后生成的波形，第四时钟信号线(XCK2)与第三时钟信号线的波形相反，且第三时钟信号线(CK2)相对第一时钟信号线(CK1)延后半个脉冲。
可选的，在本申请一实施例中，如图2和图4所示，对于相邻的奇数行栅线2和偶数行栅线2，其中，相对于奇数行栅线2对应的第一GOA电路55的时钟信号，偶数行栅线2对应的第二GOA电路56的时钟信号延后半个脉冲。
通过增加两条时钟信号线，实现奇数行级传和偶数行级传的区分，并针对相邻的奇数行栅线2和偶数行栅线2，设置偶数行栅线2对应的第二GOA电路56的时钟信号延后奇数行栅线2对应的第一GOA电路55的时钟信号半个脉冲，可以与数据线3进行配合，实现在一个连续的时间内，控制每一列像素电路1中对应于同一颜色子像素的像素电路1根据脉冲信号依序工作。
可选的，在本申请一实施例中，如图2所示，所述数据线3包括第一类型数据线31、第二类型数据线32和第三类型数据线33；
每列像素电路1为一电路组，对应相同颜色子像素的所述电路组为第一电路组，对应两个颜色子像素的所述电路组为第二电路组；
所述第一类型数据线31与所述第二电路组中对应第一颜色子像素的所述像素电路1连接，所述第二类型数据线32与所述第二电路组中对应第二颜色子像素的所述像素电路1连接；所述第三类型数据线33与所述第一电路组中的所述像素电路1连接。
沿第二方向排列的数据线3对应于三种类型，每一类型的数据线3可分别连接至对应的像素电路1，并控制像素电路1的工作状态。其中针对每一列像素电路1可形成一电路组，根据电路组所对应的不同子像素可将电路组确定为2种不同类型的电路组。若电路组中的像素电路1对应相同颜色子像素，则该电路组为第一电路组，若电路组中的像素电路1对应两个颜色子像素，则该电路组为第二电路组。
针对数据线3而言，确定与第一电路组中的像素电路1连接的数据线3为第三类型数据线33，确定与第二电路组中对应第一颜色子像素的像素电路1连接的数据线3为第一类型数据线31，确定与第二电路组中对应第二颜色子像素的像素电路1连接的数据线3为第二类型数据线32。
由于像素阵列采用RGBG像素排列方式，因此第一电路组中的像素电路1对应绿色子像素，第一颜色子像素可以为红色或者蓝色子像素，相应的第二颜色子像素可以为蓝色或者红色子像素。
通过划分数据线类型，可以实现将对应不同颜色子像素的像素电路与相应的数据线连接，进而可以将单元列的同种颜色子像素采用同一数据线输入数据信号，保证了画面显示的一致性，改善了显示面板色偏的问题。
可选的，在本申请一实施例中，如图2所示，所述第一类型数据线31、所述第二类型数据线32和所述第三类型数据线33的数量之和为所述像素电路1所对应的列数的两倍倍；所述第一类型数据线31、所述第二类型数据线32、两条所述第三类型数据线33、所述第二类型数据线32、所述第一类型数据线31和两条所述第三类型数据线33在所述第二方向上依次排列；其中，每条所述第三类型数据线33与所述第一电路组中半数的所述像素电路1连接，且与一条所述第三类型数据线33连接的至少两个所述像素电路1相邻或者间隔排布。
针对每列像素电路1，可对应于两条数据线3，其中针对对应两个颜色子像素的电路组而言，两条数据线3分别为第一类型数据线31和第二类型数据线32；针对对应一个颜色子像素的电路组而言，两条数据线3均为第三类型数据线33。因此第一类型数据线31、第二类型数据线32和第三类型数据线33的数量之和为电路组数量的两倍。且第一类型数据线31、第二类型数据线 32、两条第三类型数据线33、第二类型数据线32、第一类型数据线31和两条第三类型数据线33在第二方向上依次排列。
以图2为例进行阐述，在第二方向上数据线D1、D1-1、D2、D2-1、D3、D3-1、D4、D4-1依次排列。第一列像素电路1中与R(红色)子像素对应的像素电路1通过D1(第一类型数据线)驱动，第一列像素电路1中与B(蓝色)子像素对应的像素电路1通过D1-1(第二类型数据线)驱动；同理第三列像素电路1中与B子像素对应的像素电路1通过D3(第二类型数据线)驱动，第三列像素电路1中与R子像素对应的像素电路1通过D3-1(第一类型数据线)驱动；第二列像素电路1中与G(绿色)子像素对应的像素电路1也采用奇数行偶数行分别用D2(第三类型数据线)和D2-1(第三类型数据线)驱动，第四列像素电路1的驱动方式同第二列。在第二方向上，第一类型数据线31、第二类型数据线32、两条第三类型数据线33、第二类型数据线32、第一类型数据线31和两条第三类型数据线33依次排列。
其中，针对第三类型数据线33而言，每条第三类型数据线33与第一电路组中一半的像素电路1连接，且可以连接相邻或者间隔设置的像素电路1。由于第一电路组中对应的像素电路1至少为4个，因此一条第三类型数据线33连接的至少两个像素电路1可以相邻或者间隔排布。图2中示出的是一条第三类型数据线33与间隔的两个像素电路1连接的示例。
可选的，在本申请一实施例中，如图2所示，所述多路分配器电路4包括：
第一驱动线41、与所述第一驱动线41时序相反的第二驱动线42、至少四个第一开关43和至少四个第二开关44；
所述第一驱动线41和所述第二驱动线42与所述IC芯片的输出端连接；
所述第一类型数据线31和各所述第一电路组中的一条所述第三类型数据线33对应于所述第一开关43，所述第二类型数据线32和各所述第一电路组中的另一条所述第三类型数据线33对应于所述第二开关44；
所述第一开关43的控制端连接所述第一驱动线41，用于在所述第一驱动线41的控制下连通所述第一类型数据线31和对应的端口数据线、半数的所述第三类型数据线33和对应的端口数据线；
所述第二开关44的控制端连接所述第二驱动线42，用于在所述第二驱动线42的控制下连通所述第二类型数据线32和对应的端口数据线、剩余半数的所述第三类型数据线33和对应的端口数据线；
其中，各所述端口数据线连接至所述IC芯片的输出端。
多路分配器电路4所包括的第一驱动线41和第二驱动线42分别连接至IC芯片输出端的不同驱动端口，且第一驱动线41和第二驱动线42的时序相反。第一驱动线41用于连接第一开关43，控制第一开关43的导通或者关断，第一开关43与第一类型数据线31和各第一电路组中的一条第三类型数据线33对应，第二驱动线44用于连接第二开关44，控制第二开关44的导通或者关断，第二开关44与第二类型数据线32和各第一电路组中的另一条第三类型数据线33对应。
第一开关43和第二开关44为TFT开关，第一开关43的控制极连接第一驱动线41，第二开关44的控制极连接第二驱动线42。在第一驱动线41的控制下，各第一开关43闭合，此时第一类型数据线31和对应的端口数据线、半数的第三类型数据线33和对应的端口数据线连通，第一类型数据线31、半数的第三类型数据线33可以获取IC芯片输出的数据信号。在第二驱动线42的控制下，各第二开关44闭合，此时第二类型数据线32和对应的端口数据线、剩余半数的第三类型数据线33和对应的端口数据线连通，第二类型数据线32、剩余半数的第三类型数据线33可以获取IC芯片输出的数据信号。
其中，端口数据线的数量与像素电路1的列数相同，两条第一类型数据线31可通过同一端口数据线连接至IC芯片输出端的对应数据端口，两条第二类型数据线32可通过同一端口数据线连接至IC芯片输出端的对应数据端口，两条不相邻的第三类型数据线33可通过同一端口数据线连接至IC芯片输出端的对应数据端口。针对图2所示的像素阵列，在第二方向上数据线D1、D1-1、D2、D2-1、D3、D3-1、D4、D4-1依次排列时，数据线D3-1和数据线D1可通过端口数据线data1连接至IC芯片输出端，数据线D1-1和数据线D3通过端口数据线data3连接至IC芯片输出端，数据线D4-1和数据线D2通过端口数据线data2连接至IC芯片输出端，数据线D2-1和数据线D4通过端口数据线data4连接至IC芯片输出端。
需要说明的是，针对两个第一电路组而言，第三类型数据线33与第一开关43和第二开关44连接的情况可以相同或者不同，图2中示意出的是不同的情况。在相同时，两个第一电路组中的左侧的第三类型数据线33均连接第一开关43或第二开关44，在不同时，可以是图2所示的第二列像素电路1左侧的第三类型数据线33连接第二开关44，第四列像素电路1左侧的第三类型数据线33连接第一开关43，还可以是其他情况，这里不再一一列举。
可选的，在本申请一实施例中，如图2和图4所示，在所述第一驱动线41控制所述第一开关43导通时，在各栅线2对应的工作脉冲内，与所述第一类型数据线31连接的所述像素电路1处于工作状态、与对应于所述第一开关43的所述第三类型数据线33连接的所述像素电路1处于工作状态；
在所述第二驱动线42控制所述第二开关44导通时，在各栅线2对应的工作脉冲内，与所述第二类型数据线32连接的所述像素电路1处于工作状态、与对应于所述第二开关44的所述第三类型数据线33连接的所述像素电路1处于工作状态。
下面参见图4的时序图，针对图2的像素阵列，对根据栅线2与数据线3配合控制像素电路1工作的情况进行阐述，其中第一开关43和第二开关44在低电位的控制下导通。
在(第一栅线)第一行栅线2对应的前半个脉冲内，第一驱动线41为低电平可以控制第一开关43导通，此时与R1(第一行第一列的位置)子像素对应的像素电路1、与G5(第一行第四列的位置)子像素对应的像素电路1工作。在第一行栅线2对应的后半个脉冲内，第二驱动线42为低电平可以控制第二开关44导通，此时与G1(第一行第二列的位置)子像素对应的像素电路1、与B3(第一行第三列的位置)子像素对应的像素电路1工作。
在(第二栅线)第二行栅线2对应的前半个脉冲内，第二驱动线42为低电平可以控制第二开关44导通，此时与B1(第二行第一列的位置)子像素对应的像素电路1、与G6(第二行第四列的位置)子像素对应的像素电路1工作。在第二行栅线2对应的后半个脉冲内，第一驱动线41为低电平可以控制第一开关43导通，此时与G2(第二行第二列的位置)子像素对应的像素电路1、与R3(第二行第三列的位置)子像素对应的像素电路1工作。
在(第三栅线)第三行栅线2对应的前半个脉冲内，第一驱动线41为低电平可以控制第一开关43导通，此时与R2(第三行第一列的位置)子像素对应的像素电路1、与G7(第三行第四列的位置)子像素对应的像素电路1工作。在第三行栅线2对应的后半个脉冲内，第二驱动线42为低电平可以控制第二开关44导通，此时与G3(第三行第二列的位置)子像素对应的像素电路1、与B4(第三行第三列的位置)子像素对应的像素电路1工作。
在(第四栅线)第四行栅线2对应的前半个脉冲内，第二驱动线42为低电平可以控制第二开关44导通，此时与B2(第四行第一列的位置)子像素对应的像素电路1、与G8(第四行第四列的位置)子像素对应的像素电路1工作。在第四行栅线2对应的后半个脉冲内，第一驱动线41为低电平可以控制第一开关43导通，此时与G4(第四行第二列的位置)子像素对应的像素电路1、与R4(第四行第三列的位置)子像素对应的像素电路1工作。
上述过程，通过像素电路1的工作可以控制对应的有机发光二极体发光。
随着屏幕高刷新率的采用(如90Hz、120Hz)，数据线充电时间越来越短，由栅线延迟引起的数据信号误写入的风险越来越高，纯色显示和区块纯色出现色偏的比率将会比60Hz的增加1倍，本申请将相同颜色子像素同列驱动，避免了上述色偏问题，另外，对于灰阶画面色偏，提供更多可调整的方法。
本申请实施例还提供一种显示面板，包括上述的像素驱动电路。
图5为实现本申请各个实施例的一种电子设备的硬件结构示意图，该电子设备500包括但不限于：射频单元501、网络模块502、音频输出单元503、输入单元504、传感器505、显示单元506、用户输入单元507、接口单元508、存储器509、处理器510、以及电源511等部件。
本领域技术人员可以理解，图5中示出的电子设备结构并不构成对电子设备的限定，电子设备可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。在本申请实施例中，电子设备包括但不限于手机、平板电脑、笔记本电脑、掌上电脑、车载终端、可穿戴设备、以及计步器等。
应理解的是，本申请实施例中，射频单元501可用于收发信息或通话过程中，信号的接收和发送，具体的，将来自基站的下行数据接收后，给处理器510处理；另外，将上行的数据发送给基站。通常，射频单元501包括但 不限于天线、至少一个放大器、收发信机、耦合器、低噪声放大器、双工器等。此外，射频单元501还可以通过无线通信系统与网络和其他设备通信。
电子设备通过网络模块502为用户提供了无线的宽带互联网访问，如帮助用户收发电子邮件、浏览网页和访问流式媒体等。
音频输出单元503可以将射频单元501或网络模块502接收的或者在存储器509中存储的音频数据转换成音频信号并且输出为声音。而且，音频输出单元503还可以提供与电子设备500执行的特定功能相关的音频输出(例如，呼叫信号接收声音、消息接收声音等等)。音频输出单元503包括扬声器、蜂鸣器以及受话器等。
输入单元504用于接收音频或视频信号。输入单元504可以包括图形处理器(Graphics Processing Unit，GPU)5041和麦克风5042，图形处理器5041对在视频捕获模式或图像捕获模式中由图像捕获装置(如摄像头)获得的静态图片或视频的图像数据进行处理。处理后的图像帧可以显示在显示单元506上。经图形处理器5041处理后的图像帧可以存储在存储器509(或其它存储介质)中或者经由射频单元501或网络模块502进行发送。麦克风5042可以接收声音，并且能够将这样的声音处理为音频数据。处理后的音频数据可以在电话通话模式的情况下转换为可经由射频单元501发送到移动通信基站的格式输出。
电子设备500还包括至少一种传感器505，比如光传感器、运动传感器以及其他传感器。具体地，光传感器包括环境光传感器及接近传感器，其中，环境光传感器可根据环境光线的明暗来调节显示面板5061的亮度，接近传感器可在电子设备500移动到耳边时，关闭显示面板5061和/或背光。作为运动传感器的一种，加速计传感器可检测各个方向上(一般为三轴)加速度的大小，静止时可检测出重力的大小及方向，可用于识别电子设备姿态(比如横竖屏切换、相关游戏、磁力计姿态校准)、振动识别相关功能(比如计步器、敲击)等；传感器505还可以包括指纹传感器、压力传感器、虹膜传感器、分子传感器、陀螺仪、气压计、湿度计、温度计、红外线传感器等，在此不再赘述。
显示单元506用于显示由用户输入的信息或提供给用户的信息。显示单 元506可包括显示面板5061，可以采用液晶显示器(Liquid Crystal Display，LCD)、有机发光二极管(Organic Light-Emitting Diode，OLED)等形式来配置显示面板5061。
显示面板5061包括像素驱动电路，像素驱动电路包括：
包括多个像素电路的像素阵列，像素阵列采用RGBG像素排列方式；
沿像素阵列的第一方向排列的至少四条栅线，相邻两条栅线之间设置一行像素电路，每行像素电路对应一条栅线；
沿与第一方向垂直的第二方向排列、且与每条栅线交叉设置的至少八条数据线，每条数据线与一列像素电路中对应于同一颜色子像素的像素电路连接；以及与数据线连接的多路分配器电路，多路分配器电路用于控制数据线连通集成电路IC芯片。
可选的，像素驱动电路包括还包括：
与IC芯片的输出端连接的阵列基板行驱动GOA单元；
GOA单元包括第一时钟信号线、第二时钟信号线、第三时钟信号线、第四时钟信号线以及与奇数行栅线连接的多个第一GOA电路和与偶数行栅线连接的多个第二GOA电路；
第一GOA电路连接第一时钟信号线和第二时钟信号线，第二GOA电路连接第三时钟信号线和第四时钟信号线；
第一时钟信号线和第二时钟信号线的时序相反，第三时钟信号线和第四时钟信号线的时序相反。
可选的，按照行数递增的排列顺序，各相邻的第一GOA电路之间连接且形成奇数行栅线的级传、各相邻的第二GOA电路之间连接且形成偶数行栅线的级传；
其中，除最后一级第一GOA电路外，每一级第一GOA电路的输出端与相邻下一级第一GOA电路的输入端连接；除最后一级第二GOA电路外，每一级第二GOA电路的输出端与相邻下一级第二GOA电路的输入端连接。
可选的，对于相邻的奇数行栅线和偶数行栅线，其中，相对于奇数行栅线对应的第一GOA电路的时钟信号，偶数行栅线对应的第二GOA电路的时钟信号延后半个脉冲。
可选的，数据线包括第一类型数据线、第二类型数据线和第三类型数据线；
每列像素电路为一电路组，对应相同颜色子像素的电路组为第一电路组，对应两个颜色子像素的电路组为第二电路组；
第一类型数据线与第二电路组中对应第一颜色子像素的像素电路连接，第二类型数据线与第二电路组中对应第二颜色子像素的像素电路连接；
第三类型数据线与第一电路组中的像素电路连接。
可选的，第一类型数据线、第二类型数据线和第三类型数据线的数量之和为像素电路所对应的列数的两倍；
第一类型数据线、第二类型数据线、两条第三类型数据线、第二类型数据线、第一类型数据线和两条第三类型数据线在第二方向上依次排列；
其中，每条第三类型数据线与第一电路组中半数的像素电路连接，且与一条第三类型数据线连接的至少两个像素电路相邻或者间隔排布。
可选的，多路分配器电路包括：
第一驱动线、与第一驱动线时序相反的第二驱动线、至少四个第一开关和至少四个第二开关；
第一驱动线和第二驱动线与IC芯片的输出端连接；
第一类型数据线和各第一电路组中的一条第三类型数据线对应于第一开关，第二类型数据线和各第一电路组中的另一条第三类型数据线对应于第二开关；
第一开关的控制端连接第一驱动线，用于在第一驱动线的控制下连通第一类型数据线和对应的端口数据线、半数的第三类型数据线和对应的端口数据线；
第二开关的控制端连接第二驱动线，用于在第二驱动线的控制下连通第二类型数据线和对应的端口数据线、剩余半数的第三类型数据线和对应的端口数据线；
其中，各端口数据线连接至集成电路的输出端。
可选的，在第一驱动线控制第一开关导通时，在各栅线对应的工作脉冲内，与第一类型数据线连接的像素电路处于工作状态、与对应于第一开关的 第三类型数据线连接的像素电路处于工作状态；
在第二驱动线控制第二开关导通时，在各栅线对应的工作脉冲内，与第二类型数据线连接的像素电路处于工作状态、与对应于第二开关的第三类型数据线连接的像素电路处于工作状态。
用户输入单元507可用于接收输入的数字或字符信息，以及产生与电子设备的用户设置以及功能控制有关的键信号输入。具体地，用户输入单元507包括触控面板5071以及其他输入设备5072。触控面板5071，也称为触摸屏，可收集用户在其上或附近的触摸操作(比如用户使用手指、触笔等任何适合的物体或附件在触控面板5071上或在触控面板5071附近的操作)。触控面板5071可包括触摸检测装置和触摸控制器两个部分。其中，触摸检测装置检测用户的触摸方位，并检测触摸操作带来的信号，将信号传送给触摸控制器；触摸控制器从触摸检测装置上接收触摸信息，并将它转换成触点坐标，再送给处理器510，接收处理器510发来的命令并加以执行。此外，可以采用电阻式、电容式、红外线以及表面声波等多种类型实现触控面板5071。除了触控面板5071，用户输入单元507还可以包括其他输入设备5072。具体地，其他输入设备5072可以包括但不限于物理键盘、功能键(比如音量控制按键、开关按键等)、轨迹球、鼠标、操作杆，在此不再赘述。
进一步的，触控面板5071可覆盖在显示面板5061上，当触控面板5071检测到在其上或附近的触摸操作后，传送给处理器510以确定触摸事件的类型，随后处理器510根据触摸事件的类型在显示面板5061上提供相应的视觉输出。虽然在图5中，触控面板5071与显示面板5061是作为两个独立的部件来实现电子设备的输入和输出功能，但是在某些实施例中，可以将触控面板5071与显示面板5061集成而实现电子设备的输入和输出功能，具体此处不做限定。
接口单元508为外部装置与电子设备500连接的接口。例如，外部装置可以包括有线或无线头戴式耳机端口、外部电源(或电池充电器)端口、有线或无线数据端口、存储卡端口、用于连接具有识别模块的装置的端口、音频输入/输出(I/O)端口、视频I/O端口、耳机端口等等。接口单元508可以用于接收来自外部装置的输入(例如，数据信息、电力等等)并且将接收到的输入传输 到电子设备500内的一个或多个元件或者可以用于在电子设备500和外部装置之间传输数据。
存储器509可用于存储软件程序以及各种数据。存储器509可主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序(比如声音播放功能、图像播放功能等)等；存储数据区可存储根据手机的使用所创建的数据(比如音频数据、电话本等)等。此外，存储器509可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他易失性固态存储器件。
处理器510是电子设备的控制中心，利用各种接口和线路连接整个电子设备的各个部分，通过运行或执行存储在存储器509内的软件程序和/或模块，以及调用存储在存储器509内的数据，执行电子设备的各种功能和处理数据，从而对电子设备进行整体监控。处理器510可包括一个或多个处理单元；优选的，处理器510可集成应用处理器和调制解调处理器，其中，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调处理器主要处理无线通信。可以理解的是，上述调制解调处理器也可以不集成到处理器510中。
电子设备500还可以包括给各个部件供电的电源511(比如电池)，优选的，电源511可以通过电源管理系统与处理器510逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗管理等功能。
另外，电子设备500包括一些未示出的功能模块，在此不再赘述。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体 现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端(可以是手机，计算机，服务器，空调器，或者网络设备等)执行本申请各个实施例所述的方法。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。

Claims (10)

  1. 一种像素驱动电路，包括：
    包括多个像素电路(1)的像素阵列，所述像素阵列采用RGBG像素排列方式；
    沿所述像素阵列的第一方向排列的至少四条栅线(2)，相邻两条栅线(2)之间设置一行像素电路(1)，每行像素电路(1)对应一条栅线(2)；
    沿与所述第一方向垂直的第二方向排列、且与每条栅线(2)交叉设置的至少八条数据线(3)，每条数据线(3)与一列像素电路(1)中对应于同一颜色子像素的所述像素电路(1)连接；以及
    与所述数据线(3)连接的多路分配器电路(4)，所述多路分配器电路(4)用于控制所述数据线(3)连通集成电路IC芯片。
  2. 根据权利要求1所述的像素驱动电路，还包括：
    与所述IC芯片的输出端连接的阵列基板行驱动GOA单元(5)；
    所述GOA单元(5)包括第一时钟信号线(51)、第二时钟信号线(52)、第三时钟信号线(53)、第四时钟信号线(54)以及与奇数行栅线(2)连接的多个第一GOA电路(55)和与偶数行栅线(2)连接的多个第二GOA电路(56)；
    所述第一GOA电路(55)连接所述第一时钟信号线(51)和所述第二时钟信号线(52)，所述第二GOA电路(56)连接所述第三时钟信号线(53)和所述第四时钟信号线(54)；
    所述第一时钟信号线(51)和所述第二时钟信号线(52)的时序相反，所述第三时钟信号线(53)和所述第四时钟信号线(54)的时序相反。
  3. 根据权利要求2所述的像素驱动电路，其中，
    按照行数递增的排列顺序，各相邻的所述第一GOA电路(55)之间连接且形成奇数行栅线(2)的级传、各相邻的所述第二GOA电路(56)之间连接且形成偶数行栅线(2)的级传；
    其中，除最后一级所述第一GOA电路(55)外，每一级所述第一GOA电路(55)的输出端与相邻下一级所述第一GOA电路(55)的输入端连接； 除最后一级所述第二GOA电路(56)外，每一级所述第二GOA电路(56)的输出端与相邻下一级所述第二GOA电路(56)的输入端连接。
  4. 根据权利要求3所述的像素驱动电路，其中，
    对于相邻的奇数行栅线(2)和偶数行栅线(2)，其中，相对于奇数行栅线(2)对应的第一GOA电路(55)的时钟信号，偶数行栅线(2)对应的第二GOA电路(56)的时钟信号延后半个脉冲。
  5. 根据权利要求4所述的像素驱动电路，其中，所述数据线(3)包括第一类型数据线(31)、第二类型数据线(32)和第三类型数据线(33)；
    每列像素电路(1)为一电路组，对应相同颜色子像素的所述电路组为第一电路组，对应两个颜色子像素的所述电路组为第二电路组；
    所述第一类型数据线(31)与所述第二电路组中对应第一颜色子像素的像素电路(1)连接，所述第二类型数据线(32)与所述第二电路组中对应第二颜色子像素的像素电路(1)连接；
    所述第三类型数据线(33)与所述第一电路组中的所述像素电路(1)连接。
  6. 根据权利要求5所述的像素驱动电路，其中，
    所述第一类型数据线(31)、所述第二类型数据线(32)和所述第三类型数据线(33)的数量之和为所述像素电路(1)所对应的列数的两倍；
    所述第一类型数据线(31)、所述第二类型数据线(32)、两条所述第三类型数据线(33)、所述第二类型数据线(32)、所述第一类型数据线(31)和两条所述第三类型数据线(33)在所述第二方向上依次排列；
    其中，每条所述第三类型数据线(33)与所述第一电路组中半数的所述像素电路(1)连接，且与一条所述第三类型数据线(33)连接的至少两个所述像素电路(1)相邻或者间隔排布。
  7. 根据权利要求6所述的像素驱动电路，其中，所述多路分配器电路(4)包括：
    第一驱动线(41)、与所述第一驱动线(41)时序相反的第二驱动线(42)、至少四个第一开关(43)和至少四个第二开关(44)；
    所述第一驱动线(41)和所述第二驱动线(42)与所述IC芯片的输出端 连接；
    所述第一类型数据线(31)和各所述第一电路组中的一条所述第三类型数据线(33)对应于所述第一开关(43)，所述第二类型数据线(32)和各所述第一电路组中的另一条所述第三类型数据线(33)对应于所述第二开关(44)；
    所述第一开关(43)的控制端连接所述第一驱动线(41)，用于在所述第一驱动线(41)的控制下连通所述第一类型数据线(31)和对应的端口数据线、半数的所述第三类型数据线(33)和对应的端口数据线；
    所述第二开关(44)的控制端连接所述第二驱动线(42)，用于在所述第二驱动线(42)的控制下连通所述第二类型数据线(32)和对应的端口数据线、剩余半数的所述第三类型数据线(33)和对应的端口数据线；
    其中，各所述端口数据线连接至所述IC芯片的输出端。
  8. 根据权利要求7所述的像素驱动电路，其中，
    在所述第一驱动线(41)控制所述第一开关(43)导通时，在各栅线(2)对应的工作脉冲内，与所述第一类型数据线(31)连接的所述像素电路(1)处于工作状态、与对应于所述第一开关(43)的所述第三类型数据线(33)连接的所述像素电路(1)处于工作状态；
    在所述第二驱动线(42)控制所述第二开关(44)导通时，在各栅线(2)对应的工作脉冲内，与所述第二类型数据线(32)连接的所述像素电路(1)处于工作状态、与对应于所述第二开关(44)的所述第三类型数据线(33)连接的所述像素电路(1)处于工作状态。
  9. 一种显示面板，包括如权利要求1至8任一项所述的像素驱动电路。
  10. 一种电子设备，包括如权利要求9所述的显示面板。
PCT/CN2021/081767 2020-03-24 2021-03-19 像素驱动电路、显示面板及电子设备 Ceased WO2021190409A1 (zh)

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