WO2021196074A1 - 任务调度方法及装置 - Google Patents

任务调度方法及装置 Download PDF

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Publication number
WO2021196074A1
WO2021196074A1 PCT/CN2020/082729 CN2020082729W WO2021196074A1 WO 2021196074 A1 WO2021196074 A1 WO 2021196074A1 CN 2020082729 W CN2020082729 W CN 2020082729W WO 2021196074 A1 WO2021196074 A1 WO 2021196074A1
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Prior art keywords
algorithm
task
software component
tasks
scheduling
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English (en)
French (fr)
Inventor
何琦健
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Priority to PCT/CN2020/082729 priority Critical patent/WO2021196074A1/zh
Priority to EP20928698.8A priority patent/EP4120076A4/en
Priority to CN202080004240.2A priority patent/CN112513814B/zh
Publication of WO2021196074A1 publication Critical patent/WO2021196074A1/zh
Priority to US17/957,940 priority patent/US12333333B2/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5061—Partitioning or combining of resources
    • G06F9/5066—Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/542—Event management; Broadcasting; Multicasting; Notifications
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/48—Indexing scheme relating to G06F9/48
    • G06F2209/484—Precedence
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/50—Indexing scheme relating to G06F9/50
    • G06F2209/5017—Task decomposition

Definitions

  • This application relates to the field of smart cars, and in particular to a task scheduling method and device.
  • Automotive open system architecture (AUTOSAR) is an open and standardized software architecture developed for the automotive industry.
  • the embodiments of the present application provide a task scheduling method and device, which can solve the problem that the process of implementing a certain algorithm function through AUTOSAR is relatively complicated and the efficiency is low in the related art.
  • the present application provides a task scheduling method, which can be applied to an embedded device using AUTOSAR.
  • the embedded device includes a memory and a processor, the memory stores an interface function, and the processor is deployed with the first software Component and a second software component; the method may include: the interface function obtains registration information of the algorithm to be deployed, the algorithm includes a plurality of tasks, the registration information includes: relationship data used to describe the dependency between the plurality of tasks , And the configuration information of each task; the interface function generates a dependency graph of the multiple tasks according to the relationship data, the dependency graph includes multiple nodes, and each node is used to indicate a task; the interface function is then used in the
  • the memory records the mapping relationship between each node in the dependency graph and the configuration information of the task indicated to obtain the execution flow graph of the algorithm; then the first software component can create an algorithm instance based on the execution flow graph, and can The target task that meets the scheduling condition among the multiple tasks included in the algorithm is scheduled to the second software component, and the second software component can then execute the target
  • the registration information of the algorithm can be obtained and analyzed through the interface function, and the scheduling and execution of the tasks in the algorithm can be realized through the software components deployed in the processor.
  • developers do not need to perform complex configuration, which effectively simplifies the deployment process of the algorithm, and improves the efficiency of algorithm deployment and the efficiency of task scheduling and execution.
  • the process of the first software component creating an algorithm instance based on the execution flow graph may include: if the first software component determines that it satisfies the instance creation condition, creating an algorithm instance based on the execution flow graph, where the instance creation
  • the conditions can include one or more of the following conditions:
  • the total number of created instances of the first software component is less than the number threshold
  • the embedded device has resources for executing tasks in the algorithm.
  • the number threshold can be equal to 1 or can also be an integer greater than one. If the number threshold is an integer greater than 1, the first software component can create multiple algorithm instances in parallel, and the second software component can execute tasks in multiple algorithm instances in parallel, thereby effectively reducing the scheduling delay of algorithm instances. The execution cycle of the algorithm instance is shortened, and the utilization rate of the hardware resources of the embedded device is improved.
  • multiple second software components may be deployed in the processor; the first software component is based on the algorithm instance, and the target task that meets the scheduling conditions among the multiple tasks included in the algorithm is scheduled to the second software component
  • the process may include: the first software component determines the identification of the target task that meets the scheduling condition from the multiple tasks included in the algorithm based on the algorithm instance, and determines from the multiple second software components according to the identification of the target task
  • the target second software component used to execute the target task.
  • the first software component can send the target task identifier to the target second software component.
  • the target second software component can then execute the target task according to the identifier of the target task.
  • the first software component can schedule the target task to the pre-deployed second software component for execution without creating a process or thread in real time to execute the target task, the task scheduling delay can be effectively shortened.
  • the method may further include: after the second software component executes and completes the target task, sending a notification message to the first software component, where the notification message is used to indicate that the target task has been executed; the first software component The component can then respond to the notification message to update the status of the target task to a completed status.
  • the communication between different software components can be realized based on the operating environment layer in AUTOSAR.
  • the method may further include: the first software component responds to the notification message and detects the algorithm based on the algorithm instance Whether there is a target task that meets the scheduling conditions among the multiple tasks included.
  • the first software component can periodically perform task scheduling according to the scheduling cycle; or it can actively trigger the next task scheduling in response to the notification message sent by the second software component without waiting for the next scheduling cycle. This can effectively improve task scheduling efficiency.
  • the scheduling condition may include: the embedded device has resources required to execute the task, and the state of the task on which the task depends is a completed state.
  • the interface function first records the mapping relationship between each node in the dependency graph and the attribute information of the task it indicates in the memory to obtain the task flow graph of the algorithm; then records the task flow graph in the memory The mapping relationship between each node and the scheduling information of the task it indicates, thereby obtaining the execution flow graph of the algorithm.
  • the interface function can directly store the parsed execution flow graph in the memory
  • the first software component can directly query the data in the execution flow graph from the memory when creating an algorithm instance, without file parsing, which effectively reduces The scheduling delay of the task is reduced.
  • an embedded device adopts AUTOSAR, and the embedded device includes a memory and a processor, the memory stores an interface function, and a first software component and a second software component are deployed in the processor. Two software components; the interface function, the first software component, and the second software component can be used to implement the task scheduling method provided in the foregoing aspects.
  • a computer-readable storage medium is provided, and instructions are stored in the computer-readable storage medium.
  • the embedded device executes the instructions provided in the above-mentioned aspect.
  • the task scheduling method is provided.
  • a chip in yet another aspect, includes a programmable logic circuit and/or program instructions. When the chip is running, it is used to implement the task scheduling method provided in the above-mentioned aspect.
  • the embodiments of the present application provide a task scheduling method and device.
  • the solution can obtain and parse algorithm registration information through an interface function, and can implement scheduling and execution of tasks in the algorithm through software components deployed in the processor.
  • developers do not need to perform complex configuration, which effectively simplifies the deployment process of the algorithm, and improves the deployment efficiency of the algorithm and the efficiency of task scheduling.
  • the interface function can directly store the parsed execution flow graph in the memory
  • the software component can directly query the data in the execution flow graph from the memory when creating an algorithm instance without file parsing, so it effectively reduces The scheduling delay of the task is reduced.
  • the processor can be pre-deployed with software components for implementing task scheduling and execution, there is no need for the processor to create processes or threads in real time during the running process, so the task scheduling delay can also be effectively reduced.
  • FIG. 1 is an architecture diagram of AUTOSAR used in an embedded device provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of the functional structure of a perception scheduling framework provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of an embedded device using AUTOSAR provided by an embodiment of the present application.
  • FIG. 4 is a flowchart of a task scheduling method provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of generating an execution flow graph provided by an embodiment of the present application.
  • FIG. 6 is a flowchart of a method for generating an execution flow diagram of an algorithm provided by an embodiment of the present application
  • FIG. 7 is a schematic diagram of creating multiple algorithm instances based on one execution flow graph according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of software components deployed in a processor provided by an embodiment of the present application.
  • FIG. 9 is a flowchart of a method for scheduling a target task provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of a state of a maintenance task provided by an embodiment of the present application.
  • FIG. 11 is a flowchart of another task scheduling method provided by an embodiment of the present application.
  • FIG. 12 is a flowchart of a method for creating an algorithm instance provided by an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of another embedded device using AUTOSAR provided by an embodiment of the present application.
  • an algorithm needs to be deployed in AUTOSAR to realize the function of the algorithm, it needs to go through the following configuration process:
  • the developer uses the AUTOSAR system configuration tool to complete the software component (SWC) design and The design of the port for interaction between SWCs generates algorithm-related SWC description files.
  • ECU electronic control unit
  • OS Tasks operating system tasks
  • developers need to manually configure the OS The properties of Task, get multiple configuration files.
  • the code generation tool is used to convert the multiple configuration files into code, and the code is compiled and linked to generate an executable file for realizing the function of the algorithm.
  • the above configuration process is complicated and requires developers to be proficient in the entire set of AUTOSAR development tool chain to achieve, and the efficiency is low.
  • FIG. 1 is an architecture diagram of AUTOSAR used in an embedded device provided by an embodiment of the present application.
  • the AUTOSAR 01 may include an application layer (application layer) 011 and a runtime environment (RTE) Layer 012 and basic software (BSW) layer 013 running on the microcontroller 02.
  • the AUTOSAR 01 may also include a perceptual scheduling framework (perceptual scheduling framework) 013 located between the application layer 011 and the RTE layer 012.
  • the PSF 014 can uniformly manage the scheduling and execution of tasks in the upper-layer algorithm (also called business).
  • the upper-layer algorithm does not need to pay attention to how the SWC communicates and how the tasks are scheduled and executed, so that the algorithm is decoupled from AUTOSAR 01, which can solve the problem.
  • AUTOSAR 01 the deployment algorithm configuration process is long and the efficiency is low.
  • the BSW layer 013 may include a safety operation system (safety operation system, safety OS) 0131, a service layer (services layer) 0132, an ECU abstraction layer (ECU abstraction layer) 0133, and a microcontroller abstraction layer (micro-controller abstraction layer) 0134 and complex device drivers (complex device drivers) 0135.
  • safety operation system safety operation system
  • service layer service layer
  • ECU abstraction layer ECU abstraction layer
  • microcontroller abstraction layer micro-controller abstraction layer
  • complex device drivers complex device drivers
  • Fig. 2 is a schematic diagram of the functional structure of a PSF 014 provided by an embodiment of the present application.
  • the PSF 014 may include two functional modules: task orchestration (TO) module 0141 and task management (task management). , TM) Module 0142.
  • TO task orchestration
  • TM task management
  • the task orchestration module 0141 is mainly used to implement static orchestration of tasks included in the algorithm to be deployed.
  • the task orchestration module 0141 may include the following four sub-modules:
  • the algorithm registration sub-module 1a is responsible for realizing algorithm registration, that is, obtaining registration information of the algorithm, parsing the registration information and passing it to other sub-modules.
  • the algorithm may include multiple tasks, and the registration information of the algorithm may include relationship data used to describe the dependencies of the multiple tasks, and configuration information of each task.
  • the configuration information may include the attribute information of the task and the resource of the task. Dependent information and task scheduling constraint information, etc.
  • the directed acyclic graph (DAG) management sub-module 1b is responsible for analyzing the execution dependency relationship between multiple tasks included in the algorithm, and generating a DAG used to describe the dependency relationship between the multiple tasks. Due to the high real-time requirements of the vehicle-mounted scene, the traditional way of resolving dependency relationships by reading configuration files becomes unrealistic. For this reason, the embodiment of the present application adopts DAG to store dependency relationships between tasks in the memory.
  • DAG directed acyclic graph
  • the task attribute management sub-module 1c is responsible for analyzing the attribute information of each task included in the algorithm, and associating the attribute information of the task with the corresponding task node in the DAG, thereby generating a task flow graph (TFG) with task attribute information. ).
  • the attribute information of the task may include the name of the task and the storage address of the task.
  • each task may include one or more functions for realizing a specific function.
  • the task name is the function name
  • the storage address of the task is the storage address of the function
  • the storage address may be a function pointer.
  • the task scheduling information management sub-module 1d is responsible for parsing the scheduling information of the tasks included in the algorithm, and associating the scheduling information with the corresponding nodes in the TFG, thereby generating an execution flow graph that can be scheduled and executed by the task management module 0142. graph, EFG).
  • the task scheduling information management submodule 1d may provide an interface for obtaining the EFG to the task management module 0142.
  • the scheduling information may include resource dependency information and scheduling constraint information of the task.
  • the resource dependency information may include: the memory on which the task depends, and the identification of the computing unit used to execute the task in the processor.
  • the scheduling constraint information may include the starting time of the task and the maximum running time after the task is started.
  • the task management module 0142 is mainly used to realize the dynamic management of tasks. As shown in FIG. 2, the task management module 0142 may include the following four sub-modules:
  • the task state machine management sub-module 2a is used to manage the state transition of each task in the algorithm.
  • the execution flow graph instance management sub-module 2b is used to create and delete execution flow graph instances, and to analyze the resources on which tasks in the execution flow graph depend.
  • the execution flow graph instance scheduling sub-module 2c is used to reasonably schedule task execution according to the state transition of the task.
  • Fig. 3 is a schematic structural diagram of an embedded device using AUTOSAR provided by an embodiment of the present application.
  • the embedded device can be an in-vehicle device, and can be applied to a smart car, a connected car or a new energy car.
  • the embedded device may include a memory 10 and a processor 20.
  • An interface function 101 is stored in the memory 10, and a first SWC 201 and a second SWC 202 are deployed in the processor 20.
  • the processor 20 may be a microcontroller as shown in FIG. 1, and may also be referred to as a micro-controller unit (MCU).
  • the interface function 101 can be used to implement the function of the task scheduling module 0141 in the PSF 014.
  • the first SWC 201 may be used to implement the function of the task management module 0142 in the PSF 014, that is, the first SWC 201 is mainly used to implement task scheduling, so the first SWC 201 may also be referred to as a scheduling SWC or a master (master). )SWC.
  • the second SWC 202 is used to perform tasks, so the second SWC 202 may also be referred to as a worker SWC.
  • the embedded device provided by the embodiment of the present application can realize task scheduling and execution through the first SWC and the second SWC pre-deployed in the processor, so there is no need for the processor to create processes or threads in real time during the running process to schedule execution. Tasks, which can effectively reduce the scheduling delay of tasks.
  • FIG. 4 is a flowchart of a task scheduling method provided by an embodiment of the present application. The method can be applied to the embedded device shown in FIG. 3. Referring to Figure 4, the method may include:
  • Step 401 The interface function obtains the registration information of the algorithm to be deployed.
  • the algorithm may include multiple tasks, and the registration information may include: relationship data used to describe the dependency relationship between the multiple tasks, and configuration information of each task.
  • the configuration information may include attribute information of the task, resource dependency information of the task, scheduling constraint information of the task, and the like.
  • the attribute information of the task may include the name of the task and the storage address of the task.
  • each task may include one or more functions for realizing a specific function.
  • the task name is the function name
  • the storage address of the task is the storage address of the function
  • the storage address may be a function pointer.
  • multiple tasks included in the algorithm can be stored in the memory of the embedded device.
  • the scheduling information may include resource dependency information and scheduling constraint information of the task.
  • the resource dependency information may include: the memory on which the task depends, and the identification of the computing unit used to execute the task in the processor.
  • the scheduling constraint information may include the starting time of the task and the maximum running time after the task is started.
  • the algorithm to be deployed may be an algorithm related to an advanced driving assistance system (ADAS).
  • ADAS advanced driving assistance system
  • it can be a millimeter-wave radar algorithm, which can be used to implement functions such as detection (such as distance detection, speed detection, or obstacle detection, etc.) and tracking.
  • the processor can start to run the interface function in the memory, and the interface function can further implement the method shown in step 401 above.
  • Step 402 The interface function generates a dependency relationship graph of multiple tasks according to the relationship data.
  • the interface function After the interface function obtains the registration information, it can analyze the relationship data in the registration information and generate a dependency graph that can reflect the dependency between the multiple tasks.
  • the dependency graph may include multiple nodes, each A node is used to indicate a task.
  • the dependency graph generated by the interface function may be a DAG.
  • the dependency relationship graph may be represented by an adjacency linked list or an adjacency matrix, that is, the dependency relationship graph may be stored in the form of an adjacency linked list or an adjacency matrix.
  • the interface function can generate the DAG as shown in Figure 5 by analyzing the dependencies of the five tasks.
  • Step 403 The interface function records in the memory the mapping relationship between each node in the dependency graph and the configuration information of the task indicated to obtain an execution flow graph of the algorithm.
  • the interface function can associate each node with the configuration information of the task indicated by recording the mapping relationship between each node and the configuration information of the task indicated to obtain the execution flow graph of the algorithm.
  • the embedded device generally does not support a file system, so the interface function can use the target data structure to directly store the execution flow graph in the memory.
  • the target data structure may be a JSON (JavaScript object notation, JS object notation) data structure or an extensible markup language (XML) data structure.
  • JSON JavaScript object notation, JS object notation
  • XML extensible markup language
  • the configuration information of each task may include: attribute information of each task and scheduling information of each task.
  • the process of generating the execution flow graph of the algorithm may include:
  • Step 4031 The interface function records the mapping relationship between each node in the dependency graph and the attribute information of the task indicated by the interface function in the memory to obtain the task flow graph of the algorithm.
  • the interface function can first associate each node in the dependency graph with the attribute information of the task indicated to obtain the task flow graph of the algorithm.
  • Step 4032 The interface function records in the memory the mapping relationship between each node in the task flow graph and the scheduling information of the task indicated to obtain an execution flow graph of the algorithm.
  • the interface function can associate each node in the task flow graph with the scheduling information of the task it indicates, thereby obtaining an execution flow graph that can be scheduled by the first SWC deployed in the processor.
  • mapping relationship recorded in the memory of the interface function may be expressed in the form of a mapping table, that is, the mapping relationship may be stored in the memory in the form of a mapping table.
  • Step 404 The first SWC detects whether it meets the instance creation condition.
  • the first SWC deployed in the processor may run periodically according to a preset scheduling period, that is, the processor may periodically trigger the first SWC according to the scheduling period. After the first SWC starts to run, it can first detect whether the current instance creation conditions are met. If the first SWC determines that the instance creation condition is satisfied, step 405 may be continued; if the first SWC determines that the instance creation condition is not satisfied, step 406 may be performed.
  • instance creation conditions may include one or more of the following conditions:
  • the total number of instances created by the first SWC is less than the number threshold, which is the upper limit of the number of instances that the processor of the embedded device can run in parallel;
  • the embedded device has resources for executing tasks in the algorithm.
  • the first SWC may serially schedule algorithm instances, that is, each scheduling period can only execute tasks in one algorithm instance.
  • the number threshold may be 1.
  • the instance creation condition may be: the total number of instances created by the first SWC is less than one. That is, the first SWC may execute step 405 when it detects that the number of created instances is 0.
  • the first SWC can schedule multiple algorithm instances in parallel, that is, each scheduling period can execute tasks in multiple algorithm instances. Therefore, in this implementation manner, the number threshold may be an integer greater than 1, for example, 3 or 5, etc. Correspondingly, the instance creation condition may include that the total number of instances created by the first SWC is less than the number threshold.
  • the multiple algorithm instances of the parallel scheduling may be created based on one execution flow graph, or may be created based on different execution flow graphs, which is not limited in the embodiment of the present application.
  • the instance creation condition may further include: the embedded device has resources for executing the tasks in the execution flow graph.
  • the first SWC detects that an algorithm instance of an execution flow graph has been created, and the embedded device also has the ability to execute Based on the resources of the tasks in the execution flow graph, the first SWC can create an algorithm instance again based on the execution flow graph, and schedule and execute the tasks in the algorithm instance, so as to improve the scheduling efficiency of the algorithm.
  • a certain execution flow graph includes a total of 6 tasks from tasks T1 to T6.
  • the first SWC creates algorithm instance 1 based on the execution flow graph, and schedules and executes the tasks in algorithm instance 1 in turn. If the first SWC detects in the second scheduling cycle that the tasks T1 and T2 in the algorithm instance 1 have been executed, the task T3 is being executed, and it is detected that the computing unit of the second SWC used to execute the tasks T1 and T2 is in In the idle state, algorithm instance 2 can be created based on the execution flow graph, and tasks T1 and T2 can be executed.
  • the first SWC detects in the third scheduling period that the task T1 in the algorithm instance 2 has been executed, the task T2 is being executed, and the computing unit to which the second SWC used to execute the task T1 belongs is in an idle state, then the first SWC can continue to create algorithm instance 3 based on the execution flow graph, and can execute the task T1.
  • the execution cycle ensures that the algorithm instance can be executed within the specified execution cycle.
  • the refresh time of the target reported by the radar can be significantly shortened.
  • Step 405 The first SWC creates an algorithm instance based on the execution flow graph.
  • the first SWC after the first SWC detects that the instance creation condition is met, it can query the execution flow graph from the memory through the interface provided by the interface function, and create an algorithm instance based on the execution flow graph.
  • creating an algorithm instance may refer to: obtaining the address of the execution flow graph and saving it.
  • the first SWC can also create a new data structure in the memory for recording the execution status and execution time of each task, where the execution time includes the start time (also referred to as the start time) and the end time of the task.
  • Step 406 The first SWC detects, based on the algorithm instance, whether there is a target task that meets the scheduling condition among the multiple tasks included in the algorithm.
  • the first SWC after the first SWC has created the algorithm instance, it can poll the configuration information of each task based on the algorithm instance, and then detect whether there is a target task that meets the scheduling conditions among the multiple tasks. If the first SWC determines that there is a target task that meets the scheduling condition among the multiple tasks included in the algorithm, step 407 may be performed; if the first SWC determines that there is no target task that meets the scheduling condition among the multiple tasks included in the algorithm, then You can end the operation.
  • the scheduling condition may at least include: the state of the task on which the task depends is a completed state. If the configuration information of each task also includes scheduling information, and the scheduling information includes resource dependency information, the scheduling condition may also include: the resource indicated by the resource dependency information in the embedded device is in an idle state, where the resource may include memory Resources and computing resources, computing resources are also processor resources. If the scheduling information further includes scheduling constraint information, the scheduling condition may further include: the current operating environment satisfies the scheduling constraint information, for example, the current time is the specified start time of the task.
  • the first SWC can detect whether there is a target task that meets the scheduling condition among the multiple tasks included in the algorithm based on the algorithm instance.
  • the first SWC may determine that an algorithm instance already exists in the processor when it detects that it does not meet the instance creation condition, so it may directly detect whether there is a target task that meets the scheduling condition among the multiple tasks included in the algorithm instance.
  • Step 407 The first SWC schedules the target task to the second SWC.
  • the target task can be scheduled to the second SWC for execution.
  • multiple second SWCs may be pre-deployed in the processor, and each second SWC may be used to execute part of the tasks in the algorithm.
  • the processor may include multiple computing units, and each computing unit may refer to a processor core.
  • the first SWC may be deployed in a computing unit.
  • the first SWC may be deployed in a computing unit with a higher security level.
  • Each second SWC can be deployed in one computing unit, the second SWC and the first SWC are deployed in different computing units, and each computing unit can be deployed with one or more second SWCs.
  • the process of scheduling the target task by the first SWC to the second SWC may include:
  • Step 4071 the first SWC determines the identity of the target task.
  • the identification of each task can be the task name of the standard task, or can also be an identification (identification, ID) uniquely assigned to each task after the interface function obtains the registration information.
  • Step 4072 the first SWC determines the target second SWC used to execute the target task from the multiple second SWCs according to the identifier of the target task.
  • the first SWC may query the configuration information of the target task from the execution flow graph, and the configuration information may record the identification of the computing unit used to execute the target task.
  • the first SWC may further determine the second SWC for executing the target task based on the type of the target task and the correspondence between the type of the task stored in advance and the identifier of the second SWC.
  • the first SWC may directly determine the target second SWC used to execute the target task from the configuration information of the target task.
  • Step 4073 The first SWC sends the identifier of the target task to the target second SWC.
  • the target task identifier can be sent to the target second SWC.
  • Step 408 The second SWC executes the target task.
  • the second SWC After receiving the identifier of the target task scheduled by the first SWC, the second SWC can query the configuration information of the target task according to the identifier, and determine the storage address of the target task, such as the function pointer of the target task. After that, the second SWC can perform the target task.
  • Step 409 The second SWC sends a notification message to the first SWC, where the notification message is used to indicate that the target task has been executed.
  • a notification message can be sent to the first SWC.
  • the communication between the first SWC and the second SWC may be implemented based on the RTE in AUTOSAR.
  • the RTE may implement communication between different SWCs through shared memory and inter-core interruption.
  • Step 410 In response to the notification message, the first SWC updates the status of the target task to a completed status.
  • the first SWC After the first SWC receives the notification message sent by the second SWC, it can respond to the notification message and update the status of the target task to a completed status.
  • the first SWC may also continue to perform step 406 in response to the notification message to detect whether there is a target task that meets the scheduling condition among the multiple tasks included in the algorithm. That is, the second SWC does not need to wait until the next scheduling period to actively trigger the next task scheduling. Compared with periodically executing task scheduling according to the scheduling period, this active triggering method can effectively improve task scheduling efficiency.
  • the number of second SWCs deployed in the processor may be determined according to the function of the algorithm to be deployed. For example, suppose the algorithm to be deployed can be divided into N sub-functions, N is an integer greater than 1, and each sub-function is implemented by one or more tasks, that is, each sub-function can include one or more tasks of the same type. Then, N second SWCs corresponding to the N sub-functions may be deployed in the processor, and each second SWC may perform various tasks for implementing one sub-function.
  • the first SWC can store the correspondence between each sub-function (that is, the type of task) and the identifier of the second SWC.
  • the embodiments of the present application provide a task scheduling method, which can obtain and parse algorithm registration information through an interface function, and can implement scheduling and execution of tasks in the algorithm through SWC.
  • a task scheduling method which can obtain and parse algorithm registration information through an interface function, and can implement scheduling and execution of tasks in the algorithm through SWC.
  • developers do not need to perform complex configuration, which effectively simplifies the deployment process of the algorithm, and improves the deployment efficiency of the algorithm and the efficiency of task scheduling.
  • the interface function can directly store the parsed execution flow graph in the memory
  • SWC can directly query the data in the execution flow graph from the memory when creating an algorithm instance, without file parsing, which effectively reduces
  • the scheduling delay of the task is reduced.
  • the processor can pre-deploy the SWC used to implement task scheduling and execution, there is no need for the processor to create processes or threads in real time during the running process, so the task scheduling delay can also be effectively reduced.
  • the task scheduling method provided by the embodiment of the present application has a small scheduling delay and a high scheduling efficiency, and can meet the requirements of high real-time performance in an in-vehicle scenario.
  • FIG. 10 is a schematic diagram of a state of a first SWC maintenance task provided by an embodiment of the present application.
  • the first SWC can initialize the state of each task in the algorithm instance to a waiting state after creating an algorithm instance based on a certain execution flow graph.
  • the status of the task can be updated to a ready state.
  • the first SWC may update the state of the task to a running state after detecting that the resource on which the task depends is idle, that is, meeting the scheduling condition and scheduling the task to the second SWC for execution.
  • the state of the task may be updated to an abnormal state.
  • the first SWC detects the reset command, it can update the status of the task in the abnormal state to the waiting state.
  • the first SWC detects that a certain task has ended normally without overtime (that is, the execution time of the task does not exceed the time specified in the configuration information)
  • the status of the task can be updated to a finished state.
  • the first SWC can also restore the states of all tasks to the waiting state when it detects that all tasks in the algorithm instance have been executed (that is, the states of all tasks are completed). Since the first SWC can record the state of each task in the memory, after all tasks in the algorithm instance are executed, the states of all tasks are restored to the waiting state, which can release the memory.
  • FIG. 11 is a flowchart of another task scheduling method provided by an embodiment of the present application, and the method may be applied to the first SWC. As shown in Figure 11, the method may include:
  • Step 1101 It is detected whether the processing of the algorithm instance is completed.
  • the first SWC after the first SWC creates an algorithm instance, before scheduling and executing tasks in the algorithm instance, it can first detect whether the algorithm instance is processed, for example, it can detect whether the state of the algorithm instance is a completed state. If it is determined that the processing of the algorithm instance is completed, the first SWC may end the operation; if it is determined that the processing of the algorithm instance is not completed, the first SWC may continue to perform step 1102.
  • Step 1102 It is detected whether the task in the completed state has timed out.
  • the first SWC may continue to detect whether the task in the completed state in the algorithm instance has timed out, that is, whether the execution time of the completed task exceeds the maximum running time specified in the configuration information. If the task has timed out, step 1103 can be performed; if the task has not timed out, step 1104 can be performed.
  • Step 1103 Update the state of the algorithm instance to an abnormal state.
  • the first SWC may update the state of the algorithm instance to an abnormal state.
  • Step 1104 It is detected whether the status of all tasks is a completed status.
  • the first SWC detects that the task in the completed state has not timed out, it can continue to detect whether the states of all tasks are in the completed state, that is, whether all tasks in the algorithm instance are executed.
  • step 1105 can be executed; if the status of any task is not in the completed state, step 1106 can be executed.
  • Step 1105 Update the state of the algorithm instance to a completed state.
  • the first SWC detects that the states of all tasks in the algorithm instance are in the completed state, it can be determined that all tasks in the algorithm instance have been executed, and therefore the state of the algorithm instance can be updated to the completed state.
  • Step 1106 Update the running time of all tasks in the running state.
  • the first SWC detects that the state of any task in the algorithm instance is not in the completed state, it can update the running time of all tasks in the running state.
  • Step 1107 Detect whether the state of the dependent task exists as a completed task.
  • step 1108 can be executed; if it does not exist, the operation can be ended.
  • this step 1107 reference may be made to the above step 406.
  • Step 1108 Update the status of the task to a ready-to-complete status.
  • the status of the task can be updated to the ready to complete status.
  • Step 1109 Schedule the task to the second SWC for execution.
  • the first SWC may then schedule tasks in the ready-to-complete state to the second SWC for execution.
  • this step 1109 reference may be made to the foregoing step 407 and step 408.
  • Step 1110 Update the status of the task to the running status.
  • the status of the task can be updated to the running status.
  • FIG. 12 is a flowchart of a method for creating an algorithm instance provided by an embodiment of the present application, and the method can be applied to the first SWC. As shown in Figure 12, the method may include:
  • Step 1201 Acquire the type of execution flow graph according to the algorithm configuration information.
  • the first SWC After the first SWC detects that the instance creation conditions are met, it may first determine the type of execution flow graph of the instance that it can create according to the algorithm configuration information in the memory. Among them, the algorithm configuration information may be pre-written into the memory by the developer, or may also be externally configured.
  • Step 1202 Create a corresponding type of algorithm instance according to the type of execution flow graph.
  • the first SWC can query the execution flow graph of the same type from the memory according to the determined type of the execution flow graph, and create an algorithm instance based on the execution flow graph of this type.
  • Step 1203 Initialize the task in the algorithm instance to a waiting state.
  • the states of all tasks in the algorithm instance can be initialized to a waiting state.
  • Step 1204 Validate system configuration parameters.
  • the system configuration parameters can be validated.
  • the system configuration parameters may include the installation position of the radar, and the external configuration parameters of the radar.
  • the method provided by the embodiment of the present application adds a PSF 014 between the AUTOSAR application layer 011 and the RTE layer 012.
  • the PSF 014 can uniformly manage the scheduling and execution of tasks in the upper algorithm, thereby achieving the following benefits Effect:
  • the algorithm is decoupled from the original AUTOSAR framework, that is, the PSF is responsible for the registration and execution of the algorithm.
  • the algorithm has no perception of the AUTOSAR framework.
  • the change of the algorithm does not need to reconfigure AUTOSAR, which effectively improves the scalability and scalability of AUTOSAR. Evolutionary.
  • the algorithm does not perceive the execution timing and status of tasks, which can avoid the performance loss caused by unnecessary tasks waking up to sleep.
  • PSF can support the simultaneous execution of multiple algorithm instances through pipeline scheduling, when the previous algorithm instance has not been executed, the next round of algorithm instances is started, which can shorten the execution cycle of the algorithm.
  • the embodiment of the present application also provides an embedded device, the embedded device adopts AUTOSAR, and as shown in FIG. 3, the embedded device includes a memory 10 and a processor 20, the memory 10 stores an interface function 101, the A first SWC 201 and a second SWC 202 are deployed in the processor 20.
  • the interface function 101 can be used to:
  • Acquiring registration information of an algorithm to be deployed the algorithm including a plurality of tasks, the registration information including: relationship data used to describe the dependency between the plurality of tasks, and configuration information of each task;
  • the dependency graph including multiple nodes, and each node is used to indicate a task
  • mapping relationship between each node in the dependency graph and the configuration information of the task indicated by it is recorded in the memory to obtain an execution flow graph of the algorithm.
  • the first SWC 201 can be used to: create an algorithm instance based on the execution flow graph, and based on the algorithm instance, schedule target tasks that satisfy scheduling conditions among the multiple tasks included in the algorithm to the second SWC 202;
  • the second SWC 202 can be used to execute the target task.
  • the functional implementation of the interface function 101 can refer to the related descriptions of steps 401 to 403 in the above method embodiment; the functional implementation of the first SWC 201 can refer to the related descriptions of step 405 and step 407 in the above method embodiment;
  • the functional realization of the second SWC 202 reference may be made to the related description of step 408 in the foregoing method embodiment.
  • the first SWC 201 can be used for:
  • an algorithm instance is created based on the execution flow graph, where the instance creation conditions include one or more of the following conditions: the total number of created instances is less than the number threshold; the embedded device Has the resources needed to perform the tasks in the algorithm.
  • multiple second SWCs 202 may be deployed in the processor; the first SWC 201 may be used for:
  • the identification of the target task that satisfies the scheduling conditions is determined from the multiple tasks included in the algorithm; the target second SWC used to execute the target task is determined from the plurality of second SWCs according to the identification of the target task ; Send the target task identifier to the target second SWC.
  • the second SWC 202 may also be used to send a notification message to the first SWC 201 after the target task is executed and completed, and the notification message is used to indicate that the target task has been executed.
  • the first SWC 201 can also be used to update the status of the target task to a completed status in response to the notification message.
  • step 409 For the functional realization of the second SWC 202, reference may also be made to the related description of step 409 in the foregoing method embodiment.
  • step 410 For the functional realization of step 410 in the foregoing method embodiment.
  • the first SWC 201 may also be used to: in response to the notification message, detect whether there is a target task that meets the scheduling condition among the multiple tasks included in the algorithm based on the algorithm instance.
  • the scheduling condition may include: the embedded device has resources required to execute the task, and the state of the task on which the task depends is a completed state.
  • the configuration information may include: attribute information of each task and scheduling information of each task; the interface function 101 may be used for:
  • mapping relationship between each node in the task flow graph and the scheduling information of the task indicated by it is recorded in the memory to obtain the execution flow graph of the algorithm.
  • the embodiments of the present application provide an embedded device, which can obtain and parse the registration information of the algorithm through the interface function in the memory, and can realize the registration information of the algorithm through the SWC deployed in the processor.
  • Scheduled execution of tasks During the deployment of the algorithm and task scheduling, developers do not need to perform complex configuration, which effectively simplifies the deployment process of the algorithm, and improves the deployment efficiency of the algorithm and the efficiency of task scheduling.
  • the interface function can directly store the parsed execution flow graph in the memory
  • SWC can directly query the data in the execution flow graph from the memory when creating an algorithm instance, without file parsing, which effectively reduces The scheduling delay of the task is reduced.
  • the processor can pre-deploy the SWC used to implement task scheduling and execution, there is no need for the processor to create processes or threads in real time during the running process, so the task scheduling delay can also be effectively reduced.
  • the embedded device can be implemented by an application-specific integrated circuit (ASIC) or a programmable logic device (PLD).
  • ASIC application-specific integrated circuit
  • PLD programmable logic device
  • the above PLD can be a complex program.
  • Logic device complex programmable logical device, CPLD
  • field-programmable gate array field-programmable gate array
  • FPGA field-programmable gate array
  • GAL general array logic
  • FIG. 13 is a schematic structural diagram of another embedded device provided by an embodiment of the present application.
  • the embedded device may include: a processor 1301, a memory 1302, a memory 1303, a network interface 1304, and a bus 1305.
  • the bus 1305 is used to connect the processor 1301, the memory 1302, the memory 1303, and the network interface 1304.
  • the communication connection with other devices can be realized through the network interface 1304 (which can be wired or wireless).
  • a computer program 13031 is stored in the memory 1303, and the computer program 13031 is used to implement various application functions.
  • the processor 1301 may be a CPU, and the processor 1301 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays ( FPGA), GPU or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • DSP digital signal processors
  • ASIC application-specific integrated circuits
  • FPGA field programmable gate arrays
  • GPU GPU or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • the general-purpose processor may be a microprocessor or any conventional processor.
  • the memory 1303 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory can be read-only memory (ROM), programmable read-only memory (programmable ROM, PROM), erasable programmable read-only memory (erasable PROM, EPROM), and electrically available Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • the volatile memory may be random access memory (RAM), which is used as an external cache.
  • RAM random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • Double data rate synchronous dynamic random access memory double data date SDRAM, DDR SDRAM
  • enhanced SDRAM enhanced synchronous dynamic random access memory
  • SLDRAM synchronous connection dynamic random access memory
  • direct rambus RAM direct rambus RAM
  • bus 1305 may also include a power bus, a control bus, and a status signal bus. However, for clear description, various buses are marked as bus 1305 in the figure.
  • the processor 1301 is configured to execute an interface function in the memory 1302 and a computer program stored in the memory 1303, and the processor 1301 implements the method shown in the foregoing method embodiment by executing the interface function and the computer program 13031.
  • the embodiment of the present application also provides a computer-readable storage medium that stores instructions in the computer-readable storage medium, and when the computer-readable storage medium runs on an embedded device, the computer is caused to execute as described in the foregoing method embodiments. Indicates the method.
  • the embodiment of the present application also provides a computer program product containing instructions, which when the computer program product runs on an embedded device, causes the computer to execute the method shown in the above method embodiment.
  • An embodiment of the present application also provides a chip, which includes a programmable logic circuit and/or program instructions, and is used to implement the task scheduling method provided in the above-mentioned aspect when the chip is running.
  • the program can be stored in a computer-readable storage medium.
  • the storage medium mentioned can be a read-only memory, a magnetic disk or an optical disk, etc.

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Abstract

本申请公开了一种任务调度方法及装置，属于智能汽车领域，该方法可以应用于采用汽车开放系统架构的嵌入式设备，该嵌入式设备包括内存和处理器，该内存中存储有接口函数，该处理器中部署有第一软件组件以及第二软件组件。该方案可以通过该接口函数获取并解析待部署的算法的注册信息，并可以通过该软件组件实现对算法中的任务的调度执行。由于该算法的部署以及任务的调度过程中，无需开发人员进行复杂的配置，应用在智能汽车、网联汽车、新能源汽车上，能够有效简化算法的部署流程，提高了算法的部署效率以及任务的调度效率。

Description

任务调度方法及装置 技术领域
本申请涉及智能汽车领域，特别涉及一种任务调度方法及装置。
背景技术
汽车开放系统架构(automotive open system architecture，AUTOSAR)是为汽车工业开发的一个开放的且标准化的软件架构。
相关技术中，当需要在AUTOSAR中部署某种算法，使其实现该算法的功能时，需要开发人员使用AUTOSAR的系统配置工具、电子控制单元(electronic control unit，ECU)配置工具以及代码生成工具对算法进行一系列的配置，最终生成用于实现该算法的功能的可执行文件。
但是，相关技术中通过AUTOSAR实现某种算法的功能的流程较为复杂，效率较低。
发明内容
本申请实施例提供了一种任务调度方法及装置，可以解决相关技术中通过AUTOSAR实现某种算法的功能的流程较为复杂，效率较低的问题。
一方面，本申请提供了一种任务调度方法，可以应用于采用AUTOSAR的嵌入式设备，该嵌入式设备包括内存和处理器，该内存中存储有接口函数，该处理器中部署有第一软件组件以及第二软件组件；该方法可以包括：接口函数获取待部署的算法的注册信息，该算法包括多个任务，该注册信息包括：用于描述该多个任务之间的依赖关系的关系数据，以及每个任务的配置信息；接口函数根据该关系数据生成该多个任务的依赖关系图，该依赖关系图包括多个节点，每个节点用于指示一个该任务；该接口函数进而在该内存中记录该依赖关系图中的每个节点与其所指示的任务的配置信息的映射关系，得到该算法的执行流图；之后该第一软件组件可以基于该执行流图创建算法实例，并可以将该算法包括的多个任务中满足调度条件的目标任务调度至该第二软件组件，该第二软件组件进而可以执行该目标任务。
本申请提供的方法，可以通过接口函数获取并解析算法的注册信息，并可以通过处理器中部署的软件组件实现对算法中的任务的调度和执行。该算法的部署以及任务的调度和执行过程中，无需开发人员进行复杂的配置，有效简化了算法的部署流程，提高了算法的部署效率以及任务的调度和执行的效率。
可选的，该第一软件组件基于该执行流图创建算法实例的过程可以包括：若该第一软件组件确定其满足实例创建条件，则基于该执行流图创建算法实例，其中，该实例创建条件可以包括下述条件中的一种或多种：
该第一软件组件已创建的实例的总数小于数量阈值；
该嵌入式设备中具备用于执行该算法中的任务的资源。
其中，该数量阈值可以等于1或者也可以为大于1的整数。若该数量阈值为大于1的整数，则该第一软件组件可以并行创建多个算法实例，第二软件组件可以并行执行多个算法实 例中的任务，从而有效降低了算法实例的调度时延，缩短了算法实例的执行周期，且提高了对嵌入式设备硬件资源的利用率。
可选的，该处理器中可以部署有多个第二软件组件；该第一软件组件基于该算法实例，将该算法包括的多个任务中满足调度条件的目标任务调度至该第二软件组件的过程可以包括：该第一软件组件基于该算法实例，从算法包括的多个任务中确定满足调度条件的目标任务的标识，并根据该目标任务的标识，从多个第二软件组件中确定用于执行该目标任务的目标第二软件组件，之后，该第一软件组件即可将该目标任务的标识发送至该目标第二软件组件。目标第二软件组件进而可以根据目标任务的标识执行该目标任务。
由于第一软件组件可以将目标任务调度至预先部署好的第二软件组件中执行，而无需再实时创建进程或线程来执行该目标任务，因此可以有效缩短任务的调度时延。
可选的，该方法还可以包括：在该第二软件组件执行完成该目标任务之后，向该第一软件组件发送通知消息，该通知消息用于指示该目标任务已执行完成；该第一软件组件进而可以响应于该通知消息，将该目标任务的状态更新为已完成状态。
其中，不同软件组件之间的通信可以基于AUTOSAR中的运行环境层实现。
可选的，在该第一软件组件将满足调度条件的目标任务调度至该第二软件组件之前，该方法还可以包括：该第一软件组件响应于该通知消息，基于该算法实例检测该算法包括的多个任务中是否存在满足调度条件的目标任务。
本申请提供的方案，第一软件组件可以按照调度周期，周期性执行任务调度；或者也可以响应于第二软件组件发送的通知消息，主动触发下一次任务调度，而无需等待下一个调度周期，由此可以有效提高任务的调度效率。
可选的，该调度条件可以包括：该嵌入式设备中具备执行该任务所需的资源，且该任务所依赖的任务的状态为已完成状态。
可选的，该配置信息可以包括：每个任务的属性信息以及每个任务的调度信息；该接口函数生成算法的执行流图的过程可以包括：
该接口函数先在该内存中记录该依赖关系图中的每个节点与其所指示的任务的属性信息的映射关系，得到该算法的任务流图；然后在该内存中记录该任务流图中的每个节点与其所指示的任务的调度信息的映射关系，从而得到该算法的执行流图。
由于接口函数可以将解析得到的执行流图直接存储在内存中，使得第一软件组件在创建算法实例时可以直接从内存中查询执行流图中的数据，而无需进行文件解析，因此有效减小了任务的调度时延。
另一方面，提供了一种嵌入式设备，该嵌入式设备采用AUTOSAR，且该嵌入式设备包括内存和处理器，该内存中存储有接口函数，该处理器中部署有第一软件组件以及第二软件组件；该接口函数、第一软件组件以及第二软件组件可以用于实现上述方面所提供的任务调度方法。
又一方面，提供了一种计算机可读存储介质，该计算机可读存储介质中存储有指令，当该计算机可读存储介质在嵌入式设备上运行时，使得嵌入式设备执行如上述方面所提供的任务调度方法。
再一方面，提供了一种芯片，该芯片包括可编程逻辑电路和/或程序指令，当该芯片运行时用于实现如上述方面所提供的任务调度方法。
本申请提供的技术方案至少包括以下有益效果：
本申请实施例提供了一种任务调度方法及装置，该方案可以通过接口函数获取并解析算法的注册信息，并可以通过处理器中部署的软件组件实现对算法中的任务的调度执行。该算法的部署以及任务的调度过程中，无需开发人员进行复杂的配置，有效简化了算法的部署流程，提高了算法的部署效率以及任务的调度效率。
并且，由于该接口函数可以将解析得到的执行流图直接存储在内存中，使得软件组件在创建算法实例时可以直接从内存中查询执行流图中的数据，而无需进行文件解析，因此有效减小了任务的调度时延。又由于该处理器中可以预先部署用于实现任务调度和执行的软件组件，无需处理器在运行过程中实时创建进程或线程，因此也可以有效减小任务的调度时延。
附图说明
图1是本申请实施例提供的一种嵌入式设备中所采用的AUTOSAR的架构图；
图2是本申请实施例提供的一种感知调度框架的功能结构示意图；
图3是本申请实施例提供的一种采用AUTOSAR的嵌入式设备的结构示意图；
图4是本申请实施例提供的一种任务调度方法的流程图；
图5是本申请实施例提供的一种生成执行流图的示意图；
图6是本申请实施例提供的一种生成算法的执行流图的方法流程图；
图7是本申请实施例提供的一种基于一个执行流图创建多个算法实例的示意图；
图8是本申请实施例提供的一种处理器中部署的软件组件的示意图；
图9是本申请实施例提供的一种调度目标任务的方法流程图；
图10是本申请实施例提供的一种维护任务的状态的示意图；
图11是本申请实施例提供的另一种任务调度方法的流程图；
图12是本申请实施例提供的一种创建算法实例的方法流程图；
图13是本申请实施例提供的另一种采用AUTOSAR的嵌入式设备的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
相关技术中，若需要在AUTOSAR中部署某种算法，以实现该算法的功能，需要经过如下配置流程：首先，开发人员使用AUTOSAR的系统配置工具，完成软件组件(software component，SWC)的设计以及SWC之间交互的端口(port)的设计，生成算法相关的SWC描述文件。然后，使用AUTOSAR的电子控制单元(electronic control unit，ECU)配置工具，将生成的SWC内的可运行实体(runnable)映射到不同的操作系统任务(OS Task)中，同时开发人员需手动配置OS Task的属性，得到多个配置文件。最后，使用代码生成工具将该多个配置文件转化为代码，并对代码进行编译和链接即可生成用于实现该算法的功能的可执行文件。上述配置过程流程复杂，需要开发人员熟练掌握整套AUTOSAR的开发工具链才可以实现，效率较低。
图1是本申请实施例提供的一种嵌入式设备中所采用的AUTOSAR的架构图，如图1所 示，该AUTOSAR 01可以包括应用层(application layer)011、运行环境(runtime environment，RTE)层012以及运行在微控制器02上的基础软件(basic software，BSW)层013。并且除了上述三层外，该AUTOSAR 01还可以包括位于该应用层011和RTE层012之间的感知调度框架(perceptual scheduling framework)013。
其中，该PSF 014可以统一管理上层算法(也可以称为业务)中的任务的调度执行，上层算法无需关注SWC间如何通信以及任务如何调度执行，使得的算法与AUTOSAR 01解耦，从而可以解决在AUTOSAR 01中部署算法配置流程长且效率较低的问题。
参考图1还可以看出，该BSW层013可以包括安全操作系统(safety operation system，safety OS)0131、服务层(services layer)0132、ECU抽象层(ECU abstraction layer)0133、微控制器抽象层(micro-controller abstraction layer)0134以及复杂设备驱动(complex device drivers)0135。
图2是本申请实施例提供的一种PSF 014的功能结构示意图，如图2所示，该PSF 014可以包括两个功能模块：任务编排(task orchestration，TO)模块0141以及任务管理(task management，TM)模块0142。
其中，该任务编排模块0141主要用于实现对待部署的算法包括的任务的静态编排。参考图2，该任务编排模块0141可以包括如下四个子模块：
算法注册子模块1a，负责实现算法的注册，即获取算法的注册信息，并将该注册信息解析后传递至其他子模块。该算法可以包括多个任务，该算法的注册信息可以包括用于描述该多个任务的依赖关系的关系数据，以及每个任务的配置信息，该配置信息可以包括任务的属性信息、任务的资源依赖信息以及任务的调度约束信息等。
由于在AUTOSAR不支持文件系统，因此常见的基于解析文件来获取注册信息的方式并不可行，故在本申请实施例中，采用了基于内存的配置表来实现算法的注册，同时提高注册信息的解析速度。
有向无环图(directed acyclic graph，DAG)管理子模块1b，负责解析算法所包括的多个任务之间的执行依赖关系，并生成用于描述多个任务之间的依赖关系的DAG。由于车载场景对实时性要求高，传统的通过读取配置文件来解析依赖关系的方式变得不现实，为此本申请实施例采用DAG在内存中存储任务之间的依赖关系。
任务属性管理子模块1c，负责解析算法包括的各个任务的属性信息，并将任务的属性信息与DAG中对应的任务节点相关联，从而生成具有任务属性信息的任务流图(task flow graph，TFG)。其中，任务的属性信息可以包括任务名以及任务的存储地址。在本申请实施例中，每个任务可以包括用于实现特定功能的一个或多个函数，该任务名即为函数名，任务的存储地址即为函数的存储地址，该存储地址可以采用函数指针表示。
任务调度信息管理子模块1d，负责解析算法包括的任务的调度信息，并将该调度信息与TFG中的对应的节点相关联，从而生成可被任务管理模块0142调度执行的执行流图(execution flow graph，EFG)。并且，任务调度信息管理子模块1d可以提供用于获取该EFG的接口给任务管理模块0142。其中，该调度信息可以包括任务的资源依赖信息以及调度约束信息。该资源依赖信息可以包括：任务依赖的内存，以及处理器中用于执行该任务的计算单元的标识。该调度约束信息可以包括任务的启动时间以及任务启动后最大的运行时长。
任务管理模块0142主要用于实现任务的动态管理，如图2所示，该任务管理模块0142可以包括如下四个子模块：
任务状态机管理子模块2a，用于管理算法中每个任务的状态迁移。
执行流图实例管理子模块2b，用于创建以及删除执行流图实例，以及对执行流图中的任务所依赖的资源进行解析。
执行流图实例调度子模块2c，用于根据任务的状态迁移合理调度任务执行。
图3是本申请实施例提供的一种采用AUTOSAR的嵌入式设备的结构示意图。该嵌入式设备可以为车载设备，且可以应用于智能汽车、网联汽车或新能源汽车中。如图3所示，该嵌入式设备可以包括内存10以及处理器20。该内存10中存储有接口函数101，该处理器20中部署有第一SWC 201以及第二SWC 202。其中，该处理器20可以为如图1所示的微控制器，也可以称为微控制单元(micro-controller unit；MCU)。该接口函数101可以用于实现该PSF 014中任务编排模块0141的功能。该第一SWC 201可以用于实现该PSF 014中任务管理模块0142的功能，即该第一SWC 201主要用于实现任务的调度，因此该第一SWC 201也可以称为调度SWC或者主(master)SWC。该第二SWC 202用于执行任务，因此该第二SWC 202也可以称为运行(worker)SWC。
本申请实施例提供的嵌入式设备，由于可以通过预先部署在处理器中的第一SWC和第二SWC实现任务的调度和执行，因此无需处理器在运行过程中实时创建进程或线程来调度执行任务，从而可有效降低任务的调度时延。
图4是本申请实施例提供的一种任务调度方法的流程图，该方法可以应用于如图3所示的嵌入式设备中。参考图4，该方法可以包括：
步骤401、接口函数获取待部署的算法的注册信息。
该算法可以包括多个任务，该注册信息可以包括：用于描述该多个任务之间的依赖关系的关系数据，以及每个任务的配置信息。该配置信息可以包括任务的属性信息、任务的资源依赖信息以及任务的调度约束信息等。
其中，任务的属性信息可以包括任务名以及任务的存储地址。在本申请实施例中，每个任务可以包括用于实现特定功能的一个或多个函数，该任务名即为函数名，任务的存储地址即为函数的存储地址，该存储地址可以采用函数指针表示。并且，该算法所包括的多个任务可以存储在嵌入式设备的存储器中。
该调度信息可以包括任务的资源依赖信息以及调度约束信息。该资源依赖信息可以包括：任务依赖的内存，以及处理器中用于执行该任务的计算单元的标识。该调度约束信息可以包括任务的启动时间以及任务启动后最大的运行时长。
可选的，在本申请实施例中，该待部署的算法可以为高级驾驶辅助系统(advanced driving assistance system，ADAS)相关的算法。例如可以为毫米波雷达算法，该毫米波雷达算法可以用于实现检测(比如距离检测、速度检测或障碍物检测等)和追踪等功能。
需要说明的是，该嵌入式设备在启动后，处理器即可开始运行该内存中的接口函数，该接口函数进而可以实现上述步骤401所示的方法。
步骤402、接口函数根据关系数据生成多个任务的依赖关系图。
接口函数获取到该注册信息后，可以对该注册信息中的关系数据进行解析，并生成能够体现该多个任务之间的依赖关系的依赖关系图，该依赖关系图可以包括多个节点，每个节点用于指示一个任务。其中，该接口函数生成的依赖关系图可以为DAG。并且，该依赖关系图可以采用邻接链表或者邻接矩阵表示，即该依赖关系图可以采用邻接链表或者邻接矩阵的形式进行存储。
示例的，参考图5，假设该算法包括任务1至任务5共5个任务，该5个任务的依赖关系为：任务1无依赖任务(即任务1为该算法中的首个任务)，任务2依赖于任务1，任务3依赖于任务2，任务4依赖于任务2和任务3，任务5依赖于任务4。则接口函数通过解析该5个任务的依赖关系，可以生成如图5所示的DAG。
步骤403、接口函数在内存中记录该依赖关系图中的每个节点与其所指示的任务的配置信息的映射关系，得到该算法的执行流图。
接口函数可以通过记录每个节点与其所指示的任务的配置信息的映射关系，将每个节点与其所指示的任务的配置信息相关联，从而得到该算法的执行流图。
在本申请实施例中，该嵌入式设备一般不支持文件系统，因此该接口函数可以采用目标数据结构直接在内存中存储该执行流图。该目标数据结构可以为JSON(JavaScript object notation，JS对象简谱)数据结构或者可扩展标记语言(extensible markup language，XML)数据结构。相比于相关技术中采用配置文件的方式在磁盘中存储各个任务的依赖关系图，以及每个任务的配置信息，直接按照目标数据结构在内存中存储该执行流图，由于无需进行文件解析，因此可以有效提高执行流图的读取效率，进而降低任务的调度时延，例如任务的调度时延可以降低至微秒(us)级。
可选的，如前文所述，每个任务的配置信息可以包括：每个任务的属性信息以及每个任务的调度信息。相应的，如图6所示，生成该算法的执行流图的过程可以包括：
步骤4031、接口函数在内存中记录依赖关系图中的每个节点与其所指示的任务的属性信息的映射关系，得到算法的任务流图。
如图5所示，接口函数可以先将该依赖关系图中的每个节点与其所指示的任务的属性信息相关联，从而得到算法的任务流图。
步骤4032、接口函数在内存中记录该任务流图中的每个节点与其所指示的任务的调度信息的映射关系，得到算法的执行流图。
继续参考图5，接口函数可以将任务流图中的每个节点与其所指示的任务的调度信息相关联，从而得到能够被处理器中部署的第一SWC调度的执行流图。
需要说明的是，在本申请实施例中，接口函数在内存中记录的映射关系可以采用映射表的方式表示，即映射关系可以通过映射表的方式存储在内存中。
步骤404、第一SWC检测其是否满足实例创建条件。
在本申请实施例中，该处理器中部署的第一SWC可以按照预设的调度周期，周期性运行，即该处理器可以按照该调度周期，周期性触发该第一SWC。该第一SWC开始运行后，可以先检测当前是否满足实例创建条件。若该第一SWC确定满足实例创建条件，则可以继续执行步骤405；若该第一SWC确定不满足实例创建条件，则可以执行步骤406。
其中，该实例创建条件可以包括下述条件中的一种或多种：
第一SWC已创建的实例的总数小于数量阈值，该数量阈值为嵌入式设备的处理器能够 并行运行的实例的个数上限；
该嵌入式设备中具备用于执行该算法中的任务的资源。
作为一种可选的实现方式，该第一SWC可以串行调度算法实例，即每个调度周期仅能够执行一个算法实例中的任务。在该实现方式中，该数量阈值可以为1。相应的，该实例创建条件可以为：第一SWC已创建的实例的总数小于1。也即是，第一SWC可以在检测到已创建的实例的个数为0时，执行步骤405。
作为另一种可选的实现方式，该第一SWC可以并行调度多个算法实例，即每个调度周期可以执行多个算法实例中的任务。因此在该实现方式中，该数量阈值可以为大于1的整数，例如可以为3或者5等。相应的，该实例创建条件可以包括第一SWC已创建的实例的总数小于数量阈值。其中，该并行调度的多个算法实例可以基于一个执行流图创建，也可以基于不同的执行流图创建，本申请实施例对此不做限定。
并且，为了确保算法实例的可靠运行，该实例创建条件还可以包括：该嵌入式设备中具备用于执行该执行流图中的任务的资源。
若该并行调度的多个算法实例基于一个执行流图创建，则在该实现方式中，第一SWC若检测到某个执行流图的算法实例已经创建，且该嵌入式设备中还具备能够执行该执行流图中的任务的资源，则第一SWC可以基于该执行流图再次创建一个算法实例，并调度执行该算法实例中的任务，以提高该算法的调度效率。
示例的，如图7所示，假设某个执行流图包括任务T1至T6共6个任务。第一SWC在第一个调度周期，基于该执行流图创建了算法实例1，并依次调度执行该算法实例1中的任务。若该第一SWC在第二个调度周期检测到算法实例1中的任务T1和T2已执行完成，任务T3正在执行，且检测到用于执行任务T1和T2的第二SWC所属的计算单元处于空闲状态，则可以基于该执行流图创建算法实例2，并可以执行该任务T1和任务T2。若该第一SWC在第三个调度周期检测到算法实例2中的任务T1已执行完成，任务T2正在执行，且用于执行任务T1的第二SWC所属的计算单元处于空闲状态，则第一SWC可以继续基于该执行流图创建算法实例3，并可以执行该任务T1。
通过并行调度多个算法实例，即流水执行算法实例，由于无需等待一个算法实例执行完成后再创建新的算法实例，因此不仅可以有效提高嵌入式设备的资源利用率，还可以有效缩短算法实例的执行周期，确保算法实例能够在规定的执行周期内执行完成。在毫米波雷达算法中可以显著缩短雷达上报目标的刷新时间。
步骤405、第一SWC基于该执行流图创建算法实例。
在本申请实施例中，第一SWC检测到满足实例创建条件后，即可通过接口函数提供的接口，从内存中查询执行流图，并基于该执行流图创建算法实例。其中，创建算法实例可以是指：获取执行流图的地址并保存。后续在调度算法实例时，只需要根据该地址索引执行流图中的数据即可。并且，该第一SWC还可以在内存中创建一个新的数据结构，用于记录各个任务的执行状态以及执行时间，其中执行时间包括任务的开始时间(也称为启动时间)和结束时间。
步骤406、第一SWC基于该算法实例检测该算法包括的多个任务中是否存在满足调度条件的目标任务。
在本申请实施例中，第一SWC在创建完成算法实例后，可以基于该算法实例轮询每个 任务的配置信息，进而检测该多个任务中是否存在满足调度条件的目标任务。若第一SWC确定该算法包括的多个任务中存在满足调度条件的目标任务，则可以执行步骤407；若第一SWC确定该算法包括的多个任务中不存在满足调度条件的目标任务，则可以结束操作。
其中，该调度条件至少可以包括：任务所依赖的任务的状态为已完成状态。若每个任务的配置信息中还包括调度信息，且该调度信息包括资源依赖信息，则该调度条件还可以包括：嵌入式设备中该资源依赖信息指示的资源处于空闲状态，其中资源可以包括内存资源和计算资源，计算资源也即是处理器资源。若该调度信息还包括调度约束信息，则该调度条件还可以包括：当前运行环境满足该调度约束信息，例如，当前时间为任务的规定的启动时间。
结合上述步骤404和步骤405可知，第一SWC可以在创建了新的算法实例后，基于该算法实例检测该算法包括的多个任务中是否存在满足调度条件的目标任务。或者，第一SWC可以在检测到其不满足实例创建条件时，确定处理器中已经存在算法实例，因此可以直接检测该算法实例包括的多个任务中是否存在满足调度条件的目标任务。
步骤407、第一SWC将该目标任务调度至第二SWC。
在本申请实施例中，第一SWC确定出满足调度条件的目标任务后，即可将该目标任务调度至第二SWC执行。
可选的，该处理器中可以预先部署有多个第二SWC，每个第二SWC可以用于执行算法中的部分任务。在本申请实施例中，如图8所示，该处理器可以包括多个计算单元，每个计算单元可以是指一个处理器核。则该第一SWC可以部署在一个计算单元中，例如为了确保算法部署和调度的可靠性，该第一SWC可以部署在安全等级较高的计算单元中。每个第二SWC可以部署在一个计算单元中，该第二SWC与第一SWC部署于不同的计算单元，且每个计算单元可以部署一个或多个第二SWC。
相应的，如图9所示，第一SWC将目标任务调度至该第二SWC的过程可以包括：
步骤4071、第一SWC确定目标任务的标识。
每个任务的标识可以为该标任务的任务名，或者也可以是接口函数在获取到注册信息后，为每个任务唯一分配的标识(identification，ID)。
步骤4072、第一SWC根据该目标任务的标识，从多个第二SWC中确定用于执行该目标任务的目标第二SWC。
在本申请实施例中，第一SWC可以从执行流图中查询目标任务的配置信息，该配置信息中可以记录有用于执行该目标任务的计算单元的标识。第一SWC进而可以基于该目标任务的类型，以及预先存储的任务的类型与第二SWC的标识的对应关系，确定用于执行该目标任务的第二SWC。或者，第一SWC也可以直接从该目标任务的配置信息中确定用于执行该目标任务的目标第二SWC。
步骤4073、第一SWC将该目标任务的标识发送至该目标第二SWC。
第一SWC确定出目标第二SWC后，即可将目标任务的标识发送至该目标第二SWC。
步骤408、第二SWC执行该目标任务。
第二SWC接收到第一SWC调度的目标任务的标识后，即可根据该标识，查询该目标任务的配置信息，并确定该目标任务的存储地址，例如目标任务的函数指针。之后，第二SWC即可执行该目标任务。
步骤409、第二SWC向该第一SWC发送通知消息，该通知消息用于指示该目标任务已 执行完成。
在该第二SWC执行完成该目标任务之后，即可向该第一SWC发送通知消息。可选的，在本申请实施例中，第一SWC与第二SWC之间的通信可以基于AUTOSAR中的RTE实现，例如RTE可以通过共享内存和核间中断的方式实现不同SWC之间的通信。
步骤410、第一SWC响应于该通知消息，将该目标任务的状态更新为已完成状态。
该第一SWC接收到第二SWC发送的通知消息后，即可响应于该通知消息，将该目标任务的状态更新为已完成状态。
可选的，在本申请实施例中，第一SWC还可以响应于该通知消息，继续执行步骤406，以检测该算法包括的多个任务中是否存在满足调度条件的目标任务。也即是，该第二SWC无需等到下一个调度周期，即可主动触发下一次任务调度。相比于按照调度周期，周期性执行任务调度，该主动触发的方式可以有效提高任务的调度效率。
需要说明的是，在本申请实施例中，处理器中部署的第二SWC的个数可以是根据待部署的算法的功能进行确定的。例如，假设待部署的算法可以划分为N个子功能，N为大于1的整数，且每个子功能由一个或多个任务实现，即每个子功能可以包括相同类型的一个或多个任务。则处理器中可以部署有对应于该N个子功能的N个第二SWC，每个第二SWC可以执行用于实现一个子功能的各个任务。该第一SWC则可以存储每个子功能(即任务的类型)与第二SWC的标识的对应关系。
综上所述，本申请实施例提供了一种任务调度方法，该方法可以通过接口函数获取并解析算法的注册信息，并可以通过SWC实现对算法中的任务的调度执行。该算法的部署以及任务的调度过程中，无需开发人员进行复杂的配置，有效简化了算法的部署流程，提高了算法的部署效率以及任务的调度效率。并且，由于该接口函数可以将解析得到的执行流图直接存储在内存中，使得SWC在创建算法实例时可以直接从内存中查询执行流图中的数据，而无需进行文件解析，因此有效减小了任务的调度时延。又由于该处理器中可以预先部署用于实现任务调度和执行的SWC，无需处理器在运行过程中实时创建进程或线程，因此也可以有效减小任务的调度时延。
基于上述分析可知，本申请实施例提供的任务调度方法的调度时延较小，调度效率较高，能够满足车载场景高实时性的要求。
图10是本申请实施例提供的一种第一SWC维护任务的状态的示意图。参考图10可以看出，该第一SWC可以在基于某个执行流图创建算法实例后，将该算法实例中的各个任务的状态均初始化为等待(waiting)状态。第一SWC在检测到某个任务所依赖的任务执行完成时，可以将该任务的状态更新为准备完成(ready)状态。之后，第一SWC可以在检测到该任务所依赖的资源空闲，即满足调度条件并将该任务调度至第二SWC执行后，将该任务的状态更新为运行(running)状态。若第一SWC检测到该任务处于等待状态、准备完成状态或运行状态中的任一状态的时长超过规定时长，则可以将该任务的状态更新为异常(abnormal)状态。并且，第一SWC在检测到复位指令时，可以将处于异常状态的任务的状态更新为等待状态。若第一SWC检测到某个任务正常运行结束，且未超时(即任务的执行时长未超过配置信息中规定的时长)，则可以将该任务的状态更新为完成(finish)状态。该第一SWC还可以在检测到算法实例中的所有任务都执行完成(即所有任务的状态均为完成 状态)时，将所有任务的状态均还原为等待状态。由于第一SWC可以在内存中记录每个任务的状态，因此在算法实例中的所有任务都执行完成后，将所有任务的状态均还原为等待状态，可以实现对内存的释放。
图11是本申请实施例提供的另一种任务调度方法的流程图，该方法可以应用于第一SWC。如图11所示，该方法可以包括：
步骤1101、检测算法实例是否处理完成。
在本申请实施例中，第一SWC创建完成算法实例后，在调度执行该算法实例中的任务之前，可以先检测该算法实例是否处理完成，例如可以检测该算法实例的状态是否为完成状态。若确定该算法实例处理完成，则第一SWC可以结束操作；若确定该算法实例未处理完成，则第一SWC可以继续执行步骤1102。
步骤1102、检测状态为完成状态的任务是否超时。
第一SWC可以继续检测该算法实例中，状态为完成状态的任务是否超时，即检测已执行完成的任务的执行时长是否超过配置信息中规定的最大的运行时长。若任务超时，则可以执行步骤1103；若任务未超时，则可以执行步骤1104。
步骤1103、更新算法实例的状态为异常状态。
第一SWC若检测到状态为完成状态的任务超时，则可以将该算法实例的状态更新为异常状态。
步骤1104、检测所有任务的状态是否均为完成状态。
第一SWC若检测到状态为完成状态的任务未超时，则可以继续检测所有任务的状态是否均为完成状态，即检测算法实例中的所有任务是否均执行完成。
若所有任务的状态均为完成状态，则可以执行步骤1105；若任一任务的状态不为完成状态，则可以执行步骤1106。
步骤1105、更新算法实例的状态为完成状态。
第一SWC若检测到算法实例中的所有任务的状态均为完成状态，则可以确定该算法实例中的所有任务均已执行完成，因此可以将算法实例的状态更新为完成状态。
步骤1106、更新所有处于运行状态的任务的运行时间。
第一SWC若检测到算法实例中任一任务的状态不为完成状态，则可以更新所有处于运行状态的任务的运行时长。
步骤1107、检测是否存在所依赖的任务的状态为执行完成的任务。
第一SWC更新处于运行状态的任务的运行时间后，可以继续检测算法实例中是否存在所依赖的任务的状态为执行完成的任务。若存在，则可以执行步骤1108；若不存在，则可以结束操作。该步骤1107的实现过程可以参考上述步骤406。
步骤1108、更新该任务的状态为准备完成状态。
第一SWC若检测到某个任务所依赖的所有任务均已执行完成，则可以将该任务的状态更新为准备完成状态。
步骤1109、将该任务调度至第二SWC执行。
第一SWC进而可以将准备完成状态的任务调度至第二SWC执行。该步骤1109的实现过程可以参考上述步骤407和步骤408。
步骤1110、更新该任务的状态为运行状态。
第一SWC将任务调度至第二SWC后，可以更新该任务的状态为运行状态。
图12是本申请实施例提供的一种创建算法实例的方法流程图，该方法可以应用于第一SWC。如图12所示，该方法可以包括：
步骤1201、根据算法配置信息获取执行流图的类型。
第一SWC在检测到满足实例创建条件后，可以先根据内存中的算法配置信息确定其所能够创建实例的执行流图的类型。其中，该算法配置信息可以是开发人员预先写入内存的，或者也可以是外部配置的。
步骤1202、根据执行流图的类型创建对应类型的算法实例。
第一SWC可以根据确定出的执行流图的类型，从内存中查询相同类型的执行流图，并基于该类型的执行流图创建算法实例。
步骤1203、初始化算法实例中的任务为等待状态。
第一SWC创建完成算法实例后，即可将该算法实例中的所有任务的状态均初始化为等待状态。
步骤1204、生效系统配置参数。
第一SWC初始化任务的状态后，可以生效系统配置参数。例如，对于毫米波雷达算法，该系统配置参数可以包括雷达的安装位置，以及雷达的外部配置参数等。
综上所述，本申请实施例提供的方法在该AUTOSAR的应用层011和RTE层012之间增加了PSF 014，该PSF 014可以统一管理上层算法中的任务的调度执行，从而可以实现如下有益效果：
1、算法与AUTOSAR原有框架的解耦，即PSF统一负责算法的注册与执行，算法对AUTOSAR的框架无感知，算法的变动不需要重新配置AUTOSAR，从而有效提高了AUTOSAR的可扩展性与可演进性。
2、算法部署和更新简单，只需要更新注册表并调用PSF注册接口就可以完成算法注册。并且，PSF支持动态注册。
3、算法对任务的执行时序和状态无感知，从而可以避免不必要的任务唤醒休眠带来的性能损耗。
4、充分利用了嵌入式设备的底层硬件资源，缩短了算法执行周期。由于PSF可以通过流水调度的方式，支持多个算法实例同时执行，在前一个算法实例还没有执行完时，启动下一轮算法实例，从而可以缩短算法的执行周期。
本申请实施例还提供了一种嵌入式设备，该嵌入式设备采用AUTOSAR，且如图3所示，该嵌入式设备包括内存10和处理器20，该内存10中存储有接口函数101，该处理器20中部署有第一SWC 201以及第二SWC 202。
该接口函数101可以用于：
获取待部署的算法的注册信息，该算法包括多个任务，该注册信息包括：用于描述该多个任务之间的依赖关系的关系数据，以及每个任务的配置信息；
根据该关系数据生成该多个任务的依赖关系图，该依赖关系图包括多个节点，每个节点用于指示一个该任务；
在该内存中记录该依赖关系图中的每个节点与其所指示的任务的配置信息的映射关系，得到该算法的执行流图。
该第一SWC 201可以用于：基于该执行流图创建算法实例，以及基于该算法实例，将该算法包括的多个任务中满足调度条件的目标任务调度至该第二SWC 202；
该第二SWC 202，可以用于执行该目标任务。
其中，该接口函数101的功能实现可以参考上述方法实施例中步骤401至步骤403的相关描述；该第一SWC 201的功能实现可以参考上述方法实施例中步骤405和步骤407的相关描述；该第二SWC 202的功能实现可以参考上述方法实施例中步骤408的相关描述。
可选的，该第一SWC 201可以用于：
若确定其满足实例创建条件，则基于该执行流图创建算法实例，其中，该实例创建条件包括下述条件中的一种或多种：已创建的实例的总数小于数量阈值；该嵌入式设备中具备执行该算法中的任务所需的资源。
该第一SWC 201的功能实现还可以参考上述方法实施例中步骤404的相关描述；
可选的，该处理器中可以部署有多个第二SWC 202；该第一SWC 201可以用于：
基于该算法实例，从该算法包括的多个任务中确定满足调度条件的目标任务的标识；根据该目标任务的标识，从多个第二SWC中确定用于执行该目标任务的目标第二SWC；将该目标任务的标识发送至该目标第二SWC。
该第一SWC 201的功能实现还可以参考上述方法实施例中步骤4071至步骤4073的相关描述。
可选的，该第二SWC 202还可以用于：在执行完成该目标任务之后，向该第一SWC 201发送通知消息，该通知消息用于指示该目标任务已执行完成。
相应的，该第一SWC 201，还可以用于响应于该通知消息，将该目标任务的状态更新为已完成状态。
该第二SWC 202的功能实现还可以参考上述方法实施例中步骤409的相关描述。该第一SWC 201的功能实现还可以参考上述方法实施例中步骤410的相关描述。
可选的，该第一SWC 201还可以用于：响应于该通知消息，基于该算法实例检测该算法包括的多个任务中是否存在满足调度条件的目标任务。
可选的，该调度条件可以包括：该嵌入式设备中具备执行该任务所需的资源，且该任务所依赖的任务的状态为已完成状态。
可选的，该配置信息可以包括：每个任务的属性信息以及每个任务的调度信息；该接口函数101可以用于：
在该内存中记录该依赖关系图中的每个节点与其所指示的任务的属性信息的映射关系，得到该算法的任务流图；
在该内存中记录该任务流图中的每个节点与其所指示的任务的调度信息的映射关系，得到该算法的执行流图。
该接口函数101的功能实现还可以参考上述方法实施例中步骤4031和步骤4032的相关描述。
综上所述，本申请实施例提供了一种嵌入式设备，该嵌入式设备可以通过内存中的接口函数获取并解析算法的注册信息，并可以通过处理器中部署的SWC实现对算法中的任务的 调度执行。该算法的部署以及任务的调度过程中，无需开发人员进行复杂的配置，有效简化了算法的部署流程，提高了算法的部署效率以及任务的调度效率。并且，由于该接口函数可以将解析得到的执行流图直接存储在内存中，使得SWC在创建算法实例时可以直接从内存中查询执行流图中的数据，而无需进行文件解析，因此有效减小了任务的调度时延。又由于该处理器中可以预先部署用于实现任务调度和执行的SWC，无需处理器在运行过程中实时创建进程或线程，因此也可以有效减小任务的调度时延。
应理解的是，本申请实施例提供的嵌入式设备可以用专用集成电路(application-specific integrated circuit，ASIC)实现，或可编程逻辑器件(programmable logic device，PLD)实现，上述PLD可以是复杂程序逻辑器件(complex programmable logical device，CPLD)，现场可编程门阵列(field-programmable gate array，FPGA)，通用阵列逻辑(generic array logic，GAL)或其任意组合。
图13是本申请实施例提供的另一种嵌入式设备的结构示意图，参考图13，该嵌入式设备可以包括：处理器1301、内存1302、存储器1303、网络接口1304和总线1305。其中，总线1305用于连接处理器1301、内存1302、存储器1303和网络接口1304。通过网络接口1304(可以是有线或者无线)可以实现与其他器件之间的通信连接。存储器1303中存储有计算机程序13031，该计算机程序13031用于实现各种应用功能。
应理解，在本申请实施例中，处理器1301可以是CPU，该处理器1301还可以是其他通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现场可编程门阵列(FPGA)、GPU或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者是任何常规的处理器等。
存储器1303可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data date SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。
总线1305除包括数据总线之外，还可以包括电源总线、控制总线和状态信号总线等。但是为了清楚说明起见，在图中将各种总线都标为总线1305。
处理器1301被配置为执行内存1302中的接口函数，以及存储器1303中存储的计算机程序，处理器1301通过执行该接口函数和计算机程序13031来实现上述方法实施例所示的方法。
本申请实施例还提供了一种计算机可读存储介质，该计算机可读存储介质中存储有指令， 当该计算机可读存储介质在嵌入式设备上运行时，使得计算机执行如上述方法实施例所示的方法。
本申请实施例还提供了一种包含指令的计算机程序产品，当该计算机程序产品在嵌入式设备上运行时，使得计算机执行上述方法实施例所示的方法。
本申请实施例还提供了一种芯片，该芯片包括可编程逻辑电路和/或程序指令，当该芯片运行时用于实现如上述方面所提供的任务调度方法。
应当理解的是，在本申请实施例中提及的“和/或”，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。字符“/”一般表示前后关联对象是一种“或”的关系。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本申请的示例性实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (16)

  1. 一种任务调度方法，其特征在于，应用于采用汽车开放系统架构AUTOSAR的嵌入式设备，所述嵌入式设备包括内存和处理器，所述内存中存储有接口函数，所述处理器中部署有第一软件组件以及第二软件组件；所述方法包括：
    所述接口函数获取待部署的算法的注册信息，所述算法包括多个任务，所述注册信息包括：用于描述所述多个任务之间的依赖关系的关系数据，以及每个所述任务的配置信息；
    所述接口函数根据所述关系数据生成所述多个任务的依赖关系图，所述依赖关系图包括多个节点，每个所述节点用于指示一个所述任务；
    所述接口函数在所述内存中记录所述依赖关系图中的每个所述节点与其所指示的任务的配置信息的映射关系，得到所述算法的执行流图；
    所述第一软件组件基于所述执行流图创建算法实例；
    所述第一软件组件基于所述算法实例，将所述算法包括的多个任务中满足调度条件的目标任务调度至所述第二软件组件；
    所述第二软件组件执行所述目标任务。
  2. 根据权利要求1所述的方法，其特征在于，所述第一软件组件基于所述执行流图创建算法实例，包括：
    若所述第一软件组件确定其满足实例创建条件，则基于所述执行流图创建算法实例，其中，所述实例创建条件包括下述条件中的一种或多种：
    所述第一软件组件已创建的实例的总数小于数量阈值；
    所述嵌入式设备中具备执行所述算法中的任务所需的资源。
  3. 根据权利要求1或2所述的方法，其特征在于，所述处理器中部署有多个所述第二软件组件；所述第一软件组件基于所述算法实例，将所述算法包括的多个任务中满足调度条件的目标任务调度至所述第二软件组件，包括：
    所述第一软件组件基于所述算法实例，从所述算法包括的多个任务中确定满足调度条件的目标任务的标识；
    所述第一软件组件根据所述目标任务的标识，从多个所述第二软件组件中确定用于执行所述目标任务的目标第二软件组件；
    所述第一软件组件将所述目标任务的标识发送至所述目标第二软件组件。
  4. 根据权利要求1至3任一所述的方法，其特征在于，所述方法还包括：
    在所述第二软件组件执行完成所述目标任务之后，所述第二软件组件向所述第一软件组件发送通知消息，所述通知消息用于指示所述目标任务已执行完成；
    所述第一软件组件响应于所述通知消息，将所述目标任务的状态更新为已完成状态。
  5. 根据权利要求4所述的方法，其特征在于，在所述第一软件组件基于所述算法实例将 所述算法中满足调度条件的目标任务调度至所述第二软件组件之前，所述方法还包括：
    所述第一软件组件响应于所述通知消息，基于所述算法实例检测所述算法包括的多个任务中是否存在满足调度条件的目标任务。
  6. 根据权利要求1至5任一所述的方法，其特征在于，所述调度条件包括：
    所述嵌入式设备中具备执行所述任务所需的资源，且所述任务所依赖的任务的状态为已完成状态。
  7. 根据权利要求1至6任一所述的方法，其特征在于，所述配置信息包括：每个所述任务的属性信息以及每个所述任务的调度信息；
    所述接口函数在所述内存中记录所述依赖关系图中的每个所述节点与其所指示的任务的配置信息的映射关系，得到所述算法的执行流图，包括：
    所述接口函数在所述内存中记录所述依赖关系图中的每个所述节点与其所指示的任务的属性信息的映射关系，得到所述算法的任务流图；
    所述接口函数在所述内存中记录所述任务流图中的每个所述节点与其所指示的任务的调度信息的映射关系，得到所述算法的执行流图。
  8. 一种嵌入式设备，其特征在于，所述嵌入式设备采用汽车开放系统架构AUTOSAR，所述嵌入式设备包括内存和处理器，所述内存中存储有接口函数，所述处理器中部署有第一软件组件以及第二软件组件；
    所述接口函数用于：
    获取待部署的算法的注册信息，所述算法包括多个任务，所述注册信息包括：用于描述所述多个任务之间的依赖关系的关系数据，以及每个所述任务的配置信息；
    根据所述关系数据生成所述多个任务的依赖关系图，所述依赖关系图包括多个节点，每个所述节点用于指示一个所述任务；
    在所述内存中记录所述依赖关系图中的每个所述节点与其所指示的任务的配置信息的映射关系，得到所述算法的执行流图；
    所述第一软件组件用于：基于所述执行流图创建算法实例，以及基于所述算法实例，将所述算法包括的多个任务中满足调度条件的目标任务调度至所述第二软件组件；
    所述第二软件组件用于执行所述目标任务。
  9. 根据权利要求8所述的设备，其特征在于，所述第一软件组件用于：
    若确定其满足实例创建条件，则基于所述执行流图创建算法实例，其中，所述实例创建条件包括下述条件中的一种或多种：
    已创建的实例的总数小于数量阈值；
    所述嵌入式设备中具备执行所述算法中的任务所需的资源。
  10. 根据权利要求8或9所述的设备，其特征在于，所述处理器中部署有多个所述第二软件组件；所述第一软件组件，用于：
    基于所述算法实例，从所述算法包括的多个任务中确定满足调度条件的目标任务的标识；
    根据所述目标任务的标识，从多个所述第二软件组件中确定用于执行所述目标任务的目标第二软件组件；
    将所述目标任务的标识发送至所述目标第二软件组件。
  11. 根据权利要求8至10任一所述的设备，其特征在于，所述第二软件组件还用于：
    在执行完成所述目标任务之后，向所述第一软件组件发送通知消息，所述通知消息用于指示所述目标任务已执行完成；
    所述第一软件组件，还用于响应于所述通知消息，将所述目标任务的状态更新为已完成状态。
  12. 根据权利要求11所述的设备，其特征在于，所述第一软件组件还用于：
    响应于所述通知消息，基于所述算法实例检测所述算法包括的多个任务中是否存在满足调度条件的目标任务。
  13. 根据权利要求8至12任一所述的设备，其特征在于，所述调度条件包括：
    所述嵌入式设备中具备执行所述任务所需的资源，且所述任务所依赖的任务的状态为已完成状态。
  14. 根据权利要求8至13任一所述的设备，其特征在于，所述配置信息包括：每个所述任务的属性信息以及每个所述任务的调度信息；所述接口函数用于：
    在所述内存中记录所述依赖关系图中的每个所述节点与其所指示的任务的属性信息的映射关系，得到所述算法的任务流图；
    在所述内存中记录所述任务流图中的每个所述节点与其所指示的任务的调度信息的映射关系，得到所述算法的执行流图。
  15. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有指令，当所述计算机可读存储介质在嵌入式设备上运行时，使得嵌入式设备执行如权利要求1至8任一所述的方法。
  16. 一种芯片，其特征在于，所述芯片包括可编程逻辑电路和/或程序指令，当所述芯片运行时用于实现如权利要求1至8任一所述的方法。
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