WO2021196868A1 - 显示基板及显示面板 - Google Patents

显示基板及显示面板 Download PDF

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Publication number
WO2021196868A1
WO2021196868A1 PCT/CN2021/074884 CN2021074884W WO2021196868A1 WO 2021196868 A1 WO2021196868 A1 WO 2021196868A1 CN 2021074884 W CN2021074884 W CN 2021074884W WO 2021196868 A1 WO2021196868 A1 WO 2021196868A1
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WO
WIPO (PCT)
Prior art keywords
layer
isolation
sub
substrate
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/074884
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English (en)
French (fr)
Inventor
杨富强
赵攀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US17/618,475 priority Critical patent/US12238979B2/en
Priority to EP21772937.5A priority patent/EP4131405A4/en
Publication of WO2021196868A1 publication Critical patent/WO2021196868A1/zh
Anticipated expiration legal-status Critical
Priority to US19/030,884 priority patent/US20250386669A1/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H10K59/8731—Encapsulations multilayered coatings having a repetitive structure, e.g. having multiple organic-inorganic bilayers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness

Definitions

  • the present disclosure belongs to the field of display technology, and specifically relates to a display substrate and a display panel.
  • the present disclosure aims to solve at least one of the technical problems existing in the prior art, and to provide a display substrate and a display panel.
  • an embodiment of the present disclosure provides a display substrate having an opening area, a transition area surrounding the opening area, and a display area surrounding the transition area; the display substrate includes:
  • the isolation column and the cofferdam structure are all set on the base, located in the transition area and surrounding the opening area; wherein, the isolation column includes a first isolation column, and the first isolation column is located in the enclosure.
  • the weir structure is close to the side of the display area; the organic electroluminescent diode, the first encapsulation layer, the second encapsulation layer, and the third encapsulation layer are sequentially arranged on the substrate, and the organic electroluminescence diode is located on the Display area, the orthographic projection of the first packaging layer and the third packaging layer on the substrate at least covers the display area and the transition area; the orthographic projection of the second packaging layer on the substrate The first isolation column covering the display area and the transition area; wherein,
  • the ratio of the thickness of the second packaging layer on the first isolation pillar to the thickness of the first isolation pillar is 2:1-6:1.
  • the first isolation column includes a first sub-isolation column, the first sub-isolation column is adjacent to the cofferdam structure, and the orthographic projection of the second encapsulation layer on the substrate and the The ratio of the average thickness of the overlapping area of the first sub-isolation column to the thickness of the first sub-isolation column is 2:1-6:1.
  • the ratio of the thickness of the area where the orthographic projection of the second packaging layer on the substrate overlaps the first sub-isolation column to the thickness of the first sub-isolation column is 6:1.
  • the thickness of the second encapsulation layer gradually decreases from the display area to the transition area.
  • the first sub-isolation column includes: a first sub-isolation layer, a second sub-isolation layer, and a third sub-isolation layer arranged in a stack;
  • the orthographic projections of the first sub-isolation layer and the third sub-isolation layer on the substrate coincide, and the orthographic projection of the second sub-isolation layer on the substrate falls on the first sub-isolation layer. In the orthographic projection on the substrate.
  • the thickness of the first sub-isolation layer and the third sub-isolation layer is 0.04 ⁇ m-0.08 ⁇ m; the thickness of the second sub-isolation layer is 0.4 ⁇ m-0.6 ⁇ m.
  • the material of the first sub-isolation layer and the third sub-isolation layer includes titanium, and the material of the second isolation pillar includes aluminum.
  • a granular structure is attached to the surface of the second sub-isolation layer close to the third sub-isolation layer.
  • the third sub-isolation layer is upwardly warped with respect to the plane where the substrate is located.
  • a groove is provided on the side of the first sub-isolation column.
  • the display substrate further includes a driving circuit layer disposed on the base; the driving circuit layer at least includes a driving transistor, the drain of the driving transistor and the first electrode of the organic electroluminescent diode Connection; the source and drain of the driving transistor and the isolation pillar are arranged in the same layer, and the material is the same.
  • a planarization layer is provided between the source and drain of the driving transistor and the layer where the first electrode of the organic electroluminescent diode is located; the drain of the driving transistor passes through the planarization layer.
  • the via hole is connected to the first pole of the organic electroluminescent diode.
  • a passivation layer, a transfer electrode, a first sub-planarization layer, and a second sub-planarization layer are sequentially arranged between the source and drain of the driving transistor and the layer where the first electrode of the organic electroluminescent diode is located.
  • the transfer electrode is connected to the drain of the driving transistor through a via hole penetrating the passivation layer and the first sub-planarization layer, and the first electrode of the organic electroluminescent diode It is connected to the transfer electrode through a via hole penetrating the second sub-planarization layer.
  • the transition area is provided with a multi-circle cofferdam structure, and the multi-circle cofferdam structure is arranged adjacently; in the multi-circle cofferdam structure, an auxiliary structure is provided at least below the cofferdam structure near the opening area. Structure so that one of the two adjacent cofferdam structures close to the opening area protrudes from the other in a direction away from the substrate; the auxiliary structure and the planarization layer are arranged in the same layer, And the materials are the same.
  • the display substrate further includes a driving circuit layer located thereon;
  • the driving circuit layer includes at least a driving transistor and an interlayer dielectric layer;
  • the active layer of the driving transistor is arranged so that the substrate is close to the organic electroluminescence
  • the first gate insulating layer is the active layer
  • the gate is arranged on the side of the first gate insulating layer away from the active layer
  • the second gate insulating layer covers the gate and the first gate insulating layer.
  • a gate insulating layer, the interlayer dielectric layer covers the second gate insulating layer; the source and drain of the drive transistor are formed on the side of the interlayer dielectric layer away from the substrate; the first The isolation column includes a first sub-isolation column adjacent to the cofferdam structure, and a second sub-isolation column located on a side of the first sub-isolation column close to the display area;
  • a first slot is provided between the first sub-isolation column and the second sub-isolation column, and a second slot is provided between the first sub-isolation column and the cofferdam structure; the first The slot and the second slot penetrate at least one of the interlayer dielectric layer, the first gate insulating layer, and the second gate insulating layer.
  • the thickness of the first packaging layer is 1 ⁇ m-2 ⁇ m; the thickness of the second packaging layer is 10 ⁇ m-15 ⁇ m; the thickness of the third packaging layer is 0.5 ⁇ m-1 ⁇ m.
  • an embodiment of the present disclosure provides a method for manufacturing a display substrate, the display substrate having an opening region, a transition region surrounding the opening region, and a display region surrounding the transition region; wherein, the The preparation method of the display substrate includes:
  • An isolation column and a cofferdam structure are formed on the base; the isolation column and the cofferdam structure are both located in the transition area and surround the opening area; wherein forming the isolation column includes forming a first isolation column, The first isolation column is located on a side of the cofferdam structure close to the display area;
  • An organic electroluminescent diode, a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer are sequentially formed on the side of the layer where the isolation column is located away from the substrate, and the organic electroluminescence diode is located in the display area,
  • the orthographic projections of the first encapsulation layer and the third encapsulation layer on the substrate cover at least the display area and the transition area; the orthographic projections of the second encapsulation layer on the substrate cover the The first isolation column of the display area and the transition area;
  • the ratio of the thickness of the second packaging layer on the first isolation pillar to the thickness of the first isolation pillar is 2:1-6:1.
  • the first isolation column includes a first sub-isolation column, the first sub-isolation column is adjacent to the cofferdam structure, and the orthographic projection of the second encapsulation layer on the substrate and the The ratio of the average thickness of the overlapping area of the first sub-isolation column to the thickness of the first sub-isolation column is 2:1-6:1.
  • the manufacturing method further includes: forming a driving circuit layer on a side of the isolation pillar close to the substrate; the driving circuit layer at least includes a driving transistor;
  • the source and drain of the driving transistor and the isolation pillar are formed by a patterning process.
  • a pixel defining layer between the first electrode of the organic electroluminescent diode and the light emitting layer is further included, the pixel defining layer has a receiving portion for receiving the light emitting layer; the dam structure and The pixel defining layer is formed by a single patterning process.
  • the transition area is provided with a multi-circle cofferdam structure, and the multi-circle cofferdam structure is arranged adjacently; in the multi-circle cofferdam structure, at least the cofferdam structure near the opening area is formed with Auxiliary structure, so that one of the two adjacent weir structures close to the opening area protrudes from the other in a direction away from the substrate; in the layer where the source and drain of the drive transistor are located A planarization layer is formed between the first electrode of the organic electroluminescent diode and the layer where the first electrode is connected to the drain of the driving transistor through a via hole penetrating the planarization layer; the auxiliary structure is connected to the The planarization layer is formed by a single patterning process.
  • embodiments of the present disclosure provide a display panel including the above-mentioned display substrate.
  • FIG. 1 is a display substrate area distribution area according to an embodiment of the disclosure.
  • Fig. 2 is a cross-sectional view of A-A in the display substrate of Fig. 1.
  • Fig. 3 is another cross-sectional view of A-A in the display substrate of Fig. 1.
  • Fig. 4 is a cross-sectional view of B-B in the display substrate of Fig. 1.
  • FIG. 5 is a schematic diagram of an isolation pillar structure of a display substrate according to an embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of another isolation pillar structure of a display substrate according to an embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of the structure of the base of the display substrate according to an embodiment of the disclosure.
  • FIG. 8 is a flowchart of a method for manufacturing a display substrate according to an embodiment of the disclosure.
  • FIG. 9 is a flowchart of another method for manufacturing a display substrate according to an embodiment of the disclosure.
  • Fig. 10 is a detailed flowchart of step S11.
  • an embodiment of the present disclosure provides a display substrate divided into a display area Q1, a transition area Q2, and an opening area Q3; wherein the transition area Q2 surrounds the via area Q3 and the display area.
  • Q1 surrounds the transition zone Q2.
  • the display substrate includes a base 101 and a pixel structure arranged on the base 101 in the display area Q1.
  • the pixel structure includes at least a driving circuit layer and a light-emitting device.
  • the driving circuit layer usually includes at least a switching transistor, a driving transistor, and a storage capacitor (that is, the existing 2T1C pixel drive circuit), light-emitting devices include but are not limited to Organic Light Emitting Diode (OLED) 1d.
  • OLED Organic Light Emitting Diode
  • the display substrate further includes an isolation pillar 120 located in the transition area Q2; a planarization layer 117 is formed on the side of the isolation pillar 120 away from the base 101, and the display area Q1 corresponds to the position of the drain 111 of the driving transistor in the driving circuit layer
  • the via is etched so that the first electrode 112 of the organic electroluminescent diode 1d formed on the planarization layer 117 can be connected to the drain 111 of the driving transistor through the via. Since the isolation pillar 120 is formed in the transition region Q2, the light-emitting layer 114 and the second electrode 115 of the organic electroluminescent diode are disconnected in the transition region Q2 between the display region Q1 and the via region Q3, so as to avoid the via region.
  • the display substrate also includes the second electrode 115 sequentially arranged on the organic electroluminescent diode 1d
  • the display substrate further includes a through hole located in the opening area Q3 and penetrating the display substrate.
  • the perforated area Q3 in the display substrate of the embodiment of the present disclosure forms a through hole after the perforating process, which is used to assemble devices such as a camera, a sensor, a HOME key, an earpiece, or a speaker.
  • the opening area Q3 has not been subjected to opening treatment, and the opening treatment can be carried out before assembling the camera and other devices.
  • the display substrate of the embodiment of the present disclosure has been subjected to the opening treatment in the opening area Q3. In this case, the display substrate can be directly used for subsequent assembly.
  • the driving circuit layer may be formed on the buffer layer 102.
  • the driving circuit layer may include an interlayer dielectric layer 103 located in the display area Q1 and the transition area Q2.
  • the interlayer dielectric layer 103 is made of inorganic materials, such as silicon oxide, silicon nitride and other inorganic materials.
  • the drive circuit layer also includes drive transistors and storage capacitors located in the display area, and of course also includes switching elements such as switching transistors.
  • the structure is the same as that of the drive transistor and can be It is prepared in the process, so it will not be explained one by one here.
  • the driving transistor may be a top-gate type, and the driving transistor may include an active layer 104, a first gate insulating layer 105, a gate 106, a second gate insulating layer 108, an interlayer dielectric layer 103, and a source electrode. 110, the drain 111.
  • the active layer 104 may be formed on the buffer layer 102, the first gate insulating layer 105 covers the buffer layer 102 and the active layer 104, and the gate 106 is formed on the side of the first gate insulating layer 105 away from the active layer 104
  • the second gate insulating layer 108 covers the gate 106 and the first gate insulating layer 105
  • the interlayer dielectric layer 103 covers the second gate insulating layer 108
  • the source 110 and the drain 111 are formed on the interlayer dielectric layer 103 away from the base substrate
  • the source electrode 110 and the drain electrode 111 can respectively pass through via holes (for example, metal via holes) with the source contact area and the source electrode contact area on the opposite sides of the active layer 104
  • the drain contact area is in contact.
  • the driving transistor may also be a bottom gate type.
  • the capacitor structure may include a first electrode plate 130 and a second electrode plate 131.
  • the first electrode plate 130 and the gate electrode 103 are arranged in the same layer, and the second electrode plate 131 is located on the second gate insulating layer 105 and the layer Between the dielectric layers 103 and opposite to the first electrode plate 130, they are arranged.
  • the materials of the gate 103, the first electrode plate 130, and the second electrode plate 131 may include metal materials or alloy materials, such as molybdenum, aluminum, and titanium.
  • the source 110 and the drain 111 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, etc.
  • the multi-layer structure is a multi-metal laminate layer, such as titanium, aluminum, Titanium three-layer metal laminate (Al/Ti/Al), etc.
  • a planarization layer 117 is provided on the side of the driving transistor away from the substrate 101, and the planarization layer 117 is located in the display area Q1.
  • the planarization layer 117 is usually made of organic materials, such as photoresist, acrylic-based polymer, silicon-based polymer and other materials.
  • the organic electroluminescent diode 1d is located in the display area Q1.
  • the organic electroluminescent diode 1d may include the first electrode 112 of the organic electroluminescent diode 1d and the pixel defining layer sequentially formed on the planarization layer 117. 113. It should be understood that the organic electroluminescent diode 1d may further include a light-emitting layer 114 and a second electrode 115.
  • the first electrode 112 of the organic electroluminescent diode 1d can be electrically connected to the drain 111 of the driving transistor through a via hole penetrating the planarization layer 117.
  • the first electrode 112 can be an anode, and the anode can be ITO (oxidized ITO).
  • the pixel defining layer 113 can cover the planarization layer 117, and the pixel defining layer 113 can be made of organic materials, such as photolithography
  • the pixel defining layer 113 may have a receiving portion exposing the first electrode 112; the light-emitting layer is located in the receiving portion and formed on the first electrode 112, and the light-emitting layer 114 may include small molecular organic materials or polymer molecular organic materials.
  • the material can be a fluorescent light-emitting material or a phosphorescent light-emitting material, which can emit red light, green light, blue light, or white light, etc.; and, according to actual needs, in different examples, the light-emitting layer 114 may further include electron injection Layer, electron transport layer, hole injection layer, hole transport layer and other functional layers; the second pole 115 covers the light-emitting layer, and the polarity of the second pole 115 is opposite to the polarity of the first pole 112; this second pole 115 can be a cathode, and the cathode can be made of metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), and silver (Ag).
  • the first electrode 112, the light-emitting layer, and the second electrode 115 can constitute an organic electroluminescent diode 1d.
  • the display area Q1 includes organic electroluminescent diodes 1d arranged in an array.
  • the first electrode 112 of each organic electroluminescent diode 1d is independent of each other, and the second electrode 115 of each organic electroluminescent diode 1d can be connected over the entire surface; that is, the second electrode 115 is arranged on the display substrate
  • the entire surface structure on 10 is a common electrode for a plurality of organic electroluminescent diodes 1d.
  • the first electrode 112 of the organic electroluminescent diode 1d can also be electrically connected to the drain 111 through the transfer electrode 133.
  • the planarization portion 117 may have a double-layer structure, and specifically may include a first sub-planarization (PLN1) layer 117a and a second sub-planarization (PLN1) layer 117a and a second sub-layer that are sequentially formed.
  • a passivation (PVX) layer 116 may be formed between the first sub-planarization layer 117a and the interlayer dielectric layer 103.
  • the passivation layer 116 may be silicon oxide, silicon nitride or The passivation layer 116 covers the source 110 and the drain 111; and the transfer electrode 133 is formed between the first sub-planarization layer 117a and the second sub-planarization layer 117b, and passes through the first sub-planarization layer 117a and 117b sequentially.
  • a sub-planarization layer 117a and a via (e.g., metal via) on the passivation layer 116 are electrically connected to the drain 111; and the first electrode 112 can pass through a via (e.g., metal via) on the second sub-planarization layer 117b.
  • the via is electrically connected to the transfer electrode 133, thereby completing the connection between the first electrode 112 of the organic electroluminescent diode 1d and the drain 111 of the driving transistor.
  • the side of the pixel defining layer 113 away from the interlayer dielectric layer 103 may also be provided with a supporting portion 132, which may serve to support the protective film layer (not shown in the figure). To prevent the protective film layer from contacting the first pole 112 or other traces, which may cause the first pole 112 or other traces to be easily damaged.
  • this protective film layer mainly occurs during the transfer of semi-finished products to avoid damage to the semi-finished products during the transfer process, specifically: in the process of transferring the substrate on which the support portion 132 has been fabricated to the evaporation production line , Can be covered with a protective film layer, when the luminescent material needs to be evaporated, the protective film layer is removed.
  • the material of the support portion 132 can be the same as that of the pixel defining layer 113, and the support portion 132 and the pixel defining layer 113 can be formed by the same patterning process, but it is not limited to this.
  • the material of the support portion 132 can also be the same as that of the pixel defining layer.
  • the materials of 113 are different, and the supporting portion 132 and the pixel defining layer 113 can also be formed by different patterning processes.
  • the isolation pillar 120 is located in the transition area Q2, is disposed around the opening area Q3, and is disposed on the side of the passivation layer 116 away from the substrate 101.
  • the light-emitting layer 114 and the second electrode 115 of the organic electroluminescent diode 1d are disconnected between the isolation pillar 120 and the isolation pillar 120 in the transition region Q2 to avoid the existence of via holes in the via region Q3, which may cause corrosion by water, oxygen, etc.
  • the organic electroluminescent diode 1d in the display area causes poor display.
  • the structure shown in FIG. 4 may not include the passivation layer 116 and the second electrode 115 of the organic light emitting diode 1d.
  • a dam structure 150 is also provided in the transition area Q4.
  • the dam structure 150 can prevent the flow of the organic encapsulation film layer material in the encapsulation layer 118.
  • the hole area Q3 enters the display area Q1, so that the failure of the organic electroluminescent diode 1d in the display area Q1 can be avoided and the display effect is poor, and the service life of the product is prolonged.
  • the encapsulation layer 118 of the display substrate 10 may include a first encapsulation layer 118a, a second encapsulation layer 118b, and a third encapsulation layer 118c stacked in sequence.
  • the first encapsulation layer 118a and the third encapsulation layer 118c encapsulate the organic electroluminescent diode 1d, the isolation pillar 120 and the dam structure 150, and the second encapsulation layer 118b encapsulates the organic electroluminescence diode 1d, and the dam structure 150 is close to the display One side of zone Q1 is blocked.
  • the first encapsulation layer 118a and the third encapsulation 118c layer are used to prevent water and oxygen from entering the light emitting layer 114 of the display area Q1 from the display side of the display function and the opening area Q3; the first encapsulation layer 118a and the third encapsulation layer 118c can be made of inorganic materials such as silicon nitride and silicon oxide.
  • the second encapsulation layer 118b is used to achieve a planarization effect to facilitate the production of the third encapsulation film layer 118c.
  • the second encapsulation layer 118b can be made of acrylic-based polymer, silicon-based polymer, or other materials.
  • the first encapsulation layer 118a and the third encapsulation layer 118c can be made by chemical vapor deposition process, but not limited to this, physical vapor deposition process, etc. can also be used; and the second encapsulation layer 118b can be made by inkjet printing process , But not limited to this, spraying process etc. can also be used.
  • the dam structure 150 can restrict the flow of the material of the second encapsulation layer 118b and avoid the second encapsulation layer 118b. The material flow to the opening area Q3 causes the problem of package failure.
  • the dam structure 150 and the pixel defining layer 113 are arranged in the same layer, that is, the dam structure 150 and the pixel defining layer 113 can be formed at the same time through a single patterning process, which can reduce the processing steps and the use of masks. , Which can reduce costs.
  • the dam structure and the pixel defining layer 113 should be disconnected from each other.
  • the cofferdam structure 150 can also be a structure formed of stacked insulating materials. For example, a first sub cofferdam layer provided on the same layer as the pixel defining layer 113 and a second sub cofferdam layer provided on the same layer as the support portion 132 can be adopted. The structure formed by layer stacking.
  • the isolation column includes a first isolation column 120 located on the side of the cofferdam structure close to the display area Q1; wherein, the first isolation column 120 includes a first isolation column 120 disposed adjacent to the cofferdam structure 150 A sub-isolation column 120a.
  • the number of the first sub-isolation column 120a may be one or multiple. In the embodiment of the present disclosure, the number of the first sub-isolation column 120a is taken as an example.
  • the first isolation pillar 120 may also include a second sub isolation pillar 120b located near the display area Q1 of the first sub isolation pillar 120a, and the structure of the second sub isolation pillar 120b may be the same as or different from the first sub isolation pillar 120a.
  • the second sub-isolation column 120b and the first sub-isolation column 120a are the same as an example for description.
  • the number of the second sub-isolation column 120b can also be one or more. In the disclosed embodiment, the number of the second sub-isolation column 120b is one as an example.
  • the isolation column may further include a second isolation column 121 located on the side of the cofferdam structure close to the transition area Q2, wherein the number of the second isolation column 121 may be one or more, and its structure may be the same as
  • the first sub-isolation column 120a and the second sub-isolation column 120b have the same structure.
  • the two sub-isolation columns may be inconsistent in structure. Take the same structure of 120b as an example.
  • FIG. 4 illustrates that the isolation column includes two second isolation columns 121, but this does not constitute a limitation to the embodiment of the present disclosure.
  • a specific structure of the first sub-isolation column 120a is provided.
  • the first sub-isolation column 120a of this structure is used to ensure the light-emitting layer 114 of the organic electroluminescent diode 1d.
  • the edge of the first isolation pillar 120a structure in the transition region Q2 is completely disconnected, and the first sub-isolation pillar 120a may include a first sub-isolation layer 120a1, a second sub-isolation layer 120a2, and a third sub-isolation layer 120a3 that are stacked.
  • the projection on the substrate 101 that is, the cross section of the first sub-isolation column 120a perpendicular to the direction of the substrate 101 has a groove (as shown in FIGS. 5 and 6, the side surface of the second sub-isolation layer 120a2 is compared with the first sub-isolation
  • the isolation layer 120a1 and the third sub-isolation layer 120a2 are recessed, that is, a side groove of the isolation column is formed).
  • the material of the first sub-isolation layer 120a1 and the third sub-isolation layer 120a3 of the isolation pillar 120 is titanium Ti, and the material of the second sub-isolation layer 120a2 is aluminum Al.
  • the metal Al material and the Ag ions in the etching solution undergo a substitution reaction during wet etching to form Ag particles with a size of about 1 to 5um, which have strong adhesion. , It is not easy to remove, and eventually become conductive particles, which appear as dark spots.
  • the silver and Ag ions in the etching solution may be replaced, so that a layer of silver particles is attached to the upper surface of the second sub-isolation layer 120a2 (as shown in FIG. 5)
  • the third sub-isolation layer 120a3 in the formed first isolation pillar 120a may also be upturned (as shown in FIG. 6).
  • the third packaging layer 118c above the isolation pillars is formed with a risk of fracture at the position corresponding to the isolation pillars, and once the third packaging layer 118c is broken, the packaging of the display substrate will fail.
  • an embodiment of the present disclosure provides a display substrate, in which the first isolation column 120 located on the side of the cofferdam structure 150 close to the display area Q1 and adjacent to the cofferdam structure 150 is away from the base 101
  • the ratio of the thickness of the second encapsulation layer 118b on one side to the thickness of the first spacer 120 includes 2:1 to 6:1, so that the surface of the second encapsulation layer 118b that is formed away from the substrate 101 is substantially flat, thereby avoiding the formation of
  • the third encapsulation layer 118c on the surface of the second encapsulation layer 118b away from the base 101 is broken, and the problem of display substrate encapsulation failure occurs.
  • the average thickness D1 of the area where the orthographic projection of the second encapsulation layer 118b on the substrate 101 overlaps the first sub-isolation column 120a and the thickness D2 of the first sub-isolation column 120a The ratio is 2:1 to 6:1.
  • D1:D2 is 2:1
  • the surface facing away from the substrate 101 forming the second encapsulation layer 118b can be made roughly flat.
  • the thickness of the second encapsulation layer 118b can be made to avoid the formation of While the third encapsulation layer 118c on the second encapsulation layer 118b is broken, it is also possible to prevent the second encapsulation layer 118b from being too thick, which affects the lightness and thinness of the display substrate.
  • the thickness of the second encapsulation layer 118b is thinner the closer to the dam structure 150, that is, the thickness of the second encapsulation layer 118b changes from The thickness of the display area Q1 to the transition area Q2 is gradually reduced, and the first sub-isolation column is arranged adjacent to the cofferdam structure 150.
  • the ratio of the average thickness D1 of the region to the thickness D2 of the first sub-isolation column 120a is 2:1 to 6:1, so the thickness of the second encapsulation layer 118b and the first sub-isolation column 120a in the remaining positions of the transition region Q2
  • the thickness D2 ratio must be greater than 2:1-6:1, so the third packaging layer 118c formed on the second packaging layer 118b away from the surface of the base 101 can be completely prevented from breaking, and the display substrate packaging failure problem can occur.
  • the ratio of the average thickness D1 of the area where the orthographic projection of the second encapsulation layer 118b on the substrate 101 and the first sub-isolation column 120a overlaps to the thickness D2 of the first sub-isolation column 120a is 6:1.
  • the second encapsulation layer 118b and the first sub-isolation column 120a with corresponding thickness ratios are adopted according to product requirements.
  • the ratio of the thickness D1 of the second encapsulation layer 6 to the thickness D2 of the first sub-isolation column 120a is 2:1, 3. :1, 4:1, etc.
  • the thickness of the isolation pillar includes but is not limited to 0.4 ⁇ m-0.7 ⁇ m.
  • spacers 120 of different thicknesses can also be selected according to the thickness of the light-emitting layer 114 of the organic electroluminescent diode 1d, and the thickness of the spacers can be as long as the light-emitting layer 114 of the organic electroluminescent diode 1d can be disconnected at the transition region Q2. .
  • the isolation pillar can be arranged in the same layer as the source 110 and the drain 111 of the driving transistor, that is, the isolation pillar, the source 110 and the drain 111 are formed by the same patterning process. This design can also reduce the processing steps. And the use of mask, which can reduce costs. In addition, it should be understood that the isolation pillar may be disconnected from the source 110 and the drain 111 of the driving transistor to avoid the isolation pillar 124 being energized during display.
  • the structure and material of the isolation pillar may be the same as the structure and material of the source 110 and the drain 111, for example When the source 110 and the drain 111 have a three-layer metal structure, the isolation pillar may also have a three-layer metal structure.
  • the first sub-isolation column 120a in the isolation column may include a first sub-isolation layer 120a1, a second sub-isolation layer 120a2, and a third sub-isolation layer 120a1, a second sub-isolation layer 120a2, and a third sub-isolation layer 120a1 that are sequentially stacked on the interlayer dielectric layer 103 Isolation layer 120a3, the outer boundary of the orthographic projection of the second sub-isolation layer 120a2 on the interlayer dielectric layer 103 is located at the outer boundary of the orthographic projection of the first sub-isolation layer 120a1 and the third sub-isolation layer 120a3 on the interlayer dielectric layer 103 On the inner side, a groove is formed on the sidewall of the isolation column 120, so that the longitudinal section of the isolation column 120 has an "I-shaped" structure.
  • the material of the first sub-isolation layer 120a1 and the third sub-isolation layer 120a3 may be a titanium layer, that is, the first sub-isolation layer 120a1 and the third sub-isolation layer 120a3 may be made of titanium (Ti) material, and the second The sub-isolation layer 120a2, that is, the second sub-isolation layer 120a2 can be made of aluminum (Al) material, which can ensure that when the second sub-isolation layer 120a2 undergoes side etching, the first sub-isolation layer 120a1 is isolated from the third sub-isolation layer 120a1 and the third sub-isolation layer 120a2.
  • the layer 120a3 will not be affected by etching.
  • the first sub-isolation layer 120a1, the second sub-isolation layer 120a2, and the third sub-isolation layer 120a3 can also be made of other materials, such as: molybdenum, aluminum and other metal materials or alloy materials, as long as the above can be achieved The technical effect is sufficient, and the present disclosure does not limit this.
  • the difference between the first sub-isolation layer 120a1 and the third sub-isolation layer 120a3 includes but is not limited to 0.04 ⁇ m-0.08 ⁇ m; the thickness of the second sub-isolation layer 120a2 includes but is not limited to 0.4 ⁇ m-0.6 ⁇ m.
  • the first sub-isolation layer 120a1, the second sub-isolation layer 120a2, the third sub-isolation layer 120a3, the first sub-isolation layer 120a1, the second sub-isolation layer 120a3, the The total thickness of the second sub-isolation layer 120a2 and the third sub-isolation layer 120a3 only needs to satisfy that the light-emitting layer 114 of the organic electroluminescent diode 1d can be disconnected at the edge of the first sub-isolation column 120a of the transition region Q2.
  • the driving circuit layer has a first slot 125 and a second slot 126 located in the transition area Q2; the first slot 125 is located in the first sub-isolation pillar 120a and the second sub-isolation Between the columns 120b, the first slot 125 is arranged around the first sub-isolation column 120a; the second slot 126 is located between the first sub-isolation column 120a and the cofferdam structure 150, and the second slot 126 is arranged around the cofferdam structure.
  • the probability that the luminescent material is disconnected at the side of the isolation pillar 120 can be increased.
  • the first slot 125 and the second slot 126 can penetrate at least one of the dielectric layer 103, the first gate insulating layer 105, and the second gate insulating layer 108 in the transition region Q2, for example, the first slot 125 And the second slot 126 can penetrate the dielectric layer 103, the first gate insulating layer 105, the second gate insulating layer 108, and the passivation layer 116 of the transition region Q2, that is, the slot can extend to the buffer layer 102.
  • the first slot 125 and the second slot 126 can penetrate the entire driving circuit layer to further increase the probability that the luminescent material or the cathode material is disconnected on the side of the isolation column 124; in addition, the display substrate 10 When flexible and bent, this design can also relieve the stress on the portion of the drive circuit layer located in the display area 10a, and ensure the connection reliability of the components in the drive circuit layer.
  • a third slot 127 can also be provided between the second isolation column 121 and the second isolation column 121, and the third slot 127 is connected to the first slot 125 and the second slot.
  • the structure of the grooves 126 can be the same; when the opening area Q3 is circular, the orthographic projection of the first groove 125, the second groove 126, and the spacer 120 on the base substrate can also be a circular ring; in the opening area When Q3 is rectangular, the orthographic projection of the first slot 125, the second slot 126, the first sub-isolation column 120a, the second sub-isolation column 120b, and the second isolation column 121 on the substrate 101 can also be a rectangular ring; but Not limited to this opening area Q3 can also be other regular or irregular shapes, the first slot 125, the second slot 126, the third slot 127, the first sub-isolation column 120a, the second sub-isolation column 120b, and the The two isolation columns 121 can be adapted to
  • the thickness range of the first encapsulation layer 118a includes but is not limited to 1 ⁇ m-2 ⁇ m
  • the thickness range of the second encapsulation layer 118b includes but is not limited to 10 ⁇ m-15 ⁇ m
  • the thickness range of the third encapsulation layer 118c includes but is not limited to 0.5 ⁇ m-1 ⁇ m.
  • the cofferdam structure 150 has multiple circles, and the multi-circle cofferdam structures 150 are arranged adjacent to each other; in the multi-circle cofferdam structure 150, an auxiliary structure 140 is provided at least below the cofferdam structure 150 near the opening area Q3. , So that one of the two adjacent cofferdam structures 150 close to the opening area Q3 protrudes from the other in a direction away from the base 101.
  • the two circles of cofferdam structures 150 are arranged on the second circle of isolation columns 120 and the second circle in the direction from the display area Q1 to the opening area. Between the three circles of isolation columns 120, the cofferdam structure 150 near the via area Q3 is provided with an auxiliary structure 130 on the side close to the base 101, so that the cofferdam structure 120 protrudes farther away from the base 101 in the direction away from the base 101.
  • the reason for this arrangement is that in the direction along the display area Q1 pointing to the opening area Q3, even if the first dam structure 150 cannot block the material of the second encapsulation layer 118b, the second dam structure 150 can also be used to block the second encapsulation layer 118b. The material of the encapsulation layer 118b is blocked.
  • the auxiliary structure 130 may be provided in the same layer as the planarization layer 117 and have the same material. In this way, the auxiliary structure 130 can be formed at the same time as the planarization layer 117 is formed, so that the process steps can be simplified and the production efficiency can be improved.
  • the auxiliary structure 130 can also be provided in the same layer as at least one of the dielectric layer 103, the first gate insulating layer 105, and the second gate insulating layer 108, and the material is the same.
  • the base 101 may be a flexible substrate to improve the flexibility of the display substrate, so that the display substrate 1 can have properties such as bendability and bendability, so as to expand the application range of the display substrate; But it is not limited to this, the base may also be set to be rigid, and the specific performance of the base substrate may be determined according to the actual requirements of the product.
  • the substrate 101 may have a single-layer structure or a multi-layer structure.
  • the base substrate may include a polyimide layer 101a, a buffer layer 101b, and a polyimide layer 101c stacked in sequence, wherein the buffer layer 101b may be silicon nitride, silicon oxide, etc. It is made of materials to achieve the effects of blocking water and oxygen and blocking alkaline ions; it should be noted that the structure of the base substrate is not limited to this, and can be determined according to actual needs.
  • embodiments of the present disclosure provide a method for preparing a display substrate, and the method can be used to prepare the above-mentioned display substrate.
  • the display substrate has a display area Q1, a transition area Q2, and an opening area Q3; as shown in FIG. 9, the method includes:
  • the isolation column includes a first isolation column 120 located on the side of the bank structure 150 close to the display area Q1, which is used to disconnect the organic light-emitting layer at the transition area Q2 between the display area Q1 and the opening area Q3 to avoid opening
  • the water, oxygen, etc. at the through holes of the hole region Q3 erodes the organic electroluminescent diode 1d in the display region Q1, and affects the performance of the organic electroluminescent diode 1d.
  • a first encapsulation layer 118a, a second encapsulation layer 118b, and a third encapsulation layer 118c are sequentially formed to seal the organic electroluminescence diode 1d.
  • the thickness of the second encapsulation layer 118b on the side of the first isolation pillar 120 away from the substrate 101 and the thickness ratio of the first isolation pillar 120 include 2:1 to 6:1, so that the formed second encapsulation layer 118b is away from the substrate 101
  • the surface of the second encapsulation layer 118b is substantially flat, so as to prevent the third encapsulation layer 118c formed on the second encapsulation layer 118b away from the surface of the base from breaking, and the problem of the display substrate encapsulation failure.
  • the average thickness D1 of the area where the orthographic projection of the second encapsulation layer 118b on the substrate 101 overlaps the first sub-isolation column 120a and the thickness D2 of the first sub-isolation column 120a The ratio is 2:1 to 6:1.
  • the reason for this is that, for the second encapsulation layer 118b, due to the fluidity of its material, the thickness of the second encapsulation layer 118b is thinner the closer to the dam structure 150, that is, the thickness of the second encapsulation layer 118b changes from The thickness of the display area Q1 to the transition area Q2 is gradually reduced, and the first sub-isolation column is arranged adjacent to the cofferdam structure 150.
  • the ratio of the average thickness D1 of the region to the thickness D2 of the first sub-isolation column 120a is 2:1 to 6:1, so the thickness of the second encapsulation layer 118b and the first sub-isolation column 120a in the remaining positions of the transition region Q2
  • the thickness D2 ratio must be greater than 2:1-6:1, so the third packaging layer 118c formed on the second packaging layer 118b away from the surface of the base 101 can be completely prevented from breaking, and the display substrate packaging failure problem can occur.
  • the method specifically includes the following steps:
  • a substrate 101 is provided, and a driving circuit layer in a pixel structure, an organic electroluminescent diode 1d and an isolation pillar 120 are formed on the substrate 101.
  • step S11 may include the following steps:
  • S111 forming a buffer layer 102 located in the display area Q1 and the transition area Q2 on the substrate 101; and forming the buffer layer 102 and each layer of the drive circuit layer (switching transistor, drive transistor, storage capacitor, etc.) located in the display area Q1 Structures and isolation pillars located in the transition region Q2, such as the active layer 104 of the driving transistor, the first gate insulating layer 105, the gate 106, the second gate insulating layer 108, the interlayer dielectric layer 103, the source 110, and the drain 111 .
  • the drive circuit layer switching transistor, drive transistor, storage capacitor, etc.
  • the active layer 104 may be formed on the buffer layer 102, the first gate insulating layer 105 covers the buffer layer 102 and the active layer 104, and the gate 106 is formed on the side of the first gate insulating layer 105 away from the active layer 104
  • the second gate insulating layer 108 covers the gate 106 and the first gate insulating layer 105
  • the interlayer dielectric layer 103 covers the second gate insulating layer 108
  • the source 110 and the drain 111 are formed on the interlayer dielectric layer 103 away from the base substrate
  • the source electrode 110 and the drain electrode 111 can respectively pass through via holes (for example, metal via holes) with the source contact area and the source electrode contact area on the opposite sides of the active layer 104
  • the drain contact area is in contact.
  • the driving transistor may also be a bottom gate type.
  • the capacitor structure may include a first electrode plate 130 and a second electrode plate 131.
  • the first electrode plate 130 and the gate electrode 103 are arranged in the same layer, and the second electrode plate 131 is located on the second gate insulating layer 105 and the layer Between the dielectric layers 103 and opposite to the first electrode plate 130, they are arranged.
  • the isolation column includes a first isolation column 120 and a second isolation column 121; wherein, the first isolation column 120 includes a first sub-isolation column 120a and a second sub-isolation column 120b.
  • the first sub-isolation pillar 120a, the second sub-isolation pillar 120b, and the second isolation pillar 121 and the source 110 and the drain 111 of the driving transistor may be formed in one patterning process.
  • the first sub-isolation pillar 120a, the second sub-isolation pillar 120b, and the second isolation pillar 121 may also have a three-layer metal structure.
  • the first sub-isolation column 120a, the second sub-isolation column 120b, and the second sub-isolation column 121 all include a first sub-isolation layer 120a1, a second sub-isolation layer 120a2, and a third sub-isolation layer 120a1, a second sub-isolation layer 120a2, and a third sub-isolation layer 120a1, a second sub-isolation layer 120a2, and a third sub-isolation layer 120a1, a second sub-isolation layer 120a2, and a The isolation layer 120a3.
  • forming the first sub-isolation pillar 120a of the three-layer structure may include the following steps:
  • a first sub-isolation material layer is sequentially formed on the interlayer, and the first sub-isolation layer 120a1 is formed by wet etching.
  • a second sub-isolation material layer is sequentially formed on the interlayer, and the second sub-isolation layer 120a2 is formed by wet etching.
  • a third sub-isolation material layer is sequentially formed on the interlayer, and the third sub-isolation layer 120a3 is formed by wet etching.
  • the first sub-isolation column 120a has a groove in a cross section perpendicular to the direction of the substrate 101.
  • the material of the first sub-isolation layer 120a1 and the third sub-isolation layer 120a3 is titanium Ti
  • the material of the second sub-isolation layer 120a2 is aluminum Al.
  • the isolation pillar 2 is not limited to the isolation pillar 120 with a three-layer structure, and the isolation pillar 120 may also have a four-layer structure or even more layers.
  • the isolation pillar 120 includes the above-mentioned three-layer structure of the first sub-isolation layer 120a1, the second sub-isolation layer 120a2, and the third sub-isolation layer 120a3, wherein, due to the etching process, the second sub-isolation layer 120a2 is close to the first sub-isolation layer 120a2.
  • the surface of the three sub-isolation layer 120a3 is attached with a granular structure.
  • the sub-isolation layer 120a3 is tilted up relative to the plane of the substrate 101 (that is, tilted toward the direction away from the substrate 101).
  • a planarization layer 117 in the display area Q1 and an auxiliary structure 140 in the transition area are formed, and the driving circuit layer in the display area Q1 A via hole penetrating the planarization layer 116 and the interlayer insulating layer 117 is formed at a position corresponding to the drain 111 of the driving transistor in.
  • the planarization layer 117 and the auxiliary structure 140 formed in step S112 are arranged in the same layer and have the same material, that is, the two are formed by a single patterning process.
  • step S113 On the substrate 101 where the planarization layer 117 and the auxiliary structure 140 are formed, the first electrode 112 of the organic electroluminescent diode 1d is formed, and the first electrode 112 of the organic electroluminescent diode 1 is formed in step S112 The hole is connected to the drain 111 of the driving transistor.
  • a pixel defining layer 113 located in the display area Q1 and a dam structure 150 located in the transition area Q2 are formed; wherein the pixel defining layer 113 is in contact with each other.
  • An accommodating portion is formed at a position corresponding to the first pole 112 of the electromechanical light-emitting diode 1d, and one of the cofferdam structure 150 close to the via area Q3 is disposed on the auxiliary structure 140.
  • the pixel defining layer 113 and the dam structure 150 formed in step S114 are arranged in the same layer and have the same material, that is, the two are formed by a single patterning process.
  • the light emitting layer 114 of the organic light emitting diode 1d is formed by a method including but not limited to inkjet printing. Since the isolation pillar 120 is formed in the transition region Q2, it is formed The light emitting layer of the organic electroluminescent device 1d above the isolation pillar 120 is disconnected.
  • the second electrode 115 of the organic light-emitting diode 1d is formed by an evaporation process including but not limited to.
  • a passivation layer 116 may be formed first, a via hole is formed at the position of the passivation layer 116 corresponding to the drain electrode 111 of the driving transistor, and the passivation layer 116 is away from the substrate 101.
  • a transfer electrode 133 is formed on one side of the passivation layer 116 so that the transfer electrode 133 is connected to the drain 111 of the driving transistor through a via hole penetrating the passivation layer 116, and then the first sub-planarization layer 117a and the second sub-planarization layer are sequentially formed Layer 117b, and via holes are formed at the positions of the first sub-planarization layer 117a and the second sub-planarization layer 117b corresponding to the transfer electrode 133.
  • step S113 is performed to connect the first electrode 112 of the organic electroluminescent diode 1d formed in step S113 to the via electrode 133 through the via hole penetrating the first sub-planarization layer 117a and the second sub-planarization layer 117b .
  • the material of the first encapsulation layer 118a may be using chemical vapor deposition, physical vapor deposition, atomic force is formed on the deposition SiN x, SiON, SiO x, etc., first encapsulation layer 118a.
  • a support structure (not shown in the figure) located in the opening area Q3 is formed.
  • the material of the support structure may be at least one of polyamide, polyester, and polycarbonate. Using these fast curing rate materials can directly avoid material flow
  • the orthographic projection of the second encapsulation layer 118b on the substrate 101 is located in a part of the transition area Q3 and the display area Q1.
  • the material of the second encapsulation layer 118b may include acrylic-based polymer, silicon-based polymer, and the like.
  • the second encapsulation layer 118b can be formed on the first encapsulation layer 118a by inkjet printing, spray coating, or the like.
  • the orthographic projection of the third encapsulation layer 118c on the substrate 101 is located in the transition area Q2 and the display area Q1.
  • the material of the third encapsulation layer 7 may be SiN x , SiCN, SiO 2, etc., and the third encapsulation layer 118 c may be formed by chemical vapor deposition, physical vapor deposition, atomic force deposition, or the like.
  • first encapsulation layer 118a formed in step S12 and the third encapsulation layer 118c formed in step S15 are inorganic encapsulation layers, and the second encapsulation layer 118b formed in step S14 is an organic encapsulation layer.
  • a protective layer is formed on the side of the third encapsulation layer 118c away from the substrate 101, and the supporting structure 8 supports the protective layer.
  • the protective layer is lifted up by the support structure, which prevents the protective layer from having too large a gap between the opening area Q3 and the display area Q1, and improves the flatness of the protective layer, so that when the protective layer is removed, the third encapsulation layer 118c will not Being brought up prevents the third encapsulation layer 118c from being peeled off from the second encapsulation layer 118b, ensures the encapsulation effect, and improves the product yield of the display panel.
  • the third encapsulation layer 118c will not be lifted up when the protective layer is peeled off, which prevents the third encapsulation layer 118c from being removed from the second encapsulation.
  • the layer 118b is peeled off.
  • a through hole is formed in the opening area Q3, so as to achieve the purpose of opening a hole on the screen.
  • the through hole is formed in the opening area, since the supporting structure is located on the opening area, the area corresponding to the opening area of the display substrate and the supporting structure can be removed at the same time through the same process.
  • the opening area on the substrate and the removal of the supporting structure can also be displayed separately through two processes, which is not limited in the embodiment of the present disclosure.
  • embodiments of the present disclosure also provide a display panel, which includes the above-mentioned display substrate.
  • the display panel can be, for example, an electronic device with a display panel such as a mobile phone, a tablet computer, an electronic watch, a sports bracelet, or a notebook computer.
  • the technical effects of the display device can be referred to the above discussion on the technical effects of the display panel, which will not be repeated here.

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Abstract

本公开提供一种显示基板及显示面板，属于显示技术领域。本公开的显示基板，其具有开孔区、环绕所述开孔区的过渡区，以及环绕所述过渡区的显示区；所述显示基板包括：基底，隔离柱、围堰结构，均设置在所述基底上，位于所述过渡区且环绕所述开孔区；其中，所述隔离柱包括第一隔离柱，所述第一隔离柱位于所述围堰结构靠近所述显示区的一侧；有机电致发光二极管、第一封装层、第二封装层、第三封装层，依次设置在所述基底上，所述有机电致发光二极管位于所述显示区，所述第一封装层和所述第三封装层在所述基底上的正投影至少覆盖所述显示区和所述过渡区；所述第二封装层在所述基底上的正投影覆盖所述显示区和所述过渡区的所述第一隔离柱；其中，位于所述第一隔离柱上的所述第二封装层的厚度，与所述第一隔离柱的厚度比为2:1～6:1。

Description

显示基板及显示面板 技术领域
本公开属于显示技术领域，具体涉及一种显示基板及显示面板。
背景技术
随着用户的对产品要求的日益增长以及行业内激烈的竞争环境，大部分手机厂商都在追求更高的屏幕屏占比，以期给用户带来更炫的视觉冲击，赢得市场竞争。但是，对于摄像头及一些感应器来说，却限制着屏幕往更高的屏占比发展，将摄像头及一些感应器放于屏内正备受业内的高度关注。
发明内容
本公开旨在至少解决现有技术中存在的技术问题之一，提供一种显示基板及显示面板。
第一方面，本公开实施例提供一种显示基板，其具有开孔区、环绕所述开孔区的过渡区，以及环绕所述过渡区的显示区；所述显示基板包括：
基底，
隔离柱、围堰结构，均设置在所述基底上，位于所述过渡区且环绕所述开孔区；其中，所述隔离柱包括第一隔离柱，所述第一隔离柱位于所述围堰结构靠近所述显示区的一侧；有机电致发光二极管、第一封装层、第二封装层、第三封装层，依次设置在所述基底上，所述有机电致发光二极管位于所述显示区，所述第一封装层和所述第三封装层在所述基底上的正投影至少覆盖所述显示区和所述过渡区；所述第二封装层在所述基底上的正投影覆盖所述显示区和所述过渡区的所述第一隔离柱；其中，
位于所述第一隔离柱上的所述第二封装层的厚度，与所述第一隔离柱的厚度比为2:1～6:1。
可选地，所述第一隔离柱包括第一子隔离柱，所述第一子隔离柱与所述 围堰结构相邻，所述第二封装层在所述基底上的正投影与所述第一子隔离柱重叠的区域的平均厚度与所述第一子隔离柱的厚度比为2:1～6:1。
可选地，所述第二封装层在所述基底上的正投影与所述第一子隔离柱重叠的区域的厚度与所述第一子隔离柱的厚度比为6:1。
可选地，所述第二封装层从所述显示区到所述过渡区的厚度逐渐减小。
可选地，所述第一子隔离柱包括：叠层设置的第一子隔离层、第二子隔离层、第三子隔离层；
所述第一子隔离层和所述第三子隔离层在所述基底上的正投影重合，所述第二子隔离层在所述基底上的正投影落在所述第一子隔离层在所述基底上的正投影内。
可选地，所述第一子隔离层和所述第三子隔离层的厚度为0.04μm-0.08μm；所述第二子隔离层的厚度为0.4μm-0.6μm。
可选地，所述第一子隔离层和所述第三子隔离层的材料包括钛，所述第二隔离柱的材料包括铝。
可选地，在所述第二子隔离层靠近所述第三子隔离层的表面附着有颗粒结构。
可选地，所述第三子隔离层相对于所述基底所在平面上翘。
可选地，所述第一子隔离柱的侧边设置有凹槽。
可选地，所述显示基板还包括设置在所述基底上的驱动电路层；所述驱动电路层至少包括驱动晶体管，所述驱动晶体管的漏极与所述有机电致发光二极管的第一极连接；所述驱动晶体管的源极和漏极与所述隔离柱同层设置，且材料相同。
可选地，所述驱动晶体管的源极和漏极与所述有机电致发光二极管的第一极所在层之间设置有平坦化层；所述驱动晶体管的漏极通过贯穿所述平坦化层的过孔与所述有机电致发光二极管的第一极连接。
可选地，所述驱动晶体管的源极和漏极与所述有机电致发光二极管的第一极所在层之间依次设置有钝化层、转接电极、第一子平坦化层、第二子平坦化层；所述转接电极通过贯穿所述钝化层和所述第一子平坦化层的过孔与所述驱动晶体管的漏极连接，所述有机电致发光二极管的第一极通过贯穿所述第二子平坦化层的过孔与所述转接电极连接。
可选地，所述过渡区设置有多圈围堰结构，且所述多圈围堰结构相邻设置；所述多圈围堰结构中至少靠近开孔区的围堰结构的下方设置有辅助结构，以使在两相邻的所述围堰结构中靠近开孔区的一者在背离所述基底的方向上突出于另一者；所述辅助结构与所述平坦化层同层设置，且材料相同。
可选地，所述显示基板还包括位于的驱动电路层；所述驱动电路层至少包括驱动晶体管和层间介质层；所述驱动晶体管的有源层设置所述基底靠近所述有机电致发光二极管的一侧，第一栅绝缘层所述有源层，栅极设置所述第一栅绝缘层背离所述有源层的一侧，第二栅绝缘层覆盖所述栅极和所述第一栅绝缘层，所述层间介质层覆盖所述第二栅绝缘层；所述驱动晶体管的源极和漏极形成在所述层间介质层背离所述基底的一侧；所述第一隔离柱包括与围堰结构相邻的第一子隔离柱，以及位于所述第一子隔离柱靠近所述显示区一侧的第二子隔离柱；
在所述第一子隔离柱与第二子隔离柱之间设置有第一开槽，在所述第一子隔离柱与所述围堰结构之间设置有第二开槽；所述第一开槽和所述第二开槽贯穿所述层间介质层、所述第一栅绝缘层、所述第二栅绝缘层中的至少一层。
可选地，所述第一封装层的厚度为1μm-2μm；所述第二封装层的厚度为10μm-15μm；所述第三封装层的厚度为0.5μm-1μm。
第二方面，本公开实施例提供一种显示基板的制备方法，所述显示基板具有开孔区、环绕所述开孔区的过渡区，以及环绕所述过渡区的显示区；其中，所述显示基板的制备方法包括：
在基底上形成隔离柱、围堰结构；所述隔离柱和所述围堰结构均位于所述过渡区且环绕所述开孔区的；其中，形成所述隔离柱包括形成第一隔离柱，所述第一隔离柱位于所述围堰结构靠近所述显示区的一侧；
在所述隔离柱所在层背离所述基底的一侧依次形成有机电致发光二极管、第一封装层、第二封装层、第三封装层，所述有机电致发光二极管位于所述显示区，所述第一封装层和所述第三封装层在所述基底上的正投影至少覆盖所述显示区和所述过渡区；所述第二封装层在所述基底上的正投影覆盖所述显示区和所述过渡区的所述第一隔离柱；其中，
位于所述第一隔离柱上的所述第二封装层的厚度，与所述第一隔离柱的厚度比为2:1～6:1。
可选地，所述第一隔离柱包括第一子隔离柱，所述第一子隔离柱与所述围堰结构相邻，所述第二封装层在所述基底上的正投影与所述第一子隔离柱重叠的区域的平均厚度与所述第一子隔离柱的厚度比为2:1～6:1。
可选地，所述制备方法还包括：所述隔离柱靠近所述基底上的一侧形成驱动电路层；所述驱动电路层至少包括驱动晶体管；
所述驱动晶体管的源极和漏极与所述隔离柱采用一次构图工艺形成。
可选地，在形成所述有机电致发光二极管的第一极和发光层之间还包括形成像素限定层，所述像素限定层具有容纳所述发光层的容纳部；所述围堰结构与所述像素限定层采用一次构图工艺形成。
可选地，所述过渡区设置有多圈围堰结构，且所述多圈围堰结构相邻设置；所述多圈围堰结构中至少靠近开孔区的所述围堰结构的形成有辅助结构，以使在两相邻的所述围堰结构中靠近开孔区的一者在背离所述基底的方向上突出于另一者；在所述驱动晶体管的源极和漏极所在层与有机电致发光二极管的第一极所在层之间形成有平坦化层，所述第一极通过贯穿所述平坦化层的过孔与所述驱动晶体管的漏极连接；所述辅助结构与所述平坦化层采用一次构图工艺形成。
第三方面，本公开实施例提供一种显示面板，其包括上述的显示基板。
附图说明
图1为本公开实施例的显示基板区域分布区。
图2为图1的显示基板中A-A的一种截面图。
图3为图1的显示基板中A-A的另一种截面图。
图4为图1的显示基板中B-B的一种截面图。
图5为本公开实施例的显示基板的一种隔离柱结构示意图。
图6为本公开实施例的显示基板的另一种隔离柱结构示意图。
图7为本公开实施例的显示基板的基底的结构示意图。
图8为本公开实施例的一种显示基板的制备方法的流程图。
图9为本公开实施例的另一种显示基板的制备方法的流程图。
图10为步骤S11的具体流程图。
具体实施方式
为使本领域技术人员更好地理解本公开的技术方案，下面结合附图和具体实施方式对本公开作进一步详细描述。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
第一方面，如图1-4所示，本公开实施例提供一种该显示基板划分为显示区Q1、过渡区Q2、开孔区Q3；其中，过渡区Q2环绕过孔区Q3、显示区Q1环绕过渡区Q2。显示基板包括基底101、设置在基底101上位于显示区Q1的像素结构，像素结构至少包括驱动电路层和发光器件，驱动电路层通常至少包括开关晶体管、驱动晶体管、存储电容(也即现有的2T1C的像素驱动电路)，发光器件包括但不限于有机电致发光二极管(Organic Light Emitting Diode；OLED)1d。显示基板还包括位于过渡区Q2的隔离柱120；在隔离柱120所在层背离基底101的一侧形成有平坦化层117，并在显示区Q1对应驱动电路层中驱动晶体管的漏极111的位置刻蚀过孔，以使形成在平坦化层117之上的有机电致发光二极管1d的第一极112可以通过过孔与驱动晶体管的漏极111连接。由于隔离柱120形成在了过渡区Q2，故有机电致发光二极管的发光层114和第二极115在显示区Q1和过孔区Q3之间的过渡区Q2断开，以避免过孔区中的过孔的存在，导致水、氧等侵蚀显示区中的有机电致发光二极管1d，而引起显示不良；当然，显示基板还包括依次设置在有机电致发光二极管1d的第二极115之上的第一封装层118a、第二封装层118b、第三封装层118c。显示基板还包括位于开孔区Q3，贯穿显示基板的通孔。
需要说明的是，本公开实施例的显示基板中开孔区Q3在开孔处理后形成通孔，用于组装摄像头、传感器、HOME键、听筒或扬声器等器件。对于本公开实施例的显示基板，开孔区Q3未进行开孔处理，在组装摄像头等器件前，再进行开口处理即可。此外，本公开实施例的显示基板，在开孔区Q3已进行了开孔处理，在此情况下，该显示基板可直接拿来进行后续组装。
以下分别对显示区Q1、过渡区Q2、过孔区Q3的各个区域的结构进行详细说明。
在一些实施例中，如图2所示，驱动电路层可以形成在缓冲层102上。其中，其中，此驱动电路层可以包括位于显示区Q1和过渡区Q2的层间介质层103，此层间介质层103采用无机材料制作而成，例如：氧化硅、氮化 硅等无机材料，以达到阻水氧和阻隔碱性离子的效果；驱动电路层还包括位于显示区的驱动晶体管、存储电容，当然还包括开关晶体管等开关元件，其结构与驱动晶体管的结构相同，且可以在一次工艺中制备，故在此不再一一说明。
如图3所示，驱动晶体管可为顶栅型，此驱动晶体管可包括有源层104、第一栅绝缘层105、栅极106、第二栅绝缘层108、层间介质层103、源极110、漏极111。具体地，有源层104可形成在缓冲层102上，第一栅绝缘层105覆盖缓冲层102及有源层104，栅极106形成在第一栅绝缘层105背离有源层104的一侧，第二栅绝缘层108覆盖栅极106和第一栅绝缘层105，层间介质层103覆盖第二栅绝缘层108，源极110和漏极111形成在层间介质层103背离衬底基板的一侧并分别位于栅极106的相对两侧，该源极110和漏极111可分别通过过孔(例如：金属过孔)分别与有源层104的相对两侧的源极接触区和漏极接触区接触。应当理解的是，此驱动晶体管也可为底栅型。
如图3所示，电容结构可包括第一极板130和第二极板131，此第一极板130与栅极103同层设置，第二极板131位于第二栅绝缘层105与层间介质层103之间，并与第一极板130相对设置。
举例而言，栅极103和第一极板130、第二极板131的材料可以包括金属材料或者合金材料，例如包括钼、铝及钛等。源极110和漏极111可以包括金属材料或者合金材料，例如由钼、铝及钛等形成的金属单层或多层结构，例如，该多层结构为多金属层叠层，例如钛、铝、钛三层金属叠层(Al/Ti/Al)等。
如图2所示，在驱动晶体管背离基底101的一侧设置有平坦化层117，平坦化层117位于显示区Q1。其中，平坦化层117通常采用有机材料制作而成，例如：光刻胶、丙烯酸基聚合物、硅基聚合物等材料。
如图2所示，有机电致发光二极管1d位于显示区Q1，该有机电致发光二极管1d可以包括依次形成在平坦化层117上的有机电致发光二极管1d的第一极112和像素限定层113，应当理解的是，该有机电致发光二极管1d还 可包括发光层114和第二极115。
其中，有机电致发光二极管1d的第一极112可通过贯穿平坦化层117的过孔与驱动晶体管的漏极111电性连接，该第一极112可为阳极，此阳极可为ITO(氧化铟锡)、氧化铟锌(IZO)、氧化锌(ZnO)等材料制作而成；像素限定层113可覆盖平坦化层117，此像素限定层113可为有机材料制作而成，例如：光刻胶等有机材料，且像素限定层113可具有露出第一电极112的容纳部；发光层位于容纳部内并形成在第一极112上，该发光层114可包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光等；并且，根据实际不同需要，在不同的示例中，发光层114还可以进一步包括电子注入层、电子传输层、空穴注入层、空穴传输层等功能层；第二极115覆盖发光层，且该第二极115的极性与第一极112的极性相反；此第二极115可为阴极，此阴极可为锂(Li)、铝(Al)、镁(Mg)、银(Ag)等金属材料制作而成。
需要说明的是，如图2所示，第一极112、发光层和第二极115可构成一个有机电致发光二极管1d。其中，显示区Q1中包括呈阵列排布的有机电致发光二极管1d。此外，还需说明的是，各有机电致发光二极管1d的第一极112相互独立，各有机电致发光二极管1d的第二极115可整面连接；即第二电极115为设置在显示基板10上的整面结构，为用于多个有机电致发光二极管1d的公共电极。
在一些实施例中，如图3所示，有机电致发光二极管1d的第一极112还可通过转接电极133与漏极111电性连接。当第一极112通过转接电极133与漏极111电性连接时，该平坦化部117可为双层结构，具体可包括依次形成的第一子平坦化(PLN1)层117a及第二子平坦化(PLN2)层117b，此外，在第一子平坦化层117a与层间介质层103之间还可形成钝化(PVX)层116，该钝化层116可由氧化硅、氮化硅或者氮氧化硅等材料形成；该钝化层116覆盖源极110、漏极111；而转接电极133形成在第一子平坦化层117a与第二子平坦化层117b之间，并依次通过第一子平坦化层117a及钝化层116上 的过孔(例如金属过孔)与漏极111电性连接；而第一极112可通过第二子平坦化层117b上的过孔(例如金属过孔)与转接电极133电性连接，以此完成有机电致发光二极管1d的第一极112与驱动晶体管的漏极111的连接。在一些实施例中，如图2和3所示，像素限定层113背离层间介质层103的一侧还可设置支撑部132，该支撑部132可起到支撑保护膜层(图中未示出)的作用，以避免保护膜层与第一极112或其他走线接触而导致第一极112或其他走线容易损坏的情况。需要说明的是，此保护膜层主要出现在半成品转移的过程中，以避免转移过程中半成品出现损坏的情况，具体地：在将制作完支撑部132的基板转移到蒸镀产线的过程中，可覆盖一层保护膜层，当需要进行发光材料的蒸镀时，而将保护膜层移除。
其中，支撑部132的材料可与像素限定层113的材料相同，且支撑部132与像素限定层113可采用同一次构图工艺形成，但不限于此，支撑部132的材料也可与像素限定层113的材料不同，且支撑部132与像素限定层113也可采用不同构图工艺形成。
在一些实施例中，如图4所示，隔离柱120位于过渡区Q2、环绕开孔区Q3设置，且设置在钝化层116背离基底101的一侧。有机电致发光二极管1d的发光层114和第二极115在过渡区Q2的隔离柱120与隔离柱120之间断开，以避免过孔区Q3中的过孔的存在，导致水、氧等侵蚀显示区中的有机电致发光二极管1d，而引起显示不良。
在一些实施例中，图4所示的结构中也可以没有钝化层116和有机发光二极管1d的第二极115。
如图4所示，在过渡区Q4还设置有围堰结构150，在通过封装层118对此显示基板进行封装时，该围堰结构150能够对封装层118中的有机封装薄膜层材料的流动形成限制，避免封装层118中的有机封装薄膜层材料流动至开孔区Q3引起封装失效的问题，也就是说，该围堰结构150可与封装层118配合，以有效阻隔水、氧通过开孔区Q3进入到显示区Q1，从而可避免显示区Q1的有机电致发光二极管1d失效而导致显示效果差的情况，延长了 产品的使用寿命。
详细说明，如图3至5所示，显示基板10的封装层118可包括依次层叠设置的第一封装层118a、第二封装层118b和第三封装层118c。此第一封装层118a和第三封装层118c封装有机电致发光二极管1d、隔离柱120和围堰结构150，第二封装层118b封装有机电致发光二极管1d，并在围堰结构150靠近显示区Q1的一侧阻断。第一封装层118a、第三封装118c层用于防止水、氧从显示功能的显示侧及开孔区Q3进入到显示区Q1的发光层114中；该第一封装层118a、第三封装层118c可采用氮化硅、氧化硅等无机材料制作而成。第二封装层118b用于实现平坦化作用，以便于第三封装薄膜层118c层的制作，此第二封装层118b可采用丙烯酸基聚合物、硅基聚合物等材料制作而成。
其中，此第一封装层118a和第三封装层118c可采用化学气相沉积工艺制作而成，但不限于此，也可采用物理气相沉积工艺等；而第二封装层118b采用喷墨打印工艺制作，但不限于此，也可采用喷涂工艺等。在制作第二封装层118b的过程中，由于第二封装层118b具有一定的流动性，因此，通过设置围堰结构150可对第二封装层118b材料的流动形成限制，避免第二封装层118b材料流动至开孔区Q3引起封装失效的问题。
在本公开实施例中，围堰结构150与像素限定层113同层设置，即：通过一次构图工艺即可同时形成围堰结构150和像素限定层113，可减少加工步骤及掩膜板的使用，从而可降低成本。此外，应当理解的是，该围堰结构与像素限定层113应相互断开。当然，围堰结构150也可以为由堆叠的绝缘材料形成的结构，例如可以为采用与像素限定层113同层设置第一子围堰层和与支撑部132同层设置的第二子围堰层堆叠形成的结构。
在一些实施例中，如图4所示，隔离柱包括位于围堰结构靠近显示区Q1一侧的第一隔离柱120；其中，第一隔离柱120包括与围堰结构150相邻设置的第一子隔离柱120a。对于第一子隔离柱120a的数量可以是一个，也可以是多个，在本公开实施例中，以第一子隔离柱120a的数量为一个为例。 当然，第一隔离柱120还可以包括位于第一子隔离柱120a靠近显示区Q1的第二子隔离柱120b，第二子隔离柱120b的结构可以与第一子隔离柱120a相同，也可以不同，在本公开实施例中以第二子隔离柱120b与第一子隔离柱120a相同为例进行说明，其中，第二子隔离柱120b的数量也可为一个，也可以为多个，在本公开实施例中第二子隔离柱120b的数量为一个为例。
在一些实施例中，隔离柱还可以包括位于围堰结构靠近过渡区Q2一侧的第二隔离柱121，其中，第二隔离柱121的数量可以为一个也可以为多个，其结构可以与第一子隔离柱120a和第二子隔离柱120b结构一致，当然二者的结构不一致也可以，在本公开实施例中以第二隔离柱121与第一子隔离柱120a和第二子隔离柱120b结构一致为例。图4中示意出隔离柱包括两个第二隔离柱121，但并不构成对本公开实施例的限制。
在一些实施例中，如图5和6所示，提供一种第一子隔离柱120a的具体结构，该种结构的第一子隔离柱120a用于保证有机电致发光二极管1d的发光层114在过渡区Q2的第一隔离柱120a结构的边缘完全断开，该第一子隔离柱120a可以包括叠层设置的第一子隔离层120a1、第二子隔离层120a2、第三子隔离层120a3三层结构，其中，第一子隔离层120a1和第三子隔离层120a3在基底110上的投影可以是重合的，第二子隔离层120a2在基底上的投影落在第一子隔离层120a1在基底101上的投影内；也即，第一子隔离柱120a垂直于基底101方向的截面具有凹槽(如图5和6所示，第二子隔离层120a2的侧面，相较于第一子隔离层120a1和第三子隔离层120a2内陷，也即形成隔离柱的侧面凹槽)。隔离柱120的第一子隔离层120a1和第三子隔离层120a3的材料采用钛Ti，第二子隔离层120a2的材料采用铝Al。在第二子隔离层120a2形成过程中，金属Al材料和刻蚀液里的Ag离子在湿刻时发生置换反应，形成1～5um左右的大小的Ag颗粒，这种颗粒具有很强粘附性，不易清除，最终成为导电的颗粒，表现为暗点。而在刻蚀形成第二子隔离层120a2的结构时，可能会将刻蚀液中银Ag离子置换出来，以使第二子隔离层120a2的上表面附着一层银颗粒(如图5所示)，同时，由于工艺的原因也可 能导致所形成的第一隔离柱120a中的第三子隔离层120a3的出现上翘等问题(如图6所示)。这样一来，将会导致在形成隔离柱上方的第三封装层118c对应隔离柱的位置出现断裂的风险，而一旦第三封装层118c断裂将会导致显示基板的封装失效。
为解决上述技术问题，本公开实施例提供一种显示基板，该显示基板中的位于围堰结构150靠近显示区Q1一侧，且与围堰结构150相邻的第一隔离柱120背离基底101一侧的第二封装层118b的厚度，与第一隔离柱120的厚度比包括2:1～6:1，以使形成的第二封装层118b的背离基底101的表面大致平坦，从而避免形成在第二封装层118b背离基底101表面的第三封装层118c发生断裂，而出现显示基板封装失效的问题。
在一些实施例中，如图4所示，第二封装层118b在基底101上的正投影与第一子隔离柱120a重叠的区域的平均厚度D1与所述第一子隔离柱120a的厚度D2比为2:1～6:1。例如当D1：D2为2：1时可以使形成第二封装层118b的背离基底101的表面大致平坦，当D1：D2为6：1时可以使的第二封装层118b的厚度以避免形成在第二封装层118b之上的第三封装层118c发生断裂的同时，还可能避免第二封装层118b过厚，影响显示基板的轻薄化。之所以如此是设置是因为，对于第二封装层118b而言，由于其材料的流动性，第二封装层118b越是靠近围堰结构150的厚度越薄，也即，第二封装层118b从显示区Q1到过渡区Q2的厚度逐渐减小，同时第一子隔离柱与围堰结构150相邻设置，一旦第二封装层118b在基底101上的正投影与第一子隔离柱120a重叠的区域的平均厚度D1与所述第一子隔离柱120a的厚度D2比为2:1～6:1，那么过渡区Q2其余位置的厚度第二封装层118b与所述第一子隔离柱120a的厚度D2比一定大于2:1～6:1，因此可以完全避免形成在第二封装层118b背离基底101表面的第三封装层118c发生断裂，而出现显示基板封装失效的问题。在一些实施例中，第二封装层118b在基底101上的正投影与第一子隔离柱120a重叠的区域的平均厚度D1与所述第一子隔离柱120a的厚度D2比为6:1。这样一来，通过合理设计第二封装层118b的 厚度以避免形成在第二封装层118b之上的第三封装层118c发生断裂的同时，还可能避免第二封装层118b过厚，影响显示基板的轻薄化。当然，根据产品需求采用相应厚度比例的第二封装层118b和第一子隔离柱120a，例如：第二封装层6的厚度D1与第一子隔离柱120a的厚度D2比为2:1、3:1、4:1等。
在一些实施例中，隔离柱的厚度包括但不限于0.4μm-0.7μm。当然，也可以根据有机电致发光二极管1d的发光层114的厚度选用不同厚度的隔离柱120，隔离柱的厚度只要满足有机电致发光二极管1d的发光层114在过渡区Q2可以断开即可。
在一些实施例中，该隔离柱可与驱动晶体管的源极110、漏极111同层设置，即：隔离柱与源极110、漏极111通过同一构图工艺形成，这样设计还可减少加工步骤及掩膜板的使用，从而可降低成本。此外，应当理解的是，该隔离柱可与驱动晶体管的源极110、漏极111应相互断开，以避免隔离柱124在显示时通电的情况。
由于前述提到隔离柱可与显示区中薄膜晶体管的源极110和漏极111同层设置，因此，该隔离柱的结构、材料可与源极110和漏极111的结构和材料相同，例如，在源极110和漏极111为三层金属结构时，该隔离柱也可为三层金属结构。
具体地，如图5和6所示，隔离柱中的第一子隔离柱120a可包括依次层叠在层间介质层103上的第一子隔离层120a1、第二子隔离层120a2及第三子隔离层120a3，第二子隔离层120a2在层间介质层103上的正投影的外边界位于第一子隔离层120a1、第三子隔离层120a3在层间介质层103上的正投影的外边界内侧，以在隔离柱120的侧壁形成凹槽，使得隔离柱120的纵截面成“工字形”结构。
其中，第一子隔离层120a1与第三子隔离层120a3的材料可为钛层，即：第一子隔离层120a1和第三子隔离层120a3可采用钛(Ti)材料制作而成，第二子隔离层120a2，即：第二子隔离层120a2可采用铝(Al)材料制作而 成，这样可保证第二子隔离层120a2在进行侧蚀时，第一子隔离层120a1和第三子隔离层120a3不会受到刻蚀的影响。但不限于此，第一子隔离层120a1、第二子隔离层120a2及第三子隔离层120a3也可采用其它材料制作而成，例如：钼、铝等金属材料或者合金材料，只要能实现上述技术效果即可，本公开对此不做限制。
在一些实施例中，当第一子隔离柱120a包括第一子隔离层120a1、第二子隔离层120a2、第三子隔离层120a3时，第一子隔离层120a1和第三子隔离层120a3的厚度包括但不限于0.04μm-0.08μm；第二子隔离层120a2的厚度包括但不限于0.4μm-0.6μm。当然，也可以根据有机电致发光二极管1d的发光层114的厚度选用不同厚度的第一子隔离层120a1、第二子隔离层120a2、第三子隔离层120a3，第一子隔离层120a1、第二子隔离层120a2、第三子隔离层120a3的总厚度只要满足有机电致发光二极管1d的发光层114在过渡区Q2的第一子隔离柱120a的边缘可以断开即可。
在一些实施例中，如图4所示，驱动电路层具有位于过渡区Q2的第一开槽125和第二开槽126；第一开槽125位于第一子隔离柱120a与第二子隔离柱120b之间，第一开槽125环绕第一子隔离柱120a设置；第二开槽126位于第一子隔离柱120a与围堰结构150，第二开槽126环绕围堰结构设置，这样设计可增大发光材料在隔离柱120的侧面断开的概率。
其中，第一开槽125和第二开槽126可贯穿位于过渡区Q2的介质层103、第一栅绝缘层105、第二栅绝缘层108中的至少一层，例如，第一开槽125和第二开槽126可贯穿过渡区Q2的介质层103、第一栅绝缘层105、第二栅绝缘层108、钝化层116，即：开槽可延伸至缓冲层102。
如图4所示，第一开槽125和第二开槽126可贯穿整个驱动电路层，以进一步增大发光材料或阴极材料在隔离柱124的侧面断开的概率；此外，在显示基板10具有柔性并进行弯曲时，这样设计还可缓解驱动电路层位于显示区10a的部分所受到的应力，保证驱动电路层中各元件的连接可靠性。
需要说明的是，本公开的实施例中，还可以在第二隔离柱121和第二隔 离柱121之间设置第三开槽127，第三开槽127与第一开槽125和第二开槽126的结构可以相同；在开孔区Q3为圆形时，第一开槽125、第二开槽126、隔离柱120在衬底基板上的正投影也可为圆环；在开孔区Q3为矩形时，第一开槽125、第二开槽126、第一子隔离柱120a、第二子隔离柱120b、第二隔离柱121在基底101上的正投影也可为矩形环；但不限于此开孔区Q3还可为其他规则或不规则形状，第一开槽125、第二开槽126、第三开槽127、第一子隔离柱120a、第二子隔离柱120b、第二隔离柱121可与之相适配。
在一些实施例中，第一封装层118a的厚度范围包括但不限于1μm-2μm，第二封装层118b的厚度范围包括但不限于10μm-15μm，第三封装层118c的厚度范围包括但不限于0.5μm-1μm。
在一些实施例中，围堰结构150为多圈，且多圈围堰结构150相邻设置；多圈围堰结构150中至少靠近开孔区Q3的围堰结构150的下方设置有辅助结构140，以使在两相邻的围堰结构150中靠近开孔区Q3的一者在背离基底101的方向上突出于另一者。
具体的，如图4所示，以显示基板包括两圈围堰结构150为例，这两圈围堰结构150设置在由显示区Q1指向开孔区方向上的第二圈隔离柱120与第三圈隔离柱120之间，其中靠近过孔区Q3的围堰结构150靠近基底101的一侧设置有辅助结构130，以使该围堰结构120在在背离基底101的方向上突出于远离开孔区Q3的围堰结构150。之所以如此设置，在沿显示区Q1指向开孔区Q3方向上，即使第一个围堰结构150不能够将第二封装层118b材料阻挡，也可以通过第二个围堰结构150将第二封装层118b材料阻挡。
在一些实施例中，辅助结构130可以与平坦化层117同层设置且材料相同。这样一来，可以在形成平坦化层117的同时形成辅助结构130，从而可以简化工艺步骤，提高生产效率。当然，辅助结构130也可以与介质层103、第一栅绝缘层105、第二栅绝缘层108中的至少一层中的至少一层同层设置，且材料相同。
在一些实施例中，如图8所示，基底101可为柔性基板，以提高显示基 板的柔性，使得显示基板1能够具有可弯曲、可弯折等性能，以便于扩大显示基板的适用范围；但不限于此，该基底也可设置为刚性，具体该衬底基板的性能可根据产品的实际需求而定。
此外，该基底101可为单层结构，也可为多层结构。例如，如图8所示，该衬底基板可包括依次层叠设置的聚酰亚胺层101a、缓冲层101b、聚酰亚胺层101c，其中，缓冲层101b可为氮化硅、氧化硅等材料制作而成，以达到阻水氧和阻隔碱性离子的效果；需要说明的是，该衬底基板的结构不限于此，可根据实际需求而定。
相应的，本公开实施例提供一种显示基板的制备方法，该方法可用于制备上述的显示基板。显示基板具有显示区Q1、过渡区Q2、开孔区Q3；如图9所示，该方法包括：
S01、在基底101上形成驱动电路层、有机电致发光二极管1d、隔离柱和围堰结构150。其中，隔离柱包括位于围堰结构150靠近显示区Q1一侧的第一隔离柱120，用于使得有机发光层在显示区Q1和开孔区Q3之间的过渡区Q2断开，以避免开孔区Q3的通孔处的水、氧等侵蚀显示区Q1的有机电致发光二极管1d，而影响有机电致发光二极管1d的性能。
S02、在有机电致发光二极管1d的第二极115所在层上方，依次形成第一封装层118a、第二封装层118b、第三封装层118c，以对有机电致发光二极管1d进行密封。第一隔离柱120背离基底101一侧的第二封装层118b的厚度，与第一隔离柱120的厚度比包括2:1～6:1，以使形成的第二封装层118b的背离基底101的表面大致平坦，从而避免形成在第二封装层118b背离基底表面的第三封装层118c发生断裂，而出现显示基板封装失效的问题。
在一些实施例中，如图4所示，第二封装层118b在基底101上的正投影与第一子隔离柱120a重叠的区域的平均厚度D1与所述第一子隔离柱120a的厚度D2比为2:1～6:1。之所以如此是设置是因为，对于第二封装层118b而言，由于其材料的流动性，第二封装层118b越是靠近围堰结构150的厚度越薄，也即，第二封装层118b从显示区Q1到过渡区Q2的厚度逐渐减小， 同时第一子隔离柱与围堰结构150相邻设置，一旦第二封装层118b在基底101上的正投影与第一子隔离柱120a重叠的区域的平均厚度D1与所述第一子隔离柱120a的厚度D2比为2:1～6:1，那么过渡区Q2其余位置的厚度第二封装层118b与所述第一子隔离柱120a的厚度D2比一定大于2:1～6:1，因此可以完全避免形成在第二封装层118b背离基底101表面的第三封装层118c发生断裂，而出现显示基板封装失效的问题。
以下为了清楚的理解本公开实施例的显示基板的制备方法，给出一种显示基板的制备方法的示例，但该示例并不够呈对本公开保护范围的限制。如图10所示，该方法具体包括如下步骤：
S11、提供一基底101，在基底101上形成像素结构中的驱动电路层、有机电致发光二极管1d和隔离柱120。
具体的，如图11所示，步骤S11可以包括如下步骤：
S111、在基底101上形成位于显示区Q1和过渡区Q2的缓冲层102；以及形成缓冲层102之，且位于显示区Q1的驱动电路层(开关晶体管、驱动晶体管、存储电容等)的各层结构和位于过渡区Q2的隔离柱，例如驱动晶体管的有源层104、第一栅绝缘层105、栅极106、第二栅绝缘层108、层间介质层103、源极110、漏极111。具体地，有源层104可形成在缓冲层102上，第一栅绝缘层105覆盖缓冲层102及有源层104，栅极106形成在第一栅绝缘层105背离有源层104的一侧，第二栅绝缘层108覆盖栅极106和第一栅绝缘层105，层间介质层103覆盖第二栅绝缘层108，源极110和漏极111形成在层间介质层103背离衬底基板的一侧并分别位于栅极106的相对两侧，该源极110和漏极111可分别通过过孔(例如：金属过孔)分别与有源层104的相对两侧的源极接触区和漏极接触区接触。应当理解的是，此驱动晶体管也可为底栅型。如图3所示，电容结构可包括第一极板130和第二极板131，此第一极板130与栅极103同层设置，第二极板131位于第二栅绝缘层105与层间介质层103之间，并与第一极板130相对设置。
其中，如图4所示，隔离柱包括第一隔离柱120和第二隔离柱121；其 中，第一隔离柱120包括第一子隔离柱120a和第二子隔离柱120b。在一些实施例中，第一子隔离柱120a、第二子隔离柱120b和第二隔离柱121可以与驱动晶体管的源极110和漏极111可以在一次构图工艺中形成。具体的，源极110和漏极111为三层金属结构时，第一子隔离柱120a、第二子隔离柱120b和第二隔离柱121也可为三层金属结构。也即，第一子隔离柱120a、第二子隔离柱120b和第二隔离柱121均包括由背离基底101依次叠层设置的第一子隔离层120a1、第二子隔离层120a2及第三子隔离层120a3。
其中，形成三层结构的第一子隔离柱120a可以包括如下步骤：
通过包括但不限于磁控溅射、物理气相沉积等工艺，在层间之上依次形成第一子隔离材料层、通过湿法刻蚀形成第一子隔离层120a1。
通过包括但不限于磁控溅射、物理气相沉积等工艺，在层间之上依次形成第二子隔离材料层、通过湿法刻蚀形成第二子隔离层120a2。
通过包括但不限于磁控溅射、物理气相沉积等工艺，在层间之上依次形成第三子隔离材料层、通过湿法刻蚀形成第三子隔离层120a3。
第一子隔离层120a1和第三子隔离层120a3在基底101上的投影重合，第二隔离柱120a2在基底101上的投影落在第一子隔离层120a1在基底101上的投影内，也即第一子隔离柱120a垂直于基底101方向的截面具有凹槽。其中，第一子隔离层120a1和第三子隔离层120a3的材料采用钛Ti，第二子隔离层120a2的材料采用铝Al。当然，隔离柱2不局限于三层结构的隔离柱120，隔离柱120也可以是四层结构，甚至更多层结构。其中，隔离柱120包括上述的第一子隔离层120a1、第二子隔离层120a2、第三子隔离层120a3三层结构时，其中，由于刻蚀工艺的原因，第二子隔离层120a2靠近第三子隔离层120a3的的表面上附着有颗粒结构，具体可以是在刻蚀形成第一子隔离柱120a的结构时，刻蚀液中所置换出的银离子；当然，由于工艺的原因第三子隔离层120a3相对于基底101所在平面上翘(也即朝向背离基底101的方向翘起)。
S112、在形成隔离柱、驱动晶体管的源极110和漏极111的基底101上，形成位于显示区Q1的平坦化层117和位于过渡区的辅助结构140，并在显示区Q1的驱动电路层中的驱动晶体管的漏极111对应的位置形成贯穿平坦化层116和层间绝缘层117的过孔。
在一些实施例中，在步骤S112中所形成的平坦化层117和辅助结构140同层设置、且材料形同，也即二者采用一次构图工艺形成。
S113、在形成平坦化层117和辅助结构140的基底101上，形成位于有机电致发光二极管1d的第一极112，且有机电致发光二极管1的第一极112通过步骤S112中所形成过孔与驱动晶体管的漏极111连接。
S114、在形成有机电致发光二极管1d的第一极112的基底101上，形成位于显示区Q1的像素限定层113和位于过渡区Q2的围堰结构150；其中，像素限定层113在与有机电致发光二极管1d的第一极112对应的位置形成有容纳部，围堰结构150靠近过孔区Q3的一者设置在辅助结构140之上。
在一些实施例中，在步骤S114中形成的像素限定层113和围堰结构150同层设置、且材料形同，也即二者采用一次构图工艺形成。
S115、在形成像素限定层113和围堰结构150的基底101上，通过包括但不限于喷墨打印的方式形成有机发光二极管1d的发光层114，由于在过渡区Q2形成隔离柱120，故形成在隔离柱120之上的有机电致发光器件1d的发光层断开。
S116、在形成有机发光二极管1d的发光层114的基底101，通过包括但不限于蒸镀工艺形成有机发光二极管1d的第二极115。
至此完成了驱动电路层、有机电致发光二极管1d、隔离柱120的制备。
在此需要说明的是，如图3所示，在步骤S112中可以先形成钝化116层，在钝化层116对应驱动晶体管漏极111的位置形成过孔，在钝化层116背离基底101的一侧形成转接电极133，以使转接电极133通过贯穿钝化层116的过孔与驱动晶体管的漏极111连接，之后依次形成的第一子平坦化层 117a及第二子平坦化层117b，并在第一子平坦化层117a及第二子平坦化层117b对应转接电极133的位置形成过孔。之后再执行步骤S113，以使步骤S113中形成的有机电致发光二极管1d的第一极112通过贯穿第一子平坦化层117a及第二子平坦化层117b的过孔与转接电极133连接。
S12、在有机电致发光二极管1d的第二极115的基底101上，形成第一封装层118a。
其中，第一封装层118a上的材料可以为SiN x、SiON、SiO x等，第一封装层118a上可采用化学气相沉积、物理气相沉积、原子力沉积等方式形成。
S13、在形成有第一封装层118a的基底101上，形成位于开孔区Q3的支撑结构(图中未示)。
具体地，可采用化学气相沉积、物理气相沉积、原子力沉积、喷墨打印、喷涂等方式在开孔区上形成支撑结构。支撑结构的材料可为为聚酰胺、聚酯、聚碳酸酯中的至少一种。采用这些固化速率快的材料，能够直接避免材料流淌
S14、在形成有支撑结构的基底101上，形成位于围堰结构150靠近显示区Q1一侧的第二封装层118b。
其中，第二封装层118b在基底101上的正投影位于部分过渡区Q3与显示区Q1内。第二封装层118b的材料可包括丙烯酸基聚合物、硅基聚合物等。第二封装层118b可采用喷墨打印、喷涂等方式形成于第一封装层118a上。
S15、在形成有第二封装层118b的基底101上，形成第三封装层118c。
其中，第三封装层118c在基底101上的正投影位于过渡区Q2与显示区Q1内。其中，第三封装层7的材料可以为SiN x、SiCN、SiO 2等，第三封装层118c可采用化学气相沉积、物理气相沉积、原子力沉积等方式形成。
在此需要说明的是，步骤S12中所形成第一封装层118a与步骤S15中所形成的第三封装层118c为无机封装层，步骤S14中所形成第二封装层118b为有机封装层。
S16、在形成有第三封装层118c的基底101上，形成保护层(图中未示)，其中，支撑结构支撑保护层。
具体地，在第三封装层118c远离基底101的一侧形成保护层，支撑结构8支撑保护层。保护层被支撑结构顶起，避免了保护层在开孔区Q3与显示区Q1膜层落差过大，提高了保护层的平坦度，从而在撕掉保护层时，第三封装层118c不会被带起，避免了第三封装层118c从第二封装层118b上剥离，保证了封装效果，提高了显示面板的产品良率。
S17、剥离保护层。
具体地，在MDL工艺段中，需要先剥离保护层然后再贴POL，通过支撑结构，在剥离保护层时第三封装层118c不会被带起，避免了第三封装层118c从第二封装层118b上剥离。
S18、在与开孔区Q3对应的区域形成通孔。
具体地，剥离保护层后，在开孔区Q3形成通孔，从而实现屏幕上开孔的目的。在开孔区形成通孔时，由于支撑结构位于开孔区上，可通过同一次工艺将显示基板的开孔区对应区域与支撑结构同时去除。当然，也可通过两次工艺分别显示基板上开孔区与支撑结构去除，本公开实施例对此不做限制。
第二方面，本公开实施例还提供一种显示面板，该显示面板包括上述的显示基板。该显示面板例如可为手机、平板电脑、电子手表、运动手环、笔记本电脑等具有显示面板的电子设备。该显示装置具有的技术效果可参考上述对显示面板的技术效果的论述，在此不再赘述。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (22)

  1. 一种显示基板，其具有开孔区、环绕所述开孔区的过渡区，以及环绕所述过渡区的显示区；所述显示基板包括：
    基底，
    隔离柱、围堰结构，均设置在所述基底上，位于所述过渡区且环绕所述开孔区；其中，所述隔离柱包括第一隔离柱，所述第一隔离柱位于所述围堰结构靠近所述显示区的一侧；
    有机电致发光二极管、第一封装层、第二封装层、第三封装层，依次设置在所述基底上，所述有机电致发光二极管位于所述显示区，所述第一封装层和所述第三封装层在所述基底上的正投影至少覆盖所述显示区和所述过渡区；所述第二封装层在所述基底上的正投影覆盖所述显示区和所述过渡区的所述第一隔离柱；其中，
    位于所述第一隔离柱上的所述第二封装层的厚度，与所述第一隔离柱的厚度比为2:1～6:1。
  2. 根据权利要求1所述的显示基板，其中，所述第一隔离柱包括第一子隔离柱，所述第一子隔离柱与所述围堰结构相邻，所述第二封装层在所述基底上的正投影与所述第一子隔离柱重叠的区域的平均厚度与所述第一子隔离柱的厚度比为2:1～6:1。
  3. 根据权利要求2所示的显示基板，其中，所述第二封装层在所述基底上的正投影与所述第一子隔离柱重叠的区域的厚度与所述第一子隔离柱的厚度比为6:1。
  4. 根据权利要求1-3中任一项所述的显示基板，其中，所述第二封装层从所述显示区到所述过渡区的厚度逐渐减小。
  5. 根据权利要求2-4中任一项所述的显示基板，其中，所述第一子隔离柱包括：叠层设置的第一子隔离层、第二子隔离层、第三子隔离层；
    所述第一子隔离层和所述第三子隔离层在所述基底上的正投影重合，所 述第二子隔离层在所述基底上的正投影落在所述第一子隔离层在所述基底上的正投影内。
  6. 根据权利要求5所述的显示基板，其中，所述第一子隔离层和所述第三子隔离层的厚度为0.04μm-0.08μm；所述第二子隔离层的厚度为0.4μm-0.6μm。
  7. 根据权利要求5所述的显示基板，其中，所述第一子隔离层和所述第三子隔离层的材料包括钛，所述第二隔离柱的材料包括铝。
  8. 根据权利要求5所述的显示基板，其中，在所述第二子隔离层靠近所述第三子隔离层的表面附着有颗粒结构。
  9. 根据权利要求5所述的显示基板，其中，所述第三子隔离层相对于所述基底所在平面上翘。
  10. 根据权利要求2-4中任一项所述的显示基板，其中，所述第一子隔离柱的侧边设置有凹槽。
  11. 根据权利要求1所述的显示基板，其中，所述显示基板还包括设置在所述基底上的驱动电路层；所述驱动电路层至少包括驱动晶体管，所述驱动晶体管的漏极与所述有机电致发光二极管的第一极连接；所述驱动晶体管的源极和漏极与所述隔离柱同层设置，且材料相同。
  12. 根据权利要求11所述的显示基板，其中，所述驱动晶体管的源极和漏极与所述有机电致发光二极管的第一极所在层之间设置有平坦化层；所述驱动晶体管的漏极通过贯穿所述平坦化层的过孔与所述有机电致发光二极管的第一极连接。
  13. 根据权利要求11所述的显示基板，其中，所述驱动晶体管的源极和漏极与所述有机电致发光二极管的第一极所在层之间依次设置有钝化层、转接电极、第一子平坦化层、第二子平坦化层；所述转接电极通过贯穿所述钝化层和所述第一子平坦化层的过孔与所述驱动晶体管的漏极连接，所述有机电致发光二极管的第一极通过贯穿所述第二子平坦化层的过孔与所述转接电极连接。
  14. 根据权利要求12或13所述的显示基板，其中，所述过渡区设置有多圈围堰结构，且所述多圈围堰结构相邻设置；所述多圈围堰结构中至少靠近开孔区的所述围堰结构的下方设置有辅助结构，以使在两相邻的所述围堰结构中靠近开孔区的一者在背离所述基底的方向上突出于另一者；所述辅助结构与所述平坦化层同层设置，且材料相同。
  15. 根据权利要求1所述的显示基板，其中，所述显示基板还包括位于所述基底上的驱动电路层；所述驱动电路层至少包括驱动晶体管和层间介质层；所述驱动晶体管的有源层设置所述基底靠近所述有机电致发光二极管的一侧，第一栅绝缘层所述有源层，栅极设置所述第一栅绝缘层背离所述有源层的一侧，第二栅绝缘层覆盖所述栅极和所述第一栅绝缘层，所述层间介质层覆盖所述第二栅绝缘层；所述驱动晶体管的源极和漏极形成在所述层间介质层背离所述基底的一侧；所述第一隔离柱包括与围堰结构相邻的第一子隔离柱，以及位于所述第一子隔离柱靠近所述显示区一侧的第二子隔离柱；
    在所述第一子隔离柱与第二子隔离柱之间设置有第一开槽，在所述第一子隔离柱与所述围堰结构之间设置有第二开槽；所述第一开槽和所述第二开槽贯穿所述层间介质层、所述第一栅绝缘层、所述第二栅绝缘层中的至少一层。
  16. 根据权利要求1所述的显示基板，其中，所述第一封装层的厚度为1μm-2μm；所述第二封装层的厚度为10μm-15μm；所述第三封装层的厚度为0.5μm-1μm。
  17. 一种显示基板的制备方法，所述显示基板具有开孔区、环绕所述开孔区的过渡区，以及环绕所述过渡区的显示区；其中，所述显示基板的制备方法包括：
    在基底上形成隔离柱、围堰结构；所述隔离柱和所述围堰结构均位于所述过渡区且环绕所述开孔区的；其中，形成所述隔离柱包括形成第一隔离柱，所述第一隔离柱位于所述围堰结构靠近所述显示区的一侧；
    在所述隔离柱所在层背离所述基底的一侧依次形成有机电致发光二极 管、第一封装层、第二封装层、第三封装层，所述有机电致发光二极管位于所述显示区，所述第一封装层和所述第三封装层在所述基底上的正投影至少覆盖所述显示区和所述过渡区；所述第二封装层在所述基底上的正投影覆盖所述显示区和所述过渡区的所述第一隔离柱；其中，
    位于所述第一隔离柱上的所述第二封装层的厚度，与所述第一隔离柱的厚度比为2:1～6:1。
  18. 根据权利要求17所述的制备方法，其中，所述第一隔离柱包括第一子隔离柱，所述第一子隔离柱与所述围堰结构相邻，所述第二封装层在所述基底上的正投影与所述第一子隔离柱重叠的区域的平均厚度与所述第一子隔离柱的厚度比为2:1～6:1。
  19. 根据权利要求17或18所述的制备方法，其中，还包括：所述隔离柱靠近所述基底上的一侧形成驱动电路层；所述驱动电路层至少包括驱动晶体管；
    所述驱动晶体管的源极和漏极与所述隔离柱采用一次构图工艺形成。
  20. 根据权利要求17-19中任一项所述的制备方法，其中，在形成所述有机电致发光二极管的第一极和发光层之间还包括形成像素限定层，所述像素限定层具有容纳所述发光层的容纳部；所述围堰结构与所述像素限定层采用一次构图工艺形成。
  21. 根据权利要求20所述的制备方法，其中，所述过渡区设置有多圈围堰结构，且所述多圈围堰结构相邻设置；所述多圈围堰结构中至少靠近开孔区的所述围堰结构的形成有辅助结构，以使在两相邻的所述围堰结构中靠近开孔区的一者在背离所述基底的方向上突出于另一者；在所述驱动晶体管的源极和漏极所在层与有机电致发光二极管的第一极所在层之间形成有平坦化层，所述第一极通过贯穿所述平坦化层的过孔与所述驱动晶体管的漏极连接；所述辅助结构与所述平坦化层采用一次构图工艺形成。
  22. 一种显示面板，其包括权利要求1-16中任一项所述的显示基板。
PCT/CN2021/074884 2020-03-31 2021-02-02 显示基板及显示面板 Ceased WO2021196868A1 (zh)

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