WO2021196974A1 - 一种半导体外延结构及半导体器件 - Google Patents

一种半导体外延结构及半导体器件 Download PDF

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WO2021196974A1
WO2021196974A1 PCT/CN2021/079157 CN2021079157W WO2021196974A1 WO 2021196974 A1 WO2021196974 A1 WO 2021196974A1 CN 2021079157 W CN2021079157 W CN 2021079157W WO 2021196974 A1 WO2021196974 A1 WO 2021196974A1
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layer
barrier layer
epitaxial structure
semiconductor epitaxial
digital alloy
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陈智斌
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
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    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
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    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
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    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3214—Materials thereof being Group IIIA-VA semiconductors
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    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
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    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
    • H10P14/3244—Layer structure
    • H10P14/3251—Layer structure consisting of three or more layers
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    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3416—Nitrides

Definitions

  • This application relates to the field of semiconductor technology, in particular to a semiconductor epitaxial structure and a semiconductor device.
  • Gallium nitride is widely used in power electronic devices and radio frequency devices due to its advantages such as large band gap and high mobility. Among them, it is the most widely used in the field of High Electron Mobility Transistor (HEMT).
  • the current enhanced HEMT includes a channel layer, a barrier layer, and a p-GaN layer stacked in sequence, and the p-GaN layer is generally implemented by Mg ion doping.
  • Mg ions have a diffusion problem. When a large amount of Mg ions diffuse into the barrier layer and the channel layer, it will affect the density and mobility of two-dimensional electronic gas (2DEG), resulting in an increase in on-resistance.
  • 2DEG two-dimensional electronic gas
  • the present application provides a semiconductor epitaxial structure, which effectively prevents Mg ions in the p-GaN layer from diffusing into the barrier layer and the channel layer, affecting the density and mobility of the 2DEG, and causing the problem of increased on-resistance.
  • the application also provides a semiconductor device.
  • the semiconductor epitaxial structure of the present application includes a channel layer, a composite barrier layer, and a doped layer.
  • the doped layer is provided on the composite barrier layer, and the channel layer is located away from the composite barrier layer.
  • the composite barrier layer includes a stacked digital alloy barrier layer and an AlGaN barrier layer, and the digital alloy barrier layer includes one or more AlN layers.
  • the composite barrier layer is arranged between the doped layer and the channel layer, and the digital alloy barrier layer in the composite barrier layer includes one or more AlN layers, It is an atomic layer formed by a compound.
  • the present application can effectively prevent the doping layer and the channel layer by providing the digital alloy barrier layer including one or more AlN layers.
  • the Mg ions doped in the impurity layer diffuse in the composite barrier layer and the channel layer, avoiding the increase of on-resistance, and ensuring the electrical performance of the semiconductor epitaxial structure.
  • the digital alloy barrier layer also functions as an equivalent AlGaN barrier layer, that is, the digital alloy barrier layer and the AlGaN barrier layer together form the composite barrier layer for Polarization is generated with the channel layer, so that 2DEG is generated between the composite barrier layer and the channel layer.
  • the growth rate of the digital alloy barrier layer is much lower than that of the AlGaN barrier layer. Therefore, by combining the digital alloy barrier and the AlGaN barrier layer, on the basis of preventing the diffusion of Mg ions , Effectively improve the production efficiency of the product and reduce the production cost of the product.
  • the growth method of the digital alloy barrier layer generates extremely small stress under the same Al atomic number ratio, and avoids the inverse piezoelectric effect caused by stress under high-temperature and high-power working conditions.
  • the digital alloy barrier layer is disposed between the doped layer and the AlGaN barrier layer. That is to say, the digital alloy barrier layer is closer to the doped layer than the AlGaN barrier layer. Since the digital alloy barrier layer is an atomic layer formed of a simple substance or a compound, it is compared with that formed by a mixture.
  • the AlGaN barrier layer the digital alloy barrier layer can more effectively block the diffusion of Mg ions in the doped layer. Therefore, it is more effective to place the digital alloy barrier layer close to the doped layer
  • the Mg ions doped in the doped layer are prevented from diffusing in the composite barrier layer and the channel layer, which prevents the on-resistance from increasing, and ensures the electrical performance of the semiconductor epitaxial structure.
  • the AlGaN barrier layer is connected between the doped layer and the digital alloy barrier layer.
  • the digital alloy barrier layer is a stack of 1-10 single-period AlN layers/GaN layers. That is to say, the AlN layer and the GaN layer are periodically arranged to form the digital alloy barrier layer, so that the arrangement of the digital alloy barrier layer is more regular, thereby having better prevention of doping in the doped layer.
  • the effect of the diffusion of impurity Mg ions in the composite barrier layer and the channel layer prevents the on-resistance from increasing and ensures the electrical performance of the semiconductor epitaxial structure.
  • the digital alloy barrier layer is limited to a stack of 1-10 single-period AlN layers/GaN layers. Therefore, on the basis of preventing the diffusion of Mg ions, the production efficiency of the product is effectively improved, and the production cost of the product is reduced.
  • the thickness of the digital alloy barrier layer is 1 nm-10 nm. With this thickness, the digital alloy barrier layer can better combine with the AlGaN barrier layer, ensuring the electrical properties of the digital alloy barrier layer and the AlGaN barrier layer. At the same time, the thickness of the digital alloy barrier layer is between 1 nm and 10 nm, which can effectively improve the production efficiency of the product and reduce the production cost of the product on the basis of preventing the diffusion of Mg ions.
  • the thickness of the AlGaN barrier layer is 2 nm to 40 nm, so as to avoid the excessive thickness of the AlGaN barrier layer from causing relaxation phenomena, which would affect the electrical properties of the semiconductor epitaxial structure.
  • the proportion of Al atoms in the single-period AlN layer/GaN layer in the digital alloy barrier layer is 10%-50%.
  • the ratio of Al atoms in the single-period AlN layer/GaN layer of 10% to 50% can effectively prevent the diffusion of Mg ions, and at the same time, it can also avoid the excessive proportion of Al atoms in the digital alloy barrier layer to cause leakage This phenomenon ensures the electrical performance of the semiconductor epitaxial structure.
  • the ratio of the thickness of the AlN layer to the GaN layer in the single-period AlN layer/GaN layer is m:n, where m is a positive integer less than or equal to 3, and n is a positive integer less than or equal to 10. That is to say, in this embodiment, the ratio of the thickness of the AlN layer and the GaN layer in the single-period AlN layer/GaN layer is controlled to control the proportion of the number of Al atoms in the single-period AlN layer/GaN layer.
  • the thickness ratio of the AlN layer and the GaN layer in the single-period AlN layer/GaN layer is 1:3, so as to ensure that the digital alloy barrier layer prevents the diffusion of Mg ions. Effectively improve product production efficiency and reduce product production costs.
  • the proportion of Al atoms in the digital alloy barrier layer is greater than the proportion of Al atoms in the AlGaN barrier layer. That is to say, the number of Al atoms in the digital alloy barrier layer close to the doped layer is higher, so as to better prevent the diffusion of Mg ions.
  • the proportion of Al atoms in the digital alloy barrier layer may also be less than or equal to the proportion of Al atoms in the AlGaN barrier layer.
  • the number of the digital alloy barrier layers is two layers, the two layers of the digital alloy barrier layers are respectively arranged on both sides of the AlGaN barrier layer, and the AlGaN barrier layer in the digital alloy barrier layer
  • the atomic ratio is greater than the atomic ratio of Al in the AlGaN barrier layer.
  • both sides of the AlGaN barrier layer are provided with the digital alloy barrier layer that can prevent the diffusion of Mg ions, which can effectively prevent the diffusion of Mg ions into the AlGaN barrier layer, even if there is If a small amount of Mg ions diffuse into the AlGaN barrier layer, they will still be blocked by the digital alloy barrier layer on the other side, so that Mg ions can be prevented from diffusing into the channel layer through the AlGaN barrier layer. In order to increase the on-resistance, the electrical performance of the semiconductor epitaxial structure is effectively ensured.
  • the proportion of Al atoms in the digital alloy barrier layer may also be less than or equal to the proportion of Al atoms in the AlGaN barrier layer.
  • the semiconductor epitaxial structure further includes an insertion layer, and two opposite surfaces of the insertion layer are respectively connected to the AlGaN barrier layer and the channel layer.
  • the insertion layer is an AlN layer, and the forbidden band width of the insertion layer is larger, which enhances the polarization effect of the channel layer and can increase the concentration of 2DEG. The role of lattice mismatch between the barrier layer and the channel layer.
  • the semiconductor epitaxial structure further includes a substrate layer, and the substrate layer is located on the side of the channel layer facing away from the composite barrier layer.
  • the material of the substrate layer is silicon.
  • the substrate layer can also be made of other substrate materials, such as sapphire, gallium nitride, silicon carbide, diamond and other materials.
  • the substrate layer is used to carry layer structures such as the channel layer, the composite barrier layer, and the doped layer.
  • the semiconductor epitaxial structure further includes a buffer layer provided on the surface of the channel layer facing away from the composite barrier layer.
  • the material of the buffer layer is AlGaN.
  • the buffer layer may also be made of AlN, GaN, and other materials. The buffer layer is used to buffer the effect of the force between the channel layer and the related layer structure.
  • the semiconductor epitaxial structure further includes a nucleation layer, and the buffer layer of the nucleation layer faces away from the surface of the channel layer.
  • the material of the nucleation layer is AlN, which plays a role in improving the stress caused by the lattice mismatch between the materials.
  • the semiconductor device described in the present application includes the above-mentioned semiconductor epitaxial structure.
  • the semiconductor device with the above semiconductor epitaxial structure can effectively avoid the increase in on-resistance caused by the diffusion of Mg ions from the p-GaN layer to the barrier layer and the channel layer, thereby increasing the power density of the semiconductor device and having better performance. Electrical performance.
  • the composite barrier layer is arranged between the doped layer and the channel layer, and the digital alloy barrier layer in the composite barrier layer includes one or more AlN layers, It is an atomic layer formed by a compound.
  • the present application can effectively prevent the doping layer and the channel layer by providing the digital alloy barrier layer including one or more AlN layers.
  • the Mg ions doped in the impurity layer diffuse in the composite barrier layer and the channel layer to prevent the on-resistance from increasing, thereby ensuring the electrical performance of the semiconductor epitaxial structure.
  • FIG. 1 is a schematic structural diagram of a semiconductor epitaxial structure provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of the structure of the digital alloy barrier layer in the semiconductor epitaxial structure provided in FIG. 1.
  • FIG. 3 is a schematic diagram of the specific arrangement structure of the digital alloy barrier layer provided in FIG. 2.
  • FIG. 4 is a schematic diagram of the specific arrangement structure of the AlGaN barrier layer provided in FIG. 1.
  • FIG. 5 is a schematic diagram of another structure of the semiconductor epitaxial structure.
  • FIG. 6 is a schematic diagram of another structure of the semiconductor epitaxial structure.
  • FIG. 7 is a schematic diagram of another structure of the semiconductor epitaxial structure.
  • FIG. 8 is a schematic diagram of another structure of the semiconductor epitaxial structure.
  • HEMTs are mostly D-mode structures, that is, depletion type HEMTs, without p-GaN layer, that is to say, the channel layer of depletion type HEMT is provided with a barrier layer, between the channel layer and the barrier layer 2DEG is produced through polarization.
  • the design purpose of the barrier layer is to increase the density and mobility of the 2DEG.
  • the barrier layer mainly uses an AlGaN barrier layer, and digital alloys are rarely used as a barrier layer due to low growth rate and other reasons.
  • the commercial HEMT structure must be an E-mode structure, that is, an enhanced HEMT. Compared with the depleted HEMT, it is not dangerous and has low static power consumption.
  • the enhanced HEMT includes a channel layer, a barrier layer, and a p-GaN layer stacked in sequence.
  • the p-GaN layer is formed by doping Mg ions. Increase the Mg ion concentration in the p-GaN layer to increase the hole concentration.
  • the barrier layer mainly uses an AlGaN barrier layer, the AlGaN barrier layer has a poor effect on preventing the diffusion of Mg ions in the p-GaN layer, and it is too high.
  • the concentration of Mg ions diffuses into the channel layer through the AlGaN barrier layer, resulting in the increase of the sheet resistance (Rsheet) and on-resistance (Ron) of the channel layer, thereby limiting the power density of the HEMT and affecting the electrical performance of the HEMT.
  • the embodiments of the present application provide a semiconductor device, which solves the increase in the sheet resistance (Rsheet) and the on-resistance (Ron) of the channel layer caused by the diffusion of Mg ions in the p-GaN layer, thereby limiting the HEMT Power density is a problem that affects the electrical performance of HEMT, effectively preventing the diffusion of Mg ions, and using a composite structure of digital alloy barriers and traditional AlGaN barriers to reduce growth time and reduce costs.
  • Semiconductor devices include, but are not limited to, semiconductor devices such as HEMT and power electronic devices with heterostructures that generate 2DEG, and semiconductor devices such as radio frequency devices.
  • the semiconductor device is a HEMT as an example for specific description.
  • the semiconductor device of the present application includes a semiconductor epitaxial structure.
  • the semiconductor device with the above semiconductor epitaxial structure can effectively avoid the increase of on-resistance caused by the diffusion of Mg ions from the p-GaN layer to the barrier layer and the channel layer, thereby increasing the power density and having good electrical performance.
  • FIG. 1 is a schematic structural diagram of a semiconductor epitaxial structure provided by an embodiment of the present application.
  • FIG. 1 shows a first embodiment of a semiconductor epitaxial structure 10.
  • the semiconductor epitaxial structure 10 of the present application includes a substrate layer 11, a buffer layer 12, a channel layer 13, a composite barrier layer 14 and a doped layer 15.
  • the doped layer 15 is provided on the composite barrier layer 14, and the channel layer 13 is located on the composite barrier layer.
  • the barrier layer 14 is on the side away from the doped layer 15, the substrate layer 11 is on the side of the channel layer 13 away from the composite barrier layer 14, the buffer layer 12 is located between the substrate layer 11 and the channel layer 13, and the composite barrier layer 14 includes
  • the digital alloy barrier layer 141 and the AlGaN barrier layer 142 are stacked, and the digital alloy barrier layer 141 may include one or more AlN layers 1411.
  • a composite barrier layer 14 is provided between the doped layer 15 and the channel layer 13.
  • the digital alloy barrier layer 141 in the composite barrier layer 14 may include one or more AlN layers. 1411, which is an atomic layer formed by a compound.
  • the present application provides a digital alloy barrier layer 141 including one or more AlN layers 1411 between the doped layer 15 and the channel layer 13, which can effectively prevent doping.
  • the Mg ions doped in the impurity layer 15 diffuse in the composite barrier layer 14 and the channel layer 13 to avoid an increase in on-resistance and ensure the electrical performance of the semiconductor epitaxial structure 10.
  • the digital alloy barrier layer 141 also functions as an equivalent AlGaN barrier layer 142, that is to say, the digital alloy barrier layer 141 and the AlGaN barrier layer 142 together form a composite barrier layer 14 for use with the channel
  • the layer 13 generates polarization, so that 2DEG is generated between the composite barrier layer 14 and the channel layer 13.
  • the growth rate of the digital alloy barrier layer 141 is much lower than that of the AlGaN barrier layer 142. Therefore, by combining the digital alloy barrier layer 141 and the AlGaN barrier layer 142, it is effective to prevent the diffusion of Mg ions. Product production efficiency reduces product production costs.
  • the growth method of the digital alloy barrier layer 141 generates extremely small stress under the same Al atomic ratio, which avoids the inverse piezoelectric effect caused by stress under high-temperature and high-power working conditions.
  • the material of the substrate layer 11 is silicon.
  • the substrate layer 11 can also be made of other substrate materials, such as sapphire, gallium nitride, silicon carbide, diamond and other materials.
  • the substrate layer 11 is used to carry the buffer layer 12, the channel layer 13, the composite barrier layer 14, and the doped layer 15 and other layer structures.
  • the buffer layer 12 is provided on the surface of the substrate layer 11 facing the channel layer 13, and the material of the buffer layer 12 is AlGaN. Of course, in other embodiments, the buffer layer 12 may also be made of AlN, GaN, and other materials.
  • the thickness of the buffer layer 12 is between 0.5 um and 10 um, and the buffer layer 12 is used to buffer the effect of the force between the substrate layer 11 and the channel layer 13.
  • the channel layer 13 is connected to the surface of the buffer layer 12 facing away from the substrate layer 11, and the material of the channel layer 13 is GaN.
  • the channel layer 13 may also be made of materials such as AlGaN or InGaN.
  • the thickness of the channel layer 13 is between 0.02 um and 1 um, and the channel layer 13 interacts with the composite barrier layer 14 to form 2DEG.
  • the digital alloy barrier layer 141 is provided between the doped layer 15 and the AlGaN barrier layer 142, and the AlGaN barrier layer 142 is provided on the surface of the channel layer 13 facing away from the buffer layer 12. That is to say, the channel layer 13, the AlGaN barrier layer 142, the digital alloy barrier layer 141 and the doped layer 15 are stacked in sequence, and the opposite two surfaces of the digital alloy barrier layer 141 are respectively connected to the doped layer 15 and the AlGaN potential layer.
  • the barrier layer 142 is connected, and the digital alloy barrier layer 141 is closer to the doped layer 15 than the AlGaN barrier layer 142.
  • the digital alloy barrier layer 141 is an atomic layer formed of a simple substance or a compound, it is compared with the AlGaN potential formed by a mixture.
  • the barrier layer 142 and the digital alloy barrier layer 141 can more effectively block the diffusion of Mg ions in the doped layer 15. Therefore, placing the digital alloy barrier layer 141 close to the doped layer 15 can more effectively prevent the doped layer 15 from doping.
  • the Mg ions in the composite barrier layer 14 and the channel layer 13 diffuse in the composite barrier layer 14 and the channel layer 13 to avoid the on-resistance increase and ensure the electrical performance of the semiconductor epitaxial structure 10.
  • the AlGaN barrier layer 142 is connected between the doped layer 15 and the digital alloy barrier layer 141.
  • changing the positions of the digital alloy barrier layer 141 and the AlGaN barrier layer 142 can also effectively prevent the Mg ions from diffusing into the composite barrier layer 14 and the channel layer 13 and avoid the on-resistance increase.
  • the electrical performance of the semiconductor epitaxial structure 10 is ensured.
  • the doped layer 15 in this embodiment is provided on the surface of the digital alloy barrier layer 141 facing away from the AlGaN barrier layer 142, and the doped layer 15 is a P-type doped layer 15 formed of GaN material and doped with Mg ions.
  • the surface of the doped layer 15 facing the digital alloy barrier layer 141 is laminated with the GaN layer 1412 in the digital alloy barrier layer 141.
  • FIG. 2 is a schematic diagram of the digital alloy barrier layer in the semiconductor epitaxial structure provided in FIG. 1.
  • FIG. 3 is a schematic diagram of the specific arrangement structure of the digital alloy barrier layer provided in FIG. 2.
  • the digital alloy barrier layer 141 is a stack of three single-period AlN layers 1411 / GaN layers 1412. It is understandable that the single-period AlN layer 1411 / GaN layer 1412 is formed by stacking an AlN layer 1411 and a GaN layer 1412, and three single-period AlN layers 1411 / GaN layer 1412 are an AlN layer 1411 and a GaN layer 1412.
  • AlN layer 1411 a GaN layer
  • AlN layer 1411 a GaN layer
  • AlN layer 1411 a GaN layer
  • GaN layer 1412 three-layer AlN layers 1411 and three GaN layers Overlapping in turn.
  • the AlN layer 1411 and the doped layer 15 in the digital alloy barrier layer 141 are laminated on the surface of the digital alloy barrier layer 141, which is beneficial to prevent the diffusion of Mg ions.
  • the AlN layer 1411 and the GaN layer 1412 are periodically arranged to form a digital alloy barrier layer 141, so that the compound AlNa and the compound GaNb of the digital alloy barrier layer 141 are arranged in rows, respectively, compared to the AlGaN compound in the AlGaN mixture.
  • the random arrangement of the compound AlNa and the compound GaNb (see Figure 4), the compound AlNa in the digital alloy barrier layer 141 is arranged more regularly, which has a better prevention of the recombination potential of the Mg ions doped in the doped layer 15
  • the diffusion effect in the barrier layer 14 and the channel layer 13 prevents the on-resistance from rising and ensures the electrical performance of the semiconductor epitaxial structure 10.
  • the digital alloy barrier layer 141 is limited to a stack of 3 single-period AlN layers 1411 / GaN layer 1412, that is, the digital alloy barrier layer 141 is sufficient to block the diffusion of Mg ions, thereby preventing the diffusion of Mg ions. On the basis of this, effectively improve the production efficiency of the product and reduce the production cost of the product.
  • the digital alloy barrier layer 141 is a stack of 1-10 single-period AlN layers 1411 / GaN layers 1412.
  • the GaN in the digital alloy barrier layer 141 can also be replaced by other compounds.
  • the digital alloy barrier layer 141 is a stack of InN layer ⁇ AlN layer.
  • the thickness of the digital alloy barrier layer 141 in this embodiment is 6 nm. Specifically, with this thickness, the digital alloy barrier layer 141 can better combine with the AlGaN barrier layer 142, ensuring the electrical properties of the digital alloy barrier layer 141 and the AlGaN barrier layer 142. At the same time, the thickness of the digital alloy barrier layer 141 is 6 nm, which can effectively improve the production efficiency of the product and reduce the production cost of the product on the basis of preventing the diffusion of Mg ions. Of course, in other embodiments, the thickness of the digital alloy barrier layer 141 can be selected from 1 nm to 10 nm.
  • the number of Al atoms in the single-period AlN layer 1411/GaN layer 1412 in the digital alloy barrier layer 141 is 25%, that is, the number of Al atoms in the single-period AlN layer 1411/GaN layer 1412 accounts for all atoms. The proportion of the number.
  • the single-layer thickness of the GaN layer 1412 and the AlN layer 1411 in the single-period AlN layer 1411/GaN layer 1412 is about 0.5 nm, and the thickness of the AlN layer 1411 and the GaN layer 1412 in the single-period AlN layer 1411 With a thickness ratio of 1:3, three GaN layers 1412 and an AlN layer 1411 are stacked in sequence, that is, the ratio of Al atoms in the single-period AlN layer 1411 / GaN layer 1412 is 25%.
  • the single-period AlN layer 1411 / GaN layer 1412 may also be an AlN layer 1411 and three GaN layers 1412 stacked in sequence, or one AlN layer 1411 is located between any two of the three GaN layers 1412.
  • the single-period AlN layer 1411/GaN layer 1412 contains 25% of Al atoms, which can effectively prevent the diffusion of Mg ions, and at the same time avoid the excessively high Al atoms in the digital alloy barrier layer 141 and the leakage phenomenon.
  • the electrical performance of the semiconductor epitaxial structure 10 is ensured. At the same time, it can ensure that the digital alloy barrier layer 141 can effectively improve the production efficiency of the product and reduce the production cost of the product on the basis of preventing the diffusion of Mg ions.
  • the proportion of Al atoms in the single-period AlN layer 1411 / GaN layer 1412 may be 10%-50%.
  • the single layer thickness of the GaN layer 1412 and the AlN layer 1411 is about 0.5 nm
  • the ratio of the thickness of the AlN layer 1411 to the GaN layer 1412 in the single-period AlN layer 1411/GaN layer 1412 is m:n, where m is a positive integer less than or equal to 3, and n is a positive integer less than or equal to 10, that is, in this embodiment
  • the ratio of Al atoms in the single-period AlN layer 1411 / GaN layer 1412 is controlled to be 10%-50%. It can effectively prevent the diffusion of Mg ions, and at the same time, it can also avoid the leakage phenomenon caused by the excessive proportion of
  • the thickness of the AlGaN barrier layer 142 is 2nm-40nm, so as to avoid the excessive thickness of the AlGaN barrier layer 142 and the relaxation phenomenon, that is, the excessive thickness of the AlGaN barrier layer 142 will cause stress.
  • Deformation for example, the phenomenon of surface bending
  • the proportion of Al atoms in the AlGaN barrier layer 142 is 25%.
  • the proportion of Al atoms in the AlGaN barrier layer 142 can also be 5%-30%, which can be adjusted according to the proportion of Al atoms in the digital alloy barrier layer 141, so that the entire The composite barrier layer 14 meets the electrical performance requirements.
  • FIG. 5 is a schematic diagram of another structure of the semiconductor epitaxial structure.
  • FIG. 5 shows a second embodiment of the semiconductor epitaxial structure 10.
  • the semiconductor epitaxial structure 10 in this embodiment includes a substrate layer 11, a buffer layer 12, a channel layer 13, a composite barrier layer 14 and a doped layer 15.
  • the substrate layer 11, the buffer layer 12 and the channel layer 13 are stacked in sequence,
  • the composite barrier layer 14 is provided on the side of the channel layer 13 away from the buffer layer 12, and the doped layer 15 is provided on the surface of the composite barrier layer 14 away from the channel layer 13, and the composite barrier layer 14 includes stacked digital alloy potentials.
  • the barrier layer 141 and the AlGaN barrier layer 142, and the digital alloy barrier layer 141 are arranged close to the doped layer 15.
  • the semiconductor epitaxial structure 10 in this embodiment further includes an insertion layer 16, and two opposite surfaces of the insertion layer 16 are respectively connected to the AlGaN barrier layer 142 and the channel layer 13.
  • the insertion layer 16 is an AlN layer, and the forbidden band width of the insertion layer 16 (forbidden band width refers to a band gap width (unit is electron volt (ev)), the trapped electrons must become free electrons or holes , It is necessary to obtain enough energy to transition from the valence band to the conduction band.
  • the semiconductor epitaxial structure 10 may also include a nucleation layer 17.
  • FIG. 6 is a schematic diagram of another structure of the semiconductor epitaxial structure.
  • FIG. 6 shows a third embodiment of the semiconductor epitaxial structure 10.
  • the semiconductor epitaxial structure 10 in this embodiment includes a substrate layer 11, a buffer layer 12, a channel layer 13, a composite barrier layer 14 and a doped layer 15.
  • the buffer layer 12 and the channel layer 13 are stacked, and the substrate layer is located in the buffer layer.
  • the side of the layer 12 facing away from the channel layer 13, the composite barrier layer 14 is provided on the side of the channel layer 13 away from the buffer layer 12, and the doped layer 15 is provided on the surface of the composite barrier layer 14 away from the channel layer 13.
  • the composite barrier layer 14 includes a stacked digital alloy barrier layer 141 and an AlGaN barrier layer 142.
  • the digital alloy barrier layer 141 is arranged close to the doped layer 15, and there is an insert between the composite barrier layer 14 and the channel layer 13.
  • Layer 16 The semiconductor epitaxial structure 10 in this embodiment further includes a nucleation layer 17 provided on the surface of the substrate layer 11 facing the buffer layer 12.
  • the material of the nucleation layer 17 is AlN, which plays a role in improving the stress caused by the lattice mismatch between the materials.
  • the insertion layer 16 is not provided between the composite barrier layer 14 and the channel layer 13, that is, the composite barrier layer 14 and the channel layer 13 are directly connected.
  • FIG. 7 is a schematic diagram of another structure of the semiconductor epitaxial structure.
  • FIG. 7 shows a fourth embodiment of the semiconductor epitaxial structure 10.
  • the semiconductor epitaxial structure 10 in this embodiment includes a substrate layer 11, a nucleation layer 17, a buffer layer 12, a channel layer 13, an insertion layer 16, a composite barrier layer 14 and a doped layer 15, which are sequentially stacked and arranged.
  • the layer 14 includes a digital alloy barrier layer 141 and an AlGaN barrier layer 142 arranged in a stack, and the digital alloy barrier layer 141 is arranged close to the doped layer 15.
  • the proportion of Al atoms in the digital alloy barrier layer 141 is greater than the proportion of Al atoms in the AlGaN barrier layer 142.
  • the proportion of Al atoms in the digital alloy barrier layer 141 and the proportion of Al atoms in the AlGaN barrier layer 142 can be set according to specific needs.
  • the digital alloy barrier layer 141 close to the doped layer 15 has a higher proportion of Al atoms, so as to better prevent the diffusion of Mg ions.
  • the proportion of Al atoms in the digital alloy barrier layer 141 may also be less than or equal to the proportion of Al atoms in the AlGaN barrier layer 142.
  • the semiconductor epitaxial structure 10 may also not be provided with the core layer 17 and/or the insertion layer 16, that is, the substrate layer 11, the buffer layer 12, the channel layer 13, the insertion layer 16, the composite barrier layer 14 and the doping layer 15.
  • the substrate layer 11 Laminated in sequence, or the substrate layer 11, the nucleation layer 17, the buffer layer 12, the channel layer 13, the composite barrier layer 14 and the doped layer 15 are stacked in sequence, or the substrate layer 11, the buffer layer 12, and the channel layer 13 , The composite barrier layer 14 and the doped layer 15 are stacked in sequence.
  • FIG. 8 is a schematic diagram of another structure of the semiconductor epitaxial structure.
  • FIG. 8 shows a fifth embodiment of the semiconductor epitaxial structure 10.
  • the semiconductor epitaxial structure 10 in this embodiment includes a substrate layer 11, a nucleation layer 17, a buffer layer 12, a channel layer 13, an insertion layer 16, a composite barrier layer 14 and a doped layer 15, which are sequentially stacked and arranged.
  • the layer 14 includes a digital alloy barrier layer 141 and an AlGaN barrier layer 142 arranged in a stack, and the digital alloy barrier layer 141 is arranged close to the doped layer 15.
  • the number of digital alloy barrier layers 141 in this embodiment is two layers, and the two digital alloy barrier layers 141 are respectively arranged on both sides of the AlGaN barrier layer 142, that is, between the AlGaN barrier layer 142 and the insertion layer 16 A new layer of digital alloy barrier layer 141 is added, and the proportion of Al atoms in the digital alloy barrier layer 141 is greater than the proportion of Al atoms in the AlGaN barrier layer 142.
  • the thickness of the two digital alloy barrier layers 141 in this embodiment is the same or different, that is to say, digital alloy barrier layers 141 are provided on both sides of the AlGaN barrier layer 142 to prevent the diffusion of Mg ions. It can effectively prevent the diffusion of Mg ions into the AlGaN barrier layer 142.
  • the proportion of Al atoms in the digital alloy barrier layer 141 may also be less than or equal to the proportion of Al atoms in the AlGaN barrier layer 142.
  • the number of AlGaN barrier layers 142 may also be two, which are respectively provided on both sides of the digital alloy barrier layer 141.
  • the semiconductor epitaxial structure 10 may not be provided with the nucleus layer 17 and/or the insertion layer 16, that is, the substrate layer 11, the buffer layer 12, the channel layer 13, the insertion layer 16, the composite barrier layer 14 and the doping layer 15. Laminated in sequence, or the substrate layer 11, the nucleation layer 17, the buffer layer 12, the channel layer 13, the composite barrier layer 14 and the doped layer 15 are stacked in sequence, or the substrate layer 11, the buffer layer 12, and the channel layer 13 , The composite barrier layer 14 and the doped layer 15 are stacked in sequence.
  • a composite barrier layer 14 is provided between the doped layer 15 and the channel layer 13.
  • the digital alloy barrier layer 141 in the composite barrier layer 14 includes one or more layers of AlN layer 1411, which is formed by a compound
  • the present application provides a digital alloy barrier layer 141 including one or more AlN layers 1411 between the doped layer 15 and the channel layer 13, which can effectively prevent doping in the doped layer 15
  • the Mg ions in the composite barrier layer 14 and the channel layer 13 diffuse in the composite barrier layer 14 and the channel layer 13 to avoid the increase of the on-resistance of the 2DEG and ensure the electrical performance of the semiconductor epitaxial structure 10.
  • the digital alloy barrier layer 141 also functions as an equivalent AlGaN barrier layer 142, that is to say, the digital alloy barrier layer 141 and the AlGaN barrier layer 142 together form a composite barrier layer 14 for use with the channel
  • the layer 13 generates a polarization effect, so that 2DEG is generated between the composite barrier layer 14 and the channel layer 13.
  • the growth rate of the digital alloy barrier layer 141 is much lower than that of the AlGaN barrier layer 142. Therefore, by combining the digital alloy barrier and the AlGaN barrier layer 142, on the basis of preventing the diffusion of Mg ions, the product is effectively improved. Production efficiency reduces product production costs.
  • the growth method of the digital alloy barrier layer 141 generates extremely small stress under the same Al atomic ratio, which avoids the inverse piezoelectric effect caused by stress under high-temperature and high-power working conditions.

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Abstract

本申请提供一种半导体外延结构及半导体器件。所述半导体外延结构包括沟道层、复合势垒层和掺杂层，所述掺杂层设于所述复合势垒层上，所述沟道层位于所述复合势垒层背离所述掺杂层一侧，所述复合势垒层包括层叠设置的数字合金势垒层和AlGaN势垒层，所述数字合金势垒层中包括一层或多层AlN层。本申请提供的半导体外延结构有效避免p-GaN层中Mg离子扩散到势垒层和沟道层，影响二维电子气的密度和迁移率，导致导通电阻上升的问题。

Description

一种半导体外延结构及半导体器件
本申请要求于2020年03月31日提交中国专利局、申请号为202010241496.7、申请名称为“一种半导体外延结构及半导体器件”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，特别涉及一种半导体外延结构及半导体器件。
背景技术
氮化镓(Gallium nitride，GaN)由于禁带宽度大、迁移率高等优势，广泛用于电力电子器件和射频器件等。其中，在高电子迁移率晶体管(High electron mobility transistor，HEMT)领域应用最广泛。目前的增强型HEMT包括依次层叠的沟道层、势垒层和p-GaN层，而其中的p-GaN层一般通过Mg离子掺杂实现。但是Mg离子存在扩散问题，当Mg离子大量扩散到势垒层和沟道层时，会影响二维电子气(Two-dimensional electronic gas，2DEG)的密度和迁移率，导致导通电阻上升。
发明内容
本申请提供一种半导体外延结构，有效避免p-GaN层中的Mg离子扩散到势垒层和沟道层，影响2DEG的密度和迁移率，导致导通电阻上升的问题。
本申请还提供一种半导体器件。
本申请所述半导体外延结构包括沟道层、复合势垒层和掺杂层，所述掺杂层设于所述复合势垒层上，所述沟道层位于所述复合势垒层背离所述掺杂层一侧，所述复合势垒层包括层叠设置的数字合金势垒层和AlGaN势垒层，所述数字合金势垒层中包括一层或多层AlN层。
本申请通过在所述掺杂层和所述沟道层之间设置所述复合势垒层，所述复合势垒层中的所述数字合金势垒层中包括一层或多层AlN层，其为化合物形成的原子层叠层，换言之，本申请通过在所述掺杂层和所述沟道层之间设置包括一层或多层AlN层的所述数字合金势垒层，能有效防止掺杂层中掺杂的Mg离子在所述复合势垒层和所述沟道层中扩散，避免了导通电阻上升，保证了所述半导体外延结构的电性能。同时，所述数字合金势垒层还起到等效AlGaN势垒层的作用，也就是说，所述数字合金势垒层和所述AlGaN势垒层共同形成所述复合势垒层，用于与所述沟道层产生极化作用，以使所述复合势垒层和所述沟道层之间产生2DEG。且所述数字合金势垒层的生长速率远低于所述AlGaN势垒层，因此，通过将所述数字合金势垒和所述AlGaN势垒层组合，在起到防止Mg离子扩散的基础上，有效提高产品的生产效率，降低产品生产成本。所述数字合金势垒层的生长方法在同样的Al的原子数占比下产生的应力极小，避免了在高温大功率工作条件下，应力造成的逆压电效应。
一种实施方式中，所述数字合金势垒层设置在所述掺杂层和所述AlGaN势垒层之间。 也就是说，所述数字合金势垒层相对于所述AlGaN势垒层更加靠近所述掺杂层，由于所述数字合金势垒层为单质或化合物形成的原子层，相比于由混合物形成的所述AlGaN势垒层，所述数字合金势垒层能更有效的阻挡所述掺杂层的Mg离子扩散，因此，将所述数字合金势垒层靠近所述掺杂层设置能更有效防止掺杂层中掺杂的Mg离子在所述复合势垒层和所述沟道层中扩散，避免了导通电阻上升，保证了所述半导体外延结构的电性能。当然，在其他实施例中，所述AlGaN势垒层连接在所述掺杂层和所述数字合金势垒层之间。
一种实施方式中，所述数字合金势垒层为1～10个单周期AlN层/GaN层形成的叠层。也就是说，将AlN层和GaN层周期性排列以形成所述数字合金势垒层，以使所述数字合金势垒层的排列方式更为规则，从而具有更好的防止掺杂层中掺杂的Mg离子在所述复合势垒层和所述沟道层中扩散的作用，避免了导通电阻上升，保证了所述半导体外延结构的电性能。同时，由于所述数字合金势垒层的生长速率相对于所述AlGaN势垒层慢很多，因此，将所述数字合金势垒层限制为1～10个单周期AlN层/GaN层形成的叠层，从而在起到防止Mg离子扩散的基础上，有效提高产品的生产效率，降低产品生产成本。
一种实施方式中，所述数字合金势垒层的厚度为1nm～10nm。在此厚度下，所述数字合金势垒层能更好的与所述AlGaN势垒层结合，保证了所述数字合金势垒层和所述AlGaN势垒层的电性能。同时，所述数字合金势垒层的厚度在1nm～10nm之间，在起到防止Mg离子扩散的基础上，能有效提高产品的生产效率，降低产品生产成本。
一种实施方式中，所述AlGaN势垒层的厚度为2nm～40nm，以避免所述AlGaN势垒层的厚度过厚而产生驰豫现象，而影响所述半导体外延结构的电性能。
一种实施方式中，所述数字合金势垒层中所述单周期AlN层/GaN层中Al的原子数占比为10％～50％。单周期AlN层/GaN层中Al的原子数占比为10％～50％能有效防止Mg离子扩散，同时还能避免所述数字合金势垒层中Al的原子数占比过高而产生漏电现象，保证了半导体外延结构的电性能。
一种实施方式中，所述单周期AlN层/GaN层中AlN层和GaN层的厚度比值为m:n，其中m为小于等于3的正整数，n为小于等于10的正整数。也就是说，本实施例通过控制单周期AlN层/GaN层中AlN层和GaN层的厚度比值，来控制单周期AlN层/GaN层中Al的原子数占比。
一种实施方式中，所述单周期AlN层/GaN层中的AlN层和GaN层的厚度比值1:3，从而能保证所述数字合金势垒层在起到防止Mg离子扩散的基础上，有效提高产品的生产效率，降低产品生产成本。
一种实施方式中，所述数字合金势垒层中Al的原子数占比大于所述AlGaN势垒层中Al的原子数占比。也就是说，靠近所述掺杂层的所述数字合金势垒层中的Al的原子数占比更高，从而起到更好的防止Mg离子扩散的作用。当然，在其他实施例中，所述数字合金势垒层中Al的原子数占比还可以小于或等于所述AlGaN势垒层中Al的原子数占比。
一种实施方式中，所述数字合金势垒层的数量为两层，两层所述数字合金势垒层分别设于所述AlGaN势垒层两侧，所述数字合金势垒层中Al的原子数占比大于所述AlGaN势垒层中Al的原子数占比。也就是说，在所述AlGaN势垒层的两侧均设有具有很好防止Mg离子扩散的所述数字合金势垒层，能有效避免Mg离子扩散到所述AlGaN势垒层中，就算 有少量Mg离子扩散到所述AlGaN势垒层中，还是会被位于另一侧的数字合金势垒层阻挡，从而能避免Mg离子通过所述AlGaN势垒层扩散到所述沟道层中，避免了导通电阻上升，有效保证了所述半导体外延结构的电性能。当然，在其他实施例中，所述数字合金势垒层中Al的原子数占比还可以小于或等于所述AlGaN势垒层中Al的原子数占比。
一种实施方式中，所述半导体外延结构还包括插入层，所述插入层的相对两个表面分别与所述AlGaN势垒层和所述沟道层连接。本实施例中，插入层为AlN层，插入层的禁带宽度更大，增强沟道层的极化效应，可增加2DEG的浓度，同时还具有缓冲应力的作用，即起到缓和所述复合势垒层与沟道层之间晶格失配的作用。
一种实施方式中，所述半导体外延结构还包括衬底层，所述衬底层位于所述沟道层背向所述复合势垒层一侧。本实施例中，所述衬底层的材料为硅。当然，在其他实施例中，所述衬底层也可以用其他衬底材料制成，例如蓝宝石、氮化镓、碳化硅和金刚石等材料。所述衬底层用于承载所述沟道层、所述复合势垒层和所述掺杂层等层结构。
一种实施方式中，所述半导体外延结构还包括缓冲层，所述缓冲层设于所述沟道层背向所述复合势垒层的表面。本实施例中，所述缓冲层的材料为AlGaN。当然，在其他实施例中，所述缓冲层还可以由AlN、GaN等材料构成。所述缓冲层用于缓冲所述沟道层与相关层结构之间的力的作用。
一种实施方式中，所述半导体外延结构还包括成核层，所述成核层所述缓冲层背向所述沟道层的表面。本实施例中，成核层的材料为AlN，起到改善材料间晶格失配带来的应力作用。
本申请所述半导体器件包括上述的半导体外延结构。具有上述半导体外延结构的所述半导体器件能有效避免Mg离子从p-GaN层扩散至势垒层和沟道层导致的导通电阻上升，进而使得所述半导体器件的功率密度提高，具有更好的电学性能。
本申请通过在所述掺杂层和所述沟道层之间设置所述复合势垒层，所述复合势垒层中的所述数字合金势垒层中包括一层或多层AlN层，其为化合物形成的原子层叠层，换言之，本申请通过在所述掺杂层和所述沟道层之间设置包括一层或多层AlN层的所述数字合金势垒层，能有效防止掺杂层中掺杂的Mg离子在所述复合势垒层和所述沟道层中扩散，避免了导通电阻上升，进而保证了所述半导体外延结构的电性能。
附图说明
为了更清楚地说明本申请实施例或背景技术中的技术方案，下面将对本申请实施例或背景技术中所需要使用的附图进行说明。
图1是本申请实施例提供的一种半导体外延结构的结构示意图。
图2是图1提供的半导体外延结构中的数字合金势垒层的结构示意图。
图3是图2提供的数字合金势垒层的具体排列结构示意图。
图4是图1提供的AlGaN势垒层的具体排列结构示意图。
图5是半导体外延结构的另一种结构示意图。
图6是半导体外延结构的又一种结构示意图。
图7是半导体外延结构的又一种结构示意图。
图8是半导体外延结构的再一种结构示意图。
具体实施方式
下面结合本申请实施例中的附图对本申请实施例进行描述。
传统的HEMT多为D-mode结构，即耗尽型HEMT，无p-GaN层，也就是说，耗尽型HEMT的沟道层上设有势垒层，沟道层和势垒层之间通过极化作用产生2DEG，势垒层的设计目的在于提高2DEG密度和迁移率，势垒层主要采用AlGaN势垒层，数字合金由于生长速率低等原因鲜少作为势垒层使用。但商用的HEMT结构必须为E-mode结构，即增强型HEMT，相比于耗尽型HEMT没有危险性，且静态功耗小，其主要实现方式之一是通过在势垒层上增加一层p-GaN来调控阈值电压。也就是说，增强型HEMT包括依次层叠设置的沟道层、势垒层和p-GaN层，p-GaN层通过掺杂Mg离子以形成，其矛盾点在于为了使阈值电压正飘，需要通过提高p-GaN层中的Mg离子浓度来提高空穴浓度，由于势垒层主要采用AlGaN势垒层，但是AlGaN势垒层防止p-GaN层中的Mg离子扩散的效果不好，过高的Mg离子浓度会通过AlGaN势垒层扩散进入沟道层，导致沟道层的方块电阻(Rsheet)和导通电阻(Ron)上升，进而限制HEMT的功率密度，影响HEMT的电学性能。
鉴于此，本申请实施例提供一种半导体器件，解决了由于p-GaN层中的Mg离子扩散而导致的沟道层的方块电阻(Rsheet)和导通电阻(Ron)上升，进而限制HEMT的功率密度，影响HEMT的电学性能的问题，有效防止Mg离子扩散，并采用数字合金势垒和传统AlGaN势垒的复合结构来减少生长时间，降低成本。
半导体器件包括且不限于HEMT和具有产生2DEG的异质结构等电力电子器件及射频器件等半导体器件。本申请以半导体器件是HEMT为例进行具体说明。本申请半导体器件包括半导体外延结构。具有上述半导体外延结构的半导体器件能有效避免Mg离子从p-GaN层扩散至势垒层和沟道层导致的导通电阻上升，进而使得功率密度提高，具有很好的电学性能。
请参阅图1，图1是本申请实施例提供的一种半导体外延结构的结构示意图。图1为半导体外延结构10的第一实施例。
本申请半导体外延结构10包括衬底层11、缓冲层12、沟道层13、复合势垒层14和掺杂层15，掺杂层15设于复合势垒层14上，沟道层13位于复合势垒层14背离掺杂层15一侧，衬底层11位于沟道层13背离复合势垒层14一侧，缓冲层12位于衬底层11和沟道层13之间，复合势垒层14包括层叠设置的数字合金势垒层141和AlGaN势垒层142，数字合金势垒层141内可以包括一层或多层AlN层1411。
本申请的半导体外延结构10通过在掺杂层15和沟道层13之间设置复合势垒层14，复合势垒层14中的数字合金势垒层141内可以包括一层或多层AlN层1411，其为化合物形成的原子层叠层，换言之，本申请通过在掺杂层15和沟道层13之间设置包括一层或多层AlN层1411的数字合金势垒层141，能有效防止掺杂层15中掺杂的Mg离子在复合势垒层14和沟道层13中扩散，避免了导通电阻上升，保证了半导体外延结构10的电性能。同时，数字合金势垒层141还起到等效AlGaN势垒层142的作用，也就是说，数字合金势垒层141和AlGaN势垒层142共同形成复合势垒层14，用于与沟道层13产生极化作用， 以使复合势垒层14和沟道层13之间产生2DEG。且数字合金势垒层141的生长速率远低于AlGaN势垒层142，因此，通过将数字合金势垒层141和AlGaN势垒层142组合，在起到防止Mg离子扩散的基础上，有效提高产品的生产效率，降低产品生产成本。数字合金势垒层141的生长方法在同样的Al的原子数占比下产生的应力极小，避免了在高温大功率工作条件下，应力造成的逆压电效应。
本实施例中，衬底层11的材料为硅。当然，在其他实施例中，衬底层11也可以用其他衬底材料制成，例如蓝宝石、氮化镓、碳化硅和金刚石等材料。衬底层11用于承载缓冲层12、沟道层13、复合势垒层14和掺杂层15等层结构。
缓冲层12设于衬底层11朝向沟道层13的表面，缓冲层12的材料为AlGaN。当然，在其他实施例中，缓冲层12还可以由AlN、GaN等材料构成。缓冲层12的厚度为0.5um～10um之间，缓冲层12用于缓冲衬底层11和沟道层13之间的力的作用。
沟道层13连接于缓冲层12背向衬底层11的表面，沟道层13的材料为GaN。当然，在其他实施例中，沟道层13还可以由AlGaN或InGaN等材料构成。沟道层13的厚度为0.02um～1um之间，沟道层13与复合势垒层14作用形成2DEG。
本实施例中，数字合金势垒层141设置在掺杂层15和AlGaN势垒层142之间，AlGaN势垒层142设于沟道层13背向缓冲层12的表面。也就是说，沟道层13、AlGaN势垒层142、数字合金势垒层141和掺杂层15依次层叠设置，数字合金势垒层141的相对两个表面分别与掺杂层15和AlGaN势垒层142连接，数字合金势垒层141相对于AlGaN势垒层142更加靠近掺杂层15，由于数字合金势垒层141为单质或化合物形成的原子层，相比于由混合物形成的AlGaN势垒层142，数字合金势垒层141能更有效的阻挡掺杂层15的Mg离子扩散，因此，将数字合金势垒层141靠近掺杂层15设置能更有效防止掺杂层15中掺杂的Mg离子在复合势垒层14和沟道层13中扩散，避免了导通电阻上升，保证了半导体外延结构10的电性能。当然，在其他实施例中，AlGaN势垒层142连接在掺杂层15和数字合金势垒层141之间。也就是说，数字合金势垒层141和AlGaN势垒层142的设置位置相换，也能有效防止Mg离子大量扩散到复合势垒层14和沟道层13中，避免了导通电阻上升，保证了半导体外延结构10的电性能。
本实施例中的掺杂层15设于数字合金势垒层141背向AlGaN势垒层142的表面，掺杂层15为GaN材料形成并通过掺杂Mg离子形成的P型掺杂层15。当然，在其他实施例中，掺杂层15朝向数字合金势垒层141的表面与数字合金势垒层141中的GaN层1412层叠。
请参阅图2和图3，图2是图1提供的半导体外延结构中的数字合金势垒层的结构示意图。图3是图2提供的数字合金势垒层的具体排列结构示意图。
具体的，在氮化物材料中，AlN材料的杂质扩散抑制能力远强于GaN。本实施例中，数字合金势垒层141为3个单周期AlN层1411/GaN层1412形成的叠层。可以理解的是，单周期AlN层1411/GaN层1412为一层AlN层1411和一层GaN层1412层叠形成，3个单周期AlN层1411/GaN层1412为一层AlN层1411、一层GaN层、一层AlN层1411、一层GaN层、一层AlN层1411和一层GaN层层叠形成，换言之，3个单周期AlN层1411/GaN层1412为三层AlN层1411和三层GaN层依次交叠形成。数字合金势垒层141中的AlN 层1411与掺杂层15朝向数字合金势垒层141的表面层叠，有利于防止Mg离子的扩散。本实施例将AlN层1411和GaN层1412周期性排列以形成数字合金势垒层141，以使数字合金势垒层141的化合物AlNa和化合物GaNb分别成排规则排列，相比于混合物AlGaN中的化合物AlNa和化合物GaNb的无规则排列方式(请参阅图4)，数字合金势垒层141中的化合物AlNa排列得更加规则，具有更好的防止掺杂层15中掺杂的Mg离子在复合势垒层14和沟道层13中扩散的作用，避免了导通电阻上升，保证了半导体外延结构10的电性能。同时，由于数字合金势垒层141的生长速率相对于AlGaN势垒层142慢很多，也就是说，形成越多个周期AlN层1411/GaN层1412叠层，花费的生产时间越多，因此，将数字合金势垒层141限制为3个单周期AlN层1411/GaN层1412形成的叠层，即数字合金势垒层141足够用于阻挡Mg离子扩散即可，从而在起到防止Mg离子扩散的基础上，有效提高产品的生产效率，降低产品生产成本。当然，在其他实施例中，数字合金势垒层141为1～10个单周期AlN层1411/GaN层1412形成的叠层。或者，数字合金势垒层141中的GaN还可以由其他化合物代替，例如数字合金势垒层141为InN层\AlN层形成的叠层。
本实施例中数字合金势垒层141的厚度为6nm。具体的，在此厚度下，数字合金势垒层141能更好的与AlGaN势垒层142结合，保证了数字合金势垒层141和AlGaN势垒层142的电性能。同时，数字合金势垒层141的厚度为6nm，在起到防止Mg离子扩散的基础上，能有效提高产品的生产效率，降低产品生产成本。当然，在其他实施例中，数字合金势垒层141的厚度可选为1nm～10nm。
数字合金势垒层141中单周期AlN层1411/GaN层1412中Al的原子数占比为25％，也就是说，单周期AlN层1411/GaN层1412中Al的原子数占所有原子的原子数的比例。本实施例中，单周期AlN层1411/GaN层1412中GaN层1412与AlN层1411的单层厚度约为0.5nm，单周期AlN层1411/GaN层1412中的AlN层1411和GaN层1412的厚度比值1:3，三层GaN层1412和一层AlN层1411依次层叠设置，即得到单周期AlN层1411/GaN层1412中Al的原子数占比为25％。当然，单周期AlN层1411/GaN层1412还可以是一层AlN层1411和三层GaN层1412依次层叠设置，或者，一层AlN层1411位于三层GaN层1412中任意两层之间。单周期AlN层1411/GaN层1412中Al的原子数占比为25％能有效防止Mg离子扩散，同时还能避免数字合金势垒层141中Al的原子数占比过高而产生漏电现象，保证了半导体外延结构10的电性能。同时，能保证数字合金势垒层141在起到防止Mg离子扩散的基础上，有效提高产品的生产效率，降低产品生产成本。当然，在其他实施例中，单周期AlN层1411/GaN层1412中Al的原子数占比可选为10％～50％，例如GaN层1412与AlN层1411的单层厚度约为0.5nm，单周期AlN层1411/GaN层1412中AlN层1411和GaN层1412的厚度比值为m:n，其中m为小于等于3的正整数，n为小于等于10的正整数，也就是说，本实施例通过控制单周期AlN层1411/GaN层1412中AlN层1411和GaN层1412的厚度比值，来控制单周期AlN层1411/GaN层1412中Al的原子数占比为10％～50％。能有效防止Mg离子扩散，同时还能避免数字合金势垒层141中Al的原子数占比过高而产生漏电现象，保证了半导体外延结构10的电性能。
如图2所示，AlGaN势垒层142的厚度为2nm～40nm，以避免AlGaN势垒层142的厚度过厚而产生驰豫现象，即AlGaN势垒层142厚度过厚会产生应力作用而产生形变(例 如表面发生弯曲的现象)，从而导致AlGaN势垒层142和与其层叠的层不能很好的贴合，而影响半导体外延结构10的电性能。AlGaN势垒层142中Al的原子数占比为25％。当然，在其他实施例中，AlGaN势垒层142中Al原子数占比还可以为5％～30％，具体可根据数字合金势垒层141中的Al的原子数占比调整，从而使得整个复合势垒层14达到电性能要求。
请参阅图5，图5是半导体外延结构的另一种结构示意图。图5为半导体外延结构10的第二实施例。本实施例中的半导体外延结构10包括衬底层11、缓冲层12、沟道层13、复合势垒层14和掺杂层15，衬底层11、缓冲层12和沟道层13依次层叠设置，复合势垒层14设于沟道层13背离缓冲层12的一侧，掺杂层15设于复合势垒层14背离沟道层13的表面，复合势垒层14包括层叠设置的数字合金势垒层141和AlGaN势垒层142，数字合金势垒层141靠近掺杂层15设置。本实施例中的半导体外延结构10还包括插入层16，插入层16的相对两个表面分别与AlGaN势垒层142和沟道层13连接。本实施例中，插入层16为AlN层，插入层16的禁带宽度(禁带宽度是指一个带隙宽度(单位是电子伏特(ev))，被束缚的电子要成为自由电子或者空穴，就必须获得足够能量从价带跃迁到导带，这个能量的最小值就是禁带宽度。)更大，增强沟道层13的极化效应，可增加2DEG的浓度，同时还具有缓冲应力的作用，即起到缓和复合势垒层14与沟道层13之间晶格失配的作用。当然，在其他实施例中，半导体外延结构10还可以包括成核层17。
请参阅图6，图6是半导体外延结构的又一种结构示意图。图6为半导体外延结构10的第三实施例。本实施例中的半导体外延结构10包括衬底层11、缓冲层12、沟道层13、复合势垒层14和掺杂层15，缓冲层12和沟道层13层叠设置，衬底层设于缓冲层12背向沟道层13的一侧，复合势垒层14设于沟道层13背离缓冲层12的一侧，掺杂层15设于复合势垒层14背离沟道层13的表面，复合势垒层14包括层叠设置的数字合金势垒层141和AlGaN势垒层142，数字合金势垒层141靠近掺杂层15设置，复合势垒层14和沟道层13之间设有插入层16。本实施例中的半导体外延结构10还包括成核层17，成核层17设于衬底层11朝向缓冲层12的表面。本实施例中，成核层17的材料为AlN，起到改善材料间晶格失配带来的应力作用。当然，其他实施例中，复合势垒层14和沟道层13之间未设有插入层16，也就是说，复合势垒层14和沟道层13直接连接。
请参阅图7，图7是半导体外延结构的又一种结构示意图。图7为半导体外延结构10的第四实施例。本实施例中的半导体外延结构10包括依次层叠设置的衬底层11、成核层17、缓冲层12、沟道层13、插入层16、复合势垒层14和掺杂层15，复合势垒层14包括层叠设置的数字合金势垒层141和AlGaN势垒层142，数字合金势垒层141靠近掺杂层15设置。本实施例中的数字合金势垒层141中Al的原子数占比大于AlGaN势垒层142中Al的原子数占比。具体的，数字合金势垒层141中Al的原子数占比和AlGaN势垒层142中Al的原子数占比可根据具体需要设置。也就是说，靠近掺杂层15的数字合金势垒层141中的Al的原子数占比更高，从而起到更好的防止Mg离子扩散的作用。当然，其他实施例中，数字合金势垒层141中Al的原子数占比还可以小于或等于AlGaN势垒层142中Al的原子数占比。半导体外延结构10还可以不设置成核层17和/或插入层16，也就是说，衬底层11、缓冲层12、沟道层13、插入层16、复合势垒层14和掺杂层15依次层叠设置，或者衬底层11、成核层17、缓冲层12、沟道层13、复合势垒层14和掺杂层15依次层叠设 置，或者衬底层11、缓冲层12、沟道层13、复合势垒层14和掺杂层15依次层叠设置。
请参阅图8，图8是半导体外延结构的再一种结构示意图。图8为半导体外延结构10的第五实施例。本实施例中的半导体外延结构10包括依次层叠设置的衬底层11、成核层17、缓冲层12、沟道层13、插入层16、复合势垒层14和掺杂层15，复合势垒层14包括层叠设置的数字合金势垒层141和AlGaN势垒层142，数字合金势垒层141靠近掺杂层15设置。本实施例中的数字合金势垒层141的数量为两层，两层数字合金势垒层141分别设于AlGaN势垒层142两侧，即，在AlGaN势垒层142和插入层16之间新增了一层数字合金势垒层141，数字合金势垒层141中Al的原子数占比大于AlGaN势垒层142中Al的原子数占比。本实施例中的两层数字合金势垒层141的厚度相同或不同，也就是说，在AlGaN势垒层142的两侧均设有具有很好防止Mg离子扩散的数字合金势垒层141，能有效避免Mg离子扩散到AlGaN势垒层142中，就算有少量Mg离子扩散到AlGaN势垒层142中，还是会被位于另一侧的数字合金势垒层141阻挡，从而能避免Mg离子通过AlGaN势垒层142扩散到沟道层13中，避免了导通电阻上升，有效保证了半导体外延结构10的电性能。当然，其他实施例中，数字合金势垒层141中Al的原子数占比还可以小于或等于AlGaN势垒层142中Al的原子数占比。AlGaN势垒层142的数量也可以为两层，分别设于数字合金势垒层141的两侧。半导体外延结构10还可以不设置成核层17和/或插入层16，也就是说，衬底层11、缓冲层12、沟道层13、插入层16、复合势垒层14和掺杂层15依次层叠设置，或者衬底层11、成核层17、缓冲层12、沟道层13、复合势垒层14和掺杂层15依次层叠设置，或者衬底层11、缓冲层12、沟道层13、复合势垒层14和掺杂层15依次层叠设置。
本申请中的保护范围不限于上述实施例一至实施例五，实施例一至实施例五中的任意组合也在本申请的保护范围内，也就是说，上述描述的多个实施例还可根据实际需要任意组合。
本申请通过在掺杂层15和沟道层13之间设置复合势垒层14，复合势垒层14中的数字合金势垒层141中包括一层或多层AlN层1411，其为化合物形成的原子层叠层，换言之，本申请通过在掺杂层15和沟道层13之间设置包括一层或多层AlN层1411的数字合金势垒层141，能有效防止掺杂层15中掺杂的Mg离子在复合势垒层14和沟道层13中扩散，避免了2DEG导通电阻上升，保证了半导体外延结构10的电性能。同时，数字合金势垒层141还起到等效AlGaN势垒层142的作用，也就是说，数字合金势垒层141和AlGaN势垒层142共同形成复合势垒层14，用于与沟道层13产生极化作用，以使复合势垒层14和沟道层13之间产生2DEG。且数字合金势垒层141的生长速率远低于AlGaN势垒层142，因此，通过将数字合金势垒和AlGaN势垒层142组合，在起到防止Mg离子扩散的基础上，有效提高产品的生产效率，降低产品生产成本。数字合金势垒层141的生长方法在同样的Al的原子数占比下产生的应力极小，避免了在高温大功率工作条件下，应力造成的逆压电效应。
以上，仅为本申请的部分实施例和实施方式，本申请的保护范围不局限于此，任何熟知本领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (12)

  1. 一种半导体外延结构，其特征在于，包括沟道层、复合势垒层和掺杂层，所述掺杂层设于所述复合势垒层上，所述沟道层位于所述复合势垒层背离所述掺杂层一侧，所述复合势垒层包括层叠设置的数字合金势垒层和AlGaN势垒层，所述数字合金势垒层中包括一层或多层AlN层。
  2. 根据权利要求1所述的半导体外延结构，其特征在于，所述数字合金势垒层设置在所述掺杂层和所述AlGaN势垒层之间。
  3. 根据权利要求2所述的半导体外延结构，其特征在于，所述数字合金势垒层为1～10个单周期AlN层/GaN层形成的叠层。
  4. 根据权利要求1-3中任意一项权利要求所述的半导体外延结构，其特征在于，所述数字合金势垒层中所述单周期AlN层/GaN层中Al的原子数占比为10％～50％。
  5. 根据权利要求4所述的半导体外延结构，其特征在于，所述单周期AlN层/GaN层中AlN层和GaN层的厚度比值为m:n，其中m为小于等于3的正整数，n为小于等于10的正整数。
  6. 根据权利要求5所述的半导体外延结构，其特征在于，所述数字合金势垒层中Al的原子数占比大于或等于所述AlGaN势垒层中Al的原子数占比。
  7. 根据权利要求5所述的半导体外延结构，其特征在于，所述数字合金势垒层的数量为两层，两层所述数字合金势垒层分别设于所述AlGaN势垒层两侧，所述数字合金势垒层中Al的原子数占比大于或等于所述AlGaN势垒层中Al的原子数占比。
  8. 根据权利要求1所述的半导体外延结构，其特征在于，所述半导体外延结构还包括插入层，所述插入层的相对两个表面分别与所述AlGaN势垒层和所述沟道层连接。
  9. 根据权利要求8所述的半导体外延结构，其特征在于，所述半导体外延结构还包括衬底层，所述衬底层位于所述沟道层背向所述复合势垒层一侧。
  10. 根据权利要求8或9所述的半导体外延结构，其特征在于，所述半导体外延结构还包括缓冲层，所述缓冲层设于所述沟道层背向所述复合势垒层的表面。
  11. 根据权利要求10所述的半导体外延结构，其特征在于，所述半导体外延结构还包括成核层，所述成核层设于所述缓冲层背向所述沟道层的表面。
  12. 一种半导体器件，其特征在于，所述半导体器件包括权利要求1-11任一项所述的半导体外延结构。
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Families Citing this family (4)

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Publication number Priority date Publication date Assignee Title
CN111477536A (zh) * 2020-03-31 2020-07-31 华为技术有限公司 一种半导体外延结构及半导体器件
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CN117293174A (zh) * 2022-06-16 2023-12-26 华为技术有限公司 射频半导体器件、电子设备及射频半导体器件的制备方法
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140264441A1 (en) * 2013-03-15 2014-09-18 Renesas Electronics Corporation Semiconductor device
CN106449914A (zh) * 2016-08-25 2017-02-22 映瑞光电科技(上海)有限公司 一种GaN基发光二极管外延结构及其制备方法
CN108511522A (zh) * 2018-03-16 2018-09-07 英诺赛科（珠海）科技有限公司 p-GaN基增强型HEMT器件
CN109952655A (zh) * 2016-11-23 2019-06-28 三菱电机株式会社 半导体器件和设计半导体器件的方法
CN111477536A (zh) * 2020-03-31 2020-07-31 华为技术有限公司 一种半导体外延结构及半导体器件

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2875338B1 (fr) 2004-09-13 2007-01-05 Picogiga Internat Soc Par Acti Methode d'elaboration de structures hemt piezoelectriques a desordre d'alliage nul
FR2929445B1 (fr) * 2008-03-25 2010-05-21 Picogiga Internat Procede de fabrication d'une couche de nitrure de gallium ou de nitrure de gallium et d'aluminium
JP5782033B2 (ja) 2010-07-29 2015-09-24 日本碍子株式会社 半導体素子用エピタキシャル基板、半導体素子、ｐｎ接合ダイオード素子、および半導体素子用エピタキシャル基板の製造方法
JP2012227227A (ja) * 2011-04-15 2012-11-15 Advanced Power Device Research Association 半導体デバイス
WO2014188715A1 (ja) 2013-05-24 2014-11-27 パナソニックＩｐマネジメント株式会社 半導体装置及びその製造方法
CN103500763B (zh) 2013-10-15 2017-03-15 苏州晶湛半导体有限公司 Ⅲ族氮化物半导体器件及其制造方法
US20160032225A1 (en) * 2014-07-30 2016-02-04 Church & Dwight Co., Inc. Single phase automatic dishwashing detergent composition
JP2016207890A (ja) 2015-04-24 2016-12-08 トヨタ自動車株式会社 ヘテロ接合半導体装置
US9620362B2 (en) * 2015-04-29 2017-04-11 Taiwan Semiconductor Manufacutring Co., Ltd. Seed layer structure for growth of III-V materials on silicon
JP6781095B2 (ja) * 2017-03-31 2020-11-04 エア・ウォーター株式会社 化合物半導体基板
KR20190112523A (ko) * 2018-03-26 2019-10-07 홍익대학교 산학협력단 이종접합 전계효과 트랜지스터 및 그 제조 방법
CN108649071B (zh) * 2018-05-17 2019-03-19 苏州汉骅半导体有限公司 半导体器件及其制造方法
CN109217109B (zh) * 2018-08-29 2020-05-26 中国科学院半导体研究所 基于数字合金势垒的量子阱结构、外延结构及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140264441A1 (en) * 2013-03-15 2014-09-18 Renesas Electronics Corporation Semiconductor device
CN106449914A (zh) * 2016-08-25 2017-02-22 映瑞光电科技(上海)有限公司 一种GaN基发光二极管外延结构及其制备方法
CN109952655A (zh) * 2016-11-23 2019-06-28 三菱电机株式会社 半导体器件和设计半导体器件的方法
CN108511522A (zh) * 2018-03-16 2018-09-07 英诺赛科（珠海）科技有限公司 p-GaN基增强型HEMT器件
CN111477536A (zh) * 2020-03-31 2020-07-31 华为技术有限公司 一种半导体外延结构及半导体器件

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4113580A4

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