WO2021200874A1 - 接合体、および、絶縁回路基板 - Google Patents
接合体、および、絶縁回路基板 Download PDFInfo
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- WO2021200874A1 WO2021200874A1 PCT/JP2021/013405 JP2021013405W WO2021200874A1 WO 2021200874 A1 WO2021200874 A1 WO 2021200874A1 JP 2021013405 W JP2021013405 W JP 2021013405W WO 2021200874 A1 WO2021200874 A1 WO 2021200874A1
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- insulating resin
- circuit layer
- layer
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- insulating
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0284—Details of three-dimensional rigid printed circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
- H05K3/384—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by plating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
- H10W70/652—Cross-sectional shapes
- H10W70/6525—Cross-sectional shapes for securing the interconnections to the substrate, e.g. to prevent peeling
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/6875—Shapes or dispositions thereof being on a metallic substrate, e.g. insulated metal substrates [IMS]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/06—Lamination
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
- H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/20—Arrangements for cooling
- H10W40/25—Arrangements for cooling characterised by their materials
- H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
Definitions
- the present invention relates to a bonded body having a structure in which an insulating resin member made of an insulating resin and a metal member are joined, and an insulating circuit board.
- the present application claims priority under Japanese Patent Application No. 2020-200641 filed in Japan on March 30, 2020, and Japanese Patent Application No. 2020-161017 filed in Japan on September 25, 2020. , The contents are used here.
- the power module, LED module, and thermoelectric module have a structure in which a power semiconductor element, an LED element, and a thermoelectric element are bonded to an insulating circuit substrate in which a circuit layer made of a conductive material is formed on one surface of the insulating layer. ..
- a circuit layer made of a conductive material is formed on one surface of the insulating layer.
- insulating layer one using ceramics or one using an insulating resin has been proposed.
- Patent Document 1 proposes a metal-based circuit board.
- Patent Document 2 proposes a multilayer wiring board.
- an insulating resin layer is formed on the metal substrate, and a circuit layer having a circuit pattern is formed on the insulating resin layer.
- the insulating resin layer is made of an epoxy resin which is a thermosetting resin
- the circuit layer is made of a copper foil.
- a semiconductor element is bonded on the circuit layer, and a heat sink is arranged on the surface of the metal substrate opposite to the insulating resin layer, and heat generated by the semiconductor element is transferred to the heat sink side. It has a structure that dissipates heat.
- the surface roughness (Ra) of the metal foil is set to 0.2 ⁇ m or more by etching the metal foil adhered to the resin film, and further, the circuit pattern is formed.
- the wiring circuit layer is formed by etching, and the wiring circuit layer formed on the surface of the resin film is embedded while applying pressure to the surface of the soft insulating sheet, and the insulating circuit layer is transferred to the surface of the insulating sheet. , It is manufactured by laminating a plurality of insulating sheets thus obtained and heat-curing them all at once.
- the surface roughness (Ra) of the wiring circuit layer is set to 0.2 ⁇ m or more and embedded in the insulating sheet to improve the adhesion between the insulating sheet and the wiring circuit layer.
- the surface roughness (Ra) of the metal plate (wiring circuit layer) is too large, electric charges are concentrated on the portion where the surface of the metal plate has entered, and the insulating property (insulation withstand voltage) of the insulating resin layer is lowered. There was a risk that it could not be used as an insulated circuit board.
- the present invention has been made in view of the above-mentioned circumstances, and has excellent adhesion between the insulating resin member and the metal member, and also has excellent insulating properties in the insulating resin member, and can be used stably. It is an object of the present invention to provide a joint and an insulated circuit board.
- the joint body of the present invention is a joint body having a structure in which an insulating resin member made of an insulating resin and a metal member made of a metal are joined, and the insulating resin member and the metal member are joined.
- the interface between the metal member and the metal member has a concavo-convex shape having a convex portion in which the metal member protrudes toward the insulating resin member and a concave portion in which the metal member recedes from the insulating resin member side.
- At least one of the contour curve Kurtosis Rku at the interface and the contour curved surface Kurtosis Sku at the joint interface of the metal member is within the range of 2.75 or more and 6.00 or less, and the stacking direction in the direction along the joint interface.
- the overhang rate, which indicates the length ratio of the overlapping regions, is 7% or more.
- the bonding interface between the insulating resin member and the metal member is such that the convex portion of the metal member protruding toward the insulating resin member and the metal member retracting from the insulating resin member side. It has a concavo-convex shape with recesses, and at least one of the contour curve Kurtosis Rku at the joint interface of the metal member and the contour curved surface Kurtosis Sku at the joint interface of the metal member is 2.75 or more and 6.00. Since it is within the following range, the tip of the convex portion is not sharpened more than necessary, and the insulating property (insulation withstand voltage) of the insulating resin member can be sufficiently ensured.
- the metal member and the insulating resin member are sufficiently engaged. , The adhesion between the insulating resin member and the metal member can be improved.
- At least one of the root mean square square root height Rq of the contour curve at the joining interface of the metal member and the root mean square square root height Sq of the contour curved surface at the joining interface of the metal member is at least one. , 0.20 ⁇ m or more and 0.90 ⁇ m or less is preferable.
- at least one of the root mean square square root height Rq of the contour curve at the joint interface of the metal member and the root mean square square root height Sq of the contour curved surface at the joint interface of the metal member is 0.20 ⁇ m or more and 0.90 ⁇ m.
- the occurrence of electric field concentration at the tip of the convex portion can be suppressed, the insulating property can be reliably ensured, and the adhesion between the insulating resin member and the metal member can be ensured. Can be improved.
- the insulating circuit board of the present invention is an insulating circuit board including an insulating resin layer and a circuit layer in which a metal plate is bonded to one surface of the insulating resin layer, and the insulating resin layer and the circuit layer.
- the bonding interface with the circuit layer has a concavo-convex shape having a convex portion in which the circuit layer protrudes toward the insulating resin layer side and a concave portion in which the circuit layer recedes from the insulating resin layer side.
- At least one of the contour curve Kurtosis Rku at the interface and the contour curved surface Kurtosis Sku at the junction interface of the circuit layer is within the range of 2.75 or more and 6.00 or less, and the stacking direction in the direction along the junction interface. It is characterized in that the overhang rate indicating the length ratio of the overlapping region is 7% or more.
- the bonding interface between the insulating resin layer and the circuit layer is such that the convex portion of the circuit layer protruding toward the insulating resin layer and the circuit layer retracting from the insulating resin layer side. 2. Since it is within the range of 00 or less, the tip of the convex portion is not sharpened more than necessary, and the insulating property (insulation withstand voltage) in the insulating resin portion layer can be sufficiently ensured. Since the overhang rate indicating the length ratio of the regions overlapping in the stacking direction in the direction along the bonding interface is 7% or more, the circuit layer and the insulating resin layer are sufficiently engaged. , The adhesion between the circuit layer and the insulating resin layer can be improved.
- At least one of the root mean square Rq of the contour curve at the junction interface of the circuit layer and the root mean square Sq of the contour curved surface at the junction interface of the circuit layer is in the range of 0.20 ⁇ m or more and 0.90 ⁇ m or less.
- at least one of the root mean square Rq of the contour curve at the junction interface of the circuit layer and the root mean square Sq of the contour curved surface at the junction interface of the circuit layer is 0.20 ⁇ m or more and 0.90 ⁇ m.
- the occurrence of electric field concentration at the tip of the convex portion can be suppressed, the insulating property can be reliably ensured, and the adhesion between the insulating resin layer and the circuit layer can be ensured. Can be improved.
- a joint and an insulating circuit board which are excellent in adhesion between an insulating resin member and a metal member, are excellent in insulating properties in the insulating resin member, and can be used stably. It becomes possible.
- the bonded body according to the present embodiment is an insulating circuit board 10 formed by joining an insulating resin layer 12 which is an insulating resin member, a metal plate 23 (circuit layer 13) which is a metal member, and a metal substrate 11. It is said that.
- FIG. 1 shows an insulated circuit board 10 according to an embodiment of the present invention and a power module 1 using the insulated circuit board 10.
- the power module 1 shown in FIG. 1 includes an insulating circuit board 10, a semiconductor element 3 bonded to one surface (upper surface in FIG. 1) of the insulating circuit board 10 via a first solder layer 2, and an insulating circuit board.
- a heat sink 31 joined via a solder layer 32 is provided on the other side (lower side in FIG. 1) of the 10.
- the semiconductor element 3 is made of a semiconductor material such as Si.
- the first solder layer 2 that joins the insulating circuit board 10 and the semiconductor element 3 is, for example, a Sn-Ag-based, Sn-Cu-based, Sn-In-based, or Sn-Ag-Cu-based solder material (so-called lead-free solder). Material).
- the heat sink 31 is for dissipating heat on the insulating circuit board 10 side.
- the heat sink 31 is made of copper or a copper alloy, aluminum, an aluminum alloy, or the like having good thermal conductivity. In the present embodiment, the heat sink is made of oxygen-free copper.
- the thickness of the heat sink 31 is set within the range of 3 mm or more and 10 mm or less.
- the insulating circuit board 10 and the heat sink 31 are joined via the solder layer 32.
- the solder layer 32 can have the same structure as the solder layer 2 described above.
- the insulating circuit board 10 of the present embodiment includes a metal substrate 11, an insulating resin layer 12 formed on one surface (upper surface in FIG. 1) of the metal substrate 11, and an insulating resin.
- a circuit layer 13 formed on one surface (upper surface in FIG. 1) of the layer 12 is provided.
- the metal substrate 11 has an effect of improving heat dissipation characteristics by spreading the heat generated in the semiconductor element 3 mounted on the insulating circuit substrate 10 in the plane direction. Therefore, the metal substrate 11 is made of a metal having excellent thermal conductivity, for example, copper or a copper alloy, aluminum or an aluminum alloy. In this embodiment, it is composed of a rolled plate of oxygen-free copper.
- the thickness of the metal substrate 11 is set within the range of 0.05 mm or more and 3 mm or less, and is set to 2.0 mm in the present embodiment.
- the insulating resin layer 12 prevents electrical connection between the circuit layer 13 and the metal substrate 11, and is made of a thermosetting resin having an insulating property.
- a thermosetting resin containing a filler is used in order to secure the strength of the insulating resin layer 12 and the thermal conductivity.
- the filler for example, alumina, boron nitride, aluminum nitride and the like can be used.
- the thermosetting resin an epoxy resin, a polyimide resin, or the like can be used.
- the insulating resin layer 12 is made of an epoxy resin containing alumina as a filler.
- the thickness of the insulating resin layer 12 is in the range of 20 ⁇ m or more and 250 ⁇ m or less, and in the present embodiment, it is 150 ⁇ m.
- the circuit layer 13 is formed by joining a metal plate 23 made of a metal having excellent conductivity to one surface (upper surface in FIG. 4) of the insulating resin layer 12.
- a metal plate 23 made of a metal having excellent conductivity to one surface (upper surface in FIG. 4) of the insulating resin layer 12.
- a rolled plate such as copper or a copper alloy, aluminum or an aluminum alloy can be used.
- an oxygen-free copper rolled plate is used as the metal plate 23 constituting the circuit layer 13.
- a circuit pattern is formed, and one surface (upper surface in FIG. 1) is a mounting surface on which the semiconductor element 3 is mounted.
- the thickness of the circuit layer 13 (metal plate 23) is set within the range of 0.3 mm or more and 3 mm or less, and is set to 0.5 mm in the present embodiment.
- the circuit layer 13 protrudes toward the insulating resin layer 12 at the bonding interface between the insulating resin layer 12 and the circuit layer 13 (metal substrate 11).
- the convex portion 18 and the circuit layer 13 (metal substrate 11) have a concave-convex shape having a concave portion 19 recessed from the insulating resin layer 12 side. That is, in the present embodiment, the circuit layer 13 (metal substrate 11) is embedded in the insulating resin layer 12.
- At least one of the contour curve Kurtosis Rku at the junction interface of the circuit layer 13 (metal substrate 11) and the contour curved surface Kurtosis Sku at the junction interface of the circuit layer 13 (metal substrate 11) is 2. It is within the range of .75 or more and 6.00 or less.
- the overhang rate which indicates the length ratio of the regions overlapping in the stacking direction in the direction along the bonding interface, is 7% or more.
- the overhang rate which indicates the length ratio of the overlapping regions in the stacking direction in the direction along the bonding interface, the root mean square height Rq of the contour curve at the bonding interface of the circuit layer 13 (metal substrate 11), and the circuit layer 13 (metal).
- the contour curve Kurtosis Rku is a parameter defined in JIS B 0601: 2001
- the contour curved surface Kurtosis Sku is a parameter defined in JIS B 0681-2: 2018, and is a measure of surface sharpness. It is an evaluation of the degree.
- the contour curved surface Kurtosis Sku is a parameter obtained by extending the contour curve Kurtosis Rku in three dimensions.
- both the contour curve Kurtosis Rku and the contour curved surface Kurtosis Sku at the junction interface of the circuit layer 13 (metal substrate 11) are less than 2.75, the surface of the circuit layer 13 (the tip of the convex portion 18) becomes It has a crushed shape, and the circuit layer 13 (metal substrate 11) does not sufficiently enter the insulating resin layer 12, and the adhesion between the insulating resin layer 12 and the circuit layer 13 (metal substrate 11) can be improved. It may not be possible.
- At least one of the contour curve Kurtosis Rku and the contour curved surface Kurtsis Sku at the junction interface of the circuit layer 13 (metal substrate 11) is set within the range of 2.75 or more and 6.00 or less. ing.
- At least one of the contour curve Kurtosis Rku and the contour curved surface Kurtosis Sku at the bonding interface of the circuit layer 13 (metal substrate 11) is preferably 2.75 or more, and more preferably 3.00 or more. ..
- at least one of the contour curve Kurtosis Rku and the contour curved surface Kurtosis Sku at the bonding interface of the circuit layer 13 (metal substrate 11) is preferably 6.00 or less, and more preferably 3.75 or less. ..
- the overhang ratio is determined by image-analyzing the cross-sectional shape of the joint interface with image processing software, and for the obtained cross-sectional curve in the stacking direction (height direction: X direction) in the direction along the joint interface (horizontal direction: X direction).
- the region overlapping in the Y direction was defined as the overhang portion, and the ratio of the length of the overhang portion in the X direction to the total length of the obtained cross-sectional curve in the X direction was defined.
- the overhang rate may be 100% or more.
- the overhang rate indicating the length ratio of the regions overlapping in the stacking direction in the direction along the bonding interface is defined as 7% or more.
- the overhang rate described above is preferably 7% or more, and more preferably 15% or more.
- the overhang rate is not particularly limited, but is preferably 100% or less.
- Root mean square height Rq of the contour curve at the junction interface and root mean square Sq of the contour surface The root mean square height Rq of the contour curve is a parameter specified in JIS B 0601: 2001, and the root mean square height Sq of the contour curved surface is a parameter specified in JIS B 0681-2: 2018. It means the standard deviation of the surface roughness.
- At least one of the root mean square Rq of the contour curve and the root mean square height Sq of the contour curved surface at the junction interface of the circuit layer 13 (metal substrate 11) is set to 0.20 ⁇ m or more.
- the insulating resin layer 12 It is possible to suppress the generation of electric field concentration at the tip of the convex portion 18 made of the circuit layer 13 (metal substrate 11) that has entered the inside of the circuit board, and it is possible to reliably secure the insulating property of the insulating resin layer 12.
- At least one of the root mean square Rq of the contour curve and the root mean square height Sq of the contour curved surface at the junction interface of the circuit layer 13 (metal substrate 11) is set to 0. It is preferably within the range of .20 ⁇ m or more and 0.90 ⁇ m or less. At least one of the root mean square height Rq of the contour curve and the root mean square height Sq of the contour curved surface at the junction interface of the circuit layer 13 (metal substrate 11) is preferably 0.20 ⁇ m or more, and 0. It is more preferably 30 ⁇ m or more.
- At least one of the root mean square height Rq of the contour curve and the root mean square height Sq of the contour curved surface at the junction interface of the circuit layer 13 (metal substrate 11) is preferably 0.90 ⁇ m or less. It is more preferably 80 ⁇ m or less.
- the roughened plating layer 23a is formed on the joint surface of the metal plate 23 serving as the circuit layer 13 with the insulating resin layer 12, and the roughened plating layer 11a is formed on the joint surface of the metal substrate 11 with the insulating resin layer 12. do.
- uneven portions are formed on the joint surface of the metal plate 23 serving as the circuit layer 13 with the insulating resin layer 12 and the joint surface of the metal substrate 11 with the insulating resin layer 12.
- the roughened plating layers 23a and 11a are formed as follows.
- Electroplating is applied to the joint surfaces of the metal plate 23 and the metal substrate 11.
- 3,3'-dithiobis (1-propanesulfonic acid) 2 sodium is added to a copper sulfate bath containing copper sulfate (CuSO 4 ) and sulfuric acid (H 2 SO 4 ) as main components as an electrolytic plating solution. It is preferable to use an electrolytic solution composed of the aqueous solution. Further, the temperature of the plating bath is preferably in the range of, for example, 25 ° C. or higher and 35 ° C. or lower.
- a PR (Periodic Reverse) pulse plating treatment is used as the electrolytic plating treatment.
- This PR pulse plating process is a method of performing electrolytic plating by energizing while periodically reversing the direction of electric current.
- 1A / dm 2 or more and 30A / dm 2 or less positive electrode is 1ms or more and 1000ms or less
- Negative electrode electrolysis with the metal plate 23 and the metal substrate 11 as the negative electrodes is set to 1 ms or more and 1000 ms or less, and this is repeated. As a result, the melting of the surfaces of the metal plate 23 and the metal substrate 11 and the precipitation of copper are repeatedly carried out, and the roughened plating layers 23a and 11a are formed.
- the surface texture of the metal plate 23 and the metal substrate 11 before forming the roughened plating layers 23a and 11a, and various plating conditions (pulse application time, pulse waveform (precipitation amount / dissolution amount ratio), pulse frequency). Adjusts the root mean square Rku of the contour curve and the root mean square Sq of the contour curve, the overhang rate, the root mean square height Rq of the contour curve, and the root mean square height Sq of the contour curve at the joint surface of the metal plate 23 and the metal substrate 11. It becomes possible to do.
- the contour curve Kurtosis Rku and the contour curved surface Kurtosis Sku are close to 3, the overhang rate increases, and the root mean square height Rq of the contour curve and the root mean square height of the contour surface are increased. Sq increases.
- the precipitation / dissolution ratio is increased as a pulse waveform, the Kurtosis Rku of the contour curve and the Kurtosis Sku of the contour curved surface increase, the overhang rate decreases, and the root mean square height Rq of the contour curve and the contour curved surface The root mean square height Sq decreases.
- FIG. 3A shows a cross-sectional photograph of the metal plate 23 (metal substrate 11) before the surface roughening step S01 is carried out
- FIG. 3B shows a cross-sectional photograph of the metal plate 23 after the surface roughening step S01 is carried out.
- a cross-sectional photograph of (metal substrate 11) is shown.
- a resin composition 22 containing alumina as a filler, an epoxy resin as a thermosetting resin, and a curing agent is disposed on one surface (upper surface in FIG. 4) of the metal substrate 11.
- the resin composition 22 is formed in a sheet shape.
- a metal plate 23 to be a circuit layer 13 is arranged on one surface (upper surface in FIG. 4) of the resin composition 22.
- thermocompression bonding step S03 Next, the laminated metal substrate 11, the resin composition 22, and the metal plate 23 are pressurized and pressed in the laminating direction to cure the resin composition 22 to form the insulating resin layer 12, and the metal substrate 11 and the metal substrate 11.
- the insulating resin layer 12, the insulating resin layer 12 and the metal plate 23 are joined.
- the conditions of this thermocompression bonding step S03 are that the heating temperature is within the range of 150 ° C. or higher and 400 ° C. or lower, the holding time at the heating temperature is within the range of 30 minutes or more and 90 minutes or less, and the pressurizing pressure in the stacking direction is 1 MPa or more and 100 MPa or less. It is preferable that the temperature is within the range of.
- circuit pattern forming step S04 Next, the metal plate 23 bonded to the insulating resin layer 12 is etched to form a circuit pattern to form the circuit layer 13.
- the insulated circuit board 10 according to the present embodiment is manufactured.
- Heat sink joining step S05 Next, the heat sink 31 is joined to the other surface of the metal substrate 11 of the insulating circuit board 10.
- the metal substrate 11 and the heat sink 31 are joined via a solder material.
- semiconductor element joining step S06 the semiconductor element 3 is bonded to the circuit layer 13 of the insulating circuit board 10.
- the circuit layer 13 and the semiconductor element 3 are joined via a solder material.
- the circuit layer 13 (metal) is formed at the bonding interface between the insulating resin layer 12 and the circuit layer 13 (metal substrate 11).
- the substrate 11) has a convex portion 18 protruding toward the insulating resin layer 12, and the circuit layer 13 (metal substrate 11) has a concave portion 19 recessed from the insulating resin layer 12 side, and has a concave-convex shape.
- the circuit layer 13 (metal substrate 11) sufficiently penetrates into the insulating resin layer 12 side. , It is possible to improve the adhesion between the insulating resin layer 12 and the circuit layer 13 (metal substrate 11). Further, since at least one of the contour curve Kurtosis Rku and the contour curved surface Kurtosis Sku at the junction interface of the circuit layer 13 (metal substrate 11) is set to 6.00 or less, the tip of the convex portion 18 is sharpened more than necessary. Therefore, sufficient insulation (insulation withstand voltage) in the insulating resin portion layer can be ensured.
- the circuit layer 13 (metal substrate 11) and the insulating resin layer 12 are sufficient. It is possible to improve the adhesion between the circuit layer 13 (metal substrate 11) and the insulating resin layer 12.
- the root mean square height Rq of the contour curve and the root mean square height Sq of the contour curved surface at the joining interface of the circuit layer 13 (metal substrate 11) When at least one of them is within the range of 0.20 ⁇ m or more and 0.90 ⁇ m or less, the occurrence of electric field concentration at the tip of the convex portion 18 can be suppressed, and the insulating property of the insulating resin layer 12 can be reliably ensured. At the same time, the adhesion between the circuit layer 13 (metal substrate 11) and the insulating resin layer 12 can be reliably improved.
- the present invention is not limited to this, and can be appropriately changed without departing from the technical idea of the invention.
- the insulated circuit board is manufactured by the method for manufacturing the insulated circuit board shown in FIGS. 2 to 4, but the present embodiment is not limited thereto.
- the metal plate forming the metal substrate and the circuit layer has been described as being composed of oxygen-free copper, but the present invention is not limited to this, and the metal plate is composed of other copper or a copper alloy. It may be made of copper or it may be made of other metals such as aluminum or an aluminum alloy. Further, it may have a structure in which a plurality of metals are laminated.
- thermoelectric element is mounted on the circuit layer of the insulated circuit board to form a thermoelectric module.
- a metal substrate (40 mm ⁇ 40 mm ⁇ thickness 2 mm) made of rolled oxygen-free copper and a metal plate (40 mm ⁇ 40 mm ⁇ thickness 0.5 mm) to be a circuit layer are prepared, and the insulating resin of these metal substrates and the metal plate.
- a roughened plating layer was formed on the joint surface with the layer by the PR pulse electrolysis method described in the above-described embodiment.
- a sheet material (40 mm ⁇ 40 mm ⁇ thickness 0.15 mm) of a resin composition containing an epoxy resin containing Al 2 O 3 as a filler was placed on the surface of the metal substrate on which the roughened plating layer was formed. Further, a metal plate to be a circuit layer was laminated on one surface of the sheet material of the resin composition so that the surface on which the roughened plating layer was formed faces the sheet material side of the resin composition.
- the metal substrate laminated as described above, the sheet material of the resin composition, and the metal plate are heated while being pressurized in the lamination direction to cure the resin composition to form an insulating resin layer, and the metal substrate and the insulating resin.
- the layer and the insulating resin layer were joined to a metal plate to obtain an insulated circuit substrate.
- the pressurizing pressure in the stacking direction was 10 MPa, the heating temperature was 180 ° C., and the holding time at the heating temperature was 60 minutes.
- the obtained insulated circuit boards were evaluated for the following items.
- the junction interface between the circuit layer and the insulating resin layer is observed using a laser microscope OLS5000 with an objective lens of 100 times in a measurement range of 129 ⁇ m ⁇ 129 ⁇ m, and processing is performed to remove sample inclination and noise, and the contour curved surface at the junction interface is performed. Kurtosis Sku and the root mean square height Sq of the contour curved surface were calculated. Next, the Kurtosis Rku of the contour polarity at the junction interface and the root mean square height Rq of the contour curved surface were calculated in the direction in which the roughness was considered to be the coarsest. At least three points were measured within the measurement range, and the average value was shown in the table.
- This SIM image was binarized using image analysis software ImageJ to manually remove noise, and then outline extraction was performed.
- FIG. 5 A measurement example is shown in FIG. In the cross-sectional curve shown in FIG. 5, the number of overlapping regions in the Y direction for each X-axis position is 0,1,1,0,0,0,0,0,1,1,2,2 in order from the left. , 1, 1, 0, the total of these is 10, and the number of pixels in the X direction is 15, so the overhang rate is 10/15 ⁇ 100, which is 67%.
- the above-mentioned insulating circuit board was placed in a constant temperature and humidity chamber (temperature 85 ° C., humidity 85%) and held for 3 days. Then, it was charged into a heating furnace and reflowed at 290 ° C. for 10 minutes.
- the bonding ratio between the circuit layer and the insulating resin layer and the dielectric breakdown voltage were evaluated as follows.
- the metal substrate 11 was placed on the base plate 61, the probe 62 was brought into contact with the circuit layer 13, and the partial discharge was evaluated.
- a partial discharge tester manufactured by Mitsubishi Electric Wire Co., Ltd. was used as the measuring device.
- As a test atmosphere it was carried out in Fluorinert (tm) FC-770 manufactured by 3M. Then, the voltage was boosted by a step profile (holding time 30 seconds) every 0.5 kV, and the voltage at which dielectric breakdown occurred (voltage at which the leakage current was 10 mA or more) was defined as the dielectric breakdown voltage.
- the evaluation results are shown in Table 1.
- At least one of the contour curve Kurtosis Rku and the contour curved surface Kurtosis Sku at the junction interface of the circuit layer is within the range of 2.75 or more and 6.00 or less, and the overhang rate is 7% or more.
- the bonding ratio after the moisture absorption reflow was 84% or more, and the adhesion between the circuit layer and the insulating resin layer was excellent.
- the dielectric breakdown voltage after the moisture absorption reflow was 5.8 V or more, and the insulating resin layer was excellent in insulating properties.
- Example 1-8 of the present invention at least one of the root mean square height Rq of the contour curve and the root mean square height Sq of the contour curved surface at the junction interface of the circuit layer is within the range of 0.20 ⁇ m or more and 0.90 ⁇ m or less. Met. Further, in Example 1-8 of the present invention, since both the Kurtosis Rku of the contour curve and the Kurtosis Sku of the contour curved surface at the junction interface of the circuit layer were in the range of 2.75 or more and 6.00 or less, the circuit layer and the insulating resin. The adhesion with the layer was particularly excellent.
- Example 1-6 of the present invention in which both the root mean square height Rq of the contour curve and the root mean square height Sq of the contour curved surface at the junction interface of the circuit layer are within the range of 0.20 ⁇ m or more and 0.90 ⁇ m or less.
- the bonding ratio after the moisture absorption reflow was 85% or more, and the adhesion between the circuit layer and the insulating resin layer was particularly excellent.
- the adhesion between the insulating resin layer (insulating resin member) and the circuit layer (metal member) is excellent, and the insulating property of the insulating resin layer (insulating resin member) is excellent. It was confirmed that it is possible to provide an insulated circuit board (joint) that can be used stably.
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Abstract
Description
本願は、2020年3月30日に、日本に出願された特願2020-060041号、および2020年9月25日に、日本に出願された特願2020-161017号に基づき優先権を主張し、その内容をここに援用する。
ここで、絶縁樹脂層を備えた絶縁回路基板として、例えば特許文献1には、金属ベース回路基板が提案されている。また、特許文献2には、多層配線基板が提案されている。
この金属ベース回路基板においては、回路層上に半導体素子が接合され、金属基板の絶縁樹脂層とは反対側の面にヒートシンクが配設されており、半導体素子で発生した熱をヒートシンク側に伝達して放熱する構造とされている。
ここで、特許文献1に記載された金属ベース回路基板においては、絶縁樹脂層と回路層との密着性を向上させることは考慮されておらず、使用時に絶縁樹脂層と回路層(金属板)の剥離が生じるおそれがあった。
しかしながら、金属板(配線回路層)の表面粗さ(Ra)が大きすぎると、金属板表面が入り込んだ部分に電荷が集中し、絶縁樹脂層における絶縁性(絶縁耐圧)が低下してしまい、絶縁回路基板として使用できなくなるおそれがあった。
そして、前記接合界面に沿った方向における積層方向に重複する領域の長さ割合を示すオーバーハング率が7%以上とされているので、金属部材と絶縁樹脂部材とが十分に係合しており、絶縁樹脂部材と金属部材との密着性を向上させることができる。
この場合、前記金属部材の前記接合界面における輪郭曲線の二乗平均平方根高さRqおよび前記金属部材の前記接合界面における輪郭曲面の二乗平均平方根高さSqの少なくとも一方が、0.20μm以上0.90μm以下の範囲内とされているので、前記凸部の先端における電界集中の発生を抑制でき、絶縁性を確実に確保することができるとともに、前記絶縁樹脂部材と前記金属部材との密着性を確実に向上させることができる。
そして、前記接合界面に沿った方向における積層方向に重複する領域の長さ割合を示すオーバーハング率が7%以上とされているので、回路層と絶縁樹脂層とが十分に係合しており、回路層と絶縁樹脂層との密着性を向上させることができる。
この場合、前記回路層の前記接合界面における輪郭曲線の二乗平均平方根高さRqおよび前記回路層の前記接合界面における輪郭曲面の二乗平均平方根高さSqの少なくとも一方が、0.20μm以上0.90μm以下の範囲内とされているので、前記凸部の先端における電界集中の発生を抑制でき、絶縁性を確実に確保することができるとともに、前記絶縁樹脂層と前記回路層との密着性を確実に向上させることができる。
本実施形態に係る接合体は、絶縁樹脂部材である絶縁樹脂層12と、金属部材である金属板23(回路層13)および金属基板11とが接合されることにより構成された絶縁回路基板10とされている。
図1に、本発明の実施形態である絶縁回路基板10およびこの絶縁回路基板10を用いたパワーモジュール1を示す。
ここで、絶縁回路基板10とヒートシンク31とは、はんだ層32を介して接合されている。このはんだ層32は、上述のはんだ層2と同様の構成とすることができる。
本実施形態では、絶縁樹脂層12の強度を確保するとともに、熱伝導性を確保するために、フィラーを含有する熱硬化型樹脂が用いられている。ここで、フィラーとしては、例えばアルミナ、窒化ホウ素、窒化アルミニウム等を用いることができる。また、熱硬化型樹脂としては、エポキシ樹脂やポリイミド樹脂等を用いることができる。本実施形態では、絶縁樹脂層12は、フィラーとしてアルミナを含有するエポキシ樹脂で構成されている。また、絶縁樹脂層12の厚さは、20μm以上250μm以下の範囲内とされており、本実施形態では、150μmとされている。
この回路層13においては、回路パターンが形成されており、その一方の面(図1において上面)が、半導体素子3が搭載される搭載面とされている。ここで、回路層13(金属板23)の厚さは0.3mm以上3mm以下の範囲内に設定されており、本実施形態では0.5mmに設定されている。
すなわち、本実施形態においては、絶縁樹脂層12に回路層13(金属基板11)が入り込んだ構造とされている。
そして、接合界面に沿った方向における積層方向に重複する領域の長さ割合を示すオーバーハング率が7%以上とされている。
なお、本実施形態においては、回路層13(金属基板11)の接合界面における輪郭曲線の二乗平均平方根高さRqおよび回路層13(金属基板11)の接合界面における輪郭曲面の二乗平均平方根高さSqの少なくとも一方が、0.20μm以上0.90μm以下の範囲内とされていることが好ましい。
輪郭曲線のクルトシスRkuは、JIS B 0601:2001に規定されたパラメータであり、輪郭曲面のクルトシスSkuは、JIS B 0681-2:2018に規定されたパラメータであり、表面の鋭さの尺度である尖度を評価したものである。
輪郭曲線のクルトシスRkuは、正規分布の形状でRku=3となり、正規分布よりも高さ分布が尖っている場合にはRku>3となり、高さ分布が正規分布よりもつぶれている場合にはRku<3となる。
また、輪郭曲面のクルトシスSkuは、輪郭曲線のクルトシスRkuを3次元に拡張したパラメータである。
このため、本実施形態においては、回路層13(金属基板11)の接合界面における輪郭曲線のクルトシスRkuおよび輪郭曲面のクルトシスSkuの少なくとも一方を2.75以上6.00以下の範囲内に設定している。
なお、回路層13(金属基板11)の接合界面における輪郭曲線のクルトシスRkuおよび輪郭曲面のクルトシスSkuの少なくとも一方は、2.75以上とすることが好ましく、3.00以上とすることがさらに好ましい。一方、回路層13(金属基板11)の接合界面における輪郭曲線のクルトシスRkuおよび輪郭曲面のクルトシスSkuの少なくとも一方は、6.00以下とすることが好ましく、3.75以下とすることがさらに好ましい。
本実施形態においてオーバーハング率は、接合界面の断面形状を画像処理ソフトで画像解析し、得られた断面曲線について接合界面に沿った方向(水平方向:X方向)において積層方向(高さ方向:Y方向)に重複する領域をオーバーハング部とし、得られた断面曲線のX方向の全長さに対するオーバーハング部のX方向長さの割合とした。
なお、オーバーハング部をX方向に長さをカウントする場合、例えば、Y方向にオーバーハング部がない場合は0、Y方向にオーバーハング部が1つある場合は1、Y方向にオーバーハング部が2つある場合は2というように、オーバーハング部が複数ある場合は複数としてカウントした。したがって、オーバーハング率は100%以上となる場合がある。
このため、本実施形態においては、接合界面に沿った方向における積層方向に重複する領域の長さ割合を示すオーバーハング率を7%以上に規定している。
なお、上述のオーバーハング率は7%以上とすることが好ましく、15%以上とすることがさらに好ましい。一方、オーバーハング率に特に制限はないが、100%以下とすることが好ましい。
輪郭曲線の二乗平均平方根高さRqは、JIS B 0601:2001に規定されたパラメータであり、輪郭曲面の二乗平均平方根高さSqは、JIS B 0681-2:2018に規定されたパラメータであり、表面粗さの標準偏差を意味するものである。
なお、回路層13(金属基板11)の接合界面における輪郭曲線の二乗平均平方根高さRqおよび輪郭曲面の二乗平均平方根高さSqの少なくとも一方は、0.20μm以上とすることが好ましく、0.30μm以上とすることがさらに好ましい。一方、回路層13(金属基板11)の接合界面における輪郭曲線の二乗平均平方根高さRqおよび輪郭曲面の二乗平均平方根高さSqの少なくとも一方は、0.90μm以下とすることが好ましく、0.80μm以下とすることがさらに好ましい。
まず、回路層13となる金属板23の絶縁樹脂層12との接合面に粗化めっき層23aを形成するとともに、金属基板11の絶縁樹脂層12との接合面に粗化めっき層11aを形成する。これにより、回路層13となる金属板23の絶縁樹脂層12との接合面および金属基板11の絶縁樹脂層12との接合面に、それぞれ凹凸部を形成する。なお、粗化めっき層23a、11aは、以下のようにして形成される。
これにより、金属板23および金属基板11の表面の溶解と銅の析出とが繰り返し実施され、粗化めっき層23a、11aが形成されることになる。
また、パルス波形として析出量/溶解量比を大きくすると、輪郭曲線のクルトシスRkuおよび輪郭曲面のクルトシスSkuは増加し、オーバーハング率は減少し、輪郭曲線の二乗平均平方根高さRqおよび輪郭曲面の二乗平均平方根高さSqは減少する。
さらに、パルス周波数が大きくなると、輪郭曲線のクルトシスRkuおよび輪郭曲面のクルトシスSkuは3に近接し、オーバーハング率は減少し、輪郭曲線の二乗平均平方根高さRqおよび輪郭曲面の二乗平均平方根高さSqは減少する。
本実施形態である表面粗化工程S01を実施することで、金属板23(金属基板11)の接合面に凹凸部が形成され、オーバーハング部が形成されていることが確認される。
次に、金属基板11の一方の面(図4において上面)に、フィラーとしてのアルミナと熱硬化型樹脂としてのエポキシ樹脂と硬化剤とを含有する樹脂組成物22を配設する。なお、本実施形態では、樹脂組成物22は、シート状に形成されている。
また、この樹脂組成物22の一方の面(図4において上面)に、回路層13となる金属板23を配設する。
次に、積層した金属基板11、樹脂組成物22、金属板23を、積層方向に加圧するとともに加圧して、樹脂組成物22を硬化させて絶縁樹脂層12を形成するとともに、金属基板11と絶縁樹脂層12、絶縁樹脂層12と金属板23を接合する。
この熱圧着工程S03の条件は、加熱温度が150℃以上400℃以下の範囲内、加熱温度での保持時間を30分以上90分以下の範囲内、積層方向の加圧圧力を1MPa以上100MPa以下の範囲内とすることが好ましい。
次に、絶縁樹脂層12に接合された金属板23に対してエッチング処理を行い、回路パターンを形成し、回路層13を構成する。
次に、この絶縁回路基板10の金属基板11の他方の面にヒートシンク31を接合する。本実施形態では、金属基板11とヒートシンク31とを、はんだ材を介して接合している。
そして、絶縁回路基板10の回路層13に半導体素子3を接合する。本実施形態では、回路層13と半導体素子3とを、はんだ材を介して接合している。
以上の工程により、図1に示すパワーモジュール1が製造される。
そして、接合界面に沿った方向における積層方向に重複する領域の長さ割合を示すオーバーハング率が7%以上とされているので、回路層13(金属基板11)と絶縁樹脂層12とが十分に係合しており、回路層13(金属基板11)と絶縁樹脂層12との密着性を向上させることができる。
本実施形態においては、図2から図4に示す絶縁回路基板の製造方法によって絶縁回路基板を製造するものとして説明したが、これに限定されることはない。
また、この樹脂組成物のシート材の一方の面に、回路層となる金属板を、粗化めっき層が形成された面が樹脂組成物のシート材側を向くように、積層した。
以上のようにして、得られた絶縁回路基板について、以下の項目についてそれぞれ評価した。
回路層と絶縁樹脂層の接合界面を、レーザ顕微鏡OLS5000を用いて対物レンズ100倍として、129μm×129μmの測定範囲で観察し、サンプルの傾き、ノイズを除去する処理を行い、接合界面における輪郭曲面のクルトシスSku、および、輪郭曲面の二乗平均平方根高さSqを算出した。
次に、最も粗さが粗くなると思われる方向において、接合界面における輪郭極性のクルトシスRku、および、輪郭曲面の二乗平均平方根高さRqを算出した。なお、測定範囲内で少なくとも3箇所以上を測定し、その平均値を表に記載した。
絶縁回路基板を対角線方向にかつ積層方向に沿って切断し、回路層と絶縁樹脂層の接合界面の断面を観察し、倍率10000倍のSIM像(512ピクセル=11μm)を得た。このSIM像を、画像解析ソフトImageJを用いて、二値化して手動でノイズを除去した後にアウトライン抽出した。
[オーバーハング率]=[X軸位置毎のオーバーハング領域の数の合計]/[X方向のピクセル数]×100(%)
上述の絶縁回路基板を、恒温恒湿槽(温度85℃、湿度85%)に入れ、3日間保持した。その後、加熱炉内に装入し、290℃で10分間のリフロー処理を実施した。
リフロー処理後の絶縁回路基板において、回路層と絶縁樹脂層の接合率、絶縁破壊電圧について以下のようにして評価した。
回路層と絶縁樹脂層及の接合率は、超音波探傷装置(株式会社日立パワーソリューションズ製FineSAT200)を用いて評価し、以下の式から算出した。ここで、初期接合面積とは、接合前における接合すべき面積とした。超音波探傷像を二値化処理した画像において剥離は接合部内の白色部で示されることから、この白色部の面積を剥離面積とした。
(接合率)={(初期接合面積)-(剥離面積)}/(初期接合面積)×100
図6に示すように、金属基板11をベース板61の上に載置し、回路層13の上にプローブ62を接触させ、部分放電を評価した。測定装置として、三菱電線株式会社製の部分放電試験機を用いた。なお、試験雰囲気として、3M社製フロリナート(tm)FC-770中で実施した。
そして、電圧を0.5kVごとのステッププロファイル(保持時間30秒)で昇圧し、絶縁破壊が生じた電圧(漏れ電流が10mA以上となった電圧)を絶縁破壊電圧とした。
評価結果を表1に示す。
回路層の接合界面における輪郭曲線のクルトシスRkuが10.30および輪郭曲面のクルトシスSkuが9.40とされた比較例2においては、吸湿リフロー後の絶縁破壊電圧が5.1Vと低くなり、絶縁性が不十分であった。
オーバーハング率が4.2%とされた比較例3においては、吸湿リフロー後の接合率が82%と低くなり、回路層と絶縁樹脂層との密着性が不十分であった。
また、回路層の接合界面における輪郭曲線の二乗平均平方根高さRqおよび輪郭曲面の二乗平均平方根高さSqの両方が0.20μm以上0.90μm以下の範囲内とされた本発明例1-6,8においては、吸湿リフロー後の接合率が85%以上であり、回路層と絶縁樹脂層との密着性に特に優れていた。
11 金属基板(金属部材)
12 絶縁樹脂層(絶縁樹脂部材)
13 回路層(金属部材)
18 凸部
19 凹部
Claims (4)
- 絶縁樹脂からなる絶縁樹脂部材と金属からなる金属部材とが接合された構造の接合体であって、
前記絶縁樹脂部材と前記金属部材との接合界面は、前記金属部材が前記絶縁樹脂部材側へ突出した凸部と前記金属部材が前記絶縁樹脂部材側から後退した凹部とを有する凹凸形状をなしており、
前記金属部材の前記接合界面における輪郭曲線のクルトシスRkuおよび前記金属部材の前記接合界面における輪郭曲面のクルトシスSkuの少なくとも一方が、2.75以上6.00以下の範囲内とされ、
前記接合界面に沿った方向における積層方向に重複する領域の長さ割合を示すオーバーハング率が7%以上とされていることを特徴とする接合体。 - 前記金属部材の前記接合界面における輪郭曲線の二乗平均平方根高さRqおよび前記金属部材の前記接合界面における輪郭曲面の二乗平均平方根高さSqの少なくとも一方が、0.20μm以上0.90μm以下の範囲内とされていることを特徴とする請求項1に記載の接合体。
- 絶縁樹脂層と、絶縁樹脂層の一方の面に金属板が接合されてなる回路層と、を備えた絶縁回路基板であって、
前記絶縁樹脂層と前記回路層との接合界面は、前記回路層が前記絶縁樹脂層側へ突出した凸部と前記回路層が前記絶縁樹脂層側から後退した凹部とを有する凹凸形状をなしており、
前記回路層の前記接合界面における輪郭曲線のクルトシスRkuおよび前記回路層の前記接合界面における輪郭曲面のクルトシスSkuの少なくとも一方が、2.75以上6.00以下の範囲内とされ、
前記接合界面に沿った方向における積層方向に重複する領域の長さ割合を示すオーバーハング率が7%以上とされていることを特徴とする絶縁回路基板。 - 前記回路層の前記接合界面における輪郭曲線の二乗平均平方根高さRqおよび前記回路層の前記接合界面における輪郭曲面の二乗平均平方根高さSqの少なくとも一方が、0.20μm以上0.90μm以下の範囲内とされていることを特徴とする請求項3に記載の絶縁回路基板。
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| CN202510118040.4A CN119653591A (zh) | 2020-03-30 | 2021-03-29 | 金属板 |
| EP24222878.1A EP4513554B1 (en) | 2020-03-30 | 2021-03-29 | Metal plate for bonding with an insulating resin member |
| KR1020227033026A KR20220160580A (ko) | 2020-03-30 | 2021-03-29 | 접합체, 및, 절연 회로 기판 |
| EP21779171.4A EP4132235B1 (en) | 2020-03-30 | 2021-03-29 | Bonded body and insulating circuit board |
| JP2022512248A JP7260059B2 (ja) | 2020-03-30 | 2021-03-29 | 接合体、および、絶縁回路基板 |
| CN202180025520.6A CN115380633B (zh) | 2020-03-30 | 2021-03-29 | 接合体及绝缘电路基板 |
| US17/915,129 US12137526B2 (en) | 2020-03-30 | 2021-03-29 | Bonded body and insulating circuit board |
| US18/904,432 US20250024610A1 (en) | 2020-03-30 | 2024-10-02 | Bonded body and insulating circuit board |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0529740A (ja) * | 1991-07-18 | 1993-02-05 | Furukawa Saakitsuto Foil Kk | プリント配線板用電解銅箔 |
| JP2000077850A (ja) | 1998-08-31 | 2000-03-14 | Kyocera Corp | 多層配線基板およびその製造方法 |
| JP2001044627A (ja) * | 1999-08-02 | 2001-02-16 | Ibiden Co Ltd | 配線基板の製造方法及び配線基板 |
| WO2013008651A1 (ja) * | 2011-07-14 | 2013-01-17 | 京セラ株式会社 | 回路基板および電子装置 |
| JP2014201777A (ja) * | 2013-04-02 | 2014-10-27 | Jx日鉱日石金属株式会社 | キャリア付き銅箔 |
| JP2015207666A (ja) | 2014-04-21 | 2015-11-19 | 住友ベークライト株式会社 | 金属ベース基板、金属ベース基板の製造方法、金属ベース回路基板および電子装置 |
| JP2018172785A (ja) * | 2017-03-31 | 2018-11-08 | Jx金属株式会社 | 表面処理銅箔、樹脂層付き表面処理銅箔、キャリア付銅箔、積層体、プリント配線板の製造方法及び電子機器の製造方法 |
| JP2020060041A (ja) | 2018-10-10 | 2020-04-16 | 株式会社熊谷組 | 足場寸法計測具 |
| JP2020161017A (ja) | 2019-03-28 | 2020-10-01 | 沖電気工業株式会社 | セキュリティインシデント可視化システム |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5178064B2 (ja) * | 2007-06-27 | 2013-04-10 | 富士フイルム株式会社 | 金属表面粗化層を有する金属層積層体及びその製造方法 |
| JP5282675B2 (ja) * | 2009-06-23 | 2013-09-04 | 日立電線株式会社 | プリント配線板用銅箔およびその製造方法 |
| JP5651564B2 (ja) * | 2011-09-30 | 2015-01-14 | 富士フイルム株式会社 | 貼り付け用銅箔 |
| JP5481577B1 (ja) * | 2012-09-11 | 2014-04-23 | Jx日鉱日石金属株式会社 | キャリア付き銅箔 |
| KR20140124402A (ko) * | 2012-11-26 | 2014-10-24 | 제이엑스 닛코 닛세키 킨조쿠 가부시키가이샤 | 표면 처리 전해 동박, 적층판, 및 프린트 배선판 |
| WO2018181726A1 (ja) * | 2017-03-30 | 2018-10-04 | 古河電気工業株式会社 | 表面処理銅箔、並びにこれを用いた銅張積層板およびプリント配線板 |
-
2021
- 2021-03-29 EP EP24222878.1A patent/EP4513554B1/en active Active
- 2021-03-29 US US17/915,129 patent/US12137526B2/en active Active
- 2021-03-29 WO PCT/JP2021/013405 patent/WO2021200874A1/ja not_active Ceased
- 2021-03-29 KR KR1020227033026A patent/KR20220160580A/ko not_active Withdrawn
- 2021-03-29 EP EP21779171.4A patent/EP4132235B1/en active Active
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- 2021-03-29 CN CN202510118040.4A patent/CN119653591A/zh active Pending
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- 2021-03-30 TW TW110111518A patent/TW202205554A/zh unknown
-
2024
- 2024-10-02 US US18/904,432 patent/US20250024610A1/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0529740A (ja) * | 1991-07-18 | 1993-02-05 | Furukawa Saakitsuto Foil Kk | プリント配線板用電解銅箔 |
| JP2000077850A (ja) | 1998-08-31 | 2000-03-14 | Kyocera Corp | 多層配線基板およびその製造方法 |
| JP2001044627A (ja) * | 1999-08-02 | 2001-02-16 | Ibiden Co Ltd | 配線基板の製造方法及び配線基板 |
| WO2013008651A1 (ja) * | 2011-07-14 | 2013-01-17 | 京セラ株式会社 | 回路基板および電子装置 |
| JP2014201777A (ja) * | 2013-04-02 | 2014-10-27 | Jx日鉱日石金属株式会社 | キャリア付き銅箔 |
| JP2015207666A (ja) | 2014-04-21 | 2015-11-19 | 住友ベークライト株式会社 | 金属ベース基板、金属ベース基板の製造方法、金属ベース回路基板および電子装置 |
| JP2018172785A (ja) * | 2017-03-31 | 2018-11-08 | Jx金属株式会社 | 表面処理銅箔、樹脂層付き表面処理銅箔、キャリア付銅箔、積層体、プリント配線板の製造方法及び電子機器の製造方法 |
| JP2020060041A (ja) | 2018-10-10 | 2020-04-16 | 株式会社熊谷組 | 足場寸法計測具 |
| JP2020161017A (ja) | 2019-03-28 | 2020-10-01 | 沖電気工業株式会社 | セキュリティインシデント可視化システム |
Non-Patent Citations (1)
| Title |
|---|
| See also references of EP4132235A4 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2025036112A (ja) * | 2023-08-29 | 2025-03-14 | アブソリックス インコーポレイテッド | 基板及びその製造方法 |
| JP7725664B2 (ja) | 2023-08-29 | 2025-08-19 | アブソリックス インコーポレイテッド | 基板及びその製造方法 |
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| JP7260059B2 (ja) | 2023-04-18 |
| CN119653591A (zh) | 2025-03-18 |
| EP4513554A2 (en) | 2025-02-26 |
| EP4513554A3 (en) | 2025-05-21 |
| EP4132235A4 (en) | 2024-04-10 |
| TW202205554A (zh) | 2022-02-01 |
| JPWO2021200874A1 (ja) | 2021-10-07 |
| EP4132235A1 (en) | 2023-02-08 |
| US20230164924A1 (en) | 2023-05-25 |
| US20250024610A1 (en) | 2025-01-16 |
| US12137526B2 (en) | 2024-11-05 |
| EP4513554B1 (en) | 2026-03-04 |
| CN115380633B (zh) | 2025-02-07 |
| CN115380633A (zh) | 2022-11-22 |
| KR20220160580A (ko) | 2022-12-06 |
| EP4132235B1 (en) | 2025-02-19 |
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