WO2021208558A1 - 一种深度学习大模型训练的方法、系统、设备及介质 - Google Patents

一种深度学习大模型训练的方法、系统、设备及介质 Download PDF

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Publication number
WO2021208558A1
WO2021208558A1 PCT/CN2021/073654 CN2021073654W WO2021208558A1 WO 2021208558 A1 WO2021208558 A1 WO 2021208558A1 CN 2021073654 W CN2021073654 W CN 2021073654W WO 2021208558 A1 WO2021208558 A1 WO 2021208558A1
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gpu
tensors
tensor
topology layer
layer
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French (fr)
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赵涟水
吴韶华
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Suzhou Wave Intelligent Technology Co Ltd
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Suzhou Wave Intelligent Technology Co Ltd
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Priority to KR1020227037803A priority Critical patent/KR102916386B1/ko
Priority to EP21788550.8A priority patent/EP4131081A4/en
Priority to JP2022562519A priority patent/JP7265099B2/ja
Priority to US17/919,312 priority patent/US20230146933A1/en
Publication of WO2021208558A1 publication Critical patent/WO2021208558A1/zh
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/10—Interfaces, programming languages or software development kits, e.g. for simulating neural networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/50—Indexing scheme relating to G06F9/50
    • G06F2209/509—Offload

Definitions

  • the present invention relates to the field of deep learning, and more specifically, to a method, system, computer equipment and readable medium for training a large model of deep learning.
  • GPU Graphics Processing Unit, graphics processing unit
  • CPU Central Processing Unit
  • Some tensors may have multiple copies in the GPU, which is not considered in the existing schemes.
  • the purpose of the embodiments of the present invention is to propose a deep learning large model training method, system, computer equipment, and computer-readable storage medium, and formulate more precise and accurate handling strategies based on the order in which tensors are used; Reduce the adverse effects of memory fragmentation by limiting the tensor from being moved into the GPU prematurely; by redistributing operations in the same topology layer to solve the problem of insufficient memory caused by excessive parallel computing, while ensuring each topology The maximum degree of parallelism of the layer; by formulating the strategy that the previous copy of the tensor has been used up before being moved into the GPU to solve the problem of excessive use of GPU memory.
  • one aspect of the embodiments of the present invention provides a method for deep learning large model training, including the following steps: arrange the tensors in ascending order according to the number of topological levels required by the tensors; The tensors are transported to the GPU in sequence according to the arrangement, and it is determined whether the sum of the tensors currently transported to the GPU exceeds the threshold; in response to the sum of the tensors currently transported to the GPU exceeds the threshold, transport the excess part to the CPU and determine the current Whether the topological layer is the last topological layer; in response to the current topological layer being the last topological layer, correct the tensor whose position is abnormal.
  • the correction of the tensor with abnormal position includes: determining whether there is an abnormally positioned tensor in the GPU; in response to the presence of an abnormally positioned tensor in the GPU, deleting the tensor and Determine whether there is a tensor with an abnormal position in the CPU; and in response to the presence of a tensor with an abnormal position in the CPU, transport the tensor to the GPU.
  • the method further includes: in response to the absence of a tensor with an abnormal position in the GPU, determining whether the memory required by the topology layer exceeds the GPU memory capacity; and in response to the memory required by the topology layer exceeding the GPU Memory capacity, redistribute operations in the topology layer.
  • the redistributing operations in the topology layer includes: creating a new topology layer, and combining operations that exceed the GPU memory capacity in the original topology layer and the next topology layer with the excess GPU. The operation of the memory capacity is not associated with the operation moved into the new topology layer.
  • a system for deep learning large model training including: a sorting module configured to sort the tensors in ascending order according to the number of topological levels at which the tensors are required;
  • the first judging module is configured to transport the tensors to the GPU in sequence according to the arrangement, and judge whether the sum of the tensors currently transported to the GPU exceeds the threshold;
  • the second judging module is configured to respond to the current transport to the GPU The sum of the GPU's tensor exceeds the threshold, and the excess part is transferred to the CPU and judges whether the current topology layer is the last topology layer;
  • the correction module is configured to respond to the current topology layer being the last topology layer, and the position is abnormal The tensor is corrected.
  • the correction module is further configured to: determine whether there is an abnormally positioned tensor in the GPU; in response to the presence of an abnormally positioned tensor in the GPU, delete the tensor and determine whether the tensor is in the CPU There is a tensor with an abnormal position; and in response to the tensor with an abnormal position in the CPU, the tensor is transported to the GPU.
  • it further includes a third judgment module configured to: in response to the absence of a tensor with an abnormal position in the GPU, determine whether the memory required by the topology layer exceeds the GPU memory capacity; and in response to the The memory required by the topology layer exceeds the GPU memory capacity, and the operations in the topology layer are redistributed.
  • the third judgment module is further configured to: create a new topology layer, and compare the calculations that exceed the GPU memory capacity in the original topology layer and the calculations that exceed the GPU memory capacity in the next topology layer. Operations that are not associated are moved into the new topology layer.
  • a computer device including: at least one processor; and a memory, the memory stores computer instructions that can run on the processor, and the instructions are The processor implements the steps of the above method when executed.
  • a computer-readable storage medium stores a computer program that implements the steps of the above method when executed by a processor.
  • the present invention has the following beneficial technical effects: formulating a more precise and accurate handling strategy through the sequence of tensors being used; reducing the adverse effects of memory fragmentation by restricting the tensors from being moved into the GPU prematurely; Allocate operations in the same topology layer to solve the problem of insufficient memory caused by excessive parallel computing, while ensuring the maximum parallelism of each topology layer; by specifying the tensor before being moved into the GPU, the previous copy has been used up.
  • FIG. 1 is a schematic diagram of an embodiment of a method for deep learning large model training provided by the present invention
  • FIG. 2 is a schematic diagram of the redistribution of operations in the topology layer of the embodiment of the method for deep learning large model training provided by the present invention
  • Fig. 3 is a schematic diagram of the hardware structure of an embodiment of a computer device for deep learning large model training provided by the present invention
  • FIG. 4 is a schematic diagram of an embodiment of a system for deep learning large model training provided by the present invention.
  • Fig. 5 is a schematic diagram of a computer-readable storage medium provided by the present invention.
  • Fig. 1 shows a schematic diagram of an embodiment of a method for training a large deep learning model provided by the present invention.
  • the embodiment of the present invention includes the following steps:
  • the tensors Arrange the tensors in ascending order according to the number of topological levels that the tensors are required to. For example, the first topological level required for tensor a is 6, the first topological level required for tensor b is 11, the first topological level required for tensor c is 13, and tensor d is required The first topology level is 15. Then, the order of the tensor is a, b, c, d.
  • the tensors are transferred to the GPU in order, and it is judged whether the sum of the tensors currently transferred to the GPU exceeds the threshold.
  • the tensor is transferred to the GPU in the order of a, b, c, and d, and it is determined in real time whether the sum of the tensors currently transferred to the GPU exceeds the threshold.
  • the threshold can be, for example, 10GB, the size of the tensor a is 4GB, and the tensor The size of b is 3GB, the size of tensor c is 4GB, and the size of tensor d is 3GB.
  • the tensors a and b are transferred to the GPU, since 4+3 ⁇ 10, the sum of the tensors transferred to the GPU does not exceed the threshold at this time, but if the tensor c is transferred to the GPU again, because 4+3 +4>10, at this time, the sum of the tensors transferred to the GPU exceeds the threshold.
  • Correcting a tensor with an abnormal position includes: determining whether there is a tensor with an abnormal position in the GPU; in response to a tensor with an abnormal position in the GPU, deleting the tensor and determining whether there is an abnormal position in the CPU And in response to the abnormally positioned tensor in the CPU, transporting the tensor to the GPU.
  • the judging whether there is a tensor with an abnormal position in the GPU includes: judging whether the position of the tensor in the next topology layer is the CPU.
  • the position of the same tensor in different topological layers may be different. For example, when the tensor c is generated in the 4th layer, the next required topological level is 11. Through calculation, it is found that the tensor c is in the fourth layer.
  • layers 6 and 8 are in the CPU
  • layers 5, 7, 9, and 10 are in the GPU, this method ensures that when the closer to the required layer, the more likely the tensor is in the GPU until the required layer In the previous layer, the tensor must be arranged to enter the GPU at this time.
  • the criterion for judging whether the position of a tensor is wrong is that it is in the GPU at this time, but its next position is in the CPU, such as layers 5 and 7. Judging from the position of the tensor determined above, the real position of the tensor c in the GPU should be the 9th and 10th layers, and in the 4th, 5th and 7th layers, the tensor c should be in the CPU, and this The time tensor c is considered to be in the GPU, which is inconsistent with reality. Therefore, the tensor c is a tensor with an abnormal position.
  • the tensor In response to the presence of an abnormally positioned tensor in the GPU, the tensor is deleted and it is determined whether there is an abnormally positioned tensor in the CPU.
  • the basis for judging that the position of a tensor in the GPU may be advanced is that it is in the CPU at this time, but its next position is in the GPU, such as the 6th and 8th layers.
  • the tensors In response to the presence of abnormally positioned tensors in the CPU, the tensors are transported to the GPU. If there is space in the GPU and there are tensors with abnormal positions in the CPU, the above tensors can be transported to the GPU.
  • the maximum degree of parallelism that can be accommodated in each topology layer can be controlled so that the memory requirement is not higher than a certain threshold.
  • the redistributing operations in the topology layer includes: creating a new topology layer, and combining operations that exceed the GPU memory capacity in the original topology layer and the next topology layer with the excess GPU.
  • the operation of the memory capacity is not associated with the operation moved into the new topology layer.
  • Figure 2 shows a schematic diagram of the redistribution of operations in the topology layer. As shown in Figure 2, a) shows the original computational graph topology layer, and all black nodes in each layer represent operations that can be calculated in parallel. By calculating the memory, it is found that the parallel calculation of the first layer does not exceed the set threshold, so the parallelism of the first layer does not need to be re-allocated.
  • the original third layer has two operations assigned to the new topology layer, in order to achieve the maximum parallelism, those operations that are not dependent on the operations in the third layer can be allocated to the third layer, such as As shown in d), there is an operation (circle) that can be assigned to the third layer.
  • the above steps can be carried out for each layer.
  • the newly created topology layer has six operations. If its memory requirement does not exceed the threshold, then these six operations will finally form a new topology layer; if its memory requirement exceeds the threshold, then execute the processing of the second layer Steps to redistribute.
  • the handling arrangement is customized for each tensor, thereby ensuring the maximum performance; by limiting the tensor being moved prematurely Into the GPU, thereby reducing the adverse effects of memory fragmentation; by limiting the same topology layer, redistributing the topology layers that are too large in parallel computing, while ensuring the maximum parallelism of each topology layer, solves the problem of the same topology layer.
  • the problem of insufficient GPU memory caused by excessive parallel computing in the topology layer; the present invention solves the problem of multiple copies of the same tensor in the GPU by formulating the measure that the previous copies of the tensor have been used before being moved into the GPU The problem avoids overuse of GPU memory.
  • the second aspect of the embodiments of the present invention proposes a deep learning large model training system 400, as shown in FIG. 4, including: a sorting module 401, configured to be configured according to the topological hierarchy required by the tensor The magnitudes of the numbers are arranged in ascending order for the tensors; the first determining module 402 is configured to sequentially transfer the tensors to the GPU according to the arrangement, and determine whether the sum of the tensors currently transferred to the GPU exceeds a threshold; The second judgment module 403 is configured to respond to the sum of the tensors currently transferred to the GPU exceeding the threshold, transfer the excess part to the CPU and determine whether the current topology layer is the last topology layer; the correction module 404 is configured to respond The current topological layer is the last topological layer, which corrects tensors whose positions are abnormal.
  • a sorting module 401 configured to be configured according to the topological hierarchy required by the tensor The magnitudes of the numbers are arranged in ascending order for the
  • the correction module 404 is further configured to: determine whether there is a tensor with an abnormal position in the GPU; in response to the presence of a tensor with an abnormal position in the GPU, delete the tensor and determine whether the tensor is in the CPU Whether there is an abnormally positioned tensor; and in response to the abnormally positioned tensor in the CPU, the tensor is transported to the GPU.
  • the system 400 further includes a third judgment module configured to: in response to the absence of an abnormally positioned tensor in the GPU, determine whether the memory required by the topology layer exceeds the GPU memory capacity; and in response to The memory required by the topology layer exceeds the GPU memory capacity, and the operations in the topology layer are redistributed.
  • a third judgment module configured to: in response to the absence of an abnormally positioned tensor in the GPU, determine whether the memory required by the topology layer exceeds the GPU memory capacity; and in response to The memory required by the topology layer exceeds the GPU memory capacity, and the operations in the topology layer are redistributed.
  • the third judgment module is further configured to: create a new topology layer, and compare the calculations that exceed the GPU memory capacity in the original topology layer and the calculations that exceed the GPU memory capacity in the next topology layer. Operations that are not associated are moved into the new topology layer.
  • the third aspect of the embodiments of the present invention proposes a computer device, including: at least one processor; and a memory.
  • the memory stores computer instructions that can be run on the processor.
  • S1 arrange the tensors in ascending order according to the number of topological levels required by the tensor;
  • S2 transport the tensors to the GPU according to the order, and determine whether the sum of the tensors currently transported to the GPU exceeds the threshold ;
  • S3 in response to the sum of the tensors currently transferred to the GPU exceeding the threshold, transfer the excess part to the CPU and determine whether the current topology layer is the last topology layer;
  • S4 in response to the current topology layer being the last topology layer, Correct the tensor whose position is abnormal.
  • the correction of the tensor with abnormal position includes: determining whether there is an abnormally positioned tensor in the GPU; in response to the presence of an abnormally positioned tensor in the GPU, deleting the tensor and Determine whether there is a tensor with an abnormal position in the CPU; and in response to the presence of a tensor with an abnormal position in the CPU, transport the tensor to the GPU.
  • the method further includes: in response to the absence of a tensor with an abnormal position in the GPU, determining whether the memory required by the topology layer exceeds the GPU memory capacity; and in response to the memory required by the topology layer exceeding the GPU Memory capacity, redistribute operations in the topology layer.
  • the redistributing operations in the topology layer includes: creating a new topology layer, and combining operations that exceed the GPU memory capacity in the original topology layer and the next topology layer with the excess GPU. The operation of the memory capacity is not associated with the operation moved into the new topology layer.
  • FIG. 3 it is a schematic diagram of the hardware structure of an embodiment of the computer device for deep learning large model training provided by the present invention.
  • the device includes a processor 301 and a memory 302, and may also include an input device 303 and an output device 304.
  • the processor 301, the memory 302, the input device 303, and the output device 304 may be connected by a bus or in other ways. In FIG. 3, the connection by a bus is taken as an example.
  • the memory 302 as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the deep learning large model training method in the embodiment of the present application Corresponding program instructions/modules.
  • the processor 301 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions, and modules stored in the memory 302, that is, the method of implementing the deep learning large model training in the above method embodiment.
  • the memory 302 may include a storage program area and a storage data area.
  • the storage program area can store an operating system and an application program required by at least one function; the storage data area can store data created according to the use of the deep learning large model training method. Wait.
  • the memory 302 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices.
  • the memory 302 may optionally include a memory remotely provided with respect to the processor 301, and these remote memories may be connected to a local module through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.
  • the input device 303 can receive the input user name and password and other information.
  • the output device 304 may include a display device such as a display screen.
  • the program instructions/modules corresponding to one or more deep learning large model training methods are stored in the memory 302, and when executed by the processor 301, the deep learning large model training methods in any of the foregoing method embodiments are executed.
  • Any embodiment of the computer device that executes the above-mentioned deep learning large model training method can achieve the same or similar effect as any of the aforementioned method embodiments.
  • the present invention also provides a computer-readable storage medium 500.
  • the computer-readable storage medium 500 stores a computer program 502 that executes the above method when executed by the processor 501.
  • the program of the deep learning large model training method can be stored in a computer In the readable storage medium, when the program is executed, it may include the processes of the above-mentioned method embodiments.
  • the storage medium of the program can be a magnetic disk, an optical disc, a read-only memory (ROM, Read-Only Memory) or a random access memory (RAM, Random Access Memory), etc.
  • the foregoing computer program embodiment can achieve the same or similar effects as any of the foregoing method embodiments corresponding thereto.
  • the method disclosed according to the embodiment of the present invention may also be implemented as a computer program executed by a processor, and the computer program may be stored in a computer-readable storage medium.
  • the computer program executes the above-mentioned functions defined in the method disclosed in the embodiment of the present invention.
  • the above method steps and system units can also be implemented by a controller and a computer-readable storage medium for storing a computer program that enables the controller to implement the above steps or unit functions.
  • non-volatile memory may include read-only memory (ROM), programmable ROM (PROM, Programmable Read-Only Memory), electrically programmable ROM (EPROM, Erasable Programmable Read-Only Memory), Electrically Erasable Programmable ROM (EEPROM, Electrically Erasable Programmable Read-Only Memory) or flash memory.
  • Volatile memory can include random access memory (RAM), which can act as external cache memory.
  • RAM can be obtained in various forms, such as dynamic RAM (DRAM, Dynamic Random Access Memory), synchronous DRAM (SDRAM, Sychronous Dynamic Random Access Memory), and double data rate SDRAM (DDR SDRAM, Double Data). Rate Sychronous Dynamic Random Access Memory, Enhanced SDRAM (ESDRAM, Enhanced Synchronous Dynamic Random Access Memory), Synchronous Link DRAM (SLDRAM, Sync Link Dynamic Random Access Memory), and Direct Rambus RAM (DRRAM, Direct Rambus Access Memory).
  • DRAM Dynamic Random Access Memory
  • SDRAM synchronous DRAM
  • DDR SDRAM Double Data rate SDRAM
  • ESDRAM Enhanced SDRAM
  • SLDRAM Synchronous Link DRAM
  • DRRAM Direct Rambus RAM
  • the storage devices of the disclosed aspects are intended to include, but are not limited to, these and other suitable types of memory.
  • DSP digital signal processors
  • ASIC Application Specific Integrated Circuit
  • FPGA Field Programmable Gate Array
  • a general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
  • the processor may also be implemented as a combination of computing devices, for example, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP, and/or any other such configuration.
  • the steps of the method or algorithm described in combination with the disclosure herein may be directly included in hardware, a software module executed by a processor, or a combination of the two.
  • Software modules can reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disks, removable disks, CD-ROM (Compact Disc-Read Only Memory), or those already in the field.
  • An exemplary storage medium is coupled to the processor such that the processor can read information from or write information to the storage medium.
  • the storage medium may be integrated with the processor.
  • the processor and the storage medium may reside in the ASIC.
  • the ASIC can reside in the user terminal.
  • the processor and the storage medium may reside as discrete components in the user terminal.
  • functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored as one or more instructions or codes on a computer-readable medium or transmitted through the computer-readable medium.
  • Computer-readable media include computer storage media and communication media, including any media that facilitates the transfer of a computer program from one location to another location.
  • a storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer.
  • the computer-readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or may be used for carrying or storing instructions in the form of Or any other medium that can be accessed by a general-purpose or special-purpose computer or general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium.
  • coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave to send software from a website, server, or other remote source
  • coaxial cable Cable, fiber optic cable, twisted pair, DSL (Digital Subscribe Line), or wireless technologies such as infrared, radio, and microwave are all included in the definition of media.
  • magnetic disks and optical disks include compact disks (CDs), laser disks, optical disks, digital versatile disks (DVD, Digital Video Disc), floppy disks, and blu-ray disks. Disks usually reproduce data magnetically, while optical disks use lasers. Reproduce the data optically. Combinations of the above content should also be included in the scope of computer-readable media.
  • the program can be stored in a computer-readable storage medium.
  • the storage medium can be a read-only memory, a magnetic disk or an optical disk, etc.

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Abstract

本发明公开了一种深度学习大模型训练的方法、系统、设备和存储介质，方法包括在每个拓扑层执行以下步骤：根据张量被需求的拓扑层级数的大小对张量按照升序排列；将张量按照该排列依次搬运到GPU，判断当前搬运到GPU的张量的总和是否超过阈值；响应于当前搬运到GPU的张量的总和超过阈值，将超过的部分搬运到CPU并判断当前拓扑层是否为最后一个拓扑层；响应于当前拓扑层是最后一个拓扑层，对位置出现异常的张量进行矫正。本发明提出的深度学习大模型训练的方法、系统、设备及介质通过张量被使用的先后关系来制定更加精细准确的搬运策略，从而保证了性能的最大化。

Description

一种深度学习大模型训练的方法、系统、设备及介质
本申请要求于2020年04月16日提交中国国家知识产权局，申请号为202010297962.3，发明名称为“一种深度学习大模型训练的方法、系统、设备及介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及深度学习领域，更具体地，特别是指一种深度学习大模型训练的方法、系统、计算机设备及可读介质。
背景技术
GPU(Graphics Processing Unit，图形处理器)在深度学习大模型训练中处于越来越重要的地位，主要原因是它很适合大模型训练中高度的并行计算，同时消耗的能量也比用CPU(Central Processing Unit，中央处理器)训练消耗的能量小。但是，由于深度学习大模型的结构越来越复杂，其所需的内存越来越大，超出了商业GPU现有的内存规格，导致了深度学习大模型无法在GPU上进行训练，因此丧失了利用GPU训练带来的效益。
为了减轻目前商业GPU内存不足带来的影响，有人提出了利用丰富的CPU内存来存储GPU中张量这个方法。在大模型训练过程中，将不需要的张量从GPU中搬运到CPU中，再在恰当的时刻将需要的张量从CPU中搬运到GPU里。由于要尽可能保持更好的性能，在将张量从CPU中搬回GPU中的时候，要尽可能地将搬运过程隐藏在计算中，使被需要的张量在被使 用前就已被搬到GPU中。现有方案中存在以下几个不足：
(1)其搬运策略过于粗略，将所有的张量用同一策略搬运，在训练性能上有提升的空间；
(2)由于在计算图中，同一拓扑层里可能存在大量的可并行计算的运算，其可能导致内存需求超过GPU内存，这种情况在现有方案中没有被考虑；
(3)某些张量在GPU中可能存在多个副本，这种情况在现有方案中也没有被考虑。
发明内容
有鉴于此，本发明实施例的目的在于提出一种深度学习大模型训练的方法、系统、计算机设备及计算机可读存储介质，通过张量被使用的先后关系来制定更加精细准确的搬运策略；通过限制张量不能被过早地搬进GPU来减小内存碎片带来的不利影响；通过重新分配同一拓扑层中的运算来解决并行计算过大引起的内存不足的问题，同时保证每一拓扑层的最大并行度；通过制定张量在被搬进GPU前，之前的副本已经被使用完毕这一策略来解决GPU内存被过度使用这一问题。
基于上述目的，本发明实施例的一方面提供了一种深度学习大模型训练的方法，包括如下步骤：根据张量被需求的拓扑层级数的大小对所述张量按照升序排列；将所述张量按照所述排列依次搬运到GPU，并判断当前搬运到GPU的张量的总和是否超过阈值；响应于当前搬运到GPU的张量的总和超过阈值，将超过的部分搬运到CPU并判断当前拓扑层是否为最后一个拓扑层；响应于当前拓扑层是最后一个拓扑层，对位置出现异常的张量进行矫正。
在一些实施方式中，所述对位置出现异常的张量进行矫正包括：判断 GPU中是否存在位置不正常的张量；响应于GPU中存在位置不正常的张量，将所述张量删除并判断CPU中是否存在位置不正常的张量；以及响应于CPU中存在位置不正常的张量，将所述张量搬运到GPU中。
在一些实施方式中，还包括：响应于GPU中不存在位置不正常的张量，判断所述拓扑层所需的内存是否超过GPU内存容量；以及响应于所述拓扑层所需的内存超过GPU内存容量，将所述拓扑层中的运算进行重新分配。
在一些实施方式中，所述将所述拓扑层中的运算进行重新分配包括：创建新的拓扑层，并将原拓扑层中超过GPU内存容量的运算和下一拓扑层中与所述超过GPU内存容量的运算没有关联的运算移入所述新的拓扑层。
本发明实施例的另一方面，还提供了一种深度学习大模型训练的系统，包括：排序模块，配置用于根据张量被需求的拓扑层级数的大小对所述张量按照升序排列；第一判断模块，配置用于将所述张量按照所述排列依次搬运到GPU，并判断当前搬运到GPU的张量的总和是否超过阈值；第二判断模块，配置用于响应于当前搬运到GPU的张量的总和超过阈值，将超过的部分搬运到CPU并判断当前拓扑层是否为最后一个拓扑层；矫正模块，配置用于响应于当前拓扑层是最后一个拓扑层，对位置出现异常的张量进行矫正。
在一些实施方式中，所述矫正模块还配置用于：判断GPU中是否存在位置不正常的张量；响应于GPU中存在位置不正常的张量，将所述张量删除并判断CPU中是否存在位置不正常的张量；以及响应于CPU中存在位置不正常的张量，将所述张量搬运到GPU中。
在一些实施方式中，还包括第三判断模块，配置用于：响应于GPU中不存在位置不正常的张量，判断所述拓扑层所需的内存是否超过GPU内存容量；以及响应于所述拓扑层所需的内存超过GPU内存容量，将所述拓扑层中的运算进行重新分配。
在一些实施方式中，所述第三判断模块还配置用于：创建新的拓扑层，并将原拓扑层中超过GPU内存容量的运算和下一拓扑层中与所述超过GPU内存容量的运算没有关联的运算移入所述新的拓扑层。
本发明实施例的又一方面，还提供了一种计算机设备，包括：至少一个处理器；以及存储器，所述存储器存储有可在所述处理器上运行的计算机指令，所述指令由所述处理器执行时实现如上方法的步骤。
本发明实施例的再一方面，还提供了一种计算机可读存储介质，计算机可读存储介质存储有被处理器执行时实现如上方法步骤的计算机程序。
本发明具有以下有益技术效果：通过张量被使用的先后关系来制定更加精细准确的搬运策略；通过限制张量不能被过早地搬进GPU来减小内存碎片带来的不利影响；通过重新分配同一拓扑层中的运算来解决并行计算过大引起的内存不足的问题，同时保证每一拓扑层的最大并行度；通过制定张量在被搬进GPU前，之前的副本已经被使用完毕这一策略来解决GPU内存被过度使用这一问题。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的实施例。
图1为本发明提供的深度学习大模型训练的方法的实施例的示意图；
图2为本发明提供的深度学习大模型训练的方法的实施例的拓扑层中的运算进行重新分配的示意图；
图3为本发明提供的深度学习大模型训练的计算机设备的实施例的硬 件结构示意图；
图4为本发明提供的深度学习大模型训练的系统的实施例的示意图；
图5为本发明提供的计算机可读存储介质的示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明实施例进一步详细说明。
需要说明的是，本发明实施例中所有使用“第一”和“第二”的表述均是为了区分两个相同名称非相同的实体或者非相同的参量，可见“第一”“第二”仅为了表述的方便，不应理解为对本发明实施例的限定，后续实施例对此不再一一说明。
基于上述目的，本发明实施例的第一个方面，提出了一种深度学习大模型训练的方法的实施例。图1示出的是本发明提供的深度学习大模型训练的方法的实施例的示意图。如图1所示，本发明实施例包括如下步骤：
S1、根据张量被需求的拓扑层级数的大小对张量按照升序排列；
S2、将张量按照排列依次搬运到GPU，并判断当前搬运到GPU的张量的总和是否超过阈值；
S3、响应于当前搬运到GPU的张量的总和超过阈值，将超过的部分搬运到CPU并判断当前拓扑层是否为最后一个拓扑层；以及
S4、响应于当前拓扑层是最后一个拓扑层，对位置出现异常的张量进行矫正。
根据张量被需求的拓扑层级数的大小对张量按照升序排列。例如，张量a被需求的第一个拓扑层级是6，张量b被需求的第一个拓扑层级是11，张量c被需求的第一个拓扑层级是13，张量d被需求的第一个拓扑层级是 15。那么，张量的排列顺序为a、b、c、d。
将张量按照顺序依次搬运到GPU，判断当前搬运到GPU的张量的总和是否超过阈值。将张量按照a、b、c、d的顺序依次搬运到GPU，并实时判断当前搬运到GPU的张量的总和是否超过阈值，阈值例如可以是10GB，张量a的大小为4GB，张量b的大小为3GB，张量c的大小为4GB，张量d的大小为3GB。如果将张量a和b搬运到GPU中，由于4+3<10，此时搬运到GPU中的张量的总和未超过阈值，但是如果再将张量c搬运到GPU中，由于4+3+4>10，此时搬运到GPU中的张量的总和超过了阈值。
响应于当前搬运到GPU的张量的总和超过阈值，将超过的部分搬运到CPU并判断当前拓扑层是否为最后一个拓扑层。继续上例，由于张量c搬运到GPU中时搬运到GPU中的张量的总和超过了阈值，可以将张量c、d搬运到CPU中。并且判断当前拓扑层是否为最后一个拓扑层。
如果当前拓扑层是最后一个拓扑层，对位置出现异常的张量进行矫正。对位置出现异常的张量进行矫正包括：判断GPU中是否存在位置不正常的张量；响应于GPU中存在位置不正常的张量，将所述张量删除并判断CPU中是否存在位置不正常的张量；以及响应于CPU中存在位置不正常的张量，将所述张量搬运到GPU中。
在一些实施方式中，所述判断GPU中是否存在位置不正常的张量包括：判断所述张量在下一个拓扑层的位置是否为CPU。同一个张量在不同的拓扑层时其所在的位置可能不一样，例如，当张量c在第4层产生，下一个被需求的拓扑层级数是11，通过计算，发现张量c在第6和8层时在CPU中，在5、7、9和10层时在GPU中，且此方法保证了当越接近被需求层时，该张量越有可能在GPU中，直到被需求层的前一层，此时该张量必须被安排进入GPU。判断一个张量的位置是否错误的标准是此时它在GPU中，但是它的下一个位置在CPU中，如第5和7层。从上面所决定的张量位置 来看，张量c真正应该在GPU中的位置应该是第9和10层，而在第4、5和7层时，张量c应该在CPU中，而此时张量c却被认为是在GPU中的，这和实际不符。因此，张量c就属于位置不正常的张量。
响应于GPU中存在位置不正常的张量，将张量删除并判断CPU中是否存在位置不正常的张量。判断一个张量在GPU中的位置有可能提前的依据是此时它在CPU中，但是它的下一个位置在GPU中，如第6和8层。
响应于CPU中存在位置不正常的张量，将所述张量搬运到GPU中。如果GPU中存在空间，并且CPU中存在位置不正常的张量，可以将上述张量搬运到GPU中。
由于影响训练性能的因素是多方面的，不但包括张量能否被及时搬运到GPU中，还包含cuDNN(CUDA Deep Neural Network library，英伟达(NVIDIA)基于CUDA的深度神经网络加速库，CUDA(Compute Unified Device Architecture，NVIDIA推出的基于GPU的运算平台))中的加速库有没有被充分地运用。如果过早地将张量搬运到GPU中，容易造成GPU中存在过多的内存碎片，从而使实际训练过程不稳定；同时，这样也使得GPU中空余的内存很有限，不利于应用cuDNN中更快速的算法，从而降低性能。通过大量的实验结果分析可知，将张量搬回GPU的时刻设置为不早于被需求的前100个拓扑层，一般会得到比较好的性能。
在一些实施方式中，响应于GPU中不存在位置不正常的张量，判断所述拓扑层所需的内存是否超过GPU内存容量；以及响应于所述拓扑层所需的内存超过GPU内存容量，将所述拓扑层中的运算进行重新分配。在计算图中，每一拓扑层中的所有运算可以进行并行计算，但如果同时存在很多并行计算时，其所需求的内存可能会超过GPU内存容量，因此这会造成模型无法在GPU上训练的问题。为了解决并行计算需求过多内存这一问题，可以控制每一拓扑层可容纳的最大并行度，使其内存需求不高于某一阈值。
在一些实施方式中，所述将所述拓扑层中的运算进行重新分配包括：创建新的拓扑层，并将原拓扑层中超过GPU内存容量的运算和下一拓扑层中与所述超过GPU内存容量的运算没有关联的运算移入所述新的拓扑层。图2示出的是拓扑层中的运算重新分配的示意图。如图2所示，a)中展示的是原始的计算图拓扑层，每一层中的所有黑色节点代表可以并行计算的运算。通过计算内存，发现第一层的并行计算没有超过设定的阈值，因此第一层的并行度不需要被重新分配。当计算第二层时，发现只有部分运算可以留在第二层，如b)中第二层的黑色节点所示；剩余的四个节点(第二层的圆圈)必须在新的一层，如c)所示，这四个运算被分配到了新的拓扑层。为了使新的拓扑层达到最大的并行度，可以将原始第三层中与之前的四个运算无依赖关系的运算，移到新的拓扑层。如c)所示，原始的第三层中有2个运算(圆圈)可以被分配到新的拓扑层，如d)所示。由于原始的第三层有2个运算被分配到了新的拓扑层，为了使其也达到最大的并行度，可以将那些与第三层中的运算无依赖关系的运算分配到第三层，如d)所示，有一个运算(圆圈)可以被分配到第三层。为了使剩余的每一层都达到最大的并行度，可以对每一层都实行以上步骤。此时新建的拓扑层有六个运算，如果其内存需求不超过阈值，那么这六个运算就最终组成了新的拓扑层；如果其内存需求超过了阈值，那么就执行处理第二层时的步骤，进行重新分配。
在GPU中，有可能出现同一张量存在多个副本的情况，这使得GPU内存被过度使用，容易引起GPU内存不足。例如，运算1-4使用同一张量，但其是通过不同的搬运操作进入GPU的。如果运算1-3没有在运算4开始执行时完成，那么GPU中就存在这一张量的两个副本，造成GPU内存的过度使用，甚至出现内存不足这一问题。为了解决这一问题，可以强制运算4使用的副本在运算1-3完成后再开始被搬进GPU。
本发明实施例根据张量越早被使用就越可能被率先搬进GPU这一思想，为每一个张量都定制了搬运安排，从而保证了性能的最大化；通过限制张量被过早搬进GPU，从而减小了内存碎片带来的不利影响；通过对同一拓扑层进行限制，重新分配并行计算过大的拓扑层，同时保证每一拓扑层最大并行度这一方法，解决了由于同一拓扑层中并行计算过大引起的GPU内存不足的问题；本发明通过制定张量在被搬进GPU前，之前的副本已经被使用完毕这一措施，解决了GPU中同一张量多个副本的问题，避免了GPU内存被过度使用。
需要特别指出的是，上述深度学习大模型训练的方法的各个实施例中的各个步骤均可以相互交叉、替换、增加、删减，因此，这些合理的排列组合变换用于深度学习大模型训练的方法也应当属于本发明的保护范围，并且不应将本发明的保护范围局限在实施例之上。
基于上述目的，本发明实施例的第二个方面，提出了一种深度学习大模型训练的系统400，如图4所示，包括：排序模块401，配置用于根据张量被需求的拓扑层级数的大小对所述张量按照升序排列；第一判断模块402，配置用于将所述张量按照所述排列依次搬运到GPU，并判断当前搬运到GPU的张量的总和是否超过阈值；第二判断模块403，配置用于响应于当前搬运到GPU的张量的总和超过阈值，将超过的部分搬运到CPU并判断当前拓扑层是否为最后一个拓扑层；矫正模块404，配置用于响应于当前拓扑层是最后一个拓扑层，对位置出现异常的张量进行矫正。
在一些实施方式中，所述矫正模块404还配置用于：判断GPU中是否存在位置不正常的张量；响应于GPU中存在位置不正常的张量，将所述张量删除并判断CPU中是否存在位置不正常的张量；以及响应于CPU中存在位置不正常的张量，将所述张量搬运到GPU中。
在一些实施方式中，系统400还包括第三判断模块，配置用于：响应 于GPU中不存在位置不正常的张量，判断所述拓扑层所需的内存是否超过GPU内存容量；以及响应于所述拓扑层所需的内存超过GPU内存容量，将所述拓扑层中的运算进行重新分配。
在一些实施方式中，所述第三判断模块还配置用于：创建新的拓扑层，并将原拓扑层中超过GPU内存容量的运算和下一拓扑层中与所述超过GPU内存容量的运算没有关联的运算移入所述新的拓扑层。
基于上述目的，本发明实施例的第三个方面，提出了一种计算机设备，包括：至少一个处理器；以及存储器，存储器存储有可在处理器上运行的计算机指令，指令由处理器执行以实现如下步骤：S1、根据张量被需求的拓扑层级数的大小对张量按照升序排列；S2、将张量按照排列依次搬运到GPU，并判断当前搬运到GPU的张量的总和是否超过阈值；S3、响应于当前搬运到GPU的张量的总和超过阈值，将超过的部分搬运到CPU并判断当前拓扑层是否为最后一个拓扑层；以及S4、响应于当前拓扑层是最后一个拓扑层，对位置出现异常的张量进行矫正。
在一些实施方式中，所述对位置出现异常的张量进行矫正包括：判断GPU中是否存在位置不正常的张量；响应于GPU中存在位置不正常的张量，将所述张量删除并判断CPU中是否存在位置不正常的张量；以及响应于CPU中存在位置不正常的张量，将所述张量搬运到GPU中。
在一些实施方式中，还包括：响应于GPU中不存在位置不正常的张量，判断所述拓扑层所需的内存是否超过GPU内存容量；以及响应于所述拓扑层所需的内存超过GPU内存容量，将所述拓扑层中的运算进行重新分配。
在一些实施方式中，所述将所述拓扑层中的运算进行重新分配包括：创建新的拓扑层，并将原拓扑层中超过GPU内存容量的运算和下一拓扑层中与所述超过GPU内存容量的运算没有关联的运算移入所述新的拓扑层。
如图3所示，为本发明提供的上述深度学习大模型训练的计算机设备的一个实施例的硬件结构示意图。
以如图3所示的装置为例，在该装置中包括一个处理器301以及一个存储器302，并还可以包括：输入装置303和输出装置304。
处理器301、存储器302、输入装置303和输出装置304可以通过总线或者其他方式连接，图3中以通过总线连接为例。
存储器302作为一种非易失性计算机可读存储介质，可用于存储非易失性软件程序、非易失性计算机可执行程序以及模块，如本申请实施例中的深度学习大模型训练的方法对应的程序指令/模块。处理器301通过运行存储在存储器302中的非易失性软件程序、指令以及模块，从而执行服务器的各种功能应用以及数据处理，即实现上述方法实施例的深度学习大模型训练的方法。
存储器302可以包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需要的应用程序；存储数据区可存储根据深度学习大模型训练的方法的使用所创建的数据等。此外，存储器302可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件、闪存器件、或其他非易失性固态存储器件。在一些实施例中，存储器302可选包括相对于处理器301远程设置的存储器，这些远程存储器可以通过网络连接至本地模块。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
输入装置303可接收输入的用户名和密码等信息。输出装置304可包括显示屏等显示设备。
一个或者多个深度学习大模型训练的方法对应的程序指令/模块存储在存储器302中，当被处理器301执行时，执行上述任意方法实施例中的深 度学习大模型训练的方法。
执行上述深度学习大模型训练的方法的计算机设备的任何一个实施例，可以达到与之对应的前述任意方法实施例相同或者相类似的效果。
本发明还提供了一种计算机可读存储介质500，如图5所示，计算机可读存储介质500存储有被处理器501执行时执行如上方法的计算机程序502。
最后需要说明的是，本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，可以通过计算机程序来指令相关硬件来完成，深度学习大模型训练的方法的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，程序的存储介质可为磁碟、光盘、只读存储记忆体(ROM，Read-Only Memory)或随机存储记忆体(RAM，Random Access Memory)等。上述计算机程序的实施例，可以达到与之对应的前述任意方法实施例相同或者相类似的效果。
此外，根据本发明实施例公开的方法还可以被实现为由处理器执行的计算机程序，该计算机程序可以存储在计算机可读存储介质中。在该计算机程序被处理器执行时，执行本发明实施例公开的方法中限定的上述功能。
此外，上述方法步骤以及系统单元也可以利用控制器以及用于存储使得控制器实现上述步骤或单元功能的计算机程序的计算机可读存储介质实现。
此外，应该明白的是，本文的计算机可读存储介质(例如，存储器)可以是易失性存储器或非易失性存储器，或者可以包括易失性存储器和非易失性存储器两者。作为例子而非限制性的，非易失性存储器可以包括只读存储器(ROM)、可编程ROM(PROM，Programmable Read-Only Memory)、电可编程ROM(EPROM，Erasable Programmable Read-Only Memory)、电 可擦写可编程ROM(EEPROM，Electrically Erasable Programmable Read-Only Memory)或快闪存储器。易失性存储器可以包括随机存取存储器(RAM)，该RAM可以充当外部高速缓存存储器。作为例子而非限制性的，RAM可以以多种形式获得，比如动态RAM(DRAM，Dynamic Random Access Memory)、同步DRAM(SDRAM，Sychronous Dynamic Random Access Memory)、双数据速率SDRAM(DDR SDRAM,Double Data Rate Sychronous Dynamic Random Access Memory)、增强SDRAM(ESDRAM，Enhanced Synchronous Dynamic Random Access Memory)、同步链路DRAM(SLDRAM，Sync Link Dynamic Random Access Memory)、以及直接Rambus RAM(DRRAM，Direct Rambus Random Access Memory)。所公开的方面的存储设备意在包括但不限于这些和其它合适类型的存储器。
本领域技术人员还将明白的是，结合这里的公开所描述的各种示例性逻辑块、模块、电路和算法步骤可以被实现为电子硬件、计算机软件或两者的组合。为了清楚地说明硬件和软件的这种可互换性，已经就各种示意性组件、方块、模块、电路和步骤的功能对其进行了一般性的描述。这种功能是被实现为软件还是被实现为硬件取决于具体应用以及施加给整个系统的设计约束。本领域技术人员可以针对每种具体应用以各种方式来实现的功能，但是这种实现决定不应被解释为导致脱离本发明实施例公开的范围。
结合这里的公开所描述的各种示例性逻辑块、模块和电路可以利用被设计成用于执行这里功能的下列部件来实现或执行：通用处理器、数字信号处理器(DSP，Digital Signal Processor)、专用集成电路(ASIC，Application Specific Integrated Circuit)、现场可编程门阵列(FPGA，Field Programmable Gate Array)或其它可编程逻辑器件、分立门或晶体管逻辑、分立的硬件组 件或者这些部件的任何组合。通用处理器可以是微处理器，但是可替换地，处理器可以是任何传统处理器、控制器、微控制器或状态机。处理器也可以被实现为计算设备的组合，例如，DSP和微处理器的组合、多个微处理器、一个或多个微处理器结合DSP和/或任何其它这种配置。
结合这里的公开所描述的方法或算法的步骤可以直接包含在硬件中、由处理器执行的软件模块中或这两者的组合中。软件模块可以驻留在RAM存储器、快闪存储器、ROM存储器、EPROM存储器、EEPROM存储器、寄存器、硬盘、可移动盘、CD-ROM(Compact Disc-Read Only Memory光盘只读存储器)、或本领域已知的任何其它形式的存储介质中。示例性的存储介质被耦合到处理器，使得处理器能够从该存储介质中读取信息或向该存储介质写入信息。在一个替换方案中，存储介质可以与处理器集成在一起。处理器和存储介质可以驻留在ASIC中。ASIC可以驻留在用户终端中。在一个替换方案中，处理器和存储介质可以作为分立组件驻留在用户终端中。
在一个或多个示例性设计中，功能可以在硬件、软件、固件或其任意组合中实现。如果在软件中实现，则可以将功能作为一个或多个指令或代码存储在计算机可读介质上或通过计算机可读介质来传送。计算机可读介质包括计算机存储介质和通信介质，该通信介质包括有助于将计算机程序从一个位置传送到另一个位置的任何介质。存储介质可以是能够被通用或专用计算机访问的任何可用介质。作为例子而非限制性的，该计算机可读介质可以包括RAM、ROM、EEPROM、CD-ROM或其它光盘存储设备、磁盘存储设备或其它磁性存储设备，或者是可以用于携带或存储形式为指令或数据结构的所需程序代码并且能够被通用或专用计算机或者通用或专用处理器访问的任何其它介质。此外，任何连接都可以适当地称为计算机可读介质。例如，如果使用同轴线缆、光纤线缆、双绞线、数字用户线路 (DSL)或诸如红外线、无线电和微波的无线技术来从网站、服务器或其它远程源发送软件，则上述同轴线缆、光纤线缆、双绞线、DSL(Digital Subscribe Line，数字用户线路)或诸如红外线、无线电和微波的无线技术均包括在介质的定义。如这里所使用的，磁盘和光盘包括压缩盘(CD)、激光盘、光盘、数字多功能盘(DVD，Digital Video Disc)、软盘、蓝光盘，其中磁盘通常磁性地再现数据，而光盘利用激光光学地再现数据。上述内容的组合也应当包括在计算机可读介质的范围内。
以上是本发明公开的示例性实施例，但是应当注意，在不背离权利要求限定的本发明实施例公开的范围的前提下，可以进行多种改变和修改。根据这里描述的公开实施例的方法权利要求的功能、步骤和/或动作不需以任何特定顺序执行。此外，尽管本发明实施例公开的元素可以以个体形式描述或要求，但除非明确限制为单数，也可以理解为多个。
应当理解的是，在本文中使用的，除非上下文清楚地支持例外情况，单数形式“一个”旨在也包括复数形式。还应当理解的是，在本文中使用的“和/或”是指包括一个或者一个以上相关联地列出的项目的任意和所有可能组合。
上述本发明实施例公开实施例序号仅仅为了描述，不代表实施例的优劣。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
所属领域的普通技术人员应当理解：以上任何实施例的讨论仅为示例性的，并非旨在暗示本发明实施例公开的范围(包括权利要求)被限于这些例子；在本发明实施例的思路下，以上实施例或者不同实施例中的技术 特征之间也可以进行组合，并存在如上的本发明实施例的不同方面的许多其它变化，为了简明它们没有在细节中提供。因此，凡在本发明实施例的精神和原则之内，所做的任何省略、修改、等同替换、改进等，均应包含在本发明实施例的保护范围之内。

Claims (10)

  1. 一种深度学习大模型训练的方法，其特征在于，包括在每个拓扑层执行以下步骤：
    根据张量被需求的拓扑层级数的大小对所述张量按照升序排列；
    将所述张量按照所述排列依次搬运到GPU，并判断当前搬运到GPU的张量的总和是否超过阈值；
    响应于当前搬运到GPU的张量的总和超过阈值，将超过的部分搬运到CPU并判断当前拓扑层是否为最后一个拓扑层；
    响应于当前拓扑层是最后一个拓扑层，对位置出现异常的张量进行矫正。
  2. 根据权利要求1所述的方法，其特征在于，所述对位置出现异常的张量进行矫正包括：
    判断GPU中是否存在位置不正常的张量；
    响应于GPU中存在位置不正常的张量，将所述张量删除并判断CPU中是否存在位置不正常的张量；以及
    响应于CPU中存在位置不正常的张量，将所述张量搬运到GPU中。
  3. 根据权利要求2所述的方法，其特征在于，还包括：
    响应于GPU中不存在位置不正常的张量，判断所述拓扑层所需的内存是否超过GPU内存容量；以及
    响应于所述拓扑层所需的内存超过GPU内存容量，将所述拓扑层中的运算进行重新分配。
  4. 根据权利要求3所述的方法，其特征在于，所述将所述拓扑层中的运算进行重新分配包括：
    创建新的拓扑层，并将原拓扑层中超过GPU内存容量的运算和下一拓扑 层中与所述超过GPU内存容量的运算没有关联的运算移入所述新的拓扑层。
  5. 一种深度学习大模型训练的系统，其特征在于，包括：
    排序模块，配置用于根据张量被需求的拓扑层级数的大小对所述张量按照升序排列；
    第一判断模块，配置用于将所述张量按照所述排列依次搬运到GPU，并判断当前搬运到GPU的张量的总和是否超过阈值；
    第二判断模块，配置用于响应于当前搬运到GPU的张量的总和超过阈值，将超过的部分搬运到CPU并判断当前拓扑层是否为最后一个拓扑层；
    矫正模块，配置用于响应于当前拓扑层是最后一个拓扑层，对位置出现异常的张量进行矫正。
  6. 根据权利要求5所述的系统，其特征在于，所述矫正模块还配置用于：
    判断GPU中是否存在位置不正常的张量；
    响应于GPU中存在位置不正常的张量，将所述张量删除并判断CPU中是否存在位置不正常的张量；以及
    响应于CPU中存在位置不正常的张量，将所述张量搬运到GPU中。
  7. 根据权利要求6所述的系统，其特征在于，还包括第三判断模块，配置用于：
    响应于GPU中不存在位置不正常的张量，判断所述拓扑层所需的内存是否超过GPU内存容量；以及
    响应于所述拓扑层所需的内存超过GPU内存容量，将所述拓扑层中的运算进行重新分配。
  8. 根据权利要求7所述的系统，其特征在于，所述第三判断模块还配置用于：
    创建新的拓扑层，并将原拓扑层中超过GPU内存容量的运算和下一拓扑层中与所述超过GPU内存容量的运算没有关联的运算移入所述新的拓扑层。
  9. 一种计算机设备，其特征在于，包括：
    至少一个处理器；以及
    存储器，所述存储器存储有可在所述处理器上运行的计算机指令，所述指令由所述处理器执行时实现权利要求1-4任意一项所述方法的步骤。
  10. 一种计算机可读存储介质，所述计算机可读存储介质存储有计算机程序，其特征在于，所述计算机程序被处理器执行时实现权利要求1-4任意一项所述方法的步骤。
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