WO2021208708A1 - 一种显示面板及显示装置 - Google Patents

一种显示面板及显示装置 Download PDF

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Publication number
WO2021208708A1
WO2021208708A1 PCT/CN2021/083388 CN2021083388W WO2021208708A1 WO 2021208708 A1 WO2021208708 A1 WO 2021208708A1 CN 2021083388 W CN2021083388 W CN 2021083388W WO 2021208708 A1 WO2021208708 A1 WO 2021208708A1
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WO
WIPO (PCT)
Prior art keywords
transistor
pixel
display
reset
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/083388
Other languages
English (en)
French (fr)
Inventor
姚远
叶帅
贾溪洋
朱正勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kunshan Govisionox Optoelectronics Co Ltd
Original Assignee
Kunshan Govisionox Optoelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kunshan Govisionox Optoelectronics Co Ltd filed Critical Kunshan Govisionox Optoelectronics Co Ltd
Priority to KR1020227014556A priority Critical patent/KR102631196B1/ko
Priority to JP2022528192A priority patent/JP7378618B2/ja
Priority to EP21787846.1A priority patent/EP4044161A4/en
Publication of WO2021208708A1 publication Critical patent/WO2021208708A1/zh
Priority to US17/690,373 priority patent/US11769444B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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Definitions

  • This application relates to the field of display technology, and in particular to a display panel and a display device.
  • the full screen has the characteristics of a larger screen-to-body ratio and a narrow frame, which can greatly improve the user's visual effect, and thus has received widespread attention.
  • a full-screen display device is used in order to realize the functions of self-timer, video call, and fingerprint recognition.
  • a special-shaped area is opened on the front of the display device, and the special-shaped area is used to install a camera, a receiver, fingerprint recognition, or physical buttons.
  • This application mainly provides a display panel and a display device to improve the display effect.
  • the first technical solution provided by this application is to provide a display panel including a first area and a second area, the first area includes a plurality of rows of first pixel rows, and the second area It includes a plurality of rows of second pixel rows, the first pixel row and the second pixel row include a plurality of pixel points, and the number of the pixel points in the first pixel row in each row is more than that in the second pixel row in each row.
  • the number of pixel points in the pixel row, wherein the plurality of pixels located in the first pixel row are multiple display pixels, and the multiple pixels located in the second pixel row are multiple display pixels Dots and a plurality of virtual pixel dots; the display pixel dots include a display pixel circuit, the virtual pixel dots include a virtual pixel circuit, the virtual pixel circuit includes a compensation unit, and the virtual pixel circuit is used to position the same
  • reset compensation is performed to reduce the voltage at the node of the light emitting device in the display pixel circuit after the display pixel circuits in the first area and the second area are reset. difference.
  • the display pixel circuit and the dummy pixel circuit include: a writing unit that receives a first scan signal to write a data signal to a driving node in a writing stage under the drive of the first scan signal; driving; A unit, connected to the writing unit through the drive node; a control unit, receiving an enable signal, and connected to the drive unit so that the drive unit is connected to the power signal line through the control unit; reset Unit, receiving a second scan signal, and connecting the driving node and the control unit to receive a reference signal driven by the second scan signal, and using the reference signal to compare the driving node and the The first node between the reset unit and the control unit is reset; wherein the control unit in the display pixel circuit is connected to the light-emitting device at the first node, and all of the virtual pixel circuits are connected to the light-emitting device at the first node.
  • the compensation unit is connected to the driving node.
  • the pixels located in the first pixel row and the second pixel row receive the same reference signal, and are located in the display pixel circuit and the dummy pixel circuit in the same second pixel row
  • the reset unit is connected to the same reference signal line.
  • the virtual pixel circuit does not include a light-emitting device.
  • the compensation unit is a compensation capacitor or a compensation resistor.
  • the compensation unit is the compensation capacitor, one end of which is connected to the driving node, and the other end is connected to the power signal line.
  • the number of the compensation capacitors is less than or equal to the number of the virtual pixels.
  • the number of compensation capacitors is the difference between the number of pixel points in the first pixel row and the second pixel row.
  • the second area includes a virtual pixel area
  • the virtual pixel area includes two perforated areas and an isolation area located between the two perforated areas
  • the virtual pixel points are located in the isolation area.
  • the writing unit includes: a first transistor including a first path end, a second path end, and a control end; the first path end of the first transistor is connected to a data signal line to receive a data signal; The second pass end of a transistor is connected to the driving unit and the control unit, the control end of the first transistor is connected to the first scan signal line to receive the first scan signal; the second transistor includes the first pass end, A second pass end and a control end, the first pass end of the second transistor is connected to the drive unit, the second pass end of the second transistor is connected to the drive unit and the control unit, the second transistor The control terminal of is connected to the first scan signal line to receive the first scan signal.
  • the driving unit includes: a third transistor, including a first path end, a second path end, and a control end, the first path end of the third transistor is connected to the control unit and the writing unit, the The second path end of the third transistor is connected to the control unit and the writing unit, and the control end of the third transistor is connected to the reset unit and the writing unit.
  • the reset unit includes: a first reset sub-unit, which receives a first scan reset sub-signal and the reference signal, and is connected to the driving node, so as to be in the first reset sub-period corresponding to the first scan reset sub-signal , Using the reference signal to reset the driving node; a second reset sub-unit, receiving a second scan reset sub-signal and the reference signal, and connected to the first node, so that the second scan reset sub-signal In the corresponding second reset sub-period, the first node is reset by using the reference signal.
  • the first reset subunit includes: a fourth transistor, including a first pass end, a second pass end, and a control end, the first pass end of the fourth transistor is connected to the driving node, and the fourth transistor The second path end of the transistor is connected to the reference signal line to receive the reference signal, and the control end of the fourth transistor is connected to the first scan reset sub-signal line to receive the first scan reset sub-signal.
  • the second reset subunit includes: a fifth transistor, including a first path end, a second path end, and a control end, the first path end of the fifth transistor is connected to the first node, and the fifth transistor The second path end of the transistor is connected to a reference signal line to receive the reference signal, and the control end of the fifth transistor is connected to a second scan reset sub-signal line to receive the second scan reset sub-signal.
  • the control unit includes: a sixth transistor, including a first path end, a second path end, and a control end, the first path end of the sixth transistor is connected to the power signal line to receive the power signal, The second path end of the sixth transistor is connected to the driving unit, the control end of the sixth transistor is connected to an enable signal line to receive the enable signal;
  • the seventh transistor includes a first path end and a second path Terminal and control terminal, the first path terminal of the seventh transistor is connected to the second path terminal of the sixth transistor, the second path terminal of the seventh transistor is connected to the first node, and the The control terminal is connected to the enable signal line and receives the enable signal.
  • the display pixel circuit and the virtual pixel circuit further include: a storage capacitor, including a first path end and a second path end, the first path end of the storage capacitor is connected to the power signal line, and the storage capacitor The second passage end is connected to the drive unit.
  • the second technical solution provided by the present application is to provide a display device including the display panel described in any one of the above.
  • the present application provides a compensation unit in the virtual pixel circuit, so that the virtual pixel circuit compensates the display pixel circuit in the second pixel row of the same row when resetting, thereby reducing After the display pixel circuits in the small first area and the second area are reset, the voltage difference at the node of the light-emitting device improves the display effect.
  • FIG. 1a and 1b are schematic diagrams of an embodiment of a display panel
  • FIG. 2 is a schematic structural diagram of an embodiment of display pixel circuits in the first area and the second area of the display panel of the present application;
  • FIG. 3 is a schematic structural diagram of an embodiment of a virtual pixel circuit in the second area of the present application.
  • 4a is a schematic diagram of voltage simulation at the first node of the first area and the second area of the prior art display panel in the reset phase;
  • 4b is a schematic diagram of voltage simulation at the first node of the first area and the second area of the display panel of the present application in the reset phase;
  • FIG. 5 is a schematic structural diagram of an embodiment of a display device of the present application.
  • a special-shaped area is opened on the front of the display device, and the special-shaped area is used to install a camera, a receiver, fingerprint recognition, or physical buttons.
  • setting a special-shaped area on the display device will change the number of pixels or load in the same row area corresponding to the special-shaped area, which will affect the display area in the same row as the special-shaped area and connected to the same reference signal line during the reset phase.
  • the reset voltage of the pixel circuit in the reset phase causes a large difference in the voltage at the node of the light-emitting device (that is, the anode of the light-emitting device) after the pixel circuit in the abnormal area and the rest of the area is reset, resulting in a large difference in the rise time of the anode voltage of the light-emitting device , Resulting in a large difference in the light-emitting time of the pixels in the irregular area and other areas within a frame, which in turn makes the display area corresponding to the irregular area and the rest of the display area display unevenly, resulting in abnormal display.
  • a common display panel provided with a special-shaped area has a perforated screen or a notch screen.
  • a special-shaped area 201 is provided in the display area of the display panel.
  • the irregular area 201 includes at least two perforated areas 122, and the perforated areas 122 are separated by an isolation area 123, so that the position of the perforated area 122 will be missing pixels, and since the isolation area 123 is not displayed, it will also lose light.
  • Device As shown in Fig. 1b, taking Liu Haiping as an example, a special-shaped area 201 is provided in the display area.
  • the special-shaped area 201 is used to place devices such as a camera. The existence of the special-shaped area 201 makes the display area lack some pixels.
  • pixel points in pixel rows located in different regions receive the same reference signal, and the pixel driving circuits of pixels located in the same row are connected to the same reference signal line, so that the light-emitting devices in the pixel driving circuits located in the same row are reset during the reset phase.
  • the anode voltage of the light-emitting device in the display pixel of the irregular area 201 will be the same as the light emission in the display pixel of the normal display area.
  • the difference in the anode voltage of the device makes the difference in the rise time of the anode voltage of the light-emitting device larger, which results in a larger difference in the light-emitting time of the pixels in the irregular area and other areas within a frame, thereby causing uneven display during the display stage.
  • the display panel includes a first area 11 and a second area 12.
  • the first area 11 includes multiple rows of first pixel rows
  • the second area 12 includes multiple rows of second pixel rows
  • the first pixel row and the second pixel row include multiple pixel points.
  • the second area 12 is provided with a special-shaped area 201, it will cause the second area 12 to miss some pixels.
  • the number of pixels in each second pixel row in the second area 12 is smaller than that of the second area 12
  • the number of pixels in each first pixel row in 11.
  • the multiple pixels located in the first pixel row are multiple display pixels
  • the multiple pixels located in the second pixel row are multiple display pixels and multiple virtual pixels.
  • the display pixel includes a display pixel circuit
  • the virtual pixel includes a virtual pixel circuit
  • the virtual pixel circuit includes a compensation unit
  • the virtual pixel circuit is used to reset and compensate the display pixel circuit located under the same second pixel row in the reset phase, Therefore, after the display pixel circuits of the first area 11 and the second area 12 are reset, the voltage difference at the node of the light-emitting device (that is, the anode position of the light-emitting device) in the display pixel circuit is reduced, and the difference between the first area 11 and the second area 12 is reduced. The difference in luminescence, thereby improving the display effect.
  • the dummy pixel circuit and the reset unit of the display pixel circuit in the same second pixel row in the second area 12 are connected to the same reference signal line. Since there are virtual pixels in each second pixel row in the second area 12 and the number of pixels in the second pixel row in the second area 12 is less than the number of pixels in the first pixel row in the first area, it is reset During the phase, the reset voltage resets different numbers of display pixel circuits, which will cause the display pixel circuits in the first region 11 and the display pixel circuits in the second region 12 to have different voltages at the anodes of the light-emitting devices.
  • the display stage causes display differences.
  • the prior art often adopts a method of connecting multiple reference signal lines, that is, the second pixel row located in the second area 12 and the first pixel row located in the first area 11 are connected to different reference signal lines, so that The reset voltages of the pixel circuits in the second area 12 and the first area 11 are the same, so that the display effects of different areas of the display panel are consistent, but there are general problems that the wiring is complicated and the display effect is improved.
  • the pixels of the first pixel row located in the first area 11 and the second pixel row located in the second area 12 receive the same reference signal, and the virtual pixel circuit and the reset unit of the display pixel circuit located in the same second pixel row Connecting the same reference signal line can not only simplify the wiring of the display panel, but also during the reset phase, the compensation unit in the dummy pixel circuit will also perform load compensation on the display pixel circuit in the second area 12, thereby making the first area 11
  • the voltage at the anode of the light-emitting device in the display pixel circuit in the display pixel circuit in the second area 12 tends to be the same, so that the first area 11 and the second area 12 are uniformly displayed during display, and the display is improved. Effect.
  • the virtual pixel circuit is arranged at the position of the isolation area 123. If the display panel is a notch as shown in FIG. 1b, the virtual pixel The circuit is arranged at the edge position of the special-shaped area 201, or may also be arranged at the frame position of the display panel, as long as it can achieve the purpose of compensating the display pixel circuit of the second area 12, and will not be repeated here.
  • FIG. 2 is a schematic structural diagram of an embodiment of the display pixel circuit in the first area and the second area
  • FIG. 3 is the virtual pixel in the second area
  • the display pixel circuit and the virtual pixel circuit both include: a writing unit 402, a driving unit 403, a control unit 404, and a reset unit 405.
  • the writing unit 402 is used to receive the first scan signal S1 to write the data signal Data to the driving node n2 during the writing phase driven by the first scan signal S1; the driving unit 403 is connected to the driving node n2 for writing Unit 402; the control unit 404 receives the enable signal EM, and is connected to the drive unit 403 so that the drive unit 403 is connected to the power signal line by the control unit 404; the reset unit 405 receives the second scan signal, and connects the drive node n2 and the control The unit 404 receives the reference signal Verf driven by the second scan signal, and uses the reference signal Verf to reset the driving node n2 and the first node n1 between the reset unit 405 and the control unit 404.
  • the control unit 404 in the display pixel circuit is connected to the light emitting device 401 at the first node n1 connected to the reset unit 405.
  • the compensation unit 406 is connected to the driving node n2 of the driving unit 403 in the virtual pixel circuit.
  • the control unit 404 in the dummy pixel circuit is not connected to the light emitting device 401 at the first node n1 connected to the reset unit 405.
  • the display pixels of the first pixel row and the display pixels of the second pixel row are displayed in the display stage, so the display pixels of the first pixel row and the display pixels of the second pixel row have light-emitting devices , And the virtual pixels are not displayed, so the virtual pixels may not include light-emitting devices.
  • the light emitting device 401 may be an organic light emitting diode OLED, which may include a red OLED, a blue OLED, and a green OLED. In another embodiment, the light emitting device 401 may also include a white OLED. It is not limited here, and the specific display is mainly performed on the display panel, as long as the display effect required by the display panel can be achieved.
  • the compensation unit 406 is a compensation capacitor or a compensation resistor.
  • the compensation unit 406 in the virtual pixel circuit is a compensation capacitor, one end of which is connected to the driving node n2, and the other end is connected to the power signal line to receive the power signal VDD.
  • the compensation unit 406 in the virtual pixel circuit can also be a compensation resistor, which can also be a compensation capacitor as shown in FIG. 3, one end is connected to the driving node n2, and the other end is connected to the power signal line. To receive the power signal VDD.
  • a compensation capacitor can be connected to the driving node n2 of each virtual pixel circuit; in another embodiment, if the display pixel circuit in the second area 12 and the second area can be made after the reset phase is completed
  • the voltage at the first node n1 (anode of the light-emitting device) of the display pixel circuit of 12 tends to be the same, and a compensation capacitor can also be connected at the position of the driving node n2 of part of the virtual pixel circuit. That is, the number of compensation capacitors is less than or equal to the number of virtual pixels. Specifically, in an embodiment, the number of compensation capacitors is the difference between the number of pixels in the first pixel row and the second pixel row.
  • the second pixel row of each row is missing 40 pixels.
  • Forty virtual pixel circuits with compensation capacitors are arranged in the second pixel row, and correspondingly connected to the reference signal line of each row.
  • the second area 12 may include a virtual pixel area.
  • the virtual pixel area includes two perforated areas 122 and an isolation area 123 located between the two perforated areas.
  • the virtual pixels are located in the isolation area 123.
  • the virtual pixels can be arranged in the edge position of the special-shaped area 201, and the virtual pixels can also be arranged at the border of the display panel.
  • the display pixel circuit and the virtual pixel circuit can be arranged in a variety of ways.
  • the display pixel circuit and the virtual pixel circuit adopt the 7T1C circuit as an example for description.
  • write The unit 402 includes: a first transistor M1 and a second transistor M2.
  • the first transistor M1 includes a first channel terminal, a second channel terminal, and a control terminal.
  • the first channel terminal of the first transistor M1 is connected to the data signal line to receive the data signal Data; the second channel terminal of the first transistor M1 is connected to The driving unit 403 and the control unit 404, specifically, the second path end of the first transistor M1 is connected to the first path end of the third transistor M3 in the driving unit 403 and the second path end of the sixth transistor M6 in the control unit 404 ; The control end of the first transistor M1 is connected to the first scan signal line to receive the first scan signal S1.
  • the second transistor M2 includes a first pass end, a second pass end, and a control end. The first pass end of the second transistor M2 is connected to the driving unit 403. Specifically, the first pass end of the second transistor M2 is connected to the driving unit 403.
  • the control end of the third transistor M3 ie, the driving node n2 in the second transistor M2; the second pass end of the second transistor M2 is connected to the second pass end of the third transistor M3 in the driving unit 403 and the seventh transistor M7 in the control unit 404
  • the driving unit 403 includes: a third transistor M3.
  • the third transistor M3 includes a first pass end, a second pass end, and a control end.
  • the first pass end of the third transistor M3 is connected to the control unit 404 and the writing unit 402.
  • the first pass of the third transistor M3 The end is connected to the second pass end of the sixth transistor M6 in the control unit 404 and the second pass end of the first transistor M1 in the writing unit 402; the second pass end of the third transistor M3 is connected to the control unit 404 and the writing unit 402.
  • the second path end of the third transistor M3 is connected to the first path end of the seventh transistor M7 in the control unit 404 and the second path end of the second transistor M2 in the writing unit 402; the third transistor M3
  • the control terminal of the third transistor M3 is connected to the reset unit 405 and the writing unit 402.
  • the control terminal of the third transistor M3 is connected to the first pass end of the fourth transistor M4 in the reset unit 405 and the second transistor M2 in the writing unit 402. The first passage end.
  • the reset unit 405 is used to receive the second scan signal, and is connected to the driving node n2 and the control unit 404 to receive the reference signal Verf under the driving of the second scan signal, and use the reference signal Verf to drive the node
  • the first node n1 between n2 and the reset unit 405 and the control unit 404 is reset.
  • the second scan signal includes a first scan reset sub-signal S2 and a second scan reset sub-signal S3; the reset unit 405 includes: a first reset sub-unit and a second sub-reset unit.
  • the first sub-reset unit receives the first scan reset sub-signal S2 and the reference signal Verf, and is connected to the driving node n2, so as to use the reference signal Verf to drive during the first reset sub-period corresponding to the first scan reset sub-signal S2
  • Node n2 is reset.
  • the second reset subunit is used to receive the second scan reset sub-signal S3 and the reference signal Verf, and is connected to the first node n1 to use the reference signal Verf to pair during the second reset sub-period corresponding to the second scan reset sub-signal S3
  • the first node n1 is reset.
  • the first reset subunit includes: a fourth transistor M4.
  • the fourth transistor M4 includes a first pass end, a second pass end, and a control end.
  • the first pass end of the fourth transistor M4 is connected to the driving unit 403.
  • the first pass end of the fourth transistor M4 is connected to the driving unit 403.
  • the control terminal of the third transistor M3 ie, drive node n2 in the third transistor M3;
  • the second path terminal of the fourth transistor M4 is connected to the reference signal line to receive the reference signal Verf;
  • the control terminal of the fourth transistor M4 is connected to the first scan reset sub-signal Line to receive the first scan reset sub-signal S2.
  • the second reset subunit includes: a fifth transistor M5.
  • the fifth transistor M5 includes a first pass end, a second pass end, and a control end.
  • the first pass end of the fifth transistor M5 is connected to the first node n1.
  • the first pass end of the fifth transistor M5 is connected to the control unit
  • the second path end of the seventh transistor M7 in 404, in the display pixel, the first path end of the fifth transistor M5 is also connected to the anode of the light emitting device 401; the second path end of the fifth transistor M5 is connected to the reference signal line,
  • the control terminal of the fifth transistor M5 is connected to the second scan reset sub-signal line to receive the second scan reset sub-signal S3.
  • the control unit 404 includes: a sixth transistor M6 and a seventh transistor M7.
  • the sixth transistor M6 includes a first path end, a second path end, and a control end.
  • the first path end of the sixth transistor M6 is connected to the power signal line to receive the power signal VDD, and the second path of the sixth transistor M6
  • the second path end of the sixth transistor M6 is connected to the first path end of the third transistor M3 in the driving unit 403, and the control end of the sixth transistor M6 is connected to the enable signal line to receive the enable signal line.
  • Signal EM The seventh transistor M7 includes a first path end, a second path end, and a control end.
  • the first path end of the seventh transistor M7 is connected to the second path end of the sixth transistor M6, and the second path end of the seventh transistor M7 is connected to The first node n1 and the control end of the seventh transistor M7 are connected to the enable signal line and receive the enable signal EM.
  • the display pixel circuit and the dummy pixel circuit further include: a storage capacitor Cst, which includes a first path end and a second path end, the first path end of the storage capacitor Cst is connected to the power signal line, and the first path end of the storage capacitor Cst The two path ends are connected to the control end of the third transistor M3.
  • the fourth transistor M4 and the fifth transistor M5 in the reset unit 405 are turned on, and the driving node n2 of the driving unit 403 and the anode of the light emitting device 401 (ie, the first node n1) are reset by the reference signal Verf.
  • the first pixel row and the second pixel row receive the same reference signal.
  • the voltage at the anode of the light-emitting device in the display pixel circuit in the first pixel row in the first area 11 and the second pixel row in the second area 12 is different, and the During the phase and the light-emitting phase, the display of the first area 11 and the second area 12 will be uneven, and the display effect will be poor.
  • a virtual pixel connected to the same reference line number line is provided on the second pixel row of each row, and a compensation unit is connected to the driving node n2 of the virtual pixel.
  • the compensation unit compensates for the pixel points of the second pixel row located in the same row, so that the anode potentials of the light-emitting devices of the display pixel circuits in the first area 11 and the second area 12 tend to be the same, thereby reducing the first area 11
  • the voltage difference between the anodes of the light-emitting devices of the display pixel circuits in the second area 12 and the second area 12 makes the display of the first area 11 and the second area 12 uniform and improves the display effect.
  • This embodiment takes a 7T1C circuit as an example for description.
  • the method of this embodiment can also be applied to, for example, a 6T1C circuit, or can also be applied to a 3T1C circuit or an 8T1C circuit, which is not limited here.
  • the anode voltages of the light-emitting devices in the first region and the second region can be made consistent after the reset phase is completed.
  • FIG. 4a is a schematic diagram of voltage simulation at the first node of the first area and the second area of the prior art display panel in the reset phase.
  • the voltage of the anode of the light-emitting device of the display pixel circuit in the second region 12 ie, the first node n1
  • the anode of the light-emitting device of the display pixel circuit in the first region 11 ie, the first node n1
  • the voltage of node n1 is -2.6056V after the reset phase is completed. It can be seen that in the existing display panel, after the reset phase is completed, the difference between the anode voltages of the light-emitting devices of the display pixel circuit in the first region and the second region is 40.1 mV.
  • Fig. 4b is a schematic diagram of voltage simulation at the first node of the first area and the second area of the display panel of the present application in the reset phase.
  • the anode voltage of the light emitting device of the display pixel circuit in the second area is -2.5997V after the reset phase is completed, and the anode voltage of the light emitting device of the display pixel circuit in the first area After the reset phase is completed, it is -2.5999V.
  • the difference between the anode voltages of the light-emitting devices of the display pixel circuits in the first region and the second region is 0.2mV.
  • the technical solution of the present application significantly reduces the anode voltage of the light-emitting device after the reset phase of the display pixel elements in the first area and the second area is completed.
  • the difference between the anode voltage of the light-emitting device of the display pixel circuit in the first area and the second area of the application is 0.2mV due to the accuracy of the simulator.
  • the anode voltages of the light-emitting devices of the display pixel circuits in the first area and the second area are the same.
  • the display panel provided by the present application may be any one of a double-sided display panel, a flexible display panel, and a full-screen display panel.
  • Flexible display panels can be applied to curved electronic devices; double-sided display panels can be applied to panels that allow people on both sides of the display panel to see the display content; full-screen display panels can be applied to full-screen mobile phones or other devices, This is not limited.
  • the virtual pixel circuits further include a compensation unit connected to the driving node and the power signal line to be in the reset phase Compensating the anode voltage of the light emitting device of the display pixel circuit in the second area so that the anode voltage of the light emitting device of the display pixel circuit in the second area tends to be consistent with the anode voltage of the light emitting device of the display pixel circuit in the first area, Furthermore, the display difference between the first area and the second area in the display stage is reduced, and the display effect is improved.
  • FIG. 5 is a schematic structural diagram of an embodiment of the display device provided by this application.
  • the display device includes the above-mentioned display panel.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.
  • a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator.
  • Other indispensable components of the display panel are understood by those of ordinary skill in the art, and will not be repeated here, nor should they be used as a limitation to the application.
  • the embodiment of the display device please refer to the embodiment of the above-mentioned display panel, and the repetition will not be repeated.
  • the display panel and the display device only describe some related structures, and the other structures are the same as the structure of the display panel and the display device in the prior art, and will not be repeated here.

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Abstract

一种显示面板及显示装置，显示面板包括第一区域（11）和第二区域（12），第一区域（11）包括多行第一像素行，第二区域（12）包括多行第二像素行，第一像素行和第二像素行包括多个像素点，每行第一像素行的像素点的数量多于每行第二像素行的像素点数量，其中位于第一像素行的像素点为显示像素点，位于第二像素行的多个像素点为多个显示像素点和多个虚拟像素点。显示像素点包括显示像素电路，虚拟像素点包括虚拟像素电路，虚拟像素电路包括补偿单元（406），虚拟像素电路用于对位于同一第二像素行的显示像素电路复位时进行复位补偿，从而减小第一区域（11）和第二区域（12）的显示像素电路复位后，显示像素电路中发光器件（410）节点（n1）处的电压差异，进而提高显示效果。

Description

一种显示面板及显示装置 技术领域
本申请涉及显示技术领域，特别是涉及一种显示面板及显示装置。
背景技术
全面屏以其具有较大的屏占比、窄边框的特点，可以大大改善使用者的视觉效果，从而受到广泛的关注。目前，采用全面屏的显示装置中，为了实现自拍、可视通话以及指纹识别的功能。通常会在显示装置的正面开设异形区域，该异形区域用于安装摄像头、听筒、指纹识别或者实体按键。
但是在显示装置上设置异形区域，会使得像素数量与负载发生变化，进而引起像素显示不均匀的现象，从而导致显示异常。
发明内容
本申请主要提供一种显示面板及显示装置，用以提高显示效果。
为解决上述技术问题，本申请提供的第一个技术方案为：提供一种显示面板，包括第一区域和第二区域，所述第一区域包括多行第一像素行，所述第二区域包括多行第二像素行，所述第一像素行和所述第二像素行包括多个像素点，每行所述第一像素行的所述像素点的数量多于每行所述第二像素行的所述像素点数量，其中位于所述第一像素行的多个所述像素点为多个显示像素点，位于第二像素行的多个所述像素点为多个所述显示像素点和多个虚拟像素点；所述显示像素点包括显示像素电路，所述虚拟像素点包括虚拟像素电路，所述虚拟像素电路包括补偿单元，所述虚拟像素电路用于对位于同一所述第二像素行的所述显示像素电路复位时进行复位补偿，从而减小所述第一区域和所述第二区域的所述显示像素电路复位后，所述显示像素电路中发光器件节点处的电压差异。
其中，所述显示像素电路和所述虚拟像素电路包括：写入单元，接收第一扫描信号，以在所述第一扫描信号的驱动下而于写入阶段向驱动节点写入数据信号；驱动单元，藉由所述驱动节点而连接所述写入单元；控制单元，接收使能信号，并连接所述驱动单元以使所述驱动单元藉由所述控制单元而连接至电源信号线；复位单元，接收第二扫描信号，并连接所述驱动节点和所述控制单元，以在所述第二扫描信号的驱动下而接收参考信号，并利用所述参考信号对所述驱动节点和所述复位单元与所述控制单元之间的第一节点进行复位；其中，所述显示像素电路中的所述控制单元在所述第一节点处连接所述发光器件，所述虚拟像素电路中的所述驱动节点处连接所述补偿单元。
其中，位于所述第一像素行和所述第二像素行的所述像素点接收同一所述参考信号，且位于同一所述第二像素行的所述显示像素电路和所述虚拟像素电路中的所述复位单元连接同一条参考信号线。
其中，所述虚拟像素电路不包括发光器件。
其中，所述补偿单元为补偿电容或补偿电阻。
其中，所述补偿单元为所述补偿电容，其一端连接所述驱动节点，而另一端连接至所述电源信号线。
其中，所述补偿电容的数量小于等于所述虚拟像素点的数量。
其中，所述补偿电容的数量为所述第一像素行和所述第二像素行中所述像素点数量的差值。
其中，所述第二区域包括虚拟像素区，所述虚拟像素区包括两个打孔区和位于两个所述打孔区之间的隔离区，所述虚拟像素点位于所述隔离区中。
其中，所述写入单元包括：第一晶体管，包括第一通路端、第二通路端及控制端，所述第一晶体管的第一通路端连接数据信号线，以接收数据信号，所述第一晶体管的第二通路端连接所述驱动单元及所述控制单元，所述第一晶体管的控制端连接第一扫描信号线，以接收第一扫描信号；第二晶体管，包括第一通路端、第二通路端及控制端，所述第二晶体管的第一通路端连接所述驱动单元，所述第二晶体管的第二通路端 连接所述驱动单元及所述控制单元，所述第二晶体管的控制端连接所述第一扫描信号线，以接收所述第一扫描信号。
其中，所述驱动单元包括：第三晶体管，包括第一通路端、第二通路端及控制端，所述第三晶体管的第一通路端连接所述控制单元及所述写入单元，所述第三晶体管的第二通路端连接所述控制单元及所述写入单元，所述第三晶体管的控制端连接所述复位单元以及所述写入单元。
其中，所述复位单元包括：第一复位子单元，接收第一扫描复位子信号和所述参考信号，并连接所述驱动节点，以在第一扫描复位子信号所对应的第一复位子期间，利用所述参考信号对所述驱动节点进行复位；第二复位子单元，接收第二扫描复位子信号和所述参考信号，并连接所述第一节点，以在第二扫描复位子信号所对应的第二复位子期间，利用所述参考信号对所述第一节点进行复位。
其中，所述第一复位子单元包括：第四晶体管，包括第一通路端、第二通路端及控制端，所述第四晶体管的第一通路端连接所述驱动节点，所述第四晶体管的第二通路端连接参考信号线，以接收所述参考信号，所述第四晶体管的控制端连接第一扫描复位子信号线，以接收所述第一扫描复位子信号。
其中，所述第二复位子单元包括：第五晶体管，包括第一通路端、第二通路端及控制端，所述第五晶体管的第一通路端连接所述第一节点，所述第五晶体管的第二通路端连接参考信号线，以接收所述参考信号，所述第五晶体管的控制端连接第二扫描复位子信号线，以接收所述第二扫描复位子信号。
其中，所述控制单元包括：第六晶体管，包括第一通路端、第二通路端及控制端，所述第六晶体管的第一通路端连接所述电源信号线，以接收所述电源信号，所述第六晶体管的第二通路端连接所述驱动单元，所述第六晶体管的控制端连接使能信号线，接收所述使能信号；第七晶体管，包括第一通路端、第二通路端及控制端，所述第七晶体管的第一通路端连接所述第六晶体管的第二通路端，所述第七晶体管的第二通路端连接所述第一节点，所述第七晶体管的控制端连接使能信号线，接收 所述使能信号。
其中，所述显示像素电路及所述虚拟像素电路还包括：存储电容，包括第一通路端及第二通路端，所述存储电容的第一通路端连接所述电源信号线，所述存储电容的第二通路端连接所述驱动单元。
为解决上述技术问题，本申请提供的第二个技术方案为：提供一种显示装置，所述显示装置包括上述任一项所述的显示面板。
本申请的有益效果：区别现有技术，本申请通过在虚拟像素电路中设置补偿单元，以使得虚拟像素电路在复位时对位于同一行的第二像素行中的显示像素电路进行补偿，从而减小第一区域及第二区域的显示像素电路在复位后，发光器件节点处的电压差异，进而提高显示效果。
附图说明
图1a及图1b是显示面板的一实施例的结构示意图；
图2是本申请显示面板的第一区域及第二区域中的显示像素电路的一实施例的结构示意图；
图3是本申请第二区域中的虚拟像素电路的一实施例的结构示意图；
图4a是现有技术显示面板在复位阶段的第一区域及第二区域的第一节点处的电压仿真示意图；
图4b是本申请显示面板在复位阶段的第一区域及第二区域的第一节点处的电压仿真示意图；
图5是本申请显示装置的一实施例的结构示意图。
具体实施方式
目前，全面屏的显示装置中，为了实现自拍、可视通话以及指纹识别的功能。通常会在显示装置的正面开设异形区域，该异形区域用于安装摄像头、听筒、指纹识别或者实体按键。但是在显示装置上设置异形区域，会使得与异形区域对应的同一行区域中的像素点数量或者负载发生变化，在复位阶段影响到与异形区域位于同一行且连接同一参考信号线的显示区域的像素电路在复位阶段的复位电压，导致异形区域和其余 区域的像素电路在复位后，发光器件节点处(即发光器件阳极)的电压差异较大，导致发光器件阳极电压上升时间产生的差异较大，导致一帧内异形区和其他区域的像素点发光时间差异较大，进而使得与异形区域对应的显示区域与其余显示区域显示不均匀，从而导致显示异常。
具体的，常见的设置有异形区的显示面板有打孔屏或者刘海屏，如图1a所示，以打孔屏中的双孔屏为例，在显示面板的显示区内设置异形区201，异形区201中包括至少两个打孔区122，打孔区122之间通过隔离区123隔离，这样打孔区122位置会缺失像素点，且由于隔离区123不进行显示，其还会缺失发光器件。如图1b所示，以刘海屏为例，在显示区内设置异形区201，异形区201用于放置摄像头等装置，异形区201的存在使得显示区缺失部分像素点。
一般的，位于不同区域的像素行中的像素点接收同一参考信号，位于同一行的像素点的像素驱动电路连接同一参考信号线，以在复位阶段对位于同一行的像素驱动电路中的发光器件的阳极进行复位，但是由于异形区201像素行像素点的缺失，会使得在复位阶段完成后，异形区201的显示像素点中的发光器件的阳极电压会与正常显示区显示像素点中的发光器件的阳极电压产生差异，使得发光器件阳极电压上升时间产生的差异较大，导致一帧内异形区和其他区域的像素点发光时间差异较大，进而在显示阶段造成显示不均匀的现象。
为了解决上述问题，以达到本申请消除显示差异，提高显示效果的目的，下面结合附图，对本申请实施例提供的显示面板及显示装置的具体实施方式进行详细的说明。
本申请提供一种显示面板，结合图1a及图1b，所述显示面板包括第一区域11和第二区域12。其中，第一区域11包括多行第一像素行，第二区域12包括多行第二像素行，第一像素行和第二像素行包括多个像素点。具体的，由于第二区域12中设置有异形区201，其会导致第二区域12缺失部分像素点，具体的，第二区域12中每一第二像素行的像素点的数量小于第二区域11中每一第一像素行的像素点的数量。其中，位于第一像素行的多个像素点为多个显示像素点，位于第二像素行的多 个像素点为多个显示像素点和多个虚拟像素点。进一步地，显示像素点包括显示像素电路，虚拟像素点包括虚拟像素电路，虚拟像素电路包括补偿单元，虚拟像素电路用于在复位阶段对位于同一第二像素行下的显示像素电路进行复位补偿，从而减小第一区域11和第二区域12的显示像素电路复位后，显示像素电路中发光器件节点处(即发光器件阳极位置)的电压差异，减少第一区域11和第二区域12之间的发光差异，进而提高显示效果。
具体的，在一实施例中，虚拟像素电路与位于第二区域12中同一第二像素行的显示像素电路的复位单元连接同一条参考信号线。由于在第二区域12中每一第二像素行存在虚拟像素点且第二区域12中的第二像素行的像素点数量少于第一区域第一像素行的像素点的数量，即在复位阶段时，复位电压对不同数量的显示像素电路进行复位，这会导致第一区域11中的显示像素电路与第二区域12中的显示像素电路中的发光器件的阳极处的电压不一致，进而在显示阶段造成显示差异。通常为了使得复位电压一致，现有技术往往采用连接多条参考信号线的方式即位于第二区域12的第二像素行和位于第一区域11的第一像素行连接不同的参考信号线，使第二区域12和第一区域11处像素电路的复位电压相同，从而使得显示面板不同区域显示效果一致，但存在走线复杂且显示效果改善一般的问题。本申请中位于第一区域11的第一像素行和位于第二区域12的第二像素行的像素点接收同一参考信号，且位于同一第二像素行的虚拟像素电路与显示像素电路的复位单元连接同一条参考信号线，不仅能够简化显示面板走线，并且在复位阶段时，虚拟像素电路中的补偿单元还会对第二区域12中的显示像素电路进行负载补偿，进而使得第一区域11中的显示像素电路与第二区域12中的显示像素电路中的发光器件的阳极处的电压趋于一致，以此在进行显示时，使得第一区域11与第二区域12显示均匀，提高显示效果。
在一实施例中，若显示面板为如图1a所述的双孔屏，则将虚拟像素电路设置于隔离区123位置，若显示面板为如图1b所示的刘海屏，则可以将虚拟像素电路设置于异形区201的边缘位置，或者还可以设置在 显示面板的边框位置，只要能够使其达到对第二区域12的显示像素电路进行补偿的目的即可，在此不再赘述。
在一实施例中，如图2及图3所示，其中，图2为第一区域及第二区域中的显示像素电路的一实施例的结构示意图，图3为第二区域中的虚拟像素电路的一实施例的结构示意图。其中，显示像素电路和虚拟像素电路均包括：写入单元402、驱动单元403、控制单元404及复位单元405。写入单元402用于接收第一扫描信号S1，以在第一扫描信号S1的驱动下而于写入阶段向驱动节点n2写入数据信号Data；驱动单元403藉由驱动节点n2而连接写入单元402；控制单元404接收使能信号EM，并连接驱动单元403以使驱动单元403藉由控制单元404而连接至电源信号线；复位单元405接收第二扫描信号，并连接驱动节点n2和控制单元404，以在第二扫描信号的驱动下而接收参考信号Verf，并利用参考信号Verf对驱动节点n2和复位单元405与控制单元404之间的第一节点n1进行复位。
其中，如图2所示的显示像素电路的结构示意图所示，显示像素电路中的控制单元404在与复位单元405连接的第一节点n1处连接发光器件401。如图3所示的显示像素电路的结构示意图所示，虚拟像素电路中的驱动单元403的驱动节点n2处连接补偿单元406。且虚拟像素电路中的控制单元404在与复位单元405连接的第一节点n1处未连接发光器件401。
在一实施例中，第一像素行的显示像素点与第二像素行的显示像素点在显示阶段进行显示，因此第一像素行的显示像素点与第二像素行的显示像素点具有发光器件，而虚拟像素点不进行显示，因此虚拟像素点可以不包括发光器件。发光器件401可以为有机发光二极管OLED，其可以包括红色OLED、蓝色OLED及绿色OLED，在另一实施例中，发光器件401还可以包括白色OLED。在此不作限定，具体以显示面板上进行显示为主，只要能够达到显示面板需要的显示效果即可。
在一实施例中，补偿单元406为补偿电容或补偿电阻。具体的，如图3所示，所述虚拟像素电路中的补偿单元406为补偿电容，其一端连 接驱动节点n2，而另一端连接至电源信号线，以接收电源信号VDD。在另一实施例中，虚拟像素电路中的补偿单元406还可以为补偿电阻，其也可以为如图3所示的补偿电容一样，一端连接驱动节点n2，而另一端连接至电源信号线，以接收电源信号VDD。只要能够在复位阶段起到补偿作用，以使得第二区域12的显示像素电路与第一区域11的显示像素电路的第一节点n1(发光器件的阳极)处的电压趋于一致即可，在此不再赘述。
在一实施例中，每一虚拟像素电路的驱动节点n2处均可连接一个补偿电容；在另一实施例中，若能够使得在复位阶段完成后第二区域12的显示像素电路与第二区域12的显示像素电路的第一节点n1(发光器件的阳极)处的电压趋于一致，也可以在部分虚拟像素电路的驱动节点n2的位置处连接补偿电容。即补偿电容的数量小于等于所述虚拟像素点的数量。具体的，在一实施例中，补偿电容的数量为所述第一像素行和所述第二像素行中所述像素点数量的差值。例如，以刘海屏为例进行说明，若异形区201的位置缺失200个像素点，异形区包括5行第二像素行，则每一行第二像素行缺失40个像素点，则可在每一行第二像素行中设置40个具有补偿电容的虚拟像素电路，并使其对应连接每一行的参考信号线。
如图1a所示，为了保证窄边框设计，第二区域12可以包括虚拟像素区，虚拟像素区包括两个打孔区122和位于两个所述打孔区之间的隔离区123，所述虚拟像素点位于所述隔离区123中。
在另一实施例中，若显示面板为如图1b所示，则可以将虚拟像素点设置于异形区201的边缘位置中，还可以将虚拟像素点设置于显示面板的边框处。
本申请中显示像素电路及虚拟像素电路的具体设置方式可以有多种，本实施例中以显示像素电路及虚拟像素电路采用7T1C电路为例进行说明，具体的，在一7T1C电路中，写入单元402包括：第一晶体管M1及第二晶体管M2。第一晶体管M1包括第一通路端、第二通路端及控制端，其中，第一晶体管M1的第一通路端连接数据信号线，以接收 数据信号Data；第一晶体管M1的第二通路端连接驱动单元403及控制单元404，具体的，第一晶体管M1的第二通路端连接驱动单元403中的第三晶体管M3的第一通路端及控制单元404中的第六晶体管M6的第二通路端；第一晶体管M1的控制端连接第一扫描信号线，以接收第一扫描信号S1。第二晶体管M2包括第一通路端、第二通路端及控制端，其中，第二晶体管M2的第一通路端连接驱动单元403，具体的，第二晶体管M2的第一通路端连接驱动单元403中的第三晶体管M3的控制端(即驱动节点n2)；第二晶体管M2的第二通路端连接驱动单元403中的第三晶体管M3的第二通路端及控制单元404中的第七晶体管M7的第一通路端；第二晶体管M2的控制端连接第一扫描信号线，以接收第一扫描信号S1。
其中，驱动单元403包括：第三晶体管M3。第三晶体管M3包括第一通路端、第二通路端及控制端，其中，第三晶体管M3的第一通路端连接控制单元404及写入单元402，具体的，第三晶体管M3的第一通路端连接控制单元404中的第六晶体管M6的第二通路端及写入单元402中的第一晶体管M1的第二通路端；第三晶体管M3的第二通路端连接控制单元404及写入单元402，具体的，第三晶体管M3的第二通路端连接控制单元404中的第七晶体管M7的第一通路端及写入单元402中的第二晶体管M2的第二通路端；第三晶体管M3的控制端连接复位单元405及写入单元402，具体的，第三晶体管M3的控制端连接复位单元405中的第四晶体管M4的第一通路端及写入单元402中的第二晶体管M2的第一通路端。
在本实施例中，复位单元405用于接收第二扫描信号，并连接驱动节点n2和控制单元404，以在第二扫描信号的驱动下而接收参考信号Verf，并利用参考信号Verf对驱动节点n2和复位单元405与控制单元404之间的第一节点n1进行复位。在一具体实施例中，第二扫描信号包括第一扫描复位子信号S2和第二扫描复位子信号S3；复位单元405包括：第一复位子单元及第二子复位单元。其中，第一子复位单元接收第一扫描复位子信号S2和参考信号Verf，并连接驱动节点n2，以在第一 扫描复位子信号S2所对应的第一复位子期间，利用参考信号Verf对驱动节点n2进行复位。第二复位子单元用于接收第二扫描复位子信号S3和参考信号Verf，并连接第一节点n1，以在第二扫描复位子信号S3所对应的第二复位子期间，利用参考信号Verf对第一节点n1进行复位。
其中，第一复位子单元包括：第四晶体管M4。第四晶体管M4包括第一通路端、第二通路端及控制端，其中，第四晶体管M4的第一通路端连接驱动单元403，具体的，第四晶体管M4的第一通路端连接驱动单元403中的第三晶体管M3的控制端(即驱动节点n2)；第四晶体管M4的第二通路端连接参考信号线，以接收参考信号Verf；第四晶体管M4的控制端连接第一扫描复位子信号线，以接收第一扫描复位子信号S2。
其中，第二复位子单元包括：第五晶体管M5。第五晶体管M5包括第一通路端、第二通路端及控制端，其中，第五晶体管M5的第一通路端连接第一节点n1，具体的，第五晶体管M5的第一通路端连接控制单元404中的第七晶体管M7的第二通路端，在显示像素点中，第五晶体管M5的第一通路端还连接发光器件401的阳极；第五晶体管M5的第二通路端连接参考信号线，以接收参考信号Verf，第五晶体管M5的控制端连接第二扫描复位子信号线，以接收第二扫描复位子信号S3。
其中，控制单元404包括：第六晶体管M6和第七晶体管M7。其中，第六晶体管M6包括第一通路端、第二通路端及控制端，其中，第六晶体管M6的第一通路端连接电源信号线，以接收电源信号VDD，第六晶体管M6的第二通路端连接驱动单元403，具体的，第六晶体管M6的第二通路端连接驱动单元403中的第三晶体管M3的第一通路端，第六晶体管M6的控制端连接使能信号线，接收使能信号EM。第七晶体管M7包括第一通路端、第二通路端及控制端，其中，第七晶体管M7的第一通路端连接第六晶体管M6的第二通路端，第七晶体管M7的第二通路端连接第一节点n1，第七晶体管M7的控制端连接使能信号线，接收使能信号EM。
在一实施例中，显示像素电路及虚拟像素电路还包含：存储电容Cst， 其包括第一通路端及第二通路端，存储电容Cst的第一通路端连接电源信号线，存储电容Cst的第二通路端连接第三晶体管M3的控制端。
在复位阶段，复位单元405中的第四晶体管M4及第五晶体管M5导通，通过参考信号Verf对驱动单元403的驱动节点n2及发光器件401的阳极(即第一节点n1)进行复位。现有的显示面板中，由于第二区域12的第二像素行中的每行的像素点数量少于第一区域11的第一像素行中的每行的像素点，第一像素行和第二像素行接收同一参考信号，因此复位完成后，第一区域11的第一像素行与第二区域12的第二像素行中的显示像素电路中发光器件阳极处的电压不同，进而在写入阶段、发光阶段中会使得第一区域11与第二区域12的显示不均匀，显示效果不佳。而本申请的显示面板中，在每一行的第二像素行上设置与其连接同一参考线号线的虚拟像素点，且虚拟像素点的驱动节点n2处连接有补偿单元，在复位阶段进行复位时，补偿单元对位于同一行的第二像素行的像素点进行补偿，以使得第一区域11及第二区域12的显示像素电路的发光器件的阳极电位趋于一致，进而减小第一区域11及第二区域12的显示像素电路的发光器件的阳极的电压差异，使得第一区域11与第二区域12的显示均匀，提升显示效果。
本实施例以7T1C电路为例进行说明，在其他实施例中，本实施例的方式还可以应用于例如6T1C电路中，或者还可以应用于3T1C电路或8T1C电路中，在此不做限定。只要能够使得第一区域及第二区域的发光器件的阳极电压在复位阶段完成后趋于一致即可。
请参见图4a，为现有技术显示面板在复位阶段的第一区域及第二区域的第一节点处的电压仿真示意图。其中，第二区域12的显示像素电路的发光器件的阳极(即第一节点n1)电压在复位阶段完成后为-2.6457V，第一区域11的显示像素电路的发光器件的阳极(即第一节点n1)电压在复位阶段完成后为-2.6056V，可知现有的显示面板，在复位阶段完成后，第一区域与第二区域的显示像素电路的发光器件的阳极电压之间的差异为40.1mV。
请参见图4b，为本申请显示面板在复位阶段的第一区域及第二区域 的第一节点处的电压仿真示意图。其中，在虚拟像素电路中的补偿单元的作用下，第二区域的显示像素电路的发光器件的阳极电压在复位阶段完成后为-2.5997V，第一区域的显示像素电路的发光器件的阳极电压在复位阶段完成后为-2.5999V，可知本申请的显示面板，在复位阶段完成后，第一区域与第二区域的显示像素电路的发光器件的阳极电压之间的差异为0.2mV。相较于现有技术，本申请的技术方案明显的降低了第一区域与第二区域中的显示像素点元在复位阶段完成后的发光器件的阳极电压。其中，本申请第一区域与第二区域的显示像素电路的发光器件的阳极电压之间的差异为0.2mV是由于仿真器的精度影响造成的，理论上来说，通过本申请的技术方案，在补偿单元的作用下，在复位阶段完成后，第一区域与第二区域的显示像素电路的发光器件的阳极电压之相同。
本申请提供的显示面板可以为双面显示面板、柔性显示面板、全面屏显示面板中任一种。柔性显示面板可以应用于弯曲的电子设备；双面显示面板可以应用于为使显示面板两侧的人员都能看到显示内容的面板；全面屏显示面板可以应用于全面屏手机或其他装置，在此不做限定。
本申请提供的显示面板，通过在第二区域的第二像素行中设置包括虚拟像素电路的虚拟像素点，虚拟像素电路进一步包括补偿单元，补偿单元连接驱动节点及电源信号线，以在复位阶段对第二区域的显示像素电路的发光器件的阳极电压进行补偿，以使得第二区域的显示像素电路的发光器件的阳极电压与第一区域的显示像素电路的发光器件的阳极电压趋于一致，进而降低第一区域与第二区域在显示阶段的显示差异，提高显示效果。
请参见图5，为本申请提供的显示装置的一实施例的结构示意图。其显示装置包括上述所述的显示面板。
在一实施例中，该显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于显示面板的其他必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本申请的限制。该显示 装置的实施例可以参见上述显示面板的实施例，重复之处不再赘述。
在本申请各实施例中，显示面板及显示装置只描述了部分相关结构，其他结构与现有技术中的显示面板及显示装置的结构相同，在此不再赘述。
以上仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (17)

  1. 一种显示面板，其中，包括：
    第一区域和第二区域，所述第一区域包括多行第一像素行，所述第二区域包括多行第二像素行，所述第一像素行和所述第二像素行包括多个像素点，每行所述第一像素行的所述像素点的数量多于每行所述第二像素行的所述像素点数量，其中位于所述第一像素行的多个所述像素点为多个显示像素点，位于第二像素行的多个所述像素点为多个所述显示像素点和多个虚拟像素点；
    所述显示像素点包括显示像素电路，所述虚拟像素点包括虚拟像素电路，所述虚拟像素电路包括补偿单元，所述虚拟像素电路用于对位于同一所述第二像素行的所述显示像素电路复位时进行复位补偿，从而减小所述第一区域和所述第二区域的所述显示像素电路复位后，所述显示像素电路中发光器件节点处的电压差异。
  2. 根据权利要求1所述的显示面板，其中，所述显示像素电路和所述虚拟像素电路包括：写入单元，接收第一扫描信号，以在所述第一扫描信号的驱动下而于写入阶段向驱动节点写入数据信号；
    驱动单元，藉由所述驱动节点而连接所述写入单元；
    控制单元，接收使能信号，并连接所述驱动单元以使所述驱动单元藉由所述控制单元而连接至电源信号线；
    复位单元，接收第二扫描信号，并连接所述驱动节点和所述控制单元，以在所述第二扫描信号的驱动下而接收参考信号，并利用所述参考信号对所述驱动节点和所述复位单元与所述控制单元之间的第一节点进行复位；
    其中，所述显示像素电路中的所述控制单元在所述第一节点处连接所述发光器件，所述虚拟像素电路中的所述驱动节点处连接所述补偿单元。
  3. 根据权利要求2所述的显示面板，其中，位于所述第一像素行和所述第二像素行的所述像素点接收同一所述参考信号，且位于同一所述第二像素行的所述显示像素电路和所述虚拟像素电路中的所述复位单元连接同一条参考信号线。
  4. 根据权利要求3所述的显示面板，其中，所述虚拟像素电路不包括发光器件。
  5. 根据权利要求2所述的显示面板，其中，所述补偿单元为补偿电容或补偿电阻。
  6. 根据权利要求5所述的显示面板，其中，所述补偿单元为所述补偿电容，其一端连接所述驱动节点，而另一端连接至所述电源信号线。
  7. 根据权利要求6所述的显示面板，其中，所述补偿电容的数量小于等于所述虚拟像素点的数量。
  8. 根据权利要求6所述的显示面板，其中，所述补偿电容的数量为所述第一像素行和所述第二像素行中所述像素点数量的差值。
  9. 根据权利要求1所述的显示面板，其中，所述第二区域包括虚拟像素区，所述虚拟像素区包括两个打孔区和位于两个所述打孔区之间的隔离区，所述虚拟像素点位于所述隔离区中。
  10. 根据权利要求2所述的显示面板，其中，所述写入单元包括：
    第一晶体管，包括第一通路端、第二通路端及控制端，所述第一晶体管的第一通路端连接数据信号线，以接收数据信号，所述第一晶体管的第二通路端连接所述驱动单元及所述控制单元，所述第一晶体管的控制端连接第一扫描信号线，以接收第一扫描信号；
    第二晶体管，包括第一通路端、第二通路端及控制端，所述第二晶体管的第一通路端连接所述驱动单元，所述第二晶体管的第二通路端连接所述驱动单元及所述控制单元，所述第二晶体管的控制端连接所述第一扫描信号线，以接收所述第一扫描信号。
  11. 根据权利要求2所述的显示面板，其中，所述驱动单元包括：
    第三晶体管，包括第一通路端、第二通路端及控制端，所述第三晶体管的第一通路端连接所述控制单元及所述写入单元，所述第三晶体管的第二通路端连接所述控制单元及所述写入单元，所述第三晶体管的控制端连接所述复位单元以及所述写入单元。
  12. 根据权利要求2所述的显示面板，其中，所述复位单元包括：
    第一复位子单元，接收第一扫描复位子信号和所述参考信号，并连接所述驱动节点，以在第一扫描复位子信号所对应的第一复位子期间，利用所述参考信号对所述驱动节点进行复位；
    第二复位子单元，接收第二扫描复位子信号和所述参考信号，并连接所述 第一节点，以在第二扫描复位子信号所对应的第二复位子期间，利用所述参考信号对所述第一节点进行复位。
  13. 根据权利要求12所述的显示面板，其中，所述第一复位子单元包括：
    第四晶体管，包括第一通路端、第二通路端及控制端，所述第四晶体管的第一通路端连接所述驱动节点，所述第四晶体管的第二通路端连接参考信号线，以接收所述参考信号，所述第四晶体管的控制端连接第一扫描复位子信号线，以接收所述第一扫描复位子信号。
  14. 根据权利要求12所述的显示面板，其中，所述第二复位子单元包括：
    第五晶体管，包括第一通路端、第二通路端及控制端，所述第五晶体管的第一通路端连接所述第一节点，所述第五晶体管的第二通路端连接参考信号线，以接收所述参考信号，所述第五晶体管的控制端连接第二扫描复位子信号线，以接收所述第二扫描复位子信号。
  15. 根据权利要求2所述的显示面板，其中，所述控制单元包括：
    第六晶体管，包括第一通路端、第二通路端及控制端，所述第六晶体管的第一通路端连接所述电源信号线，以接收所述电源信号，所述第六晶体管的第二通路端连接所述驱动单元，所述第六晶体管的控制端连接使能信号线，接收所述使能信号；
    第七晶体管，包括第一通路端、第二通路端及控制端，所述第七晶体管的第一通路端连接所述第六晶体管的第二通路端，所述第七晶体管的第二通路端连接所述第一节点，所述第七晶体管的控制端连接使能信号线，接收所述使能信号。
  16. 根据权利要求2所述的显示面板，其中，所述显示像素电路及所述虚拟像素电路还包括：
    存储电容，包括第一通路端及第二通路端，所述存储电容的第一通路端连接所述电源信号线，所述存储电容的第二通路端连接所述驱动单元。
  17. 一种显示装置，其中，所述显示装置包括：权利要求1～16任一项所述的显示面板。
PCT/CN2021/083388 2020-04-17 2021-03-26 一种显示面板及显示装置 Ceased WO2021208708A1 (zh)

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