WO2021212313A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2021212313A1
WO2021212313A1 PCT/CN2020/085889 CN2020085889W WO2021212313A1 WO 2021212313 A1 WO2021212313 A1 WO 2021212313A1 CN 2020085889 W CN2020085889 W CN 2020085889W WO 2021212313 A1 WO2021212313 A1 WO 2021212313A1
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WO
WIPO (PCT)
Prior art keywords
layer
insulating layer
power line
area
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/085889
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English (en)
French (fr)
Inventor
于鹏飞
万晨星
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US17/265,193 priority Critical patent/US11963382B2/en
Priority to JP2021566042A priority patent/JP7486523B2/ja
Priority to CN202080000578.0A priority patent/CN113826210B/zh
Priority to EP20900717.8A priority patent/EP4141942A4/en
Priority to PCT/CN2020/085889 priority patent/WO2021212313A1/zh
Publication of WO2021212313A1 publication Critical patent/WO2021212313A1/zh
Anticipated expiration legal-status Critical
Priority to US18/433,472 priority patent/US20240179940A1/en
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/80—Manufacture or treatment specially adapted for the organic devices covered by this subclass using temporary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the present disclosure relates to, but is not limited to, the field of display technology, in particular to a display substrate, a preparation method thereof, and a display device.
  • OLED Organic Light Emitting Diode
  • TFT thin film transistor
  • the present disclosure provides a display substrate, which includes a display area and a binding area located on one side of the display area.
  • the display area includes a driving structure layer, an organic insulating layer disposed on the driving structure layer, and The light-emitting element on the organic insulating layer and the composite encapsulation layer provided on the light-emitting element, the drive structure layer includes a pixel drive circuit, and the light-emitting element is connected to the pixel drive circuit;
  • the binding area includes A binding structure layer, an organic insulating layer and an isolation dam disposed on the binding structure layer, and an inorganic encapsulation layer disposed on the organic insulating layer and the isolation dam, and the binding structure layer includes driving with the pixel
  • the organic insulating layer of the binding area is provided with at least one isolation groove, the inorganic encapsulation layer covers the isolation groove and wraps the isolation dam, and the distance between the isolation groove and the edge of the display area It is smaller than the distance between the isolation dam
  • the isolation dam includes a first isolation dam and a second isolation dam, and the distance between the first isolation dam and the edge of the display area is smaller than the distance between the second isolation dam and the edge of the display area; The distance between the isolation groove and the edge of the display area is smaller than the distance between the first isolation dam and the edge of the display area.
  • the light-emitting element includes an anode, a pixel defining layer, an organic light-emitting layer, and a cathode, and the pixel defining layer and the cathode extend to the binding area; along a direction away from the display area, The distance between the edge of the cathode and the edge of the display area in the binding area is smaller than the distance between the isolation groove and the edge of the display area.
  • the width of the isolation groove is 20 ⁇ m to 70 ⁇ m.
  • the power line includes a first power line and a second power line
  • the isolation slot is provided on the first power line, or on the second power line, or Between the first power line and the second power line.
  • the orthographic projection of the isolation groove on the substrate includes an orthographic projection of the first power cord on the substrate.
  • the display substrate further includes an edge region, the edge region includes a circuit structure layer and an organic insulating layer disposed on the circuit structure layer, and the organic insulating layer is provided with a gap, so The isolation groove of the binding area is connected with the gap of the edge area.
  • the first power line includes a first strip-shaped block and a second strip-shaped block, the first strip-shaped block extends along the edge of the display area, and the second strip-shaped block The block extends in a direction away from the display area, and one end of the second strip-shaped block adjacent to the display area is connected to the first strip-shaped block to form a T-shaped structure;
  • the second voltage line is located in the A side of the first strip-shaped block away from the display area, the isolation dam is arranged on the second strip-shaped block and the second power line, and the isolation groove is arranged on the first strip-shaped block.
  • the binding structure layer of the binding area includes a composite insulating layer disposed on a substrate and a first power line and a second power line disposed on the composite insulating layer; or
  • the binding structure layer of the binding area includes a composite insulating layer provided on a substrate, a first power line and a second power line provided on the composite insulating layer, and a first power line and a second power line provided on the composite insulating layer.
  • the fifth insulating layer on the wire.
  • the organic insulating layer disposed on the binding structure layer includes a first flat layer; the composite insulating layer includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer stacked on a substrate .
  • the binding structure layer of the binding area includes a composite insulating layer disposed on a substrate, a fifth insulating layer disposed on the composite insulating layer, and a fifth insulating layer disposed on the fifth insulating layer.
  • the first flat layer on the upper side and the first power line and the second power line provided on the first flat layer; or, the bonding structure layer of the bonding area includes a composite insulating layer provided on a substrate, The first power line and the second power line on the composite insulation layer, the fifth insulation layer provided on the first power line and the second power line, and the first power line provided on the fifth insulation layer A flat layer; or, the binding structure layer of the binding area includes a composite insulating layer disposed on a substrate, a second connection electrode and a third connection electrode disposed on the composite insulating layer, and covering the second connection The fifth insulating layer of the electrode and the third connecting electrode, the first flat layer provided on the fifth insulating layer, and the first power line and the second power line provided on the first flat layer, the first A power line is connected to the second connection electrode through the via hole, and the second power line is connected to the third connection electrode through the via hole.
  • the organic insulating layer disposed on the binding structure layer includes a second flat layer; the composite insulating layer includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer stacked on a substrate .
  • the edge of the power cord is provided with a wave structure; the wave structure is provided on the edge of the power cord on the side of the isolation groove away from the display area, or the wave structure is provided On the edge of the power cord on the side of the isolation dam away from the display area, or the wave structure is arranged on the edge of the power cord in the area where the power cord overlaps with the isolation dam.
  • the wave structure includes a plurality of protrusions arranged at intervals, and the protrusion height of the protrusions is 30 ⁇ m to 60 ⁇ m.
  • the present disclosure also provides a method for manufacturing a display substrate.
  • the display substrate includes a display area and a binding area located on one side of the display area.
  • the preparation method includes:
  • the driving structure layer includes a pixel driving circuit
  • the bonding structure layer includes a power line connected to the pixel driving circuit
  • a light-emitting element and an isolation dam are formed in the display area and the binding area respectively; the light-emitting element is connected to the pixel drive circuit, and the distance between the isolation groove and the edge of the display area is smaller than the distance between the isolation dam and the edge of the display area ;
  • An inorganic encapsulation layer is formed in the binding area, and the inorganic encapsulation layer covers the isolation groove and wraps the isolation dam.
  • forming a light-emitting element and an isolation dam in the display area and the binding area respectively includes: forming a light-emitting element in the display area, and the light-emitting element is connected to the pixel driving circuit;
  • the binding area forms a first isolation dam and a second isolation dam, the distance between the first isolation dam and the edge of the display area is smaller than the distance between the second isolation dam and the edge of the display area, and the distance between the isolation groove and the edge of the display area It is smaller than the distance between the first isolation dam and the edge of the display area.
  • forming a light-emitting element in the display area includes: sequentially forming an anode, a pixel defining layer, an organic light-emitting layer, and a cathode on the organic insulating layer, and the anode is connected to the pixel driving circuit, The pixel definition layer and the cathode extend to the binding area; along a direction away from the display area, the distance between the edge of the cathode and the edge of the display area in the binding area is smaller than the isolation groove and the edge of the display area the distance.
  • the power line includes a first power line and a second power line
  • the isolation slot is provided on the first power line, or on the second power line, or Between the first power line and the second power line, along a direction away from the display area, the width of the isolation groove is 20 ⁇ m to 70 ⁇ m.
  • the display substrate further includes an edge region
  • the preparation method further includes: forming a circuit structure layer on the edge region, forming an organic insulating layer on the circuit structure layer, and the organic insulating layer At least one gap is formed on the layer, and the isolation groove of the binding area and the gap of the edge area are connected and formed by the same process.
  • the binding structure layer of the binding area includes a composite insulating layer disposed on a substrate and a first power line and a second power line disposed on the composite insulating layer; or
  • the binding structure layer of the binding area includes a composite insulating layer provided on a substrate, a first power line and a second power line provided on the composite insulating layer, and a first power line and a second power line provided on the composite insulating layer.
  • the binding structure layer of the binding area includes a composite insulating layer disposed on the substrate, a fifth insulating layer disposed on the composite insulating layer, and a fifth insulating layer disposed on the fifth insulating layer.
  • the organic insulating layer provided on the binding structure layer includes a first flat layer or a second flat layer; the composite insulating layer includes a first insulating layer, a second insulating layer, and a third insulating layer stacked on a substrate. Layer and fourth insulating layer.
  • the edge of the power cord is provided with a wave structure; the wave structure is provided on the edge of the power cord on the side of the isolation groove away from the display area, or the wave structure is provided On the edge of the power cord on the side of the isolation dam away from the display area, or the wave structure is arranged on the edge of the power cord in the area where the power cord and the isolation dam overlap; the wave structure includes spaced arrangement A plurality of protrusions, the protrusion height of the protrusions is 30 ⁇ m to 60 ⁇ m.
  • the present disclosure also provides a display device including the aforementioned display substrate.
  • FIG. 1 is a schematic diagram of the structure of the display substrate of the present disclosure
  • FIG. 2 is a schematic diagram showing the structure of the binding area in the substrate according to the present disclosure
  • FIG. 3 is a schematic diagram of a structure of the first fan-out zone of the present disclosure.
  • Figure 4 is a cross-sectional view taken along the line A-A in Figure 3;
  • FIG. 5 is a schematic diagram showing a structure of a substrate according to the present disclosure.
  • FIG. 6 is a schematic diagram of the present disclosure after forming a flexible substrate pattern
  • FIG. 7 is a schematic diagram after the patterns of the driving structure layer and the binding structure layer are formed in the present disclosure.
  • FIG. 8 is a schematic diagram of the present disclosure after forming a pattern of partition grooves
  • FIG. 9 is a schematic diagram after forming an anode pattern according to the present disclosure.
  • FIG. 10 is a schematic diagram of the present disclosure after forming a pixel definition layer pattern
  • FIG. 11 is a schematic diagram of the present disclosure after forming a pattern of spacer posts
  • FIG. 12 is a schematic diagram of the disclosure after forming an organic light-emitting layer and a cathode pattern
  • FIG. 13 is a schematic diagram of the present disclosure after forming an encapsulation layer pattern
  • FIG. 14 is a schematic diagram of the structure of the edge of the binding area of the disclosure.
  • FIG. 15 is a schematic diagram showing another structure of the substrate according to the present disclosure.
  • FIG. 16 is a schematic diagram showing another structure of the substrate in the present disclosure.
  • FIG. 17 is a schematic diagram showing another structure of the substrate in the present disclosure.
  • FIG. 18 is a schematic diagram showing another structure of the substrate according to the present disclosure.
  • FIG. 19 is a schematic diagram showing another structure of the substrate in the present disclosure.
  • FIG. 20 is a schematic diagram showing another structure of the substrate according to the present disclosure.
  • FIG. 21 is a schematic diagram showing another structure of the substrate in the present disclosure.
  • FIG. 22 is a schematic diagram of another structure of the first fan-out area of the present disclosure.
  • FIG. 23 is a schematic diagram of the cross-sectional structure of the display area and the edge area of the 2SD structure of the present disclosure.
  • 24 is a schematic diagram of the cross-sectional structure of the display area and the edge area of the 1SD structure of the present disclosure
  • 25 is a schematic diagram of another structure of the first fan-out area of the present disclosure.
  • Fig. 26 is an enlarged view of area E in Fig. 25.
  • 21 anode
  • 22 pixel definition layer
  • 23 organic light-emitting layer
  • 110 display area edge
  • 200 binding area
  • 201 first fan-out area
  • 205 Drive chip area
  • 206 Biting electrode area
  • 210 First power line
  • 220 second power line
  • 230 wave structure
  • 300 edge area
  • 600 Isolation area
  • 700 Gap
  • 801 First connecting electrode
  • 802 second connecting electrode
  • 803 third connecting electrode
  • 804 fourth connecting electrode
  • connection should be interpreted broadly. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate piece, or internal communication between two components.
  • connection should be interpreted broadly. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate piece, or internal communication between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • the transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • the channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and the “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged.
  • electrical connection includes the case where constituent elements are connected together by elements having a certain electrical function.
  • An element having a certain electrical function is not particularly limited as long as it can transmit and receive electrical signals between connected constituent elements.
  • elements having a certain electrical function include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore, it also includes a state where the angle is -5° or more and 5° or less.
  • perpendicular refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore, also includes a state where an angle of 85° or more and 95° or less is included.
  • film and “layer” can be interchanged.
  • the “conductive layer” can be replaced by the “conductive film.”
  • the “insulating film” can sometimes be replaced with an “insulating layer.”
  • the "about” in the present disclosure refers to a value within the allowable process and measurement error range without strictly limiting the limit.
  • a flexible display device includes a driving circuit layer arranged on a flexible substrate, a light emitting device arranged on the driving circuit layer, and an encapsulation layer arranged on the light emitting device.
  • the encapsulation layer is used for protecting the light emitting device. Studies have shown that the encapsulation effect of the encapsulation layer has a great influence on the display performance of the flexible display device. If the encapsulation layer fails, such as a gap or a crack in the encapsulation layer, water vapor in the atmosphere will enter the light-emitting device along the gap, causing the organic material in the light-emitting device to oxidize and fail, forming a failure area that cannot emit light. As water vapor continuously invades the light emitting device along the gap, the failure area gradually expands, resulting in poor display of the flexible display device, which is called Growing Dark Spot (GDS).
  • GDS Growing Dark Spot
  • the present disclosure provides a display substrate, which includes a display area and a binding area located on one side of the display area.
  • the display area includes a driving structure layer, an organic insulating layer disposed on the driving structure layer, and The light-emitting element on the insulating layer and the composite encapsulation layer provided on the light-emitting element, the drive structure layer includes a pixel drive circuit, and the light-emitting element is connected to the pixel drive circuit;
  • the binding area includes a binding structure Layer, an organic insulating layer and an isolation dam disposed on the binding structure layer, and an inorganic encapsulation layer disposed on the organic insulating layer and the isolation dam, and the binding structure layer includes a layer connected to the pixel driving circuit Power cord; at least one isolation groove is provided on the organic insulating layer of the binding area, the inorganic encapsulation layer covers the isolation groove and wraps the isolation dam, and the distance between the isolation groove and the edge of the display area is less than the The distance between the isolation dam and the
  • the isolation dam includes a first isolation dam and a second isolation dam, and the distance between the first isolation dam and the edge of the display area is smaller than the distance between the second isolation dam and the edge of the display area; The distance between the isolation groove and the edge of the display area is smaller than the distance between the first isolation dam and the edge of the display area.
  • the light-emitting element includes an anode, a pixel defining layer, an organic light-emitting layer, and a cathode, the pixel defining layer and the cathode extending to the binding area; along a direction away from the display area, the cathode The distance between the edge and the edge of the display area is smaller than the distance between the isolation groove and the edge of the display area.
  • the power cord includes a first power cord and a second power cord
  • the isolation slot is provided on the first power cord, or on the second power cord, or on the Between the first power line and the second power line.
  • the width of the isolation groove is 20 ⁇ m to 70 ⁇ m.
  • the orthographic projection of the isolation groove on the substrate includes the orthographic projection of the first power cord on the substrate.
  • the display substrate further includes an edge region, the edge region includes a circuit structure layer and an organic insulating layer disposed on the circuit structure layer, the organic insulating layer is provided with a gap, the The isolation grooves in the binding area are connected to the gaps in the edge area and are formed by the same process.
  • the first power cord includes a first strip block and a second strip block, the first strip block extends along an edge direction of the display area, and the second strip block Extending in a direction away from the display area, one end of the second stripe block adjacent to the display area is connected to the first stripe block to form a T-shaped structure; the second voltage line is located on the first stripe block.
  • the isolation dam is arranged on the second strip block and the second power line, and the isolation groove is arranged on the first strip block.
  • the binding structure layer of the binding area includes a composite insulating layer disposed on a substrate, and a first power line and a second power line disposed on the composite insulating layer; or, the The binding structure layer of the binding area includes a composite insulating layer provided on a substrate, a first power line and a second power line provided on the composite insulating layer, and a first power line and a second power line provided on the composite insulating layer ⁇ fifth insulating layer.
  • the organic insulating layer disposed on the binding structure layer includes a first flat layer; the composite insulating layer includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer stacked on a substrate .
  • the binding structure layer of the binding area includes a composite insulating layer disposed on a substrate, a fifth insulating layer disposed on the composite insulating layer, and a fifth insulating layer disposed on the fifth insulating layer.
  • the bonding structure layer of the bonding area includes a composite insulating layer provided on a substrate, The first power line and the second power line on the composite insulation layer, the fifth insulation layer provided on the first power line and the second power line, and the first flat insulation layer provided on the fifth insulation layer
  • the binding structure layer of the binding area includes a composite insulating layer disposed on a substrate, a second connection electrode and a third connection electrode disposed on the composite insulating layer, and covering the second connection electrode And the fifth insulating layer of the third connecting electrode, the first flat layer provided on the fifth insulating layer, and the first power line and the second power line provided on the first flat layer, the first The power line is connected to the second connection electrode through the via hole, and the second power line is connected to the third connection electrode through the via hole.
  • the organic insulating layer disposed on the binding structure layer includes a second flat layer; the composite insulating layer includes a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer stacked on a substrate .
  • the edge of the power cord is provided with a wave structure; the wave structure is provided on the edge of the power cord on the side of the isolation groove away from the display area, or the wave structure is provided at The isolation dam is located on the edge of the power cord on the side away from the display area, or the wave structure is arranged on the edge of the power cord in the overlapping area of the power cord and the isolation dam.
  • FIG. 1 is a schematic diagram of the structure of the display substrate of the present disclosure.
  • the display substrate of the present disclosure includes a display area 100 and a non-display area located at the periphery of the display area 100.
  • the non-display area includes a binding area 200 located on one side of the display area 100 and an edge area located on the other side of the display area 100. 300.
  • the display area 100 includes at least a plurality of display units arranged regularly, the binding area 200 at least includes an isolation dam and a binding circuit that connects the signal lines of the multiple display units to an external driving device, and the edge area 300 includes at least an isolation dam and A power line that transmits voltage signals to a plurality of display units, the binding area 200 and the isolation dam of the edge area 300 form a ring structure surrounding the display area 100.
  • FIG. 2 is a schematic diagram showing the structure of the binding area in the substrate according to the present disclosure.
  • the binding area 200 of the present disclosure in a plane parallel to the display substrate, is located on one side of the display area 100, and the binding area 200 includes first fan-out areas sequentially arranged along a direction away from the display area 100 201, a bending area 202, a second fan-out area 203, an anti-static area 204, a driving chip area 205, and a bonding electrode area 206.
  • the first fan-out area 201 includes a data fan-out line, a first power line, and a second power line.
  • the data fan-out line is located in the middle of the first fan-out area 201 and includes a plurality of data connection lines.
  • the data connection lines are configured to Fanout wiring is connected to the data line (Data Line) of the display area 100.
  • the first power line is located on both sides of the data fanout line and is configured to connect to the high-voltage power line (VDD) of the display area 100.
  • the power line is also located on both sides of the data fan-out line, and is configured to connect to the low-voltage power line (VSS) of the edge area 300.
  • the bending area 202 includes a composite insulating layer provided with grooves, and is configured to bend the binding area 200 to the back of the display area 100.
  • the second fan-out area 203 includes a plurality of data connection lines led out by fan-out wiring.
  • the anti-static area 204 includes an anti-static circuit configured to prevent electrostatic damage to the display substrate by eliminating static electricity.
  • the driver chip area 205 includes an integrated circuit (Integrated Circuit, IC for short), which is configured to be connected to a plurality of data connection lines.
  • the bonding electrode area 206 includes a plurality of bonding pads, which are configured to be bonded and connected to an external flexible printed circuit (FPC).
  • FIG. 3 is a schematic diagram of a structure of the first fan-out area of the present disclosure, and is an enlarged view of the area C in FIG. 2, and FIG. 4 is a cross-sectional view taken along the line A-A in FIG. 3.
  • the binding area 200 is located on one side of the display area 100, and the first fan-out area of the binding area 200 is adjacent to the edge 110 of the display area.
  • the first fan-out area includes a first power line 210, a second power line 220, and a data fan-out line (not shown).
  • the first power line 210 is connected to the high-voltage power line of the display area 100 and is configured to be connected to the display area 100.
  • the plurality of display units in the display area 100 transmit high-voltage signals
  • the second power line 220 is connected to the low-voltage power line in the edge area 300 and is configured to transmit low-voltage signals to the plurality of display units in the display area 100.
  • the first fan-out area further includes a first isolation dam 410, a second isolation dam 420, and a partition groove 500, which are configured to block water vapor from entering the display area 100.
  • the first isolation dam 410 and the second isolation dam 420 are arranged in the binding area 200 and the edge area 300, and a ring structure surrounding the display area 100 is formed in the binding area 200 and the edge area 300.
  • the first isolation dam 410 and the second isolation dam are 420 is configured to block water vapor entering the display area 100 from the periphery of the display area 100.
  • the first isolation dam 410 and the second isolation dam 420 extend in a direction parallel to the edge 110 of the display area, and the distance between the first isolation dam 410 and the edge 110 of the display area is smaller than that of the second isolation dam 420 and the display area.
  • the distance of the edge 110, that is, the second isolation dam 420 is arranged on the side of the first isolation dam 410 away from the display area 100.
  • the isolation groove 500 is provided in the binding area 200 and is configured to block water vapor that enters the display area 100 along the edges of the first power cord 210 and the second power cord 220.
  • the partition groove 500 extends in a direction parallel to the display area edge 110, and the distance between the partition groove 500 and the display area edge 110 is smaller than the distance between the first isolation dam 410 and the display area edge 110, that is, the partition groove 500 is arranged at the display area edge 110 and Between the first isolation dam 410.
  • the first fan-out area of the bonding area 200 includes a composite insulating layer disposed on the base 10, a first power line 210 and a second power line 210 disposed on the composite insulating layer.
  • the cathode 24 provided on the pixel defining layer 22, and the first encapsulation layer 25 covering the above structure.
  • the first isolation dam 410 and the second isolation dam 420 are arranged on the second power line 220 and are wrapped by the first encapsulation layer 25.
  • the first isolation dam 410 is composed of a first dam foundation and a spacer column
  • the second isolation dam 420 is composed of It consists of a flat dam foundation, a second dam foundation and a spacer column.
  • the first flat layer 15 in the vicinity of the first isolation dam 410 and the second isolation dam 420 is removed, exposing the second power line 220, and the encapsulation layer 25 covers the second power line 220 exposed in the area.
  • the first flat layer 15 on the first power cord 210 is provided with a partition groove 500, and the first flat layer 15 in the partition groove 500 is removed , The surface of the first power line 210 is exposed, so that the encapsulation layer 25 covers the exposed surface of the first power line 210 in the isolation groove 500.
  • the isolation groove 500 is disposed between the edge of the cathode 24 away from the display area and the first isolation dam 410 to prevent the first power line 210 exposed by the isolation groove 500 from contacting the cathode 24.
  • the position of the partition groove 500 can be designed according to the size of the binding area, the line width of the first power line 210 and the line width of the second power line 220, provided that the partition groove 500 is far away from the cathode 24
  • the partition groove 500 may be provided on the first flat layer 15 and the pixel definition layer 22, and the disclosure does not make specific limitations herein.
  • the first power line 210 includes a first strip block 2101 and a second strip block 2102.
  • the first strip block 2101 extends in a direction parallel to the edge 110 of the display area, and the second strip
  • the shaped block 2102 extends along a direction away from the display area 100, and one end of the second striped block 2102 adjacent to the display area 100 is connected to the first striped block 2101 to form a T-shaped structure.
  • the second power cord 220 includes a third strip-shaped block 2201 and a fourth strip-shaped block 2202.
  • the third strip-shaped block 2201 extends in a direction parallel to the edge 110 of the display area, and the fourth strip-shaped block 2202 extends away from the display area 100.
  • the fourth strip-shaped block 2202 is connected to the third strip-shaped block 2201 at one end adjacent to the display area 100 to form an angular structure.
  • the second power line 220 is located on the side of the first strip block 2101 away from the display area 100 and on the side of the second strip block 2102 away from the data fan-out line.
  • the first isolation dam 410 and the second isolation dam 420 are arranged in the first On the second strip block 2102 of the power cord 210 and the third strip block 2201 of the second power cord 220, the isolation groove 500 is provided on the first strip block 2101 of the first power cord 210.
  • FIG. 5 is a schematic diagram of a structure of a display substrate of the present disclosure, and is a cross-sectional view in the direction of B-B in FIG.
  • the display substrate In a plane direction parallel to the display substrate, the display substrate includes a display area 100 and a binding area 200, and the binding area 200 is located on one side of the display area 100.
  • the display area 100 In a plane direction perpendicular to the display substrate, the display area 100 includes a flexible substrate 10, a driving structure layer disposed on the flexible substrate 10, a light emitting element disposed on the driving structure layer, and a composite packaging layer covering the light emitting element.
  • the binding area 200 includes a flexible substrate 10, a binding structure layer disposed on the flexible substrate 10, an isolation groove 500 and an isolation region 600 disposed on the binding structure layer, and a first isolation dam 410 and a first isolation dam 410 and a second isolation region 600 are provided in the isolation region 600.
  • the driving structure layer of the display area 100 includes a plurality of transistors and storage capacitors forming a pixel driving circuit.
  • the transistor 101 may be a driving transistor.
  • the driving structure layer of the display area 100 includes: a first insulating layer 11 disposed on the flexible substrate 10, an active layer disposed on the first insulating layer 11, a second insulating layer 12 covering the active layer, and a second insulating layer 12 disposed on the second insulating layer.
  • the source and drain metal layers provided on the fourth insulating layer 14.
  • the active layer includes at least the first active layer, the first gate metal layer includes at least the first gate electrode and the first capacitor electrode, and the second gate metal layer at least It includes a second capacitor electrode, the source-drain metal layer includes at least a first source electrode and a first drain electrode.
  • the first active layer, the first gate electrode, the first source electrode, and the first drain electrode form the first transistor 101.
  • the capacitor electrode and the second capacitor electrode form the first storage capacitor 102, and the source/drain metal layer is also referred to as the first source/drain metal layer (SD1).
  • a first flat layer 15 is provided on the driving structure layer of the display area 100, and a light-emitting element is provided on the first flat layer 15.
  • the light-emitting element includes an anode 21, a pixel defining layer 22, an organic light-emitting layer 23 and a cathode 24.
  • the anode 21 passes through the A first via hole opened on the flat layer 15 is connected to the first drain electrode of the first transistor 101.
  • the composite encapsulation layer includes a first encapsulation layer 25, a second encapsulation layer 26, and a third encapsulation layer 27 that are stacked.
  • the second encapsulation layer 26 of organic material is disposed between the first encapsulation layer 25 and the third encapsulation layer 27 of inorganic material. between.
  • the binding structure layer of the binding area 200 includes a composite insulating layer composed of a plurality of inorganic insulating layers, and a first power line 210 and a second power line 220 disposed on the composite insulating layer, and the composite insulating layer is included on the flexible substrate 10
  • the first insulating layer 11, the second insulating layer 12, the third insulating layer 13, and the fourth insulating layer 14 are stacked.
  • the above-mentioned insulating layers are all inorganic insulating layers.
  • the first power line 210 and the second power line 220 are arranged on the On the fourth insulating layer 14, the first source electrode and the first drain electrode of the display area are arranged in the same layer, and are formed by the same patterning process.
  • the binding structure layer of the binding area 200 is provided with a first flat layer 15, and the first flat layer 15 is provided with a partition groove 500 and an isolation region 600.
  • the partition groove 500 is provided in the area where the first power line 210 is located, and the partition groove 500 The surface of the first power cord 210 is exposed, the isolation area 600 is arranged on the side of the second power cord 220 away from the display area 100, and the first isolation dam 410 and the second isolation dam 420 are arranged in the isolation area 600.
  • the first isolation dam 410 and the second isolation dam 420 are arranged on the second power line 220. Except for the location of the first isolation dam 410 and the second isolation dam 420, other positions of the isolation area 600 expose the surface of the second power line 220 and the composite insulating layer .
  • the inorganic encapsulation layer includes a first encapsulation layer 25 and a third encapsulation layer 27 that are stacked.
  • the first encapsulation layer 25 and the third encapsulation layer 27 made of inorganic materials cover the partition groove 500 and the isolation region 600, and wrap the first isolation dam 410 and The second isolation dam 420.
  • a pixel defining layer 22 is provided on the first flat layer 15 adjacent to the display area 100, a plurality of spacer pillars 33 are provided on the pixel defining layer 22, and the cathode 24 wraps the plurality of spacer pillars 33.
  • the isolation groove 500 may be one or more, the width of the isolation groove 500 is about 20 ⁇ m to about 50 ⁇ m, and the distance between the isolation groove 500 and the display area edge 110 is smaller than the first isolation dam 410 and the display area edge 110 The distance between the isolation groove 500 and the edge 110 of the display area is greater than the distance between the edge of the cathode 24 and the edge 110 of the display area.
  • the "patterning process” referred to in the present disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, developing, etching, and stripping the photoresist.
  • the deposition can be any one or more selected from sputtering, evaporation and chemical vapor deposition
  • the coating can be any one or more selected from spraying and spin coating
  • the etching can be selected from dry etching. Any one or more of wet engraving.
  • Thin film refers to a layer of film made by depositing or coating a certain material on a substrate.
  • the "film” can also be referred to as a "layer".
  • the patterning process is required for the "thin film” during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process.
  • the “layer” after the patterning process contains at least one "pattern”.
  • “A and B are arranged in the same layer” means that A and B are formed at the same time through the same patterning process.
  • the orthographic projection of A includes the orthographic projection of B means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.
  • the flexible substrate 10 includes a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on the glass carrier 1.
  • the materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET) or surface-treated polymer soft film, etc.
  • the first and second inorganic materials The material of the layer can be silicon nitride (SiNx) or silicon oxide (SiOx) to improve the water and oxygen resistance of the substrate.
  • the first and second inorganic material layers are also called barrier layers.
  • the material can be amorphous silicon (a-si).
  • the preparation process may include: first coating a layer of polyimide on the glass carrier 1 and curing it to After the film is formed, the first flexible (PI1) layer is formed; then a barrier film is deposited on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then a non-conductive layer is deposited on the first barrier layer A thin film of crystalline silicon forms an amorphous silicon (a-si) layer covering the first barrier layer; then a layer of polyimide is coated on the amorphous silicon layer and cured into a film to form a second flexible (PI2) layer ; Then a barrier film is deposited on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer to complete the preparation of the flexible substrate 10, as shown in FIG. 6.
  • both the display area 100 and the binding area 200 include the flexible substrate 10.
  • the driving structure layer of the display area 100 includes a first transistor 101 and a first storage capacitor 102 constituting a pixel driving circuit
  • the bonding structure layer of the bonding area 200 includes a first power line 210 and a second power line 220.
  • the preparation process of the driving structure layer may include:
  • a first insulating film and an active layer film are sequentially deposited on the flexible substrate 10, and the active layer film is patterned through a patterning process to form a first insulating layer 11 covering the entire flexible substrate 10, and set on the first insulating layer 11
  • the active layer pattern includes at least the first active layer.
  • the bonding area 200 includes the first insulating layer 11 disposed on the flexible substrate 10.
  • a second insulating film and a first metal film are sequentially deposited, and the first metal film is patterned through a patterning process to form a second insulating layer 12 covering the active layer pattern, and a first insulating layer 12 disposed on the second insulating layer 12
  • the gate metal layer pattern includes at least a first gate electrode and a first capacitor electrode.
  • the bonding area 200 includes the first insulating layer 11 and the second insulating layer 12 stacked on the flexible substrate 10.
  • a third insulating film and a second metal film are sequentially deposited, and the second metal film is patterned through a patterning process to form a third insulating layer 13 covering the first gate metal layer, and a second insulating layer disposed on the third insulating layer 13
  • the second gate metal layer pattern, the second gate metal layer pattern includes at least a second capacitor electrode, and the position of the second capacitor electrode corresponds to the position of the first capacitor electrode.
  • the bonding area 200 includes a first insulating layer 11, a second insulating layer 12, and a third insulating layer 13 stacked on the flexible substrate 10.
  • the bonding area 200 includes a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14 stacked on the flexible substrate 10.
  • the source-drain metal layer includes at least the first source electrode and the second electrode located in the display area 100 A drain electrode, and the first power line 210 and the second power line 220 located in the bonding area 200, the first source electrode and the first drain electrode are respectively connected to the first active layer through the first via hole.
  • the driving structure layer of the display area 100 and the binding structure layer pattern of the binding area 200 are prepared on the flexible substrate 10, as shown in FIG. 7.
  • the first active layer, the first gate electrode, the first source electrode and the first drain electrode constitute the first transistor 101
  • the first capacitor electrode and the second capacitor electrode constitute the first storage capacitor 102 .
  • the binding structure layer of the binding area 200 includes a composite insulating layer disposed on the flexible substrate 10, and a first power line 210 and a second power line 220 disposed on the composite insulating layer.
  • the composite insulating layer includes a laminated first insulating layer. Layer 11, second insulating layer 12, third insulating layer 13, and fourth insulating layer 14.
  • the interval between the first power supply line 210 and the second power supply line 220 is about 50 ⁇ m to about 100 ⁇ m.
  • the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer may be selected from among silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). Any one or more, can be single layer, multilayer or composite layer.
  • the first insulating layer is called a buffer layer, which is used to improve the water and oxygen resistance of the substrate, the second and third insulating layers are called gate insulating (GI) layers, and the fourth insulating layer is called a layer Inter-insulation (ILD) layer.
  • GI gate insulating
  • ILD layer Inter-insulation
  • the first metal film, the second metal film and the third metal film can be made of metal materials, such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo) or More kinds, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), can have a single-layer structure or a multilayer composite structure, such as Ti/Al/Ti.
  • metal materials such as any one of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo) or More kinds, or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb)
  • AlNd aluminum neodymium alloy
  • MoNb molybdenum niobium alloy
  • the active layer film can use amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si) , Hexathiophene, polythiophene and other materials, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology.
  • a-IGZO amorphous indium gallium zinc oxide
  • ZnON zinc oxynitride
  • IZTO indium zinc tin oxide
  • a-Si amorphous silicon
  • p-Si polysilicon
  • Hexathiophene polythiophene and other materials
  • first flat (PLN) layer 15 covering the entire flexible substrate 10.
  • first flat (PLN) layer 15 covering the entire flexible substrate 10.
  • the first flat layer 15 A pattern of the second via hole K2, the partition trench 500, the isolation region 600, and the flat dam base 30 is formed thereon, and the first flat layer 15 serves as the organic insulating layer of the present disclosure.
  • the second via hole K2 is formed in the display area 100, and the first flat layer 15 in the second via hole is developed to expose the surface of the first drain electrode of the first transistor 101.
  • the partition groove 500 is formed at the position where the first power cord 210 is located in the binding area 200, and the first flat layer 15 in the partition groove 500 is developed to expose the surface of the first power cord 210.
  • the isolation area 600 is formed on the side of the second power line 220 in the binding area 200 away from the display area 100.
  • the second power line 220 in the isolation area 600 is provided with a flat dam base 30. Except for the flat dam base 30, the isolation area 600 has other positions
  • the first flat layer 15 is developed, exposing the surface of the second power line 220 and the surface of the fourth insulating layer 14, as shown in FIG. 8.
  • the partition groove 500 of the binding area 200 is used to block water vapor that enters the display area 100 along the edge of the first power line 210 and the edge of the second power line 220, and the isolation area 600 is used to Two isolation dams are formed on the second power cord 220, and the flat dam foundation 30 is the dam foundation of the second isolation dam.
  • the width of the partition groove 500 is about 20 ⁇ m to about 50 ⁇ m, which may be one, or two, or more than three, and the width of the flat dam base 30 is about 20 ⁇ m to about 60 ⁇ m.
  • the distance L0 between the edge on the side of the isolation groove 500 adjacent to the isolation region 600 and the edge of the isolation region 600 on the side adjacent to the isolation groove 500 is about 40 ⁇ m to about 100 ⁇ m, so as to reduce the distance between the isolation groove 500 and the isolation region. There is a risk of the first flat layer 15 falling off in the area between 600.
  • the length of the partition groove 500 is equal to the length of the first power cord 210 where the partition groove 500 is located, that is, the length of the orthographic projection of the partition groove 500 on the flexible substrate 10 is equal to the first The length of the orthographic projection of a power cord 210 on the flexible substrate 10, and the surface of the first power cord 210 is exposed in the partition groove 500.
  • the length of the partition groove 500 in a direction parallel to the edge of the display area, may be greater than the length of the first power cord 210 where the partition groove 500 is located, and the length of the orthographic projection of the partition groove 500 on the flexible substrate 10 includes the first The length of the orthographic projection of the power cord 210 on the flexible substrate 10.
  • the partition groove 500 In the area where the first power cord 210 is located, the surface of the first power cord 210 is exposed in the partition groove 500, and in the area outside the first power cord 210, the partition groove 500 is exposed Out the surface of the composite insulating layer.
  • the partition grooves 500 may be continuous or may be arranged at intervals.
  • the binding area 200 includes a composite insulating layer disposed on the flexible substrate 10, a first power line 210 and a second power line 220 disposed on the composite insulating layer, and a first power line 210 and a second power line 220.
  • the first flat layer 15 on the second power line 220 is formed with a partition groove 500 and an isolation region 600, and a flat dam base 30 is formed in the isolation region 600.
  • “length” refers to the characteristic dimension along the edge of the display area
  • width refers to the characteristic dimension along the direction away from the display area.
  • the transparent conductive film may use indium tin oxide ITO or indium zinc oxide IZO.
  • the pixel definition layer 22 of the display area 100 is provided with pixel openings, and the pixel definition layer 22 in the pixel openings is developed to expose the surface of the anode 21.
  • the first dam foundation 31 and the second dam foundation 32 are formed in the isolation area 600 of the binding area 200, the first dam foundation 31 is formed on the second power line 220 in the isolation area 600, and the second dam foundation 32 is formed on the flat dam foundation 30.
  • the distance between one dam foundation 31 and the display area 100 is smaller than the distance between the second dam foundation 32 and the display area 100, as shown in FIG. 10.
  • the first dam base 31 is used to form a first isolation dam
  • the flat dam base 30 and the second dam base 32 are used to form a second isolation dam.
  • the pixel definition layer may use polyimide, acrylic, polyethylene terephthalate, or the like.
  • the cross-sectional shape of the flat dam base 30, the first dam base 31, the second dam base 32, and the spacer column 33 is a trapezoid, and the first dam base 31 and the The spacer column 33 constitutes the first supporting dam 410, and the flat dam base 30, the second dam foundation 32 and the spacer columns 33 thereon constitute the second supporting dam 420.
  • the distance between the upper end surface of the first supporting dam 410 and the flexible base 10 is smaller than the first
  • the distance between the upper end surface of the second supporting dam 420 and the flexible substrate 10, and the distance between the first supporting dam 410 and the display area 100 is smaller than the distance between the second supporting dam 420 and the display area 100.
  • the width of the orthographic projection of the first supporting dam 410 and the second supporting dam 420 on the flexible substrate 10 is about 20 ⁇ m to about 60 ⁇ m, and the distance between the first supporting dam 410 and the second supporting dam 420 is About 20 ⁇ m to about 60 ⁇ m. In some embodiments, the width of the orthographic projection of the first supporting dam 410 and the second supporting dam 420 on the flexible substrate 10 is about 40 ⁇ m, and the distance between the first supporting dam 410 and the second supporting dam 420 is about 40 ⁇ m.
  • the organic light emitting layer 23 includes a stacked hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer, and is formed in the pixel opening of the display area 100 to realize the connection between the organic light emitting layer 23 and the anode 21, and the cathode 24 is formed on the pixel defining layer 22, connected to the organic light emitting layer 23, and enveloping a plurality of spacer pillars 33 on the pixel defining layer 22.
  • the width of the cathode 24 in the binding area 200 (the distance between the edge of the cathode 24 and the edge of the display area) L1 is smaller than that of the partition groove 500 and the display area.
  • the distance L2 between the regions 100 is to prevent the first power line 210 in the isolation tank 500 from overlapping with the cathode 24.
  • the distance (L2-L1) between the edge of the cathode 24 and the partition groove 500 can be set to be about 50 ⁇ m to about 150 ⁇ m, and an open mask (OPM) can be used to set the edge of the cathode opening.
  • the cathode may use any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or use any of the foregoing metals.
  • Mg magnesium
  • silver Ag
  • aluminum Al
  • Cu copper
  • Li lithium
  • the cathode may use any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or use any of the foregoing metals.
  • the encapsulation layer is formed on the basis of forming the aforementioned pattern.
  • the encapsulation layer includes a first encapsulation layer 25, a second encapsulation layer 26, and a third encapsulation layer 27 that are stacked, as shown in FIG. 13.
  • the first encapsulation layer 25 is made of inorganic materials, covering the cathode 24 in the display area 100, wrapping a plurality of spacer posts 33, covering the partition groove 500, covering the isolation area 600, and wrapping the first support in the isolation area 600 in the binding area 200, respectively.
  • the second encapsulation layer 26 is made of organic materials, and is disposed in the area where the spacers 33 of the display area 100 and the binding area 200 are located.
  • the third encapsulation layer 27 is made of inorganic materials and covers the first encapsulation layer 25 and the second encapsulation layer 26.
  • the partition groove 500 is formed with a surface exposing the first power line 210
  • the first encapsulation layer 25 and the third encapsulation layer 27 made of inorganic materials directly cover the first power line 210, which is on the first power line 210 of organic material.
  • An inorganic material isolation structure is formed in a flat layer 15 to block the propagation path of water vapor along the organic material layer.
  • the isolation region 600 is formed with the surface exposing the second power line 220 and the fourth insulating layer 14, the first encapsulation layer 25 and the third encapsulation layer 27 of inorganic material directly cover the second power line 220 and the fourth insulating layer. On 14th, it can be ensured that outside water vapor cannot enter the display area 100, which improves the packaging effect and process quality.
  • FIG. 14 is a schematic diagram of the structure of the edge of the binding area of the disclosure, and is an enlarged view of the area D in FIG. 13.
  • the area where the first isolation dam and the second isolation dam are located and the area nearby is removed, so after the process of forming the first flat layer, the edges of the first power line 210 and the second power line 220 in this area are exposed.
  • the edges of the first power line 210 and the second power line 220 will be etched by the anode. Erosion by corrosion liquid. Since the etching rate of the etching solution to etch Al is greater than that of Ti, the edges of the first power line 210 and the second power line 220 that are eroded will form side pits, and the Ti layer above the Al layer protrudes from the Al layer. Distance, forming a "eave" structure.
  • the "eave" structure shields the vapor deposited particles, so that the side pits cannot be filled with the encapsulation material, forming a cavity 501 .
  • CVD chemical vapor deposition
  • the cavities 501 at the edges of the first power line 210 and the second power line 220 only exist in the area where the first isolation dam and the second isolation dam are located and their vicinity, the edges of the first power line 210 and the second power line 220 in other areas Covered by the first flat layer, such voids will not be formed, but because the first flat layer of organic material itself conducts water vapor, the water vapor can propagate from the cavity 501 to propagate from the first flat layer until it diffuses to the display area. Cause the display area to appear dark spots due to water and oxygen erosion.
  • the present disclosure cuts off the water vapor intrusion path that appears at the edge of the power line passing through the isolation dam by arranging isolation grooves on the first flat layer.
  • the water vapor circulates along the edge of the power cord to the first flat layer, the water vapor will conduct and diffuse in the first flat layer to the display area.
  • the partition groove is set on the first flat layer, the water vapor is blocked by the partition groove, and the water vapor needs to bypass The partition groove can enter the display area, and the intrusion path is greatly extended, which reduces the risk of GDS, avoids display failures on the display substrate, and improves the display quality.
  • the preparation process of the present disclosure can be realized by using existing mature preparation equipment, has little improvement to the existing process, can be well compatible with the existing preparation process, is simple to implement, easy to implement, high production efficiency, and low production cost. High yield rate. Since the structure and process route of the power cord passing through the isolation dam are relatively common, and the possibility of water vapor intrusion path at the edge of the power cord is very high, the solution of the present disclosure has a wide range of application prospects.
  • the display substrate provided by the present disclosure includes:
  • the first insulating layer 11 disposed on the flexible substrate 10;
  • a first active layer disposed on the first insulating layer 11;
  • the fourth insulating layer 14 covering the second gate metal layer, the fourth insulating layer 14 of the display area 100 is provided with a first via hole, and the first via hole exposes the first active layer;
  • the source-drain metal layer includes at least the first source electrode and the first drain electrode of the display area 100, and the first power line 210 and the second power line of the bonding area 200 220.
  • the first source electrode and the first drain electrode are respectively connected to the first active layer through the first via hole;
  • the first flat layer 15 Covering the first flat layer 15 of the foregoing structure; in the display area 100, the first flat layer 15 is provided with a second via hole K2 exposing the first drain electrode; in the bonding area 200, the first flat layer 15 is provided with The isolation groove 500 and the isolation area 600, the isolation groove 500 exposes the surface of the first power cord 210, the second power cord 220 in the isolation area 600 is provided with a flat dam foundation 30, and the second power cord 220 is exposed outside the flat dam foundation 30 And the fourth insulating layer 14;
  • the pixel defining layer 22, the first dam base 31 and the second dam base 32 are provided with pixel openings on the pixel defining layer 22, and the pixel openings expose the anode 21.
  • the first dam base 31 is arranged on the second power line 220 in the isolation region 600,
  • the second dam foundation 32 is arranged on the flat dam foundation 30;
  • the organic light-emitting layer 23 connected to the anode 21;
  • the distance between the edge of the cathode in the binding area 200 and the display area 100 is smaller than the distance between the partition groove 500 and the display area 100;
  • the present disclosure shows that the structure of the substrate and the preparation process thereof are only an exemplary description.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs.
  • the partition groove may have an arc shape or a broken line shape.
  • the cross-sectional shape of the partition groove may be rectangular or trapezoidal, which is not specifically limited in the present disclosure.
  • FIG. 15 is a schematic diagram showing another structure of the substrate according to the present disclosure, and is a cross-sectional view taken along the line B-B in FIG. 3.
  • the display substrate includes a display area 100 and a binding area 200.
  • the binding area 200 is located on one side of the display area 100.
  • the display area 100 includes a flexible substrate 10, and a drive structure layer disposed on the flexible substrate 10 is provided.
  • the light-emitting element on the driving structure layer and the composite encapsulation layer covering the light-emitting element.
  • the binding area 200 includes a flexible substrate 10, a binding structure layer disposed on the flexible substrate 10, an isolation groove 500 and an isolation region 600 disposed on the binding structure layer, and the isolation region 600 is provided with a first isolation dam 410 and a second isolation dam 410 and a second isolation dam.
  • the structure of the binding structure layer of the display area 100 and the binding area 200 is similar to the corresponding structure described in the foregoing embodiment, and the binding structure layer of the binding area 200 is provided with a first flat layer 15
  • the first flat layer 15 is provided with a partition groove 500 and an isolation region 600.
  • the partition groove 500 is provided in the area where the second power cord 220 is located.
  • the partition groove 500 exposes the surface of the second power cord 220.
  • the line 220 is provided with a first isolation dam 410 and a second isolation dam 420, and the area outside the first isolation dam 410 and the second isolation dam 420 exposes the surface of the second power cord 220 and the composite insulating layer.
  • the inorganic encapsulation layer includes a first encapsulation layer 25 and a third encapsulation layer 27 that are stacked.
  • the first encapsulation layer 25 and the third encapsulation layer 27 made of inorganic materials cover the partition groove 500 and the isolation region 600, and wrap the first isolation dam 410 and The second isolation dam 420.
  • the distance between the edge of the isolation groove 500 adjacent to the first isolation dam 410 and the edge of the first isolation dam 410 adjacent to the isolation groove 500 is about 40 ⁇ m to about 60 ⁇ m.
  • FIG. 16 is a schematic diagram showing another structure of the substrate according to the present disclosure, and is a cross-sectional view taken along the line B-B in FIG. 3.
  • the display substrate includes a display area 100 and a binding area 200.
  • the binding area 200 is located on one side of the display area 100.
  • the display area 100 includes a flexible substrate 10, a drive structure layer disposed on the flexible substrate 10, and The light-emitting element on the driving structure layer and the composite encapsulation layer covering the light-emitting element.
  • the binding area 200 includes a flexible substrate 10, a binding structure layer disposed on the flexible substrate 10, an isolation groove 500 and an isolation region 600 disposed on the binding structure layer, and the isolation region 600 is provided with a first isolation dam 410 and a second isolation dam.
  • the structure of the binding structure layer of the display area 100 and the binding area 200 is similar to the corresponding structure described in the foregoing embodiment, and the binding structure layer of the binding area 200 is provided with a first flat layer 15 , The first flat layer 15 is provided with a partition groove 500 and an isolation region 600, the partition groove 500 is provided in the area between the first power line 210 and the second power line 220, and the partition groove 500 exposes the first power line 210 and the second power line.
  • the second power line 220 of the isolation area 600 is provided with a first isolation dam 410 and a second isolation dam 420, the first isolation dam 410 and the second isolation dam 420
  • the outer area exposes the surface of the second power line 220 and the composite insulating layer.
  • the inorganic encapsulation layer includes a first encapsulation layer 25 and a third encapsulation layer 27 that are stacked.
  • the first encapsulation layer 25 and the third encapsulation layer 27 made of inorganic materials cover the partition groove 500 and the isolation region 600, and wrap the first isolation dam 410 and The second isolation dam 420.
  • the distance between the edge of the isolation groove 500 adjacent to the first isolation dam 410 and the edge of the first isolation dam 410 adjacent to the isolation groove 500 is about 40 ⁇ m to about 60 ⁇ m.
  • FIG. 17 is a schematic diagram showing another structure of the substrate according to the present disclosure, and is a cross-sectional view taken along the line B-B in FIG. 3.
  • the structures of the light-emitting element and the composite encapsulation layer in the display area 100, the isolation groove, the isolation region, the first isolation dam, and the second isolation dam in the binding area 200 are similar to the corresponding structures described in the foregoing embodiment, and are similar to the foregoing embodiment.
  • the difference in the structure described in is that the display substrate further includes a fifth insulating layer 16. As shown in FIG.
  • the driving structure layer of the display area 100 includes: a first insulating layer 11 disposed on the flexible substrate 10, an active layer disposed on the first insulating layer 11, and a second insulating layer covering the first active layer.
  • the fourth insulating layer 14 of the gate metal layer, the source/drain metal layer disposed on the fourth insulating layer 14, covers the fifth insulating layer 16 of the source/drain metal layer.
  • the first flat layer 15 is disposed on the driving structure layer, the light-emitting element is disposed on the first flat layer 15, and the anode 21 in the light-emitting element communicates with the first transistor 101 through the via hole penetrating the fifth insulating layer 16 and the first flat layer 15
  • the first drain electrode is connected.
  • the binding structure layer of the binding area 200 includes: a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14 made of inorganic materials stacked on the flexible substrate 10, which are arranged on the fourth insulating layer.
  • the first power line 210 and the second power line 220 on the insulating layer 14 are provided on the fifth insulating layer 16 on the first power line 210 and the second power line 220.
  • the first flat layer 15 is provided on the binding structure layer.
  • the first flat layer 15 is provided with a partition groove 500 and an isolation region 600.
  • the partition groove 500 is provided in the area where the first power line 210 is located.
  • the partition groove 500 exposes the fifth insulating layer.
  • the first isolation dam 410 and the second isolation dam 420 are arranged in the isolation area 600.
  • the fifth insulating layer 16 in the area where the first isolation dam 410 and the second isolation dam 420 are located is removed, exposing the second power supply
  • the first isolation dam 410 and the second isolation dam 420 are arranged on the second power cord 220.
  • the inorganic encapsulation layer includes a first encapsulation layer 25 and a third encapsulation layer 27 that are stacked.
  • the first encapsulation layer 25 and the third encapsulation layer 27 made of inorganic materials cover the partition groove 500 and the isolation region 600, and wrap the first isolation dam 410 and The second isolation dam 420.
  • the partition groove 500 exposes the surface of the fifth insulating layer 16, and there will be no overlap between the subsequently formed cathode and the first power line 210. Possibly, therefore, the distance L2 between the partition groove 500 and the display area 100 can be greatly reduced, and the distance between the cathode edge and the partition groove 500 to be formed later can be less than 50 ⁇ m, which is beneficial to the location layout of the partition groove 500 and the partition groove 500 It can be close to the display area 100, extend the distance of the water vapor intrusion path, increase the water vapor blocking effect, and also help simplify the process of preparing the partition groove and the cathode, and improve the production efficiency.
  • the edges of the first power line 210 and the second power line 220 are covered by the fifth insulating layer 16, in the subsequent process of etching the anode, the first power line 210 and the second power line 220 The edges will not be corroded by the etching liquid, and side pits will not be formed, thus avoiding the formation of water vapor circulation paths on the edges of the first power line 210 and the second power line 220, and reducing the number of water vapor intrusion paths.
  • the fifth insulating layer 16 in the area where the first isolation dam 410 and the second isolation dam 420 are located may be retained, and the first isolation dam 410 and the second isolation dam 420 may be disposed on the fifth insulating layer 16 On the surface.
  • the partition groove 500 may be provided in the area where the second power cord 220 is located, or the partition groove 500 may be provided in the area between the first power cord 210 and the second power cord 220. The present disclosure is here. Do not make specific restrictions.
  • FIG. 18 is a schematic diagram of another structure of the display substrate of the present disclosure, and is a cross-sectional view in the direction of B-B in FIG.
  • the display substrate In a plane direction parallel to the display substrate, the display substrate includes a display area 100 and a binding area 200, and the binding area 200 is located on one side of the display area 100.
  • the display area 100 In a plane direction perpendicular to the display substrate, the display area 100 includes a flexible substrate 10, a driving structure layer disposed on the flexible substrate 10, a light emitting element disposed on the driving structure layer, and a composite packaging layer covering the light emitting element.
  • the binding area 200 includes a flexible substrate 10, a binding structure layer disposed on the flexible substrate 10, an isolation groove 500 disposed on the binding structure layer, and an isolation region 600 provided with a first isolation dam 410 and a second isolation dam 420 , Covering the isolation trench 500, the first isolation dam 410, the second isolation dam 420, and the inorganic encapsulation layer of the isolation region 600.
  • the driving structure layer of the display area 100 includes a plurality of transistors and storage capacitors forming a pixel driving circuit.
  • one first transistor 101 and one first storage capacitor 102 are taken as examples for illustration.
  • the driving structure layer of the display area 100 includes: a first insulating layer 11 arranged on the flexible substrate 10, an active layer arranged on the first insulating layer 11, a second insulating layer 12 covering the first active layer, arranged on the The first gate metal layer on the second insulating layer 12 covers the third insulating layer 13 of the first gate metal layer, and the second gate metal layer disposed on the third insulating layer 13 covers the fourth layer of the second gate metal layer.
  • the insulating layer 14, the source and drain metal layers disposed on the fourth insulating layer 14, the fifth insulating layer 16 covering the source and drain metal layers, and the first flat layer 15 disposed on the fifth insulating layer 16, are disposed on the first flat layer.
  • the active layer includes at least a first active layer, the first gate metal layer includes at least a first gate electrode and a first capacitor electrode, the second gate metal layer includes at least a second capacitor electrode, and the source-drain metal layer includes at least a first source electrode And the first drain electrode, the metal conductive layer includes at least a first connection electrode 801, the first connection electrode 801 is connected to the first drain electrode of the first transistor 101 through a via hole, the first active layer, the first gate electrode, the first The source electrode and the first drain electrode constitute the first transistor 101, and the first capacitor electrode and the second capacitor electrode constitute the first storage capacitor 102.
  • the source-drain metal layer is referred to as the first source-drain metal layer (SD1)
  • the metal conductive layer is referred to as the second source-drain metal layer (SD2).
  • SD1 the source-drain metal layer
  • SD2 the metal conductive layer
  • SD2 the metal conductive layer
  • a second flat layer 17 is provided on the driving structure layer of the display area 100, the second flat layer 17 covers the metal conductive layer, and the light-emitting element is provided on the second flat layer 17.
  • the light-emitting element includes an anode 21, a pixel definition layer 22, and organic light emitting.
  • the layer 23 and the cathode 24, and the anode 21 are connected to the connection electrode 801 through the via hole opened in the second flat layer 17, so that the anode 21 is connected to the first drain electrode of the first transistor 101.
  • the composite encapsulation layer includes a first encapsulation layer 25, a second encapsulation layer 26, and a third encapsulation layer 27 that are stacked.
  • the second encapsulation layer 26 of organic material is disposed between the first encapsulation layer 25 and the third encapsulation layer 27 of inorganic material. between.
  • the binding structure layer of the binding area 200 includes: a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, a fourth insulating layer 14 and a fifth insulating layer of inorganic materials stacked on the flexible substrate 10 16.
  • the first flat layer 15 of organic material disposed on the fifth insulating layer 16, the first power line 210 and the second power line 220 disposed on the first flat layer 15, and the second power line 220 is far away from the display area 100
  • the edge of the first flat layer 15 covers the edge of the first flat layer 15 away from the display area 100.
  • the first power line 210 and the second power line 220 are arranged in the same layer as the metal conductive layer of the display area 100, and are formed by the same patterning process.
  • a second flat layer 17 is provided on the binding structure layer of the binding area 200.
  • the second flat layer 17 serves as the organic insulating layer of the present disclosure.
  • the second flat layer 17 is provided with a partition groove 500 and an isolation region 600.
  • the partition groove 500 Set in the area where the first power line 210 is located, the isolation groove 500 exposes the surface of the first power line 210, the isolation area 600 is provided on the side of the second power line 220 away from the display area 100, and the isolation area 600 is provided with the first isolation
  • the dam 410 and the second isolation dam 420, the first isolation dam 410 and the second isolation dam 420 are arranged on the second power line 220, except for the location of the first isolation dam 410 and the second isolation dam 420, other positions of the isolation area 600
  • the surfaces of the second power line 220 and the fifth insulating layer 16 are exposed.
  • the inorganic encapsulation layer includes a first encapsulation layer 25 and a third encapsulation layer 27 that are stacked.
  • the first encapsulation layer 25 and the third encapsulation layer 27 made of inorganic materials cover the partition groove 500 and the isolation region 600, and wrap the first isolation dam 410 and The second isolation dam 420.
  • the second flat layer 17 adjacent to the display area 100 is provided with a pixel defining layer 22, a plurality of spacer pillars 33 are arranged on the pixel defining layer 22, and the cathode 24 wraps the plurality of spacer pillars 33.
  • the isolation groove 500 may be one or more, the width of the isolation groove 500 is about 20 ⁇ m to about 50 ⁇ m, and the distance between the isolation groove 500 and the display area edge 110 is smaller than the first isolation dam 410 and the display area edge 110 The distance between the isolation groove 500 and the edge 110 of the display area is greater than the distance between the edge of the cathode 24 and the edge 110 of the display area.
  • the isolation groove 500 may be disposed in the area where the second power cord 220 is located, and the isolation groove 500 exposes the surface of the second power cord 220.
  • the partition groove 500 may be provided in the area between the first power line 210 and the second power line 220, and the first flat layer 15 and the second flat layer 17 in the partition groove 500 are removed, exposing the first power line 210 The surface of the fifth insulating layer 16 in the area between the second power line 220 and the second power line 220.
  • the first power line 210 and the second power line 220 may be formed on the fourth insulating layer 14, arranged in the same layer as the source and drain metal layers of the display area 100, and formed by the same patterning process.
  • the first flat layer 15 and the second flat layer 17 are formed, the first flat layer 15 and the second flat layer 17 in the partition groove 500 are removed, and the partition groove 500 exposes the fifth insulating layer 16 surface.
  • the first isolation dam 410 and the second isolation dam 420 are arranged on the second power line by removing the fifth insulating layer 16, the first flat layer 15 and the second flat layer 17 in some areas. 220 up.
  • the isolation groove 500 may be arranged at the position where the second power cord 220 is located, or in the area between the first power cord 210 and the second power cord 220, and the present disclosure does not specifically limit it here. .
  • the present disclosure cuts off the water vapor intrusion path appearing at the edge of the first power line 210 and the edge of the second power line 220 by arranging isolation grooves on the second flat layer.
  • the water vapor circulates to the second flat layer along the edge of the first power line 210 and the edge of the second power line 220, the water vapor will conduct and diffuse in the second flat layer to the display area.
  • the partition groove is set on the second flat layer, the water vapor Blocked by the partition groove, water vapor needs to bypass the partition groove to enter the display area.
  • the intrusion path is greatly extended, reducing the risk of GDS, avoiding poor display on the display substrate, and improving display quality.
  • FIG. 19 is a schematic diagram showing another structure of the substrate according to the present disclosure, and is a cross-sectional view in the direction of B-B in FIG. 3.
  • the structure in the display area 100, the structure of the isolation groove, the isolation area, the first isolation dam, and the second isolation dam in the binding area 200 are similar to the corresponding structures described in the embodiment shown in FIG. 18, and are similar to the embodiment shown in FIG. 18
  • the difference in the structure described in is that the bonding structure layer of the bonding area 200 further includes a second connection electrode 802 and a third connection electrode 803. As shown in FIG.
  • the binding structure layer of the binding area 200 includes: a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer of an inorganic material stacked on the flexible substrate 10. 14.
  • the second connection electrode 802 and the third connection electrode 803 disposed on the fourth insulating layer 14, the fifth insulating layer 16 disposed on the second connection electrode 802 and the third connection electrode 803, and the fifth insulating layer 16 The first flat layer 15 on the upper surface, the first power line 210 and the second power line 220 disposed on the first flat layer 15, the first power line 210 passes through the via hole penetrating the first flat layer 15 and the fifth insulating layer 16 Connected to the second connection electrode 802, the second power line 220 is connected to the third connection electrode 803 through a via hole penetrating the first flat layer 15 and the fifth insulating layer 16, and the edge of the second power line 220 away from the display area 100 covers the first A flat layer 15 is far away from the edge of the display area 100.
  • the second connection electrode 802 and the third connection electrode 803 are arranged in the same layer as the source and drain metal layers of the display area 100, and are formed by the same patterning process.
  • the first power line 210 and the second power line 220 are conductive to the metal of the display area 100
  • the layers are arranged in the same layer and formed by the same patterning process.
  • the first power line 210 and the second connection electrode 802 are connected through a via hole, and the second power line 220 is connected to the second connection electrode 802 through a via hole.
  • the three connecting electrodes 803 are connected through vias, which increases the flexibility of the layout of the first power line 210 and the second power line 220, and is beneficial to optimizing the film structure of the bonding area 200.
  • FIG. 20 is a schematic diagram showing another structure of the substrate according to the present disclosure, and is a cross-sectional view in the direction of B-B in FIG. 3.
  • the structure in the display area 100, the structure of the isolation groove, the isolation area, the first isolation dam, and the second isolation dam in the binding area 200 are similar to the corresponding structures described in the embodiment shown in FIG. 19, and are similar to the embodiment shown in FIG. 19
  • the difference in the structure described in is that the bonding structure layer of the bonding area 200 is not provided with a fifth insulating layer. As shown in FIG.
  • the binding structure layer of the binding area 200 includes: a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14 stacked on the flexible substrate 10, and
  • the second connection electrode 802 and the third connection electrode 803 on the fourth insulating layer 14 are arranged on the first flat layer 15 of the second connection electrode 802 and the third connection electrode 803, and the first flat layer 15 is arranged on the first flat layer 15.
  • a power cord 210 and a second power cord 220, the first power cord 210 is connected to the second connection electrode 802 through a via hole, and the second power cord 220 is connected to the third connection electrode 803 through a via hole.
  • the fifth insulating layer 16 since the fifth insulating layer 16 is not formed, the number of manufacturing processes is reduced, and the process complexity is reduced.
  • FIG. 21 is a schematic diagram showing another structure of the substrate according to the present disclosure, and is a cross-sectional view taken along the line B-B in FIG. 3.
  • the structure in the display area 100, the structure of the isolation groove, the isolation area, the first isolation dam, and the second isolation dam in the binding area 200 are similar to the corresponding structures described in the embodiment shown in FIG. 20, and are similar to the embodiment shown in FIG. 20
  • the difference in the structure described in is that the first flat layer 15 of the binding area 200 is removed. As shown in FIG.
  • the binding structure layer of the binding area 200 includes: a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14 stacked on the flexible substrate 10, and The second connection electrode 802 and the third connection electrode 803 on the fourth insulating layer 14, the first power line 210 provided on the second connection electrode 802 and the second power line 220 provided on the third connection electrode 803.
  • the first power line 210 is directly connected to the second connection electrode 802
  • the second power line 220 is directly connected to the third connection electrode 803
  • the contact area is increased, and the connection reliability is increased, but also the gas generated in the process of preparing the first flat layer 15 is reduced, and the process quality is improved.
  • part of the first flat layer 15 of the binding area 200 may be removed.
  • the first flat layer 15 where the first power line 210 and the second power line 220 are located is removed, and the first flat layer 15 is left in other areas.
  • the flat layer 15 is such that the first power line 210 is directly connected to the second connection electrode 802, and the second power line 220 is directly connected to the third connection electrode 803.
  • the first flat layer and the fifth insulating layer of the binding area 200 may be removed together, or a part of the first flat layer and the fifth insulating layer of the binding area 200 may be removed.
  • the flat layer and the fifth insulating layer, or part of the fifth insulating layer of the bonding region 200 and all the first flat layer of the bonding region 200 may be removed, which is not specifically limited in the present disclosure.
  • FIG. 22 is a schematic diagram of another structure of the first fan-out area of the present disclosure.
  • the display substrate includes a display area 100, a binding area 200 and an edge area 300, the binding area 200 is located on one side of the display area 100, and the edge area 300 is located on the other side of the display area 100.
  • the binding area 200 includes at least a first fan-out area, a first isolation dam 410, a second isolation dam 420, and a partition groove 500 located in the first fan-out area
  • the edge area 300 includes at least a first isolation dam 410 and a second isolation dam 420 and the gap 700, the first isolation dam 410 and the second isolation dam 420 of the binding area 200 and the first isolation dam 410 and the second isolation dam 420 of the edge area 300 are arranged in the same layer and prepared simultaneously by the same patterning process
  • the integral structure forms a ring structure surrounding the display area 100.
  • the partition groove 500 of the binding area 200 and the gap 700 of the edge area 300 are simultaneously prepared by the same patterning process, and are connected to each other at the junction of the binding area 200 and the edge area 300.
  • FIG. 23 is a schematic cross-sectional structure diagram of the display area and the edge area of the dual source-drain metal layer (2SD) structure of the present disclosure, and is a cross-sectional view taken along the line C-C in FIG. 22.
  • the display area 100 in a plane perpendicular to the display substrate, the display area 100 includes a flexible substrate 10, a driving structure layer disposed on the flexible substrate 10, a light emitting element disposed on the driving structure layer, and a composite package covering the light emitting element Floor.
  • the edge area 300 includes a flexible substrate 10, a circuit structure layer disposed on the flexible substrate 10, a gap 700 disposed on the circuit structure layer, a first isolation dam 410 and a second isolation dam 420, a composite packaging layer covering the gap 700, and a package The inorganic encapsulation layer of the first isolation dam 410 and the second isolation dam 420.
  • the driving structure layer of the display area 100 includes a plurality of transistors and storage capacitors forming a pixel driving circuit.
  • one first transistor 101 and one first storage capacitor 102 are taken as an example for illustration.
  • the driving structure layer of the display area 100 includes: a first insulating layer 11 disposed on the flexible substrate 10, an active layer disposed on the first insulating layer 11, a second insulating layer 12 covering the active layer, and a second insulating layer 12 disposed on the second insulating layer.
  • the active layer includes at least a first active layer
  • the first gate metal layer includes at least a first gate electrode and a first capacitor electrode
  • the second gate metal layer includes at least a second capacitor electrode
  • the source-drain metal layer includes at least a first source electrode
  • the metal conductive layer includes at least a first connection electrode 801, the first connection electrode 801 is connected to the first drain electrode through a via hole, the first active layer, the first gate electrode, the first source electrode and the first
  • the drain electrode constitutes the first transistor 101
  • the first capacitor electrode and the second capacitor electrode constitute the first storage capacitor 102.
  • the source-drain metal layer is referred to as the first source-drain metal layer (SD1)
  • the metal conductive layer is referred to as the second source-drain metal layer (SD2).
  • SD1 the source-drain metal layer
  • SD2 the metal conductive layer
  • SD2 the metal conductive layer
  • a second flat layer 17 is provided on the driving structure layer of the display area 100, the second flat layer 17 covers the metal conductive layer, and the light-emitting element is provided on the second flat layer 17.
  • the light-emitting element includes an anode 21, a pixel definition layer 22, and organic light emitting.
  • the layer 23 and the cathode 24, and the anode 21 are connected to the connection electrode 801 through the via hole opened in the second flat layer 17, so that the anode 21 is connected to the first drain electrode of the first transistor 101.
  • the composite encapsulation layer includes a first encapsulation layer 25, a second encapsulation layer 26, and a third encapsulation layer 27 that are stacked.
  • the second encapsulation layer 26 of organic material is disposed between the first encapsulation layer 25 and the third encapsulation layer 27 of inorganic material. between.
  • the circuit structure layer of the edge region 300 includes a plurality of transistors and storage capacitors forming a GOA circuit.
  • the circuit structure layer of the edge region 300 includes: a first insulating layer 11 disposed on the flexible substrate 10, an active layer disposed on the first insulating layer 11, a second insulating layer 12 covering the active layer, and a second insulating layer 12 disposed on the second insulating layer.
  • the active layer includes at least a second active layer and a third active layer
  • the first gate metal layer includes at least a second gate electrode, a third gate electrode, a third capacitor electrode and a fourth capacitor electrode
  • the second gate metal layer at least It includes a fifth capacitor electrode and a sixth capacitor electrode.
  • the source-drain metal layer includes at least a second source electrode, a second drain electrode, a third source electrode, a third drain electrode, and a third connecting electrode 803.
  • the metal conductive layer includes at least a second Power cord 220.
  • the second active layer, the second gate electrode, the second source electrode and the second drain electrode constitute the second transistor 103
  • the third active layer, the third gate electrode, the third source electrode and the third drain electrode constitute the third transistor 104
  • the third capacitor electrode and the fifth capacitor electrode constitute a second storage capacitor 105
  • the fourth capacitor electrode and the sixth capacitor electrode constitute a third storage capacitor 106.
  • the first transistor 101 may be a driving transistor
  • the second transistor 103 may be a scan transistor that outputs a scan (SCAN) signal in GOA
  • the third transistor 104 may be an enable (EM) signal that outputs an enable (EM) signal in GOA.
  • the driving transistor, the scan transistor, and the enable transistor may be thin film transistors.
  • a second flat layer 17 is provided on the circuit structure layer of the edge region 300, and the second flat layer 17 is provided with a gap 700, a first isolation dam 410, and a second isolation dam 420.
  • the gap 700 is disposed between the second power line 220 and the display Between the regions 100, the first flat layer 15 and the second flat layer 17 in the gap 700 are removed, and the surface of the fifth insulating layer 16 is exposed.
  • the first isolation dam 410 is disposed at the position where the second power cord 220 is located, and the second isolation dam 420 is disposed on the side of the first isolation dam 410 away from the display area 100.
  • the composite encapsulation layer includes a first encapsulation layer 25, a second encapsulation layer 26, and a third encapsulation layer 27 that are stacked, the composite encapsulation layer covers the gap 700, and the inorganic encapsulation layer includes the first encapsulation layer 25 and the third encapsulation layer 27 that are stacked , The inorganic encapsulation layer wraps the first isolation dam 410 and the second isolation dam 420.
  • a plurality of spacer posts 33 are provided on the second flat layer 17 of the edge region 300 adjacent to the display region 100.
  • the driving structure layer of the display area 100, the bonding structure layer of the bonding area 200, and the circuit structure layer of the edge area 300 are simultaneously formed using the same process.
  • the first active layer in the driving structure layer is arranged in the same layer as the second active layer and the third active layer in the circuit structure layer, and is formed by the same patterning process.
  • the first gate electrode and the first capacitor electrode in the driving structure layer are arranged in the same layer as the second gate electrode, third gate electrode, third capacitor electrode and fourth capacitor electrode in the circuit structure layer, and are formed by the same patterning process .
  • the second capacitor electrode in the driving structure layer is arranged in the same layer as the fifth capacitor electrode and the sixth capacitor electrode in the circuit structure layer, and is formed by the same patterning process.
  • the first source electrode and the first drain electrode in the driving structure layer, the second connection electrode and the third connection electrode in the binding structure layer, and the second source electrode, the second drain electrode, and the third source in the circuit structure layer are arranged in the same layer and formed by the same patterning process.
  • the first connection electrode in the driving structure layer, the first power line and the second power line in the binding structure layer, and the second power line in the circuit structure layer are arranged in the same layer, and are formed by the same patterning process.
  • the second flat layer 17 in the edge region 300 and the gap 700 provided on the second flat layer 17 and the second flat layer 17 in the binding region 200 and the partition groove 500 provided on the second flat layer 17 are formed by the same process .
  • the first isolation dam, the second isolation dam, the first encapsulation layer, and the third encapsulation layer in the edge area 300 and the first isolation dam, the second isolation dam, the first encapsulation layer, and the third encapsulation layer in the binding area 200 It is arranged in the same layer and formed by the same patterning process.
  • the partition groove 500 of the binding area 200 and the gap 700 of the edge area 300 are simultaneously formed, and the two are connected at the junction of the binding area 200 and the edge area 300 to form a whole structure.
  • the connected partition groove 500 and the gap 700 increase the water vapor isolation range, extend the water vapor intrusion path, reduce the risk of GDS, avoid display failure of the display substrate, and improve the display quality.
  • the preparation process of the display substrate includes:
  • the driving structure layer, the bonding structure layer, and the circuit structure layer patterns are formed in the display area 100, the binding area 200, and the edge area 300, respectively.
  • the driving structure layer of the display area 100 includes a first transistor 101, a first capacitor electrode 102, and a first connection electrode 801.
  • the bonding structure layer of the bonding area 200 includes a second connection electrode 802 and a third connection electrode 803, and an edge area 300
  • the circuit structure layer includes a second transistor 103, a third transistor 104, a second storage capacitor 105, a third storage capacitor 106, and a third connection electrode 803.
  • the preparation process of the driving structure layer, the binding structure layer, and the circuit structure layer may include:
  • a first insulating layer 11 and an active layer pattern disposed on the first insulating layer 11 are formed on the flexible substrate 10.
  • the active layer includes at least a first active layer, a second active layer, and a third active layer.
  • a second insulating layer 12 covering the active layer pattern is formed, and a first gate metal layer pattern disposed on the second insulating layer 12 is formed.
  • the first gate metal layer includes at least a first gate electrode, a second gate electrode, and a third gate electrode. Electrodes, a first capacitor electrode, a third capacitor electrode, and a fourth capacitor electrode.
  • a third insulating layer 13 covering the first gate metal layer and a second gate metal layer pattern disposed on the third insulating layer 13 are formed.
  • the second gate metal layer pattern includes at least a second capacitor electrode, a fifth capacitor electrode, and a second capacitor electrode. Six capacitor electrodes.
  • a pattern of the fourth insulating layer 14 covering the second gate metal layer is formed, and the fourth insulating layer 14 is provided with a plurality of first via holes.
  • a source-drain metal layer pattern is formed on the fourth insulating layer 14.
  • the source-drain metal layer includes at least a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, a third source electrode, and a third drain electrode.
  • the second connection electrode 802 and the third connection electrode 803, the first source electrode and the first drain electrode are respectively connected to the first active layer through the first via hole, and the second source electrode and the second drain electrode are respectively connected through the first via hole Connected to the second active layer, and the third source electrode and the third drain electrode are respectively connected to the third active layer through the first via hole.
  • a pattern of the fifth insulating layer 16 and the first planarization layer 15 covering the source and drain metal layers is formed, a plurality of second via holes are formed on the first planarization layer 15, and the second via holes of the display area 100 expose the first transistor 101
  • the surface of the first drain electrode, the second via hole in the binding area 200 respectively exposes the surface of the second connection electrode 802 and the third connection electrode 803, and the second via hole in the edge area exposes the surface of the third connection electrode 803 .
  • a metal conductive layer pattern is formed on the first flat layer 15.
  • the metal conductive layer includes at least a first connection electrode 801, a first power line 210, and a second power line 220.
  • the first connection electrode 801 of the display area 100 passes through the second via hole.
  • the first power line 210 and the second power line 220 of the bonding area 200 are respectively connected to the second connection electrode 802 and the third connection electrode 803 through the second via hole, and the edge area
  • the second power line 220 is connected to the third connection electrode 803 through the second via hole, and the edge of the second power line 220 away from the display area 100 covers the edge of the first flat layer 15 away from the display area 100.
  • a pattern of the second flat layer 17 is formed.
  • the second flat layer 17 of the display area 100 is provided with a third via hole, and the third via hole exposes the surface of the first connection electrode 801.
  • the second flat layer 17 of the binding area 200 is provided with a partition groove 500 and an isolation area 600.
  • the partition groove 500 is provided in the area where the first power line 210 is located.
  • the partition groove 500 exposes the surface of the first power line 210, and the isolation area 600 It is arranged on the side of the second power cord 220 away from the display area 100.
  • the second power cord 220 in the isolation area 600 is provided with a flat dam foundation. Except for the flat dam foundation, the second flat layer 17 in other positions of the isolation area 600 is developed.
  • the surface of the second power line 220 and the surface of the fifth insulating layer 16 are exposed.
  • the second flat layer 17 of the edge region 300 is provided with a fourth via hole and a gap 700, and a flat dam foundation is arranged in the fourth via hole. Except for the flat dam foundation, the second flat layer 17 in the fourth via hole is developed and exposed.
  • the surface of the second power cord 220 is exposed, and the gap 700 is arranged between the second power cord 220 and the display area 100.
  • the first flat layer 15 and the second flat layer 17 in the gap 700 are developed away, exposing the fifth insulating layer The surface of 16.
  • the orthographic projection of the opening of the second flat layer 17 on the flexible substrate 10 includes the opening of the first flat layer 15, that is, the opening width of the second flat layer 17 is greater than the opening width of the first flat layer 15.
  • the opening of a flat layer 15 exposes the fifth insulating layer 16, and the opening of the second flat layer 17 exposes the opening of the first flat layer 15.
  • a step is formed on the sidewall of the gap 700, so that the subsequently formed cathode also has a step Shape to ensure a reliable connection between the cathode and the fourth connecting electrode.
  • the anode 21 and the fourth connection electrode 804 are patterned on the substrate forming the aforementioned pattern.
  • the anode 21 is formed on the second flat layer 17 of the display area 100 and is connected to the first connection electrode 801 through the third via hole.
  • the four connecting electrodes 804 are formed on the second flat layer 17 of the edge region 300.
  • a part of the fourth connecting electrodes 804 is connected to the second power line 220 through the fourth via hole, and the other part is arranged in the gap 700.
  • the fourth via hole is connected to the The fourth connection electrode 804 between the gaps 700 is provided with a plurality of via holes. Since the sidewall of the gap 700 is stepped, the fourth connection electrode 804 disposed in the gap 700 is also stepped.
  • the pixel defining layer 22, the first dam base and the second dam base pattern are formed on the substrate forming the aforementioned pattern.
  • the pixel defining layer 22 of the display area 100 is provided with pixel openings that expose the surface of the anode 21.
  • the first dam foundation and the second dam foundation are formed in the binding area 200 and the edge area 300, the first dam foundation of the binding area 200 is formed on the second power line 220, and the second dam foundation is formed on a flat dam foundation.
  • the first dam foundation of the edge area 300 is arranged in the fourth via hole, and the second dam foundation is arranged on the second flat layer 17 on the side of the first dam foundation away from the display area 100.
  • a plurality of isolation pillars 33 patterns are formed in the binding area 200 and the edge area 300, and the plurality of isolation pillars 33 are respectively arranged on the pixel definition layer 22, the first dam foundation, the second dam foundation, and the positions on both sides of the gap 700.
  • the fixed area 200 and the edge area 300 simultaneously form a first supporting dam 410 and a second supporting dam 420, the binding area 200 and the first supporting dam 410 of the edge area 300 are integrated, and the binding area 200 and the second supporting dam 300 of the edge area
  • the supporting dam 420 is an integral structure.
  • An organic light-emitting layer 23 and a cathode 24 are sequentially formed on the substrate forming the aforementioned pattern.
  • the organic light emitting layer 23 is formed in the pixel opening. Since the anode 21 is connected to the first connection electrode 801 and the first connection electrode 801 is connected to the drain electrode of the first transistor 101, the light emission control of the organic light emitting layer 23 is realized.
  • a part of the cathode 24 is formed on the organic light emitting layer 23 of the display area 100 and the other part is formed on the binding area 200 and the edge area 300.
  • the cathode 24 of the binding area 200 wraps the plurality of spacer posts 33 on the pixel definition layer 22, and the cathode 24 of the edge area 300 is connected to the fourth connection electrode 804 through the gap 700 and the fourth via hole. Since the fourth connection electrode 804 is connected to the second power line 220, the cathode 24 and the second power line 220 are connected. Since the fourth connecting electrode 804 at the position of the gap 700 is stepped, the formed cathode 24 also has a stepped shape, and contacts the fourth connecting electrode 804 on different steps, ensuring a reliable connection between the cathode and the fourth connecting electrode 804 .
  • the encapsulation layer is formed on the basis of forming the aforementioned pattern.
  • the encapsulation layer includes a first encapsulation layer 25, a second encapsulation layer 26, and a third encapsulation layer 27 that are stacked.
  • the first encapsulating layer 25 is made of inorganic materials, covering the cathode 24 in the display area 100, wrapping a plurality of spacer posts 33, covering the partition groove 500, covering the isolation area 600, and wrapping the first supporting dam 410 and the second supporting dam 410 and the second supporting dam in the binding area 200.
  • the supporting dam 420 wraps a plurality of spacer posts 33 in the edge area 300, covers the gap 700, and wraps the first supporting dam 410 and the second supporting dam 420.
  • the second encapsulation layer 26 is made of organic materials and is arranged in the display area 100, the area where the spacers 33 of the binding area 200 are located, and the area where the spacers 33 of the edge area 300 are located.
  • the third encapsulation layer 27 is made of inorganic materials to cover the first The encapsulation layer 25 and the second encapsulation layer 26.
  • the display area 100 includes a flexible substrate 10, a driving structure layer disposed on the flexible substrate 10, a light emitting element disposed on the driving structure layer, and a composite package covering the light emitting element Floor.
  • the edge area 300 includes a flexible substrate 10, a circuit structure layer disposed on the flexible substrate 10, a gap 700 disposed on the circuit structure layer, a first isolation dam 410 and a second isolation dam 420, a composite packaging layer covering the gap 700, and a package The inorganic encapsulation layer of the first isolation dam 410 and the second isolation dam 420.
  • the driving structure layer of the display area 100 includes a plurality of transistors and storage capacitors forming a pixel driving circuit
  • the circuit structure layer of the edge area 300 includes a plurality of transistors and storage capacitors forming a GOA circuit, as shown in FIG. 24
  • Three transistors and triple storage capacitors are taken as examples for illustration.
  • the drive structure layer and the circuit structure layer include: a first insulating layer 11 disposed on the flexible substrate 10, an active layer disposed on the first insulating layer 11, a second insulating layer 12 covering the active layer, and a second insulating layer 12 disposed on the second insulating layer.
  • the source/drain metal layer disposed on the fourth insulating layer 14 covers the fifth insulating layer 16 of the source/drain metal layer.
  • the active layer includes at least a first active layer, a second active layer, and a third active layer.
  • the first gate metal layer includes at least a first gate electrode, a second gate electrode, a third gate electrode, a first capacitor electrode, The third capacitor electrode and the fourth capacitor electrode, the second gate metal layer includes at least a second capacitor electrode, a fifth capacitor electrode, and a sixth capacitor electrode, and the source-drain metal layer includes at least a first source electrode, a first drain electrode, and a second capacitor electrode.
  • the first active layer, the first gate electrode, the first source electrode and the first drain electrode constitute the first transistor 101, and the second active layer, the second gate electrode, the second source electrode and the second drain electrode constitute the second transistor. 103.
  • the third active layer, the third gate electrode, the third source electrode, and the third drain electrode constitute the third transistor 104, the first capacitor electrode and the second capacitor electrode constitute the first storage capacitor 102, and the third capacitor electrode and the third capacitor electrode
  • the five capacitor electrodes constitute the second storage capacitor 105, and the fourth capacitor electrode and the sixth capacitor electrode constitute the third storage capacitor 106.
  • the driving structure layer and the circuit structure layer are provided with a first flat layer 15, and the light-emitting elements of the display area 100 are provided on the first flat layer 15.
  • the light-emitting elements include an anode 21, a pixel defining layer 22, an organic light-emitting layer 23 and a cathode 24,
  • the anode 21 is connected to the first drain electrode of the first transistor 101 through a via hole opened on the first flat layer 15.
  • the first flat layer 15 of the edge area 300 is provided with a gap 700, a spacer column 33, a first isolation dam 410, and a second isolation dam 420.
  • the gap 700 is disposed between the second power line 220 and the display area 100, and the gap 700
  • the first flat layer 15 is removed, exposing the surface of the fifth insulating layer 16, a plurality of spacer pillars 33 are located on the first flat layer 15 in the edge region 300 adjacent to the display region 100, the first isolation dam 410 and the second isolation dam 410
  • the isolation dam 42 is arranged at the position where the second power cord 220 is located, and the second isolation dam 420 is arranged on the side of the first isolation dam 410 away from the display area 100.
  • the composite encapsulation layer includes a first encapsulation layer 25, a second encapsulation layer 26, and a third encapsulation layer 27 that are stacked.
  • the composite encapsulation layer covers the gap 700 between the display area 100 and the edge area 300 and a plurality of spacer pillars 33.
  • Inorganic encapsulation layer It includes a first encapsulation layer 25 and a third encapsulation layer 27 that are stacked, and the inorganic encapsulation layer wraps the first isolation dam 410 and the second isolation dam 420.
  • the driving structure layer of the display area 100, the bonding structure layer of the bonding area 200, and the circuit structure layer of the edge area 300 are simultaneously formed using the same process.
  • the first flat layer 15 in the edge region 300 and the gap 700 provided on the first flat layer 15 and the first flat layer 15 in the binding region 200 and the partition groove 500 provided on the first flat layer 15 are formed by the same process .
  • the first isolation dam, the second isolation dam, the first encapsulation layer, and the third encapsulation layer in the edge area 300 and the first isolation dam, the second isolation dam, the first encapsulation layer, and the third encapsulation layer in the binding area 200 It is arranged in the same layer and formed by the same patterning process.
  • the partition groove 500 of the binding area 200 and the gap 700 of the edge area 300 are simultaneously formed, and the two are connected at the junction of the binding area 200 and the edge area 300 to form a whole structure.
  • the connected partition groove 500 and the gap 700 increase the water vapor isolation range, extend the water vapor intrusion path, reduce the risk of GDS, avoid display failure of the display substrate, and improve the display quality.
  • the preparation process of the display substrate includes:
  • the driving structure layer, the bonding structure layer, and the circuit structure layer patterns are formed in the display area 100, the binding area 200, and the edge area 300, respectively.
  • the preparation process of the driving structure layer, the binding structure layer, and the circuit structure layer may include:
  • a first insulating layer 11 and an active layer pattern disposed on the first insulating layer 11 are formed on the flexible substrate 10.
  • the active layer includes at least a first active layer, a second active layer, and a third active layer.
  • a second insulating layer 12 covering the active layer pattern is formed, and a first gate metal layer pattern disposed on the second insulating layer 12 is formed.
  • the first gate metal layer includes at least a first gate electrode, a second gate electrode, and a third gate electrode. Electrodes, a first capacitor electrode, a third capacitor electrode, and a fourth capacitor electrode.
  • a third insulating layer 13 covering the first gate metal layer and a second gate metal layer pattern disposed on the third insulating layer 13 are formed.
  • the second gate metal layer pattern includes at least a second capacitor electrode, a fifth capacitor electrode, and a second capacitor electrode. Six capacitor electrodes.
  • a pattern of the fourth insulating layer 14 covering the second gate metal layer is formed, and the fourth insulating layer 14 is provided with a plurality of first via holes.
  • a source-drain metal layer pattern is formed on the fourth insulating layer 14.
  • the source-drain metal layer includes at least a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, a third source electrode, and a third drain electrode.
  • the first source electrode and the first drain electrode are respectively connected to the first active layer through the first via hole, and the second source electrode and the second drain electrode are respectively connected through the first via hole and the second active layer Connected, the third source electrode and the third drain electrode are respectively connected to the third active layer through the first via hole.
  • a fifth insulating layer 16 covering the source and drain metal layers is formed.
  • a pattern of the first flat layer 15 is formed.
  • the first flat layer 15 of the display area 100 is provided with a via hole, and the via hole exposes the first drain electrode of the first transistor 101.
  • a partition groove 500 and an isolation region 600 are formed on the first flat layer 15 of the binding area 200.
  • the partition groove 500 is disposed in the area where the first power line 210 is located.
  • the partition groove 500 exposes the surface of the first power line 210, and the isolation region 600 It is arranged on the side of the second power cord 220 away from the display area 100, and a flat dam foundation is provided on the second power cord 220 in the isolation area 600.
  • the first flat layer 15 of the edge area 300 is provided with a fourth via hole and a gap 700, the fourth via hole exposes the surface of the second power line 220, and the gap 700 is disposed between the second power line 220 and the display area 100, The gap 700 exposes the surface of the fifth insulating layer 16, and the flat dam is disposed on the side of the fourth via hole away from the display area 100.
  • the anode 21 and the fourth connection electrode 804 are patterned on the substrate forming the aforementioned pattern.
  • the anode 21 is formed on the first flat layer 15 of the display area 100 and is connected to the first drain electrode of the first transistor 101 through a via hole.
  • the fourth connection electrode 804 is formed on the first flat layer 15 of the edge region 300, a part of the fourth connection electrode 804 is connected to the second power line 220 through the fourth via hole, the other part is disposed in the gap 700, and the fourth connection electrode 804 is The fourth connection electrode 804 between the hole and the gap 700 is provided with a plurality of via holes.
  • the pixel defining layer 22, the first dam base and the second dam base pattern are formed on the substrate forming the aforementioned pattern.
  • the pixel defining layer 22 of the display area 100 is provided with pixel openings, and the pixel openings expose the surface of the anode 21.
  • the first dam foundation and the second dam foundation are formed in the binding area 200 and the edge area 300.
  • the first dam foundation of the binding area 200 is formed on the second power line 220, and the second dam foundation is formed on the flat dam foundation.
  • the dam foundation is arranged in the fourth via hole, and the second dam foundation is arranged on the flat dam foundation.
  • a plurality of isolation pillars 33 patterns are formed in the binding area 200 and the edge area 300.
  • the plurality of isolation pillars 33 are respectively arranged on the pixel definition layer 22, the first dam foundation, the second dam foundation, and the positions on both sides of the gap 700.
  • the fixed area 200 and the edge area 300 simultaneously form a first supporting dam 410 and a second supporting dam 420, the binding area 200 and the first supporting dam 410 of the edge area 300 are integrated, and the binding area 200 and the second supporting dam 300 of the edge area
  • the supporting dam 420 is an integral structure.
  • An organic light-emitting layer 23 and a cathode 24 are sequentially formed on the substrate forming the aforementioned pattern.
  • the organic light-emitting layer 23 is formed in the pixel opening, a part of the cathode 24 is formed on the organic light-emitting layer 23 of the display area 100, and the other part is formed in the binding area 200 and the edge area 300.
  • the cathode 24 of the binding area 200 wraps the plurality of spacer posts 33 on the pixel definition layer 22, and the cathode 24 of the edge area 300 is connected to the fourth connection electrode 804 through the gap 700 and the fourth via hole. Since the fourth connection electrode 804 is connected to the second power line 220, the cathode 24 and the second power line 220 are connected.
  • the encapsulation layer is formed on the basis of forming the aforementioned pattern.
  • the encapsulation layer includes a first encapsulation layer 25, a second encapsulation layer 26, and a third encapsulation layer 27 that are stacked.
  • the first encapsulating layer 25 is made of inorganic materials, covering the cathode 24 in the display area 100, wrapping a plurality of spacer posts 33, covering the partition groove 500, covering the isolation area 600, and wrapping the first supporting dam 410 and the second supporting dam 410 and the second supporting dam in the binding area 200.
  • the supporting dam 420 wraps a plurality of spacer posts 33 in the edge area 300, covers the gap 700, and wraps the first supporting dam 410 and the second supporting dam 420.
  • the second encapsulation layer 26 is made of organic materials, and is arranged in the display area 100, the area where the spacers 33 of the binding area 200 are located, and the area where the spacers 33 of the edge area 300 are located.
  • the third encapsulation layer 27 is made of inorganic materials to cover the first The encapsulation layer 25 and the second encapsulation layer 26.
  • the structure of the edge region shown in FIG. 23 and FIG. 24 is only an exemplary illustration.
  • the edge structures of the second power cord 220, the first supporting dam 410, and the second supporting dam 420 can be changed according to actual needs.
  • the fifth insulating layer 16 may not be provided in the driving structure layer, the bonding structure layer, and the circuit structure layer.
  • the second power cord 220 may extend to a side away from the display area 100 or.
  • multiple gaps 700 may be provided, which is not specifically limited in the present disclosure.
  • FIG. 25 and FIG. 26 are schematic diagrams of another structure of the first fan-out area of the present disclosure, and FIG. 26 is an enlarged view of area E in FIG. 25.
  • the binding area 200 is located on one side of the display area 100, and the first fan-out area of the binding area 200 is adjacent to the edge 110 of the display area.
  • the first fan-out area includes a first power line 210, a second power line 220, a first isolation dam 410, a second isolation dam 420, and at least one isolation slot 500, the first power line 210 and the high-voltage power line of the display area 100 VDD is connected, the second power line 220 is connected to the low-voltage power line VSS of the edge area 300, the first isolation dam 410 and the second isolation dam 420 extend in a direction parallel to the edge 110 of the display area, and at least one isolation groove 500 extends along the Extending in a direction parallel to the edge 110 of the display area, the distance between the partition groove 500 and the edge 110 of the display area is smaller than the distance between the first isolation dam 410 and the edge 110 of the display area.
  • the first power line 210 includes a first bar 2101 extending in a direction parallel to the edge 110 of the display area and a second bar 2102 extending in a direction away from the display area 100.
  • the second bar 2102 is adjacent to the display area 100.
  • One end of is connected with the first strip block 2101 to form a T-shaped structure.
  • the second power cord 220 includes a third strip-shaped block 2201 extending in a direction parallel to the edge 110 of the display area and a fourth strip-shaped block 2202 extending in a direction away from the display area 100, and the fourth strip-shaped block 2202 is adjacent to the display area 100
  • One end of is connected with the third strip block 2201 to form an angular structure.
  • the edges of the first power cord 210 and the second power cord 220 are provided with a wave structure 230.
  • the wave structure 230 may be disposed on the edges on both sides of the second strip 2102 in the first power cord 210, and may be disposed on the edges on both sides of the second power cord 220.
  • the wave structure 230 may be disposed on the edges of the first power line 210 and the second power line 220 on the side of the isolation groove 500 away from the display area 100, or the wave structure 230 may be disposed on the first isolation dam 410 On the edge of the first power cord 210 and the second power cord 220 on the side far from the display area 100, or the wave structure 230 may be provided on the first power cord 210 and the second power cord 210 on the side of the second isolation dam 420 far away from the display area 100.
  • the wave structure 230 may be provided at the first power cord 210 and the second power cord in the overlapping area of the first power cord 210 and the second power cord 220 and the first isolation dam 410 and the second isolation dam 420 On the edge of line 220.
  • the wavy structure 230 includes a plurality of protrusions arranged at intervals and depressions between the plurality of protrusions to form wavy edges of the first power cord 210 and the second power cord 220.
  • the length of the water vapor transmission path can be increased, hysteresis and alleviated The diffusion of water vapor.
  • the protrusion height T1 between the outer highest point and the inner lowest point in the wave structure 230 is about 30 ⁇ m to about 60 ⁇ m, and the distance T2 between adjacent protrusions is about 20 ⁇ m to about 50 ⁇ m.
  • the wave structure shown in FIG. 25 and FIG. 26 is only an exemplary illustration.
  • the position and shape of the wave structure 230 can be changed according to actual needs.
  • the wave structure 230 may be provided only on the edges on both sides of the power cord in the area between the first isolation dam 410 and the second isolation dam 420.
  • the wave structure 230 may only be disposed on the edges of the power cord on the side of the second isolation dam 420 away from the display area 100.
  • the wave structure 230 may only be arranged on the edge of the second power cord 220 facing the second bar 2102 and the edge of the second bar 2102 facing the second power cord 220.
  • the wave structure 230 may only be arranged on the edge of the second power cord 220 away from the second bar 2102 and the edge of the second bar 2102 away from the second power cord 220.
  • the protrusions and depressions in the wave structure can be composed of multiple arcs, or can be composed of multiple straight lines, or can be composed of multiple arcs and multiple straight lines, which are not specifically limited in the present disclosure.
  • the present disclosure also provides a method for manufacturing a display substrate.
  • the display substrate includes a display area and a binding area on one side of the display area.
  • the preparation method includes:
  • a driving structure layer and a bonding structure layer are formed in the display area and the bonding area respectively; the driving structure layer includes a pixel driving circuit, and the bonding structure layer includes a power line connected to the pixel driving circuit;
  • An organic insulating layer is formed on the driving structure layer and the binding structure layer, and at least one isolation groove is formed on the organic insulating layer on the binding structure layer;
  • a light emitting element and an isolation dam are formed in the display area and the binding area respectively; the light emitting element is connected to the pixel drive circuit, and the distance between the isolation groove and the edge of the display area is smaller than the isolation dam and the edge of the display area the distance;
  • An inorganic encapsulation layer is formed in the binding area, and the inorganic encapsulation layer covers the isolation groove and wraps the isolation dam.
  • forming a light-emitting element and an isolation dam in the display area and the binding area respectively includes: forming a light-emitting element in the display area, and the light-emitting element is connected to the pixel driving circuit; A predetermined area forms a first isolation dam and a second isolation dam, the distance between the first isolation dam and the edge of the display area is less than the distance between the second isolation dam and the edge of the display area, and the distance between the isolation groove and the edge of the display area is less than The distance between the first isolation dam and the edge of the display area.
  • forming a light-emitting element in the display area includes: sequentially forming an anode, a pixel defining layer, an organic light-emitting layer, and a cathode on the organic insulating layer, the anode is connected to the pixel driving circuit, and The pixel definition layer and the cathode extend to the binding area; along a direction away from the display area, the width of the cathode in the binding area is smaller than the distance between the isolation groove and the edge of the display area.
  • the power cord includes a first power cord and a second power cord
  • the isolation slot is provided on the first power cord, or on the second power cord, or on the Between the first power line and the second power line, along a direction away from the display area, the width of the isolation groove is about 20 ⁇ m to about 70 ⁇ m.
  • the display substrate further includes an edge region
  • the preparation method further includes: forming a circuit structure layer on the edge region, forming an organic insulating layer on the circuit structure layer, and the organic insulating layer At least one gap is formed thereon, and the isolation groove of the binding area is connected with the gap of the edge area and is formed by the same process.
  • the binding structure layer of the binding area includes a composite insulating layer disposed on a substrate, and a first power line and a second power line disposed on the composite insulating layer; or, the The binding structure layer of the binding area includes a composite insulating layer provided on a substrate, a first power line and a second power line provided on the composite insulating layer, and a first power line and a second power line provided on the composite insulating layer Or, the binding structure layer of the binding area includes a composite insulating layer disposed on the substrate, a fifth insulating layer disposed on the composite insulating layer, and a fifth insulating layer disposed on the fifth insulating layer.
  • the organic insulating layer disposed on the binding structure layer includes a first flat layer or a second flat layer; the composite insulating layer includes a first insulating layer, a second insulating layer, and a third insulating layer stacked on a substrate. An insulating layer and a fourth insulating layer.
  • the edge of the power cord is provided with a wave structure; the wave structure is provided on the edge of the power cord on the side of the isolation groove away from the display area, or the wave structure is provided at The isolation dam is located on the edge of the power cord on the side away from the display area, or the wave structure is arranged on the edge of the power cord in the overlapping area of the power cord and the isolation dam; the wave structure includes spaced apart A plurality of protrusions, and the protrusion height of the protrusions is about 30 ⁇ m to about 60 ⁇ m.
  • the present disclosure also provides a display device including the display substrate of the foregoing embodiment.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and so on.

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Abstract

一种显示基板及其制备方法、显示装置，显示基板包括显示区域（100）和位于显示区域（100）一侧的绑定区域（200），显示区域（100）包括驱动结构层、设置在驱动结构层上的有机绝缘层（15）以及设置在有机绝缘层（15）上的发光元件，驱动结构层包括像素驱动电路，发光元件与像素驱动电路连接；绑定区域（200）包括绑定结构层、设置在绑定结构层上的有机绝缘层（15）和隔离坝（410,420），以及设置在有机绝缘层（15）和隔离坝（410,420）上的无机封装层（25,27），绑定结构层包括与像素驱动电路连接的电源线（210,220）；绑定区域（200）的有机绝缘层（15）上设置有至少一个隔离槽（500），无机封装层（25,27）覆盖隔离槽（500）和包裹隔离坝（410,420），隔离槽（500）与显示区域边缘（110）的距离小于隔离坝（410,420）与显示区域边缘（110）的距离。

Description

显示基板及其制备方法、显示装置 技术领域
本公开涉及但不限于显示技术领域，尤指一种显示基板及其制备方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度等优点。随着显示技术的不断发展，以OLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括显示区域和位于显示区域一侧的绑定区域，所述显示区域包括驱动结构层、设置在所述驱动结构层上的有机绝缘层、设置在所述有机绝缘层上的发光元件以及设置在所述发光元件上的复合封装层，所述驱动结构层包括像素驱动电路，所述发光元件与所述像素驱动电路连接；所述绑定区域包括绑定结构层、设置在所述绑定结构层上的有机绝缘层和隔离坝以及设置在所述有机绝缘层和隔离坝上的无机封装层，所述绑定结构层包括与所述像素驱动电路连接的电源线；所述绑定区域的有机绝缘层上设置有至少一个隔离槽，所述无机封装层覆盖所述隔离槽和包裹所述隔离坝，所述隔离槽与显示区域边缘的距离小于所述隔离坝与显示区域边缘的距离。
在一些可能的实现方式中，所述隔离坝包括第一隔离坝和第二隔离坝，所述第一隔离坝与显示区域边缘的距离小于所述第二隔离坝与显示区域边缘的距离；所述隔离槽与显示区域边缘的距离小于所述第一隔离坝与显示区域 边缘的距离。
在一些可能的实现方式中，所述发光元件包括阳极、像素定义层、有机发光层和阴极，所述像素定义层和阴极延伸到所述绑定区域；沿着远离所述显示区域的方向，所述绑定区域中阴极边缘与显示区域边缘之间的距离小于所述隔离槽与显示区域边缘的距离。
在一些可能的实现方式中，沿着远离所述显示区域的方向，所述隔离槽的宽度为20μm～70μm。
在一些可能的实现方式中，所述电源线包括第一电源线和第二电源线，所述隔离槽设置在所述第一电源线上，或者设置在所述第二电源线上，或者设置在所述第一电源线与第二电源线之间。
在一些可能的实现方式中，沿着所述显示区域边缘方向，所述隔离槽在基底上的正投影包含所述第一电源线在基底上的正投影。
在一些可能的实现方式中，所述显示基板还包括边缘区域，所述边缘区域包括电路结构层和设置在所述电路结构层上的有机绝缘层，所述有机绝缘层上设置有缝隙，所述绑定区域的隔离槽和边缘区域的缝隙连通。
在一些可能的实现方式中，所述第一电源线包括第一条形块和第二条形块，所述第一条形块沿着所述显示区域边缘方向延伸，所述第二条形块沿着远离所述显示区域的方向延伸，所述第二条形块邻近所述显示区域的一端与所述第一条形块连接，形成T状结构；所述第二电压线位于所述第一条形块远离所述显示区域的一侧，所述隔离坝设置在所述的第二条形块和第二电源线上，所述隔断槽设置在所述第一条形块上。
在一些可能的实现方式中，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层和设置在所述复合绝缘层上的第一电源线和第二电源线；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第一电源线和第二电源线和设置在所述第一电源线和第二电源线上的第五绝缘层。设置在所述绑定结构层上的有机绝缘层包括第一平坦层；所述复合绝缘层包括在基底上叠设的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层。
在一些可能的实现方式中，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第五绝缘层、设置在所述第五绝缘层上的第一平坦层以及设置在所述第一平坦层上的第一电源线和第二电源线；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第一电源线和第二电源线、设置在所述第一电源线和第二电源线上的第五绝缘层以及设置在所述第五绝缘层上的第一平坦层；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第二连接电极和第三连接电极、覆盖所述第二连接电极和第三连接电极的第五绝缘层、设置在所述第五绝缘层上的第一平坦层以及设置在所述第一平坦层上的第一电源线和第二电源线，所述第一电源线通过过孔与第二连接电极连接，所述第二电源线通过过孔与第三连接电极连接。设置在所述绑定结构层上的有机绝缘层包括第二平坦层；所述复合绝缘层包括在基底上叠设的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层。
在一些可能的实现方式中，所述电源线的边缘设置有波浪结构；所述波浪结构设置在所述隔离槽远离所述显示区域一侧的电源线的边缘上，或者，所述波浪结构设置在所述隔离坝远离所述显示区域一侧的电源线的边缘上，或者，所述波浪结构设置在所述电源线与所述隔离坝重叠区域的电源线的边缘上。
在一些可能的实现方式中，所述波浪结构包括间隔设置的多个凸起，所述凸起的突起高度为30μm到60μm。
另一方面，本公开还提供了一种显示基板的制备方法，显示基板包括显示区域和位于显示区域一侧的绑定区域，所述制备方法包括：
在所述显示区域和绑定区域分别形成驱动结构层和绑定结构层；所述驱动结构层包括像素驱动电路，所述绑定结构层包括与所述像素驱动电路连接的电源线；
在所述驱动结构层和绑定结构层上形成有机绝缘层，所述绑定结构层上的有机绝缘层上形成有至少一个隔离槽；
在所述显示区域和绑定区域分别形成发光元件和隔离坝；所述发光元件与所述像素驱动电路连接，所述隔离槽与显示区域边缘的距离小于所述隔离坝与显示区域边缘的距离；
在所述绑定区域形成无机封装层，所述无机封装层覆盖所述隔离槽和包裹所述隔离坝。
在一些可能的实现方式中，在所述显示区域和绑定区域分别形成发光元件和隔离坝包括：在所述显示区域形成发光元件，所述发光元件与所述像素驱动电路连接；在所述绑定区域形成第一隔离坝和第二隔离坝，所述第一隔离坝与显示区域边缘的距离小于所述第二隔离坝与显示区域边缘的距离，所述隔离槽与显示区域边缘的距离小于所述第一隔离坝与显示区域边缘的距离。
在一些可能的实现方式中，在所述显示区域形成发光元件包括：在所述有机绝缘层上依次形成阳极、像素定义层、有机发光层和阴极，所述阳极与所述像素驱动电路连接，所述像素定义层和阴极延伸到所述绑定区域；沿着远离所述显示区域的方向，所述绑定区域中阴极边缘与显示区域边缘之间的距离小于所述隔离槽与显示区域边缘的距离。
在一些可能的实现方式中，所述电源线包括第一电源线和第二电源线，所述隔离槽设置在所述第一电源线上，或者设置在所述第二电源线上，或者设置在所述第一电源线与第二电源线之间，沿着远离所述显示区域的方向，所述隔离槽的宽度为20μm～70μm。
在一些可能的实现方式中，所述显示基板还包括边缘区域，所述制备方法还包括：在所述边缘区域形成电路结构层，在所述电路结构层上形成有机绝缘层，所述有机绝缘层上形成有至少一个缝隙，所述绑定区域的隔离槽和边缘区域的缝隙连通，且通过同一次工艺形成。
在一些可能的实现方式中，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层和设置在所述复合绝缘层上的第一电源线和第二电源线；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第一电源线和第二电源线和设置在所述第一电源线和第二 电源线上的第五绝缘层；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第五绝缘层、设置在所述第五绝缘层上的第一平坦层以及设置在所述第一平坦层上的第一电源线和第二电源线；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第一电源线和第二电源线、设置在所述第一电源线和第二电源线上的第五绝缘层以及设置在所述第五绝缘层上的第一平坦层；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第二连接电极和第三连接电极、覆盖所述第二连接电极和第三连接电极的第五绝缘层、设置在所述第五绝缘层上的第一平坦层以及设置在所述第一平坦层上的第一电源线和第二电源线，所述第一电源线通过过孔与第二连接电极连接，所述第二电源线通过过孔与第三连接电极连接。设置在所述绑定结构层上的有机绝缘层包括第一平坦层或者包括第二平坦层；所述复合绝缘层包括在基底上叠设的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层。
在一些可能的实现方式中，所述电源线的边缘设置有波浪结构；所述波浪结构设置在所述隔离槽远离所述显示区域一侧的电源线的边缘上，或者，所述波浪结构设置在所述隔离坝远离所述显示区域一侧的电源线的边缘上，或者，所述波浪结构设置在所述电源线与隔离坝重叠区域的电源线的边缘上；所述波浪结构包括间隔设置的多个凸起，所述凸起的突起高度为30μm到60μm。
又一方面，本公开还提供了一种显示装置，包括前述的显示基板。
在阅读理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的进一步理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开的技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1为本公开显示基板的结构示意图；
图2为本公开显示基板中绑定区域的结构示意图；
图3为本公开第一扇出区一种结构的示意图；
图4为图3中A-A向的剖视图；
图5为本公开显示基板一种结构的示意图；
图6为本公开形成柔性基底图案后的示意图；
图7为本公开形成驱动结构层和绑定结构层图案后的示意图；
图8为本公开形成隔断槽图案后的示意图；
图9为本公开形成阳极图案后的示意图；
图10为本公开形成像素定义层图案后的示意图；
图11为本公开形成隔垫柱图案后的示意图；
图12为本公开形成有机发光层和阴极图案后的示意图；
图13为本公开形成封装层图案后的示意图；
图14为本公开绑定区域边缘的结构示意图；
图15为本公开显示基板另一种结构的示意图；
图16为本公开显示基板又一种结构的示意图；
图17为本公开显示基板又一种结构的示意图；
图18为本公开显示基板又一种结构的示意图；
图19为本公开显示基板又一种结构的示意图；
图20为本公开显示基板又一种结构的示意图；
图21为本公开显示基板又一种结构的示意图；
图22为本公开第一扇出区的另一种结构示意图；
图23为本公开2SD结构显示区域和边缘区域的剖面结构示意图；
图24为本公开1SD结构显示区域和边缘区域的剖面结构示意图；
图25为本公开第一扇出区的另一种结构示意图；
图26为图25中E区域的放大图。
附图标记说明:
1—玻璃载板；           10—柔性基底；          11—第一绝缘层；
12—第二绝缘层；        13—第三绝缘层；        14—第四绝缘层；
15—第一平坦层；        16—第五绝缘层；        17—第二平坦层；
21—阳极；              22—像素定义层；        23—有机发光层；
24—阴极；              25—第一封装层；        26—第二封装层；
27—第三封装层；        30—平坦坝基；          31—第一坝基；
32—第二第二；          33—隔垫柱；            100—显示区域；
101—第一晶体管；       102—第一存储电容；     103—第二晶体管；
104—第三晶体管；       105—第二存储电容；     106—第三存储电容；
110—显示区域边缘；     200—绑定区域；         201—第一扇出区；
202—弯折区；           203—第二扇出区；       204—防静电区；
205—驱动芯片区；       206—绑定电极区；       210—第一电源线；
220—第二电源线；       230—波浪结构；         300—边缘区域；
410—第一隔离坝；       420—第二隔离坝；       500—隔离槽；
600—隔离区；           700—缝隙；             801—第一连接电极；
802—第二连接电极；     803—第三连接电极；     804—第四连接电极；
2101—第一条形块；      2102—第二条形块；      2201—第三条形块；
2202—第四条形块。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意 组合。
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线形成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
一种柔性显示装置包括设置在柔性基底上的驱动电路层、设置在驱动电路层上的发光器件以及设置在发光器件上的封装层，封装层用于保护发光器件。研究表明，封装层的封装效果对柔性显示装置的显示性能影响很大。如果封装层出现封装失效，如封装层产生缝隙或发生断裂，大气中的水汽会沿着缝隙进入发光器件，使发光器件中的有机材料氧化失效，形成无法发光的失效区域。随着水汽沿着缝隙不断入侵发光器件，失效区域逐渐扩大，导致柔性显示装置出现显示不良，称之为不断扩大的暗点(Growing Dark Spot，简称GDS)。
本公开提供了一种显示基板，包括显示区域和位于显示区域一侧的绑定区域，所述显示区域包括驱动结构层、设置在所述驱动结构层上的有机绝缘层、设置在所述有机绝缘层上的发光元件以及设置在所述发光元件上的复合封装层，所述驱动结构层包括像素驱动电路，所述发光元件与所述像素驱动电路连接；所述绑定区域包括绑定结构层、设置在所述绑定结构层上的有机绝缘层和隔离坝以及设置在所述有机绝缘层和隔离坝上的无机封装层，所述绑定结构层包括与所述像素驱动电路连接的电源线；所述绑定区域的有机绝缘层上设置有至少一个隔离槽，所述无机封装层覆盖所述隔离槽和包裹所述 隔离坝，所述隔离槽与显示区域边缘的距离小于所述隔离坝与显示区域边缘的距离。
在示例性实施方式中，所述隔离坝包括第一隔离坝和第二隔离坝，所述第一隔离坝与显示区域边缘的距离小于所述第二隔离坝与显示区域边缘的距离；所述隔离槽与显示区域边缘的距离小于所述第一隔离坝与显示区域边缘的距离。
在示例性实施方式中，所述发光元件包括阳极、像素定义层、有机发光层和阴极，所述像素定义层和阴极延伸到所述绑定区域；沿着远离所述显示区域的方向，阴极边缘与显示区域边缘之间的距离小于所述隔离槽与显示区域边缘的距离。
在示例性实施方式中，所述电源线包括第一电源线和第二电源线，所述隔离槽设置在所述第一电源线上，或者设置在所述第二电源线上，或者设置在所述第一电源线与第二电源线之间。沿着远离所述显示区域的方向，所述隔离槽的宽度为20μm～70μm。沿着所述显示区域边缘方向，所述隔离槽在基底上的正投影包含所述第一电源线在基底上的正投影。
在示例性实施方式中，所述显示基板还包括边缘区域，所述边缘区域包括电路结构层和设置在所述电路结构层上的有机绝缘层，所述有机绝缘层上设置有缝隙，所述绑定区域的隔离槽和边缘区域的缝隙连通，且通过同一次工艺形成。
在示例性实施方式中，所述第一电源线包括第一条形块和第二条形块，所述第一条形块沿着所述显示区域边缘方向延伸，所述第二条形块沿着远离所述显示区域的方向延伸，所述第二条形块邻近所述显示区域的一端与所述第一条形块连接，形成T状结构；所述第二电压线位于所述第一条形块远离所述显示区域的一侧，所述隔离坝设置在所述的第二条形块和第二电源线上，所述隔断槽设置在所述第一条形块上。
在示例性实施方式中，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层和设置在所述复合绝缘层上的第一电源线和第二电源线；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复 合绝缘层上的第一电源线和第二电源线和设置在所述第一电源线和第二电源线上的第五绝缘层。设置在所述绑定结构层上的有机绝缘层包括第一平坦层；所述复合绝缘层包括在基底上叠设的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层。
在示例性实施方式中，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第五绝缘层、设置在所述第五绝缘层上的第一平坦层以及设置在所述第一平坦层上的第一电源线和第二电源线；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第一电源线和第二电源线、设置在所述第一电源线和第二电源线上的第五绝缘层以及设置在所述第五绝缘层上的第一平坦层；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第二连接电极和第三连接电极、覆盖所述第二连接电极和第三连接电极的第五绝缘层、设置在所述第五绝缘层上的第一平坦层以及设置在所述第一平坦层上的第一电源线和第二电源线，所述第一电源线通过过孔与第二连接电极连接，所述第二电源线通过过孔与第三连接电极连接。设置在所述绑定结构层上的有机绝缘层包括第二平坦层；所述复合绝缘层包括在基底上叠设的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层。
在示例性实施方式中，所述电源线的边缘设置有波浪结构；所述波浪结构设置在所述隔离槽远离所述显示区域一侧的电源线的边缘上，或者，所述波浪结构设置在所述隔离坝远离所述显示区域一侧的电源线的边缘上，或者，所述波浪结构设置在所述电源线与所述隔离坝重叠区域的电源线的边缘上。
图1为本公开显示基板的结构示意图。如图1所示，本公开显示基板包括显示区域100和位于显示区域100周边的非显示区域，非显示区域包括位于显示区域100一侧的绑定区域200和位于显示区域100其它侧的边缘区域300，显示区域100至少包括规则排列的多个显示单元，绑定区域200至少包括隔离坝和将多个显示单元的信号线连接至外部驱动装置的绑定电路，边缘区域300至少包括隔离坝和向多个显示单元传输电压信号的电源线，绑定区域200和边缘区域300的隔离坝形成环绕显示区域100的环形结构。
图2为本公开显示基板中绑定区域的结构示意图。如图2所示，在平行于显示基板的平面内，本公开绑定区域200位于显示区域100的一侧，绑定区域200包括沿着远离显示区域100的方向依次设置的第一扇出区201、弯折区202、第二扇出区203、防静电区204、驱动芯片区205和绑定电极区206。第一扇出区201包括数据扇出线、第一电源线和第二电源线，数据扇出线位于第一扇出区201的中部，包括多条数据连接线，多条数据连接线被配置为以扇出(Fanout)走线方式连接显示区域100的数据线(Data Line)，第一电源线位于数据扇出线的两侧，被配置为连接显示区域100的高电压电源线(VDD)，第二电源线也位于数据扇出线的两侧，被配置为连接边缘区域300的低电压电源线(VSS)。弯折区202包括设置有凹槽的复合绝缘层，被配置为使绑定区域200弯折到显示区域100的背面。第二扇出区203包括扇出走线方式引出的多条数据连接线。防静电区204包括防静电电路，被配置为通过消除静电防止显示基板的静电损伤。驱动芯片区205包括集成电路(Integrated Circuit，简称IC)，被配置为与多条数据连接线连接。绑定电极区206包括多个绑定焊盘(Bonding Pad)，被配置为与外部的柔性线路板(Flexible Printed Circuit，简称FPC)绑定连接。
图3为本公开第一扇出区一种结构的示意图，为图2中C区域的放大图，图4为图3中A-A向的剖视图。如图3所示，在平行于显示基板的平面内，绑定区域200位于显示区域100的一侧，绑定区域200的第一扇出区邻近显示区域边缘110。第一扇出区包括第一电源线210、第二电源线220和数据扇出线(未示出)，第一电源线210与显示区域100的高电压电源线连接，被配置为向显示区域100的多个显示单元传输高电压信号，第二电源线220与边缘区域300的低电压电源线连接，被配置为向显示区域100的多个显示单元传输低电压信号。第一扇出区还包括第一隔离坝410、第二隔离坝420和隔断槽500，被配置为阻隔水汽进入显示区域100。第一隔离坝410和第二隔离坝420设置在绑定区域200和边缘区域300，在绑定区域200和边缘区域300形成环绕显示区域100的环形结构，第一隔离坝410和第二隔离坝420被配置为阻隔从显示区域100外围进入显示区域100的水汽。在绑定区域200，第一隔离坝410和第二隔离坝420沿着平行于显示区域边缘110的方向延伸，第一隔离坝410与显示区域边缘110的距离小于第二隔离坝420与显 示区域边缘110的距离，即第二隔离坝420设置在第一隔离坝410远离显示区域100的一侧。隔断槽500设置在绑定区域200，被配置为阻隔沿着第一电源线210的边缘和第二电源线220的边缘进入显示区域100的水汽。隔断槽500沿着平行于显示区域边缘110的方向延伸，隔断槽500与显示区域边缘110的距离小于第一隔离坝410与显示区域边缘110的距离，即隔断槽500设置在显示区域边缘110与第一隔离坝410之间。
如图4所示，在垂直于显示基板的平面内，绑定区域200的第一扇出区包括设置在基底10上的复合绝缘层，设置在复合绝缘层上的第一电源线210和第二电源线220，设置在第一电源线210和第二电源线220上的第一平坦层15、第一隔离坝410和第二隔离坝420，设置在第一平坦层15上的像素定义层22，设置在像素定义层22上的阴极24，以及覆盖上述结构的第一封装层25。第一隔离坝410和第二隔离坝420设置在第二电源线220上，且被第一封装层25包裹，第一隔离坝410由第一坝基和隔垫柱组成，第二隔离坝420由平坦坝基、第二坝基和隔垫柱组成。第一隔离坝410和第二隔离坝420附近区域的第一平坦层15被去除，暴露出第二电源线220，封装层25覆盖该区域暴露出的第二电源线220。为了阻隔从第一电源线210边缘和第二电源线220边缘入侵的水汽，第一电源线210上的第一平坦层15设置有隔断槽500，隔断槽500中的第一平坦层15被去除，暴露出第一电源线210的表面，使封装层25覆盖隔断槽500内暴露出的第一电源线210的表面。隔断槽500设置在阴极24远离显示区域的边缘与第一隔离坝410之间，以避免隔断槽500暴露的第一电源线210与阴极24接触。在一些实施例中，隔断槽500的位置可以根据绑定区域的尺寸、第一电源线210的线宽和第二电源线220的线宽进行设计，在保证隔断槽500远离阴极24的前提下，隔断槽500可以设置在第一平坦层15和像素定义层22上，本公开在此不做具体的限定。
如图2和图3所示，第一电源线210包括第一条形块2101和第二条形块2102，第一条形块2101沿着平行于显示区域边缘110的方向延伸，第二条形块2102沿着远离显示区域100的方向延伸，第二条形块2102邻近显示区域100的一端与第一条形块2101连接，形成T状结构。第二电源线220包括第三条形块2201和第四条形块2202，第三条形块2201沿着平行于显示区域边 缘110的方向延伸，第四条形块2202沿着远离显示区域100的方向延伸，第四条形块2202邻近显示区域100的一端与第三条形块2201连接，形成角状结构。第二电源线220位于第一条形块2101远离显示区域100的一侧以及位于第二条形块2102远离数据扇出线的一侧，第一隔离坝410和第二隔离坝420设置在第一电源线210的第二条形块2102和第二电源线220的第三条形块2201上，隔断槽500设置在第一电源线210的第一条形块2101上。
图5为本公开显示基板一种结构的示意图，为图3中B-B向的剖视图，示意了单源漏金属层(1SD)结构显示区域和绑定区域的剖面结构。在平行于显示基板的平面方向，显示基板包括显示区域100和绑定区域200，绑定区域200位于显示区域100的一侧。在垂直于显示基板的平面方向，显示区域100包括柔性基底10，设置在柔性基底10上的驱动结构层，设置在驱动结构层上的发光元件以及覆盖发光元件的复合封装层。绑定区域200包括柔性基底10，设置在柔性基底10上的绑定结构层，设置在绑定结构层上的隔离槽500和隔离区600，隔离区600内设置有第一隔离坝410和第二隔离坝420，以及覆盖隔离槽500、第一隔离坝410、第二隔离坝420和隔离区600的无机封装层。
在示例性实施方式中，显示区域100的驱动结构层包括形成像素驱动电路的多个晶体管和存储电容，图5中以一个第一晶体管101和一个第一存储电容102为例进行示意，第一晶体管101可以是驱动晶体管。显示区域100的驱动结构层包括：设置在柔性基底10上的第一绝缘层11，设置在第一绝缘层11上的有源层，覆盖有源层的第二绝缘层12，设置在第二绝缘层12上的第一栅金属层，覆盖第一栅金属层的第三绝缘层13，设置在第三绝缘层13上的第二栅金属层，覆盖第二栅金属层的第四绝缘层14，设置在第四绝缘层14上的源漏金属层，有源层至少包括第一有源层，第一栅金属层至少包括第一栅电极和第一电容电极，第二栅金属层至少包括第二电容电极，源漏金属层至少包括第一源电极和第一漏电极，第一有源层、第一栅电极、第一源电极和第一漏电极组成第一晶体管101，第一电容电极和第二电容电极组成第一存储电容102，源漏金属层也称之为第一源漏金属层(SD1)。显示区域100的驱动结构层上设置有第一平坦层15，发光元件设置在第一平坦层 15上，发光元件包括阳极21、像素定义层22、有机发光层23和阴极24，阳极21通过第一平坦层15上开设的第一过孔与第一晶体管101的第一漏电极连接。复合封装层包括叠设的第一封装层25、第二封装层26和第三封装层27，有机材料的第二封装层26设置在无机材料的第一封装层25和第三封装层27之间。
绑定区域200的绑定结构层包括由多个无机绝缘层组成的复合绝缘层和设置在复合绝缘层上的第一电源线210和第二电源线220，复合绝缘层包括在柔性基底10上叠设的第一绝缘层11、第二绝缘层12、第三绝缘层13和第四绝缘层14，上述绝缘层均为无机绝缘层，第一电源线210和第二电源线220设置在第四绝缘层14上，与显示区域的第一源电极和第一漏电极同层设置，且通过同一次构图工艺形成。绑定区域200的绑定结构层上设置有第一平坦层15，第一平坦层15上设置有隔断槽500和隔离区600，隔断槽500设置在第一电源线210所在区域，隔断槽500暴露出第一电源线210的表面，隔离区600设置在第二电源线220远离显示区域100的一侧，隔离区600内设置有第一隔离坝410和第二隔离坝420，第一隔离坝410和第二隔离坝420设置在第二电源线220上，除了第一隔离坝410和第二隔离坝420所在位置，隔离区600的其它位置暴露出第二电源线220和复合绝缘层的表面。无机封装层包括叠设的第一封装层25和第三封装层27，无机材料的第一封装层25和第三封装层27覆盖隔断槽500和隔离区600，且包裹第一隔离坝410和第二隔离坝420。此外，邻近显示区域100的第一平坦层15上设置有像素定义层22，像素定义层22上设置有多个间隔设置的隔垫柱33，阴极24包裹多个隔垫柱33。
在示例性实施方式中，隔离槽500可以是一个或多个，隔断槽500的宽度为约20μm到约50μm，隔离槽500与显示区域边缘110的距离小于第一隔离坝410与显示区域边缘110的距离，隔离槽500与显示区域边缘110的距离大于阴极24边缘与显示区域边缘110的距离。
下面通过显示基板的制备过程的示例说明本公开显示基板的结构。本公开所说的“构图工艺”包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀和剥离光刻胶等处理。沉积可以采用选自溅射、蒸镀和化学气相沉积中的任意 一种或多种，涂覆可以采用选自喷涂和旋涂中的任意一种或多种，刻蚀可以采用选自干刻和湿刻中的任意一种或多种。“薄膜”是指将某一种材料在基底上利用沉积或涂覆工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需构图工艺，则该“薄膜”还可以称为“层”。当在整个制作过程当中该“薄膜”还需构图工艺，则在构图工艺前称为“薄膜”，构图工艺后称为“层”。经过构图工艺后的“层”中包含至少一个“图案”。本公开中所说的“A和B同层设置”是指，A和B通过同一次构图工艺同时形成。“A的正投影包含B的正投影”是指，B的正投影落入A的正投影范围内，或者A的正投影覆盖B的正投影。
(1)在玻璃载板1上制备柔性基底10。本公开中，柔性基底10包括在玻璃载板1上叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称之为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。在一示例性实施方式中，以叠层结构PI1/Barrier1/a-si/PI2/Barrier2为例，其制备过程可以包括：先在玻璃载板1上涂布一层聚酰亚胺，固化成膜后形成第一柔性(PI1)层；随后在第一柔性层上沉积一层阻挡薄膜，形成覆盖第一柔性层的第一阻挡(Barrier1)层；然后在第一阻挡层上沉积一层非晶硅薄膜，形成覆盖第一阻挡层的非晶硅(a-si)层；然后在非晶硅层上再涂布一层聚酰亚胺，固化成膜后形成第二柔性(PI2)层；然后在第二柔性层上沉积一层阻挡薄膜，形成覆盖第二柔性层的第二阻挡(Barrier2)层，完成柔性基底10的制备，如图6所示。本次工艺后，显示区域100和绑定区域200均包括柔性基底10。
(2)在柔性基底10上制备驱动结构层和绑定结构层图案。显示区域100的驱动结构层包括构成像素驱动电路的第一晶体管101和第一存储电容102，绑定区域200的绑定结构层包括第一电源线210和第二电源线220。在示例性实施方式中，驱动结构层的制备过程可以包括：
在柔性基底10上依次沉积第一绝缘薄膜和有源层薄膜，通过构图工艺 对有源层薄膜进行构图，形成覆盖整个柔性基底10的第一绝缘层11，以及设置在第一绝缘层11上的有源层图案，有源层图案至少包括第一有源层。本次构图工艺后，绑定区域200包括设置在柔性基底10上的第一绝缘层11。
随后，依次沉积第二绝缘薄膜和第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成覆盖有源层图案的第二绝缘层12，以及设置在第二绝缘层12上的第一栅金属层图案，第一栅金属层图案至少包括第一栅电极和第一电容电极。本次构图工艺后，绑定区域200包括在柔性基底10叠设的第一绝缘层11和第二绝缘层12。
随后，依次沉积第三绝缘薄膜和第二金属薄膜，通过构图工艺对第二金属薄膜进行构图，形成覆盖第一栅金属层的第三绝缘层13，以及设置在第三绝缘层13上的第二栅金属层图案，第二栅金属层图案至少包括第二电容电极，第二电容电极的位置与第一电容电极的位置相对应。本次构图工艺后，绑定区域200包括在柔性基底10叠设的第一绝缘层11、第二绝缘层12和第三绝缘层13。
随后，沉积第四绝缘薄膜，通过构图工艺对第四绝缘薄膜进行构图，形成覆盖第二栅金属层的第四绝缘层14图案，第四绝缘层14上开设有至少两个第一过孔，两个第一过孔内的第四绝缘层14、第三绝缘层13和第二绝缘层12被刻蚀掉，暴露出第一有源层的表面。本次构图工艺后，绑定区域200包括在柔性基底10上叠设的第一绝缘层11、第二绝缘层12、第三绝缘层13和第四绝缘层14。
随后，沉积第三金属薄膜，通过构图工艺对第三金属薄膜进行构图，在第四绝缘层14上形成源漏金属层图案，源漏金属层至少包括位于显示区域100的第一源电极和第一漏电极、以及位于绑定区域200的第一电源线210和第二电源线220，第一源电极和第一漏电极分别通过第一过孔与第一有源层连接。
至此，在柔性基底10上制备完成显示区域100的驱动结构层和绑定区域200的绑定结构层图案，如图7所示。显示区域100的驱动结构层中，第一有源层、第一栅电极、第一源电极和第一漏电极组成第一晶体管101，第一 电容电极和第二电容电极组成第一存储电容102。绑定区域200的绑定结构层包括设置在柔性基底10上的复合绝缘层以及设置在复合绝缘层上的第一电源线210和第二电源线220，复合绝缘层包括叠设的第一绝缘层11、第二绝缘层12、第三绝缘层13和第四绝缘层14。在示例性实施方式中，第一电源线210与第二电源线220之间的间距为约50μm到约100μm。
在示例性实施方式中，第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或更多种，可以是单层、多层或复合层。第一绝缘层称之为缓冲(Buffer)层，用于提高基底的抗水氧能力，第二绝缘层和第三绝缘层称之为栅绝缘(GI)层，第四绝缘层称之为层间绝缘(ILD)层。第一金属薄膜、第二金属薄膜和第三金属薄膜可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)、钛(Ti)和钼(Mo)中的任意一种或更多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Ti/Al/Ti等。有源层薄膜可以采用非晶态氧化铟镓锌材料(a-IGZO)、氮氧化锌(ZnON)、氧化铟锌锡(IZTO)、非晶硅(a-Si)、多晶硅(p-Si)、六噻吩、聚噻吩等各种材料，即本公开适用于基于氧化物Oxide技术、硅技术以及有机物技术制造的晶体管。
(3)在形成前述图案的柔性基底上涂覆有机材料的平坦薄膜，形成覆盖整个柔性基底10的第一平坦(PLN)层15，通过掩膜、曝光、显影工艺，在第一平坦层15上形成第二过孔K2、隔断槽500、隔离区600和平坦坝基30图案，第一平坦层15作为本公开的有机绝缘层。第二过孔K2形成在显示区域100，第二过孔内的第一平坦层15被显影掉，暴露出第一晶体管101的第一漏电极的表面。隔断槽500形成在绑定区域200中第一电源线210所在位置，隔断槽500内的第一平坦层15被显影掉，暴露出第一电源线210的表面。隔离区600形成在绑定区域200中第二电源线220远离显示区域100的一侧，隔离区600内的第二电源线220上设置有平坦坝基30，除了平坦坝基30，隔离区600其它位置的第一平坦层15被显影掉，暴露出第二电源线220的表面和第四绝缘层14的表面，如图8所示。在示例性实施方式中，绑定区域200的隔断槽500是用于阻隔沿着第一电源线210的边缘和第二电源线220 的边缘进入显示区域100的水汽，隔离区600是用于在第二电源线220上形成两个隔离坝，平坦坝基30是第二隔离坝的坝基。在一些实施例中，隔断槽500的宽度为约20μm到约50μm，可以是一个，或者是二个，或者是三个以上，平坦坝基30的宽度为约20μm到约60μm。
在一些实施例中，隔断槽500邻近隔离区600一侧的边缘与隔离区600邻近隔断槽500一侧的边缘之间的距离L0为约40μm到约100μm，以减小隔断槽500与隔离区600之间区域第一平坦层15脱落的风险。在示例性实施方式中，在平行于显示区域边缘的方向，隔断槽500的长度等于隔断槽500所在位置第一电源线210的长度，即隔断槽500在柔性基底10上正投影的长度等于第一电源线210在柔性基底10上正投影的长度，隔断槽500中暴露出第一电源线210的表面。在一些实施例中，在平行于显示区域边缘的方向，隔断槽500的长度可以大于隔断槽500所在位置第一电源线210的长度，隔断槽500在柔性基底10上正投影的长度包含第一电源线210在柔性基底10上正投影的长度，在第一电源线210所在区域，隔断槽500中暴露出第一电源线210的表面，在第一电源线210以外区域，隔断槽500中暴露出复合绝缘层的表面。对于暴露出复合绝缘层表面的隔断槽500，隔断槽500可以是连续的，或者可以是间隔设置的。
本次构图工艺后，绑定区域200包括设置在柔性基底10上的复合绝缘层，设置在复合绝缘层上的第一电源线210和第二电源线220，设置在第一电源线210和第二电源线220上的第一平坦层15，第一平坦层15形成有隔断槽500和隔离区600，隔离区600内形成有平坦坝基30。本公开中，“长度”是指沿着显示区域边缘方向的特征尺寸，“宽度”是指沿着远离显示区域方向的特征尺寸。
(4)在形成前述图案的柔性基底上沉积透明导电薄膜，通过构图工艺对透明导电薄膜进行构图，形成阳极21图案，阳极21形成在显示区域100的第一平坦层15上，通过第二过孔K2与第一晶体管101的第一漏电极连接，如图9所示。
本次构图工艺后，绑定区域200的膜层结构没有变化。在示例性实施方式中，透明导电薄膜可以采用氧化铟锡ITO或氧化铟锌IZO。
(5)在形成前述图案的基底上涂覆像素定义薄膜，通过掩膜、曝光、显影工艺，形成像素定义(PDL)层22、第一坝基31和第二坝基32图案，像素定义层22形成在显示区域100以及绑定区域200邻近显示区域100的部分区域，显示区域100的像素定义层22上开设有像素开口，像素开口内的像素定义层22被显影掉，暴露出阳极21的表面。第一坝基31和第二坝基32形成在绑定区域200的隔离区600，第一坝基31形成在隔离区600内的第二电源线220上，第二坝基32形成在平坦坝基30上，第一坝基31与显示区域100的距离小于第二坝基32与显示区域100的距离，如图10所示。本公开中，第一坝基31是用于形成第一隔离坝，平坦坝基30和第二坝基32是用于形成第二隔离坝。在示例性实施方式中，像素定义层可以采用聚酰亚胺、亚克力或聚对苯二甲酸乙二醇酯等。
(6)在形成前述图案的柔性基底上涂覆有机材料薄膜，通过掩膜、曝光、显影工艺，形成多个隔垫柱(PS)33图案，多个隔垫柱33分别形成在绑定区域200的像素定义层22、第一坝基31和第二坝基32上，如图11所示。在示例性实施方式中，在垂直于柔性基底10的方向上，平坦坝基30、第一坝基31、第二坝基32和隔垫柱33的横截面形状为梯形，第一坝基31和其上的隔垫柱33组成第一支撑坝410，平坦坝基30、第二坝基32和其上的隔垫柱33组成第二支撑坝420，第一支撑坝410的上端面与柔性基底10的距离小于第二支撑坝420的上端面与柔性基底10的距离，第一支撑坝410与显示区域100的距离小于第二支撑坝420与显示区域100的距离。在示例性实施方式中，第一支撑坝410和第二支撑坝420在柔性基底10上正投影的宽度为约20μm到约60μm，第一支撑坝410与第二支撑坝420之间的间距为约20μm到约60μm。在一些实施例中，第一支撑坝410和第二支撑坝420在柔性基底10上正投影的宽度为约40μm，第一支撑坝410与第二支撑坝420之间的间距为约40μm。
(7)在形成前述图案的柔性基底上依次形成有机发光层23和阴极24，如图12所示。有机发光层23包括叠设的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层，形成在显示区域100的像素开口内，实现有机发光层23与阳极21连接，阴极24形成在像素定义层22上，与有机发光 层23连接，并包裹像素定义层22上的多个隔垫柱33。本次构图工艺中，由于隔断槽500处暴露出第一电源线210，因此阴极24在绑定区域200内的宽度(阴极24边缘与显示区域边缘之间的距离)L1小于隔断槽500与显示区域100之间的距离L2，以避免隔断槽500内的第一电源线210与阴极24搭接。在一些实施例中，阴极24边缘与隔断槽500之间的距离(L2-L1)可以设置为约50μm到约150μm，可以采用开放式掩膜板(Open Mask，简称OPM)通过设置阴极开口边缘与隔离槽之间的距离大于阴极遮罩(Shadow)的距离来实现。在示例性实施方式中，阴极可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或更多种，或采用上述金属中任意一种或多种制成的合金。
(8)在形成前述图案的基础上形成封装层，封装层包括叠设的第一封装层25、第二封装层26和第三封装层27，如图13所示。第一封装层25采用无机材料，在显示区域100覆盖阴极24，在绑定区域200分别包裹多个隔垫柱33、覆盖隔断槽500、覆盖隔离区600以及包裹隔离区600中的第一支撑坝410和第二支撑坝420。第二封装层26采用有机材料，设置在显示区域100和绑定区域200的隔垫柱33所在区域。第三封装层27采用无机材料，覆盖第一封装层25和第二封装层26。本公开中，由于隔断槽500形成有暴露出第一电源线210的表面，因而无机材料的第一封装层25和第三封装层27直接覆盖在第一电源线210上，在有机材料的第一平坦层15内形成无机材料的隔断结构，阻隔了水汽沿着有机材料层的传播路径。由于隔离区600形成有暴露出第二电源线220和第四绝缘层14的表面，因而无机材料的第一封装层25和第三封装层27直接覆盖在第二电源线220和第四绝缘层14上，可以保证外界水汽无法进入显示区域100，提高了封装效果和工艺质量。
图14为本公开绑定区域边缘的结构示意图，为图13中D区域的放大图。如图14所示，为了在绑定区域200形成第一隔离坝和第二隔离坝，在形成第一平坦层的工艺中，将第一隔离坝和第二隔离坝所在区域及其附近区域(隔离区600)的第一平坦层去除，因而在形成第一平坦层工艺后，该区域的第一电源线210和第二电源线220的边缘是裸露的。对于采用Ti/Al/Ti多层复合结构的第一电源线210和第二电源线220，在后续刻蚀阳极的工艺 中，第一电源线210和第二电源线220的边缘会被阳极刻蚀液侵蚀。由于刻蚀液刻蚀Al的速率大于刻蚀Ti的速率，因而被侵蚀的第一电源线210和第二电源线220的边缘会形成侧面凹坑，Al层上方的Ti层凸出Al层一段距离，形成一个“屋檐”结构。在后续采用化学气相沉积(CVD)形成第一封装层25和第三封装层27工艺中，该“屋檐”结构遮挡了气相沉积的粒子，使得侧面凹坑内无法被封装材料填充，形成了空洞501。这样，当第一封装层25和第三封装层27出现裂纹502时，外界的水汽可以通过裂纹502进入空洞501，造成水汽在第一电源线210的边缘和第二电源线220的边缘流通。虽然第一电源线210和第二电源线220边缘的空洞501仅存在于第一隔离坝和第二隔离坝所在区域及其附近区域，其它区域的第一电源线210和第二电源线220边缘被第一平坦层覆盖，不会形成这种空洞，但由于有机材料的第一平坦层自身是传导水汽的，因而水汽可由空洞501传播转为从第一平坦层传播，直至扩散到显示区域，造成显示区域因水氧侵蚀出现暗点不良。
对于单源漏金属层(1SD)结构的显示基板，本公开通过在第一平坦层上设置隔断槽，隔断了穿过隔离坝的电源线边缘出现的水汽入侵路径。当水汽沿着电源线边缘流通到第一平坦层后，水汽会在第一平坦层内向显示区域传导扩散，由于第一平坦层上设置了隔断槽，水汽受到隔断槽的阻挡，水汽需要绕过隔断槽才能进入显示区域，入侵路径被大大延长，降低了出现GDS的风险，避免了显示基板出现显示不良，提高了显示品质。本公开的制备工艺利用现有成熟的制备设备即可实现，对现有工艺改进较小，可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。由于电源线穿过隔离坝的结构和工艺路线比较普遍，电源线边缘出现水汽入侵路径的可能性很大，因而本公开的解决方案具有广泛的应用前景。
如图3～图14所示，本公开所提供的显示基板包括：
柔性基底10；
设置在柔性基底10上的第一绝缘层11；
设置在第一绝缘层11上的第一有源层；
覆盖第一有源层的第二绝缘层12；
设置在第二绝缘层12上的第一栅金属层，第一栅金属层设置在显示区域100，第一栅金属层至少包括第一栅电极和第一电容电极；
覆盖第一栅金属层的第三绝缘层13；
设置在第三绝缘层13上的第二栅金属层，第二栅金属层设置在显示区域100，第二栅金属层至少包括第二电容电极；
覆盖第二栅金属层的第四绝缘层14，显示区域100的第四绝缘层14上开设有第一过孔，第一过孔暴露出第一有源层；
设置在第四绝缘层14上的源漏金属层，源漏金属层至少包括显示区域100的第一源电极和第一漏电极，以及绑定区域200的第一电源线210和第二电源线220，第一源电极和第一漏电极分别通过第一过孔与第一有源层连接；
覆盖前述结构的第一平坦层15；在显示区域100，第一平坦层15上设置有暴露出第一漏电极的第二过孔K2；在绑定区域200，第一平坦层15上设置有隔断槽500和隔离区600，隔断槽500暴露出第一电源线210的表面，隔离区600内的第二电源线220上设置有平坦坝基30，平坦坝基30以外位置暴露出第二电源线220和第四绝缘层14；
形成在显示区域100的阳极21，阳极21通过第二过孔与第一漏电极连接；
像素定义层22、第一坝基31和第二坝基32，像素定义层22上设置有像素开口，像素开口暴露出阳极21，第一坝基31设置在隔离区600内的第二电源线220上，第二坝基32设置在平坦坝基30上；
设置在像素定义层22、第一坝基31和第二坝基32上的多个隔垫柱33；
与阳极21连接的有机发光层23；
与有机发光层23连接的阴极24，绑定区域200内阴极边缘与显示区域100之间的距离小于隔断槽500与显示区域100之间的距离；
覆盖上述结构的封装层。
本公开显示基板的结构及其制备过程仅仅是一种示例性说明。在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺。例如，在平行于显示基板的平面内，隔断槽可以是弧线形或折线形。又如，在垂直于显示基板的平面内，隔断槽的剖面形状可以是矩形或梯形，本公开在此不做具体的限定。
图15为本公开显示基板另一种结构的示意图，为图3中B-B向的剖视图。如图15所示，显示基板包括显示区域100和绑定区域200，绑定区域200位于显示区域100的一侧，显示区域100包括柔性基底10，设置在柔性基底10上的驱动结构层，设置在驱动结构层上的发光元件以及覆盖发光元件的复合封装层。绑定区域200包括柔性基底10，设置在柔性基底10上的绑定结构层，设置在绑定结构层上的隔离槽500和隔离区600，隔离区600设置有第一隔离坝410和第二隔离坝420，以及覆盖隔离槽500、第一隔离坝410、第二隔离坝420和隔离区600的无机封装层。在示例性实施方式中，显示区域100和绑定区域200的绑定结构层的结构与前述实施例中描述的相应结构类似，绑定区域200的绑定结构层上设置有第一平坦层15，第一平坦层15上设置有隔断槽500和隔离区600，隔断槽500设置在第二电源线220所在区域，隔断槽500暴露出第二电源线220的表面，隔离区600的第二电源线220上设置有第一隔离坝410和第二隔离坝420，第一隔离坝410和第二隔离坝420以外区域暴露出第二电源线220和复合绝缘层的表面。无机封装层包括叠设的第一封装层25和第三封装层27，无机材料的第一封装层25和第三封装层27覆盖隔断槽500和隔离区600，且包裹第一隔离坝410和第二隔离坝420。在一些实施例中，隔离槽500邻近第一隔离坝410一侧的边缘与第一隔离坝410邻近隔断槽500一侧的边缘之间的距离为约40μm到约60μm。
图16为本公开显示基板又一种结构的示意图，为图3中B-B向的剖视图。如图16所示，显示基板包括显示区域100和绑定区域200，绑定区域200位于显示区域100的一侧，显示区域100包括柔性基底10，设置在柔性基底10上的驱动结构层，设置在驱动结构层上的发光元件以及覆盖发光元件的复合封装层。绑定区域200包括柔性基底10，设置在柔性基底10上的 绑定结构层，设置在绑定结构层上的隔离槽500和隔离区600，隔离区600设置有第一隔离坝410和第二隔离坝420，以及覆盖隔离槽500、第一隔离坝410、第二隔离坝420和隔离区600的无机封装层。在示例性实施方式中，显示区域100和绑定区域200的绑定结构层的结构与前述实施例中描述的相应结构类似，绑定区域200的绑定结构层上设置有第一平坦层15，第一平坦层15上设置有隔断槽500和隔离区600，隔断槽500设置在第一电源线210与第二电源线220之间的区域，隔断槽500暴露出第一电源线210与第二电源线220之间区域第四绝缘层14的表面，隔离区600的第二电源线220上设置有第一隔离坝410和第二隔离坝420，第一隔离坝410和第二隔离坝420以外区域暴露出第二电源线220和复合绝缘层的表面。无机封装层包括叠设的第一封装层25和第三封装层27，无机材料的第一封装层25和第三封装层27覆盖隔断槽500和隔离区600，且包裹第一隔离坝410和第二隔离坝420。在一些实施例中，隔离槽500邻近第一隔离坝410一侧的边缘与第一隔离坝410邻近隔断槽500一侧的边缘之间的距离为约40μm到约60μm。
图17为本公开显示基板又一种结构的示意图，为图3中B-B向的剖视图。显示区域100中的发光元件和复合封装层、绑定区域200中的隔离槽、隔离区、第一隔离坝和第二隔离坝的结构与前述实施例中描述的相应结构类似，与前述实施例中描述的结构不同的是，显示基板还包括第五绝缘层16。如图17所示，显示区域100的驱动结构层包括：设置在柔性基底10上的第一绝缘层11，设置在第一绝缘层11上的有源层，覆盖第一有源层的第二绝缘层12，设置在第二绝缘层12上的第一栅金属层，覆盖第一栅金属层的第三绝缘层13，设置在第三绝缘层13上的第二栅金属层，覆盖第二栅金属层的第四绝缘层14，设置在第四绝缘层14上的源漏金属层，覆盖源漏金属层的第五绝缘层16。第一平坦层15设置在驱动结构层上，发光元件设置在第一平坦层15上，发光元件中的阳极21通过贯通第五绝缘层16和第一平坦层15的过孔与第一晶体管101的第一漏电极连接。绑定区域200的绑定结构层包括：在柔性基底10上叠设的无机材料的第一绝缘层11、第二绝缘层12、第三绝缘层13和第四绝缘层14，设置在第四绝缘层14上的第一电源线210和第二电源线220，设置在第一电源线210和第二电源线220上的第五绝缘层16。第一平坦层15设置在绑定结构层上，第一平坦层15上设置有隔断槽 500和隔离区600，隔断槽500设置在第一电源线210所在区域，隔断槽500暴露出第五绝缘层16的表面，隔离区600内设置有第一隔离坝410和第二隔离坝420，第一隔离坝410和第二隔离坝420所在区域的第五绝缘层16被去掉，暴露出第二电源线220的表面，第一隔离坝410和第二隔离坝420设置在第二电源线220上。无机封装层包括叠设的第一封装层25和第三封装层27，无机材料的第一封装层25和第三封装层27覆盖隔断槽500和隔离区600，且包裹第一隔离坝410和第二隔离坝420。
在示例性实施方式中，由于第一电源线210被第五绝缘层16覆盖，隔断槽500暴露出第五绝缘层16的表面，不会出现后续形成的阴极与第一电源线210搭接的可能，因而隔断槽500与显示区域100之间的距离L2可以大大减小，后续形成的阴极边缘与隔断槽500之间的距离可以小于50μm，既有利于隔断槽500的位置布局，隔断槽500可以靠近显示区域100，延长水汽入侵路径的距离，增加水汽隔断效果，又有利于简化制备隔断槽和阴极的工艺，提高生产效率。在示例性实施方式中，由于第一电源线210和第二电源线220的边缘被第五绝缘层16覆盖，在后续刻蚀阳极的工艺中，第一电源线210和第二电源线220的边缘不会被刻蚀液侵蚀，不会形成侧面凹坑，因而避免了在第一电源线210的边缘和第二电源线220的边缘形成水汽流通路径，减小了水汽入侵路径的数量。
在一些可能的实现方式中，第一隔离坝410和第二隔离坝420所在区域的第五绝缘层16可以保留，第一隔离坝410和第二隔离坝420可以设置在第五绝缘层16的表面上。在一些可能的实现方式中，隔断槽500可以设置在第二电源线220所在区域，或者，隔断槽500可以设置在第一电源线210与第二电源线220之间的区域，本公开在此不做具体的限定。
图18为本公开显示基板又一种结构的示意图，为图3中B-B向的剖视图，示意了双源漏金属层(2SD)结构显示区域和绑定区域的剖面结构。在平行于显示基板的平面方向，显示基板包括显示区域100和绑定区域200，绑定区域200位于显示区域100的一侧。在垂直于显示基板的平面方向，显示区域100包括柔性基底10，设置在柔性基底10上的驱动结构层，设置在驱动结构层上的发光元件以及覆盖发光元件的复合封装层。绑定区域200包 括柔性基底10，设置在柔性基底10上的绑定结构层，设置在绑定结构层上的隔离槽500和设置有第一隔离坝410和第二隔离坝420的隔离区600，覆盖隔离槽500、第一隔离坝410、第二隔离坝420和隔离区600的无机封装层。
在示例性实施方式中，显示区域100的驱动结构层包括形成像素驱动电路的多个晶体管和存储电容，图18中以一个第一晶体管101和一个第一存储电容102为例进行示意。显示区域100的驱动结构层包括：设置在柔性基底10上的第一绝缘层11，设置在第一绝缘层11上的有源层，覆盖第一有源层的第二绝缘层12，设置在第二绝缘层12上的第一栅金属层，覆盖第一栅金属层的第三绝缘层13，设置在第三绝缘层13上的第二栅金属层，覆盖第二栅金属层的第四绝缘层14，设置在第四绝缘层14上的源漏金属层，覆盖源漏金属层的第五绝缘层16和设置在第五绝缘层16上的第一平坦层15，设置在第一平坦层15上的金属导电层。有源层至少包括第一有源层，第一栅金属层至少包括第一栅电极和第一电容电极，第二栅金属层至少包括第二电容电极，源漏金属层至少包括第一源电极和第一漏电极，金属导电层至少包括第一连接电极801，第一连接电极801通过过孔与第一晶体管101的第一漏电极连接，第一有源层、第一栅电极、第一源电极和第一漏电极组成第一晶体管101，第一电容电极和第二电容电极组成第一存储电容102。在一些实施例中，源漏金属层称之为第一源漏金属层(SD1)，金属导电层称之为第二源漏金属层(SD2)。显示区域100的驱动结构层上设置有第二平坦层17，第二平坦层17覆盖金属导电层，发光元件设置在第二平坦层17上，发光元件包括阳极21、像素定义层22、有机发光层23和阴极24，阳极21通过第二平坦层17上开设的过孔与连接电极801连接，因而实现阳极21与第一晶体管101的第一漏电极连接。复合封装层包括叠设的第一封装层25、第二封装层26和第三封装层27，有机材料的第二封装层26设置在无机材料的第一封装层25和第三封装层27之间。
绑定区域200的绑定结构层包括：在柔性基底10上叠设的无机材料的第一绝缘层11、第二绝缘层12、第三绝缘层13、第四绝缘层14和第五绝缘层16，设置在第五绝缘层16上的有机材料的第一平坦层15，设置在第一平坦 层15上的第一电源线210和第二电源线220，第二电源线220远离显示区域100的边缘覆盖第一平坦层15远离显示区域100的边缘。第一电源线210和第二电源线220与显示区域100的金属导电层同层设置，且通过同一次构图工艺形成。绑定区域200的绑定结构层上设置有第二平坦层17，第二平坦层17作为本公开的有机绝缘层，第二平坦层17上设置有隔断槽500和隔离区600，隔断槽500设置在第一电源线210所在区域，隔断槽500暴露出第一电源线210的表面，隔离区600设置在第二电源线220远离显示区域100的一侧，隔离区600内设置有第一隔离坝410和第二隔离坝420，第一隔离坝410和第二隔离坝420设置在第二电源线220上，除了第一隔离坝410和第二隔离坝420所在位置，隔离区600的其它位置暴露出第二电源线220和第五绝缘层16的表面。无机封装层包括叠设的第一封装层25和第三封装层27，无机材料的第一封装层25和第三封装层27覆盖隔断槽500和隔离区600，且包裹第一隔离坝410和第二隔离坝420。此外，邻近显示区域100的第二平坦层17上设置有像素定义层22，像素定义层22上设置有多个间隔设置的隔垫柱33，阴极24包裹多个隔垫柱33。
在示例性实施方式中，隔离槽500可以是一个或多个，隔断槽500的宽度为约20μm到约50μm，隔离槽500与显示区域边缘110的距离小于第一隔离坝410与显示区域边缘110的距离，隔离槽500与显示区域边缘110的距离大于阴极24边缘与显示区域边缘110的距离。隔断槽500可以设置在第二电源线220所在区域，隔断槽500暴露出第二电源线220的表面。或者，隔断槽500可以设置在第一电源线210与第二电源线220之间的区域，隔断槽500内的第一平坦层15和第二平坦层17被去除，暴露出第一电源线210与第二电源线220之间区域第五绝缘层16的表面。
在一些可能的实现方式中，第一电源线210和第二电源线220可以形成在第四绝缘层14上，与显示区域100的源漏金属层同层设置，且通过同一次构图工艺形成。形成第五绝缘层16、第一平坦层15和第二平坦层17后，隔断槽500中的第一平坦层15和第二平坦层17被去掉，隔断槽500暴露出第五绝缘层16的表面。在第二电源线220所在位置，通过去除部分区域的第五绝缘层16、第一平坦层15和第二平坦层17，使第一隔离坝410和第二隔离 坝420设置在第二电源线220上。在一些可能的实现方式中，隔断槽500可以设置在第二电源线220所在位置，或者设置在第一电源线210和第二电源线220之间的区域，本公开在此不做具体的限定。
对于双源漏金属层(2SD)结构的显示基板，本公开通过在第二平坦层上设置隔断槽，隔断了第一电源线210边缘和第二电源线220边缘出现的水汽入侵路径。当水汽沿着第一电源线210边缘和第二电源线220边缘流通到第二平坦层后，水汽会在第二平坦层内向显示区域传导扩散，由于第二平坦层上设置了隔断槽，水汽受到隔断槽的阻挡，水汽需要绕过隔断槽才能进入显示区域，入侵路径被大大延长，降低了出现GDS的风险，避免了显示基板出现显示不良，提高了显示品质。
图19为本公开显示基板又一种结构的示意图，为图3中B-B向的剖视图。显示区域100中的结构、绑定区域200中隔离槽、隔离区、第一隔离坝和第二隔离坝的结构与图18所示实施例中描述的相应结构类似，与图18所示实施例中描述的结构不同的是，绑定区域200的绑定结构层还包括第二连接电极802和第三连接电极803。如图19所示，绑定区域200的绑定结构层包括：在柔性基底10上叠设的无机材料的第一绝缘层11、第二绝缘层12、第三绝缘层13和第四绝缘层14，设置在第四绝缘层14上的第二连接电极802和第三连接电极803，设置在第二连接电极802和第三连接电极803的第五绝缘层16，设置在第五绝缘层16上的第一平坦层15，设置在第一平坦层15上的第一电源线210和第二电源线220，第一电源线210通过贯通第一平坦层15和第五绝缘层16的过孔与第二连接电极802连接，第二电源线220通过贯通第一平坦层15和第五绝缘层16的过孔与第三连接电极803连接，第二电源线220远离显示区域100的边缘覆盖第一平坦层15远离显示区域100的边缘。第二连接电极802和第三连接电极803与显示区域100的源漏金属层同层设置，且通过同一次构图工艺形成，第一电源线210和第二电源线220与显示区域100的金属导电层同层设置，且通过同一次构图工艺形成。
在示例性实施方式中，通过在绑定区域200制备第二连接电极802和第三连接电极803，使第一电源线210与第二连接电极802通过过孔连接，第 二电源线220与第三连接电极803通过过孔连接，增加了第一电源线210和第二电源线220的布局灵活性，有利于优化绑定区域200的膜层结构。
图20为本公开显示基板又一种结构的示意图，为图3中B-B向的剖视图。显示区域100中的结构、绑定区域200中隔离槽、隔离区、第一隔离坝和第二隔离坝的结构与图19所示实施例中描述的相应结构类似，与图19所示实施例中描述的结构不同的是，绑定区域200的绑定结构层没有设置第五绝缘层。如图20所示，绑定区域200的绑定结构层包括：在柔性基底10上叠设的第一绝缘层11、第二绝缘层12、第三绝缘层13和第四绝缘层14，设置在第四绝缘层14上的第二连接电极802和第三连接电极803，设置在第二连接电极802和第三连接电极803的第一平坦层15，设置在第一平坦层15上的第一电源线210和第二电源线220，第一电源线210通过过孔与第二连接电极802连接，第二电源线220通过过孔与第三连接电极803连接。在示例性实施方式中，由于没有形成第五绝缘层16，减少了制备工艺次数，降低了工艺复杂度。
图21为本公开显示基板又一种结构的示意图，为图3中B-B向的剖视图。显示区域100中的结构、绑定区域200中隔离槽、隔离区、第一隔离坝和第二隔离坝的结构与图20所示实施例中描述的相应结构类似，与图20所示实施例中描述的结构不同的是，绑定区域200的第一平坦层15被去除。如图21所示，绑定区域200的绑定结构层包括：在柔性基底10上叠设的第一绝缘层11、第二绝缘层12、第三绝缘层13和第四绝缘层14，设置在第四绝缘层14上的第二连接电极802和第三连接电极803，设置在第二连接电极802上的第一电源线210和设置在第三连接电极803上的第二电源线220。在示例性实施方式中，由于去除了绑定区域200的第一平坦层15，使得第一电源线210与第二连接电极802直接连接，第二电源线220与第三连接电极803直接连接，不仅增加了接触面积，增加了连接可靠性，而且减少了制备第一平坦层15过程中的产生的气体，提高了工艺质量。
在一些可能的实现方式中，可以去除绑定区域200的部分第一平坦层15，如仅去除第一电源线210和第二电源线220所在位置的第一平坦层15，其它区域保留第一平坦层15，使得第一电源线210与第二连接电极802直接连 接，第二电源线220与第三连接电极803直接连接。在一些可能的实现方式中，当显示基板设置有第五绝缘层时，可以将绑定区域200的第一平坦层和第五绝缘层一起去除，或者，可以去除绑定区域200的部分第一平坦层和第五绝缘层，或者，可以去除绑定区域200的部分第五绝缘层和绑定区域200的全部第一平坦层，本公开在此不做具体的限定。
图22为本公开第一扇出区的另一种结构示意图。如图22所示，显示基板包括显示区域100、绑定区域200和边缘区域300，绑定区域200位于显示区域100的一侧，边缘区域300位于显示区域100的其它侧。绑定区域200至少包括第一扇出区和位于第一扇出区的第一隔离坝410、第二隔离坝420和隔断槽500，边缘区域300至少包括第一隔离坝410、第二隔离坝420和缝隙700，绑定区域200的第一隔离坝410和第二隔离坝420与边缘区域300的第一隔离坝410和第二隔离坝420为同层设置且通过相同的构图工艺同步制备的一体结构，形成环绕显示区域100的环形结构。在示例性实施方式中，绑定区域200的隔断槽500与边缘区域300的缝隙700通过相同的构图工艺同步制备，且在绑定区域200和边缘区域300的交界处相互连通。
图23为本公开双源漏金属层(2SD)结构显示区域和边缘区域的剖面结构示意图，为图22中C-C向的剖视图。如图23所示，在垂直于显示基板的平面内，显示区域100包括柔性基底10，设置在柔性基底10上的驱动结构层，设置在驱动结构层上的发光元件以及覆盖发光元件的复合封装层。边缘区域300包括柔性基底10，设置在柔性基底10上的电路结构层，设置在电路结构层上的缝隙700、第一隔离坝410和第二隔离坝420，覆盖缝隙700的复合封装层以及包裹第一隔离坝410和第二隔离坝420的无机封装层。
在示例性实施方式中，显示区域100的驱动结构层包括形成像素驱动电路的多个晶体管和存储电容，图23中以一个第一晶体管101和一个第一存储电容102为例进行示意。显示区域100的驱动结构层包括：设置在柔性基底10上的第一绝缘层11，设置在第一绝缘层11上的有源层，覆盖有源层的第二绝缘层12，设置在第二绝缘层12上的第一栅金属层，覆盖第一栅金属层的第三绝缘层13，设置在第三绝缘层13上的第二栅金属层，覆盖第二栅金属层的第四绝缘层14，设置在第四绝缘层14上的源漏金属层，覆盖源漏金 属层的第五绝缘层16和第一平坦层15，设置在第一平坦层15上的金属导电层。有源层至少包括第一有源层，第一栅金属层至少包括第一栅电极和第一电容电极，第二栅金属层至少包括第二电容电极，源漏金属层至少包括第一源电极和第一漏电极，金属导电层至少包括第一连接电极801，第一连接电极801通过过孔与第一漏电极连接，第一有源层、第一栅电极、第一源电极和第一漏电极组成第一晶体管101，第一电容电极和第二电容电极组成第一存储电容102。在一些实施例中，源漏金属层称之为第一源漏金属层(SD1)，金属导电层称之为第二源漏金属层(SD2)。显示区域100的驱动结构层上设置有第二平坦层17，第二平坦层17覆盖金属导电层，发光元件设置在第二平坦层17上，发光元件包括阳极21、像素定义层22、有机发光层23和阴极24，阳极21通过第二平坦层17上开设的过孔与连接电极801连接，因而实现阳极21与第一晶体管101的第一漏电极连接。复合封装层包括叠设的第一封装层25、第二封装层26和第三封装层27，有机材料的第二封装层26设置在无机材料的第一封装层25和第三封装层27之间。
在示例性实施方式中，边缘区域300的电路结构层包括形成GOA电路的多个晶体管和存储电容，图23中以二个晶体管和二个存储电容为例进行示意。边缘区域300的电路结构层包括：设置在柔性基底10上的第一绝缘层11，设置在第一绝缘层11上的有源层，覆盖有源层的第二绝缘层12，设置在第二绝缘层12上的第一栅金属层，覆盖第一栅金属层的第三绝缘层13，设置在第三绝缘层13上的第二栅金属层，覆盖第二栅金属层的第四绝缘层14，设置在第四绝缘层14上的源漏金属层，覆盖源漏金属层的第五绝缘层16和第一平坦层15，设置在第一平坦层15上的金属导电层。有源层至少包括第二有源层和第三有源层，第一栅金属层至少包括第二栅电极、第三栅电极、第三电容电极和第四电容电极，第二栅金属层至少包括第五电容电极和第六电容电极，源漏金属层至少包括第二源电极、第二漏电极、第三源电极、第三漏电极和第三连接电极803，金属导电层至少包括第二电源线220。第二有源层、第二栅电极、第二源电极和第二漏电极组成第二晶体管103，第三有源层、第三栅电极、第三源电极和第三漏电极组成第三晶体管104，第三电容电极和第五电容电极组成第二存储电容105，第四电容电极和第六电容电极组成第三存储电容106。在一些实施例中，第一晶体管101可以是 驱动晶体管，第二晶体管103可以是GOA中输出扫描(SCAN)信号的扫描晶体管，第三晶体管104可以是GOA中输出使能(EM)信号的使能晶体管。在一些实施例中，驱动晶体管、扫描晶体管和使能晶体管可以是薄膜晶体管。
边缘区域300的电路结构层上设置有第二平坦层17，第二平坦层17上设置有缝隙700、第一隔离坝410和第二隔离坝420，缝隙700设置在第二电源线220与显示区域100之间，缝隙700中的第一平坦层15和第二平坦层17被去除，暴露出第五绝缘层16的表面。第一隔离坝410设置在第二电源线220所在位置，第二隔离坝420设置在第一隔离坝410远离显示区域100的一侧。复合封装层包括叠设的第一封装层25、第二封装层26和第三封装层27，复合封装层覆盖缝隙700，无机封装层包括叠设的第一封装层25和第三封装层27，无机封装层包裹第一隔离坝410和第二隔离坝420。在示例性实施方式中，边缘区域300邻近显示区域100的第二平坦层17上设置有多个隔垫柱33。
在示例性实施方式中，显示区域100的驱动结构层、绑定区域200的绑定结构层和边缘区域300的电路结构层采用相同的工艺同步形成。驱动结构层中的第一有源层与电路结构层中的第二有源层和第三有源层同层设置，且通过同一次构图工艺形成。驱动结构层中的第一栅电极和第一电容电极与电路结构层中的第二栅电极、第三栅电极、第三电容电极和第四电容电极同层设置，且通过同一次构图工艺形成。驱动结构层中的第二电容电极与电路结构层中的第五电容电极和第六电容电极同层设置，且通过同一次构图工艺形成。驱动结构层中的第一源电极和第一漏电极、绑定结构层中的第二连接电极和第三连接电极、以及电路结构层中的第二源电极、第二漏电极、第三源电极、第三漏电极和第三连接电极同层设置，且通过同一次构图工艺形成。驱动结构层中的第一连接电极、绑定结构层中的第一电源线和第二电源线、以及电路结构层中的第二电源线同层设置，且通过同一次构图工艺形成。
边缘区域300中的第二平坦层17以及第二平坦层17上设置的缝隙700与绑定区域200中的第二平坦层17以及第二平坦层17上设置的隔断槽500通过同一次工艺形成。边缘区域300中的第一隔离坝、第二隔离坝、第一封 装层和第三封装层与绑定区域200中的第一隔离坝、第二隔离坝、第一封装层和第三封装层同层设置，且通过同一次构图工艺形成。这样，在形成第二平坦层17的工艺中，绑定区域200的隔断槽500和边缘区域300的缝隙700同步形成，且两者在绑定区域200和边缘区域300的交界处连通，形成一体结构。连通的隔断槽500和缝隙700增加了水汽隔离范围，延长了水汽入侵路径，降低了出现GDS的风险，避免了显示基板出现显示不良，提高了显示品质。
结合图19和图23，显示基板的制备过程包括：
(11)在玻璃载板1上制备柔性基底10。
(12)在显示区域100、绑定区域200和边缘区域300分别形成驱动结构层、绑定结构层和电路结构层图案。显示区域100的驱动结构层包括第一晶体管101、第一电容电极102和第一连接电极801，绑定区域200的绑定结构层包括第二连接电极802和第三连接电极803，边缘区域300的电路结构层包括第二晶体管103、第三晶体管104、第二存储电容105、第三存储电容106和第三连接电极803。在示例性实施方式中，驱动结构层、绑定结构层和电路结构层的制备过程可以包括：
在柔性基底10上形成第一绝缘层11，以及设置在第一绝缘层11上的有源层图案，有源层至少包括第一有源层、第二有源层和第三有源层。
形成覆盖有源层图案的第二绝缘层12，以及设置在第二绝缘层12上的第一栅金属层图案，第一栅金属层至少包括第一栅电极、第二栅电极、第三栅电极、第一电容电极、第三电容电极和第四电容电极。
形成覆盖第一栅金属层的第三绝缘层13，以及设置在第三绝缘层13上的第二栅金属层图案，第二栅金属层图案至少包括第二电容电极、第五电容电极和第六电容电极。
形成覆盖第二栅金属层的第四绝缘层14图案，第四绝缘层14上开设有多个第一过孔。在第四绝缘层14上形成源漏金属层图案，源漏金属层至少包括第一源电极、第一漏电极、第二源电极、第二漏电极、第三源电极、第三漏电极、第二连接电极802和第三连接电极803，第一源电极和第一漏电 极分别通过第一过孔与第一有源层连接，第二源电极和第二漏电极分别通过第一过孔与第二有源层连接，第三源电极和第三漏电极分别通过第一过孔与第三有源层连接。
形成覆盖源漏金属层的第五绝缘层16和第一平坦化层15图案，在第一平坦层15上形成多个第二过孔，显示区域100的第二过孔暴露出第一晶体管101的第一漏电极的表面，绑定区域200的第二过孔分别暴露出第二连接电极802和第三连接电极803的表面，边缘区域的第二过孔暴露出第三连接电极803的表面。
在第一平坦层15上形成金属导电层图案，金属导电层至少包括第一连接电极801、第一电源线210和第二电源线220，显示区域100的第一连接电极801通过第二过孔与第一晶体管101的第一漏电极连接，绑定区域200的第一电源线210和第二电源线220分别通过第二过孔与第二连接电极802和第三连接电极803连接，边缘区域的第二电源线220通过第二过孔与第三连接电极803连接，且第二电源线220远离显示区域100的边缘覆盖第一平坦层15远离显示区域100的边缘。
(13)形成第二平坦层17图案，显示区域100的第二平坦层17上开设有第三过孔，第三过孔暴露出第一连接电极801的表面。绑定区域200的第二平坦层17上设置有隔断槽500和隔离区600，隔断槽500设置在第一电源线210所在区域，隔断槽500暴露出第一电源线210的表面，隔离区600设置在第二电源线220远离显示区域100的一侧，隔离区600内的第二电源线220上设置有平坦坝基，除了平坦坝基，隔离区600其它位置的第二平坦层17被显影掉，暴露出第二电源线220的表面和第五绝缘层16的表面。边缘区域300的第二平坦层17上开设有第四过孔和缝隙700，第四过孔内设置有平坦坝基，除了平坦坝基，第四过孔内的第二平坦层17被显影掉，暴露出第二电源线220的表面，缝隙700设置在第二电源线220与显示区域100之间，缝隙700内的第一平坦层15和第二平坦层17被显影掉，暴露出第五绝缘层16的表面。在缝隙700所在区域，第二平坦层17的开口在柔性基底10上的正投影包含第一平坦层15的开口，即第二平坦层17的开口宽度大于第一平坦层15的开口宽度，第一平坦层15的开口暴露出第五绝缘层16，第二 平坦层17的开口暴露出第一平坦层15的开口，在缝隙700的侧壁上形成阶梯状，使后续形成的阴极也具有阶梯状，以保证阴极与第四连接电极的可靠连接。
(14)在形成前述图案的基底上形成阳极21和第四连接电极804图案，阳极21形成在显示区域100的第二平坦层17上，通过第三过孔与第一连接电极801连接，第四连接电极804形成在边缘区域300的第二平坦层17上，第四连接电极804的一部分通过第四过孔与第二电源线220连接，另一部分设置在缝隙700中，第四过孔与缝隙700之间的第四连接电极804上开设有多个过孔。由于缝隙700的侧壁为阶梯状，因此设置在缝隙700中的第四连接电极804也为阶梯状。
(15)在形成前述图案的基底上形成像素定义层22、第一坝基和第二坝基图案，显示区域100的像素定义层22上开设有像素开口，像素开口暴露出阳极21的表面。第一坝基和第二坝基形成在绑定区域200和边缘区域300，绑定区域200的第一坝基形成在第二电源线220上，第二坝基形成在平坦坝基上。边缘区域300的第一坝基设置在第四过孔内，第二坝基设置在第一坝基远离显示区域100一侧的第二平坦层17上。
(16)在绑定区域200和边缘区域300形成多个隔离柱33图案，多个隔离柱33分别设置在像素定义层22、第一坝基、第二坝基以及缝隙700两侧的位置，在绑定区域200和边缘区域300同步形成第一支撑坝410和第二支撑坝420，绑定区域200和边缘区域300的第一支撑坝410为一体结构，绑定区域200和边缘区域300的第二支撑坝420为一体结构。
(17)在形成前述图案的基底上依次形成有机发光层23和阴极24。有机发光层23形成在像素开口内，由于阳极21与第一连接电极801连接，第一连接电极801与第一晶体管101的漏电极连接，因而实现了有机发光层23的发光控制。阴极24的一部分形成在显示区域100的有机发光层23上，另一部分形成在绑定区域200和边缘区域300。绑定区域200的阴极24包裹像素定义层22上的多个隔垫柱33，边缘区域300的阴极24通过缝隙700和第四过孔与第四连接电极804连接。由于第四连接电极804与第二电源线220连接，因而实现了阴极24与第二电源线220的连接。由于缝隙700位置的第 四连接电极804为阶梯状，因此所形成的阴极24也具有阶梯状，在不同的台阶上与第四连接电极804接触，保证了阴极与第四连接电极804的可靠连接。
(18)在形成前述图案的基础上形成封装层，封装层包括叠设的第一封装层25、第二封装层26和第三封装层27。第一封装层25采用无机材料，在显示区域100覆盖阴极24，在绑定区域200分别包裹多个隔垫柱33、覆盖隔断槽500、覆盖隔离区600以及包裹第一支撑坝410和第二支撑坝420，在边缘区域300包裹多个隔垫柱33、覆盖缝隙700以及包裹第一支撑坝410和第二支撑坝420。第二封装层26采用有机材料，设置在显示区域100、绑定区域200的隔垫柱33所在区域和边缘区域300的隔垫柱33所在区域，第三封装层27采用无机材料，覆盖第一封装层25和第二封装层26。
图24为本公开单源漏金属层(1SD)结构显示区域和边缘区域的剖面结构示意图，为图22中C-C向的剖视图。如图24所示，在垂直于显示基板的平面内，显示区域100包括柔性基底10，设置在柔性基底10上的驱动结构层，设置在驱动结构层上的发光元件以及覆盖发光元件的复合封装层。边缘区域300包括柔性基底10，设置在柔性基底10上的电路结构层，设置在电路结构层上的缝隙700、第一隔离坝410和第二隔离坝420，覆盖缝隙700的复合封装层以及包裹第一隔离坝410和第二隔离坝420的无机封装层。
在示例性实施方式中，显示区域100的驱动结构层包括形成像素驱动电路的多个晶体管和存储电容，边缘区域300的电路结构层包括形成GOA电路的多个晶体管和存储电容，图24中以三个晶体管和三合存储电容为例进行示意。驱动结构层和电路结构层包括：设置在柔性基底10上的第一绝缘层11，设置在第一绝缘层11上的有源层，覆盖有源层的第二绝缘层12，设置在第二绝缘层12上的第一栅金属层，覆盖第一栅金属层的第三绝缘层13，设置在第三绝缘层13上的第二栅金属层，覆盖第二栅金属层的第四绝缘层14，设置在第四绝缘层14上的源漏金属层，覆盖源漏金属层的第五绝缘层16。有源层至少包括第一有源层、第二有源层和第三有源层，第一栅金属层至少包括第一栅电极、第二栅电极、第三栅电极、第一电容电极、第三电容电极和第四电容电极，第二栅金属层至少包括第二电容电极、第五电容电极 和第六电容电极，源漏金属层至少包括第一源电极、第一漏电极、第二源电极、第二漏电极、第三源电极、第三漏电极和第二电源线220。第一有源层、第一栅电极、第一源电极和第一漏电极组成第一晶体管101，第二有源层、第二栅电极、第二源电极和第二漏电极组成第二晶体管103，第三有源层、第三栅电极、第三源电极和第三漏电极组成第三晶体管104，第一电容电极和第二电容电极组成第一存储电容102，第三电容电极和第五电容电极组成第二存储电容105，第四电容电极和第六电容电极组成第三存储电容106。
驱动结构层和电路结构层上设置有第一平坦层15，显示区域100的发光元件设置在第一平坦层15上，发光元件包括阳极21、像素定义层22、有机发光层23和阴极24，阳极21通过第一平坦层15上开设的过孔与第一晶体管101的第一漏电极连接。边缘区域300的第一平坦层15上设置有缝隙700、隔垫柱33、第一隔离坝410和第二隔离坝420，缝隙700设置在第二电源线220与显示区域100之间，缝隙700中的第一平坦层15被去除，暴露出第五绝缘层16的表面，多个隔垫柱33位于边缘区域300邻近显示区域100的第一平坦层15上，第一隔离坝410和第二隔离坝42设置在第二电源线220所在位置，第二隔离坝420设置在第一隔离坝410远离显示区域100的一侧。复合封装层包括叠设的第一封装层25、第二封装层26和第三封装层27，复合封装层覆盖显示区域100和边缘区域300的缝隙700和多个隔垫柱33，无机封装层包括叠设的第一封装层25和第三封装层27，无机封装层包裹第一隔离坝410和第二隔离坝420。
在示例性实施方式中，显示区域100的驱动结构层、绑定区域200的绑定结构层和边缘区域300的电路结构层采用相同的工艺同步形成。边缘区域300中的第一平坦层15以及第一平坦层15上设置的缝隙700与绑定区域200中的第一平坦层15以及第一平坦层15上设置的隔断槽500通过同一次工艺形成。边缘区域300中的第一隔离坝、第二隔离坝、第一封装层和第三封装层与绑定区域200中的第一隔离坝、第二隔离坝、第一封装层和第三封装层同层设置，且通过同一次构图工艺形成。这样，在形成第一平坦层15的工艺中，绑定区域200的隔断槽500和边缘区域300的缝隙700同步形成，且 两者在绑定区域200和边缘区域300的交界处连通，形成一体结构。连通的隔断槽500和缝隙700增加了水汽隔离范围，延长了水汽入侵路径，降低了出现GDS的风险，避免了显示基板出现显示不良，提高了显示品质。
结合图17和图24，显示基板的制备过程包括：
(21)在玻璃载板1上制备柔性基底10。
(22)在显示区域100、绑定区域200和边缘区域300分别形成驱动结构层、绑定结构层和电路结构层图案。在示例性实施方式中，驱动结构层、绑定结构层和电路结构层的制备过程可以包括：
在柔性基底10上形成第一绝缘层11，以及设置在第一绝缘层11上的有源层图案，有源层至少包括第一有源层、第二有源层和第三有源层。
形成覆盖有源层图案的第二绝缘层12，以及设置在第二绝缘层12上的第一栅金属层图案，第一栅金属层至少包括第一栅电极、第二栅电极、第三栅电极、第一电容电极、第三电容电极和第四电容电极。
形成覆盖第一栅金属层的第三绝缘层13，以及设置在第三绝缘层13上的第二栅金属层图案，第二栅金属层图案至少包括第二电容电极、第五电容电极和第六电容电极。
形成覆盖第二栅金属层的第四绝缘层14图案，第四绝缘层14上开设有多个第一过孔。在第四绝缘层14上形成源漏金属层图案，源漏金属层至少包括第一源电极、第一漏电极、第二源电极、第二漏电极、第三源电极、第三漏电极和第二电源线220，第一源电极和第一漏电极分别通过第一过孔与第一有源层连接，第二源电极和第二漏电极分别通过第一过孔与第二有源层连接，第三源电极和第三漏电极分别通过第一过孔与第三有源层连接。
形成覆盖源漏金属层的第五绝缘层16。
(23)形成第一平坦层15图案，显示区域100的第一平坦层15上开设有过孔，过孔暴露出第一晶体管101的第一漏电极。绑定区域200的第一平坦层15上形成有隔断槽500和隔离区600，隔断槽500设置在第一电源线210所在区域，隔断槽500暴露出第一电源线210的表面，隔离区600设置在第 二电源线220远离显示区域100的一侧，隔离区600内的第二电源线220上设置有平坦坝基。边缘区域300的第一平坦层15上开设有第四过孔和缝隙700，第四过孔暴露出第二电源线220的表面，缝隙700设置在第二电源线220与显示区域100之间，缝隙700暴露出第五绝缘层16的表面，平坦坝基设置在第四过孔远离显示区域100的一侧。
(24)在形成前述图案的基底上形成阳极21和第四连接电极804图案，阳极21形成在显示区域100的第一平坦层15上，通过过孔与第一晶体管101的第一漏电极连接，第四连接电极804形成在边缘区域300的第一平坦层15上，第四连接电极804的一部分通过第四过孔与第二电源线220连接，另一部分设置在缝隙700中，第四过孔与缝隙700之间的第四连接电极804上开设有多个过孔。
(25)在形成前述图案的基底上形成像素定义层22、第一坝基和第二坝基图案，显示区域100的像素定义层22上开设有像素开口，像素开口暴露出阳极21的表面。第一坝基和第二坝基形成在绑定区域200和边缘区域300，绑定区域200的第一坝基形成在第二电源线220上，第二坝基形成在平坦坝基上，边缘区域300的第一坝基设置在第四过孔内，第二坝基设置在平坦坝基上。
(26)在绑定区域200和边缘区域300形成多个隔离柱33图案，多个隔离柱33分别设置在像素定义层22、第一坝基、第二坝基以及缝隙700两侧的位置，在绑定区域200和边缘区域300同步形成第一支撑坝410和第二支撑坝420，绑定区域200和边缘区域300的第一支撑坝410为一体结构，绑定区域200和边缘区域300的第二支撑坝420为一体结构。
(27)在形成前述图案的基底上依次形成有机发光层23和阴极24。有机发光层23形成在像素开口内，阴极24的一部分形成在显示区域100的有机发光层23上，另一部分形成在绑定区域200和边缘区域300。绑定区域200的阴极24包裹像素定义层22上的多个隔垫柱33，边缘区域300的阴极24通过缝隙700和第四过孔与第四连接电极804连接。由于第四连接电极804与第二电源线220连接，因而实现了阴极24与第二电源线220的连接。
(28)在形成前述图案的基础上形成封装层，封装层包括叠设的第一封 装层25、第二封装层26和第三封装层27。第一封装层25采用无机材料，在显示区域100覆盖阴极24，在绑定区域200分别包裹多个隔垫柱33、覆盖隔断槽500、覆盖隔离区600以及包裹第一支撑坝410和第二支撑坝420，在边缘区域300包裹多个隔垫柱33、覆盖缝隙700以及包裹第一支撑坝410和第二支撑坝420。第二封装层26采用有机材料，设置在显示区域100、绑定区域200的隔垫柱33所在区域和边缘区域300的隔垫柱33所在区域，第三封装层27采用无机材料，覆盖第一封装层25和第二封装层26。
图23和图24所示的边缘区域的结构仅仅是一种示例性说明。在示例性实施方式中，可以根据实际需要变更第二电源线220、第一支撑坝410和第二支撑坝420等边缘结构。例如，驱动结构层、绑定结构层和电路结构层中可以不设置第五绝缘层16。又如，第二电源线220可以向远离显示区域100的一侧延伸或。再如，可以设置多个缝隙700，本公开在此不做具体的限定。
图25和图26为本公开第一扇出区的另一种结构示意图，图26为图25中E区域的放大图。如图25所示，在平行于显示基板的平面内，绑定区域200位于显示区域100的一侧，绑定区域200的第一扇出区邻近显示区域边缘110。第一扇出区包括第一电源线210、第二电源线220、第一隔离坝410、第二隔离坝420和至少一个隔断槽500，第一电源线210与显示区域100的高电压电源线VDD连接，第二电源线220与边缘区域300的低电压电源线VSS连接，第一隔离坝410和第二隔离坝420沿着平行于显示区域边缘110的方向延伸，至少一个隔断槽500沿着平行于显示区域边缘110的方向延伸，隔断槽500与显示区域边缘110的距离小于第一隔离坝410与显示区域边缘110的距离。第一电源线210包括沿着平行于显示区域边缘110方向延伸的第一条形块2101和沿着远离显示区域100方向延伸的第二条形块2102，第二条形块2102邻近显示区域100的一端与第一条形块2101连接，形成T状结构。第二电源线220包括沿着平行于显示区域边缘110方向延伸的第三条形块2201和沿着远离显示区域100方向延伸的第四条形块2202，第四条形块2202邻近显示区域100的一端与第三条形块2201连接，形成角状结构。在示例性实施方式中，第一电源线210和第二电源线220的边缘设置有波浪结构230。沿着远离显示区域100的方向，波浪结构230可以设置 在第一电源线210中第二条形块2102两侧的边缘上，可以设置在第二电源线220两侧的边缘上。在一些实施例中，波浪结构230可以设置在隔离槽500远离显示区域100一侧的第一电源线210和第二电源线220的边缘上，或者，波浪结构230可以设置在第一隔离坝410远离显示区域100一侧的第一电源线210和第二电源线220的边缘上，或者，波浪结构230可以设置在第二隔离坝420远离显示区域100一侧的第一电源线210和第二电源线220的边缘上，或者，波浪结构230可以设置在第一电源线210和第二电源线220与第一隔离坝410和第二隔离坝420重叠区域的第一电源线210和第二电源线220的边缘上。
如图26所示，波浪结构230包括间隔设置的多个凸起以及多个凸起之间的凹陷，形成第一电源线210和第二电源线220的波浪状边缘。对于第一电源线210和第二电源线220边缘出现的水汽传输路径，通过将第一电源线210和第二电源线220的边缘设置成波浪状，可以增加水汽传输路径的长度，迟滞和缓解水汽的扩散。在示例性实施方式中，波浪结构230中外侧最高点与内侧最低点之间的突起高度T1为约30μm到约60μm，相邻凸起之间的距离T2为约20μm到约50μm。
图25和图26所示的波浪结构仅仅是一种示例性说明。在示例性实施方式中，可以根据实际需要变更波浪结构230的设置位置和形状。例如，沿着远离显示区域100的方向，波浪结构230可以仅设置在第一隔离坝410和第二隔离坝420之间区域的电源线两侧的边缘上。又如，沿着远离显示区域100的方向，波浪结构230可以仅设置在第二隔离坝420远离显示区域100一侧区域的电源线两侧的边缘上。再如，波浪结构230可以仅设置在第二电源线220朝向第二条形块2102一侧的边缘上以及第二条形块2102朝向第二电源线220一侧的边缘上。再如，波浪结构230可以仅设置在第二电源线220远离第二条形块2102一侧的边缘上以及第二条形块2102远离第二电源线220一侧的边缘上。再如，波浪结构中的凸起和凹陷可以由多段弧线组成，或者可以由多段直线组成，或者可以由多段弧线和多段直线组成，本公开在此不做具体的限定。
本公开还提供了一种显示基板的制备方法，显示基板包括显示区域和位 于显示区域一侧的绑定区域，所述制备方法包括：
S1、在所述显示区域和绑定区域分别形成驱动结构层和绑定结构层；所述驱动结构层包括像素驱动电路，所述绑定结构层包括与所述像素驱动电路连接的电源线；
S2、在所述驱动结构层和绑定结构层上形成有机绝缘层，所述绑定结构层上的有机绝缘层上形成有至少一个隔离槽；
S3、在所述显示区域和绑定区域分别形成发光元件和隔离坝；所述发光元件与所述像素驱动电路连接，所述隔离槽与显示区域边缘的距离小于所述隔离坝与显示区域边缘的距离；
S4、在所述绑定区域形成无机封装层，所述无机封装层覆盖所述隔离槽和包裹所述隔离坝。
在示例性实施方式中，在所述显示区域和绑定区域分别形成发光元件和隔离坝包括：在所述显示区域形成发光元件，所述发光元件与所述像素驱动电路连接；在所述绑定区域形成第一隔离坝和第二隔离坝，所述第一隔离坝与显示区域边缘的距离小于所述第二隔离坝与显示区域边缘的距离，所述隔离槽与显示区域边缘的距离小于所述第一隔离坝与显示区域边缘的距离。
在示例性实施方式中，在所述显示区域形成发光元件包括：在所述有机绝缘层上依次形成阳极、像素定义层、有机发光层和阴极，所述阳极与所述像素驱动电路连接，所述像素定义层和阴极延伸到所述绑定区域；沿着远离所述显示区域的方向，所述绑定区域中阴极的宽度小于所述隔离槽与显示区域边缘的距离。
在示例性实施方式中，所述电源线包括第一电源线和第二电源线，所述隔离槽设置在所述第一电源线上，或者设置在所述第二电源线上，或者设置在所述第一电源线与第二电源线之间，沿着远离所述显示区域的方向，所述隔离槽的宽度为约20μm～约70μm。
在示例性实施方式中，所述显示基板还包括边缘区域，所述制备方法还包括：在所述边缘区域形成电路结构层，在所述电路结构层上形成有机绝缘层，所述有机绝缘层上形成有至少一个缝隙，所述绑定区域的隔离槽和边缘 区域的缝隙连通，且通过同一次工艺形成。
在示例性实施方式中，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层和设置在所述复合绝缘层上的第一电源线和第二电源线；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第一电源线和第二电源线和设置在所述第一电源线和第二电源线上的第五绝缘层；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第五绝缘层、设置在所述第五绝缘层上的第一平坦层以及设置在所述第一平坦层上的第一电源线和第二电源线；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第一电源线和第二电源线、设置在所述第一电源线和第二电源线上的第五绝缘层以及设置在所述第五绝缘层上的第一平坦层；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第二连接电极和第三连接电极、覆盖所述第二连接电极和第三连接电极的第五绝缘层、设置在所述第五绝缘层上的第一平坦层以及设置在所述第一平坦层上的第一电源线和第二电源线，所述第一电源线通过过孔与第二连接电极连接，所述第二电源线通过过孔与第三连接电极连接。设置在所述绑定结构层上的有机绝缘层包括第一平坦层，或者包括第二平坦层；所述复合绝缘层包括在基底上叠设的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层。
在示例性实施方式中，所述电源线的边缘设置有波浪结构；所述波浪结构设置在所述隔离槽远离所述显示区域一侧的电源线的边缘上，或者，所述波浪结构设置在所述隔离坝远离所述显示区域一侧的电源线的边缘上，或者，所述波浪结构设置在所述电源线与隔离坝重叠区域的电源线的边缘上；所述波浪结构包括间隔设置的多个凸起，所述凸起的突起高度为约30μm到约60μm。
本公开还提供了一种显示装置，包括前述实施例的显示基板。显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本申请中的附图只涉及本公开涉及到的结构，其他结构可参考通常设 计。在不冲突的情况下，本公开的实施例即实施例中的特征可以相互组合以得到新的实施例。
本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本申请的权利要求的范围当中。

Claims (20)

  1. 一种显示基板，包括显示区域和位于显示区域一侧的绑定区域，所述显示区域包括驱动结构层、设置在所述驱动结构层上的有机绝缘层以及设置在所述有机绝缘层上的发光元件，所述驱动结构层包括像素驱动电路，所述发光元件与所述像素驱动电路连接；所述绑定区域包括绑定结构层、设置在所述绑定结构层上的有机绝缘层和隔离坝以及设置在所述有机绝缘层和隔离坝上的无机封装层，所述绑定结构层包括与所述像素驱动电路连接的电源线；所述绑定区域的有机绝缘层上设置有至少一个隔离槽，所述无机封装层覆盖所述隔离槽和包裹所述隔离坝，所述隔离槽与显示区域边缘的距离小于所述隔离坝与显示区域边缘的距离。
  2. 根据权利要求1所述的显示基板，其中，所述隔离坝包括第一隔离坝和第二隔离坝，所述第一隔离坝与显示区域边缘的距离小于所述第二隔离坝与显示区域边缘的距离；所述隔离槽与显示区域边缘的距离小于所述第一隔离坝与显示区域边缘的距离。
  3. 根据权利要求2所述的显示基板，其中，所述发光元件包括阳极、像素定义层、有机发光层和阴极，所述像素定义层和阴极延伸到所述绑定区域；沿着远离所述显示区域的方向，所述绑定区域中阴极边缘与显示区域边缘之间的距离小于所述隔离槽与显示区域边缘的距离。
  4. 根据权利要求1所述的显示基板，其中，沿着远离所述显示区域的方向，所述隔离槽的宽度为20μm～70μm。
  5. 根据权利要求1所述的显示基板，其中，所述电源线包括第一电源线和第二电源线，所述隔离槽设置在所述第一电源线上，或者设置在所述第二电源线上，或者设置在所述第一电源线上与第二电源线之间。
  6. 根据权利要求5所述的显示基板，其中，沿着所述显示区域边缘方向，所述隔离槽在基底上的正投影包含所述第一电源线在基底上的正投影。
  7. 根据权利要求5所述的显示基板，所述显示基板还包括边缘区域，所述边缘区域包括电路结构层和设置在所述电路结构层上的有机绝缘层，所述有机绝缘层上设置有缝隙，所述绑定区域的隔离槽和边缘区域的缝隙连 通。
  8. 根据权利要求5所述的显示基板，其中，所述第一电源线包括第一条形块和第二条形块，所述第一条形块沿着所述显示区域边缘方向延伸，所述第二条形块沿着远离所述显示区域的方向延伸，所述第二条形块邻近所述显示区域的一端与所述第一条形块连接，形成T状结构；所述第二电压线位于所述第一条形块远离所述显示区域的一侧，所述隔离坝设置在所述的第二条形块和第二电源线上，所述隔断槽设置在所述第一条形块上。
  9. 根据权利要求5所述的显示基板，其中，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层和设置在所述复合绝缘层上的第一电源线和第二电源线；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第一电源线和第二电源线和设置在所述第一电源线和第二电源线上的第五绝缘层；
    设置在所述绑定结构层上的有机绝缘层包括第一平坦层；所述复合绝缘层包括在基底上叠设的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层。
  10. 根据权利要求5所述的显示基板，其中，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第五绝缘层、设置在所述第五绝缘层上的第一平坦层以及设置在所述第一平坦层上的第一电源线和第二电源线；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第一电源线和第二电源线、设置在所述第一电源线和第二电源线上的第五绝缘层以及设置在所述第五绝缘层上的第一平坦层；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第二连接电极和第三连接电极、覆盖所述第二连接电极和第三连接电极的第五绝缘层、设置在所述第五绝缘层上的第一平坦层以及设置在所述第一平坦层上的第一电源线和第二电源线，所述第一电源线通过过孔与第二连接电极连接，所述第二电源线通过过孔与第三连接电极连接；
    设置在所述绑定结构层上的有机绝缘层包括第二平坦层；所述复合绝缘层包括在基底上叠设的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘 层。
  11. 根据权利要求1到10任一项所述的显示基板，其中，所述电源线的边缘设置有波浪结构；所述波浪结构设置在所述隔离槽远离所述显示区域一侧的电源线的边缘上，或者，所述波浪结构设置在所述隔离坝远离所述显示区域一侧的电源线的边缘上，或者，所述波浪结构设置在所述电源线与所述隔离坝重叠区域的电源线的边缘上。
  12. 根据权利要求11所述的显示基板，其中，所述波浪结构包括间隔设置的多个凸起，所述凸起的突起高度为30μm到60μm。
  13. 一种显示基板的制备方法，显示基板包括显示区域和位于显示区域一侧的绑定区域，所述制备方法包括：
    在所述显示区域和绑定区域分别形成驱动结构层和绑定结构层；所述驱动结构层包括像素驱动电路，所述绑定结构层包括与所述像素驱动电路连接的电源线；
    在所述驱动结构层和绑定结构层上形成有机绝缘层，所述绑定结构层上的有机绝缘层上形成有至少一个隔离槽；
    在所述显示区域和绑定区域分别形成发光元件和隔离坝；所述发光元件与所述像素驱动电路连接，所述隔离槽与显示区域边缘的距离小于所述隔离坝与显示区域边缘的距离；
    在所述显示区域和绑定区域分别形成复合封装层和无机封装层，所述无机封装层覆盖所述隔离槽和包裹所述隔离坝。
  14. 根据权利要求13所述的制备方法，其中，在所述显示区域和绑定区域分别形成发光元件和隔离坝包括：在所述显示区域形成发光元件，所述发光元件与所述像素驱动电路连接；在所述绑定区域形成第一隔离坝和第二隔离坝，所述第一隔离坝与显示区域边缘的距离小于所述第二隔离坝与显示区域边缘的距离，所述隔离槽与显示区域边缘的距离小于所述第一隔离坝与显示区域边缘的距离。
  15. 根据权利要求14所述的制备方法，其中，在所述显示区域形成发 光元件包括：在所述有机绝缘层上依次形成阳极、像素定义层、有机发光层和阴极，所述阳极与所述像素驱动电路连接，所述像素定义层和阴极延伸到所述绑定区域；沿着远离所述显示区域的方向，所述绑定区域中阴极边缘与显示区域边缘之间的距离小于所述隔离槽与显示区域边缘的距离。
  16. 根据权利要求13所述的制备方法，其中，所述电源线包括第一电源线和第二电源线，所述隔离槽设置在所述第一电源线上，或者设置在所述第二电源线上，或者设置在所述第一电源线与第二电源线之间，沿着远离所述显示区域的方向，所述隔离槽的宽度为20μm～70μm。
  17. 根据权利要求13所述的制备方法，其中，所述显示基板还包括边缘区域，所述制备方法还包括：在所述边缘区域形成电路结构层，在所述电路结构层上形成有机绝缘层，所述有机绝缘层上形成有至少一个缝隙，所述绑定区域的隔离槽和边缘区域的缝隙连通，且通过同一次工艺形成。
  18. 根据权利要求13所述的制备方法，其中，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层和设置在所述复合绝缘层上的第一电源线和第二电源线；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第一电源线和第二电源线和设置在所述第一电源线和第二电源线上的第五绝缘层；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第五绝缘层、设置在所述第五绝缘层上的第一平坦层以及设置在所述第一平坦层上的第一电源线和第二电源线；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第一电源线和第二电源线、设置在所述第一电源线和第二电源线上的第五绝缘层以及设置在所述第五绝缘层上的第一平坦层；或者，所述绑定区域的绑定结构层包括设置在基底上的复合绝缘层、设置在所述复合绝缘层上的第二连接电极和第三连接电极、覆盖所述第二连接电极和第三连接电极的第五绝缘层、设置在所述第五绝缘层上的第一平坦层以及设置在所述第一平坦层上的第一电源线和第二电源线，所述第一电源线通过过孔与第二连接电极连接，所述第二电源线通过过孔与第三连接电极连接；
    设置在所述绑定结构层上的有机绝缘层包括第一平坦层，或者包括第二 平坦层；所述复合绝缘层包括在基底上叠设的第一绝缘层、第二绝缘层、第三绝缘层和第四绝缘层。
  19. 根据权利要求13到18任一项所述的制备方法，其中，所述电源线的边缘设置有波浪结构；所述波浪结构设置在所述隔离槽远离所述显示区域一侧的电源线的边缘上，或者，所述波浪结构设置在所述隔离坝远离所述显示区域一侧的电源线的边缘上，或者，所述波浪结构设置在所述电源线与隔离坝重叠区域的电源线的边缘上；所述波浪结构包括间隔设置的多个凸起，所述凸起的突起高度为30μm到60μm。
  20. 一种显示装置，包括如权利要求1到12任一项所述的显示基板。
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