WO2021213237A1 - 多通道信号同步系统、电路及方法 - Google Patents

多通道信号同步系统、电路及方法 Download PDF

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Publication number
WO2021213237A1
WO2021213237A1 PCT/CN2021/087347 CN2021087347W WO2021213237A1 WO 2021213237 A1 WO2021213237 A1 WO 2021213237A1 CN 2021087347 W CN2021087347 W CN 2021087347W WO 2021213237 A1 WO2021213237 A1 WO 2021213237A1
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WIPO (PCT)
Prior art keywords
signal
clock signal
synchronization
generation module
clock
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Ceased
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PCT/CN2021/087347
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English (en)
French (fr)
Inventor
罗浚洲
方超敏
严波
王悦
王铁军
李维森
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Rigol Technologies Co Ltd
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Rigol Technologies Co Ltd
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Priority to EP21793541.0A priority Critical patent/EP4142203B1/en
Priority to JP2022563188A priority patent/JP7471447B2/ja
Publication of WO2021213237A1 publication Critical patent/WO2021213237A1/zh
Priority to US17/966,133 priority patent/US11902015B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • G01R19/2506—Arrangements for conditioning or analysing measured signals, e.g. for indicating peak values ; Details concerning sampling, digitizing or waveform capturing
    • G01R19/2509—Details concerning sampling, digitizing or waveform capturing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R13/00—Arrangements for displaying electric variables or waveforms

Definitions

  • the embodiments of the present application relate to the field of signal technology, for example, to a multi-channel signal synchronization system, circuit, and method.
  • clock signals are the basis for circuits with sequential logic to perform corresponding operations.
  • it is necessary to transmit clock signals to components corresponding to multiple channels in the system so that the multi-channel system can implement the corresponding work of the system based on the corresponding clock signals.
  • a clock signal can be generated and output to the analog-to-digital converter corresponding to each channel to realize data collection.
  • the synchronization operation may fail.
  • the purpose of the embodiments of the present application is to provide a multi-channel signal synchronization system, circuit, and method to solve the problem of how to conveniently and effectively realize signal synchronization in a multi-channel system.
  • the embodiment of the present application provides a multi-channel signal synchronization system, including a clock signal generation module, a synchronization signal generation module, and at least two signal receiving modules;
  • the clock signal generation module is configured to generate a first clock signal and transmit the first clock signal to the synchronization signal generation module;
  • the synchronization signal generation module is configured to generate a synchronization signal based on the first clock signal output by the clock signal generation module, and transmit the synchronization signal to the clock signal generation module;
  • the clock signal generation module is further configured to generate a second clock signal based on the synchronization signal fed back by the synchronization signal generation module, and transmit the second clock signal to the at least two signal receiving modules;
  • the synchronization signal generating module is further configured to transmit the synchronization signal to the at least two signal receiving modules.
  • the embodiment of the present application provides a multi-channel signal synchronization system, including a clock signal generation module, a synchronization signal generation module, and at least two signal receiving modules;
  • the clock signal generation module is configured to generate a first clock signal and transmit the first clock signal to the synchronization signal generation module;
  • the synchronization signal generation module is configured to generate a synchronization signal based on the first clock signal output by the clock signal generation module, and transmit the synchronization signal to the clock signal generation module;
  • the clock signal generation module is further configured to generate a second clock signal based on the synchronization signal fed back by the synchronization signal generation module, and transmit the synchronization signal and the second clock signal to the at least two signal receiving modules.
  • the embodiment of the present application provides a multi-channel signal synchronization circuit, including a clock signal generation module, a synchronization signal generation module, and a signal output port;
  • a first clock signal transmission branch and a first synchronization signal transmission branch are provided between the clock signal generation module and the synchronization signal generation module, and the first clock signal transmission branch is set to be controlled by the clock signal.
  • the generation module transmits the first clock signal to the synchronization signal generation module, and the synchronization signal transmission first branch is configured to transmit the synchronization signal from the synchronization signal generation module to the clock signal generation module; the synchronization The signal generating module is configured to generate the synchronization signal based on the received first clock signal;
  • a second clock signal transmission branch is provided between the clock signal generation module and the signal output port, and the second clock signal transmission branch is configured to transmit the second clock signal to the clock signal generation module.
  • the signal output port; the clock signal generation module is configured to generate the second clock signal based on the received synchronization signal and the first clock signal;
  • a second synchronization signal transmission branch is provided between the synchronization signal generation module and the signal output port, and the synchronization signal transmission second branch is configured to transmit the synchronization signal to the synchronization signal by the synchronization signal generation module.
  • the signal output port is provided between the synchronization signal generation module and the signal output port, and the synchronization signal transmission second branch is configured to transmit the synchronization signal to the synchronization signal by the synchronization signal generation module.
  • the embodiment of the present application provides a multi-channel signal synchronization circuit, including a clock signal generation module, a synchronization signal generation module, and a signal output port;
  • a first clock signal transmission branch and a synchronization signal transmission branch are provided between the clock signal generation module and the synchronization signal generation module, and the first clock signal transmission branch is configured to be generated by the clock signal generation module.
  • the first clock signal is transmitted to the synchronization signal generation module, and the synchronization signal transmission branch is configured to transmit the synchronization signal from the synchronization signal generation module to the clock signal generation module; the synchronization signal signal generation module Configured to generate the synchronization signal based on the received first clock signal;
  • a mixed signal transmission branch is provided between the clock signal generation module and the signal output port, and the mixed signal transmission branch is configured to transmit the second clock signal and the synchronization signal to the clock signal generation module.
  • the signal output port; the clock signal generation module is configured to generate the second clock signal based on the received synchronization signal.
  • the embodiment of the present application provides a multi-channel signal synchronization method, including:
  • the clock signal generation module generates a first clock signal and outputs the first clock signal to the synchronization signal generation module;
  • the synchronization signal generation module generates a synchronization signal based on the first clock signal, and transmits the synchronization signal to the clock signal generation module;
  • the clock signal generating module generates a second clock signal based on the synchronization signal and transmits the second clock signal to at least two signal receiving modules;
  • the synchronization signal generating module transmits the synchronization signal to the at least two signal receiving modules to achieve synchronization of the at least two signal receiving modules.
  • the embodiment of the present application provides a multi-channel signal synchronization method, including:
  • the clock signal generation module generates a first clock signal and outputs the first clock signal to the synchronization signal generation module;
  • the synchronization signal generation module generates a synchronization signal based on the first clock signal, and transmits the synchronization signal to the clock signal generation module;
  • the clock signal generating module generates a second clock signal based on the synchronization signal
  • the clock signal generating module transmits the synchronization signal and the second clock signal to at least two signal receiving modules to realize synchronization of the at least two signal receiving modules.
  • FIG. 1A is a schematic diagram of a multi-channel signal synchronization system according to an embodiment of this application;
  • FIG. 1B is a schematic diagram of a signal synchronization timing diagram according to an embodiment of this application.
  • FIG. 2 is a schematic diagram of a clock signal generation module according to an embodiment of the application.
  • 3A is a schematic diagram of a delay unit according to an embodiment of the application.
  • 3B is a schematic diagram of a delay unit according to an embodiment of this application.
  • 3C is a schematic diagram of a delay unit according to an embodiment of the application.
  • 4A is a schematic diagram of a multi-channel signal synchronization system according to an embodiment of this application.
  • 4B is a schematic diagram of a signal synchronization timing diagram according to an embodiment of this application.
  • FIG. 5 is a schematic diagram of a multi-channel signal synchronization circuit according to an embodiment of the application.
  • FIG. 6 is a flowchart of a method for synchronizing multi-channel signals according to an embodiment of this application.
  • FIG. 7 is a schematic diagram of a multi-channel signal synchronization system according to an embodiment of this application.
  • FIG. 8 is a schematic diagram of a multi-channel signal synchronization circuit according to an embodiment of the application.
  • FIG. 9 is a flowchart of a multi-channel signal synchronization method according to an embodiment of this application.
  • a multi-channel system refers to a system that needs to use a signal generation module to transmit corresponding signals to other modules through multiple channels.
  • a signal generation module For example, in a data sampling system, multiple analog-to-digital converters are often included to implement data sampling.
  • the clock signal is often the basis of a circuit that implements sequential logic, and it is generally necessary to transmit a corresponding clock signal to each channel.
  • the synchronization signal can be used to clear the count in the register of each module, so as to complete the synchronization of the modules corresponding to each channel in the system.
  • an embodiment of the present application proposes a multi-channel signal synchronization system.
  • the multi-channel signal synchronization system includes a clock signal generation module 110, a synchronization signal generation module 120, and at least two signal receiving modules.
  • FIG. 1A records the reference clock signal 101 and the second clock signals 111, 112, 113 to 11N, where N represents a positive integer greater than 1, for example, 11N may be 115. Also recorded are signal receiving modules 131, 132, 133 to 13N.
  • the clock signal generating module 110 can generate the first clock signal 103.
  • the first clock signal 103 is a clock signal having a specific clock cycle.
  • the clock signal generating module 110 can generate the first clock signal 103 by using an oscillator set by itself, for example.
  • the clock signal generating module 110 may receive the reference clock signal 101 as an input signal.
  • the reference clock signal 101 is a clock signal.
  • the clock signal generating module 110 may generate the first clock signal 103 according to the reference clock signal 101.
  • the clock signal generation module 110 may delay the reference clock signal 101 to generate the first clock signal 103, or adjust the clock period of the reference clock signal 101 to generate the first clock signal.
  • the clock signal 103 may receive the reference clock signal 101 as an input signal.
  • the reference clock signal 101 is a clock signal.
  • the clock signal generating module 110 may generate the first clock signal 103 according to the reference clock signal 101.
  • the clock signal generation module 110 may delay the reference clock signal 101 to generate the first clock signal 103, or adjust the clock period of the reference clock signal 101 to generate the first clock signal.
  • the clock signal 103 may be any suitable clock signal.
  • the reference clock signal 101 when the clock signal generation module 110 receives the reference clock signal 101 as an input signal, the reference clock signal 101 may be processed to obtain an intermediate clock signal.
  • the reference clock signal 101 may be frequency-divided to obtain an intermediate clock signal.
  • the first clock signal 103 can be obtained based on the intermediate clock signal.
  • the specific clock period of the first clock signal 103 may be determined based on the period of the intermediate clock signal. For example, it may be ensured that the frequency of the first clock signal 103 is an integer multiple of the intermediate clock signal, The specific clock period of the first clock signal 103 is determined. Based on this, it can be ensured that the signal edge of the synchronization signal 121 generated based on the first clock signal 103 is aligned with the signal edge of the intermediate clock signal, which facilitates data processing in subsequent steps.
  • the first clock signal transmission branch connected between the clock signal generation module 110 and the synchronization signal generation module 120 may be used to transfer the first clock signal A clock signal is transmitted to the synchronization signal generating module 120.
  • the synchronization signal generating module 120 may generate the synchronization signal 121 according to the first clock signal 103.
  • the synchronization signal 121 is a signal with a limited length of effective signal segment.
  • the synchronization signal 121 may be transmitted to each signal receiving module in the system, and when the synchronization signal 121 is a valid signal segment, synchronization of each signal receiving module is realized.
  • the count in the register in each signal receiving module may be cleared to zero, so as to realize synchronization of each signal receiving module.
  • the system resumes normal operation, and each signal receiving module performs corresponding work according to the clock signal.
  • the synchronization signal generating module 120 may generate the synchronization signal 121 according to the clock period of the first clock signal 103.
  • the clock period is the reciprocal of the signal frequency of the clock signal.
  • the clock period may also be the time from one rising edge to the next rising edge of the clock signal.
  • the synchronization signal generating module 120 may receive the reference synchronization signal 102. To facilitate data processing in subsequent steps, the synchronization signal generation module 120 may process the reference synchronization signal 102 based on the first clock signal to obtain the synchronization signal 121. In an embodiment, for example, the edge of the reference synchronization signal 102 may be aligned with the edge of the first clock signal to obtain the synchronization signal 121. In practical applications, the reference synchronization signal 102 may be aligned with the rising edge of the first clock signal, or the reference synchronization signal 102 may be aligned with the falling edge of the first clock signal 103.
  • the synchronization signal generating module 120 when the synchronization signal generating module 120 generates the synchronization signal 121 according to the clock period of the first clock signal 103, it may generate the synchronization signal 121 with a signal valid period greater than or equal to twice the clock period.
  • the signal valid duration is the duration of the corresponding signal segment when the synchronization signal 121 functions in the system. For example, when the synchronization signal 121 is active at a high level, it may be the duration of the high level of the synchronization signal 121.
  • the first synchronization signal transmission branch is connected between the synchronization signal generation module 120 and each signal receiving module, so that the synchronization signal generation module 120 can send the synchronization signal 121 based on the synchronization signal transmission first branch.
  • To each signal receiving module so as to realize the synchronization of the signal receiving module.
  • the synchronization signal transmission first branch and the first clock signal transmission branch are distinguished only by the function of each signal line.
  • the same signal line can be used to achieve
  • two signal lines may also be used to implement the transmission of the first clock signal and the synchronization signal 121.
  • the clock signal generation module 110 may generate a second clock signal based on the synchronization signal 121.
  • the manner in which the clock signal generation module 110 generates the second clock signal may be to generate an intermediate clock signal according to the received reference clock signal 101, and to generate the second clock signal according to the synchronization signal 121 and the intermediate clock signal. Signal.
  • the manner in which the clock signal generation module 110 generates the second clock signal according to the synchronization signal 121 and the intermediate clock signal may be to input the synchronization signal 121 and the intermediate clock signal into a gated clock
  • the unit gets the second clock signal.
  • the gated clock unit is configured to turn off the output of the intermediate clock signal according to the synchronization signal 121, and then obtain a clock signal whose low level duration is the high level duration of the synchronization signal 121 as the second clock signal.
  • the clock signal generation module 110 may delay the synchronization signal 121, and generate a second clock signal according to the delayed synchronization signal 121.
  • the synchronization signal may be delayed first, and then generated according to the delayed synchronization signal The second clock signal.
  • the synchronization signal may be delayed based on the edge of the next cycle of the first clock signal, and the delayed synchronization signal may be used to delay the first clock signal, so The edge of the next cycle of the first clock signal may be a rising edge or a falling edge.
  • the next cycle of the second clock signal refers to the time corresponding to the high-level start point of the synchronization signal 121, and the cycle in which the second clock signal is located is used as the second clock For the current cycle of the signal, the next cycle of the current cycle is taken as the next cycle of the second clock signal.
  • T100, T101, T102 to T111 represent different times.
  • the second clock signal 111 is a clock signal generated by the intermediate clock signal without time delay
  • the high-level starting point of the synchronization signal 121 exactly corresponds to the falling edge of the second clock signal 111
  • the second clock signal 111 is delayed so that the falling edge of the next cycle of the second clock signal 111 is
  • the length of the low level duration is equal to the time length of the high level duration T sync of the synchronization signal 121.
  • the time between the high-level end point of the second clock signal and the high-level end point of the synchronization signal 121 is taken as T3, and the high-level end point of the synchronization signal 121 and the second clock signal are in the synchronization
  • the start of the next rising edge after the end of the high level of the signal 121 is taken as T2.
  • the sum of the time lengths of T2 and T3 is the high-level duration T sync of the synchronization signal 121.
  • the high-level duration T sync is greater than or equal to two clock periods T
  • the lengths of T2 and T3 are both greater than or equal to the clock period T.
  • the synchronization signal 121 When the length of T3 is greater than or equal to the clock period, the synchronization signal 121 will not be interfered by a valid clock signal during the time period corresponding to T3, and the validity of the synchronization signal 121 is guaranteed, so that the synchronization signal 121 is The corresponding data can be correctly read into the register of the signal receiving module.
  • the length of T2 In the case that the length of T2 is greater than or equal to the clock period, it not only reserves sufficient setup time for the clock signal, but also ensures that the clock signal will not be in the high-level validity period after the synchronization signal 121 ends at a high level, thereby ensuring The synchronization of the signals in each signal receiving module avoids the situation that some signal receiving modules perform advance counting according to the clock signal.
  • the synchronization signal 121 and the intermediate clock signal 212 can be input to the delay unit 201 to delay the synchronization signal 121, and then the delayed synchronization signal 121 is input by the D type A gated clock circuit composed of flip-flop DFF202 and AND gate circuit AND203. After the intermediate clock signal passes through the clock signal generation module, a clock signal with a delay will be obtained, thereby realizing the synchronization signal 121 and the intermediate clock signal. 212 combines to obtain the second clock signal.
  • FIG. 3A is a specific embodiment corresponding to the delay unit in FIG. 2.
  • the delay unit is composed of a plurality of D-type flip-flops (DFF, delay flip-flop) to form a delay chain.
  • DFF D-type flip-flops
  • Each DFF can delay the synchronization signal 121 by one clock cycle.
  • a corresponding number of DFFs can be selected according to the delay requirement of the synchronization signal 121, so as to delay the synchronization signal 121 by a corresponding time.
  • CLK represents a clock interface
  • DFF301, DFF302, and DFF303 represent DFF
  • 313 represents a delayed synchronization signal
  • the input intermediate clock signal 212 can be replaced with a clock signal with a smaller clock period, so as to obtain a better delay effect.
  • FIG. 3B is another embodiment of a delay unit that delays the synchronization signal 121.
  • BUF321 is a signal driving circuit
  • BUF322 is a waveform shaping circuit.
  • the RC delay unit can be obtained by combining these two circuits with a resistor R323 and a capacitor C324. After passing the synchronization signal 121 through the RC delay unit, the synchronization signal 121 can be delayed. By adjusting the parameters of the resistance and capacitance, the delay time of the synchronization signal 121 can be adjusted accordingly, so as to meet the specific requirements for delaying the synchronization signal 121.
  • FIG. 3C is another embodiment of a delay unit that delays the synchronization signal 121.
  • the delay unit is composed of several buffers (BUF, buffer). Since each BUF has a fixed delay length, after multiple BUFs are connected in series, the corresponding time delay of the synchronization signal 121 can be realized.
  • BUF341, BUF342, and BUF34N all represent BUF, and N is a positive integer, for example, 345, 347, and so on.
  • All of the delay units introduced in the foregoing embodiments can delay the synchronization signal 121.
  • the clock signal generating module 110 may also generate the second clock signal according to the reference clock signal 101 and the synchronization signal 121.
  • the specific implementation process can refer to the above-mentioned process of generating the second clock signal by using the intermediate clock signal and the synchronization signal, which will not be repeated here.
  • An information line is connected between the clock signal generating module 110 and the signal receiving module, so that the clock signal generating module 110 can transmit the second clock signal to each signal receiving module through the information line. After the signal receiving module receives the second clock signal, it can realize the effective execution of the sequential circuit based on the second clock signal, thereby completing the corresponding data sampling work.
  • each signal receiving module may have different requirements for the clock signal.
  • there is also a certain delay between different second clock signals that is, different signal receiving modules may correspond to There are different delay lengths.
  • the clock signal generation module 110 after the clock signal generation module 110 generates the second clock signal, it can perform corresponding delay processing on the second clock signal transmitted to the different signal receiving module, which can be specifically based on the signal receiving module.
  • the corresponding delay length performs delay processing on the second clock signal.
  • the clock signal generating module 110 transmits the delayed second clock signal to each signal receiving module, so as to meet the different requirements of the signal receiving module for the clock signal.
  • the clock signal generation module 110 after the clock signal generation module 110 generates the second clock signal, it can directly transmit the second clock signal to the signal receiving module, and each signal receiving module delays the second clock signal. deal with.
  • the specific delay length can be determined according to the delay lengths corresponding to different signal receiving modules.
  • the second clock signal is delayed by the signal receiving module. It can be seen that the clock signal generating module 110 transmits the same second clock signal to each signal receiving module, and each signal receiving module delays the second clock signal by itself.
  • FIG. 4B it is a timing diagram between the second clock signal and the synchronization signal 121 in this embodiment.
  • the second clock signal and the synchronization signal 121 For the specific characteristics of the second clock signal and the synchronization signal 121, reference may be made to the introduction in the embodiment corresponding to FIG. 1B, and details are not described herein.
  • T400, T401, T402, and T411 represent different times.
  • the signal receiving module is a module that performs operations such as data sampling or data calculation based on a clock signal.
  • the signal receiving module may include an analog-to-digital converter.
  • the signal receiving module can clear the count corresponding to its own register. In the case of transmitting the synchronization signal 121 to each signal receiving module, synchronization of each signal receiving module can be realized.
  • the clock signal generation module 110 Based on the above-mentioned multi-channel signal synchronization system, after the synchronization signal 121 is generated, the clock signal generation module 110 generates a corresponding clock signal based on the synchronization signal 121, thereby ensuring that the synchronization signal 121 is not used to synchronize each signal receiving module. It will be interfered, and the normal operation of each signal receiving module after synchronization is also guaranteed. In addition, when a valid synchronization signal 121 is not generated, the second clock signal will not deviate, thereby ensuring that the signal receiving module can perform normal operation according to the second clock signal in a normal working state. Therefore, the above-mentioned multi-channel signal synchronization system realizes the convenient and effective synchronization of the signal receiving modules in the system.
  • the multi-channel signal synchronization circuit includes a clock signal generation module 110, a synchronization signal generation module 120 and a signal output port.
  • 531, 532, 533, and 53N all represent signal output ports, and N is a positive integer, for example, 534, 535, etc.
  • the clock signal generation module 110 the synchronization signal generation module 120, and the signal output port
  • the clock signal generating module can generate the first clock signal 103.
  • a first clock signal transmission branch may be provided between the clock signal generation module 110 and the synchronization signal generation module 120, so that the clock signal generation module 110 can transmit the first clock signal 103 to the synchronization signal generation module. Module 120.
  • a synchronization signal transmission first branch may also be provided between the clock signal generation module 110 and the synchronization signal generation module 120, so that the synchronization signal generation module 120 transmits the synchronization signal 121 to the clock signal generation module 110 .
  • the process of generating the synchronization signal 121 reference may be made to the introduction of the process of generating the synchronization signal 121 in the embodiment corresponding to FIG. 1A, which will not be repeated here.
  • the synchronization signal transmission first branch and the first clock signal transmission branch are only distinguished from a functional point of view. In practical applications, the synchronization signal transmission first branch and the first clock signal transmission branch are distinguished from each other.
  • the first clock signal transmission branch may be the same signal line or different signal lines.
  • the clock signal generation module 110 may generate a second clock signal based on the synchronization signal 121.
  • the manner in which the clock signal generation module 110 generates the second clock signal may be to generate an intermediate clock signal according to the received reference clock signal 101, and to generate the second clock signal according to the synchronization signal 121 and the intermediate clock signal. Signal.
  • a second clock signal transmission branch may be provided between the clock signal generation module 110 and the signal output port, so that the clock signal generation module 110 transmits the second clock signal to the signal output port.
  • a second synchronization signal transmission branch may also be provided between the synchronization signal generation module 120 and the signal output port, so that the synchronization signal generation module 120 transmits the synchronization signal 121 to the signal output port.
  • the signal output port can transmit the second clock signal and the synchronization signal 121 to a module connected to the signal output port outside the circuit.
  • the second clock signal can be transmitted to the analog-to-digital converter to realize the normal data sampling operation of the analog-to-digital converter; it can also be output through the signal
  • the port transmits the synchronization signal 121 to the analog-to-digital converter so that the analog-to-digital converters corresponding to different signal output ports can be synchronized.
  • any module that works based on a clock signal and needs to be synchronized can be connected to the signal output port.
  • the multi-channel signal synchronization method may include the following steps.
  • the clock signal generation module generates a first clock signal and outputs it to the synchronization signal generation module.
  • the synchronization signal generation module generates a synchronization signal based on the first clock signal, and transmits the synchronization signal to the clock signal generation module.
  • the synchronization signal generation module 120 For the introduction of the synchronization signal generation module 120 and the process of generating and transmitting the synchronization signal 121, please refer to the description of the synchronization signal generation module 120 and the synchronization signal 121 in the embodiment corresponding to FIG. 1A, which will not be described here. Go into details.
  • the clock signal generating module generates a second clock signal according to the synchronization signal and transmits the second clock signal to the signal receiving module.
  • a synchronization signal transmission line is connected between the clock signal generating module and the signal receiving module, so that the clock signal generating module can transmit the second clock signal to each signal receiving module through the synchronization signal transmission line.
  • the signal receiving module After the signal receiving module receives the second clock signal, it can realize the effective execution of the sequential circuit based on the second clock signal, thereby completing the corresponding data sampling work.
  • the clock signal generation module after the clock signal generation module generates the second clock signal, it can directly transmit the second clock signal to the signal receiving module, and each signal receiving module delays the second clock signal. deal with.
  • the specific delay length can be determined according to the delay lengths corresponding to different signal receiving modules.
  • FIG. 4A it is a specific example of using the signal receiving module to delay processing the second clock signal. It can be seen that the signal transmitted by the clock signal generating module to each signal receiving module is the same second clock signal, and each signal receiving module delays the second clock signal by itself.
  • the synchronization signal generating module transmits the synchronization signal to the signal receiving module to achieve synchronization of the signal receiving module.
  • step S630 and step S640 can be reversed, or can be executed simultaneously.
  • the second clock signal can be transmitted to the signal receiving module by the clock signal generation module, and then the synchronization signal can be transmitted to the signal receiving module by the synchronization signal generation module, or the synchronization signal can be transmitted by the synchronization signal generation module first.
  • the second clock signal is transmitted to the signal receiving module, and then the second clock signal is transmitted to the signal receiving module by the clock signal generating module.
  • the clock signal transmitted to the signal receiving module will be adjusted based on the synchronization signal , So that the synchronization signal can be transmitted to the signal receiving module without being interfered by the clock signal when the synchronization signal is active at high level.
  • the timing margin of the adjusted clock signal at the end of synchronization can also meet the clock signal
  • the signal receiving module can respond normally, which ensures the effectiveness and accuracy of the synchronization of the signal receiving module.
  • the multi-channel signal synchronization system includes a clock signal generation module 110, a synchronization signal generation module 120, and at least two signal receiving modules.
  • the clock signal generation module 110 the synchronization signal generation module 120, and the signal output port
  • the clock signal generation module 110 can generate the first clock signal 103 and transmit the first clock signal to the synchronization signal generation module 120.
  • the synchronization signal generation module 120 may generate a synchronization signal 121 and transmit the synchronization signal 121 to the clock signal generation module.
  • the clock signal generating module may generate the second clock signal 111 after receiving the synchronization signal 121.
  • the synchronization signal transmission line is not connected between the synchronization signal generating module 120 and the signal receiving module, but the synchronization signal 121 is directly transmitted to each signal receiving module through the clock signal generating module 110.
  • the mixed signal transmission branch 812 may be directly used to transmit the synchronization signal 121 and the second clock signal 111.
  • the clock signal generation module 110 may be used to composite the second clock signal 111 and the synchronization signal 121 based on a preset rule.
  • the second clock signal 111 and the synchronization signal 121 have different clock periods.
  • the signal receiving module receives the composite signal, it can distinguish the second clock signal 111 and the synchronization signal 121 from the composite signal based on a preset rule.
  • the combined signal will exhibit the characteristics of aperiodic signals at the rising and falling edges corresponding to the synchronization signal 121 , So that the effective signal segment of the synchronization signal 121 can be determined.
  • the synchronization signal line connected between the synchronization signal generation module and each signal receiving module is eliminated, and the clock signal generation module is directly used to realize the transmission of the clock signal and the synchronization signal by using the same signal line, which simplifies the system The difficulty of design.
  • the multi-channel signal synchronization circuit includes a clock signal generation module 110, a synchronization signal generation module 120 and a signal output port.
  • FIG. 8 there are also a clock signal input port 801 and a synchronization signal input port 802.
  • the synchronization signal generating module 120 when the synchronization signal generating module 120 generates a synchronization signal according to the clock period of the first clock signal, it may generate a synchronization signal with a signal valid period of greater than or equal to twice the clock period.
  • the signal valid duration is the duration of the corresponding signal segment when the synchronization signal acts in the system. For example, when the synchronization signal is active at a high level, it may be the duration of the high level of the synchronization signal.
  • a synchronization signal transmission branch may also be provided between the clock signal generation module 110 and the synchronization signal generation module 120.
  • This synchronization signal transmission branch may also be recorded as a synchronization signal transmission third branch 821, so that the The synchronization signal generation module 120 transmits the synchronization signal to the clock signal generation module 110.
  • the synchronization signal transmission third branch 821 and the first clock signal transmission branch 811 are only distinguished from a functional point of view. In practical applications, the synchronization signal transmission third branch 821 and the first clock signal transmission branch 811 are distinguished from each other.
  • the clock signal transmission branch 811 may be the same signal line or different signal lines.
  • the clock signal generation module 110 may generate a second clock signal based on the synchronization signal.
  • the clock signal generation module 110 generates the second clock signal by generating an intermediate clock signal according to the received reference clock signal, and generating the second clock signal according to the synchronization signal and the intermediate clock signal.
  • a mixed signal transmission branch 812 may be provided between the clock signal generation module 110 and the signal output port, so that the clock signal generation module 110 transmits the second clock signal and the synchronization signal to the signal output port .
  • the signal output port can transmit the second clock signal and the synchronization signal to a module connected to the signal output port outside the circuit.
  • the second clock signal may be transmitted to the analog-to-digital converter to realize the normal data sampling operation of the analog-to-digital converter; or the signal output
  • the port transmits the synchronization signal to the analog-to-digital converter so that the analog-to-digital converters corresponding to different signal output ports can be synchronized.
  • any module that works based on a clock signal and needs to be synchronized can be connected to the signal output port.
  • the multi-channel signal synchronization method may include the following steps.
  • the clock signal generation module generates a first clock signal and outputs it to the synchronization signal generation module.
  • the synchronization signal generation module generates a synchronization signal based on the first clock signal, and transmits the synchronization signal to the clock signal generation module.
  • the synchronization signal generation module 120 For the introduction of the synchronization signal generation module 120 and the process of generating and transmitting the synchronization signal 121, please refer to the description of the synchronization signal generation module 120 and the synchronization signal 121 in the embodiment corresponding to FIG. 7, which will not be described here. Go into details.
  • the clock signal generating module generates a second clock signal according to the synchronization signal.
  • a synchronization signal transmission line is connected between the clock signal generating module and the signal receiving module, so that the clock signal generating module can transmit the second clock signal to each signal receiving module through the synchronization signal transmission line.
  • the signal receiving module After the signal receiving module receives the second clock signal, it can realize the effective execution of the sequential circuit based on the second clock signal, thereby completing the corresponding data sampling work.
  • the clock signal generation module after the clock signal generation module generates the second clock signal, it can directly transmit the second clock signal to the signal receiving module, and each signal receiving module delays the second clock signal. deal with.
  • the specific delay length can be determined according to the delay lengths corresponding to different signal receiving modules.
  • the clock signal generating module transmits the synchronization signal and the second clock signal to the signal receiving module to realize synchronization of the signal receiving module.
  • the clock signal generating module can directly transmit the previously received synchronization signal to the signal receiving module.
  • the synchronization signal generating module does not need to transmit the synchronization signal to the signal receiving module, and there is no need for the synchronization signal generating module and the signal receiving module.
  • the same mixed signal transmission branch may be directly used to transmit the synchronization signal and the second clock signal.
  • the second transmission branch of the synchronization signal connected between the synchronization signal generation module and each signal receiving module is eliminated, and the clock signal generation module is directly used to realize the clock signal and the synchronization signal using the mixed signal transmission branch.
  • the transmission simplifies the difficulty of system design.
  • the signal receiving module includes an analog-to-digital converter.
  • the clock signal generating module is configured to generate the first clock signal according to the received reference clock signal.
  • the first clock signal corresponds to a clock period; the signal valid duration of the synchronization signal is greater than or equal to twice the clock period.
  • the clock signal generation module is configured to generate an intermediate clock signal according to the received reference clock signal, and generate a second clock signal according to the intermediate clock signal and the synchronization signal.
  • the clock signal generation module is configured to input the synchronization signal and the intermediate clock signal into a gated clock unit to obtain a second clock signal.
  • the clock signal generation module is configured to delay the synchronization signal, and generate a second clock signal according to the delayed synchronization signal and the intermediate clock signal.
  • the clock signal generation module uses the first clock signal to delay the synchronization signal
  • the clock signal generation module uses a resistance-capacitance delay unit to delay the synchronization signal
  • the clock signal generation module uses a buffer to delay the synchronization signal.
  • the synchronization signal generation module is configured to generate a synchronization signal based on the first clock signal and the received reference synchronization signal.
  • the signal receiving module corresponds to a designated delay length
  • the clock signal generation module is configured to, after generating the second clock signal, perform delay processing on the second clock signal corresponding to the delay length of the signal receiving module, and transmit the delayed second clock signal to The signal receiving module.
  • the signal receiving module corresponds to a designated delay length
  • the clock signal generating module is configured to respectively transmit the second clock signal to the signal receiving module after generating the second clock signal;
  • the signal receiving module is configured to perform delay processing of a corresponding delay length on the received second clock signal.
  • the first clock signal transmission branch and the synchronization signal transmission first branch are the same branch.
  • the clock signal transmitted to the signal receiving module will be adjusted based on the synchronization signal, This enables the synchronization signal to be transmitted to the signal receiving module without being interfered by the clock signal when it is active at high level. Accordingly, after the clock signal is adjusted, the timing margin at the end of the synchronization can also be satisfied. Set up time requirements, so as to be able to respond normally in the signal receiving module.
  • the use of mixed-signal transmission branches to realize the transmission of clock signals and synchronization signals at the same time also reduces the number of lines in the design and reduces the design difficulty. Therefore, the multi-channel signal synchronization system, circuit and method conveniently and accurately realize the synchronization of the signal receiving module in the multi-channel system.
  • the multi-channel signal synchronization system introduced in the embodiments of the present application generates the second clock signal according to the synchronization signal, so that there is a gap between the second clock signal and the synchronization signal.
  • the signal receiving module is synchronized by the synchronization signal
  • the second clock signal received by the signal receiving module will not cause interference to the synchronization signal.
  • the clock signals in each channel can also take effect normally Therefore, the correct operation of the signal receiving module is ensured, the difficulty of signal synchronization for the multi-channel system is reduced, and the multi-channel signal synchronization is conveniently and effectively realized.

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Abstract

本申请实施例提供一种多通道信号同步系统、电路及方法。多通道信号同步系统包括时钟信号产生模块、同步信号产生模块和信号接收模块；时钟信号产生模块设置为生成第一时钟信号；同步信号产生模块设置为基于第一时钟信号生成同步信号，并将同步信号传输至时钟信号产生模块；时钟信号产生模块基于同步信号生成第二时钟信号，并将第二时钟信号传输至信号接收模块；同步信号产生模块将同步信号传输至信号接收模块。

Description

多通道信号同步系统、电路及方法
本公开要求在2020年04月21日提交中国专利局、申请号为202010315258.6的中国专利申请的优先权，以上申请的全部内容通过引用结合在本公开中。
技术领域
本申请实施例涉及信号技术领域，例如涉及一种多通道信号同步系统、电路及方法。
背景技术
在通信领域中，时钟信号是具有时序逻辑的电路执行相应操作的基础。在一些多通道系统中，需要传输时钟信号至系统中多个通道所对应的元件，使得多通道系统能够基于对应的时钟信号实现系统所对应的工作。例如，可以生成时钟信号并输出至每个通道所对应的模数转换器，以实现数据的采集。相应的，为了保证上述系统的正常工作，还需要利用同步信号对不同通道中对应于时钟信号的计数进行同步。但是，同步操作可能失败。
发明内容
本申请实施例的目的是提供一种多通道信号同步系统、电路及方法，以解决如何方便有效地实现多通道系统中的信号同步的问题。
本申请实施例提供一种多通道信号同步系统，包括时钟信号产生模块、同步信号产生模块和至少两个信号接收模块；
所述时钟信号产生模块设置为生成第一时钟信号并将所述第一时钟信号传输至所述同步信号产生模块；
所述同步信号产生模块设置为基于所述时钟信号产生模块输出的所述第一时钟信号生成同步信号，并将所述同步信号传输至所述时钟信号产生模块；
所述时钟信号产生模块还设置为基于所述同步信号产生模块反馈的所述同步信号生成第二时钟信号，并将所述第二时钟信号传输至所述至少两个信号接收模块；
所述同步信号产生模块还设置为将所述同步信号传输至所述至少两个信号接收模块。
本申请实施例提供一种多通道信号同步系统，包括时钟信号产生模块、同步信号产生模块和至少两个信号接收模块；
所述时钟信号产生模块设置为生成第一时钟信号并将所述第一时钟信号传输至所述同步信号产生模块；
所述同步信号产生模块设置为基于所述时钟信号产生模块输出的所述第一时钟信号生成同步信号，并将所述同步信号传输至所述时钟信号产生模块；
所述时钟信号产生模块还设置为基于所述同步信号产生模块反馈的同步信号生成第二时钟信号，并将所述同步信号和所述第二时钟信号传输至所述至少两个信号接收模块。
本申请实施例提供一种多通道信号同步电路，包括时钟信号产生模块、同步信号产生模块和信号输出端口；
所述时钟信号产生模块与所述同步信号产生模块之间设置有第一时钟信号传输支路和同步信号传输第一支路，所述第一时钟信号传输支路被设置为由所述时钟信号产生模块传输第一时钟信号至所述同步信号产生模块，以及，所述同步信号传输第一支路被设置为由所述同步信号产生模块传输同步信号至所述时钟信号产生模块；所述同步信号产生模块设置为基于接收到的第一时钟信号生成所述同步信号；
所述时钟信号产生模块与所述信号输出端口之间设置有第二时钟信号传输支路，所述第二时钟信号传输支路被设置为由所述时钟信号产生模块传输第二时钟信号至所述信号输出端口；所述时钟信号产生模块设置为基于接收到的所述同步信号和所述第一时钟信号生成所述第二时钟信号；
所述同步信号产生模块与所述信号输出端口之间设置有同步信号传输第二支路，所述同步信号传输第二支路被设置为由所述同步信号产生模块传输所述同步信号至所述信号输出端口。
本申请实施例提供一种多通道信号同步电路，包括时钟信号产生模块、同步信号产生模块和信号输出端口；
所述时钟信号产生模块与所述同步信号产生模块之间设置有第一时钟信号传输支路和同步信号传输支路，所述第一时钟信号传输支路被设置为由所述时钟信号产生模块传输第一时钟信号至所述同步信号产生模块，以及，所述同步信号传输支路被设置为由所述同步信号产生模块传输同步信号至所述时钟信号产生模块；所述同步信号信号产生模块设置为基于接收到的所述第一时钟信号生成所述同步信号；
所述时钟信号产生模块与所述信号输出端口之间设置有混合信号传输支路，所述混合信号传输支路被配置为由所述时钟信号产生模块传输第二时钟信 号和所述同步信号至所述信号输出端口；所述时钟信号产生模块设置为基于接收到的所述同步信号生成所述第二时钟信号。
本申请实施例提供一种多通道信号同步方法，包括：
时钟信号产生模块生成第一时钟信号并将所述第一时钟信号输出至同步信号产生模块；
所述同步信号产生模块基于所述第一时钟信号生成同步信号，并将所述同步信号传输至所述时钟信号产生模块；
所述时钟信号产生模块基于所述同步信号生成第二时钟信号并将所述第二时钟信号传输至至少两个信号接收模块；
所述同步信号产生模块将所述同步信号传输至所述至少两个信号接收模块，以实现所述至少两个信号接收模块的同步。
本申请实施例提供一种多通道信号同步方法，包括：
时钟信号产生模块生成第一时钟信号并将所述第一时钟信号输出至同步信号产生模块；
所述同步信号产生模块基于所述第一时钟信号生成同步信号，并将所述同步信号传输至所述时钟信号产生模块；
所述时钟信号产生模块基于所述同步信号生成第二时钟信号；
所述时钟信号产生模块将所述同步信号和所述第二时钟信号传输至至少两个信号接收模块，以实现所述至少两个信号接收模块的同步。
附图说明
为了说明本申请实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍。
图1A为本申请实施例一种多通道信号同步系统的示意图；
图1B为本申请实施例一种信号同步时序图的示意图；
图2为本申请实施例一种时钟信号产生模块的示意图；
图3A为本申请实施例一种延时单元的示意图；
图3B为本申请实施例一种延时单元的示意图；
图3C为本申请实施例一种延时单元的示意图；
图4A为本申请实施例一种多通道信号同步系统的示意图；
图4B为本申请实施例一种信号同步时序图的示意图；
图5为本申请实施例一种多通道信号同步电路的示意图；
图6为本申请实施例一种多通道信号同步方法的流程图；
图7为本申请实施例一种多通道信号同步系统的示意图；
图8为本申请实施例一种多通道信号同步电路的示意图；
图9为本申请实施例一种多通道信号同步方法的流程图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。
在相关技术中，由于系统中的不同通道接收到的时钟信号可能存在不同的时延，在输入同步信号时，同步信号可能不能满足部分时钟信号的对于建立时间和保持时间的要求，从而导致同步失败。因此，亟需一种方便有效地对多通道系统进行同步的手段。
多通道系统指需要利用信号产生模块通过多个通道分别传输相应的信号至其他模块的系统。例如，在数据采样系统中，往往包含有多个模数转换器设置为实现数据采样。而时钟信号往往是实现时序逻辑的电路的基础，一般需要向每个通道传输相应的时钟信号。相应的，为了保证上述系统中每个通道所对应的模块的正常工作，还需要利用同步信号对不同模块中对应于时钟信号的计数进行同步。例如，可以是利用同步信号对各个模块的寄存器中的计数进行清零，从而完成系统中各个通道所对应的模块的同步。
如图1A所示，本申请实施例提出一种多通道信号同步系统。所述多通道信号同步系统包括时钟信号产生模块110、同步信号产生模块120和至少两个信号接收模块。
在一实施例中，图1A中记录有，参考时钟信号101，第二时钟信号111、112、113至11N，N表示大于1的正整数，例如，11N可为115。还记录有，信号接收模块131、132、133至13N。
所述时钟信号产生模块110可以生成第一时钟信号103。所述第一时钟信号103为具有特定时钟周期的时钟信号。所述时钟信号产生模块110例如可以利用自身所设置的振荡器来产生第一时钟信号103。
在一些实施方式中，所述时钟信号产生模块110可以接收参考时钟信号101作为输入信号。参考时钟信号101为一个时钟信号。所述时钟信号产生模块110可以根据所述参考时钟信号101生成第一时钟信号103。在一实施例中，所述时钟信号产生模块110可以是将所述参考时钟信号101进行延时处理生成第一时 钟信号103，也可以是调整所述参考时钟信号101的时钟周期进而生成第一时钟信号103。
在一些实施方式中，在所述时钟信号产生模块110接收参考时钟信号101作为输入信号时，可以对所述参考时钟信号101进行处理得到中间时钟信号。在一实施例中，例如可以是对所述参考时钟信号101进行分频得到中间时钟信号。在获取到中间时钟信号后，可以基于所述中间时钟信号得到第一时钟信号103。所述第一时钟信号103的特定时钟周期可以基于所述中间时钟信号的周期进行确定，例如，可以在保证所述第一时钟信号103的频率是所述中间时钟信号的整数倍的情况下，确定所述第一时钟信号103的特定时钟周期。基于此，能够保证基于所述第一时钟信号103生成的同步信号121的信号沿与所述中间时钟信号的信号沿对齐，便于后续步骤中的数据处理。
所述时钟信号产生模块110在生成第一时钟信号103之后，可以通过所述时钟信号产生模块110和所述同步信号产生模块120之间所连接的第一时钟信号传输支路，将所述第一时钟信号传输至所述同步信号产生模块120。
所述同步信号产生模块120在接收到所述第一时钟信号103后，可以根据所述第一时钟信号103来生成同步信号121。所述同步信号121，是具有有限长度的有效信号段的信号。所述同步信号121可以传输至系统中的各个信号接收模块，并在所述同步信号121为有效信号段时，实现对各个信号接收模块的同步。在一实施例中，例如可以是在基于所述同步信号121输入有效信号后将各个信号接收模块中的寄存器中的计数清零，从而实现各个信号接收模块的同步。在所述同步信号121的有效信号段经过后，系统恢复正常工作，各个信号接收模块再根据时钟信号执行相应的工作。
在一实施例中，所述同步信号产生模块120可以根据所述第一时钟信号103的时钟周期来生成同步信号121。时钟周期是时钟信号的信号频率的倒数，在一实施例中，所述时钟周期还可以是时钟信号的一个上升沿到下一个上升沿的时间。
在一实施例中，所述同步信号产生模块120可以接收到参考同步信号102。为了方便后续步骤中的数据处理，所述同步信号产生模块120可以基于第一时钟信号对所述参考同步信号102进行处理得到同步信号121。在一实施例中，例如可以是将所述参考同步信号102的边沿与所述第一时钟信号的边沿对齐得到同步信号121。实际应用中可以是将参考同步信号102与所述第一时钟信号的上升沿对齐，也可以是将参考同步信号102与所述第一时钟信号103的下降沿对 齐。
在一实施例中，在所述同步信号产生模块120根据所述第一时钟信号103的时钟周期生成同步信号121时，可以是生成信号有效时长大于或等于两倍的时钟周期的同步信号121。所述信号有效时长为所述同步信号121在系统中起作用时对应的信号段的持续时长。例如，当所述同步信号121为高电平有效时，可以是所述同步信号121的高电平所持续的时长。
所述同步信号产生模块120与各个信号接收模块之间连接有同步信号传输第一支路，使得所述同步信号产生模块120能够基于所述同步信号传输第一支路将所述同步信号121发送至各个信号接收模块中，从而实现信号接收模块的同步。
图1A所对应的系统中只是通过各个信号线所起的功能对所述同步信号传输第一支路和所述第一时钟信号传输支路进行区分，实际应用中可以使用同一个信号线来实现第一时钟信号和同步信号121的传输，也可以使用两根信号线来实现第一时钟信号和同步信号121的传输。
所述时钟信号产生模块110在接收到所述同步信号121后，可以基于所述同步信号121生成第二时钟信号。
在一实施例中，时钟信号产生模块110生成第二时钟信号的方式可以是根据接收到的参考时钟信号101生成中间时钟信号，并根据所述同步信号121和所述中间时钟信号生成第二时钟信号。
在一实施例中，所述时钟信号产生模块110根据所述同步信号121和所述中间时钟信号生成第二时钟信号的方式可以是将所述同步信号121和所述中间时钟信号输入门控时钟单元得到第二时钟信号。所述门控时钟单元设置为根据同步信号121关闭中间时钟信号的输出，进而得到一段低电平时长为所述同步信号121的高电平时长的时钟信号，作为第二时钟信号。
在一实施例中，时钟信号产生模块110可以对所述同步信号121进行延时，并根据所述延时后的同步信号121生成第二时钟信号。
实际应用中，为了不影响生成的第二时钟信号的正常波形，在利用同步信号生成第二时钟信号之前，可以先将所述同步信号进行延时，再根据所述延时后的同步信号生成第二时钟信号。在一实施例中，可以基于所述第一时钟信号的下一周期的边沿对所述同步信号进行延时，再将利用延时后的同步信号对所述第一时钟信号进行延时，所述第一时钟信号的下一周期的边沿可以是上升沿，也可以是下降沿。
在一实施例中，所述第二时钟信号的下一周期，指的是在同步信号121的高电平起点对应的时刻，将所述第二时钟信号所处的周期作为所述第二时钟信号的当前周期，将所述当前周期的下一个周期作为所述第二时钟信号的下一周期。
结合附图1B对上述生成第二时钟信号的过程进行解释。在一实施例中，在附图1B中，T100、T101、T102至T111表示不同的时刻。
假设所述第二时钟信号111为中间时钟信号未做时延而所生成的时钟信号，可以看出，所述同步信号121的高电平起点正好对应于所述第二时钟信号111的下降沿，则在所述第二时钟信号111的下一个下降沿的终点，将所述第二时钟信号111延时，使所述第二时钟信号111的下一周期的下降沿至下一上升沿的低电平持续时间的长度等同于所述同步信号121的高电平持续时间T sync的时间长度。
基于附图1B，将第二时钟信号的高电平结束点与同步信号121高电平结束点之间的时间作为T3，将同步信号121高电平结束点与第二时钟信号在所述同步信号121高电平结束点后的下一个上升沿起点作为T2。T2和T3的时间长度之和即为所述同步信号121的高电平持续时间T sync。在所述高电平持续时间T sync大于或等于两个时钟周期T的情况下，使得T2和T3的长度均大于或等于时钟周期T。在T3的长度大于或等于时钟周期的情况下，使得所述同步信号121在T3对应的时间段内不会存在有效的时钟信号的干扰，保证了同步信号121的有效性，使得同步信号121所对应的数据能够正确读入信号接收模块的寄存器中。在T2的长度大于或等于时钟周期的情况下，不仅为时钟信号预留了充足的建立时间，也能够保证在同步信号121结束高电平后，时钟信号不会处于高电平有效期，从而保证了对各个信号接收模块中的信号的同步，避免了部分信号接收模块根据时钟信号进行提前计数的情况。
下面结合图2对所述时钟信号产生模块的一个实施方式进行介绍。在所述时钟信号产生模块中，首先可以将所述同步信号121和中间时钟信号212输入延迟单元201实现对所述同步信号121的延时，再将延时后的同步信号121输入由D类型触发器DFF202和与门电路AND203共同组成的门控时钟电路，中间时钟信号在通过该时钟信号产生模块之后，会得到存在一段延时的时钟信号，从而将实现所述同步信号121与中间时钟信号212进行结合得到第二时钟信号。
图3A是对应于图2中的延时单元的一个具体的实施方式。所述延时单元由多个D类触发器(DFF，delay flip-flop)组成了一个延时链。每个DFF能够将 同步信号121延时一个时钟周期。根据对所述同步信号121的延时需求可以选择相应数量的DFF，从而将所述同步信号121延时相应的时间。
在一实施例中，图3A中，CLK表示时钟接口，DFF301、DFF302及DFF303表示DFF，313表示延时后的同步信号。
为了获取对同步信号121更为精确的延时操作，可以将输入的中间时钟信号212替换为时钟周期较小的时钟信号，从而获取更好的延时效果。
图3B是另一种对同步信号121进行延时的延时单元的实施方式。在该实施方式中，其中，BUF321为信号驱动电路，BUF322为波形整形电路，将这两个电路与电阻R323和电容C324进行组成可以获取RC延迟单元。将同步信号121通过所述RC延迟单元后，可以对所述同步信号121进行延时处理。通过调整电阻和电容的参数，可以对同步信号121的延时时长进行相应的调整，从而满足具体的对同步信号121进行延时的要求。
图3C是另一种对同步信号121进行延时的延时单元的实施方式。所述延时单元由若干个缓冲器(BUF，buffer)组成。由于各个BUF具有固定的延时长度，串联多个BUF后可以实现对所述同步信号121的相应时长的延时。
在一实施例中，图3C中，BUF341、BUF342及BUF34N均表示BUF，N为正整数，例如，345、347等。
上述实施方式中所介绍的延时单元均可对同步信号121进行延时。
在另一实施方式中，所述时钟信号产生模块110也可以根据参考时钟信号101和同步信号121来生成第二时钟信号。具体的实现过程可以参考上述利用中间时钟信号和同步信号来生成第二时钟信号的过程，在此不做赘述。
所述时钟信号产生模块110与信号接收模块之间连接有信息线，使得所述时钟信号产生模块110能够通过所述信息线将第二时钟信号传输至各个信号接收模块中。所述信号接收模块在接收到所述第二时钟信号后，能够基于所述第二时钟信号实现时序电路的有效进行，从而完成相应的数据采样工作。
实际应用中，各个信号接收模块中可能对时钟信号存在不同的需求，如图1B所示，不同的第二时钟信号之间也存在有一定的延时，即，不同的信号接收模块可能会对应有不同的延时长度。在这种情况下，所述时钟信号产生模块110在生成第二时钟信号之后，可以对传输至不同信号接收模块的第二时钟信号进行对应的延时处理，具体的可以是根据信号接收模块所对应的延时长度对第二时钟信号进行延时处理。相应的，时钟信号产生模块110将延时后的第二时钟信号传输至各个信号接收模块，从而满足信号接收模块对时钟信号的不同需求。
在一实施例中，所述时钟信号产生模块110在生成第二时钟信号后，可以直接将所述第二时钟信号分别传输至信号接收模块，由各个信号接收模块对第二时钟信号进行延时处理。具体的延时长度可以根据不同的信号接收模块所对应的延时长度而确定。
如图4A所示，通过信号接收模块对第二时钟信号进行延时处理。可以看出，时钟信号产生模块110传输至各个信号接收模块的为相同的第二时钟信号，由各个信号接收模块自行对第二时钟信号进行延时。
如图4B所示，为在该实施方式中第二时钟信号与同步信号121之间的时序图。具体的第二时钟信号与同步信号121的特征可以参照附图1B所对应的实施方式中的介绍，在此不做赘述。
在一实施例中，图4B中，T400、T401、T402及T411表示不同的时刻。
所述信号接收模块是基于时钟信号进行数据采样或数据运算等操作的模块。例如，所述信号接收模块可以包括模数转换器。所述信号接收模块在接收到所述同步信号121后，可以对自身寄存器所对应的计数进行清零。在传输同步信号121至各个信号接收模块的情况下，可以实现各个信号接收模块的同步。
基于上述多通道信号同步系统，使得生成同步信号121后，时钟信号产生模块110会基于所述同步信号121生成相应的时钟信号，从而保证了在利用同步信号121对各个信号接收模块进行同步时不会受到干扰，也保证了同步后各个信号接收模块的正常工作。此外，在未产生有效的同步信号121的情况下，第二时钟信号也不会出现偏差，从而保证了正常工作状态下信号接收模块能够根据所述第二时钟信号进行正常的工作。因此，上述多通道信号同步系统实现了方便有效地对系统中的信号接收模块进行同步。
基于上述多通道信号同步系统，如图5所示，介绍本申请实施例一种多通道信号同步电路。所述多通道信号同步电路包括时钟信号产生模块110、同步信号产生模块120和信号输出端口。
在一实施例中，图5中，531、532、533及53N均表示信号输出端口，N为正整数，例如，534、535等。
对于所述时钟信号产生模块110、同步信号产生模块120和信号输出端口的介绍可以参照图1A所对应的实施例中对于时钟信号产生模块110、同步信号产生模块120和信号接收模块的介绍，在此不做赘述。
所述时钟信号产生模块可以生成第一时钟信号103。所述时钟信号产生模块110与所述同步信号产生模块120之间可以设置有第一时钟信号传输支路，以使 所述时钟信号产生模块110能够传输第一时钟信号103至所述同步信号产生模块120。
所述第一时钟信号103的产生的过程可以参照图1A所对应的实施例中对于生成第一时钟信号103的介绍，在此也不做赘述。
所述时钟信号产生模块110与所述同步信号产生模块120之间还可以设置有同步信号传输第一支路，以使所述同步信号产生模块120传输同步信号121至所述时钟信号产生模块110。所述同步信号121的产生过程可以参照图1A所对应的实施例中生成同步信号121的过程的介绍，在此也不做赘述。
在一实施例中，所述同步信号传输第一支路和所述第一时钟信号传输支路只是从功能性的角度上进行区分，实际应用中，所述同步信号传输第一支路和所述第一时钟信号传输支路可以是同一根信号线，也可以是不同的信号线。
所述时钟信号产生模块110在接收到所述同步信号121后，可以基于所述同步信号121生成第二时钟信号。
在一实施例中，时钟信号产生模块110生成第二时钟信号的方式可以是根据接收到的参考时钟信号101生成中间时钟信号，并根据所述同步信号121和所述中间时钟信号生成第二时钟信号。
生成第二时钟信号的过程可以参照图1A对应的实施例中对于生成第二时钟信号的过程的介绍，在此不做赘述。
所述时钟信号产生模块110与所述信号输出端口之间可以设置有第二时钟信号传输支路，以使所述时钟信号产生模块110传输第二时钟信号至所述信号输出端口。
所述同步信号产生模块120与所述信号输出端口之间还可以设置有同步信号传输第二支路，以使所述同步信号产生模块120传输同步信号121至所述信号输出端口。
所述信号输出端口，可以将所述第二时钟信号和所述同步信号121传输至电路外与所述信号输出端口相连接的模块。例如，在所述信号输出端口与模数转换器连接的情况下，可以将所述第二时钟信号传输至模数转换器实现模数转换器的正常数据采样操作；也可以通过所述信号输出端口将所述同步信号121传输至模数转换器以使得不同的信号输出端口所对应的模数转换器能够实现同步。实际应用中，任何基于时钟信号进行工作并且需要进行同步的模块均可以与所述信号输出端口相连接。
基于上述多通道信号同步系统，如图6所示，介绍本申请实施例一种多通 道信号同步方法。所述多通道信号同步方法可以包括以下步骤。
S610：时钟信号产生模块生成第一时钟信号并输出至同步信号产生模块。
对于所述时钟信号产生模块110的介绍以及生成和传输所述第一时钟信号103的过程的说明可以参照图1A所对应的实施例中对于所述时钟信号产生模块110和第一时钟信号103的介绍，在此不做赘述。
S620：同步信号产生模块基于所述第一时钟信号生成同步信号，并将所述同步信号传输至所述时钟信号产生模块。
对于所述同步信号产生模块120的介绍以及生成和传输所述同步信号121的过程可以参照图1A所对应的实施例中对于所述同步信号产生模块120和同步信号121的介绍，在此不做赘述。
S630：所述时钟信号产生模块根据所述同步信号生成第二时钟信号并将所述第二时钟信号传输至信号接收模块。
生成所述第二时钟信号的过程可以参照图1A所对应的实施例中对于生成所述第二时钟信号的介绍，在此不做赘述。
所述时钟信号产生模块与信号接收模块之间连接有同步信号传输线，使得所述时钟信号产生模块能够通过所述同步信号传输线将第二时钟信号传输至各个信号接收模块中。所述信号接收模块在接收到所述第二时钟信号后，能够基于所述第二时钟信号实现时序电路的有效进行，从而完成相应的数据采样工作。
在另一个实施方式中，所述时钟信号产生模块在生成第二时钟信号后，可以直接将所述第二时钟信号分别传输至信号接收模块，由各个信号接收模块对第二时钟信号进行延时处理。具体的延时长度可以根据不同的信号接收模块所对应的延时长度而确定。
如图4A所示，为利用信号接收模块对第二时钟信号进行延时处理的具体示例。可以看出，时钟信号产生模块传输至各个信号接收模块的信号为相同的第二时钟信号，由各个信号接收模块自行对第二时钟信号进行延时。
S640：所述同步信号产生模块将所述同步信号传输至所述信号接收模块以实现所述信号接收模块的同步。
对于所述信号接收模块的介绍和所述信号接收模块的同步过程的介绍可以参照图1A所对应的实施例中对于信号接收模块的说明，在此不做赘述。
在上述多通道信号同步方法中，对于步骤S630和步骤S640的执行顺序可前后调换，也可同时执行。实际应用中，可以是先由时钟信号产生模块将第二时钟信号传输至信号接收模块，再由同步信号产生模块将同步信号传输至信号 接收模块，也可以是先由同步信号产生模块将同步信号传输至信号接收模块，再由时钟信号产生模块将第二时钟信号传输至信号接收模块。
基于上述多通道信号同步系统、电路及方法的实施例，在向多通道系统中的信号接收模块传输同步信号以实现同步时，会基于所述同步信号对向信号接收模块传输的时钟信号进行调整，使得所述同步信号在高电平有效时能够在不受时钟信号干扰的情况下传输至信号接收模块中，相应的，调整后的时钟信号在同步结束时的时序余量也能够满足时钟信号对于建立时间的需求，从而能够在信号接收模块中正常响应，保证了对信号接收模块的同步的有效性和准确性。
下面结合附图7介绍本申请实施例另一种多通道信号同步系统。所述多通道信号同步系统包括时钟信号产生模块110、同步信号产生模块120和至少两个信号接收模块。
对于所述时钟信号产生模块110、同步信号产生模块120和信号输出端口的介绍可以参照图1A所对应的实施例中对于时钟信号产生模块110、同步信号产生模块120和信号接收模块的介绍，在此不做赘述。
所述时钟信号产生模块110可以生成第一时钟信号103，并将所述第一时钟信号传输至同步信号产生模块120。所述同步信号产生模块120在接收到所述第一时钟信号103后，可以生成同步信号121，并将所述同步信号121传输至时钟信号产生模块。所述时钟信号产生模块在接收到所述同步信号121后可以生成第二时钟信号111。对于上述过程中各个信号的产生以及传输的过程可以参照图1A所对应的实施例中对于生成第一时钟信号103、同步信号121、第二时钟信号以及传输所述第一时钟信号103、同步信号121的过程的介绍，在此不做赘述。
在该实施例中，所述同步信号产生模块120与信号接收模块之间并未连接有同步信号传输线，而是直接通过时钟信号产生模块110向各个信号接收模块传输同步信号121。在一些实施方式中，可以直接利用混合信号传输支路812传输同步信号121和第二时钟信号111。
当利用所述混合信号传输支路传输同步信号121和第二时钟信号111时，可以是先利用时钟信号产生模块110基于预设规则将所述第二时钟信号111和所述同步信号121进行复合，例如使所述第二时钟信号111与所述同步信号121具有不同的时钟周期。所述信号接收模块在接收到复合后的信号后，可以基于预设规则从所述复合信号中区分出第二时钟信号111和同步信号121。例如在所述同步信号121的周期大于所述第二时钟信号111的周期的情况下，复合后的信号在所述同步信号121对应的上升沿和下降沿处会表现出非周期信号具有的 特征，从而可以确定同步信号121的有效信号段。
基于上述多通道信号同步系统，取消了同步信号产生模块与各个信号接收模块之间所连接的同步信号线，直接利用时钟信号产生模块利用同一信号线实现时钟信号和同步信号的传输，简化了系统的设计难度。
基于上述多通道信号同步系统，结合图8，介绍本申请实施例一种多通道信号同步电路。所述多通道信号同步电路包括时钟信号产生模块110、同步信号产生模块120和信号输出端口。
在一实施例中，图8中，还存在时钟信号输入端口801与同步信号输入端口802。
在一些实施方式中，在所述同步信号产生模块120根据所述第一时钟信号的时钟周期生成同步信号时，可以是生成信号有效时长大于或等于两倍的时钟周期的同步信号。所述信号有效时长为所述同步信号在系统中起作用时对应的信号段的持续时长。例如，当所述同步信号为高电平有效时，可以是所述同步信号的高电平所持续的时长。
所述时钟信号产生模块110与所述同步信号产生模块120之间还可以设置有同步信号传输支路，此同步信号传输支路也可记为同步信号传输第三支路821，以使所述同步信号产生模块120传输同步信号至所述时钟信号产生模块110。
所述同步信号传输第三支路821和所述第一时钟信号传输支路811只是从功能性的角度上进行区分，实际应用中，所述同步信号传输第三支路821和所述第一时钟信号传输支路811可以是同一根信号线，也可以是不同的信号线。
所述时钟信号产生模块110在接收到所述同步信号后，可以基于所述同步信号生成第二时钟信号。
在一些实施方式中，时钟信号产生模块110生成第二时钟信号的方式可以是根据接收到的参考时钟信号生成中间时钟信号，并根据所述同步信号和所述中间时钟信号生成第二时钟信号。
所述时钟信号产生模块110与所述信号输出端口之间可以设置有混合信号传输支路812，以使所述时钟信号产生模块110传输第二时钟信号和所述同步信号至所述信号输出端口。
所述信号输出端口，可以将所述第二时钟信号和所述同步信号传输至电路外与所述信号输出端口相连接的模块。例如，在所述信号输出端口与模数转换器连接的情况下，可以将所述第二时钟信号传输至模数转换器实现模数转换器 的正常数据采样操作；也可以通过所述信号输出端口将所述同步信号传输至模数转换器以使得不同的信号输出端口所对应的模数转换器能够实现同步。实际应用中，任何基于时钟信号进行工作并且需要进行同步的模块均可以与所述信号输出端口相连接。
基于图7所对应的多通道信号同步系统，如图9所示，介绍本申请实施例一种多通道信号同步方法。所述多通道信号同步方法可以包括以下步骤。
S910：时钟信号产生模块生成第一时钟信号并输出至同步信号产生模块。
对于所述时钟信号产生模块110的介绍以及生成和传输所述第一时钟信号103的过程的说明可以参照图7所对应的实施例中对于所述时钟信号产生模块110和第一时钟信号103的介绍，在此不做赘述。
S920：同步信号产生模块基于所述第一时钟信号生成同步信号，并将所述同步信号传输至所述时钟信号产生模块。
对于所述同步信号产生模块120的介绍以及生成和传输所述同步信号121的过程可以参照图7所对应的实施例中对于所述同步信号产生模块120和同步信号121的介绍，在此不做赘述。
S930：所述时钟信号产生模块根据所述同步信号生成第二时钟信号。
生成所述第二时钟信号111的过程可以参照图7所对应的实施例中对于生成所述第二时钟信号111的介绍，在此不做赘述。
所述时钟信号产生模块与信号接收模块之间连接有同步信号传输线，使得所述时钟信号产生模块能够通过所述同步信号传输线将第二时钟信号传输至各个信号接收模块中。所述信号接收模块在接收到所述第二时钟信号后，能够基于所述第二时钟信号实现时序电路的有效进行，从而完成相应的数据采样工作。
在另一个实施方式中，所述时钟信号产生模块在生成第二时钟信号后，可以直接将所述第二时钟信号分别传输至信号接收模块，由各个信号接收模块对第二时钟信号进行延时处理。具体的延时长度可以根据不同的信号接收模块所对应的延时长度而确定。
S940：所述时钟信号产生模块将所述同步信号和所述第二时钟信号传输至所述信号接收模块以实现所述信号接收模块的同步。
对于所述信号接收模块的介绍和传输所述同步信号和所述第二时钟信号的过程的介绍可以参照图7所对应的实施例中相应的说明，在此不做赘述。
所述时钟信号产生模块可以直接将之前所接收到的同步信号传输至所述信号接收模块，不需要所述同步信号产生模块传输同步信号至信号接收模块，进 而无需在同步信号产生模块和信号接收模块之间设置信号线。在一个实施方式中，可以直接利用同一根混合信号传输支路传输同步信号和第二时钟信号。
基于上述多通道信号同步系统，取消了同步信号产生模块与各个信号接收模块之间所连接的同步信号第二传输支路，直接利用时钟信号产生模块利用混合信号传输支路实现时钟信号和同步信号的传输，简化了系统的设计难度。
在一些实施方式中，所述信号接收模块包括模数转换器。
在一些实施方式中，所述时钟信号产生模块设置为根据接收到的参考时钟信号生成第一时钟信号。
在一些实施方式中，所述第一时钟信号对应有时钟周期；所述同步信号的信号有效时长大于或等于两倍的时钟周期。
在一些实施方式中，所述时钟信号产生模块设置为根据接收到的参考时钟信号生成中间时钟信号，并根据所述中间时钟信号和所述同步信号生成第二时钟信号。
在一些实施方式中，所述时钟信号产生模块设置为将所述同步信号和所述中间时钟信号输入门控时钟单元得到第二时钟信号。
在一些实施方式中，所述时钟信号产生模块设置为对所述同步信号进行延时，并根据延时后的同步信号和所述中间时钟信号生成第二时钟信号。
在一些实施方式中，所述时钟信号产生模块利用所述第一时钟信号对所述同步信号进行延时；
和/或，
所述时钟信号产生模块利用电阻电容延迟单元对所述同步信号进行延时；
和/或，
所述时钟信号产生模块利用缓冲器对所述同步信号进行延时。
在一些实施方式中，所述同步信号产生模块设置为基于所述第一时钟信号和接收到的参考同步信号生成同步信号。
在一些实施方式中，所述信号接收模块对应有指定的延时长度；
所述时钟信号产生模块设置为在生成第二时钟信号后，对所述第二时钟信号进行对应于信号接收模块的延时长度的延时处理，并将延时后的第二时钟信号传输至所述信号接收模块。
在一些实施方式中，所述信号接收模块对应有指定的延时长度；
所述时钟信号产生模块设置为在生成第二时钟信号后，将所述第二时钟信号分别传输至所述信号接收模块；
所述信号接收模块设置为对接收到的所述第二时钟信号进行对应的延时长度的延时处理。
在一些实施方式中，所述第一时钟信号传输支路与所述同步信号传输第一支路为同一条支路。
基于上述多通道信号同步系统、电路及方法的实施例，向多通道系统中的信号接收模块传输同步信号以实现同步时，会基于所述同步信号对向信号接收模块传输的时钟信号进行调整，使得所述同步信号在高电平有效时能够在不受时钟信号干扰的情况下被传输至信号接收模块中，相应的，所述时钟信号在调整后，同步结束时的时序余量也能够满足建立时间的需求，从而能够在信号接收模块中正常响应。此外，利用混合信号传输支路同时实现时钟信号和同步信号的传输也减少了设计中的线路，降低了设计难度。因此，所述多通道信号同步系统、电路及方法方便准确地实现了对多通道系统中的信号接收模块的同步。
由以上本申请实施例提供的技术方案可见，本申请实施例所介绍的多通道信号同步系统根据同步信号来生成第二时钟信号，从而使得所述第二时钟信号与所述同步信号之间存在关联性。在利用同步信号对信号接收模块进行同步时，使得所述信号接收模块所接收到的第二时钟信号不会对同步信号造成干扰，同步过程完成后之后各通道中的时钟信号也都能正常生效，从而保证了信号接收模块的工作的正确进行，减轻了对多通道系统进行信号同步的难度，方便有效地实现了多通道信号同步。
本申请中的各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于系统实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。

Claims (14)

  1. 一种多通道信号同步系统，包括时钟信号产生模块、同步信号产生模块和至少两个信号接收模块；
    所述时钟信号产生模块设置为生成第一时钟信号并将所述第一时钟信号传输至所述同步信号产生模块；
    所述同步信号产生模块设置为基于所述时钟信号产生模块输出的所述第一时钟信号生成同步信号，并将所述同步信号传输至所述时钟信号产生模块；
    所述时钟信号产生模块还设置为基于所述同步信号产生模块反馈的所述同步信号生成第二时钟信号，并将所述第二时钟信号传输至所述至少两个信号接收模块；
    所述同步信号产生模块还设置为将所述同步信号传输至所述至少两个信号接收模块。
  2. 如权利要求1所述的系统，其中，所述时钟信号产生模块是设置为根据接收到的参考时钟信号生成中间时钟信号，并根据所述中间时钟信号和所述同步信号生成第二时钟信号。
  3. 如权利要求2所述的系统，其中，所述时钟信号产生模块是设置为将所述同步信号和所述中间时钟信号输入门控时钟单元得到第二时钟信号。
  4. 如权利要求2所述的系统，其中，所述时钟信号产生模块是设置为对所述同步信号进行延时，并根据延时后的同步信号和所述中间时钟信号生成第二时钟信号。
  5. 如权利要求1所述的系统，其中，所述同步信号产生模块是设置为基于所述第一时钟信号和接收到的参考同步信号生成同步信号。
  6. 一种多通道信号同步系统，包括时钟信号产生模块、同步信号产生模块和至少两个信号接收模块；
    所述时钟信号产生模块设置为生成第一时钟信号并将所述第一时钟信号传输至所述同步信号产生模块；
    所述同步信号产生模块设置为基于所述时钟信号产生模块输出的所述第一时钟信号生成同步信号，并将所述同步信号传输至所述时钟信号产生模块；
    所述时钟信号产生模块还设置为基于所述同步信号产生模块反馈的同步信号生成第二时钟信号，并将所述同步信号和所述第二时钟信号传输至所述至少两个信号接收模块。
  7. 如权利要求6所述的系统，其中，所述时钟信号产生模块是设置为根据接收到的参考时钟信号生成中间时钟信号，并根据所述中间时钟信号和所述同步信号生成第二时钟信号。
  8. 如权利要求7所述的系统，其中，所述时钟信号产生模块是设置为将所述同步信号和所述中间时钟信号输入门控时钟单元得到第二时钟信号。
  9. 如权利要求7所述的系统，其中，所述时钟信号产生模块是设置为对所述同步信号进行延时，并根据延时后的同步信号和所述中间时钟信号生成第二时钟信号。
  10. 如权利要求6所述的系统，其中，所述同步信号产生模块是设置为基于所述第一时钟信号和接收到的参考同步信号生成同步信号。
  11. 一种多通道信号同步电路，包括时钟信号产生模块、同步信号产生模块和信号输出端口；
    所述时钟信号产生模块与所述同步信号产生模块之间设置有第一时钟信号传输支路和同步信号传输第一支路，所述第一时钟信号传输支路被设置为由所述时钟信号产生模块传输第一时钟信号至所述同步信号产生模块，以及，所述同步信号传输第一支路被设置为由所述同步信号产生模块传输同步信号至所述时钟信号产生模块；所述同步信号产生模块设置为基于接收到的第一时钟信号生成所述同步信号；
    所述时钟信号产生模块与所述信号输出端口之间设置有第二时钟信号传输支路，所述第二时钟信号传输支路被设置为由所述时钟信号产生模块传输第二时钟信号至所述信号输出端口；所述时钟信号产生模块设置为基于接收到的所述同步信号和所述第一时钟信号生成所述第二时钟信号；
    所述同步信号产生模块与所述信号输出端口之间设置有同步信号传输第二支路，所述同步信号传输第二支路被设置为由所述同步信号产生模块传输所述 同步信号至所述信号输出端口。
  12. 一种多通道信号同步电路，包括时钟信号产生模块、同步信号产生模块和信号输出端口；
    所述时钟信号产生模块与所述同步信号产生模块之间设置有第一时钟信号传输支路和同步信号传输支路，所述第一时钟信号传输支路被设置为由所述时钟信号产生模块传输第一时钟信号至所述同步信号产生模块，以及，所述同步信号传输支路被设置为由所述同步信号产生模块传输同步信号至所述时钟信号产生模块；所述同步信号信号产生模块设置为基于接收到的所述第一时钟信号生成所述同步信号；
    所述时钟信号产生模块与所述信号输出端口之间设置有混合信号传输支路，所述混合信号传输支路被配置为由所述时钟信号产生模块传输第二时钟信号和所述同步信号至所述信号输出端口；所述时钟信号产生模块设置为基于接收到的所述同步信号生成所述第二时钟信号。
  13. 一种多通道信号同步方法，包括：
    时钟信号产生模块生成第一时钟信号并将所述第一时钟信号输出至同步信号产生模块；
    所述同步信号产生模块基于所述第一时钟信号生成同步信号，并将所述同步信号传输至所述时钟信号产生模块；
    所述时钟信号产生模块基于所述同步信号生成第二时钟信号并将所述第二时钟信号传输至至少两个信号接收模块；
    所述同步信号产生模块将所述同步信号传输至所述至少两个信号接收模块，以实现所述至少两个信号接收模块的同步。
  14. 一种多通道信号同步方法，包括：
    时钟信号产生模块生成第一时钟信号并将所述第一时钟信号输出至同步信号产生模块；
    所述同步信号产生模块基于所述第一时钟信号生成同步信号，并将所述同步信号传输至所述时钟信号产生模块；
    所述时钟信号产生模块基于所述同步信号生成第二时钟信号；
    所述时钟信号产生模块将所述同步信号和所述第二时钟信号传输至至少两 个信号接收模块，以实现所述至少两个信号接收模块的同步。
PCT/CN2021/087347 2020-04-21 2021-04-15 多通道信号同步系统、电路及方法 Ceased WO2021213237A1 (zh)

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