WO2021213439A1 - 显示装置、显示面板及其制造方法 - Google Patents

显示装置、显示面板及其制造方法 Download PDF

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Publication number
WO2021213439A1
WO2021213439A1 PCT/CN2021/088701 CN2021088701W WO2021213439A1 WO 2021213439 A1 WO2021213439 A1 WO 2021213439A1 CN 2021088701 W CN2021088701 W CN 2021088701W WO 2021213439 A1 WO2021213439 A1 WO 2021213439A1
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WIPO (PCT)
Prior art keywords
layer
substrate
electrode
insulating layer
light
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Ceased
Application number
PCT/CN2021/088701
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English (en)
French (fr)
Inventor
黄冠达
李育豪
张大成
童慧
申晓斌
李世鹏
杨超
李东升
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Priority to EP21726546.1A priority Critical patent/EP4141944A4/en
Priority to JP2021530217A priority patent/JP7640456B2/ja
Priority to CN202310487217.9A priority patent/CN116963536A/zh
Priority to KR1020217016207A priority patent/KR20230002018A/ko
Priority to CN202310485818.6A priority patent/CN116709834A/zh
Priority to CN202180000830.2A priority patent/CN114097092B/zh
Priority to CN202310505881.1A priority patent/CN116782705A/zh
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US17/428,326 priority patent/US12317689B2/en
Publication of WO2021213439A1 publication Critical patent/WO2021213439A1/zh
Anticipated expiration legal-status Critical
Priority to US18/336,196 priority patent/US12414445B2/en
Priority to US18/336,883 priority patent/US12453250B2/en
Priority to US18/336,892 priority patent/US20230337474A1/en
Priority to US18/641,532 priority patent/US20240268160A1/en
Priority to JP2025024830A priority patent/JP2025081509A/ja
Priority to JP2025024832A priority patent/JP2025081511A/ja
Priority to JP2025024831A priority patent/JP2025081510A/ja
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/805—Electrodes
    • H10K59/8052—Cathodes
    • H10K59/80521—Cathodes characterised by their shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/38—Devices specially adapted for multicolour light emission comprising colour filters or colour changing media [CCM]

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display device, a display panel, and a manufacturing method of the display panel.
  • OLED Organic Light-Emitting Diode, organic light-emitting diode
  • the light-emitting device usually includes a plurality of OLED light-emitting devices distributed in an array, and each light-emitting device can emit light independently in order to display images.
  • the luminescence stability of the OLED light-emitting device still needs to be improved.
  • the purpose of the present disclosure is to overcome the above-mentioned shortcomings of the prior art and provide a display device, a display panel, and a manufacturing method of the display panel.
  • a display panel including:
  • the first insulating layer is provided on one side of the substrate, and the first insulating layer has a plurality of pixel regions distributed in an array and a partition region separating the pixel regions;
  • the first electrode layer is provided on the surface of the first insulating layer away from the substrate and includes a plurality of first electrodes; the orthographic projection of each of the first electrodes on the first insulating layer is located in each of the pixels Within the district
  • the pixel definition layer is provided on the surface of the first insulating layer away from the substrate, and each of the first electrodes is exposed; the pixel definition layer is formed with a pixel definition groove in a region corresponding to the separation area, The middle of the pixel defining groove has a first protrusion protruding in a direction away from the substrate, and a sub-groove is formed between the side wall of the first protrusion and the side wall of the pixel defining groove;
  • a light-emitting function layer covering the pixel defining layer and the first electrode exposed by the pixel defining layer;
  • the second electrode covers the light-emitting function layer.
  • the two side walls of the first protrusion are inclined surfaces that expand toward the substrate, and the two side walls of the pixel defining groove are inclined surfaces that shrink toward the substrate. .
  • the slope of the side wall of the first protrusion is different from the slope of the side wall of the pixel defining groove.
  • the thickness of the first protrusion is smaller than the depth of the pixel defining groove.
  • the orthographic projection of the middle of the pixel defining groove on the first insulating layer is located in the partition area.
  • the pixel definition layer includes a spacer and an extension, the spacer is located in an area other than the first electrode, and the pixel definition groove is at least partially provided in the spacer. Portion; the extension portion is connected to the spacer portion, and extends to the surface of the first electrode away from the substrate, and does not completely cover the first electrode.
  • the width of the extension part covering any one of the first electrodes is smaller than the width of the spacing part between two adjacent first electrodes.
  • At least two of the first electrodes have different thicknesses.
  • the maximum depth of the pixel defining groove is not more than 60% of the sum of the thicknesses of the light-emitting function layer and the first electrode.
  • a display panel including:
  • the first insulating layer is provided on one side of the substrate;
  • the first electrode layer is provided on the surface of the first insulating layer away from the substrate and includes a plurality of first electrodes
  • a pixel definition layer disposed on the surface of the first insulating layer away from the substrate, and exposing each of the first electrodes;
  • a light-emitting function layer covering the pixel defining layer and the first electrode exposed by the pixel defining layer;
  • the second electrode covers the light-emitting functional layer and includes a recessed portion and a plurality of smooth portions separated by the recessed portion, and the orthographic projection of each smooth portion on the first insulating layer is located in each of the first insulating layers.
  • the electrode Within the electrode; at least part of the recessed portion is recessed toward the side of the smooth portion close to the substrate, and the orthographic projection of the recessed portion on the first insulating layer is at least partially located outside the first electrode
  • a second protrusion is provided in the middle of the recessed portion, and a sub-recess is formed between the side surface of the second protrusion and the side surface of the recessed portion.
  • the first insulating layer has a plurality of pixel regions distributed in an array and a partition region separating the pixel regions, and each of the first electrodes is on the surface of the first insulating layer.
  • the orthographic projection is located within each of the first electrodes;
  • the pixel defining layer exposes each of the first electrodes, and a pixel defining groove is formed in a region corresponding to the separation area, and the middle of the pixel defining groove has a first protruding direction away from the substrate.
  • a protrusion, a sub-groove is formed between the side wall of the first protrusion and the side wall of the pixel defining groove;
  • the orthographic projection of the recess on the first insulating layer is at least partially located in the pixel defining groove.
  • the orthographic projection of the point of the sub-recess closest to the substrate on the first insulating layer is located in the sub-groove.
  • the concave portion includes a first side surface and a second side surface, and the first side surface and the second side surface are relatively connected to two sides of the second protrusion, and The first side surface and the second side surface shrink toward the substrate.
  • the second protrusion includes a first slope surface, a second slope surface, and a connecting surface connected between the first slope surface and the second slope surface,
  • the connecting surface is located on a side of the first side surface and the bottom side of the second side surface away from the substrate, the first slope surface is connected to the bottom side of the first side surface, and the second slope The surface is connected with the bottom edge of the second side surface.
  • the minimum thickness of the area of the second electrode corresponding to the first side surface and the second side surface is larger than that corresponding to the first slope surface and the second side surface. The minimum thickness of the slope area.
  • the pixel definition layer includes a spacer portion and an extension portion, the spacer portion is located in an area other than the first electrode, and the pixel definition groove is provided in the spacer portion;
  • the extension portion is connected to the spacer portion and extends to the surface of the first electrode facing away from the substrate, and does not completely cover the first electrode;
  • the second electrode further has a convex portion that protrudes in a direction away from the substrate, and the smooth portion is connected to the concave portion through the convex portion; the convex portion is on the substrate.
  • the orthographic projection of and the orthographic projection of the extension on the substrate at least partially overlap.
  • one of the protrusions is farthest from the substrate and the substrate The distance of is different from the distance between the furthest point of the protrusion from the substrate and the substrate.
  • the display panel further includes:
  • the first encapsulation layer covers the second electrode and forms a pit in a region corresponding to the recessed portion.
  • the two sidewalls of the pit are narrowed and connected in a direction approaching the substrate.
  • a method of manufacturing a display panel including:
  • the first insulating layer Forming a first insulating layer on one side of a substrate; the first insulating layer has a plurality of pixel regions distributed in an array and a partition region separating the pixel regions;
  • a first electrode layer including a plurality of first electrodes is formed on the surface of the first insulating layer away from the substrate; the orthographic projection of each of the first electrodes on the first insulating layer is located within each of the pixel regions ;
  • a pixel defining layer is formed on the surface of the first insulating layer away from the substrate, and each of the first electrodes is exposed; the pixel defining layer is formed with a pixel defining groove in a region corresponding to the separation area, and The middle of the pixel defining groove has a first protrusion protruding in a direction away from the substrate, and a sub-groove is formed between the side wall of the first protrusion and the side wall of the pixel defining groove;
  • a second electrode covering the light-emitting function layer is formed.
  • a method of manufacturing a display panel including:
  • first electrode layer Forming a first electrode layer on the surface of the first insulating layer away from the substrate, the first electrode layer including a plurality of first electrodes;
  • a second electrode covering the light-emitting function layer is formed, the second electrode includes a recessed portion and a plurality of smooth portions separated by the recessed portion, and the orthographic projection of each smooth portion on the first insulating layer is located Within each of the first electrodes; at least part of the recessed portion is recessed toward the side of the smooth portion close to the substrate, and the orthographic projection of the recessed portion on the first insulating layer is at least partially located
  • a second protrusion is provided in the middle of the recessed portion, and a sub-recess is formed between the side surface of the second protrusion and the side surface of the recessed portion.
  • a display device including the display panel described in any one of the above.
  • FIG. 1 is a schematic diagram of an embodiment of the first display panel of the present disclosure.
  • FIG. 2 is a partial electron micrograph of an embodiment of the first display panel of the present disclosure.
  • FIG. 3 is a schematic diagram of another embodiment of the first display panel of the present disclosure.
  • FIG. 4 is a schematic diagram of still another embodiment of the first display panel of the present disclosure.
  • FIG. 5 is a top view of a pixel definition layer in an embodiment of the first display panel of the present disclosure.
  • FIG. 6 is a top view of a pixel defining layer and a first electrode in an embodiment of the first display panel of the present disclosure.
  • FIG. 7 is a schematic diagram of an embodiment of the second display panel of the present disclosure.
  • Fig. 8 is an enlarged view of part A in Fig. 7.
  • FIG. 9 is a partial electron micrograph of an embodiment of the second display panel of the present disclosure.
  • FIG. 10 is a schematic diagram of an embodiment of a third display panel of the present disclosure.
  • FIG. 11 is a schematic diagram of another embodiment of the third display panel of the present disclosure.
  • FIG. 12 is a schematic diagram of another embodiment of the fourth display panel of the present disclosure.
  • Fig. 13 is an enlarged view of part B in Fig. 12.
  • FIG. 14 is a schematic diagram of an embodiment of the first method of manufacturing a display panel of the present disclosure.
  • FIG. 15 is a schematic diagram of another embodiment of the first method of manufacturing a display panel of the present disclosure.
  • FIG. 16 is a schematic diagram of an embodiment of a method for manufacturing a second display panel of the present disclosure.
  • FIG. 17 is a schematic diagram of an embodiment of a method for manufacturing a third display panel of the present disclosure.
  • FIG. 18 is a schematic diagram of an embodiment of the fourth display panel manufacturing method of the present disclosure.
  • Substrate; 101 active area; 1011, source; 1012, drain; 2. flat layer; 201, separation groove; 2011, sidewall; 2012, bottom wall; 202, pixel area; 3.
  • light-emitting function layer 501, light-emitting unit Layer; 502, charge generation layer; 6, second electrode; 61, recess; 611, first side surface; 612, second side surface; 613, bottom surface; 6131, first slope surface; 6132, second slope surface; 6133 , Connection surface; 600, the second bump; 62, the gentle part; 63, the protruding part; 7, the gate insulating layer; 8, the gate electrode; 9, the second insulating layer; 10, the first wiring layer; 11. The third insulating layer; 12. The second wiring layer; 13. The first packaging layer; 1301; The pits; 14. The color film layer; 15. The second packaging layer; 16. The transparent cover plate; 17. The light extraction layer.
  • an OLED display panel includes a driving backplane, a plurality of first electrodes, a pixel definition layer, a light-emitting function layer, a second electrode, and a color film layer.
  • the first electrode array is distributed on the driving backplane; the pixel definition layer Set on the surface of the driving backplane where the first electrode is provided, and each first electrode is exposed; the light-emitting function layer covers the pixel definition layer and the surface of the first electrode facing away from the driving backplane, and the second electrode covers the light-emitting function layer facing away from the driving backplane
  • a plurality of light-emitting devices can be defined by the pixel definition layer.
  • the color filter layer is arranged on the side of the second electrode away from the driving backplane, and has multiple filter regions corresponding to each light-emitting device one by one, and each filter region and its corresponding light-emitting device can be used as a sub-pixel.
  • the thickness of the pixel definition layer is greater than that of the first electrode, when the light-emitting function layer is formed by the evaporation process, the light-emitting function layer will be recessed at the junction of the first electrode and the pixel definition layer, that is, at the edge of the light-emitting device, so that The second electrode correspondingly forms a recessed area, and the distance between the recessed area of the second electrode and the first electrode is relatively close, which is prone to tip discharge or even short circuit, which affects the stability of the light-emitting device and makes it difficult for the display panel to emit light stably.
  • the recessed area of the second electrode corresponds to the first electrode, and therefore also emits light.
  • the topography of the recessed area is a structure recessed toward the driving backplane, rather than a planar structure, the light is emitted within the range of the recessed area.
  • the light is in a scattered state, and at least part of the light is skewed toward adjacent sub-pixels, so that the light emission of the adjacent sub-pixels interferes with each other and affects the display effect.
  • the light-emitting function layer is recessed in the second electrode at the junction of the first electrode and the pixel definition layer, so that the second electrode forms a recessed area in the area corresponding to the recessed area, and the recessed area is directly opposite to the first electrode, that is, the recessed area is driving back.
  • the orthographic projection of the plate is located in the first electrode, so that a sharp discharge or even a short circuit may occur between the two.
  • the recessed area emits light, and because the shape of the recessed area is curved, the light emitted by the recessed area is in a scattered state, which interferes with the light emission of adjacent sub-pixels.
  • the light-emitting function layer is a continuous film layer, so that the sub-pixels are connected to each other, at least a part of the film layer (including but not limited to the hole injection layer) in the light-emitting function layer will cause the gap between adjacent sub-pixels. Produce crosstalk.
  • the light-emitting function layer includes a plurality of light-emitting unit layers, and two adjacent light-emitting unit layers are connected in series through a charge generation layer.
  • the charge generation layer has good charge conduction characteristics, which will cause crosstalk between adjacent sub-pixels and affect the light-emitting effect.
  • embodiments of the present disclosure provide various display panels.
  • the display panel may include a substrate 1, a first insulating layer 2, a first electrode layer 3, a pixel definition layer 4, a light-emitting function layer 5, and a second electrode 6, wherein:
  • the first insulating layer 2 is provided on the side of the substrate 1, and the surface of the first insulating layer 2 facing away from the substrate 1 is provided with a plurality of separation grooves 201 to divide a plurality of pixel regions 202 on the first insulating layer 2, and The pixel regions 202 are arranged in an array.
  • the first electrode layer 3 is provided on the surface of the first insulating layer 2 facing away from the substrate 1, and includes a plurality of first electrodes 31 distributed in an array. Within each pixel area 202.
  • the first electrode 31 includes a flat middle part 310 and an edge part 311 surrounding the middle part 310; the edge part 311 includes a flat part 3110 surrounding the middle part 310 and a climbing part 3111 connected between the middle part 310 and the flat part 3110,
  • the thickness of the flat portion 3110 is smaller than that of the middle portion 310.
  • the pixel definition layer 4 is disposed on the surface of the first insulating layer 2 away from the substrate 1 and exposes at least a part of the middle portion 310.
  • the light-emitting function layer 5 covers the pixel defining layer 4 and the intermediate portion 310 and the first insulating layer 2 exposed by the pixel defining layer 4.
  • the second electrode 6 covers the light-emitting function layer 5.
  • the area where the middle portion 310 of each first electrode 31 is exposed by the pixel defining layer 4 and its corresponding light-emitting function layer 5 and second electrode 6 can constitute a light-emitting device to emit light.
  • the light-emitting functional layer 5 can be The position of the separation groove 201 is recessed toward the substrate 1, so that the second electrode 6 forms a recess 61 in the recess, and the orthographic projection of the recess 61 on the first insulating layer 2 is at least partially located in the middle of the first electrode 31 310, that is, outside the light-emitting device.
  • the position of the recessed portion 61 of the second electrode 6 can be restricted by the separation groove 201 to prevent tip discharge or even short circuit between the recessed portion 61 and the intermediate portion 310. It helps to ensure that the light-emitting device emits light stably. At the same time, light emission within the range of the recess 61 can be reduced or even avoided, thereby reducing the mutual interference of the light emission of adjacent light-emitting devices.
  • FIG. 2 is a partial electron micrograph of an embodiment of the first display panel of the present disclosure. It can be seen that the orthographic projection of the recess 61 on the first insulating layer 2 is at least partially outside the range of the first electrode 31 , Can reduce the risk of sharp discharge with the first electrode 31. At the same time, it can reduce or even prevent the recess 61 from emitting light, and prevent interference to adjacent sub-pixels.
  • the material of the substrate 1 may be a semiconductor material such as single crystal silicon or polycrystalline silicon, or other hard or soft materials such as glass.
  • a plurality of driving transistors may be provided on the substrate 1 to drive each light-emitting device to emit light to display an image.
  • the display panel further includes a gate insulating layer 7, a gate electrode 8, a second insulating layer 9 and a first wiring layer 10.
  • the material of the substrate 1 can be monocrystalline silicon or Semiconductor materials such as polysilicon, and the substrate 1 includes an active region 101 and a source electrode 1011 and a drain electrode 1012 located at both ends of the active region 101.
  • the gate insulating layer 7 covers the active region 101; the gate 8 is provided on the surface of the gate insulating layer 7 away from the substrate 1, and the material of the gate 8 may include polysilicon material.
  • the second insulating layer 9 covers the gate 8 and the substrate 1, and its material may include at least one of silicon oxide and silicon nitride.
  • the first wiring layer 10 is provided on the surface of the second insulating layer 9 away from the substrate 1, and the gate 8, the source 1011 and the drain 1012 are all connected to the first wiring layer 10 through via holes filled with tungsten or other metals .
  • the display panel may further include a third insulating layer 11 and a second wiring layer 12.
  • the third insulating layer 11 covers the first wiring layer 10 and the second insulating layer 9, and the second wiring layer 12 is provided on the third insulating layer.
  • the layer 11 is away from the surface of the substrate 1.
  • the specific pattern of the second wiring layer 12 is not particularly limited here, and it can be connected to the first wiring layer 10 through via holes filled with tungsten or other metals.
  • the first insulating layer 2 is provided on one side of the substrate 1.
  • the first insulating layer 2 can cover the second wiring layer 12, and the first electrode 31 can pass through tungsten. Or other metal-filled vias are connected to the second wiring layer 12.
  • the material of the first insulating layer 2 may include at least one of silicon nitride and silicon oxide, and of course, may also include other insulating materials.
  • the first insulating layer 2 can be planarized by a polishing process.
  • the surface of the first insulating layer 2 facing away from the substrate 1 can be provided with a plurality of separation grooves 201.
  • the depth of the separation grooves 201 is smaller than the thickness of the first insulating layer 2, that is, the separation grooves 201 do not penetrate the first insulating layer 2 in the depth direction.
  • a plurality of pixel regions 202 can be divided on the first insulating layer 2 by the separation grooves 201, and the pixel regions 202 are arranged in an array.
  • the shape of the orthographic projection of the pixel area 202 on the substrate 1 may be a rectangle, a pentagon, a hexagon or other polygons, of course, it may also be a circle or other shapes, which is not specifically limited here. At the same time, the shape and size of different pixel regions 202 may be different.
  • the separation groove 201 may include a first separation groove and a second separation groove, wherein the number of the first separation groove is multiple, and each first separation groove extends linearly along the first direction , And distributed along the second direction at intervals; the number of the second partition grooves is multiple, and each second partition groove extends linearly along the second direction, and is distributed at intervals along the first direction; the first direction and the second direction cross each other For example, the first direction and the second direction are mutually perpendicular directions. In this way, a plurality of pixel regions 202 distributed in an array can be divided on the first insulating layer 2 by the staggered first separation grooves and second separation grooves.
  • the first separation groove and the second separation groove may also extend along a curved or broken line track, thereby dividing the pixel area 202 of other shapes.
  • Each separation groove 201 may include two opposite side walls 2011 and a bottom wall 2012 connected between the two side walls 2011.
  • the two sidewalls 2011 may be arranged in parallel, that is, in a direction perpendicular to the substrate 1, the two sidewalls 2011 and their extension surfaces do not intersect.
  • the two side walls 2011 may also be arranged at a certain angle.
  • the bottom wall 2012 may be approximately parallel to the surface of the first insulating layer 2 facing away from the substrate 1, or, as shown in FIG. 1, the bottom wall 2012 may also be a convex curved surface in a direction away from the substrate 1.
  • the curvature and shape of the curved surface are not particularly limited here, and in the cross section perpendicular to the substrate 1, the contour of the bottom wall 2012 can be roughly arc-shaped, parabolic or wavy, of course, it can also be other rules. Or irregular shapes, as long as they are convex in the direction away from the substrate 1.
  • the two side walls 2011 shrink toward the bottom wall 2012, that is, the distance between the two side walls 2011 gradually decreases toward the bottom wall 2012, so that the side walls 2011 have a
  • the slope of the surface of an insulating layer 2 away from the substrate 1 is the angle between the sidewall 2011 and the surface of the first insulating layer 2 away from the substrate 1. Further, the slope is not less than 70° and not more than 90°, for example, the slope may be 70°, 80°, 90°, and so on.
  • the maximum distance S between the two sidewalls 2011 of the separation groove 201 may be 0.2 ⁇ m-0.7 ⁇ m, such as 0.2 ⁇ m 0.3 ⁇ m, 0.5 ⁇ m, or 0.7 ⁇ m.
  • the first electrode layer 3 is provided on the surface of the first insulating layer 2 away from the substrate 1, and includes a plurality of first electrodes 31 distributed in an array.
  • the projections are located within each pixel area 202 in a one-to-one correspondence, that is, the boundary of the orthographic projection of each first electrode 31 on the substrate 1 is located within the boundary of the orthographic projection of each pixel area 202 on the substrate 1 in a one-to-one correspondence.
  • Only one first electrode 31 is provided on each pixel area 202. Since the pixel area 202 is separated by the separation groove 201 and the first electrode 31 is located on the pixel area 202, the separation groove 201 is located outside the first electrode 31.
  • the shape of the orthographic projection of each first electrode 31 on the first insulating layer 2 may be the same as the shape of the pixel area 202 where it is located, and the boundary of the first electrode 31 is located within the pixel area 202 where it is located.
  • the at least one first electrode 31 may include an intermediate portion 310 and an edge portion 311 surrounding the intermediate portion 310, wherein the intermediate portion 310 is a flat structure, that is, the intermediate portion 310 is away from the first insulating layer 2
  • the surface of the substrate 1 is approximately parallel.
  • the boundary of the orthographic projection of the intermediate portion 310 of each first electrode 31 on the substrate 1 may be located within the boundary of the orthographic projection of the pixel area 202 on the substrate 1, that is, the middle
  • the boundary of the orthographic projection of the portion 310 on the substrate 1 and the boundary of the orthographic projection of the pixel area 202 on the substrate 1 has a distance L that is not zero. Further, the distance L is not less than 0.15 ⁇ m, for example, the distance may be 0.15 ⁇ m, 0.2 ⁇ m, 0.25 ⁇ m, or the like.
  • the edge portion 311 may include a flat portion 3110 and a climbing portion 3111.
  • the flat portion 3110 is located on the surface of the first insulating layer 2 facing away from the substrate 1 and arranged around the middle portion 310, and the flat portion 3110 is away from the first insulating layer 2
  • the surface of the substrate 1 is approximately parallel.
  • the thickness of the flat portion 3110 is smaller than the thickness of the middle portion 310.
  • the flat portion 3110 has a non-zero distance between the boundary of the orthographic projection of the substrate 1 and the boundary of the pixel region 202 on the substrate 1 where it is located.
  • the boundary of the orthographic projection of the flat portion 3110 on the substrate 1 overlaps the boundary of the orthographic projection of the pixel region 202 on the substrate 1 where it is located.
  • the climbing part 3111 is connected between the middle part 310 and the flat part 3110, that is, the climbing part 3111 surrounds the middle part 310, and the flat part 3110 is arranged around the climbing part 3111.
  • the slope of the climbing portion 3111 relative to the surface of the first insulating layer 2 away from the substrate 1 is not less than 30°, and the slope is such that the surface of the climbing portion 3111 and the first insulating layer 2 are away from the liner.
  • the first electrode 31 includes a first conductive layer 320, a second conductive layer 321, and a third conductive layer 322.
  • the first conductive layer 320 is provided on the surface of the first insulating layer 2 away from the substrate 1, and the second conductive layer 321 is provided on the first insulating layer 2.
  • a conductive layer 320 is away from the surface of the substrate 1, and a third conductive layer 322 is provided on the surface of the second conductive layer 321 away from the substrate 1, and extends to the first insulating layer 2 at a certain slope, thereby covering the first conductive layer 320 and the second conductive layer 321 protect the first conductive layer 320 and the second conductive layer 321.
  • the middle portion 310 of the first electrode 31 includes the third conductive layer 322 in the area of the second conductive layer 321 facing away from the surface of the substrate 1 and the first conductive layer 320 and the second conductive layer 321, and the edge portion 311 includes the third conductive layer 322
  • the area covering the edges of the first conductive layer 320 and the second conductive layer 321 is the area extending toward the first insulating layer 2.
  • the material of the first conductive layer 320 may include titanium (Ti), the material of the second conductive layer 321 includes silver (Ag), and the material of the third conductive layer 322 includes indium tin oxide (ITO). Of course, it may also be Use other materials.
  • the pixel definition layer 4 is made of insulating material, and is provided on the surface of the first insulating layer 2 away from the substrate 1 with the first electrode layer 3. At the same time, the pixel definition layer 4 exposes at least a part of the middle portion 310 of the first electrode 31, and the middle portion 310 exposed by the pixel definition layer 4 can form a light emitting device with the corresponding light emitting function layer 5 and the second electrode 6.
  • each first electrode 31 does not completely cover the pixel area 202 where it is located, and the boundary of the orthographic projection of the first electrode 31 on the substrate 1 and the pixel area 202 where it is located is The boundary of the orthographic projection of the substrate 1 has a certain distance.
  • the pixel definition layer 4 extends to the side walls 2011 and the bottom wall 2012 of the separation groove 201, that is, the pixel definition layer 4 is conformally attached to the pixel area 202 not covered by the first electrode 31, so that the pixel definition layer 4 is in the corresponding separation groove 201 The area is sunken.
  • the pixel definition layer 4 is provided with a plurality of openings 401 that expose at least a part of each middle portion 310 in a one-to-one correspondence, so that the light-emitting range of the light-emitting device can be defined by the pixel definition layer 4.
  • the opening 401 of the pixel definition layer 4 may have a hexagonal or other polygonal structure
  • the first electrode 31 may also have a polygonal structure, and is connected to the opening 401.
  • the shape is the same.
  • the first electrode 31 may also have other shapes.
  • the light-emitting functional layer 5 can be a continuous film layer, and at least partially covers the middle portion 310 of each first electrode 31, that is, covers the area exposed by the opening 401. At the same time, the light-emitting functional layer 5 also covers the pixel definition. Layer 4 and the area of the first insulating layer 2 not covered by the pixel defining layer 4 and the first electrode 31, when the light-emitting functional layer 5 is formed by evaporation or other processes, the light-emitting functional layer 5 is closer to the area corresponding to the separation groove 201 The direction of the substrate 1 is recessed.
  • the light-emitting function layer 5 includes a multilayer light-emitting unit layer 501, and the hole injection layer, the hole transport layer, the light-emitting layer, and the electron transport layer of each light-emitting unit layer 501 Same as the distribution of the electron injection layer.
  • a charge generation layer 502 is provided between two adjacent light-emitting unit layers 501, so that the light-emitting unit layers 501 are connected in series through the charge generation layer 502, so as to form a series-type OLED light-emitting device.
  • the light-emitting function layer 5 includes a light-emitting unit layer, and the light-emitting unit layer includes a hole injection layer, a hole transport layer, Emitting layer, electron transport layer and electron injection layer.
  • the charge generation layer 502 cannot cover the sidewall 2011 of the separation groove 201, so that the charge generation layer 502 of the light-emitting device can be cut off by the separation groove 201 to avoid crosstalk between two adjacent light-emitting devices.
  • the separation groove 201 can also cut off the hole injection layer or other film layers, which can also prevent crosstalk.
  • the second electrode 6 covers the light-emitting functional layer 5, and can apply driving signals to the first electrode 31 and the second electrode 6, so that the light-emitting functional layer 5 is located between the first electrode 31 and the second electrode 6. Glow.
  • the morphology of the second electrode 6 matches that of the light-emitting functional layer 5, which is recessed in the recess of the light-emitting functional layer 5 to form a recess 61, and a smooth portion 62 is formed in the region corresponding to the middle portion 310 of the first electrode 31,
  • the orthographic projection of the recessed portion 61 on the first insulating layer 2 is at least partially located outside the middle portion 310 of the first electrode 31 to reduce or avoid the tip discharge of the recessed portion 61 of the first electrode 31 and the second electrode 6.
  • the material of the second electrode 6 may be an alloy material.
  • the material of the second electrode 6 may include Mg and Ag; or, the second electrode 6 may also be an alloy of Al and Li.
  • the second electrode 6 can also use other alloys or elemental metals, which will not be listed here.
  • the smooth part 62 can be convex in the direction away from the substrate 1 in the area corresponding to the pixel definition layer 4 covering the middle part 310, but the height of the convexity is It is smaller than the thickness of the first middle portion 310 so that the smooth portion 62 is generally smooth.
  • the lowest point of the recess 61 of the second electrode 6 on the cross section perpendicular to the substrate 1 is on the orthographic projection of the first insulating layer 2. It is completely located inside the separation groove 201, that is, completely outside the middle portion 310.
  • the separation groove 201 In order to ensure that the separation groove 201 can cut off the hole injection layer, the charge generation layer 502 or other film layers, the separation groove 201 should be made to have a certain depth, but the separation groove 201 should also be prevented from being too deep to penetrate the first insulating layer 2. And affect the drive device. Therefore, in some embodiments of the present disclosure, in the direction perpendicular to the substrate 1, the maximum depth H of the separation groove 201 is not less than 30% of the sum of the thicknesses of the light-emitting function layer 5 and the first electrode 31; at the same time, the separation groove The maximum depth H of 201 is not more than 60% of the sum of the thickness of the light-emitting function layer 5 and the first electrode 31.
  • the maximum depth of the separation groove 201 is: in the direction perpendicular to the substrate 1 on the bottom wall 2012 of the separation groove 201 and the first insulating layer 2 away from the surface of the substrate 1 the largest distance between the first insulating layer 2 The distance away from the surface of the substrate 1.
  • the maximum depth H of the separation groove 201 is
  • the first type of display panel may further include a first encapsulation layer 13, a color film layer 14, a second encapsulation layer 15, and a transparent cover plate 16, wherein:
  • the first encapsulation layer 13 may cover the second electrode 6.
  • the first encapsulation layer 13 may include two inorganic layers and an organic layer between the two inorganic layers.
  • the first encapsulation layer 13 may be recessed to form a pit 1301 in the region corresponding to the recess 61.
  • the first encapsulation layer 13 is away from the substrate 1
  • the surface can also be roughly flat
  • the color filter layer 14 is disposed on the side of the first encapsulation layer 13 away from the second electrode 6, and the color filter layer 14 includes filter regions corresponding to each first electrode 31 one by one.
  • the color filter regions have multiple colors, such as Red, blue and green.
  • the second encapsulation layer 15 can cover the color filter layer 14, and its structure can be the same as that of the first encapsulation layer 13.
  • the transparent cover plate 16 can cover the second encapsulation layer 15, and its material can be glass or material.
  • the first type of display panel may further include a light extraction layer 17, which covers the surface of the second electrode 6 away from the substrate 1, and is positioned on the surface of the second electrode 6 away from the substrate 1.
  • the area with the recess 61 is recessed, and the first encapsulation layer 13 is provided on the side of the light extraction layer 17 away from the substrate 1.
  • the refractive index of the light extraction layer 17 is greater than that of the second electrode 6, which can improve the light extraction efficiency, and the higher the refractive index, the higher the light extraction efficiency.
  • the second display panel of the present disclosure may include a substrate 1, a first insulating layer 2, a first electrode layer 3, a light-emitting function layer 5, and a second electrode 6, wherein:
  • the first insulating layer 2 is provided on the side of the substrate 1;
  • the first electrode layer 3 is provided on the surface of the first insulating layer 2 facing away from the substrate 1 and includes a plurality of first electrodes 31; the first electrode 31 includes a flat middle portion 310 and an edge portion 311 surrounding the middle portion 310; 311 includes a flat part 3110 surrounding the middle part 310 and a climbing part 3111 connected between the middle part 310 and the flat part 3110.
  • the thickness of the flat part 3110 is smaller than that of the middle part 310.
  • the light-emitting function layer 5 covers at least a part of the middle portion 310.
  • the second electrode 6 covers the light-emitting functional layer 5, and includes a recessed portion 61 and a plurality of smooth portions 62 separated by the recessed portion 61.
  • the orthographic projection of each smooth portion 62 on the first insulating layer 2 is located in each first insulating layer 2 in a one-to-one correspondence.
  • the recessed portion 61 is recessed toward the side of the gentle portion 62 close to the substrate 1, and the orthographic projection of the recessed portion 61 on the first insulating layer 2 is at least partially located outside the middle portion 310.
  • each first electrode 31 and its corresponding light-emitting function layer 5 and second electrode 6 can constitute a light-emitting device, which can emit light.
  • the concave portion 61 and the first electrode can be reduced.
  • the risk of sharp discharge occurring between 31 helps to ensure that the light-emitting device emits light stably.
  • the light emission within the range of the recessed portion 61 can be reduced, thereby reducing the mutual interference of the light emission of adjacent light-emitting devices.
  • a plurality of driving transistors may be provided on the substrate 1 to drive each light-emitting device to emit light to display an image.
  • the display panel further includes a gate insulating layer 7, a gate electrode 8, a second insulating layer 9 and a first wiring layer 10.
  • the material of the substrate 1 can be monocrystalline silicon or Semiconductor materials such as polysilicon, and the substrate 1 may include an active region 101 and a source electrode 1011 and a drain electrode 1012 located at both ends of the active region 101.
  • the gate insulating layer 7 covers the active region 101; the gate 8 is provided on the surface of the gate insulating layer 7 away from the substrate 1.
  • the second insulating layer 9 covers the gate 8 and the substrate 1, and its material may include at least one of silicon oxide and silicon nitride.
  • the first wiring layer 10 is provided on the surface of the second insulating layer 9 away from the substrate 1, and the gate 8, the source 1011 and the drain 1012 are all connected to the first wiring layer 10 through via holes filled with tungsten or other metals .
  • the display panel may further include a third insulating layer 11 and a second wiring layer 12.
  • the third insulating layer 11 covers the first wiring layer 10 and the second insulating layer 9, and the second wiring layer 12 is provided on the third insulating layer.
  • the layer 11 is away from the surface of the substrate 1.
  • the specific pattern of the second wiring layer 12 is not particularly limited here, and it can be connected to the first wiring layer 10 through via holes filled with tungsten or other metals.
  • the first insulating layer 2 is provided on one side of the substrate 1.
  • the first insulating layer 2 can cover the second wiring layer 12, and the first electrode 31 can pass through tungsten. Or other metal-filled vias are connected to the second wiring layer 12.
  • the material of the first insulating layer 2 may include at least one of silicon nitride and silicon oxide, and of course, may also include other insulating materials.
  • the first electrode layer 3 is provided on the side of the first insulating layer 2 away from the substrate 1, and includes a plurality of first electrodes 31, the first electrodes 31 are arranged in an array, and adjacent first electrodes 31 are arranged at intervals .
  • each first electrode 31 may include a middle portion 310 and an edge portion 311 surrounding the middle portion 310, wherein the middle portion 310 is a flat structure, that is, the middle portion 310 is away from the first insulating layer 2
  • the surface of the substrate 1 is approximately parallel.
  • the edge portion 311 may include a flat portion 3110 and a climbing portion 3111.
  • the flat portion 3110 is located on the surface of the first insulating layer 2 facing away from the substrate 1 and arranged around the middle portion 310, and the flat portion 3110 is away from the first insulating layer 2
  • the surface of the substrate 1 is approximately parallel.
  • the thickness of the flat portion 3110 is smaller than the thickness of the middle portion 310.
  • the boundary of the flat portion 3110 may also overlap the boundary of the pixel area 202.
  • the climbing part 3111 is connected between the middle part 310 and the flat part 3110, that is, the climbing part 3111 surrounds the middle part 310, and the flat part 3110 is arranged around the climbing part 3111.
  • the slope of the climbing portion 3111 relative to the surface of the first insulating layer 2 away from the substrate 1 is not less than 30°, and the slope is such that the surface of the climbing portion 3111 and the first insulating layer 2 are away from the liner.
  • the first electrode 31 includes a first conductive layer 320, a second conductive layer 321, and a third conductive layer 322.
  • the first conductive layer 320 is provided on the surface of the first insulating layer 2 away from the substrate 1, and the second conductive layer 321 is provided on the first insulating layer 2.
  • a conductive layer 320 is away from the surface of the substrate 1, and a third conductive layer 322 is provided on the surface of the second conductive layer 321 away from the substrate 1, and extends at a certain slope to the surface of the pixel area 202 where it is away from the substrate 1. , Thereby covering the first conductive layer 320 and the second conductive layer 321 to protect the first conductive layer 320 and the second conductive layer 321.
  • the middle portion 310 of the first electrode 31 includes the third conductive layer 322 in the area of the second conductive layer 321 facing away from the surface of the substrate 1 and the first conductive layer 320 and the second conductive layer 321, and the edge portion 311 includes the third conductive layer 322
  • the area covering the edges of the first conductive layer 320 and the second conductive layer 321 is the area extending toward the first insulating layer 2.
  • the material of the first conductive layer 320 may include titanium (Ti), the material of the second conductive layer 321 includes silver (Ag), and the material of the third conductive layer 322 includes indium tin oxide (ITO). Of course, it may also be Use other materials.
  • the light-emitting function layer 5 may be a continuous film layer, and at the same time cover at least a part of the area of each first electrode 31.
  • the light-emitting functional layer 5 includes a light-emitting unit layer, and the light-emitting unit layer includes a hole injection, a hole transport layer, and a light-emitting layer that are sequentially stacked from the first electrode 31 in a direction away from the substrate 1. , Electron transport layer and electron injection layer.
  • the light-emitting functional layer 5 includes multiple light-emitting unit layers, and the hole injection, hole transport layer, light-emitting layer, electron transport layer, and electron injection layer of each light-emitting unit layer are distributed in the same manner.
  • a charge generation layer is provided between two adjacent light-emitting unit layers, so that the light-emitting unit layers are connected in series through the charge generation layer, so as to form a series-type OLED light-emitting device.
  • the second electrode 6 covers the light-emitting functional layer 5, and a driving signal can be applied to the first electrode 31 and the second electrode 6, so that the light-emitting functional layer 5 is located between the first electrode 31 and the second electrode 6. Glow.
  • the second electrode 6 includes a plurality of recessed portions 61 and a plurality of smooth portions 62, wherein:
  • the smooth portions 62 are distributed in an array and are arranged in a one-to-one correspondence with the middle portion 310 of each first electrode 31, that is, the orthographic projection of each smooth portion 62 on the first insulating layer 2 is located within each first electrode 31 in a one-to-one correspondence.
  • the gentle portion 62 is parallel or substantially parallel to the middle portion 310.
  • the recessed portion 61 corresponds to the area of the first insulating layer 2 that is not covered by the intermediate portion 310, and is used to separate the smooth portion 62, and the recessed portion 61 is recessed toward the side of the smooth portion 62 close to the substrate 1.
  • the recessed portion 61 has a ring structure, and the number is multiple, and each recessed portion 61 surrounds each smooth portion 62 in a one-to-one correspondence, that is, the recessed portion 61 is a transition area of two adjacent smooth portions 62.
  • the orthographic projection of the recess 61 on the substrate 1 is at least partially located outside the middle portion 310 of the first electrode 31, so as to be directly opposite to the area other than the first electrode 31 or the edge portion 311 with a smaller thickness, but not with the larger thickness.
  • the middle portion 310 is directly opposite, which can reduce the risk of tip discharge and short circuit between the recessed portion 61 and the first electrode 31, thereby improving the stability of the light-emitting device.
  • the orthographic projection of the lowest point of the recess 61 on the first insulating layer 2 is located outside the middle part 310, for example, the lowest point and the climbing part 3111 corresponds to one of the flat portions 3110 to avoid the occurrence of tip discharges with the middle portion 310.
  • the lowest point of the recess 61 on the cross section perpendicular to the substrate 1 is: on the cross section perpendicular to the substrate 1, the recess 61 is the closest point to the first electrode 31, that is, the point farthest from the gentle portion 62.
  • the number of recesses 61 in the section perpendicular to the substrate 1 may be multiple, and the lowest point on different sections may be different.
  • the lowest point may be the middle part from the first electrode 31 in the depth direction.
  • the nearest point 310 may also be another point in the depth direction, depending on the position of the cross section perpendicular to the substrate 1.
  • the recess 61 has two side surfaces, including a first side surface 611, a second side surface 612, and a bottom surface 613, wherein the first side surface 611 and the second side surface 612 are arranged oppositely and connected to both sides of the bottom surface 613.
  • the first side surface 611 and the second side surface 612 may shrink in a direction close to the substrate 1.
  • the first side surface 611 and the second side surface 612 may be curved surfaces or flat surfaces, which are not specifically limited here.
  • the bottom surface 613 may be a curved surface convex in a direction away from the substrate 1.
  • the bottom surface 613 of the recess 61 includes a first slope surface 6131, a second slope surface 6132, and a connecting surface 6133, wherein, Both the first slope surface 6131 and the second slope surface 6132 can be curved or flat.
  • the connecting surface 6133 is located on the side of the first side surface 611 and the second side surface 612 facing away from the substrate 1, and the connecting surface 6133 is connected to the first side surface 611 and the second side surface 612. Between the slope surface 6131 and the second slope surface 6132.
  • the first slope surface 6131 is connected to the bottom edge of the first side surface 611
  • the second slope surface 6132 is connected to the bottom edge of the second side surface 612.
  • the slope of the first slope surface 6131 relative to the middle portion 310 is not less than the slope of the first side surface 611 relative to the middle portion 310.
  • the slope of the second slope surface 6132 relative to the middle portion 310 is not less than the slope of the second side surface 612 relative to the middle portion 310.
  • the first slope surface 6131 and the second slope surface 6132 are symmetrical with respect to the connecting surface 6133, that is, the cross section of the first slope surface 6131 perpendicular to the substrate 1 and the second slope surface 6132
  • the cross-section perpendicular to the substrate 1 is symmetrical with respect to the cross-section perpendicular to the substrate 1 of the connection surface 6133.
  • the first side surface 611 and the second side surface 612 are symmetrical with respect to the bottom surface 613, that is, the cross section of the first side surface 611 is perpendicular to the substrate 1 and the second side surface 612 is perpendicular to the substrate 1.
  • the cross section of is symmetrical with respect to the cross section of the bottom surface 613 perpendicular to the substrate 1.
  • the minimum thickness of the area of the second electrode 6 corresponding to the first side surface 611 and the second side surface 612 is larger than the area of the second electrode 6 corresponding to the first slope surface 6131 and the second slope surface 6132 The minimum thickness.
  • the depth of the recess 61 is less than twice the maximum thickness of the second electrode 6.
  • the maximum thickness of the second electrode 6 is 90 nm
  • the recess 61 The depth of 61 is less than 180 nm, such as 120 nm, 100 nm, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm, and so on.
  • the depth of the recessed portion 61 refers to the maximum depth of the recessed portion 61, that is, in the direction perpendicular to the substrate 1, the distance between the closest point of the recessed portion 61 to the substrate 1 and the surface of the smooth portion 62 away from the substrate 1.
  • the orthographic projection of each recess 61 on the first insulating layer 2 surrounds the middle portion 310 of a first electrode 31, and the bottom surface of the recess 61
  • the minimum value of the distance between 613 and the intermediate portion 310 of the adjacent first electrode 31 is not less than the flat portion 62 and 70% of the total thickness of the light-emitting functional layer 5, the total thickness of the smooth portion 62 and the light-emitting functional layer 5 is the sum of the thickness of the smooth portion 62 and the light-emitting functional layer 5, for example, the total of the smooth portion 62 and the light-emitting functional layer 5
  • the thickness is about 365 nm, and the minimum value of the distance between the bottom of the recess 61 in the direction perpendicular to the substrate 1 and the middle portion 310 of the adjacent first electrode
  • the maximum value of the distance between the bottom of the recess 61 and the middle part 310 of the adjacent first electrode 31 is not less than 400nm, and the maximum value is not greater than 450nm.
  • a plurality of separation grooves 201 may be provided on the surface of the first insulating layer 2 away from the substrate 1, and the depth of the separation groove 201 is It is smaller than the thickness of the first insulating layer 2, that is, the separation groove 201 does not penetrate the first insulating layer 2 in the depth direction.
  • a plurality of pixel regions 202 can be divided on the first insulating layer 2 by the separation grooves 201, and the pixel regions 202 are arranged in an array.
  • the specific structure of the partition groove 201 can refer to the above-mentioned first implementation of the display panel, which will not be described in detail here.
  • the second display panel of the present disclosure further includes a pixel definition layer 4, which is made of insulating material, and is provided with the first electrode layer 3 on the surface of the first insulating layer 2 away from the substrate 1.
  • the pixel definition layer 4 exposes at least part of the area of the middle portion 310 of the first electrode 31 and is recessed in the area corresponding to the separation groove 201.
  • the middle portion 310 exposed by the pixel definition layer 4 can be connected to the corresponding light emitting function layer 5 and
  • the second electrode 6 constitutes a light emitting device.
  • the structure of the pixel definition layer 4 can refer to the implementation of the first display panel described above, which will not be described in detail here.
  • the light-emitting functional layer 5 also covers the pixel defining layer 4 and the area of the first insulating layer 2 not covered by the pixel defining layer 4 and the first electrode 31.
  • the light-emitting functional layer 5 is The area corresponding to the separation groove 201 is recessed toward the direction of the substrate 1.
  • the recess 61 of the second electrode 6 is at least partially located within the range of the separation groove 201 in the orthographic projection of the first insulating layer 2.
  • the first display panel of the present disclosure may further include a first encapsulation layer 13, and the first encapsulation layer 13 may cover the second electrode 6.
  • the first encapsulation layer 13 may include two layers. The inorganic layer and the organic layer between the two inorganic layers. The first encapsulation layer 13 forms a pit 1301 in an area corresponding to the recess 61, the two sidewalls of the pit 1301 are narrowed toward the substrate 1, and the two sidewalls are connected.
  • the display panel may further include a color film layer 14, a second encapsulation layer 15, and a transparent cover plate 16, wherein:
  • the color filter layer 14 is disposed on the side of the first encapsulation layer 13 away from the second electrode 6, and the color filter layer 14 includes filter regions corresponding to each first electrode 31 one by one.
  • the color filter regions have multiple colors, such as Red, blue and green.
  • the second encapsulation layer 15 can cover the color filter layer 14, and its structure can be the same as that of the first encapsulation layer 13.
  • the transparent cover plate 16 can cover the second encapsulation layer 15, and its material can be glass or material.
  • the second type of display panel may further include a light extraction layer 17, which covers the surface of the second electrode 6 facing away from the substrate 1
  • the area with the recess 61 is recessed, and the first encapsulation layer 13 is provided on the side of the light extraction layer 17 away from the substrate 1.
  • the refractive index of the light extraction layer 17 is greater than that of the second electrode 6, which can improve the light extraction efficiency, and the higher the refractive index, the higher the light extraction efficiency.
  • the display panel may include a substrate 1, a first insulating layer 2, a first electrode layer 3, a pixel definition layer 4, a light-emitting function layer 5 and a second electrode 6, wherein:
  • the first insulating layer 2 is disposed on one side of the substrate 1, and the first insulating layer 2 has a plurality of pixel regions 202 distributed in an array and a partition region 201 that separates the pixel regions 202.
  • the first electrode layer 3 is disposed on the surface of the first insulating layer 2 away from the substrate 1 and includes a plurality of first electrodes 31 distributed in an array.
  • the orthographic projection of each first electrode 31 on the first insulating layer 2 is located in each pixel area 202 Within.
  • the pixel definition layer 4 is provided on the surface of the first insulating layer 2 away from the substrate 1 and exposes the first electrodes 31;
  • the middle part has a first protrusion 42 protruding in a direction away from the substrate 1, and a sub-groove 40 is formed between the side wall of the first protrusion 42 and the side wall of the pixel defining groove 41.
  • the light-emitting function layer 5 covers the pixel defining layer 4 and the first electrode 31 exposed by the pixel defining layer 4.
  • the second electrode 6 covers the light-emitting function layer 5.
  • the middle of the pixel defining groove 41 in this article refers to any area of the bottom surface between the two side walls of the pixel defining groove 41, and is not limited to the distance between the two side walls of the pixel defining groove 41 and the two side walls. Equal areas.
  • each first electrode 31 exposed by the pixel defining layer 4 and the corresponding light-emitting function layer 5 and second electrode 6 can be used to form a light-emitting device to emit light.
  • the pixel defining groove 41 is located outside the first electrode 31.
  • the light emitting function layer 5 can be placed in the pixel defining groove.
  • the position of 41 is recessed toward the substrate 1, so that the recess 61 formed by the second electrode 6 in the recess, and the orthographic projection of the recess 61 on the first insulating layer 2 is at least partially within the range of the pixel definition layer 4, at least Part of it is located outside the light-emitting device.
  • the position of the recess 61 of the second electrode 6 can be restricted by the pixel defining groove 41 to prevent sharp discharge or even short circuit between the recess 61 and the first electrode 31, which is beneficial to ensure The light-emitting device emits light stably. At the same time, light emission within the range of the recess 61 can be reduced or even avoided, thereby reducing the mutual interference of the light emission of adjacent light-emitting devices.
  • the sub-groove 40 is formed between the first protrusion 42 in the middle of the pixel defining groove 41 and the sidewall of the pixel defining groove 41, the topography of the middle of the pixel defining groove 41 is uneven. If the light-emitting function layer 5 contains charge generation Therefore, it is difficult for the charge generation layer to be formed on the sidewalls of the two sub-grooves 40, which facilitates the truncation of the charge generation layer pixel defining groove 41 and avoids crosstalk between two adjacent light-emitting devices. Of course, the sub-groove 40 of the pixel defining groove 41 can also cut off the hole injection layer or other film layers, which can also prevent crosstalk.
  • the material of the substrate 1 may be a semiconductor material such as monocrystalline silicon or polycrystalline silicon, or other hard or soft materials such as glass.
  • a plurality of driving transistors may be provided on the substrate 1 to drive each light-emitting device to emit light to display an image.
  • the display panel further includes a gate insulating layer 7, a gate electrode 8, a second insulating layer 9 and a first wiring layer 10.
  • the material of the substrate 1 can be monocrystalline silicon or Semiconductor materials such as polysilicon, and the substrate 1 includes an active region 101 and a source electrode 1011 and a drain electrode 1012 located at both ends of the active region 101.
  • the gate insulating layer 7 covers the active region 101; the gate 8 is provided on the surface of the gate insulating layer 7 away from the substrate 1, and the material of the gate 8 may include polysilicon material.
  • the second insulating layer 9 covers the gate 8 and the substrate 1, and its material may include at least one of silicon oxide and silicon nitride.
  • the first wiring layer 10 is provided on the surface of the second insulating layer 9 away from the substrate 1, and the gate 8, the source 1011 and the drain 1012 are all connected to the first wiring layer 10 through via holes filled with tungsten or other metals .
  • the display panel may further include a third insulating layer 11 and a second wiring layer 12.
  • the third insulating layer 11 covers the first wiring layer 10 and the second insulating layer 9, and the second wiring layer 12 is provided on the third insulating layer.
  • the layer 11 is away from the surface of the substrate 1.
  • the specific pattern of the second wiring layer 12 is not particularly limited here, and it can be connected to the first wiring layer 10 through via holes filled with tungsten or other metals.
  • the first insulating layer 2 is provided on one side of the substrate 1.
  • the first insulating layer 2 can cover the second wiring layer 12, and the first electrode 31 can pass through tungsten. Or other metal-filled vias are connected to the second wiring layer 12.
  • the material of the first insulating layer 2 may include at least one of silicon nitride and silicon oxide, and of course, may also include other insulating materials.
  • the first insulating layer 2 can be planarized by a polishing process.
  • the first insulating layer 2 can be divided into a plurality of pixel regions 202, and the pixel regions 202 are arranged in an array and arranged at intervals.
  • the area outside the driving area 201 is the partition area 201, so that the pixel area 202 is separated by the partition area 201.
  • the shape of the orthographic projection of the pixel area 202 on the substrate 1 may be a rectangle, a pentagon, a hexagon or other polygons, of course, it may also be a circle or other shapes, which is not specifically limited here. At the same time, the shape and size of different pixel regions 202 may be different.
  • the partition 201 may include a first partition and a second partition, wherein the number of the first partition is multiple, and each first partition extends linearly along the first direction. , And distributed along the second direction at intervals; the number of second partitions is multiple, and each second partition extends linearly along the second direction, and is distributed at intervals along the first direction; the first direction and the second direction intersect each other
  • the first direction and the second direction are mutually perpendicular directions.
  • a plurality of pixel regions 202 distributed in an array can be divided on the first insulating layer 2 by the staggered first partition region and the second partition region.
  • the first separation area and the second separation area may also extend along a curved or broken line track, thereby dividing the pixel area 202 of other shapes.
  • the first electrode layer 3 is provided on the surface of the first insulating layer 2 away from the substrate 1, and includes a plurality of first electrodes 31 distributed in an array.
  • the projections are located within each pixel area 202 in a one-to-one correspondence, that is, the boundary of the orthographic projection of each first electrode 31 on the substrate 1 is located within the boundary of the orthographic projection of each pixel area 202 on the substrate 1 in a one-to-one correspondence.
  • Only one first electrode 31 is provided on each pixel area 202. Since the pixel area 202 is formed by the separation area 201 and the first electrode 31 is located on the pixel area 202, the separation area 201 is located outside the first electrode 31.
  • the shape of the orthographic projection of each first electrode 31 on the first insulating layer 2 may be the same as the shape of the pixel area 202 where it is located, and the boundary of the first electrode 31 is located within the pixel area 202 where it is located.
  • the at least one first electrode 31 may include an intermediate portion 310 and an edge portion 311 surrounding the intermediate portion 310, wherein the intermediate portion 310 is a flat structure, that is, the intermediate portion 310 is away from the first insulating layer 2
  • the surface of the substrate 1 is approximately parallel.
  • the boundary of the orthographic projection of the intermediate portion 310 of each first electrode 31 on the substrate 1 may be located within the boundary of the orthographic projection of the pixel area 202 on the substrate 1, that is, the middle
  • the boundary of the orthographic projection of the portion 310 on the substrate 1 and the boundary of the orthographic projection of the pixel area 202 on the substrate 1 has a distance L that is not zero. Further, the distance L is not less than 0.15 ⁇ m, for example, the distance L may be 0.15 ⁇ m, 0.2 ⁇ m, 0.25 ⁇ m, or the like.
  • the edge portion 311 may include a flat portion 3110 and a climbing portion 3111.
  • the flat portion 3110 is located on the surface of the first insulating layer 2 facing away from the substrate 1 and arranged around the middle portion 310, and the flat portion 3110 is away from the first insulating layer 2
  • the surface of the substrate 1 is approximately parallel.
  • the thickness of the flat portion 3110 is smaller than the thickness of the middle portion 310.
  • the flat portion 3110 has a non-zero distance between the boundary of the orthographic projection of the substrate 1 and the boundary of the pixel region 202 on the substrate 1 where it is located.
  • the boundary of the orthographic projection of the flat portion 3110 on the substrate 1 overlaps the boundary of the orthographic projection of the pixel region 202 on the substrate 1 where it is located.
  • the climbing part 3111 is connected between the middle part 310 and the flat part 3110, that is, the climbing part 3111 surrounds the middle part 310, and the flat part 3110 is arranged around the climbing part 3111.
  • the slope of the climbing portion 3111 relative to the surface of the first insulating layer 2 away from the substrate 1 is not less than 30°, and the slope is such that the surface of the climbing portion 3111 and the first insulating layer 2 are away from the liner.
  • the first electrode 31 may include a first conductive layer 320, a second conductive layer 321, and a third conductive layer 322.
  • the first conductive layer 320 is provided on the surface of the first insulating layer 2 away from the substrate 1, and the second conductive layer 321 is provided on The first conductive layer 320 is away from the surface of the substrate 1, and the third conductive layer 322 is provided on the surface of the second conductive layer 321 away from the substrate 1, and extends to the first insulating layer 2 at a certain slope, thereby covering the first conductive layer.
  • the layer 320 and the second conductive layer 321 protect the first conductive layer 320 and the second conductive layer 321.
  • the middle portion 310 of the first electrode 31 includes the third conductive layer 322 in the area of the second conductive layer 321 facing away from the surface of the substrate 1 and the first conductive layer 320 and the second conductive layer 321, and the edge portion 311 includes the third conductive layer 322
  • the area covering the edges of the first conductive layer 320 and the second conductive layer 321 is the area extending toward the first insulating layer 2.
  • the material of the first conductive layer 320 may include titanium (Ti), the material of the second conductive layer 321 includes silver (Ag), and the material of the third conductive layer 322 includes indium tin oxide (ITO). Of course, it may also be Use other materials.
  • the pixel definition layer 4 is made of insulating material, and is provided on the surface of the first insulating layer 2 away from the substrate 1 with the first electrode layer 3, and at least part of the area of the first electrode 31 is exposed.
  • the pixel definition layer 4 is provided with a plurality of openings 401 that expose at least a part of the middle portion 310 in a one-to-one correspondence.
  • the first electrode 31 exposed by the pixel defining layer 4 can form a light emitting device with the corresponding light emitting function layer 5 and the second electrode 6.
  • the opening 401 of the pixel definition layer 4 may have a hexagonal or other polygonal structure, and the first electrode 31 may also have a polygonal structure and have the same shape as the opening 401.
  • the first electrode 31 Other shapes are also possible. For details, please refer to the implementation of the first display panel in FIG. 5 and FIG. 6.
  • the pixel definition layer 4 is formed with a pixel definition groove 41 in a region corresponding to the partition area 201, and the pixel definition groove 41 may be formed when the pixel definition layer 4 is formed by a photolithography process.
  • the pixel definition layer 4 may be recessed at the separation groove by providing a separation groove in the separation area 201 of the first insulating layer 2 to form the pixel definition groove 41.
  • the pixel definition layer 4 may include a spacer 400 and an extension 410, wherein the spacer 400 is located in an area of the first insulating layer 2 not covered by the first electrode 31, that is, located on the first electrode 31. In other areas, the pixel defining groove 41 is provided in the spacer 400.
  • the extension portion 410 is connected to the spacer portion 400 and extends to the surface of the first electrode 31 facing away from the substrate 1 and does not completely cover the first electrode 31. For example, the extension portion 410 extends to the middle portion 31 along the circumferential direction of the first electrode 31 The circumferential direction of 310 is away from the surface of the substrate 1 and does not completely cover the middle portion 310 to form an opening 401.
  • the width of the extension 410 covering any one of the first electrodes 31 is smaller than the width of the spacer 400 between two adjacent first electrodes 31. That is to say, for any first electrode 31, the area of the extension 410 on the surface of the first electrode 31 facing away from the substrate 1 has a ring structure, and the width of the ring structure is smaller than that adjacent to the first electrode 31
  • the width of the spacer 400 is the width of the ring structure as the distance between the two side walls.
  • the middle of the pixel defining groove 41 may have a first protrusion 42 protruding in a direction away from the substrate 1, and the sidewall of the first protrusion 42 is between the sidewall of the pixel defining groove 41
  • the sub-groove 40 is formed.
  • the first protrusion 42 can make the topography of the middle part of the pixel defining groove 41 more complicated, which is beneficial to break the charge generation layer or other film layers of the upper light-emitting functional layer 5 To prevent crosstalk between adjacent light-emitting devices.
  • the middle part of the sub-slot 40 herein refers to any area of the bottom surface between the two side walls of the sub-slot 40, and is not limited to the area where the distance between the two side walls of the sub-slot 40 is equal to the two side walls. .
  • the two side walls of the first protrusion 42 are inclined surfaces that expand toward the substrate 1, and the two side walls of the pixel defining groove 41 are inclined surfaces that shrink toward the substrate 1, that is, the first The distance between the two sidewalls of the protrusion 42 gradually increases toward the substrate 1, and the distance between the two sidewalls of the pixel defining groove 41 gradually decreases toward the substrate 1.
  • the sub-groove 40 is a groove whose two side walls shrink toward the substrate 1.
  • the slope of the side wall of the first protrusion 42 is different from the slope of the side wall of the pixel defining groove 41.
  • the slope of the sidewall of the first protrusion 42 is the angle between the sidewall of the first protrusion 42 and the surface of the first insulating layer 2 away from the substrate 1, and the slope of the sidewall of the pixel defining groove 41 is that of the pixel defining groove 41 The angle between the sidewall and the surface of the first insulating layer 2 away from the substrate 1.
  • the slope of the two is the angle between each section of the arc surface and the surface of the first insulating layer 2 away from the substrate 1. The maximum or average value of.
  • the thickness of the first protrusion 42 may be smaller than the depth of the pixel defining groove 41, so that the first protrusion 42 does not protrude from the surface of the first insulating layer 2 away from the substrate 1 but is completely located within the pixel defining groove 41.
  • the light-emitting function layer 5 may be a continuous film layer, and at least partially cover the middle portion 310 of each first electrode 31, that is, cover the area exposed by the opening 401. At the same time, the light-emitting function layer 5 may also cover the pixels. At least part of the area of the definition layer 4, when the light-emitting function layer 5 is formed by evaporation or other processes, the light-emitting function layer 5 is recessed in the direction close to the substrate 1 in the area corresponding to the pixel definition groove 41.
  • the light-emitting function layer 5 includes a multi-layer light-emitting unit layer 501, and the hole injection layer, the hole transport layer, the light-emitting layer, and the electron transport layer of each light-emitting unit layer 501 Same as the distribution of the electron injection layer.
  • a charge generation layer 502 is provided between two adjacent light-emitting unit layers 501, so that the light-emitting unit layers 501 are connected in series through the charge generation layer 502, so as to form a series-type OLED light-emitting device.
  • the light-emitting function layer 5 includes a light-emitting unit layer, and the light-emitting unit layer includes a hole injection layer, a hole transport layer, Emitting layer, electron transport layer and electron injection layer.
  • the charge generation layer 502 is difficult to cover the sidewalls of the sub-groove 40 of the pixel defining groove 41, so that the charge generating layer 502 of the light emitting device can be cut off by the pixel defining groove 41 to avoid crosstalk between two adjacent light emitting devices.
  • the pixel defining groove 41 can also cut off the hole injection layer or other film layers, which can also prevent crosstalk.
  • the light-emitting function layer 5 is a continuous film layer, but not every film layer is a continuous film layer.
  • the light-emitting layer of the light-emitting functional layer 5 may include a plurality of light-emitting parts distributed at intervals, and each light-emitting part is located in an opening 401, so that each light-emitting device has an independent light-emitting part.
  • the materials of different light-emitting parts can be different, so that the light-emitting colors of different light-emitting devices can be different, and the other film layers of the light-emitting functional layer 5 can be the aforementioned continuous film layers, that is, each light-emitting device can share these continuous film layers.
  • the second electrode 6 covers the light-emitting functional layer 5, and a driving signal can be applied to the first electrode 31 and the second electrode 6, so that the light-emitting functional layer 5 is located between the first electrode 31 and the second electrode 6. Glow.
  • the second electrode 6 and the first electrode 31 There is a certain distance between the second electrode 6 and the first electrode 31, so that a microcavity can be formed.
  • the light emitted by the light-emitting function layer 5 will be reflected to a certain extent at the first electrode 31 and the second electrode 6, and the light wavelength
  • the light is strengthened according to the principle of expansion interference, which is beneficial to improve the brightness of the light-emitting device.
  • the depth of the microcavity of light-emitting devices with different light-emitting colors may be different.
  • the light-emitting colors of the light-emitting layers of different light-emitting devices may be different.
  • the thickness of the first electrode 31 of the light-emitting devices of different light-emitting colors may be different. , So as to match the depth of the microcavity with the wavelength of the light. The longer the wavelength of light emission, the greater the depth of the microcavity.
  • the first electrode 31 includes a first conductive layer 320, a second conductive layer 321, and a third conductive layer 322.
  • the first conductive layer 320 may be a reflective material, and the depth of the microcavity may be between the first conductive layer 320 and the second conductive layer 320.
  • the thickness of the first conductive layer 320 of the two first electrodes 31 can be different, while the thickness of the second conductive layer 321 is the same, and the thickness of the third conductive layer 322 is also the same, so that the thickness of the two first electrodes 31 is different.
  • the morphology of the second electrode 6 matches that of the light-emitting functional layer 5, which is recessed in the recess of the light-emitting functional layer 5 to form a recess 61, and a smooth portion 62 is formed in the region corresponding to the middle portion 310 of the first electrode 31,
  • the orthographic projection of the recessed portion 61 on the first insulating layer 2 is at least partially located outside the middle portion 310 of the first electrode 31 to reduce or avoid the tip discharge of the recessed portion 61 of the first electrode 31 and the second electrode 6.
  • the material of the second electrode 6 may be an alloy material.
  • the material of the second electrode 6 may include Mg and Ag; or, the second electrode 6 may also be an alloy of Al and Li.
  • the second electrode 6 can also use other alloys or elemental metals, which will not be listed here.
  • the extension portion 410 of the pixel definition layer 4 covers the edge of the middle portion 310, and the second electrode 6 may protrude in a direction away from the substrate 1 in the region corresponding to the extension portion 410, but is protruding.
  • the height of is smaller than the thickness of the middle portion 310, so that the joint between the smooth portion 62 and the recessed portion 61 is generally smooth.
  • the lowest point of the recess 61 of the second electrode 6 on the cross section perpendicular to the substrate 1 is on the orthographic projection of the first insulating layer 2. It is completely inside the pixel defining groove 41, that is, completely outside the middle portion 310.
  • the third display panel may further include a first encapsulation layer 13, a color film layer 14, a second encapsulation layer 15, and a transparent cover plate 16. in:
  • the first encapsulation layer 13 may cover the second electrode 6.
  • the first encapsulation layer 13 may include two inorganic layers and an organic layer between the two inorganic layers.
  • the first encapsulation layer 13 may be recessed to form a pit 1301 in the region corresponding to the recess 61.
  • the first encapsulation layer 13 is away from the substrate 1 The surface can also remain substantially flat.
  • the color filter layer 14 is disposed on the side of the first encapsulation layer 13 away from the second electrode 6, and the color filter layer 14 includes filter regions corresponding to each first electrode 31 one by one.
  • the color filter regions have multiple colors, such as Red, blue and green.
  • the second encapsulation layer 15 can cover the color filter layer 14, and its structure can be the same as that of the first encapsulation layer 13.
  • the transparent cover plate 16 can cover the second encapsulation layer 15, and its material can be glass or material.
  • the third display panel may further include a light extraction layer 17, which covers the surface of the second electrode 6 facing away from the substrate 1. And the area corresponding to the recess 61 is recessed, and the first encapsulation layer 13 is provided on the side of the light extraction layer 17 away from the substrate 1.
  • the refractive index of the light extraction layer 17 is greater than that of the second electrode 6, which can improve the light extraction efficiency, and the higher the refractive index, the higher the light extraction efficiency.
  • the display panel may include a substrate 1, a first insulating layer 2, a first electrode layer 3, a pixel definition layer 4, a light-emitting function layer 5, and a second electrode 6, wherein:
  • the first insulating layer 2 is provided on the side of the substrate 1.
  • the first electrode layer 3 is disposed on the surface of the first insulating layer 2 away from the substrate 1 and includes a plurality of first electrodes 31 distributed in an array.
  • the pixel definition layer 4 is disposed on the surface of the first insulating layer 2 away from the substrate 1 and exposes the first electrodes 31.
  • the light-emitting function layer 5 covers the pixel defining layer 4 and the first electrode 31 and the first insulating layer 2 exposed by the pixel defining layer 4.
  • the second electrode 6 covers the light-emitting function layer 5, and includes a recessed portion 61 and a plurality of smooth portions 62 separated by the recessed portion 61, and the orthographic projection of each smooth portion 62 on the first insulating layer 2 is located within each first electrode 31; At least part of the recessed portion 61 is recessed toward the side of the smooth portion 62 close to the substrate 1, the orthographic projection of the recessed portion 61 on the first insulating layer 2 is at least partially located in the pixel defining groove 41, and the middle of the recessed portion 61 corresponds to the first insulating layer 2
  • the position of a protrusion 42 has a second protrusion 600, and a sub-recess 610 is formed between the side surface of the second protrusion 600 and the side surface of the recess 61.
  • the middle part of the recess 61 in this text refers to any area of the bottom surface between the two side walls of the recess 61, and is not limited to the area where the distance between the two side walls of the recess 61 is equal to the two side walls. .
  • each first electrode 31 exposed by the pixel defining layer 4 and the corresponding light-emitting function layer 5 and second electrode 6 can constitute a light-emitting device to emit light. Since the recess 61 of the second electrode 6 is at least partially located outside the first electrode in the orthographic projection of the first insulating layer 2, it can prevent tip discharge or even short circuit between the recess 61 and the first electrode 31, which is beneficial to ensure the light emitting device Stable light. At the same time, light emission within the range of the recess 61 can be reduced or even avoided, thereby reducing the mutual interference of the light emission of adjacent light-emitting devices.
  • a plurality of driving transistors may be provided on the substrate 1 for driving each light-emitting device to emit light to display an image.
  • the display panel further includes a gate insulating layer 7, a gate electrode 8, a second insulating layer 9 and a first wiring layer 10.
  • the material of the substrate 1 can be monocrystalline silicon or Semiconductor materials such as polysilicon, and the substrate 1 includes an active region 101 and a source electrode 1011 and a drain electrode 1012 located at both ends of the active region 101.
  • the gate insulating layer 7 covers the active region 101; the gate 8 is provided on the surface of the gate insulating layer 7 away from the substrate 1, and the material of the gate 8 may include polysilicon material.
  • the second insulating layer 9 covers the gate 8 and the substrate 1, and its material may include at least one of silicon oxide and silicon nitride.
  • the first wiring layer 10 is provided on the surface of the second insulating layer 9 away from the substrate 1, and the gate 8, the source 1011 and the drain 1012 are all connected to the first wiring layer 10 through via holes filled with tungsten or other metals .
  • the display panel may further include a third insulating layer 11 and a second wiring layer 12.
  • the third insulating layer 11 covers the first wiring layer 10 and the second insulating layer 9, and the second wiring layer 12 is provided on the third insulating layer.
  • the layer 11 is away from the surface of the substrate 1.
  • the specific pattern of the second wiring layer 12 is not particularly limited here, and it can be connected to the first wiring layer 10 through via holes filled with tungsten or other metals.
  • the first insulating layer 2 is provided on one side of the substrate 1.
  • the first insulating layer 2 can cover the second wiring layer 12, and the first electrode 31
  • the second wiring layer 12 may be connected to the second wiring layer 12 through vias filled with tungsten or other metals.
  • the material of the first insulating layer 2 may include at least one of silicon nitride and silicon oxide, and of course, may also include other insulating materials.
  • the first insulating layer 2 can be planarized by a polishing process.
  • the first insulating layer 2 has a partition area 201 through which a plurality of pixel areas 202 can be partitioned on the first insulating layer 2, and the pixel areas 202 are arranged in an array.
  • the first electrode layer 3 is disposed on the surface of the first insulating layer 2 away from the substrate 1 and includes a plurality of first electrodes 31 distributed in an array.
  • the orthographic projection of each first electrode 31 on the first insulating layer 2 is located within each pixel region 202 in a one-to-one correspondence, that is, the boundary of the orthographic projection of each first electrode 31 on the substrate 1 is one-to-one. A corresponding one is located within the boundary of the orthographic projection of each pixel area 202 on the substrate 1. Only one first electrode 31 is provided on each pixel area 202. Since the pixel area 202 is formed by the separation area 201 and the first electrode 31 is located on the pixel area 202, the separation area 201 is located outside the first electrode 31.
  • the shape of the orthographic projection of each first electrode 31 on the first insulating layer 2 may be the same as the shape of the pixel area 202 where it is located, and the boundary of the first electrode 31 is located within the pixel area 202 where it is located.
  • the at least one first electrode 31 may include an intermediate portion 310 and an edge portion 311 surrounding the intermediate portion 310, wherein the intermediate portion 310 is a flat structure, that is, the intermediate portion 310 is away from the first insulating layer 2
  • the surface of the substrate 1 is approximately parallel.
  • the boundary of the orthographic projection of the intermediate portion 310 of each first electrode 31 on the substrate 1 may be located within the boundary of the orthographic projection of the pixel area 202 on the substrate 1, that is, the middle
  • the boundary of the orthographic projection of the portion 310 on the substrate 1 and the boundary of the orthographic projection of the pixel region 202 on the substrate 1 where it is located has a distance L that is not zero.
  • the distance L is not less than 0.15 ⁇ m, for example, the distance L may be 0.15 ⁇ m, 0.2 ⁇ m, 0.25 ⁇ m, or the like.
  • the edge portion 311 may include a flat portion 3110 and a climbing portion 3111.
  • the flat portion 3110 is located on the surface of the first insulating layer 2 facing away from the substrate 1 and arranged around the middle portion 310, and the flat portion 3110 is away from the first insulating layer 2
  • the surface of the substrate 1 is approximately parallel.
  • the thickness of the flat portion 3110 is smaller than the thickness of the middle portion 310.
  • the flat portion 3110 has a non-zero distance between the boundary of the orthographic projection of the substrate 1 and the boundary of the pixel region 202 on the substrate 1 where it is located.
  • the boundary of the orthographic projection of the flat portion 3110 on the substrate 1 overlaps the boundary of the orthographic projection of the pixel region 202 on the substrate 1 where it is located.
  • the climbing part 3111 is connected between the middle part 310 and the flat part 3110, that is, the climbing part 3111 surrounds the middle part 310, and the flat part 3110 is arranged around the climbing part 3111.
  • the slope of the climbing portion 3111 relative to the surface of the first insulating layer 2 away from the substrate 1 is not less than 30°, and the slope is such that the surface of the climbing portion 3111 and the first insulating layer 2 are away from the liner.
  • the first electrode 31 may include a first conductive layer 320, a second conductive layer 321, and a third conductive layer 322.
  • the first conductive layer 320 is disposed on the first insulating layer 2 away from the substrate 1.
  • the second conductive layer 321 is provided on the surface of the first conductive layer 320 away from the substrate 1
  • the third conductive layer 322 is provided on the surface of the second conductive layer 321 away from the substrate 1, and extends to the first insulating layer at a certain slope.
  • Layer 2 thus covers the first conductive layer 320 and the second conductive layer 321, and protects the first conductive layer 320 and the second conductive layer 321.
  • the middle portion 310 of the first electrode 31 includes the third conductive layer 322 in the area of the second conductive layer 321 facing away from the surface of the substrate 1 and the first conductive layer 320 and the second conductive layer 321, and the edge portion 311 includes the third conductive layer 322
  • the area covering the edges of the first conductive layer 320 and the second conductive layer 321 is the area extending toward the first insulating layer 2.
  • the material of the first conductive layer 320 may include titanium (Ti), the material of the second conductive layer 321 includes silver (Ag), and the material of the third conductive layer 322 includes indium tin oxide (ITO). Of course, it may also be Use other materials.
  • the pixel definition layer 4 is made of insulating material, and is provided on the surface of the first insulating layer 2 away from the substrate 1 with the first electrode layer 3, and at least a part of the first electrode 31 is exposed.
  • the pixel definition layer 4 is provided with a plurality of openings 401 that expose at least a part of the middle portion 310 in a one-to-one correspondence.
  • the first electrode 31 exposed by the pixel defining layer 4 can form a light emitting device with the corresponding light emitting function layer 5 and the second electrode 6.
  • the opening 401 of the pixel definition layer 4 may have a hexagonal or other polygonal structure, and the first electrode 31 may also have a polygonal structure and have the same shape as the opening 401.
  • the first electrode 31 It may also have other shapes.
  • the area of the pixel definition layer 4 corresponding to the partition area 201 is formed with a pixel definition groove 41.
  • the middle of the pixel defining groove 41 may have a first protrusion 42 protruding in a direction away from the substrate 1, and the sidewall of the first protrusion 42 is between the sidewall of the pixel defining groove 41
  • the sub-groove 40 is formed.
  • the first protrusion 42 can make the topography of the middle part of the pixel defining groove 41 more complicated, which is beneficial to break the charge generation layer or other film layers of the upper light-emitting functional layer 5 To prevent crosstalk between adjacent light-emitting devices.
  • the middle of the pixel definition groove 41 can be located in the separation area 201, that is, the pixel definition groove 41 is a point or more closest to the substrate 1.
  • the point is located on the side of the first insulating layer 2 facing away from the substrate 1 and close to the substrate 1.
  • the middle of the sub-tank 40 is located in the partition area 201.
  • the detailed structure of the pixel definition layer 4 and the pixel definition groove 41 can refer to the above-mentioned third display panel implementation, which will not be described in detail here.
  • the light-emitting functional layer 5 can be a continuous film layer, and at least partially covers the middle portion 310 of each first electrode 31, that is, covers the area exposed by the opening 401, and at the same time, the light-emitting functional layer 5 also Covers the pixel defining layer 4 and the area of the first insulating layer 2 not covered by the pixel defining layer 4 and the first electrode 31.
  • the light-emitting functional layer 5 is formed by evaporation or other processes, the light-emitting functional layer 5 is located in the corresponding pixel defining groove 41 The area is recessed toward the direction of the substrate 1.
  • the hole transport layer, the light emitting layer, the electron transport layer and the electron injection layer are distributed in the same way.
  • a charge generation layer 502 is provided between two adjacent light-emitting unit layers 501, so that the light-emitting unit layers 501 are connected in series through the charge generation layer 502, so as to form a series-type OLED light-emitting device.
  • the light-emitting function layer 5 includes a light-emitting unit layer, and the light-emitting unit layer includes a hole injection layer, a hole transport layer, Emitting layer, electron transport layer and electron injection layer.
  • the charge generation layer 502 is difficult to cover the sidewalls of the sub-groove 40 of the pixel defining groove 41, so that the charge generating layer 502 of the light emitting device can be cut off by the pixel defining groove 41 to avoid crosstalk between two adjacent light emitting devices.
  • the pixel defining groove 41 can also cut off the hole injection layer or other film layers, which can also prevent crosstalk.
  • the second electrode 6 covers the light-emitting functional layer 5, and includes a recessed portion 61 and a plurality of smooth portions 62 separated by the recessed portion 61, and each smooth portion 62 is positioned on the first insulating layer 2
  • the projections are located within each first electrode 31 in a one-to-one correspondence; the recessed portion 61 is recessed toward the side of the smooth portion 62 close to the substrate 1, and the orthographic projection of the recessed portion 61 on the first insulating layer 2 is at least partially located outside the first electrode 31
  • a second protrusion 600 is provided in the middle of the recess 61, and a sub-recess 610 is formed between the side surface of the second protrusion 600 and the side surface of the recess 61.
  • the orthographic projection of the recess 61 on the first insulating layer 2 is at least partially located in the pixel defining groove 41. Further, a second protrusion 600 is provided in the middle of the recess 61 corresponding to the position of the first protrusion 42, and a sub-recess 610 is formed between the side surface of the second protrusion 600 and the side surface of the recess 61. The orthographic projection of the point of the sub-recess 610 closest to the substrate 1 on the first insulating layer 2 is located in the sub-groove 40.
  • the smooth portions 62 are distributed in an array and are arranged in a one-to-one correspondence with the middle portion 310 of each first electrode 31, that is, the orthographic projection of each smooth portion 62 on the first insulating layer 2 is located within each first electrode 31 in a one-to-one correspondence.
  • the gentle portion 62 is parallel or substantially parallel to the middle portion 310.
  • the recessed portion 61 corresponds to the area of the first insulating layer 2 that is not covered by the intermediate portion 310, and is used to separate the smooth portion 62, and the recessed portion 61 is recessed toward the side of the smooth portion 62 close to the substrate 1.
  • the recessed portion 61 has a ring structure, and the number is multiple, and each recessed portion 61 surrounds each smooth portion 62 in a one-to-one correspondence, that is, the recessed portion 61 is a transition area of two adjacent smooth portions 62.
  • the orthographic projection of the recess 61 on the substrate 1 is at least partially located outside the middle portion 310 of the first electrode 31, so as to be directly opposite to the area other than the first electrode 31 or the edge portion 311 with a smaller thickness, but not with the larger thickness.
  • the middle portion 310 is directly opposite, which can reduce the risk of tip discharge and short circuit between the recessed portion 61 and the first electrode 31, thereby improving the stability of the light-emitting device.
  • the orthographic projection of the lowest point of the recess 61 on the first insulating layer 2 is located outside the middle part 310, for example, the lowest point and the climbing part 3111 corresponds to one of the flat portions 3110 to avoid the occurrence of tip discharges with the middle portion 310.
  • the lowest point of the recess 61 on the cross section perpendicular to the substrate 1 is: on the cross section perpendicular to the substrate 1, the recess 61 is the point closest to the first electrode 31, that is, the point farthest from the gentle portion 62.
  • the number of recesses 61 in the section perpendicular to the substrate 1 may be multiple, and the lowest point on different sections may be different.
  • the lowest point may be the middle part from the first electrode 31 in the depth direction.
  • the nearest point 310 may also be another point in the depth direction, depending on the position of the cross section perpendicular to the substrate 1.
  • the recess 61 has two sides, including a first side 611, a second side 612, and a second protrusion 600, wherein the first side 611 and The second side surface 612 is oppositely disposed and connected to both sides of the second protrusion 600.
  • the first side surface 611 and the second side surface 612 may shrink in a direction close to the substrate 1.
  • the first side surface 611 and the second side surface 612 may be curved surfaces or flat surfaces, which are not specifically limited here.
  • the second protrusion 600 may be a curved surface that is convex in a direction away from the substrate 1.
  • the second protrusion 600 includes a first slope surface 6131, a second slope surface 6132, and a connecting surface 6133.
  • the first slope surface 6131 and the second slope surface 6132 can both be curved or flat
  • the connecting surface 6133 is located on the side of the first side surface 611 and the second side surface 612 facing away from the substrate 1
  • the connecting surface 6133 is connected to Between the first slope surface 6131 and the second slope surface 6132.
  • the first slope surface 6131 is connected to the bottom edge of the first side surface 611 to form a sub-recess 610
  • the second slope surface 6132 is connected to the bottom edge of the second side surface 612 to form another sub-recess 610.
  • the slope of the first slope surface 6131 relative to the middle portion 310 is not less than the slope of the first side surface 611 relative to the middle portion 310.
  • the slope of the second slope surface 6132 relative to the middle portion 310 is not less than the slope of the second side surface 612 relative to the middle portion 310.
  • the minimum thickness of the area of the second electrode 6 corresponding to the first side surface 611 and the second side surface 612 is larger than the area of the second electrode 6 corresponding to the first slope surface 6131 and the second slope surface 6132 The minimum thickness.
  • the depth of the recess 61 is less than twice the maximum thickness of the second electrode 6.
  • the maximum thickness of the second electrode 6 is 90 nm.
  • the depth of the recess 61 is less than 180 nm, such as 120 nm, 100 nm, 80 nm, 70 nm, 60 nm, 50 nm, 40 nm, etc.
  • the depth of the recessed portion 61 refers to the maximum depth of the recessed portion 61, that is, in the direction perpendicular to the substrate 1, the distance between the closest point of the recessed portion 61 to the substrate 1 and the surface of the smooth portion 62 away from the substrate 1.
  • the orthographic projection of each recess 61 on the first insulating layer 2 surrounds the middle part 310 of a first electrode 31, and the second part of the recess 61 is
  • the minimum value of the distance between the two protrusions 600 and the intermediate portion 310 of the adjacent first electrode 31 is not Less than 70% of the total thickness of the smooth portion 62 and the light-emitting functional layer 5, the total thickness of the smooth portion 62 and the light-emitting functional layer 5 is the sum of the thickness of the smooth portion 62 and the light-emitting functional layer 5, for example, the smooth portion 62 and the light-emitting functional layer
  • the total thickness of 5 is about 365 nm, and the minimum value of the distance between the middle portion of the recess 61 in the direction perpendicular to the substrate 1 and the middle portion
  • the maximum value of the distance between the middle part of the recess 61 and the middle part 310 of the adjacent first electrode 31 is not less than 400nm, and the maximum value is not greater than 450nm.
  • the pixel definition layer 4 may include a spacer 400 and an extension 410, wherein the spacer 400 is located in the first insulating layer 2 and is not covered by the first electrode 31 In the area outside the first electrode 31, the pixel defining groove 41 is provided in the spacer 400.
  • the extension portion 410 is connected to the spacer portion 400 and extends to the surface of the first electrode 31 facing away from the substrate 1 and does not completely cover the first electrode 31.
  • the extension portion 410 extends to the middle portion 31 along the circumferential direction of the first electrode 31
  • the circumferential direction of 310 is away from the surface of the substrate 1 and does not completely cover the middle portion 310.
  • the second electrode 6 corresponding to the area of the extension portion 410 also has a convex portion 63 that protrudes away from the substrate 1, and the smooth portion 62 passes through the convex portion 63.
  • the orthographic projection of the protrusion 63 on the substrate 1 and the orthographic projection of the extension 410 on the substrate 1 at least partially overlap.
  • the distance between the furthest point of one protrusion 63 from the substrate 1 and the substrate 1 is different from the distance between the furthest point of the other protrusion 63 from the substrate 1 and the substrate 1.
  • the display panel may further include a first encapsulation layer 13, a color film layer 14, a second encapsulation layer 15, and a transparent cover plate 16, wherein:
  • the first encapsulation layer 13 may cover the second electrode 6.
  • the first encapsulation layer 13 may include two inorganic layers and an organic layer between the two inorganic layers.
  • the first encapsulation layer 13 may be recessed to form a pit 1301 in the region corresponding to the recess 61.
  • the first encapsulation layer 13 is away from the substrate 1 The surface can also remain substantially flat.
  • the color filter layer 14 is disposed on the side of the first encapsulation layer 13 away from the second electrode 6, and the color filter layer 14 includes filter regions corresponding to each first electrode 31 one by one.
  • the color filter regions have multiple colors, such as Red, blue and green.
  • the second encapsulation layer 15 can cover the color filter layer 14, and its structure can be the same as that of the first encapsulation layer 13.
  • the transparent cover plate 16 can cover the second encapsulation layer 15, and its material can be glass or material.
  • the fourth type of display panel may further include a light extraction layer 17, which covers the surface of the second electrode 6 away from the substrate 1. And the area corresponding to the recess 61 is recessed, and the first encapsulation layer 13 is provided on the side of the light extraction layer 17 away from the substrate 1.
  • the refractive index of the light extraction layer 17 is greater than that of the second electrode 6, which can improve the light extraction efficiency, and the higher the refractive index, the higher the light extraction efficiency. 22.
  • the embodiments of the present disclosure also provide a method for manufacturing a display panel, which may be the first type of display panel described above. As shown in FIG. 14, the manufacturing method includes steps S110 to S160, wherein:
  • Step S110 forming a first insulating layer on one side of a substrate
  • Step S120 forming a plurality of separation grooves on the surface of the first insulating layer away from the substrate, so as to divide a plurality of pixel regions distributed in an array;
  • Step S130 forming a first electrode layer including a plurality of first electrodes on the surface of the first insulating layer away from the substrate; the orthographic projection of each of the first electrodes on the first insulating layer corresponds to one-to-one Located within each of the pixel regions; the first electrode includes a flat middle part and an edge part surrounding the middle part; the edge part includes a flat part surrounding the middle part and connected to the middle part and the For the climbing part between the flat parts, the thickness of the flat part is smaller than the middle part;
  • Step S140 forming a pixel definition layer on the surface of the first insulating layer away from the substrate, the pixel definition layer exposing at least a part of the middle portion.
  • Step S150 forming a light-emitting functional layer, the light-emitting functional layer covering the pixel defining layer and the intermediate portion exposed by the pixel defining layer and the first insulating layer.
  • Step S160 forming a second electrode covering the light-emitting function layer.
  • the embodiments of the present disclosure also provide a method for manufacturing a display panel.
  • the display panel may be the above-mentioned first display panel.
  • the manufacturing method includes step S210-step S250, wherein:
  • Step S210 forming a first insulating layer on one side of a substrate
  • Step S220 forming a first electrode layer including a plurality of first electrodes and a separation groove on the surface of the first insulating layer away from the substrate;
  • the edge part; the edge part includes a flat part surrounding the middle part and a climbing part connected between the middle part and the flat part, the thickness of the flat part is smaller than the middle part;
  • the partition The groove is divided into a plurality of pixel regions distributed in an array in the first insulating layer; the orthographic projection of each of the first electrodes on the first insulating layer is located within each of the pixel regions in a one-to-one correspondence;
  • Step S230 forming a pixel definition layer on the surface of the first insulating layer away from the substrate, the pixel definition layer exposing at least a part of the middle portion;
  • Step S240 forming a light-emitting functional layer, the light-emitting functional layer covering the pixel defining layer and the intermediate portion exposed by the pixel defining layer and the first insulating layer;
  • Step S250 forming a second electrode covering the light-emitting function layer.
  • a conductive layer may be formed on the surface of the first insulating layer away from the substrate, and the conductive layer may be patterned through a gray-scale mask process to obtain the first electrode layer.
  • the sub-gray-scale masking process can form the separation grooves together, which can simplify the manufacturing process of the display panel compared to the method of separately forming the first electrode layer and the separation grooves through two masking processes.
  • the embodiments of the present disclosure also provide a method for manufacturing a display panel, which may be the above-mentioned second display panel. As shown in FIG. 16, the manufacturing method includes steps S310-S340, wherein:
  • Step S310 forming a first insulating layer on one side of a substrate
  • Step S320 forming a first electrode layer including a plurality of first electrodes on the surface of the first insulating layer away from the substrate;
  • the first electrode includes a flat middle part and an edge part surrounding the middle part;
  • the edge part includes a flat part surrounding the middle part and a climbing part connected between the middle part and the flat part, and the thickness of the flat part is smaller than the middle part;
  • Step S330 forming a light-emitting function layer covering at least a part of the middle portion
  • Step S340 forming a second electrode covering the light-emitting function layer, the second electrode including a recessed portion and a plurality of smooth portions separated by the recessed portion, each of the smooth portions on the first insulating layer
  • the orthographic projection is located within each of the first electrodes in a one-to-one correspondence; the recessed portion is recessed toward the side of the smooth portion close to the substrate, and the orthographic projection of the recessed portion on the first insulating layer is at least Part is located outside the middle part.
  • Embodiments of the present disclosure also provide a method for manufacturing a display panel.
  • the display panel may be the above-mentioned third display panel.
  • a method for manufacturing a display panel includes steps S410-S450, in:
  • Step S410 forming a first insulating layer on one side of a substrate; the first insulating layer has a plurality of pixel regions distributed in an array and a partition region separating the pixel regions;
  • Step S420 forming a first electrode layer including a plurality of first electrodes on the surface of the first insulating layer away from the substrate; the orthographic projection of each of the first electrodes on the first insulating layer is located in each of the Within the pixel area;
  • Step S430 forming a pixel defining layer on the surface of the first insulating layer away from the substrate, and exposing each of the first electrodes;
  • the pixel defining layer is formed with a pixel defining groove in a region corresponding to the separation area
  • a middle portion of the pixel defining groove has a first protrusion protruding in a direction away from the substrate, and a sub-groove is formed between the side wall of the first protrusion and the side wall of the pixel defining groove;
  • Step S440 forming a light-emitting functional layer, the light-emitting functional layer covering the pixel defining layer and the first electrode exposed by the pixel defining layer;
  • Step S450 forming a second electrode covering the light-emitting function layer.
  • Embodiments of the present disclosure also provide a method for manufacturing a display panel, which can be the fourth type of display panel described above. As shown in FIG. 18, a method for manufacturing a display panel includes steps S510 to S550, in:
  • Step S510 forming a first insulating layer on one side of a substrate
  • Step S520 forming a first electrode layer on the surface of the first insulating layer away from the substrate, the first electrode layer including a plurality of first electrodes;
  • Step S530 forming a pixel definition layer on the surface of the first insulating layer away from the substrate, and the pixel definition exposes each of the first electrodes;
  • Step S540 forming a light-emitting functional layer, the light-emitting functional layer covering the pixel defining layer and the first electrode exposed by the pixel defining layer;
  • Step S550 forming a second electrode covering the light-emitting function layer.
  • the second electrode includes a recessed portion and a plurality of smooth portions separated by the recessed portion, each of the smooth portions being located on the first insulating layer.
  • the orthographic projection is located within each of the first electrodes; at least a part of the recessed portion is recessed toward the side of the smooth portion close to the substrate, and the orthographic projection of the recessed portion on the first insulating layer is at least Partly located outside the first electrode, a second protrusion is provided in the middle of the recessed portion, and a sub-recess is formed between the side surface of the second protrusion and the side surface of the recessed portion.
  • the embodiments of the present disclosure also provide a display device, which may include any one of the above-mentioned first type display panel, second type display panel, third type display panel, and fourth type display panel.
  • a display device which may include any one of the above-mentioned first type display panel, second type display panel, third type display panel, and fourth type display panel.
  • the display device of the present disclosure can be used in electronic devices such as mobile phones, tablet computers, televisions, etc., and will not be listed here.

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Abstract

一种显示装置、显示面板及其制造方法，显示面板包括衬底(1)、第一绝缘层(2)、第一电极层(3)、像素定义层(4)、发光功能层(5)和第二电极(6)；第一绝缘层(2)设于衬底(1)一侧，第一绝缘层(2)具有阵列分布的多个像素区(202)以及分隔像素区202的分隔区(201)；第一电极层(3)设于第一绝缘层(2)背离衬底(1)的表面，且包括多个第一电极(31)；各第一电极(31)在第一绝缘层(2)的正投影位于各像素区(202)以内；像素定义层(4)设于第一绝缘层(2)背离衬底(1)的表面，且露出各第一电极(31)；像素定义层(4)在对应于分隔区(201)的区域形成有像素定义槽(41)，像素定义槽(41)的中部具有向背离衬底(1)的方向凸起的第一凸起(42)，第一凸起(42)的侧壁与像素定义槽(41)的侧壁之间形成子槽(40)；发光功能层(5)覆盖像素定义层(4)以及被像素定义层(4)露出的第一电极(31)和第一绝缘层(2)；第二电极(6)覆盖发光功能层(5)，从而能够降低尖端放电的风险，减少对相邻子像素的干扰。

Description

显示装置、显示面板及其制造方法
交叉引用
本公开要求于2020年4月21日提交的申请号为PCT/CN2020/085955名称为“显示装置、显示面板及其制造方法”的PCT申请的优先权，该PCT申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示装置、显示面板及显示面板的制造方法。
背景技术
目前，OLED(Organic Light-Emitting Diode，有机发光二极管)显示面板的应用越来越广泛。在OLED显示面板中，发光器件通常包括阵列分布的多个OLED发光器件，每个发光器件可独立发光，以便显示图像。但是，由于制造工艺的原因，OLED发光器件发光的稳定性仍有待提高。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于克服上述现有技术的不足，提供一种显示装置、显示面板及显示面板的制造方法。
根据本公开的一个方面，提供一种显示面板，包括：
衬底；
第一绝缘层，设于所述衬底一侧，所述第一绝缘层具有阵列分布的多个像素区以及分隔所述像素区的分隔区；
第一电极层，设于所述第一绝缘层背离所述衬底的表面，且包括多个第一电极；各所述第一电极在所述第一绝缘层的正投影位于各所述像素区以内；
像素定义层，设于所述第一绝缘层背离所述衬底的表面，且露出各所述第一电极；所述像素定义层在对应于所述分隔区的区域形成有像素定义槽，所述像素定义槽的中部具有向背离所述衬底的方向凸起的第一凸起，所述第一凸起的侧壁与所述像素定义槽的侧壁之间形成子槽；
发光功能层，覆盖所述像素定义层以及被所述像素定义层露出的所述第一电极；
第二电极，覆盖所述发光功能层。
在本公开的一种示例性实施例中，所述第一凸起的两侧壁为向所述衬底扩张的斜面，所述像素定义槽的两侧壁为向所述衬底收缩的斜面。
在本公开的一种示例性实施例中，所述第一凸起的侧壁的坡度与所述像素定义槽的侧壁的坡度不同。
在本公开的一种示例性实施例中，所述第一凸起的厚度小于所述像素定义槽的深度。
在本公开的一种示例性实施例中，所述像素定义槽的中部在所述第一绝缘层上的正投影位于所述分隔区内。
在本公开的一种示例性实施例中，所述像素定义层包括间隔部和延伸部，所述间隔部位于所述第一电极以外的区域，所述像素定义槽至少部分设于所述间隔部；所述延伸部连接于所述间隔部，并延伸至所述第一电极背离所述衬底的表面，且不完全覆盖所述第一电极。
在本公开的一种示例性实施例中，覆盖任一所述第一电极的延伸部的宽度小于相邻两所述第一电极之间的间隔部的宽度。
在本公开的一种示例性实施例中，至少两个所述第一电极的厚度不同。
在本公开的一种示例性实施例中，所述像素定义槽的最大深度不大于所述发光功能层和所述第一电极的厚度和的60％。
根据本公开的一个方面，提供一种显示面板，包括：
衬底；
第一绝缘层，设于所述衬底一侧；
第一电极层，设于所述第一绝缘层背离所述衬底的表面，且包括多个第一电极；
像素定义层，设于所述第一绝缘层背离所述衬底的表面，且露出各所述第一电极；
发光功能层，覆盖所述像素定义层以及被所述像素定义层露出的所述第一电极；
第二电极，覆盖所述发光功能层，且包括凹陷部和被所述凹陷部分隔的多个平缓部，各所述平缓部在所述第一绝缘层上的正投影位于各所述第一电极以内；所述凹陷部的至少部分区域向所述平缓部靠近所述衬底的一侧凹陷，所述凹陷部在所述第一绝缘层上的正投影至少部分位于所述第一电极以外，所述凹陷部的中部具有第二凸起，所述第二凸起的侧面与所述凹陷部的侧面之间形成子凹陷。
在本公开的一种示例性实施例中，所述第一绝缘层具有阵列分布的多个像素区以及分隔所述像素区的分隔区，各所述第一电极在所述第一绝缘层的正投影位于各所述第一电极以内；
所述像素定义层露出各所述第一电极，且在对应于所述分隔区的区域形成有像素定义槽，所述像素定义槽的中部具有向背离所述衬底的方向凸起的第一凸起，所述第一凸起的侧壁与所述像素定义槽的侧壁之间形成子槽；
所述凹陷部在所述第一绝缘层上的正投影至少部分位于所述像素定义槽内。
在本公开的一种示例性实施例中，所述子凹陷距离所述衬底最近的点在所述第一绝 缘层上的正投影位于所述子槽内。
在本公开的一种示例性实施例中，所述凹陷部包括第一侧面和第二侧面，所述第一侧面和所述第二侧面相对连接于所述第二凸起的两侧，且所述第一侧面和所述第二侧面向所述衬底收缩。
在本公开的一种示例性实施例中，所述第二凸起包括第一坡面、第二坡面以及连接于所述第一坡面和所述第二坡面之间的连接面，所述连接面位于所述第一侧面和所述第二侧面的底边背离所述衬底的一侧，所述第一坡面与所述第一侧面的底边连接，所述第二坡面与所述第二侧面的底边连接。
在本公开的一种示例性实施例中，所述第二电极对应于所述第一侧面和所述第二侧面的区域的最小厚度，大于对应于所述第一坡面和所述第二坡面的区域的最小厚度。
在本公开的一种示例性实施例中，所述像素定义层包括间隔部和延伸部，所述间隔部位于所述第一电极以外的区域，所述像素定义槽设于所述间隔部；所述延伸部连接于所述间隔部，并延伸至所述第一电极背离所述衬底的表面，且不完全覆盖所述第一电极；
所述第二电极还具有向背离所述衬底的方向凸起的凸起部，所述平缓部通过所述凸起部与所述凹陷部连接；所述凸起部在所述衬底上的正投影与所述延伸部在所述衬底上的正投影至少部分重合。
在本公开的一种示例性实施例中，在连接于一所述凹陷部两侧的两所述凸起部中，一所述凸起部距离所述衬底最远点与所述衬底的距离，不同于另一所述凸起部距离所述衬底最远点与所述衬底的距离。
在本公开的一种示例性实施例中，所述显示面板还包括：
第一封装层，覆盖所述第二电极，且在对应于所述凹陷部的区域形成凹坑。
在本公开的一种示例性实施例中，所述凹坑的两个侧壁向靠近所述衬底的方向收窄且连接。
根据本公开的一个方面，提供一种显示面板的制造方法，包括：
在一衬底一侧形成第一绝缘层；所述第一绝缘层具有阵列分布的多个像素区以及分隔所述像素区的分隔区；
在所述第一绝缘层背离所述衬底的表面形成包括多个第一电极的第一电极层；各所述第一电极在所述第一绝缘层的正投影位于各所述像素区以内；
在所述第一绝缘层背离所述衬底的表面形成像素定义层，且露出各所述第一电极；所述像素定义层在对应于所述分隔区的区域形成有像素定义槽，所述像素定义槽的中部具有向背离所述衬底的方向凸起的第一凸起，所述第一凸起的侧壁与所述像素定义槽的侧壁之间形成子槽；
形成发光功能层，所述发光功能层覆盖所述像素定义层以及被所述像素定义层露出的所述第一电极；
形成覆盖所述发光功能层的第二电极。
根据本公开的一个方面，提供一种显示面板的制造方法，包括：
在一衬底一侧形成第一绝缘层；
在所述第一绝缘层背离所述衬底的表面形成第一电极层，所述第一电极层包括多个第一电极；
在所述第一绝缘层背离所述衬底的表面形成像素定义层，所述像素定义露出各所述第一电极；
形成发光功能层，所述发光功能层覆盖所述像素定义层以及被所述像素定义层露出的所述第一电极；
形成覆盖所述发光功能层的第二电极，所述第二电极包括凹陷部和被所述凹陷部分隔的多个平缓部，各所述平缓部在所述第一绝缘层上的正投影位于各所述第一电极以内；所述凹陷部的至少部分区域向所述平缓部靠近所述衬底的一侧凹陷，所述凹陷部在所述第一绝缘层上的正投影至少部分位于所述第一电极以外，所述凹陷部的中部具有第二凸起，所述第二凸起的侧面与所述凹陷部的侧面之间形成子凹陷。
根据本公开的一个方面，提供一种显示装置，包括上述任意一项所述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开的第一种显示面板一实施方式的示意图。
图2为本公开的第一种显示面板一实施方式的局部电镜图。
图3为本公开的第一种显示面板另一实施方式的示意图。
图4为本公开的第一种显示面板再一实施方式的示意图。
图5为本公开的第一种显示面板一实施方式中像素定义层的俯视图。
图6为本公开的第一种显示面板一实施方式中像素定义层和第一电极的俯视图。
图7为本公开的第二种显示面板一实施方式的示意图。
图8为图7中A部的放大图。
图9为本公开的第二种显示面板一实施方式的局部电镜图。
图10为本公开的第三种显示面板一实施方式的示意图。
图11为本公开的第三种显示面板另一实施方式的示意图。
图12为本公开的第四种显示面板另一实施方式的示意图。
图13为图12中B部的放大图。
图14为本公开的第一种显示面板的制造方法一实施方式的示意图。
图15为本公开的第一种显示面板的制造方法另一实施方式的示意图。
图16为本公开的第二种显示面板的制造方法一实施方式的示意图。
图17为本公开的第三种显示面板的制造方法一实施方式的示意图。
图18为本公开的第四种显示面板的制造方法一实施方式的示意图。
附图标记说明：
1、衬底；101、有源区；1011、源极；1012、漏极；2、平坦层；201、分隔槽；2011、侧壁；2012、底壁；202、像素区；3、第一电极层；31、第一电极；310、中间部；311、边缘部；3110、平坦部；3111、爬坡部3111；320、第一导电层；321、第二导电层；322、第三导电层；4、像素定义层；401、开口；41、像素定义槽；42、第一凸起；40、子槽；400、间隔部；410、延伸部；5、发光功能层；501、发光单元层；502、电荷产生层；6、第二电极；61、凹陷部；611、第一侧面；612、第二侧面；613、底面；6131、第一坡面；6132、第二坡面；6133、连接面；600、第二凸起；62、平缓部；63、凸出部；7、栅绝缘层；8、栅极；9、第二绝缘层；10、第一走线层；11、第三绝缘层；12、第二走线层；13、第一封装层；1301、凹坑；14、彩膜层；15、第二封装层；16、透明盖板；17、光提取层。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
相关技术中，OLED显示面板包括驱动背板、多个第一电极、像素定义层、发光功能层、第二电极和彩膜层，其中，第一电极阵列分布于驱动背板上；像素定义层设于驱动背板设有第一电极的表面，且露出各个第一电极；发光功能层覆盖像素定义层和第一电极背离驱动背板的表面，第二电极覆盖于发光功能层背离驱动背板的表面，从而可通过像素定义层限定出多个发光器件。在驱动信号的驱动下，第一电极注入的空穴和第二电极注入的电子进入到发光功能层，并形成激子，激子辐射跃迁发射光子从而形成电致发光。彩膜层设于第二电极背离驱动背板的一侧，且具有一一对应于各个发光器件的多 个滤光区，每个滤光区及其对应的发光器件可作为一子像素。
由于像素定义层的厚度大于第一电极，在通过蒸镀工艺形成发光功能层时，在第一电极与像素定义层交界处，即在发光器件的边缘位置，发光功能层会出现凹陷，从而使第二电极相应的形成凹陷区，第二电极的凹陷区与第一电极的距离较近，容易出现尖端放电，甚至短路，影响发光器件的稳定性，从而使显示面板难以稳定发光。同时，第二电极的凹陷区与第一电极对应，因而也会发射光线，但由于凹陷区的形貌为向驱动背板凹陷的结构，而非平面结构，使得该凹陷区的范围内发射的光线为散射状态，且至少部分光线向相邻的子像素偏斜，使得相邻的子像素的发光互相干扰，影响显示效果。
发光功能层在第二电极在第一电极与像素定义层的交界处凹陷，使第二电极在对应该凹陷的区域形成凹陷区，该凹陷区与第一电极正对，即凹陷区在驱动背板的正投影位于第一电极内，使得二者之间可能会出现尖端放电，甚至短路。同时，凹陷区会发光，且由于凹陷区的形貌为弯曲状，使得其发出的光线呈散射状态，从而对相邻的子像素的发光产生干扰。
此外，由于发光功能层为整层连续的膜层，使得子像素之间相互连接，发光功能层中的至少一部分膜层(包括但不限于空穴注入层)会使相邻的子像素之间产生串扰。特别地，对于串联式OLED显示面板，发光功能层包括多个发光单元层，相邻的两层发光单元层通过电荷产生层串联。但是，电荷产生层具有良好电荷传导特性，会使相邻的子像素之间产生串扰，影响发光效果。
为了解决上述相关技术中的至少一个技术问题，本公开的实施方式提供了多种显示面板。
第一种显示面板
如图1和图2所示，显示面板可包括衬底1、第一绝缘层2、第一电极层3、像素定义层4、发光功能层5和第二电极6，其中：
第一绝缘层2设于衬底1一侧，且第一绝缘层2背离衬底1的表面设有多个分隔槽201，以在第一绝缘层2上分割出多个像素区202，且各像素区202阵列分布。
第一电极层3设于第一绝缘层2背离衬底1的表面，且包括阵列分布的多个第一电极31，各第一电极31在第一绝缘层2的正投影一一对应的位于各像素区202以内。第一电极31包括平坦的中间部310和围绕中间部310的边缘部311；边缘部311包括围绕中间部310的平坦部3110以及连接于中间部310和平坦部3110之间的爬坡部3111，平坦部3110的厚度小于中间部310。
像素定义层4设于第一绝缘层2背离衬底1的表面，且露出中间部310的至少部分区域。
发光功能层5覆盖像素定义层4以及被像素定义层4露出的中间部310和第一绝缘层2。
第二电极6覆盖发光功能层5。
本公开实施方式的显示面板，每个第一电极31的中间部310被像素定义层4露出的区域及其对应的发光功能层5和第二电极6可构成一发光器件，以便发光。
由于第一电极31在第一绝缘层2的正投影一一对应的位于各像素区202以内，使得分隔槽201位于第一电极31以外，在形成发光功能层5时，发光功能层5可在分隔槽201的位置向衬底1凹陷，进而使第二电极6在该凹陷处形成的凹陷部61，且凹陷部61在第一绝缘层2的正投影至少部分位于第一电极31的中间部310以外，也即位于发光器件以外，由此，可通过分隔槽201对第二电极6的凹陷部61的位置进行限制，防止凹陷部61与中间部310之间发生尖端放电，甚至短路，有利于保证发光器件稳定发光。同时，可减少、甚至避免凹陷部61的范围内发光，从而降低相邻发光器件发光的互相干扰。
如图2所示，图2为本公开第一种显示面板一实施方式的局部电镜图，可以看出，凹陷部61在第一绝缘层2的正投影至少部分位于第一电极31的范围外，可降低与第一电极31之间出现尖端放电的风险。同时，可减少甚至避免凹陷部61发光，防止对相邻的子像素产生干扰。
下面对本公开实施方式第一种显示面板的各部分进行详细说明：
如图1所示，衬底1的材料可为单晶硅或多晶硅等半导体材料，也可以是玻璃等其它硬质或软质材料。
在本公开的一些实施方式中，衬底1上可设有多个驱动晶体管，用于驱动各个发光器件发光，以显示图像。以一个顶栅结构的驱动晶体管为例，显示面板还包括栅绝缘层7、栅极8、第二绝缘层9和第一走线层10，其中：衬底1的材料可为单晶硅或多晶硅等半导体材料，且衬底1包括有源区101和位于有源区101两端的源极1011和漏极1012。栅绝缘层7覆盖有源区101；栅极8设于栅绝缘层7背离衬底1的表面，栅极8的材料可包括多晶硅材料。第二绝缘层9覆盖栅极8和衬底1，其材料可包括氧化硅和氮化硅中至少一个。第一走线层10设于第二绝缘层9背离衬底1的表面，且栅极8、源极1011和漏极1012均通过钨或其它金属填充的过孔与第一走线层10连接。
此外，显示面板还可包括第三绝缘层11和第二走线层12，第三绝缘层11覆盖第一走线层10和第二绝缘层9，第二走线层12设于第三绝缘层11背离衬底1的表面，第二走线层12的具体图案在此不做特殊限定，其可通过钨或其它金属填充的过孔与第一走线层10连接。
如图1所示，第一绝缘层2设于衬底1的一侧，在本公开的一些实施方式中，第一绝缘层2可覆盖第二走线层12，第一电极31可通过钨或其它金属填充的过孔与第二走线层12连接。第一绝缘层2的材料可包括氮化硅和氧化硅中至少一种，当然，还可以包括其它绝缘材料。举例而言，第一绝缘层2可通过抛光工艺实现平坦化。
第一绝缘层2背离衬底1的表面可开设多个分隔槽201，分隔槽201的深度小于第一绝缘层2的厚度，即分隔槽201在深度方向上不会贯穿第一绝缘层2。通过分隔槽201可在第一绝缘层2上分割出多个像素区202，且各像素区202阵列分布。
像素区202在衬底1的正投影的形状可以是矩形、五边形、六边形或其它多边形，当然，也可以是圆形或其它形状，在此不作特殊限定。同时，不同像素区202的形状和尺寸可以不同。
在本公开的一些实施方式中，例如，分隔槽201可包括第一分隔槽和第二分隔槽，其中，第一分隔槽的数量为多个，且各第一分隔槽沿第一方向直线延伸，并沿第二方向间隔分布；第二分隔槽的数量为多个，且各第二分隔槽沿第二方向直线延伸，并沿第一方向间隔分布；第一方向和第二方向为相互交叉的方向，例如，第一方向和第二方向为相互垂直的方向。由此，可通过交错的第一分隔槽和第二分隔槽在第一绝缘层2上分割出阵列分布的多个像素区202。
在本公开的其它实施方式中，第一分隔槽和第二分隔槽也可沿曲线或折线轨迹延伸，从而分割出其他形状的像素区202。
每个分隔槽201可包括两个相对的侧壁2011以及连接于两个侧壁2011之间的底壁2012。其中，两个侧壁2011可平行设置，即在垂直于衬底1的方向上，两个侧壁2011及其延伸面不相交。或者，两个侧壁2011也可呈一定夹角设置。
如图3所示，底壁2012可与第一绝缘层2背离衬底1的表面大致平行，或者，如图1所示，底壁2012也可是沿背离衬底1的方向凸起的曲面，该曲面的曲率和形状在此不做特殊限定，且在垂直于衬底1的截面中，底壁2012的轮廓可以大致呈圆弧状、抛物线状或波浪线状，当然，也可以是其它规则或不规则的形状，只要向背离衬底1的方向凸起即可。
在本公开的一些实施方式中，两个侧壁2011向靠近底壁2012的方向收缩，即两个侧壁2011的间距向靠近底壁2012的方向逐渐减小，使得侧壁2011具有相对于第一绝缘层2背离衬底1的表面的坡度，该坡度为侧壁2011与第一绝缘层2背离衬底1的表面的夹角。进一步的，该坡度不小于70°，且不大于90°，例如，该坡度可以是70°、80°和90°等。
在本公开的一些实施方式中，分隔槽201的两个侧壁2011的最大间距S可为0.2μm-0.7μm，例如0.2μm 0.3μm、0.5μm或0.7μm等。
如图1所示，第一电极层3设于第一绝缘层2背离衬底1的表面，且包括阵列分布的多个第一电极31，各第一电极31在第一绝缘层2的正投影一一对应的位于各像素区202以内，即各第一电极31在衬底1的正投影的边界一一对应的位于各像素区202在衬底1的正投影的边界以内。每个像素区202上只设置一个第一电极31。由于像素区202是分隔槽201分隔而成，而第一电极31位于像素区202上，因此，分隔槽201位于第一电极31以外。每个第一电极31在第一绝缘层2的正投影的形状可与其所处的像素区202的形状相同，第一电极31的边界位于其所处的像素区202以内。
在平行于衬底1的方向上，至少一个第一电极31可包括中间部310和围绕中间部310边缘部311，其中，中间部310为平坦结构，即中间部310与第一绝缘层2背离衬底 1的表面大致平行。
在本公开的一些实施方式中，每个第一电极31的中间部310在衬底1的正投影的边界可位于其所处的像素区202在衬底1的正投影的边界以内，即中间部310在衬底1的正投影的边界与其所处的像素区202在衬底1的正投影的边界具有不为0的间距L。进一步的，该间距L不小于0.15μm，例如，该间距可以是0.15μm、0.2μm、0.25μm等。
边缘部311可包括平坦部3110以及爬坡部3111，其中，平坦部3110位于第一绝缘层2背离衬底1的表面，并围绕中间部310设置，且平坦部3110与第一绝缘层2背离衬底1的表面大致平行。同时，平坦部3110的厚度小于中间部310的厚度。在本公开的一些实施方式中，平坦部3110在衬底1的正投影的边界与其所处的像素区202在衬底1的正投影的边界之间具有不为0的间距。当然，平坦部3110在衬底1的正投影的边界与其所处的像素区202在衬底1的正投影的边界重叠。
爬坡部3111连接于中间部310和平坦部3110之间，即爬坡部3111围绕中间部310，平坦部3110围绕爬坡部3111设置。在本公开的一些实施方式中，爬坡部3111相对于第一绝缘层2背离衬底1的表面的坡度不小于30°，该坡度为爬坡部3111的表面与第一绝缘层2背离衬底1的表面的夹角。
第一电极31包括第一导电层320、第二导电层321和第三导电层322，第一导电层320设于第一绝缘层2背离衬底1的表面，第二导电层321设于第一导电层320背离衬底1的表面，第三导电层322设于第二导电层321背离衬底1的表面，并以一定的坡度延伸至第一绝缘层2，从而包覆第一导电层320和第二导电层321，对第一导电层320和第二导电层321进行保护。
第一电极31的中间部310包括第三导电层322位于第二导电层321背离衬底1的表面的区域以及第一导电层320和第二导电层321，边缘部311包括第三导电层322包覆第一导电层320和第二导电层321边缘的区域，即向第一绝缘层2延伸的区域。示例性的，第一导电层320的材料可包括钛(Ti)、第二导电层321的材料包括银(Ag)、第三导电层322的材料包括氧化铟锡(ITO)，当然，也可以采用其他材料。
如图1所示，像素定义层4为绝缘材质，且与第一电极层3均设于第一绝缘层2背离衬底1的表面。同时，像素定义层4露出第一电极31的中间部310的至少部分区域，被像素定义层4露出的中间部310可与对应的发光功能层5和第二电极6构成发光器件。
在本公开的一些实施方式中，每个第一电极31不完全覆盖其所在的像素区202，且第一电极31的平坦部3110在衬底1的正投影的边界与其所处的像素区202在衬底1的正投影的边界具有一定的间距。像素定义层4延伸至分隔槽201的侧壁2011和底壁2012，即像素定义层4与未被第一电极31覆盖的像素区202随形贴合，使得像素定义层4在对应分隔槽201的区域凹陷。像素定义层4设有一一对应露出各中间部310的至少部分区域的多个开口401，从而可通过像素定义层4对发光器件的发光范围进行限定。
如图5和图6所示，在本公开的一些实施方式中，像素定义层4的开口401可为六边形或其它多边形结构，第一电极31也可为多边形结构，且与开口401的形状相同，当然，第一电极31也可以是其它形状。
如图1所示，发光功能层5可为连续的膜层，且至少部分覆盖各第一电极31的中间部310，即覆盖被开口401露出的区域，同时，发光功能层5还覆盖像素定义层4以及第一绝缘层2未被像素定义层4和第一电极31覆盖的区域，在通过蒸镀或其它工艺形成发光功能层5时，发光功能层5在对应分隔槽201的区域向靠近衬底1的方向凹陷。
在本公开的一实施方式中，如图4所示，发光功能层5包括多层发光单元层501，每层发光单元层501的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层的分布方式相同。同时，相邻两发光单元层501之间设有电荷产生层502，从而通过电荷产生层502将各发光单元层501串联，以便形成串联式的OLED发光器件。
在本公开的另一些实施方式中，发光功能层5包括一层发光单元层，发光单元层包括由第一电极31向背离衬底1的方向依次层叠的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层。
电荷产生层502无法覆盖分隔槽201的侧壁2011，从而可通过分隔槽201将发光器件的电荷产生层502截断，避免相邻两个发光器件之间出现串扰。当然，分隔槽201还可将空穴注入层或其它膜层截断，同样可防止串扰。
如图1所示，第二电极6覆盖发光功能层5，可向第一电极31和第二电极6施加驱动信号，使发光功能层5位于第一电极31和第二电极6之间的部分发光。
第二电极6的形貌与发光功能层5相匹配，其在发光功能层5的凹陷处凹陷，形成凹陷部61，并在对应于第一电极31的中间部310的区域形成平缓部62，使凹陷部61在第一绝缘层2上的正投影至少部分位于第一电极31的中间部310以外，减少或避免第一电极31与第二电极6的凹陷部61发生尖端放电。第二电极6的材料可以是合金材料，例如第二电极6的材料可包括Mg和Ag；或者，第二电极6还可采用Al和Li合金。当然，第二电极6还可以采用其他合金或单质金属，在此不再一一列举。
需要说明的是，若像素定义层4覆盖中间部310的边缘，则平缓部62在对应于像素定义层4覆盖中间部310的区域可向背离衬底1的方向凸起，但凸起的高度小于第一中间部310的厚度，以使平缓部62大致保持平缓。
进一步的，如图1和图2所示，在本公开的一些实施方式中，第二电极6的凹陷部61在垂直于衬底1的截面上的最低点在第一绝缘层2的正投影完全位于分隔槽201以内，即完全位于中间部310以外。
为了保证分隔槽201能将空穴注入层、电荷产生层502或其它膜层截断，应使分隔槽201具有一定的深度，但还应防止分隔槽201过深导致穿透第一绝缘层2，而影响驱动器件。因此，在本公开的一些实施方式中，在垂直于衬底1的方向上，分隔槽201的最大深度H不小于发光功能层5和第一电极31的厚度和的30％；同时，分隔槽201的 最大深度H不大于发光功能层5和第一电极31的厚度之和的60％。其中，分隔槽201的最大深度为：在垂直于衬底1的方向上分隔槽201的底壁2012上与第一绝缘层2背离衬底1的表面的距离最大的一点与第一绝缘层2背离衬底1的表面的距离。举例而言，在本公开的一些实施方式中，分隔槽201的最大深度H为
Figure PCTCN2021088701-appb-000001
此外，在本公开的一些实施方式中，如图1所示，第一种显示面板还可包括第一封装层13、彩膜层14、第二封装层15和透明盖板16，其中：
第一封装层13可覆盖第二电极6，举例而言，第一封装层13可包括两层无机层和两层无机层之间的有机层。
在本公开的一些实施方式中，第一封装层13在对应凹陷部61的区域可凹陷形成凹坑1301，当然，若第一封装层13厚度较大，第一封装层13背离衬底1的表面也可大致保持平坦
彩膜层14设于第一封装层13背离第二电极6的一侧，且彩膜层14包括一一对应于各第一电极31的滤光区，滤光区的颜色有多种，例如红色、蓝色和绿色。
第二封装层15可覆盖彩膜层14，其结构可与第一封装层13相同。
透明盖板16可覆盖第二封装层15，其材质可以是玻璃或材料。
此外，在本公开的一些实施方式中，如图1所示，第一种显示面板还可包括光提取层17，光提取层17覆盖于第二电极6背离衬底1的表面，且在对应与凹陷部61的区域凹陷，第一封装层13设于光提取层17背离衬底1的一侧。光提取层17的折射率大于第二电极6，可提高出光效率，且折射率越高，出光效率越高。
第二种显示面板
如图7-图9所示，本公开的第二种显示面板可包括衬底1、第一绝缘层2、第一电极层3、发光功能层5和第二电极6，其中：
第一绝缘层2设于衬底1一侧；
第一电极层3设于第一绝缘层2背离衬底1的表面，且包括多个第一电极31；第一电极31包括平坦的中间部310和围绕中间部310的边缘部311；边缘部311包括围绕中间部310的平坦部3110以及连接于中间部310和平坦部3110之间的爬坡部3111，平坦部3110的厚度小于中间部310。
发光功能层5覆盖中间部310的至少部分区域。
第二电极6覆盖发光功能层5，且包括凹陷部61和被凹陷部61分隔的多个平缓部62，各平缓部62在第一绝缘层2上的正投影一一对应的位于各第一电极31以内；凹陷部61向平缓部62靠近衬底1的一侧凹陷，凹陷部61在第一绝缘层2上的正投影至少部分位于中间部310以外。
本公开实施方式的显示面板，每个第一电极31及其对应的发光功能层5和第二电极6可构成一发光器件，可进行发光。通过使第二电极6的凹陷部61在第一绝缘层2上的 正投影至少部分位于厚度较大的中间部310以外，而不与中间部310正对，可降低凹陷部61与第一电极31之间发生尖端放电的风险，有利于保证发光器件稳定发光。同时，可减少凹陷部61的范围内发光，从而降低相邻发光器件发光的互相干扰。
下面对本公开第二种显示面板的各部分进行详细说明：
在本公开的一些实施方式中，如图7所示，衬底1上可设有多个驱动晶体管，用于驱动各个发光器件发光，以显示图像。以一个顶栅结构的驱动晶体管为例，显示面板还包括栅绝缘层7、栅极8、第二绝缘层9和第一走线层10，其中：衬底1的材料可为单晶硅或多晶硅等半导体材料，且衬底1可包括有源区101和位于有源区101两端的源极1011和漏极1012。栅绝缘层7覆盖有源区101；栅极8设于栅绝缘层7背离衬底1的表面。第二绝缘层9覆盖栅极8和衬底1，其材料可包括氧化硅和氮化硅中至少一个。第一走线层10设于第二绝缘层9背离衬底1的表面，且栅极8、源极1011和漏极1012均通过钨或其它金属填充的过孔与第一走线层10连接。
此外，显示面板还可包括第三绝缘层11和第二走线层12，第三绝缘层11覆盖第一走线层10和第二绝缘层9，第二走线层12设于第三绝缘层11背离衬底1的表面，第二走线层12的具体图案在此不做特殊限定，其可通过钨或其它金属填充的过孔与第一走线层10连接。
如图7所示，第一绝缘层2设于衬底1的一侧，在本公开的一些实施方式中，第一绝缘层2可覆盖第二走线层12，第一电极31可通过钨或其它金属填充的过孔与第二走线层12连接。第一绝缘层2的材料可包括氮化硅和氧化硅中至少一种，当然，还可以包括其它绝缘材料。
如图7所示，第一电极层3设于第一绝缘层2背离衬底1的一面，且包括多个第一电极31，第一电极31阵列分布，相邻的第一电极31间隔设置。
在平行于衬底1的方向上，每个第一电极31可包括中间部310和围绕中间部310边缘部311，其中，中间部310为平坦结构，即中间部310与第一绝缘层2背离衬底1的表面大致平行。
边缘部311可包括平坦部3110以及爬坡部3111，其中，平坦部3110位于第一绝缘层2背离衬底1的表面，并围绕中间部310设置，且平坦部3110与第一绝缘层2背离衬底1的表面大致平行。同时，平坦部3110的厚度小于中间部310的厚度。在本公开的一些实施方式中，平坦部3110与其所处的像素区202的边界之间具有不为0的间距。当然，平坦部3110的边界也可与像素区202的边界重叠。
爬坡部3111连接于中间部310和平坦部3110之间，即爬坡部3111围绕中间部310，平坦部3110围绕爬坡部3111设置。在本公开的一些实施方式中，爬坡部3111相对于第一绝缘层2背离衬底1的表面的坡度不小于30°，该坡度为爬坡部3111的表面与第一绝缘层2背离衬底1的表面的夹角。
第一电极31包括第一导电层320、第二导电层321和第三导电层322，第一导电层 320设于第一绝缘层2背离衬底1的表面，第二导电层321设于第一导电层320背离衬底1的表面，第三导电层322设于第二导电层321背离衬底1的表面，并以一定的坡度延伸至其所处的像素区202背离衬底1的表面，从而包覆第一导电层320和第二导电层321，对第一导电层320和第二导电层321进行保护。
第一电极31的中间部310包括第三导电层322位于第二导电层321背离衬底1的表面的区域以及第一导电层320和第二导电层321，边缘部311包括第三导电层322包覆第一导电层320和第二导电层321边缘的区域，即向第一绝缘层2延伸的区域。示例性的，第一导电层320的材料可包括钛(Ti)、第二导电层321的材料包括银(Ag)、第三导电层322的材料包括氧化铟锡(ITO)，当然，也可以采用其他材料。
如图7所示，发光功能层5可为连续的膜层，且同时覆盖各第一电极31的至少部分区域。在本公开的一些实施方式中，发光功能层5包括一层发光单元层，发光单元层包括由第一电极31向背离衬底1的方向依次层叠的空穴注入、空穴传输层、发光层、电子传输层和电子注入层。
在本公开的另一实施方式中，发光功能层5包括多层发光单元层，每层发光单元层的空穴注入、空穴传输层、发光层、电子传输层和电子注入层的分布方式相同。同时，相邻两发光单元层之间设有电荷产生层，从而通过电荷产生层将各发光单元层串联，以便形成串联式的OLED发光器件。
如图7所示，第二电极6覆盖发光功能层5，可向第一电极31和第二电极6施加驱动信号，使发光功能层5位于第一电极31和第二电极6之间的部分发光。第二电极6包括多个凹陷部61和多个平缓部62，其中：
各平缓部62阵列分布，且与各第一电极31的中间部310一一对应设置，即各平缓部62在第一绝缘层2上的正投影一一对应的位于各第一电极31以内。平缓部62平行或大致平行于中间部310。
凹陷部61与第一绝缘层2未被中间部310覆盖的区域对应，用于分隔平缓部62，凹陷部61向平缓部62靠近衬底1的一侧凹陷。凹陷部61为环形结构，且数量为多个，各个凹陷部61一一对应的围绕各平缓部62，也就是说，凹陷部61为相邻两个平缓部62的过渡区域。
凹陷部61在衬底1上的正投影至少部分位于第一电极31的中间部310以外，从而与第一电极31以外的区域或厚度较小的边缘部311正对，而不与厚度较大的中间部310正对，可降低凹陷部61与第一电极31之间出现尖端放电和短路的风险，从而提高发光器件发光的稳定性。
在本公开的一些实施方式中，在垂直于衬底1的截面上，凹陷部61的最低点在第一绝缘层2上的正投影位于中间部310以外，例如，该最低点与爬坡部3111和平坦部3110之一对应，以避免与中间部310之间发生尖端放电。凹陷部61在垂直于衬底1的截面上的最低点为：在垂直于衬底1的截面上，凹陷部61距离第一电极31最近的一点，也即 距离平缓部62最远的一点。
需要说明的是，凹陷部61在垂直于衬底1的截面的数量可以有多个，不同截面上的最低点可能不同，例如，该最低点可以是深度方向上距离第一电极31的中间部310最近的一点，也可以是深度方向上的其它点，具体视垂直于衬底1的截面的位置而定。
如图7-图9所示，在本公开的一些实施方式中，凹陷部61具有两个侧面，包括第一侧面611、第二侧面612和底面613，其中，第一侧面611和第二侧面612相对设置，且连接于底面613的两侧。同时，第一侧面611和第二侧面612可沿靠近衬底1的方向收缩。第一侧面611和第二侧面612可以是曲面或平面，在此不做特殊限定。
底面613可为向背离衬底1的方向凸起的曲面，在本公开的一些实施方式中，凹陷部61的底面613包括第一坡面6131、第二坡面6132和连接面6133，其中，第一坡面6131和第二坡面6132均可为曲面或平面，连接面6133位于第一侧面611和第二侧面612的底边背离衬底1的一侧，且连接面6133连接于第一坡面6131和第二坡面6132之间。第一坡面6131与第一侧面611的底边连接，第二坡面6132与第二侧面612的底边连接。
在本公开的一些实施方式中，第一坡面6131相对于中间部310的坡度不小于第一侧面611相对于中间部310的坡度。同时，第二坡面6132相对于中间部310的坡度不小于第二侧面612相对于中间部310的坡度。
进一步对，在垂直于衬底1的截面中，第一坡面6131与第二坡面6132关于连接面6133对称，即第一坡面6131的垂直于衬底1的截面与第二坡面6132的垂直于衬底1的截面关于连接面6133的垂直于衬底1的截面对称。同时，在垂直于衬底1的截面中，第一侧面611和第二侧面612关于底面613对称，即第一侧面611的垂直于衬底1的截面和第二侧面612的垂直于衬底1的截面关于底面613的垂直于衬底1的截面对称。
在本公开的一些实施方式中，第二电极6对应于第一侧面611和第二侧面612的区域的最小厚度，大于第二电极6对应于第一坡面6131和第二坡面6132的区域的最小厚度。
进一步的，如图7所示，在本公开的一些实施方式中，凹陷部61的深度小于第二电极6最大厚度的两倍，举例而言，第二电极6的最大厚度为90nm，凹陷部61的深度小于180nm，例如120nm、100nm、80nm、70nm、60nm、50nm、40nm等。凹陷部61的深度指凹陷部61的最大深度，即：在垂直于衬底1的方向上，凹陷部61距离衬底1最近的一点与平缓部62背离衬底1的表面的距离。
在本公开的一些实施方式中，如图7和图8所示，每个凹陷部61在第一绝缘层2的正投影围绕于一第一电极31的中间部310外，凹陷部61的底面613与相邻的第一电极31的中间部310的距离的最小值(在垂直于衬底1的方向上，凹陷部61距离中间部310最近的一点与中间部310的距离)不小于平缓部62和发光功能层5的总厚度的70％，平缓部62和发光功能层5的总厚度为平缓部62和发光功能层5的厚度之和，例如，平缓部62和发光功能层5的总厚度约为365nm，则凹陷部61在垂直于衬底1的方向的底 部与相邻的第一电极31的中间部310距离的最小值的最大值约为255nm。
进一步的，凹陷部61的底部与相邻的第一电极31的中间部310的距离的最大值(在垂直于衬底1的方向上，凹陷部61距离中间部310最近的一点与中间部310的距离)的最大值不小于400nm，且该最大值不大于450nm。
如图7所示，为了便于形成上文中的第二电极6，在本公开的一些实施方式中，第一绝缘层2背离衬底1的表面可开设多个分隔槽201，分隔槽201的深度小于第一绝缘层2的厚度，即分隔槽201在深度方向上不会贯穿第一绝缘层2。通过分隔槽201可在第一绝缘层2上分割出多个像素区202，且各像素区202阵列分布。分隔槽201的具体结构可参考上述第一种显示面板的实施方式，在此不再详述。同时，本公开的第二种显示面板还包括像素定义层4，像素定义层4为绝缘材质，且与第一电极层3均设于第一绝缘层2背离衬底1的表面。同时，像素定义层4露出第一电极31的中间部310的至少部分区域，并在对应于分隔槽201的区域凹陷，被像素定义层4露出的中间部310可与对应的发光功能层5和第二电极6构成发光器件。像素定义层4的结构可参考上述第一种显示面板的实施方式，在此不再详述。
发光功能层5还覆盖像素定义层4以及第一绝缘层2未被像素定义层4和第一电极31覆盖的区域，在通过蒸镀或其它工艺形成发光功能层5时，发光功能层5在对应分隔槽201的区域向靠近衬底1的方向凹陷。第二电极6的凹陷部61在第一绝缘层2的正投影至少部分位于分隔槽201的范围内。
此外，如图7所示，本公开的第一种显示面板还可包括第一封装层13，第一封装层13可覆盖第二电极6，举例而言，第一封装层13可包括两层无机层和两层无机层之间的有机层。第一封装层13在对应于凹陷部61的区域形成凹坑1301，凹坑1301的两个侧壁向靠近衬底1的方向收窄，且两个侧壁连接。
此外，该显示面板还可包括彩膜层14、第二封装层15和透明盖板16，其中：
彩膜层14设于第一封装层13背离第二电极6的一侧，且彩膜层14包括一一对应于各第一电极31的滤光区，滤光区的颜色有多种，例如红色、蓝色和绿色。
第二封装层15可覆盖彩膜层14，其结构可与第一封装层13相同。
透明盖板16可覆盖第二封装层15，其材质可以是玻璃或材料。
此外，在本公开的一些实施方式中，如图7所示，第二种显示面板还可包括光提取层17，光提取层17覆盖于第二电极6背离衬底1的表面，且在对应与凹陷部61的区域凹陷，第一封装层13设于光提取层17背离衬底1的一侧。光提取层17的折射率大于第二电极6，可提高出光效率，且折射率越高，出光效率越高。
第三种显示面板
如图10和图11所示，显示面板可包括衬底1、第一绝缘层2、第一电极层3、像素定义层4、发光功能层5和第二电极6，其中：
第一绝缘层2设于衬底1一侧，且第一绝缘层2具有阵列分布的多个像素区202以及分隔像素区202分隔区201。
第一电极层3设于第一绝缘层2背离衬底1的表面，且包括阵列分布的多个第一电极31，各第一电极31在第一绝缘层2的正投影位于各像素区202以内。
像素定义层4设于第一绝缘层2背离衬底1的表面，且露出各第一电极31；像素定义层4在对应于分隔区201的区域形成有像素定义槽41，像素定义槽41的中部具有向背离衬底1的方向凸起的第一凸起42，第一凸起42的侧壁与像素定义槽41的侧壁之间形成子槽40。
发光功能层5覆盖像素定义层4以及被像素定义层4露出的第一电极31。
第二电极6覆盖发光功能层5。
需要说明是，本文中的像素定义槽41的中部是指像素定义槽41的两侧壁之间的底面的任意区域，并不限定为像素定义槽41的两侧壁之间距该两侧壁距离相等的区域。
本公开实施方式的显示面板，每个第一电极31被像素定义层4露出的区域及其对应的发光功能层5和第二电极6可用于构成一发光器件，以便发光。
由于第一电极31在第一绝缘层2的正投影位于各像素区202以内，使得像素定义槽41位于第一电极31以外，在形成发光功能层5时，发光功能层5可在像素定义槽41的位置向衬底1凹陷，进而使第二电极6在该凹陷处形成的凹陷部61，且凹陷部61在第一绝缘层2的正投影至少部分位于像素定义层4的范围内，至少部分位于发光器件以外，由此，可通过像素定义槽41对第二电极6的凹陷部61的位置进行限制，防止凹陷部61与第一电极31之间发生尖端放电，甚至短路，有利于保证发光器件稳定发光。同时，可减少、甚至避免凹陷部61的范围内发光，从而降低相邻发光器件发光的互相干扰。
此外，由于像素定义槽41的中部的第一凸起42与像素定义槽41的侧壁之间形成子槽40，使像素定义槽41中部的形貌凹凸不平，若发光功能层5包含电荷产生层，则电荷产生层难以形成在两个子槽40侧壁上，从而有利于使电荷产生层像素定义槽41内截断，避免相邻两个发光器件之间出现串扰。当然，像素定义槽41的子槽40还可将空穴注入层或其它膜层截断，同样可防止串扰。
下面对本公开实施方式第三种显示面板的各部分进行详细说明：
如图10所示，衬底1的材料可为单晶硅或多晶硅等半导体材料，也可以是玻璃等其它硬质或软质材料。
在本公开的一些实施方式中，衬底1上可设有多个驱动晶体管，用于驱动各个发光器件发光，以显示图像。以一个顶栅结构的驱动晶体管为例，显示面板还包括栅绝缘层7、栅极8、第二绝缘层9和第一走线层10，其中：衬底1的材料可为单晶硅或多晶硅等半导体材料，且衬底1包括有源区101和位于有源区101两端的源极1011和漏极1012。栅绝缘层7覆盖有源区101；栅极8设于栅绝缘层7背离衬底1的表面，栅极8的材料可包括多晶硅材料。第二绝缘层9覆盖栅极8和衬底1，其材料可包括氧化硅和氮化硅 中至少一个。第一走线层10设于第二绝缘层9背离衬底1的表面，且栅极8、源极1011和漏极1012均通过钨或其它金属填充的过孔与第一走线层10连接。
此外，显示面板还可包括第三绝缘层11和第二走线层12，第三绝缘层11覆盖第一走线层10和第二绝缘层9，第二走线层12设于第三绝缘层11背离衬底1的表面，第二走线层12的具体图案在此不做特殊限定，其可通过钨或其它金属填充的过孔与第一走线层10连接。
如图10所示，第一绝缘层2设于衬底1的一侧，在本公开的一些实施方式中，第一绝缘层2可覆盖第二走线层12，第一电极31可通过钨或其它金属填充的过孔与第二走线层12连接。第一绝缘层2的材料可包括氮化硅和氧化硅中至少一种，当然，还可以包括其它绝缘材料。举例而言，第一绝缘层2可通过抛光工艺实现平坦化。
第一绝缘层2可划分出多个像素区202，各像素区202阵列分布，且间隔设置。驱动区201以外的区域为分隔区201，从而通过分隔区201将像素区202分隔开。
像素区202在衬底1的正投影的形状可以是矩形、五边形、六边形或其它多边形，当然，也可以是圆形或其它形状，在此不作特殊限定。同时，不同像素区202的形状和尺寸可以不同。
在本公开的一些实施方式中，例如，分隔区201可包括第一分隔区和第二分隔区，其中，第一分隔区的数量为多个，且各第一分隔区沿第一方向直线延伸，并沿第二方向间隔分布；第二分隔区的数量为多个，且各第二分隔区沿第二方向直线延伸，并沿第一方向间隔分布；第一方向和第二方向为相互交叉的方向，例如，第一方向和第二方向为相互垂直的方向。由此，可通过交错的第一分隔区和第二分隔区在第一绝缘层2上分割出阵列分布的多个像素区202。
在本公开的其它实施方式中，第一分隔区和第二分隔区也可沿曲线或折线轨迹延伸，从而分割出其他形状的像素区202。
如图10所示，第一电极层3设于第一绝缘层2背离衬底1的表面，且包括阵列分布的多个第一电极31，各第一电极31在第一绝缘层2的正投影一一对应的位于各像素区202以内，即各第一电极31在衬底1的正投影的边界一一对应的位于各像素区202在衬底1的正投影的边界以内。每个像素区202上只设置一个第一电极31。由于像素区202是分隔区201分隔而成，而第一电极31位于像素区202上，因此，分隔区201位于第一电极31以外。每个第一电极31在第一绝缘层2的正投影的形状可与其所处的像素区202的形状相同，第一电极31的边界位于其所处的像素区202以内。
在平行于衬底1的方向上，至少一个第一电极31可包括中间部310和围绕中间部310边缘部311，其中，中间部310为平坦结构，即中间部310与第一绝缘层2背离衬底1的表面大致平行。
在本公开的一些实施方式中，每个第一电极31的中间部310在衬底1的正投影的边界可位于其所处的像素区202在衬底1的正投影的边界以内，即中间部310在衬底1的 正投影的边界与其所处的像素区202在衬底1的正投影的边界具有不为0的间距L。进一步的，该间距L不小于0.15μm，例如，该间距L可以是0.15μm、0.2μm、0.25μm等。
边缘部311可包括平坦部3110以及爬坡部3111，其中，平坦部3110位于第一绝缘层2背离衬底1的表面，并围绕中间部310设置，且平坦部3110与第一绝缘层2背离衬底1的表面大致平行。同时，平坦部3110的厚度小于中间部310的厚度。在本公开的一些实施方式中，平坦部3110在衬底1的正投影的边界与其所处的像素区202在衬底1的正投影的边界之间具有不为0的间距。当然，平坦部3110在衬底1的正投影的边界与其所处的像素区202在衬底1的正投影的边界重叠。
爬坡部3111连接于中间部310和平坦部3110之间，即爬坡部3111围绕中间部310，平坦部3110围绕爬坡部3111设置。在本公开的一些实施方式中，爬坡部3111相对于第一绝缘层2背离衬底1的表面的坡度不小于30°，该坡度为爬坡部3111的表面与第一绝缘层2背离衬底1的表面的夹角。
第一电极31可包括第一导电层320、第二导电层321和第三导电层322，第一导电层320设于第一绝缘层2背离衬底1的表面，第二导电层321设于第一导电层320背离衬底1的表面，第三导电层322设于第二导电层321背离衬底1的表面，并以一定的坡度延伸至第一绝缘层2，从而包覆第一导电层320和第二导电层321，对第一导电层320和第二导电层321进行保护。
第一电极31的中间部310包括第三导电层322位于第二导电层321背离衬底1的表面的区域以及第一导电层320和第二导电层321，边缘部311包括第三导电层322包覆第一导电层320和第二导电层321边缘的区域，即向第一绝缘层2延伸的区域。示例性的，第一导电层320的材料可包括钛(Ti)、第二导电层321的材料包括银(Ag)、第三导电层322的材料包括氧化铟锡(ITO)，当然，也可以采用其他材料。
如图10所示，像素定义层4为绝缘材质，且与第一电极层3均设于第一绝缘层2背离衬底1的表面，并露出第一电极31的至少部分区域。
举例而言，像素定义层4设有一一对应露出各中间部310的至少部分区域的多个开口401。被像素定义层4露出的第一电极31可与对应的发光功能层5和第二电极6构成发光器件。在本公开的一些实施方式中，像素定义层4的开口401可为六边形或其它多边形结构，第一电极31也可为多边形结构，且与开口401的形状相同，当然，第一电极31也可以是其它形状。具体可参考图5和图6中的第一种显示面板的实施方式。
如图10所示，像素定义层4在对应于分隔区201的区域形成有像素定义槽41，可通过光刻工艺在形成像素定义层4时形成像素定义槽41。当然，也可以通过在第一绝缘层2的分隔区201设置分隔槽来使像素定义层4在分隔槽处凹陷，从而形成像素定义槽41。
在本公开的一些实施方式中，像素定义层4可包括间隔部400和延伸部410，其中：间隔部400位于第一绝缘层2未被第一电极31覆盖的区域，即位于第一电极31以外的 区域，像素定义槽41设于间隔部400。延伸部410连接于间隔部400，并延伸至第一电极31背离衬底1的表面，且不完全覆盖第一电极31，例如，延伸部410沿第一电极31的周向延伸至31中间部310的周向背离衬底1的表面上，且不完全覆盖中间部310，以形成开口401。
进一步的，覆盖任一第一电极31的延伸部410的宽度小于相邻两第一电极31之间的间隔部400的宽度。也就是说，对于任一第一电极31而言，延伸部410位于该第一电极31背离衬底1的表面上的区域呈环形结构，该环形结构的宽度小于与该第一电极31相邻的间隔部400的宽度，该环形结构的宽度为其两侧壁之间的距离。
基于上述的像素定义层4，像素定义槽41的中部可具有向背离衬底1的方向凸起的第一凸起42，第一凸起42的侧壁与像素定义槽41的侧壁之间形成子槽40。相较于像素定义槽41的中部平整的情况，第一凸起42可使像素定义槽41的中部的形貌更加复杂，有利于使上方的发光功能层5的电荷产生层或其它膜层断开，从而防止相邻发光器件之间发生串扰。
需要说明是，本文中的子槽40的中部是指子槽40的两侧壁之间的底面的任意区域，并不限定为子槽40的两侧壁之间距该两侧壁距离相等的区域。
在本公开的一些实施方式中，第一凸起42的两侧壁为向衬底1扩张的斜面，像素定义槽41的两侧壁为向衬底1收缩的斜面，也就是说，第一凸起42的两侧壁的间距向衬底1逐渐增大，像素定义槽41的两侧壁的间距向衬底1逐渐减小。由此，子槽40为两侧壁向衬底1收缩的凹槽。
进一步的，第一凸起42的侧壁的坡度与像素定义槽41的侧壁的坡度不同。第一凸起42的侧壁的坡度为第一凸起42的侧壁与第一绝缘层2背离衬底1的表面的夹角，像素定义槽41的侧壁的坡度为像素定义槽41的侧壁与第一绝缘层2背离衬底1的表面的夹角。其中，若第一凸起42的侧壁和像素定义槽41的侧壁为弧面，则二者的坡度为弧面的各切面与第一绝缘层2背离衬底1的表面的夹角中的最大值或者平均值。
进一步的，第一凸起42的厚度可小于像素定义槽41的深度，使得第一凸起42不凸出于第一绝缘层2背离衬底1的表面，而完全位于像素定义槽41以内。
如图10所示，发光功能层5可为连续的膜层，且至少部分覆盖各第一电极31的中间部310，即覆盖被开口401露出的区域，同时，发光功能层5还可覆盖像素定义层4的至少部分区域，在通过蒸镀或其它工艺形成发光功能层5时，发光功能层5在对应像素定义槽41的区域向靠近衬底1的方向凹陷。
在本公开的一实施方式中，如图11所示，发光功能层5包括多层发光单元层501，每层发光单元层501的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层的分布方式相同。同时，相邻两发光单元层501之间设有电荷产生层502，从而通过电荷产生层502将各发光单元层501串联，以便形成串联式的OLED发光器件。
在本公开的另一些实施方式中，发光功能层5包括一层发光单元层，发光单元层包 括由第一电极31向背离衬底1的方向依次层叠的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层。
电荷产生层502难以覆盖像素定义槽41的子槽40的侧壁，从而可通过像素定义槽41将发光器件的电荷产生层502截断，避免相邻两个发光器件之间出现串扰。当然，像素定义槽41还可将空穴注入层或其它膜层截断，同样可防止串扰。
需要说明的是，发光功能层5为连续膜层，但并非其每一膜层均为连续膜层。举例而言，在本公开的一些实施方式中，发光功能层5的发光层可包括多个间隔分布的发光部，每个发光部位于一开口401内，使得每个发光器件具有独立的发光部，不同发光部的材料可以不同，使得不同发光器件的发光颜色可以不同，而发光功能层5的其它膜层可为前述的连续膜层，即各发光器件可共用这些连续膜层。
如图10所示，第二电极6覆盖发光功能层5，可向第一电极31和第二电极6施加驱动信号，使发光功能层5位于第一电极31和第二电极6之间的部分发光。
第二电极6和第一电极31之间具有一定的距离，因而可形成微腔，发光功能层5发出的光线会在第一电极31和第二电极6发生一定程度的反射，在光的波长和微腔的深度满足谐振条件时，光线根据相涨干涉的原理而得到加强，有利于提高发光器件的亮度。但是，由于不同颜色的光线的波长不同，发光颜色不同的发光器件的微腔的深度可以不同。
在本公开的一些实施方式中，不同发光器件的发光层的发光颜色可以不同，为了微腔对不同颜色的光线的加强作用相同，可使不同发光颜色的发光器件的第一电极31的厚度不同，从而使微腔的深度与光的波长匹配，发光的波长越长，微腔的深度越大。进一步的，第一电极31包括第一导电层320、第二导电层321和第三导电层322，第一导电层320可为反光材质，微腔的深度可为第一导电层320与第二电极6之间的距离。可使两个第一电极31的第一导电层320的厚度不同，而第二导电层321的厚度相同，第三导电层322的厚度也相同，使得两第一电极31的厚度不同。
第二电极6的形貌与发光功能层5相匹配，其在发光功能层5的凹陷处凹陷，形成凹陷部61，并在对应于第一电极31的中间部310的区域形成平缓部62，使凹陷部61在第一绝缘层2上的正投影至少部分位于第一电极31的中间部310以外，减少或避免第一电极31与第二电极6的凹陷部61发生尖端放电。第二电极6的材料可以是合金材料，例如第二电极6的材料可包括Mg和Ag；或者，第二电极6还可采用Al和Li合金。当然，第二电极6还可以采用其他合金或单质金属，在此不再一一列举。
在本公开的一些实施方式中，像素定义层4的延伸部410覆盖中间部310的边缘，第二电极6在对应于延伸部410的区域可向背离衬底1的方向凸起，但凸起的高度小于中间部310的厚度，以使平缓部62与凹陷部61的衔接处大致保持平缓。
进一步的，如图10和图11所示，在本公开的一些实施方式中，第二电极6的凹陷部61在垂直于衬底1的截面上的最低点在第一绝缘层2的正投影完全位于像素定义槽 41以内，即完全位于中间部310以外。
此外，在本公开的一些实施方式中，如图10和图11所示，第三种显示面板还可包括第一封装层13、彩膜层14、第二封装层15和透明盖板16，其中：
第一封装层13可覆盖第二电极6，举例而言，第一封装层13可包括两层无机层和两层无机层之间的有机层。
在本公开的一些实施方式中，第一封装层13在对应凹陷部61的区域可凹陷形成凹坑1301，当然，若第一封装层13厚度较大，第一封装层13背离衬底1的表面也可大致保持平坦。进一步的，
彩膜层14设于第一封装层13背离第二电极6的一侧，且彩膜层14包括一一对应于各第一电极31的滤光区，滤光区的颜色有多种，例如红色、蓝色和绿色。
第二封装层15可覆盖彩膜层14，其结构可与第一封装层13相同。
透明盖板16可覆盖第二封装层15，其材质可以是玻璃或材料。
此外，在本公开的一些实施方式中，如图10和图11所示，第三种显示面板还可包括光提取层17，光提取层17覆盖于第二电极6背离衬底1的表面，且在对应与凹陷部61的区域凹陷，第一封装层13设于光提取层17背离衬底1的一侧。光提取层17的折射率大于第二电极6，可提高出光效率，且折射率越高，出光效率越高。
第四种显示面板
如图12和图13所示，显示面板可包括衬底1、第一绝缘层2、第一电极层3、像素定义层4、发光功能层5和第二电极6，其中：
第一绝缘层2设于衬底1一侧。
第一电极层3设于第一绝缘层2背离衬底1的表面，且包括阵列分布的多个第一电极31。
像素定义层4设于第一绝缘层2背离衬底1的表面，且露出各第一电极31。
发光功能层5覆盖像素定义层4以及被像素定义层4露出的第一电极31和第一绝缘层2。
第二电极6覆盖发光功能层5，且包括凹陷部61和被凹陷部61分隔的多个平缓部62，各平缓部62在第一绝缘层2上的正投影位于各第一电极31以内；凹陷部61的至少部分区域向平缓部62靠近衬底1的一侧凹陷，凹陷部61在第一绝缘层2上的正投影至少部分位于像素定义槽41内，凹陷部61的中部对应于第一凸起42的位置具有第二凸起600，第二凸起600的侧面与凹陷部61的侧面之间形成子凹陷610。
需要说明是，本文中的凹陷部61的中部是指凹陷部61的两侧壁之间的底面的任意区域，并不限定为凹陷部61的两侧壁之间距该两侧壁距离相等的区域。
本公开实施方式的显示面板，每个第一电极31被像素定义层4露出的区域及其对应的发光功能层5和第二电极6可构成一发光器件，以便发光。由于第二电极6的凹陷部 61在第一绝缘层2的正投影至少部分位于第一电极以外，可防止凹陷部61与第一电极31之间发生尖端放电，甚至短路，有利于保证发光器件稳定发光。同时，可减少、甚至避免凹陷部61的范围内发光，从而降低相邻发光器件发光的互相干扰。
下面对本公开实施方式第四种显示面板的各部分进行详细说明：
如图12和图13所示，在本公开的一些实施方式中，衬底1上可设有多个驱动晶体管，用于驱动各个发光器件发光，以显示图像。以一个顶栅结构的驱动晶体管为例，显示面板还包括栅绝缘层7、栅极8、第二绝缘层9和第一走线层10，其中：衬底1的材料可为单晶硅或多晶硅等半导体材料，且衬底1包括有源区101和位于有源区101两端的源极1011和漏极1012。栅绝缘层7覆盖有源区101；栅极8设于栅绝缘层7背离衬底1的表面，栅极8的材料可包括多晶硅材料。第二绝缘层9覆盖栅极8和衬底1，其材料可包括氧化硅和氮化硅中至少一个。第一走线层10设于第二绝缘层9背离衬底1的表面，且栅极8、源极1011和漏极1012均通过钨或其它金属填充的过孔与第一走线层10连接。
此外，显示面板还可包括第三绝缘层11和第二走线层12，第三绝缘层11覆盖第一走线层10和第二绝缘层9，第二走线层12设于第三绝缘层11背离衬底1的表面，第二走线层12的具体图案在此不做特殊限定，其可通过钨或其它金属填充的过孔与第一走线层10连接。
如图12和图13所示，第一绝缘层2设于衬底1的一侧，在本公开的一些实施方式中，第一绝缘层2可覆盖第二走线层12，第一电极31可通过钨或其它金属填充的过孔与第二走线层12连接。第一绝缘层2的材料可包括氮化硅和氧化硅中至少一种，当然，还可以包括其它绝缘材料。举例而言，第一绝缘层2可通过抛光工艺实现平坦化。
第一绝缘层2具有分隔区201，通过分隔区201可在第一绝缘层2上分割出多个像素区202，且各像素区202阵列分布。
如图12和图13所示，第一电极层3设于第一绝缘层2背离衬底1的表面，且包括阵列分布的多个第一电极31。
在本公开的一些实施方式中，各第一电极31在第一绝缘层2的正投影一一对应的位于各像素区202以内，即各第一电极31在衬底1的正投影的边界一一对应的位于各像素区202在衬底1的正投影的边界以内。每个像素区202上只设置一个第一电极31。由于像素区202是分隔区201分隔而成，而第一电极31位于像素区202上，因此，分隔区201位于第一电极31以外。每个第一电极31在第一绝缘层2的正投影的形状可与其所处的像素区202的形状相同，第一电极31的边界位于其所处的像素区202以内。
在平行于衬底1的方向上，至少一个第一电极31可包括中间部310和围绕中间部310边缘部311，其中，中间部310为平坦结构，即中间部310与第一绝缘层2背离衬底1的表面大致平行。
在本公开的一些实施方式中，每个第一电极31的中间部310在衬底1的正投影的边界可位于其所处的像素区202在衬底1的正投影的边界以内，即中间部310在衬底1的 正投影的边界与其所处的像素区202在衬底1的正投影的边界具有不为0的间距L。进一步的，该间距L不小于0.15μm，例如，该间距L可以是0.15μm、0.2μm、0.25μm等。
边缘部311可包括平坦部3110以及爬坡部3111，其中，平坦部3110位于第一绝缘层2背离衬底1的表面，并围绕中间部310设置，且平坦部3110与第一绝缘层2背离衬底1的表面大致平行。同时，平坦部3110的厚度小于中间部310的厚度。在本公开的一些实施方式中，平坦部3110在衬底1的正投影的边界与其所处的像素区202在衬底1的正投影的边界之间具有不为0的间距。当然，平坦部3110在衬底1的正投影的边界与其所处的像素区202在衬底1的正投影的边界重叠。
爬坡部3111连接于中间部310和平坦部3110之间，即爬坡部3111围绕中间部310，平坦部3110围绕爬坡部3111设置。在本公开的一些实施方式中，爬坡部3111相对于第一绝缘层2背离衬底1的表面的坡度不小于30°，该坡度为爬坡部3111的表面与第一绝缘层2背离衬底1的表面的夹角。
如图12和图13所示，第一电极31可包括第一导电层320、第二导电层321和第三导电层322，第一导电层320设于第一绝缘层2背离衬底1的表面，第二导电层321设于第一导电层320背离衬底1的表面，第三导电层322设于第二导电层321背离衬底1的表面，并以一定的坡度延伸至第一绝缘层2，从而包覆第一导电层320和第二导电层321，对第一导电层320和第二导电层321进行保护。
第一电极31的中间部310包括第三导电层322位于第二导电层321背离衬底1的表面的区域以及第一导电层320和第二导电层321，边缘部311包括第三导电层322包覆第一导电层320和第二导电层321边缘的区域，即向第一绝缘层2延伸的区域。示例性的，第一导电层320的材料可包括钛(Ti)、第二导电层321的材料包括银(Ag)、第三导电层322的材料包括氧化铟锡(ITO)，当然，也可以采用其他材料。
如图12和图13所示，像素定义层4为绝缘材质，且与第一电极层3均设于第一绝缘层2背离衬底1的表面，并露出第一电极31的至少部分区域。
举例而言，像素定义层4设有一一对应露出各中间部310的至少部分区域的多个开口401。被像素定义层4露出的第一电极31可与对应的发光功能层5和第二电极6构成发光器件。在本公开的一些实施方式中，像素定义层4的开口401可为六边形或其它多边形结构，第一电极31也可为多边形结构，且与开口401的形状相同，当然，第一电极31也可以是其它形状，具体可参考图5和图6示出的第一种显示面板。
如图12和图13所示，像素定义层4对应于分隔区201的区域形成有像素定义槽41。
基于上述的像素定义层4，像素定义槽41的中部可具有向背离衬底1的方向凸起的第一凸起42，第一凸起42的侧壁与像素定义槽41的侧壁之间形成子槽40。相较于像素定义槽41的中部平整的情况，第一凸起42可使像素定义槽41的中部的形貌更加复杂，有利于使上方的发光功能层5的电荷产生层或其它膜层断开，从而防止相邻发光器件之间发生串扰。进一步的，为了保证像素定义槽41具有足够的深度，以便截断上方的部分 膜层，可使像素定义槽41的中部位于分隔区201内，即像素定义槽41距离衬底1最近的一点或多点位于第一绝缘层2背离衬底1的表面靠近衬底1的一侧。相应的，子槽40的中部位于分隔区201内。
像素定义层4及其像素定义槽41的详细结构可参考上述第三种显示面板的实施方式，在此不再详述。
如图12和图13所示，发光功能层5可为连续的膜层，且至少部分覆盖各第一电极31的中间部310，即覆盖被开口401露出的区域，同时，发光功能层5还覆盖像素定义层4以及第一绝缘层2未被像素定义层4和第一电极31覆盖的区域，在通过蒸镀或其它工艺形成发光功能层5时，发光功能层5在对应像素定义槽41的区域向靠近衬底1的方向凹陷。
在本公开的一实施方式中，参考第三种显示面板的发光功能层5，如图10所示，发光功能层5包括多层发光单元层501，每层发光单元层501的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层的分布方式相同。同时，相邻两发光单元层501之间设有电荷产生层502，从而通过电荷产生层502将各发光单元层501串联，以便形成串联式的OLED发光器件。
在本公开的另一些实施方式中，发光功能层5包括一层发光单元层，发光单元层包括由第一电极31向背离衬底1的方向依次层叠的空穴注入层、空穴传输层、发光层、电子传输层和电子注入层。
电荷产生层502难以覆盖像素定义槽41的子槽40的侧壁，从而可通过像素定义槽41将发光器件的电荷产生层502截断，避免相邻两个发光器件之间出现串扰。当然，像素定义槽41还可将空穴注入层或其它膜层截断，同样可防止串扰。
如图12和图13所示，第二电极6覆盖发光功能层5，且包括凹陷部61和被凹陷部61分隔的多个平缓部62，各平缓部62在第一绝缘层2上的正投影一一对应的位于各第一电极31以内；凹陷部61向平缓部62靠近衬底1的一侧凹陷，凹陷部61在第一绝缘层2上的正投影至少部分位于第一电极31外，凹陷部61的中部具有第二凸起600，第二凸起600的侧面与凹陷部61的侧面之间形成子凹陷610。
在本公开的一些实施方式中，凹陷部61在第一绝缘层2上的正投影至少部分位于像素定义槽41内。进一步的凹陷部61的中部对应于第一凸起42的位置具有第二凸起600，第二凸起600的侧面与凹陷部61的侧面之间形成子凹陷610。子凹陷610距离衬底1最近的点在第一绝缘层2上的正投影位于子槽40内。
各平缓部62阵列分布，且与各第一电极31的中间部310一一对应设置，即各平缓部62在第一绝缘层2上的正投影一一对应的位于各第一电极31以内。平缓部62平行或大致平行于中间部310。
凹陷部61与第一绝缘层2未被中间部310覆盖的区域对应，用于分隔平缓部62，凹陷部61向平缓部62靠近衬底1的一侧凹陷。凹陷部61为环形结构，且数量为多个， 各个凹陷部61一一对应的围绕各平缓部62，也就是说，凹陷部61为相邻两个平缓部62的过渡区域。
凹陷部61在衬底1上的正投影至少部分位于第一电极31的中间部310以外，从而与第一电极31以外的区域或厚度较小的边缘部311正对，而不与厚度较大的中间部310正对，可降低凹陷部61与第一电极31之间出现尖端放电和短路的风险，从而提高发光器件发光的稳定性。
在本公开的一些实施方式中，在垂直于衬底1的截面上，凹陷部61的最低点在第一绝缘层2上的正投影位于中间部310以外，例如，该最低点与爬坡部3111和平坦部3110之一对应，以避免与中间部310之间发生尖端放电。凹陷部61在垂直于衬底1的截面上的最低点为：在垂直于衬底1的截面上，凹陷部61距离第一电极31最近的一点，也即距离平缓部62最远的一点。
需要说明的是，凹陷部61在垂直于衬底1的截面的数量可以有多个，不同截面上的最低点可能不同，例如，该最低点可以是深度方向上距离第一电极31的中间部310最近的一点，也可以是深度方向上的其它点，具体视垂直于衬底1的截面的位置而定。
如图12和图13所示，在本公开的一些实施方式中，凹陷部61具有两个侧面，包括第一侧面611、第二侧面612和第二凸起600，其中，第一侧面611和第二侧面612相对设置，且连接于第二凸起600的两侧。同时，第一侧面611和第二侧面612可沿靠近衬底1的方向收缩。第一侧面611和第二侧面612可以是曲面或平面，在此不做特殊限定。
第二凸起600可为向背离衬底1的方向凸起的曲面，在本公开的一些实施方式中，第二凸起600包括第一坡面6131、第二坡面6132和连接面6133，其中，第一坡面6131和第二坡面6132均可为曲面或平面，连接面6133位于第一侧面611和第二侧面612的底边背离衬底1的一侧，且连接面6133连接于第一坡面6131和第二坡面6132之间。第一坡面6131与第一侧面611的底边连接，并形成一子凹陷610，第二坡面6132与第二侧面612的底边连接，并形成另一子凹陷610。
在本公开的一些实施方式中，第一坡面6131相对于中间部310的坡度不小于第一侧面611相对于中间部310的坡度。同时，第二坡面6132相对于中间部310的坡度不小于第二侧面612相对于中间部310的坡度。
在本公开的一些实施方式中，第二电极6对应于第一侧面611和第二侧面612的区域的最小厚度，大于第二电极6对应于第一坡面6131和第二坡面6132的区域的最小厚度。
进一步的，如图12和图13所示，在本公开的一些实施方式中，凹陷部61的深度小于第二电极6最大厚度的两倍，举例而言，第二电极6的最大厚度为90nm，凹陷部61的深度小于180nm，例如120nm、100nm、80nm、70nm、60nm、50nm、40nm等。凹陷部61的深度指凹陷部61的最大深度，即：在垂直于衬底1的方向上，凹陷部61距离衬底1最近的一点与平缓部62背离衬底1的表面的距离。
在本公开的一些实施方式中，如图12和图13所示，每个凹陷部61在第一绝缘层2的正投影围绕于一第一电极31的中间部310外，凹陷部61的第二凸起600与相邻的第一电极31的中间部310的距离的最小值(在垂直于衬底1的方向上，凹陷部61距离中间部310最近的一点与中间部310的距离)不小于平缓部62和发光功能层5的总厚度的70％，平缓部62和发光功能层5的总厚度为平缓部62和发光功能层5的厚度之和，例如，平缓部62和发光功能层5的总厚度约为365nm，则凹陷部61在垂直于衬底1的方向的中部与相邻的第一电极31的中间部310距离的最小值的最大值约为255nm。
进一步的，凹陷部61的中部与相邻的第一电极31的中间部310的距离的最大值(在垂直于衬底1的方向上，凹陷部61距离中间部310最近的一点与中间部310的距离)的最大值不小于400nm，且该最大值不大于450nm。
如图12和图13所示，在本公开的一些实施方式中，像素定义层4可包括间隔部400和延伸部410，其中：间隔部400位于第一绝缘层2未被第一电极31覆盖的区域，即位于第一电极31以外的区域，像素定义槽41设于间隔部400。延伸部410连接于间隔部400，并延伸至第一电极31背离衬底1的表面，且不完全覆盖第一电极31，例如，延伸部410沿第一电极31的周向延伸至31中间部310的周向背离衬底1的表面上，且不完全覆盖中间部310。
由于延伸部410覆盖第一电极31的边界，使得对应于延伸部410的区域的第二电极6还具有向背离衬底1的方向凸起的凸起部63，平缓部62通过凸起部63与凹陷部61连接；凸起部63在衬底1上的正投影与延伸部410在衬底1上的正投影至少部分重合。
若相邻两第一电极31的厚度不同，而该两个第一电极31上的延伸部410背离衬底1的表面与衬底1的距离不同，使得连接于一凹陷部61两侧的两凸起部63中，一凸起部63距离衬底1最远点与衬底1的距离，不同于另一凸起部63距离衬底1最远点与衬底1的距离。
此外，如图12和图13所示，该显示面板还可包括第一封装层13、彩膜层14、第二封装层15和透明盖板16，其中：
第一封装层13可覆盖第二电极6，举例而言，第一封装层13可包括两层无机层和两层无机层之间的有机层。
在本公开的一些实施方式中，第一封装层13在对应凹陷部61的区域可凹陷形成凹坑1301，当然，若第一封装层13厚度较大，第一封装层13背离衬底1的表面也可大致保持平坦。
彩膜层14设于第一封装层13背离第二电极6的一侧，且彩膜层14包括一一对应于各第一电极31的滤光区，滤光区的颜色有多种，例如红色、蓝色和绿色。
第二封装层15可覆盖彩膜层14，其结构可与第一封装层13相同。
透明盖板16可覆盖第二封装层15，其材质可以是玻璃或材料。
此外，在本公开的一些实施方式中，如图12和图13所示，第四种显示面板还可包 括光提取层17，光提取层17覆盖于第二电极6背离衬底1的表面，且在对应与凹陷部61的区域凹陷，第一封装层13设于光提取层17背离衬底1的一侧。光提取层17的折射率大于第二电极6，可提高出光效率，且折射率越高，出光效率越高。22、根据上述任意一项所述的显示面板，其中，所述凹坑的两个侧壁向靠近所述衬底的方向收窄且连接。
本公开实施方式还提供一种显示面板的制造方法，该显示面板可为上述的第一种显示面板，如图14所示，该制造方法包括步骤S110-步骤S160，其中：
步骤S110、在一衬底一侧形成第一绝缘层；
步骤S120、在所述第一绝缘层背离所述衬底的表面形成多个分隔槽，以分割出阵列分布的多个像素区；
步骤S130、在所述第一绝缘层背离所述衬底的表面形成包括多个第一电极的第一电极层；各所述第一电极在所述第一绝缘层的正投影一一对应的位于各所述像素区以内；所述第一电极包括平坦的中间部和围绕所述中间部的边缘部；所述边缘部包括围绕所述中间部的平坦部以及连接于所述中间部和所述平坦部之间的爬坡部，所述平坦部的厚度小于所述中间部；
步骤S140、在所述第一绝缘层背离所述衬底的表面形成像素定义层，所述像素定义层露出所述中间部的至少部分区域。
步骤S150、形成发光功能层，所述发光功能层覆盖所述像素定义层以及被所述像素定义层露出的所述中间部和所述第一绝缘层。
步骤S160、形成覆盖所述发光功能层的第二电极。
本公开实施方式的制造方法的各层结构的细节及有益效果已在上文的第一种显示面板的实施方式中进行了说明，在此不再赘述。
本公开实施方式还提供一种显示面板的制造方法，该显示面板可为上述的第一种显示面板，如图15所示，该制造方法包括步骤S210-步骤S250，其中：
步骤S210、在一衬底一侧形成第一绝缘层；
步骤S220、在所述第一绝缘层背离所述衬底的表面形成包括多个第一电极的第一电极层和分隔槽；所述第一电极包括平坦的中间部和围绕所述中间部的边缘部；所述边缘部包括围绕所述中间部的平坦部以及连接于所述中间部和所述平坦部之间的爬坡部，所述平坦部的厚度小于所述中间部；所述分隔槽在所述第一绝缘层分割出阵列分布的多个像素区；各所述第一电极在所述第一绝缘层的正投影一一对应的位于各所述像素区以内；
步骤S230、在所述第一绝缘层背离所述衬底的表面形成像素定义层，所述像素定义层露出所述中间部的至少部分区域；
步骤S240、形成发光功能层，所述发光功能层覆盖所述像素定义层以及被所述像素 定义层露出的所述中间部和所述第一绝缘层；
步骤S250、形成覆盖所述发光功能层的第二电极。
在本实施方式的制造方法中，可先在第一绝缘层背离衬底的表面形成用于导电层，通过一次灰阶掩膜工艺对导电层进行图案化得到第一电极层，同时，通过该次灰阶掩膜工艺可一并形成分隔槽，相较于通过两次掩膜工艺分别形成第一电极层和分隔槽的方式，可使显示面板的制造工艺得以简化。
本公开实施方式还提供一种显示面板的制造方法，该显示面板可为上述的第二种显示面板，如图16所示，该制造方法包括步骤S310-步骤S340，其中：
步骤S310、在一衬底一侧形成第一绝缘层；
步骤S320、在所述第一绝缘层背离所述衬底的表面形成包括多个第一电极的第一电极层；所述第一电极包括平坦的中间部和围绕所述中间部的边缘部；所述边缘部包括围绕所述中间部的平坦部以及连接于所述中间部和所述平坦部之间的爬坡部，所述平坦部的厚度小于所述中间部；
步骤S330、形成覆盖所述中间部的至少部分区域的发光功能层；
步骤S340、形成覆盖所述发光功能层的第二电极，所述第二电极包括凹陷部和被所述凹陷部分隔的多个平缓部，各所述平缓部在所述第一绝缘层上的正投影一一对应的位于各所述第一电极以内；所述凹陷部向所述平缓部靠近所述衬底的一侧凹陷，所述凹陷部在所述第一绝缘层上的正投影至少部分位于所述中间部以外。
本公开实施方式的制造方法的各层结构的细节及有益效果已在上文的第二种显示面板的实施方式中进行了说明，在此不再赘述。
本公开实施方式还提供一种显示面板的制造方法，该显示面板可为上述的第三种显示面板，如图17所示，一种显示面板的制造方法，其中，包括步骤S410-步骤S450，其中：
步骤S410、在一衬底一侧形成第一绝缘层；所述第一绝缘层具有阵列分布的多个像素区以及分隔所述像素区的分隔区；
步骤S420、在所述第一绝缘层背离所述衬底的表面形成包括多个第一电极的第一电极层；各所述第一电极在所述第一绝缘层的正投影位于各所述像素区以内；
步骤S430、在所述第一绝缘层背离所述衬底的表面形成像素定义层，且露出各所述第一电极；所述像素定义层在对应于所述分隔区的区域形成有像素定义槽，所述像素定义槽的中部具有向背离所述衬底的方向凸起的第一凸起，所述第一凸起的侧壁与所述像素定义槽的侧壁之间形成子槽；
步骤S440、形成发光功能层，所述发光功能层覆盖所述像素定义层以及被所述像素定义层露出的所述第一电极；
步骤S450、形成覆盖所述发光功能层的第二电极。
本公开实施方式的制造方法的各层结构的细节及有益效果已在上文的第三种显示面板的实施方式中进行了说明，在此不再赘述。
本公开实施方式还提供一种显示面板的制造方法，该显示面板可为上述的第四种显示面板，如图18所示，一种显示面板的制造方法，其中，包括步骤S510-步骤S550，其中：
步骤S510、在一衬底一侧形成第一绝缘层；
步骤S520、在所述第一绝缘层背离所述衬底的表面形成第一电极层，所述第一电极层包括多个第一电极；
步骤S530、在所述第一绝缘层背离所述衬底的表面形成像素定义层，所述像素定义露出各所述第一电极；
步骤S540、形成发光功能层，所述发光功能层覆盖所述像素定义层以及被所述像素定义层露出的所述第一电极；
步骤S550、形成覆盖所述发光功能层的第二电极，所述第二电极包括凹陷部和被所述凹陷部分隔的多个平缓部，各所述平缓部在所述第一绝缘层上的正投影位于各所述第一电极以内；所述凹陷部的至少部分区域向所述平缓部靠近所述衬底的一侧凹陷，所述凹陷部在所述第一绝缘层上的正投影至少部分位于所述第一电极以外，所述凹陷部的中部具有第二凸起，所述第二凸起的侧面与所述凹陷部的侧面之间形成子凹陷。
本公开实施方式的制造方法的各层结构的细节及有益效果已在上文的第四种显示面板的实施方式中进行了说明，在此不再赘述。
需要说明的是，尽管在附图中以特定顺序描述了本公开中制造方法的各个步骤，但是，这并非要求或者暗示必须按照该特定顺序来执行这些步骤，或是必须执行全部所示的步骤才能实现期望的结果。附加的或备选的，可以省略某些步骤，将多个步骤合并为一个步骤执行，以及/或者将一个步骤分解为多个步骤执行等。
本公开实施方式还提供一种显示装置，该显示装置可包括上述的第一种显示面板、第二种显示面板、第三种显示面板和第四种显示面板的各实施方式中的任意一个，具体结构和有益效果可参考上文的实施方式，在此不再赘述。本公开的显示装置可用于手机、平板电脑、电视等电子设备，在此不再一一例举。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (22)

  1. 一种显示面板，其中，包括：
    衬底；
    第一绝缘层，设于所述衬底一侧，所述第一绝缘层具有阵列分布的多个像素区以及分隔所述像素区的分隔区；
    第一电极层，设于所述第一绝缘层背离所述衬底的表面，且包括多个第一电极；各所述第一电极在所述第一绝缘层的正投影位于各所述像素区以内；
    像素定义层，设于所述第一绝缘层背离所述衬底的表面，且露出各所述第一电极；所述像素定义层在对应于所述分隔区的区域形成有像素定义槽，所述像素定义槽的中部具有向背离所述衬底的方向凸起的第一凸起，所述第一凸起的侧壁与所述像素定义槽的侧壁之间形成子槽；
    发光功能层，覆盖所述像素定义层以及被所述像素定义层露出的所述第一电极；
    第二电极，覆盖所述发光功能层。
  2. 根据权利要求1所述的显示面板，其中，所述第一凸起的两侧壁为向所述衬底扩张的斜面，所述像素定义槽的两侧壁为向所述衬底收缩的斜面。
  3. 根据权利要求1所述的显示面板，其中，所述第一凸起的侧壁的坡度与所述像素定义槽的侧壁的坡度不同。
  4. 根据权利要求1所述的显示面板，其中，所述第一凸起的厚度小于所述像素定义槽的深度。
  5. 根据权利要求1所述的显示面板，其中，所述像素定义槽的中部在所述第一绝缘层上的正投影位于所述分隔区内。
  6. 根据权利要求1所述的显示面板，其中，所述像素定义层包括间隔部和延伸部，所述间隔部位于所述第一电极以外的区域，所述像素定义槽设于所述间隔部；所述延伸部连接于所述间隔部，并延伸至所述第一电极背离所述衬底的表面，且不完全覆盖所述第一电极。
  7. 根据权利要求6所述的显示面板，其中，覆盖任一所述第一电极的延伸部的宽度小于相邻两所述第一电极之间的间隔部的宽度。
  8. 根据权利要求1所述的显示面板，其中，至少两个所述第一电极的厚度不同。
  9. 根据权利要求1所述的显示面板，其中，所述像素定义槽的最大深度不大于所述发光功能层和所述第一电极的厚度和的60％。
  10. 一种显示面板，其中，包括：
    衬底；
    第一绝缘层，设于所述衬底一侧；
    第一电极层，设于所述第一绝缘层背离所述衬底的表面，且包括多个第一电极；
    像素定义层，设于所述第一绝缘层背离所述衬底的表面，且露出各所述第一电极；
    发光功能层，覆盖所述像素定义层以及被所述像素定义层露出的所述第一电极；
    第二电极，覆盖所述发光功能层，且包括凹陷部和被所述凹陷部分隔的多个平缓部，各所述平缓部在所述第一绝缘层上的正投影位于各所述第一电极以内；所述凹陷部的至少部分区域向所述平缓部靠近所述衬底的一侧凹陷，所述凹陷部在所述第一绝缘层上的正投影至少部分位于所述第一电极以外，所述凹陷部的中部具有第二凸起，所述第二凸起的侧面与所述凹陷部的侧面之间形成子凹陷。
  11. 根据权利要求10所述的显示面板，其中，所述第一绝缘层具有阵列分布的多个像素区以及分隔所述像素区的分隔区，各所述第一电极在所述第一绝缘层的正投影位于各所述第一电极以内；
    所述像素定义层露出各所述第一电极，且在对应于所述分隔区的区域形成有像素定义槽，所述像素定义槽的中部具有向背离所述衬底的方向凸起的第一凸起，所述第一凸起的侧壁与所述像素定义槽的侧壁之间形成子槽；
    所述凹陷部在所述第一绝缘层上的正投影至少部分位于所述像素定义槽内。
  12. 根据权利要求11所述的显示面板，其中，所述子凹陷距离所述衬底最近的点在所述第一绝缘层上的正投影位于所述子槽内。
  13. 根据权利要求11所述的显示面板，其中，所述凹陷部包括第一侧面和第二侧面，所述第一侧面和所述第二侧面相对连接于所述第二凸起的两侧，且所述第一侧面和所述第二侧面向所述衬底收缩。
  14. 根据权利要求13所述的显示面板，其中，所述第二凸起包括第一坡面、第二坡面以及连接于所述第一坡面和所述第二坡面之间的连接面，所述连接面位于所述第一侧面和所述第二侧面的底边背离所述衬底的一侧，所述第一坡面与所述第一侧面的底边连接，所述第二坡面与所述第二侧面的底边连接。
  15. 根据权利要求14所述的显示面板，其中，所述第二电极对应于所述第一侧面和所述第二侧面的区域的最小厚度，大于对应于所述第一坡面和所述第二坡面的区域的最小厚度。
  16. 根据权利要求11所述的显示面板，其中，所述像素定义层包括间隔部和延伸部，所述间隔部位于所述第一电极以外的区域，所述像素定义槽至少部分设于所述间隔部；所述延伸部连接于所述间隔部，并延伸至所述第一电极背离所述衬底的表面，且不完全覆盖所述第一电极；
    所述第二电极还具有向背离所述衬底的方向凸起的凸起部，所述平缓部通过所述凸起部与所述凹陷部连接；所述凸起部在所述衬底上的正投影与所述延伸部在所述衬底上的正投影至少部分重合。
  17. 根据权利要求16所述的显示面板，其中，在连接于一所述凹陷部两侧的两所述凸起部中，一所述凸起部距离所述衬底最远点与所述衬底的距离，不同于另一所述凸起部距离所述衬底最远点与所述衬底的距离。
  18. 根据权利要求10所述的显示面板，其中，所述显示面板还包括：
    第一封装层，覆盖所述第二电极，且在对应于所述凹陷部的区域形成凹坑。
  19. 根据权利要求18所述的显示面板，其中，所述凹坑的两个侧壁向靠近所述衬底的方向收窄且连接。
  20. 一种显示面板的制造方法，其中，包括：
    在一衬底一侧形成第一绝缘层；所述第一绝缘层具有阵列分布的多个像素区以及分隔所述像素区的分隔区；
    在所述第一绝缘层背离所述衬底的表面形成包括多个第一电极的第一电极层；各所述第一电极在所述第一绝缘层的正投影位于各所述像素区以内；
    在所述第一绝缘层背离所述衬底的表面形成像素定义层，且露出各所述第一电极；所述像素定义层在对应于所述分隔区的区域形成有像素定义槽，所述像素定义槽的中部具有向背离所述衬底的方向凸起的第一凸起，所述第一凸起的侧壁与所述像素定义槽的侧壁之间形成子槽；
    形成发光功能层，所述发光功能层覆盖所述像素定义层以及被所述像素定义层露出的所述第一电极；
    形成覆盖所述发光功能层的第二电极。
  21. 一种显示面板的制造方法，其中，包括：
    在一衬底一侧形成第一绝缘层；
    在所述第一绝缘层背离所述衬底的表面形成第一电极层，所述第一电极层包括多个第一电极；
    在所述第一绝缘层背离所述衬底的表面形成像素定义层，所述像素定义露出各所述第一电极；
    形成发光功能层，所述发光功能层覆盖所述像素定义层以及被所述像素定义层露出的所述第一电极；
    形成覆盖所述发光功能层的第二电极，所述第二电极包括凹陷部和被所述凹陷部分隔的多个平缓部，各所述平缓部在所述第一绝缘层上的正投影位于各所述第一电极以内；所述凹陷部的至少部分区域向所述平缓部靠近所述衬底的一侧凹陷，所述凹陷部在所述第一绝缘层上的正投影至少部分位于所述第一电极以外，所述凹陷部的中部具有第二凸起，所述第二凸起的侧面与所述凹陷部的侧面之间形成子凹陷。
  22. 一种显示装置，其中，包括权利要求1-19任一项所述的显示面板。
PCT/CN2021/088701 2020-04-21 2021-04-21 显示装置、显示面板及其制造方法 Ceased WO2021213439A1 (zh)

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