WO2021223086A1 - 显示基板、其制作方法、显示装置和显示面板 - Google Patents

显示基板、其制作方法、显示装置和显示面板 Download PDF

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Publication number
WO2021223086A1
WO2021223086A1 PCT/CN2020/088695 CN2020088695W WO2021223086A1 WO 2021223086 A1 WO2021223086 A1 WO 2021223086A1 CN 2020088695 W CN2020088695 W CN 2020088695W WO 2021223086 A1 WO2021223086 A1 WO 2021223086A1
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Prior art keywords
base substrate
layer
away
substrate
display
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PCT/CN2020/088695
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English (en)
French (fr)
Inventor
朱小研
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to KR1020227016150A priority Critical patent/KR102751002B1/ko
Priority to CN202080000678.3A priority patent/CN114072911B/zh
Priority to EP20934263.3A priority patent/EP4040491B1/en
Priority to US17/280,162 priority patent/US12009463B2/en
Priority to JP2022523726A priority patent/JP7509341B2/ja
Priority to PCT/CN2020/088695 priority patent/WO2021223086A1/zh
Publication of WO2021223086A1 publication Critical patent/WO2021223086A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H29/00—Integrated devices, or assemblies of multiple devices, comprising at least one light-emitting semiconductor element covered by group H10H20/00
    • H10H29/10—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00
    • H10H29/14—Integrated devices comprising at least one light-emitting semiconductor component covered by group H10H20/00 comprising multiple light-emitting semiconductor components
    • H10H29/142—Two-dimensional arrangements, e.g. asymmetric LED layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/036—Manufacture or treatment of packages
    • H10H20/0364—Manufacture or treatment of packages of interconnections

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate and a manufacturing method thereof, a display device and a display panel.
  • a related art Micro-LED display substrate includes a pixel area and a bonding area, and is bonded with a bonding circuit (bonding IC) in the bonding area to achieve electrical connection.
  • bonding IC bonding circuit
  • an embodiment of the present disclosure provides a display substrate, including a base substrate, a first conductive pattern on the base substrate, and a side of the first conductive pattern away from the base substrate.
  • the organic layer is provided with a via hole that penetrates the organic layer in a direction perpendicular to the base substrate, the position of the via hole corresponds to the position of the first conductive pattern, and the second conductive pattern
  • the layer is electrically connected to the first conductive pattern through the via hole;
  • the display substrate further includes a filling structure for filling the via hole, the distance between the surface of the filling structure on the side far from the base substrate and the base substrate and the distance between the organic layer on the side far from the base substrate The distance difference between the surface and the base substrate is less than a preset threshold.
  • it further includes a barrier layer located on a side of the organic layer away from the base substrate, and an area corresponding to the barrier layer and the via hole is located between the filling structure and the second Between conductive layers.
  • it further includes a barrier layer located on a side of the organic layer away from the base substrate, and an area corresponding to the via hole of the barrier layer is located at the filling structure away from the substrate.
  • a barrier layer located on a side of the organic layer away from the base substrate, and an area corresponding to the via hole of the barrier layer is located at the filling structure away from the substrate.
  • it further includes a buffer layer located on a side of the barrier layer away from the base substrate, and the distance difference between different regions of the buffer layer and the base substrate is less than the preset threshold.
  • it further includes one or more of a first gate insulating layer, a second gate insulating layer, and a dielectric layer on the side of the buffer layer away from the base substrate.
  • the first gate The distance difference between the different areas of the polar insulating layer and the base substrate is less than the preset threshold, and the distance difference between the different areas of the second gate insulating layer and the base substrate is less than the preset threshold , The distance difference between the different regions of the dielectric layer and the base substrate is less than the preset threshold.
  • an embodiment of the present disclosure provides a display panel, including the display substrate described in any one of the above.
  • an embodiment of the present disclosure provides a display device including the above-mentioned display panel.
  • an embodiment of the present disclosure provides a manufacturing method of a display substrate, including the following steps:
  • a filling structure is made to fill the via, the distance between the surface of the filling structure on the side away from the base substrate and the base substrate, and the surface of the organic layer on the side away from the base substrate and the liner
  • the distance difference between the base substrates is smaller than the preset threshold.
  • the method further includes:
  • a barrier layer is formed on the side of the filling structure away from the base substrate, and the distance between the barrier layer and the base substrate is uniform.
  • the method before the fabricating the filling structure to fill the via hole, the method further includes:
  • the fabricating a filling structure to fill the via hole includes:
  • a filling structure is formed to fill the via hole.
  • the display substrate and the manufacturing method thereof are provided with a filling structure for filling the via in the via hole of the binding area, so that the filling structure can be implemented. Share the pressure generated in the bonding process, reduce the possibility of stress concentration at the via hole, thereby reducing the possibility of damage to the display substrate.
  • FIG. 1A is a schematic diagram of a structure of a display substrate in at least one embodiment of the present disclosure
  • FIG. 1B is another schematic diagram of the structure of the display substrate in at least one embodiment of the present disclosure.
  • FIG. 1C is another schematic diagram of the structure of the display substrate in at least one embodiment of the present disclosure.
  • FIG. 1D is another schematic diagram of the structure of the display substrate in at least one embodiment of the present disclosure.
  • Figure 2A is a simulation model of a display substrate in the related art
  • Fig. 2B shows the stress simulation result of the substrate in the related art
  • 2C is a simulation model of a display substrate in at least one embodiment of the present disclosure.
  • 2D is a stress simulation result of the display substrate in at least one embodiment of the present disclosure
  • FIG. 3 is a flowchart of a manufacturing method of a display substrate in at least one embodiment of the present disclosure
  • 4A is a schematic diagram of an intermediate manufacturing process of a display substrate in at least one embodiment of the present disclosure
  • 4B is a schematic diagram of another intermediate manufacturing process of the display substrate in at least one embodiment of the present disclosure.
  • 4C is a schematic diagram of another intermediate manufacturing process of the display substrate in at least one embodiment of the present disclosure.
  • 4D is a schematic diagram of another intermediate manufacturing process of the display substrate in at least one embodiment of the present disclosure.
  • 4E is a schematic diagram of another intermediate manufacturing process of the display substrate in at least one embodiment of the present disclosure.
  • 4F is a schematic diagram of another intermediate manufacturing process of the display substrate in at least one embodiment of the present disclosure.
  • At least one embodiment of the present disclosure provides a display substrate.
  • the display substrate includes a base substrate 101, a first conductive pattern 102 located on the base substrate 101, an organic layer 103 located on the side of the first conductive pattern 102 away from the base substrate 101, and The organic layer 103 is away from the second conductive layer 104 on the side of the base substrate 101.
  • the display substrate has a pixel area and a binding area.
  • the pixel area includes a plurality of pixels and a driving circuit for providing electrical signals to the plurality of pixels
  • the binding area includes a binding structure connected to the driving circuit (such as a binding terminal ), used for bonding external drive circuits such as COF (Chip On Flex) or IC (Integrated Circuit).
  • the first conductive pattern 102 is located in the bonding area A shown in FIG. 1A.
  • the material of the base substrate 101 is a rigid material, for example, glass, and the display substrate needs to be peeled off from the base substrate 101 after the manufacturing is completed.
  • the organic layer 103 is provided with a via 105 that penetrates the organic layer 103 in a direction perpendicular to the base substrate 101.
  • the position of the via 105 corresponds to the position of the first conductive pattern 102, and the second conductive layer 104 passes through the via 105 It is electrically connected to the first conductive pattern 102.
  • the first conductive pattern 102 is a part of the binding structure, which is used to realize the electrical connection between the external driving circuit and the driving circuit on the display substrate.
  • the first conductive pattern 102 may be a laminated structure of titanium aluminum titanium (Ti/Al/Ti) ,
  • Ti/Al/Ti titanium aluminum titanium
  • the thickness is controlled at 60 to 200 nanometers, and it can also be a single layer structure made of copper, and the thickness is controlled at about 80 to 150 nanometers, but it is not limited to this.
  • the organic layer 103 may be PI (polyimide), and the thickness of the organic layer 103 is about 6-20 microns, more specifically, about 6-10 microns.
  • the organic layer 103 is provided with a via 105, and the area of the via 105 corresponds to the area where the first conductive pattern 102 is located. In this way, the first conductive pattern 102 is exposed by the via 105, and the second conductive layer 104 passes through the via 105 It is electrically connected to the first conductive pattern 102, and further, the second conductive layer 104 may be electrically connected to other structures of the display substrate, thereby realizing electrical connection between the binding structure electrically connected to the first conductive pattern 102 and the display substrate.
  • PI polyimide
  • the second conductive layer 104 can be selected from metal materials such as aluminum and copper or composite materials of metal materials, but is not limited to this, and has a thickness of about 60 to 200 nanometers.
  • the second conductive layer 104 is in electrical contact with the first conductive pattern 102, and Layered routing.
  • the second conductive layer 104 can be prevented from contacting the external environment, which helps to reduce the possibility of the second conductive layer 104 failing due to factors such as corrosion.
  • the display substrate further includes a filling structure 106 that fills the via 105.
  • the distance between the surface of the filling structure 106 on the side away from the base substrate 101 and the base substrate 101 and the side of the organic layer 103 away from the base substrate 101 The distance difference between the surface of the base substrate 101 and the base substrate 101 is less than a preset threshold.
  • the filling structure 106 can be made of the same material as the organic layer 103.
  • the distance between the surface of the filling structure 106 on the side away from the base substrate 101 and the base substrate 101 and the surface of the organic layer 103 on the side away from the base substrate 101 are connected with each other.
  • the distance difference between the base substrate 101 is less than the preset threshold value means that when the filling structure 106 is fabricated, the distance between the side surface of the filling structure 106 away from the base substrate 101 and the base substrate 101 is the same as the organic
  • the distance of the layer 103 away from the surface of the base substrate 101 is relatively small.
  • the preset threshold is not greater than 10% of the thickness of the organic layer 103.
  • the preset threshold is not greater than 600 nanometers.
  • the filling structure 106 if the filling structure 106 is not made, the shape of the part of the film layer located on the side of the via hole 105 away from the base substrate 101 matches the shape of the via hole 105, that is, the film layer There is a height difference equivalent to the depth of the via hole 105 in the area where the via hole 105 is located and the area outside the via hole 105.
  • a part of the film layer located on the side of the via hole 105 away from the base substrate 101 can be directly disposed on the filling structure, so that the whole film layer is in a relatively flat state.
  • the display substrate and the manufacturing method thereof, the display device, and the display panel of the embodiment of the present disclosure are provided with a filling structure 106 for filling the via 105 in the via 105 of the binding area A, so that the filling can pass through the filling structure 106.
  • the structure 106 realizes sharing the pressure generated during the bonding process, reducing the possibility of stress concentration at the via hole 105, thereby reducing the possibility of damage to the display substrate.
  • the display substrate may also include other film structures, for example, it may also include a sacrificial layer (DBL, De-Bonding-Layer) 107, a protective layer, etc., obviously, these film structures are not necessary Yes, you can choose to add other structural layers according to the actual situation.
  • DBL sacrificial layer
  • a protective layer etc.
  • the sacrificial layer 107 is located between the first conductive pattern 102 and the base substrate 101, and its material can be selected from PI-like (polyimide-like) materials with a thickness of about 50 to 150 nanometers. It is used to separate the first conductive pattern 102 from the base substrate 101 so as to bind the binding structure to the display substrate and make electrical contact with the first conductive pattern 102.
  • the protective layer includes a first protective layer 108A and a second protective layer 108B.
  • the first protective layer 108A is located on the side of the first conductive pattern 102 away from the base substrate 101.
  • the thickness of silicon oxide is greater than that of the first conductive pattern 102, specifically, about 100 to 400 nanometers, to protect the first conductive pattern 102, and increase the first conductive pattern 102 and the organic layer 103 at the same time. The adhesion between.
  • the second protective layer 108B is located between the organic layer 103 and the second conductive layer 104. It can be made of silicon nitride material with a thickness of about 10 to 200 nanometers. It is mainly used to prevent water and oxygen from penetrating into the organic layer 103. The second conductive layer 104 is corroded.
  • At least one embodiment of the present disclosure further includes a barrier layer 109.
  • the material of the barrier layer 109 can be SiNx or silicon oxide (SiOx), and its thickness is about 40 to 200 nanometers.
  • the barrier layer 109 is mainly used to reduce During the laser lift-off process, laser irradiation may adversely affect the structure of thin film transistors (TFT).
  • the position of the barrier layer 109 is not fixed.
  • the barrier layer 109 is located on the side of the organic layer 103 away from the base substrate 101, and the area corresponding to the barrier layer 109 and the via 105 is located between the filling structure 106 and the second conductive layer 104.
  • the barrier layer 109 is located on the side of the organic layer 103 away from the base substrate 101, and the area corresponding to the barrier layer 109 and the via 105 is located on the side of the filling structure 106 away from the base substrate 101 .
  • the filling structure 106 may be provided on the side of the barrier layer 109 away from the base substrate 101 to fill the via 105, or the barrier layer 109 may be formed after the filling structure 106 is provided to fill the via 105.
  • it further includes a buffer layer 110 on the side of the barrier layer 109 away from the base substrate 101, and the distance difference between different regions of the buffer layer 110 and the base substrate 101 is less than a preset threshold.
  • the buffer layer 110 is usually an inorganic layer formed of one or more of silicon nitride and silicon oxide, and has a thickness of about 250 nm to 400 nm.
  • the portion of the buffer layer 110 corresponding to the via hole 105 is located on the side of the filling structure 106 away from the base substrate 101, so the film layer does not include a recessed area adapted to the shape of the via hole 105 , But in a substantially flat state. In this way, the distance difference between different regions of the fabricated buffer layer 110 and the base substrate 101 is small, and the buffer layer 110 is in a relatively flat state.
  • it further includes one or more of the first gate insulating layer 111A, the second gate insulating layer 111B, and the dielectric layer 113 on the side of the barrier layer 109 away from the base substrate 101, and the first gate
  • the distance difference between the different areas of the insulating layer 111A and the base substrate 101 is less than the preset threshold
  • the distance difference between the different areas of the second gate insulating layer 111B and the base substrate 101 is less than the preset threshold
  • the difference in the dielectric layer 113 The distance difference between the region and the base substrate 101 is less than a preset threshold.
  • one or more of the first gate insulating layer 111A, the second gate insulating layer 111B, and the dielectric layer 113 are planarized on the side away from the base substrate 101 to form a flat surface. .
  • the first gate insulating layer 111A and the second gate insulating layer 111B can be made of insulating materials such as silicon nitride or silicon oxide, and the dielectric layer 113 is made of organic materials, with a thickness of about 30 to 150 nanometers.
  • the first gate insulating layer 111A is located on the side of the barrier layer 109 away from the base substrate 101.
  • the first gate insulating layer 111A needs to adapt to the structure of the via hole 105, so in the region corresponding to the via hole 105 It needs to adapt to the shape of the via hole 105 and climb the slope.
  • the distance between the first gate insulating layer 111A and the base substrate is small, and in the area outside the first gate insulating layer 111A , The distance between the first gate insulating layer 111A and the base substrate is relatively large, and the distance difference is about the depth of the via 105.
  • the filling structure 106 since the filling structure 106 is provided, the filling structure is also provided between the first gate insulating layer 111A and the base substrate 101 in the area corresponding to the via hole 105, so the first gate insulating layer The distance difference between the different areas of the layer 111A and the base substrate 101 will be significantly reduced.
  • the preset threshold is not greater than 600 nanometers, that is, the flatness of the first gate insulating layer 111A, the second gate insulating layer 111B, and the dielectric layer 113 is not greater than 600 nanometers. Further, in a specific embodiment, the preset threshold value is not greater than 200 nanometers, which can further improve the flatness of each film layer.
  • the filling structure 106 is provided, the structure of other subsequent film layers has also changed accordingly, and there is no need to adapt to the shape of the via 105 to climb the slope, so the structure is relatively flat, which can also be understood as these
  • the distance between different areas of the film layer and the base substrate 101 is relatively uniform, and the distance difference is relatively small.
  • the mask required for making the first gate insulating layer 111A, the second gate insulating layer 111B, and the dielectric layer 113 can be reduced. In this way, 4 patterning processes are saved, which helps to save costs and process flow. At the same time, since exposure, etching and other operations are not required, the possibility of photoresist (PR) and metal remaining in the region corresponding to the via 105 during the manufacturing process can also be reduced, thereby helping to improve the quality of the display substrate.
  • PR photoresist
  • the display substrate may also include, but is not limited to, for example, the active layer 116, the first gate layer 112A, the second gate layer 112B, and the second gate layer.
  • the third protection layer 108C and the fourth protection layer 108D are provided with a plurality of vent holes 118 penetrating the third protection layer 108 and the fourth protection layer 108D. It should be understood that the third protection layer 108C and the fourth protection layer 108D The layers 108D are dense inorganic layers. By providing the vent holes 118, the possibility of bubbling of these layers in the subsequent high-temperature process can be reduced.
  • a pixel unit is fabricated on the side of the fourth protective layer 108D and the third conductive layer 117 away from the base substrate, and the driving electrode of the pixel unit is electrically connected to the third conductive layer 117.
  • the driving electrode of the pixel unit is electrically connected to the third conductive layer 117.
  • the inorganic light-emitting diodes 119 need to be bound to the base substrate on which the driving circuit is prepared by means of transfer.
  • the P electrode and the N electrode of the inorganic light emitting diode 119 are electrically connected to the corresponding electrodes in the third conductive layer 117, respectively.
  • FIG. 2A is a simulation model of a display substrate in related technologies.
  • the simulation model is mainly used to simulate the mechanical properties of the display substrate.
  • 2A shows the organic layer 201A including through holes, and schematically shows the metal layer 202A disposed in the through holes of the organic layer 201A, and other film layers 203A located above the metal layer 202A.
  • 2C is a simulation model of a display substrate in at least one embodiment of the present disclosure, showing an organic layer 201B including through holes, and schematically showing a metal layer 202B disposed in the through holes of the organic layer 201B, and filling in Due to the existence of the through hole, the metal layer 202B corresponds to the filling structure 206 of the recess at the position of the through hole, and other film layers 203B located above the metal layer 202B and the filling structure 206.
  • the other structures 203A and 203B of the above-mentioned display substrate refer to the collection of the film layer structures on the side of the organic layer 103 away from the base substrate 101 in the display substrate shown in FIG. 1C and FIG. 1D.
  • the arrow in the figure represents the applied load at the lower boundary of the display substrate. In a simulation, the applied load is 0.3 megapascals (MPa).
  • the display substrate is fixed at the upper boundary shown in Figure 2A.
  • the binding indenter applies pressure from the direction of the lower boundary in the figure to realize the display substrate and binding.
  • the binding of the structure is simulated by the above load.
  • the unit in the figure is MPa.
  • the stress concentration at the via hole is significantly reduced.
  • the display panel described in at least one embodiment of the present disclosure may include the above-mentioned display substrate.
  • the display device described in at least one embodiment of the present disclosure may include the above-mentioned display panel.
  • the display device provided by at least one embodiment of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the embodiment of the present disclosure provides a method for manufacturing a display substrate, as shown in FIG. 3, including the following steps:
  • Step 301 Provide a base substrate.
  • a sacrificial layer 402 is first formed on a base substrate 401.
  • Step 302 Making a first conductive pattern on the base substrate.
  • a first conductive pattern 403 is formed on the sacrificial layer 402.
  • Step 303 forming an organic layer on the side of the first conductive pattern away from the base substrate.
  • Step 304 Opening a via hole on the organic layer.
  • a first protective layer 404 is formed on the first conductive pattern 403, and then an organic layer 405 is formed, and further, a via 406 is formed on the organic layer 405, and then a second protective layer 407 is formed.
  • Step 305 Fabricate a second conductive layer on the side of the organic layer away from the base substrate, and the second conductive layer is electrically connected to the first conductive pattern through the via hole.
  • a second conductive layer 408 is fabricated, and the second conductive layer 408 is in electrical contact with the first conductive pattern 403 through the via 406.
  • Step 306 Fabricate a filling structure to fill the via, the distance between the surface of the filling structure on the side away from the base substrate and the base substrate and the surface of the organic layer on the side away from the base substrate and The distance difference between the base substrates is smaller than a preset threshold.
  • step 301 to step 305 can refer to related technologies.
  • a filling structure 409 is made to fill the via hole.
  • the filling structure 409 can be filled into the via hole by coating or inkjet printing.
  • the material can be Select high-temperature resistant PI to adapt to some high-temperature processes in the production of display substrates and avoid damage during high-temperature processes.
  • this embodiment can manufacture the display substrate in the above-mentioned display substrate embodiment, it can at least achieve all the technical effects of the above-mentioned display substrate embodiment, which will not be repeated here.
  • the step of making the barrier layer 410 is further included. This step may be made before the above step 306 or after the above step 306.
  • step 306 the method further includes:
  • a barrier layer is formed on the side of the filling structure away from the base substrate.
  • step 306 the method further includes:
  • Step 306 specifically includes:
  • a filling structure is formed to fill the via hole.
  • the barrier layer 410 can be fabricated first, as shown in FIG. 4E, and then the filling structure 409 can be fabricated to fill the via; A barrier layer is made on one side of the substrate.
  • barrier layer may also include the production of some other structures, for example, including but not limited to the production of source and drain electrode layers, planarization layers, passivation layers, etc., as well as the transfer and bonding of LEDs.
  • the production process and materials of other film structures can refer to phase technology.
  • the transfer of LEDs can choose mass transfer or single transfer.
  • the bonding method of LED can choose different methods such as eutectic soldering or conductive glue.
  • these processes can refer to related technologies, and no further limitation and description are made here.

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  • Electroluminescent Light Sources (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种显示基板、其制作方法、显示装置和显示面板。显示基板包括衬底基板（101，401）、第一导电图案（102，403）、有机层（103，201A，201B，405）和第二导电层（104，408），显示基板具有像素区和绑定区（A），第一导电图案（102，403）位于显示基板的绑定区（A）；有机层（103，201A，201B，405）上开设有沿垂直于衬底基板（101，401）的方向贯穿有机层（103，201A，201B，405）的过孔（105，406），过孔（105，406）的位置与第一导电图案（102，403）的位置相对应，且第二导电层（104，408）通过过孔（105，406）与第一导电图案（102，403）电连接；显示基板还包括填充过孔（105，406）的填充结构（106，206，409），填充结构（106，206，409）远离衬底基板（101，401）一侧的表面与衬底基板（101，401）之间距离和有机层（103，201A，201B，405）远离衬底基板（101，401）一侧的表面与衬底基板（101，401）之间距离的距离差小于预设阈值。能够降低过孔（105，406）处应力集中的可能性，从而降低显示基板损坏的可能性。

Description

显示基板、其制作方法、显示装置和显示面板 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其制作方法、显示装置和显示面板。
背景技术
随着Micro-LED(微型发光二极管)技术的成熟，Micro-LED的使用也越来越普遍。一种相关技术中的Micro-LED显示基板包括像素区和绑定区，并在绑定区与绑定电路(bonding IC)绑定(bonding)以实现电连接，然而在绑定过程中，可能出现应力集中，导致显示基板损坏的可能性增加。
发明内容
在一个方面中，本公开实施例提供了一种显示基板，包括衬底基板、位于所述衬底基板上的第一导电图案、位于所述第一导电图案远离所述衬底基板一侧的有机层和位于所述有机层远离所述衬底基板一侧的第二导电层，所述显示基板具有像素区和绑定区，所述第一导电图案位于所述显示基板的绑定区；
所述有机层上开设有沿垂直于所述衬底基板的方向贯穿所述有机层的过孔，所述过孔的位置与所述第一导电图案的位置相对应，且所述第二导电层通过所述过孔与所述第一导电图案电连接；
所述显示基板还包括填充所述过孔的填充结构，所述填充结构远离所述衬底基板一侧的表面与所述衬底基板之间距离和所述有机层远离衬底基板一侧的表面与所述衬底基板之间距离的距离差小于预设阈值。
可选的，还包括阻挡层，所述阻挡层位于所述有机层远离所述衬底基板的一侧，所述阻挡层与所述过孔对应的区域位于所述填充结构和所述第二导电层之间。
可选的，还包括阻挡层，所述阻挡层位于所述有机层远离所述衬底基板 的一侧，所述阻挡层与所述过孔对应的区域位于所述填充结构远离所述衬底基板的一侧。
可选的，还包括位于所述阻挡层远离所述衬底基板一侧的缓冲层，所述缓冲层的不同区域与所述衬底基板之间距离差小于所述预设阈值。
可选的，还包括位于所述缓冲层远离所述衬底基板一侧的第一栅极绝缘层、第二栅极绝缘层、介电层中的一项或多项，所述第一栅极绝缘层的不同区域与所述衬底基板之间距离差小于所述预设阈值，所述第二栅极绝缘层的不同区域与所述衬底基板之间距离差小于所述预设阈值，所述介电层的不同区域与所述衬底基板之间距离差小于所述预设阈值。
在第二个方面中，本公开实施例提供了一种显示面板，包括以上任一项所述的显示基板。
在第三个方面中，本公开实施例提供了一种显示装置，包括以上所述的显示面板。
在第四个方面中，本公开实施例提供了一种显示基板的制作方法，包括以下步骤：
提供一衬底基板；
在所述衬底基板上制作第一导电图案；
在所述第一导电图案远离所述衬底基板的一侧制作有机层；
在所述有机层上开设过孔；
在所述有机层远离所述衬底基板的一侧制作第二导电层，所述第二导电层通过所述过孔与所述第一导电图案电连接；
制作填充结构以填充所述过孔，所述填充结构远离所述衬底基板一侧的表面与所述衬底基板之间距离和所述有机层远离衬底基板一侧的表面与所述衬底基板之间距离的距离差小于预设阈值。
可选的，所述制作填充结构以填充所述过孔之后，还包括：
在所述填充结构远离所述衬底基板的一侧制作阻挡层，所述阻挡层与所述衬底基板之间的距离均匀。
可选的，所述制作填充结构以填充所述过孔之前，还包括：
在所述有机层远离所述衬底基板的一侧制作阻挡层；
所述制作填充结构以填充所述过孔，包括：
在所述阻挡层远离所述衬底基板一侧，制作填充结构以填充所述过孔。
与相关技术相比，本公开实施例所述的显示基板及其制作方法、显示装置和显示面板通过在绑定区的过孔中设置填充过孔的填充结构，这样，能够通过该填充结构实现分担绑定过程中产生的压力，降低过孔处应力集中的可能性，从而降低显示基板损坏的可能性。
附图说明
图1A是本公开至少一实施例中显示基板的一结构示意图；
图1B是本公开至少一实施例中显示基板的又一结构示意图；
图1C是本公开至少一实施例中显示基板的又一结构示意图；
图1D是本公开至少一实施例中显示基板的又一结构示意图；
图2A是相关技术中显示基板的仿真模型；
图2B是相关技术中显示基板的应力仿真结果；
图2C是本公开至少一实施例中显示基板的仿真模型；
图2D是本公开至少一实施例中显示基板的应力仿真结果；
图3是本公开至少一实施例中显示基板的制作方法的流程图；
图4A是本公开至少一实施例中显示基板一中间制程示意图；
图4B是本公开至少一实施例中显示基板又一中间制程示意图；
图4C是本公开至少一实施例中显示基板又一中间制程示意图；
图4D是本公开至少一实施例中显示基板又一中间制程示意图；
图4E是本公开至少一实施例中显示基板又一中间制程示意图；
图4F是本公开至少一实施例中显示基板又一中间制程示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开至少一实施例提供了一种显示基板。
如图1A和图1B所示，该显示基板包括衬底基板101、位于衬底基板101上的第一导电图案102、位于第一导电图案102远离衬底基板101一侧的有机层103和位于有机层103远离衬底基板101一侧的第二导电层104。
其中，显示基板具有像素区和绑定区，像素区包括多个像素以及用于向多个像素提供电信号的驱动线路，绑定区包括与驱动线路相连接的绑定结构(例如绑定端子)，用于绑定(bonding)COF(Chip On Flex，覆晶薄膜)或IC(Integrated Circuit，集成电路)等外部驱动电路。
第一导电图案102位于图1A所示的绑定区A。
如图1A所示，衬底基板101的材质为刚性材料，例如可以为玻璃，显示基板在制作完成之后需要从该衬底基板101上剥离。有机层103上开设有沿垂直于衬底基板101的方向贯穿有机层103的过孔105，过孔105的位置与第一导电图案102的位置相对应，且第二导电层104通过过孔105与第一导电图案102电连接。
第一导电图案102为绑定结构的一部分，用于实现外部驱动电路与显示基板上驱动线路的电连接，第一导电图案102的可以为钛铝钛(Ti/Al/Ti)的叠层结构，其厚度控制在60至200纳米，也可以为铜做的单层结构，其厚度控制在约80至150纳米，但不以此为限。
有机层103可以选用PI(聚酰亚胺)，有机层103的厚度约为6至20微米，更为具体的，约为6至10微米。有机层103上开设有过孔105，过孔105的区域与第一导电图案102所在的区域对应，这样，第一导电图案102由过孔105暴露出来，第二导电层104通过该过孔105与第一导电图案102电连接，进一步的，第二导电层104可以与显示基板的其他结构电连接，从而实现使得与第一导电图案102电连接的绑定结构与显示基板的电连接。
第二导电层104可以选择铝、铜等金属材料或金属材料的复合材料，但不局限于此，其厚度约为60至200纳米，第二导电层104与第一导电图案102电接触，且分层走线。
如图1D所示，降显示基板中的衬底基板101剥离之后，第一导电图案102靠近衬底基板101的一侧表面暴露出来，第二导电层104被第一导电图 案102所遮挡，这样，可以避免第二导电层104与外部环境接触，有助于降低第二导电层104由于腐蚀等因素失效的可能性。
如图1B所示，显示基板还包括填充过孔105的填充结构106，填充结构106远离衬底基板101一侧的表面与衬底基板101之间距离和有机层103远离衬底基板101一侧的表面与衬底基板101之间距离的距离差小于预设阈值。
填充结构106可以选择与有机层103相同的材料制作而成，填充结构106远离衬底基板101一侧的表面与衬底基板101之间距离和有机层103远离衬底基板101一侧的表面与衬底基板101之间距离的距离差小于预设阈值指的是，当制作有填充结构106的时候，填充结构106远离衬底基板101的一侧表面和衬底基板101之间的距离和有机层103远离衬底基板101一侧表面的距离两者的距离差相对较小。
在一个可选的具体实施方式中，该预设阈值不大于有机层103厚度的10％，例如，有机层103的厚度为6微米，则该预设阈值不大于600纳米，显然，实际实施时，该预设阈值越小，则后续制作的膜层的平坦度也就越高，有助于进一步提高显示面板的可靠性。
应当理解的是，如果未制作该填充结构106，位于过孔105远离衬底基板101一侧的部分膜层的形状与该过孔105过孔105的形状相匹配，也就是说，这些膜层在过孔105所在的区域和过孔105之外的区域存在与过孔深度尺寸相当的高度差。通过制作填充结构106，位于过孔105远离衬底基板101一侧的部分膜层可以直接设置在填充结构上，使得膜层整体处于相对平坦的状态。
与相关技术相比，本公开实施例的显示基板及其制作方法、显示装置和显示面板通过在绑定区A的过孔105中设置填充过孔105的填充结构106，这样，能够通过该填充结构106实现分担绑定过程中产生的压力，降低过孔105处应力集中的可能性，从而降低显示基板损坏的可能性。
如图1A和图1B所示，显示基板还可以包括其他一些膜层结构，例如，还可能包括牺牲层(DBL,De-Bonding-Layer)107、保护层等，显然，这些膜层结构并非必须的，可以根据实际情况选择增加其他结构膜层。
在本公开的至少一实施例中，牺牲层107位于第一导电图案102和衬底 基板101之间，其材料可以选择类PI(类聚酰亚胺)材料，厚度约为50至150纳米，其用于使第一导电图案102与衬底基板101相分离，以便将绑定结构与显示基板相绑定且与第一导电图案102电接触。
在本公开至少一实施例中，保护层包括第一保护层108A和第二保护层108B，其中，第一保护层108A位于第一导电图案102远离衬底基板101的一侧，可以选择利用二硅的氧化物制作，一般来说，其厚度大于第一导电图案102的厚度，具体的，约为100至400纳米，以保护第一导电图案102，同时增加第一导电图案102与有机层103之间的附着力。
第二保护层108B位于有机层103和第二导电层104之间，其可以选择利用硅的氮化物材料制作，其厚度约为10至200纳米，主要用于防止水氧等渗入有机层103而腐蚀第二导电层104。
进一步的，本公开的至少一个实施例中还包括阻挡层109，阻挡层109的材料可以选择SiNx或硅的氧化物(SiOx)，其厚度约为40至200纳米，阻挡层109主要用于降低激光剥离过程中激光照射可能对薄膜晶体管(TFT)结构造成的不利影响。
阻挡层109的位置并不是固定的。
可选的，在一个具体实施方式中，阻挡层109位于有机层103远离衬底基板101的一侧，阻挡层109与过孔105对应的区域位于填充结构106和第二导电层104之间。
可选的，在另一个具体实施方式中，阻挡层109位于有机层103远离衬底基板101的一侧，阻挡层109与过孔105对应的区域位于填充结构106远离衬底基板101的一侧。
也就是说，可以在阻挡层109远离衬底基板101的一侧设置填充结构106以填充过孔105，也可以在设置填充结构106填充过孔105之后再制作阻挡层109。
可选的，还包括位于阻挡层109远离衬底基板101一侧的缓冲层110，缓冲层110的不同区域与衬底基板101之间距离差小于预设阈值。
缓冲层110通常为由硅的氮化物、硅的氧化物中的一种或多种材料形成的无机层，厚度在250nm至400nm左右。
可以理解的是，通过设置填充结构106，缓冲层110与过孔105对应的部分位于填充结构106远离衬底基板101的一侧，所以其膜层不包括与过孔105形状适配的凹陷区域，而是处于基本平坦状态，这样，所制作出来的缓冲层110的不同区域与衬底基板101之间的距离差较小，缓冲层110处于相对平坦的状态。
可选的，还包括位于阻挡层109远离衬底基板101一侧的第一栅极绝缘层111A、第二栅极绝缘层111B、介电层113中的一项或多项，第一栅极绝缘层111A的不同区域与衬底基板101之间距离差小于预设阈值，第二栅极绝缘层111B的不同区域与衬底基板101之间距离差小于预设阈值，介电层113的不同区域与衬底基板101之间距离差小于预设阈值。
换句话说，也就是上述第一栅极绝缘层111A、第二栅极绝缘层111B、介电层113中的一项或多项远离衬底基板101的一侧经平坦化处理形成平坦的表面。
本实施例中，第一栅极绝缘层111A、第二栅极绝缘层111B可以由硅的氮化物或硅的氧化物等绝缘材料制作，而介电层113则选择有机材料，其厚度约为30至150纳米。
具体的，第一栅极绝缘层111A位于于阻挡层109远离衬底基板101一侧，相关技术中，第一栅极绝缘层111A需要适应过孔105的结构，所以在过孔105对应的区域需要适应过孔105的形状而爬坡，在过孔105对应的区域，第一栅极绝缘层111A与衬底基板之间的距离较小，而在第一栅极绝缘层111A之外的区域，第一栅极绝缘层111A与衬底基板之间的距离较大，该距离差约为过孔105的深度。
而本公开实施例的技术方案中，由于设置了填充结构106，在过孔105对应的区域，第一栅极绝缘层111A和衬底基板101之间还具有填充结构，所以第一栅极绝缘层111A的不同区域与衬底基板101之间距离差将显著减小。
具体而言，该预设阈值不大于600纳米，也就是说，第一栅极绝缘层111A、第二栅极绝缘层111B、介电层113的平坦度不大于600纳米。进一步的，在一个具体实施方式中，该预设阈值不大于200纳米，能进一步提高各膜层的平坦度。
与缓冲层110的结构类似，由于设置了填充结构106，后续其他膜层的结构也随之发生了变化，不需要适应过孔105的形状而爬坡，所以结构相对平坦，也可以理解为这些膜层的不同区域与衬底基板101之间的距离相对均匀，其距离差较小。
同时，由于这些膜层形状是相对平坦的，不需要制作与过孔105的形状相适配的结构，因此，在制作这些膜层时，只需要进行材料的沉积，而不需要采用mask工艺(掩膜版曝光)对过孔105对应的区域进行曝光，从而可以减少mask(掩膜版)的使用。
例如，可以减少制作第一栅极绝缘层111A、第二栅极绝缘层111B和介电层113所需的mask，这样，就节约了4次构图工艺，有助于节约成本并节约工艺流程，同时，由于不需要采用曝光、刻蚀等操作，也能够降低光刻胶(PR)和制作过程中金属在过孔105对应的区域残留的可能性，从而有助于提高显示基板的品质。
进一步的，如图1C和图1D所示，如显示基板包括薄膜晶体管，则显示基板中还可以包括但不限于例如有源层116、第一栅极层112A、第二栅极层112B、第一源漏电极115A、第二源漏电极115B、第一平坦层114A、第二平坦层114B、第三保护层108C、第四保护层108D和第三导电层117等膜层。
第三保护层108C和第四保护层108D上开设有多个贯穿该第三保护层108和第四保护层108D的排气孔118，应当理解的是，该第三保护层108C和第四保护层108D均为致密的无机层，通过设置该排气孔118，能够降低后续高温工艺中，这些膜层鼓泡的可能性。
进一步的，在第四保护层108D以及第三导电层117远离衬底基板一侧制作像素单元，像素单元的驱动电极与第三导电层117电连接。如图1D所示，当显示基板中的像素为无机发光二极管119时，需要将无机发光二极管119通过转移的方式绑定在制备有驱动线路的衬底基板上。且无机发光二极管119的P电极、N电极分别与第三导电层117中相对应的电极电连接。
请参阅图2A至图2D，图2A为相关技术中显示基板的仿真模型，仿真模型主要用于对显示基板的力学性能进行仿真模拟。其中，图2A中示出了包括通孔的有机层201A，并示意性的示出了设置在有机层201A通孔中的金 属层202A，以及位于金属层202A上方的其他膜层203A。图2C是本公开至少一实施例中显示基板的仿真模型，示出了包括通孔的有机层201B，并示意性的示出了设置在有机层201B通孔中的金属层202B，以及填充在由于通孔的存在而使得金属层202B对应通孔位置处出现的凹陷部的填充结构206，以及位于金属层202B和填充结构206上方的其他膜层203B。上述显示基板的其他结构203A、203B指代图1C和图1D所示显示基板中，位于有机层103远离衬底基板101一侧的各膜层结构的集合。
在图2A和图2C所示的仿真模型中，显示基板的上边界的边界条件设置为U1＝0，U2＝0，R12＝0，也就是说，显示基板的上边界的横向、纵向位移均为0，旋转为0，图中箭头代表在显示基板的下边界设定为施加的荷载，在一次仿真模拟中，施加荷载为0.3兆帕(MPa)。
实际绑定过程中，显示基板在图2A中所示的上方边界是固定的，通过上边界的边界条件模拟，绑定压头由图中下边界的方向施加压力，以实现显示基板与绑定结构的绑定，通过上述荷载模拟。
如图2B和图2D所示，图中的单位为MPa，图2B所示相关技术的显示基板的仿真结果中，可见过孔处出现了较大的应力集中，图2D所示的本公开一实施例的显示基板的仿真结果中，过孔处的应力集中显著减小。
本公开至少一实施例所述的显示面板可以包括上述的显示基板。
本公开至少一实施例所述的显示装置可以包括上述的显示面板。
本公开至少一实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开实施例提供了一种显示基板的制作方法，如图3所示，包括以下步骤：
步骤301：提供一衬底基板。
如图4A所示，在本公开的至少一具体实施方式中，首先在衬底基板401上制作牺牲层402。
步骤302：在所述衬底基板上制作第一导电图案。
如图4B所示，进一步的，在牺牲层402上制作第一导电图案403。
步骤303：在所述第一导电图案远离所述衬底基板的一侧制作有机层。
步骤304：在所述有机层上开设过孔。
如图4C所示，首先，在第一导电图案403上制作第一保护层404，然后制作有机层405，进一步的，在有机层405上开设过孔406，然后制作第二保护层407。
步骤305：在所述有机层远离所述衬底基板的一侧制作第二导电层，所述第二导电层通过所述过孔与所述第一导电图案电连接。
如图4D所指示，接下来，制作第二导电层408，第二导电层408通过过孔406与第一导电图案403电接触。
步骤306：制作填充结构以填充所述过孔，所述填充结构远离所述衬底基板一侧的表面与所述衬底基板之间距离和所述有机层远离衬底基板一侧的表面与所述衬底基板之间距离的距离差小于预设阈值。
本实施例中上述步骤301至步骤305的过程均可参考相关技术。
如图4E所示，当完成第二导电层408的制作之后，制作填充结构409以填充过孔，其具体可以通过涂覆(coating)或者喷墨打印等方式填充到过孔内，其材料可以选择耐高温PI，从而适应显示基板制作中的部分高温工艺，避免在高温工艺中损坏。
由于本实施例能够制作上述显示基板实施例中的显示基板，因此至少能实现上述显示基板实施例的全部技术效果，此处不再赘述。
在本公开的至少一实施例中，还包括制作阻挡层410的步骤，该步骤可以在上述步骤306之前制作，也可以在上述步骤306之后制作。
可选的，在一个具体实施方式中，在步骤306之后，还包括：
在所述填充结构远离所述衬底基板的一侧制作阻挡层。
可选的，在另一个具体实施方式中，在步骤306之前，还包括：
在所述有机层远离所述衬底基板的一侧制作阻挡层；
步骤306具体包括：
在所述阻挡层远离所述衬底基板一侧，制作填充结构以填充所述过孔。
也就是说，如图4F所示，可以先制作阻挡层410，如图4E所示，然后制作填充结构409填充该过孔；也可以先制作填充结构填充过孔，然后在填充结构远离衬底基板的一侧制作阻挡层。
进一步的，在阻挡层制作完成之后，还可能包括一些其他结构的制作，例如包括但不限于源漏电极层、平坦层、钝化层等的制作，以及LED的转移绑定等。
其中，其他膜层结构的制作工艺及材料等均可参考相技术，LED的转移可以选择巨量转移，也可以选择单颗转移，LED的绑定方式可以选择共晶焊或导电胶等不同的绑定方式，这些过程均可参考相关技术，此处不做进一步限定和描述。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (10)

  1. 一种显示基板，包括衬底基板、位于所述衬底基板上的第一导电图案、位于所述第一导电图案远离所述衬底基板一侧的有机层和位于所述有机层远离所述衬底基板一侧的第二导电层，所述显示基板具有像素区和绑定区，所述第一导电图案位于所述显示基板的绑定区；
    所述有机层上开设有沿垂直于所述衬底基板的方向贯穿所述有机层的过孔，所述过孔的位置与所述第一导电图案的位置相对应，且所述第二导电层通过所述过孔与所述第一导电图案电连接；
    所述显示基板还包括填充所述过孔的填充结构，所述填充结构远离所述衬底基板一侧的表面与所述衬底基板之间距离和所述有机层远离衬底基板一侧的表面与所述衬底基板之间距离的距离差小于预设阈值。
  2. 如权利要求1所述的显示基板，其中，还包括阻挡层，所述阻挡层位于所述有机层远离所述衬底基板的一侧，所述阻挡层与所述过孔对应的区域位于所述填充结构和所述第二导电层之间。
  3. 如权利要求1所述的显示基板，其中，还包括阻挡层，所述阻挡层位于所述有机层远离所述衬底基板的一侧，所述阻挡层与所述过孔对应的区域位于所述填充结构远离所述衬底基板的一侧。
  4. 如权利要求3所述的显示基板，其中，还包括位于所述阻挡层远离所述衬底基板一侧的缓冲层，所述缓冲层的不同区域与所述衬底基板之间距离差小于所述预设阈值。
  5. 如权利要求4所述的显示基板，其中，还包括位于所述缓冲层远离所述衬底基板一侧的第一栅极绝缘层、第二栅极绝缘层、介电层中的一项或多项，所述第一栅极绝缘层的不同区域与所述衬底基板之间距离差小于所述预设阈值，所述第二栅极绝缘层的不同区域与所述衬底基板之间距离差小于所述预设阈值，所述介电层的不同区域与所述衬底基板之间距离差小于所述预设阈值。
  6. 一种显示面板，包括权利要求1至5中任一权利要求所述的显示基板。
  7. 一种显示装置，包括权利要求6所述的显示面板。
  8. 一种显示基板的制作方法，包括以下步骤：
    提供一衬底基板；
    在所述衬底基板上制作第一导电图案；
    在所述第一导电图案远离所述衬底基板的一侧制作有机层；
    在所述有机层上开设过孔；
    在所述有机层远离所述衬底基板的一侧制作第二导电层，所述第二导电层通过所述过孔与所述第一导电图案电连接；
    制作填充结构以填充所述过孔，所述填充结构远离所述衬底基板一侧的表面与所述衬底基板之间距离和所述有机层远离衬底基板一侧的表面与所述衬底基板之间距离的距离差小于预设阈值。
  9. 如权利要求8所述的显示基板的制作方法，其中，所述制作填充结构以填充所述过孔之后，还包括：
    在所述填充结构远离所述衬底基板的一侧制作阻挡层。
  10. 如权利要求8所述的显示基板的制作方法，其中，所述制作填充结构以填充所述过孔之前，还包括：
    在所述有机层远离所述衬底基板的一侧制作阻挡层；
    所述制作填充结构以填充所述过孔，包括：
    在所述阻挡层远离所述衬底基板一侧，制作填充结构以填充所述过孔。
PCT/CN2020/088695 2020-05-06 2020-05-06 显示基板、其制作方法、显示装置和显示面板 Ceased WO2021223086A1 (zh)

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