WO2021226817A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2021226817A1
WO2021226817A1 PCT/CN2020/089723 CN2020089723W WO2021226817A1 WO 2021226817 A1 WO2021226817 A1 WO 2021226817A1 CN 2020089723 W CN2020089723 W CN 2020089723W WO 2021226817 A1 WO2021226817 A1 WO 2021226817A1
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WIPO (PCT)
Prior art keywords
sub
light
layer
display
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/089723
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English (en)
French (fr)
Inventor
王博
李付强
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US17/284,815 priority Critical patent/US12127457B2/en
Priority to CN202080000710.8A priority patent/CN114127947B/zh
Priority to PCT/CN2020/089723 priority patent/WO2021226817A1/zh
Priority to EP20900709.5A priority patent/EP4152400B1/en
Publication of WO2021226817A1 publication Critical patent/WO2021226817A1/zh
Anticipated expiration legal-status Critical
Priority to US18/783,678 priority patent/US12568745B2/en
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate and a display device.
  • the screen-to-body ratio that is, the ratio of the display area to the front of the entire display device, is an important design parameter.
  • the device needs to be set toward the front of the display device, such as setting the lens of the front camera unit To face the front of the display device, the sensing surface of the sensor is set to face the front of the display device, etc., so that the device can collect information in the environment to perform corresponding operations, such as collecting people or people on the front of the display device.
  • a display substrate having a display area and a peripheral area surrounding the display area, the display area including a first display area.
  • the display substrate includes: a base substrate, a first light shielding layer, a plurality of first sub-pixels, and a first power line.
  • the first light-shielding layer is disposed on one side of the base substrate, the first light-shielding layer is located in the first display area, and the first light-shielding layer has a plurality of openings arranged in an array.
  • a plurality of first sub-pixels are arranged on a side of the first light shielding layer away from the base substrate, the plurality of first sub-pixels are located in the first display area, and the plurality of first sub-pixels are located in the The orthographic projection of the base substrate and the orthographic projection of the opening on the base substrate do not overlap.
  • the first power line includes a first power bus and a plurality of first power sub-lines; at least a part of the first power bus is located in an area near the first display area in the peripheral area; the plurality of first power lines A power sub-line is located in the first display area and is electrically connected to the first power bus, and the plurality of first power sub-lines are configured to provide a first power signal to the plurality of first sub-pixels,
  • the orthographic projection of the plurality of first power sub-lines on the base substrate and the orthographic projection of the opening on the base substrate do not overlap.
  • the first light shielding layer is electrically connected to the first power line.
  • the display substrate further includes: at least one insulating film disposed between the first power line and the first light-shielding layer, and the at least one insulating film is provided with a penetrating through the at least one insulating film. Multiple vias of layer insulating film.
  • the first power line is electrically connected to the first light shielding layer through the plurality of via holes.
  • the first light shielding layer is also located in the peripheral area, the plurality of vias includes a plurality of first vias located in the peripheral area, and the first light shielding layer passes through the plurality of vias.
  • the first via is electrically connected to the first power bus.
  • the plurality of first via holes includes at least two kinds of first via holes having different hole depths.
  • the plurality of first vias includes at least one first via group, and each first via group includes at least one first via row; each first via row in each first via row The depth of a via hole is different.
  • the number of the first via group is multiple; the number of the first via row included in each first via group is multiple.
  • the plurality of first via hole groups are arranged along a first direction; the plurality of first via hole rows in each of the first via hole groups are arranged along the first direction, and each of the first via hole rows The first via holes with the same middle hole depth are arranged in a row along the first direction.
  • the plurality of via holes further includes a plurality of second via holes located in the first display area, and the first light shielding layer passes through the plurality of second via holes and the plurality of second via holes.
  • a power sub-line is electrically connected.
  • the plurality of second via holes are evenly distributed in the first display area.
  • a pixel is provided at a position between every four openings of the first light-shielding layer, the one pixel includes three of the first sub-pixels, and the position of one pixel corresponds to at least one The second via.
  • the display substrate further includes: a first insulating layer located between the first light shielding layer and the plurality of sub-pixels. At least one first sub-pixel of the plurality of first sub-pixels includes a thin film transistor and a storage capacitor.
  • the thin film transistor includes: an active layer located on the first insulating layer; a first gate insulating layer located on the side of the active layer away from the base substrate; The gate on the side of the base substrate; the second gate insulating layer on the side of the gate away from the base substrate; the interlayer insulation on the side of the second gate insulating layer away from the base substrate A layer and a source electrode and a drain electrode located on a side of the interlayer insulating layer away from the base substrate.
  • the storage capacitor includes a first electrode plate and a second electrode plate, the first electrode plate and the gate electrode are located in the same layer, and the second electrode plate is located on the second gate insulating layer and the interlayer insulation Between layers.
  • the at least one insulating film includes at least one of the first insulating layer, the first gate insulating layer, the second gate insulating layer, and the interlayer insulating layer.
  • the first power bus includes a first sublayer and a second sublayer, and the first sublayer and the second sublayer are electrically connected through a third via.
  • At least one of the plurality of first power sub-lines includes a third sub-layer and a fourth sub-layer, and the third sub-layer and the fourth sub-layer pass through the Four vias are electrically connected.
  • the display area further includes a second display area; the second display area is located on a side of the first display area away from the first power line.
  • the display substrate further includes: a plurality of second sub-pixels and a second power line. A plurality of second sub-pixels are located in the second display area.
  • the second power line includes a second power bus and a plurality of second power sub-lines; at least a part of the second power bus is located in an area near the second display area in the peripheral area, and the plurality of The second power sub-line is located in the second display area and is electrically connected to the second power bus, and the plurality of second power sub-lines are configured to provide a second power signal to the plurality of second sub-pixels .
  • the first power signal is the same as the second power signal, or the first power signal is different from the second power signal.
  • the first power signal when the first power signal is different from the second power signal, the first power signal is smaller than the second power signal.
  • the distribution density of the plurality of second sub-pixels is greater than the distribution density of the plurality of first sub-pixels.
  • the display substrate further includes a second light-shielding layer disposed on one side of the base substrate, the second light-shielding layer is located in the second display area, and the second light-shielding layer is connected to the first light-shielding layer.
  • a light-shielding layer is located on the same layer. The second light shielding layer is electrically connected to the second power line.
  • a display device in another aspect, includes: the display substrate as described above, and a front optical component disposed on the side of the display substrate away from the display surface of the display substrate. The orthographic projection of the front optical component on the display substrate is located in the first display area.
  • the front optical component includes: an infrared detection unit.
  • Figure 1 is a structural diagram of two display devices provided according to related technologies
  • FIG. 2 is a structural diagram of a display substrate provided according to some embodiments of the present disclosure.
  • 3A is a cross-sectional view obtained according to the cross-sectional line CC' in the display substrate provided in FIG. 2;
  • 3B is a cross-sectional view obtained according to the cross-sectional line DD' in the display substrate provided in FIG. 2;
  • FIG. 4 is a wiring diagram of a display substrate provided according to some embodiments of the present disclosure.
  • 5A to 5G are the film layer diagrams of the region G in the display substrate provided in FIG. 2;
  • FIG. 5H is a film layer diagram of a sub-pixel according to the film layer diagram shown in FIG. 5G;
  • FIG. 6A is a structural diagram of a display device provided according to some embodiments of the present disclosure.
  • FIG. 6B is another structural diagram of a display device provided according to some embodiments of the present disclosure.
  • FIG. 7 is a working schematic diagram of a display device provided according to some embodiments of the present disclosure.
  • FIG. 8 is a circuit diagram of a pixel driving circuit in a display substrate provided according to some embodiments of the present disclosure.
  • FIG. 9A is another cross-sectional view of a display substrate provided according to some embodiments of the present disclosure.
  • FIG. 9B is still another cross-sectional view of a display substrate provided according to some embodiments of the present disclosure.
  • FIG. 10 is a cross-sectional view of a plurality of via holes in a display substrate provided according to some embodiments of the present disclosure.
  • FIG. 11A is another cross-sectional view of a plurality of via holes in a display substrate according to some embodiments of the present disclosure.
  • FIG. 11B is still another cross-sectional view of a plurality of via holes in a display substrate provided according to some embodiments of the present disclosure.
  • 11C is still another cross-sectional view of a plurality of via holes in a display substrate provided according to some embodiments of the present disclosure.
  • FIG. 12 is a schematic diagram of a sub-pixel arrangement according to some embodiments of the present disclosure.
  • FIG. 13 is a schematic diagram of a sub-pixel opening arrangement according to some embodiments of the present disclosure.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the terms “connected” and “series connection” may be used to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • a and/or B includes the following three combinations: A only, B only, and the combination of A and B.
  • the front side of the mobile phone (that is, the side where the image is displayed) includes: a display area 01 and a non-display area located at the periphery of the display area 01 02, a part of the non-display area 02 is provided with a device 02a (for example, one or more of the front camera unit, light sensor, distance sensor, and biosensor), but the device 02a is not provided in the remaining part of the area , These areas cannot be displayed, resulting in a low screen occupancy.
  • a device 02a for example, one or more of the front camera unit, light sensor, distance sensor, and biosensor
  • the special-shaped cutting technology is used to "punch" the display panel, that is, on the side of the display area 01 Part of the area is recessed, so that the area on the front of the mobile phone where the device 02a needs to be provided is the non-display area 02, and the other areas are all the display area 01, thereby increasing the screen-to-body ratio of the display area 01 to a certain extent.
  • the areas outside the concave portion are still non-display areas, and these still occupy a certain screen-to-body ratio, so that the non-display area 02 still exists on the front of the display device, which affects the screen-to-body ratio of the display device.
  • the display substrate 1A has a display area 01 and a peripheral area 03 surrounding the display area 01.
  • the display area 01 includes a first display area 012 and a second display area 011.
  • the first display area 012 is disposed close to the edge of the display substrate 1A, and has a shape matching the edge.
  • the display substrate 1A includes a base substrate 1, a first light shielding layer 31, a plurality of first sub-pixels 41 and a first power line 5. It should be noted that in FIGS. 3A and 3B, for ease of understanding, a plurality of first sub-pixels 41 disposed on the side of the first light-shielding layer 31 away from the base substrate 1 and their corresponding signal traces (including the first The cross-sectional pattern of a power line 5) and other structures are integrated, which is shown as the display layer 2 for illustration.
  • the first light-shielding layer 31 is disposed on one side of the base substrate 1, the first light-shielding layer 31 is located in the first display area 012, and the first light-shielding layer 31 has a plurality of openings 31a arranged in an array.
  • a plurality of first sub-pixels 41 are arranged on the side of the first light-shielding layer 31 away from the base substrate 1, the plurality of first sub-pixels 41 are located in the first display area 012, and the plurality of first sub-pixels 41 are arranged on the side of the substrate.
  • the orthographic projection of the base substrate and the orthographic projection of the opening 31a on the base substrate do not overlap. Within the orthographic projection on the substrate 1.
  • the first light-shielding layer 31 is configured to block ambient light and prevent the ambient light from passing through areas other than the plurality of openings 31a of the first light-shielding layer 31
  • the ambient light signal includes an invisible light signal, such as an infrared light signal.
  • the transmission path of ambient light is shown by the dashed line with arrows in FIG. 3A.
  • the two sides of the display substrate 1A refer to opposite sides of the display substrate 1A in a direction perpendicular to the base substrate 1.
  • the first light shielding layer 31 is also configured to shield the light emitted by the light emitting device of the display substrate 1A (i.e., screen light), that is, the light emitted by the light emitting device can be directed to a portion of the first light shielding layer 31 away from the base substrate 1. Side, but cannot be directed toward the side of the first light shielding layer 31 close to the base substrate 1.
  • the first power line 5 includes a first power bus 51 and a plurality of first power sub-lines 52. At least a part of the first power bus 51 is located in an area close to the first display area 012 in the peripheral area 03.
  • the plurality of first power sub-lines 52 are located in the first display area 012 and are electrically connected to the first power bus 51, and the plurality of first power sub-lines 52 are configured to provide the first sub-pixels 41 with the For a power signal, the orthographic projection of the plurality of first power sub-lines 52 on the base substrate 1 and the orthographic projection of the opening 31a of the first light shielding layer 31 on the base substrate 1 do not overlap.
  • the first light shielding layer 31 is electrically connected to the first power line 5.
  • the first power line 5 provides the first power signal to the first light-shielding layer 31, so that the first light-shielding layer 31 is connected to a stable electric signal, so as to avoid the uncontrollable potential signal of the first light-shielding layer 31, which may affect the display.
  • the embodiment of the present disclosure does not limit the material of the first light-shielding layer 31, and the light-shielding function shall prevail.
  • the material of the first light shielding layer 31 may be black resin, metal, or the like.
  • the material of the first light-shielding layer 31 is a metal material, induced charges are easily generated on the first light-shielding layer 31, which may affect the plurality of first sub-pixels 41, for example, causing damage to the plurality of first sub-pixels 41.
  • the voltage is unstable.
  • the material of the first light-shielding layer 31 is a metal material
  • the first light-shielding layer 31 is electrically connected to the first power line 5, thereby connecting the first light-shielding layer 31
  • a constant electrical signal is used to prevent the induced charges on the first light shielding layer 31 from being generated, thereby avoiding the influence of the induced charges on the first light shielding layer 31 on the plurality of first sub-pixels 41.
  • the display substrate 1A provided by the embodiment of the present disclosure can be used to manufacture the display device 3A.
  • some embodiments of the present disclosure further provide a display device 3A, which includes a display substrate 1A and a front optical component 300.
  • the front optical component 300 is disposed on the side of the display substrate 1A far away from the display surface thereof, and the orthographic projection of the front optical component 300 on the display substrate 1A is located in the first display area 012.
  • the display device 3A is a mobile phone 3A'
  • the front optical component 300 provided in the mobile phone 3A' is an infrared detection unit 300' as an example for illustration:
  • the infrared detection unit 300' is arranged on the non-display surface of the mobile phone 3A', and there is no need to separately set an area for placing the infrared detection unit 300' in the display area 01. As shown in FIG. 7, in the detection mode (that is, the infrared detection unit is turned on), the infrared light signal emitted by the infrared detection unit 300' can pass through the area corresponding to the multiple openings 31a of the first light shielding layer 31 in the display substrate 1A.
  • the detected object such as a person
  • the infrared light signal emitted by the infrared detection unit 300' is reflected by the detected object, and then the reflected infrared light signal It passes through the area corresponding to the plurality of openings 31a of the first light shielding layer 31 in the display substrate 1A, and then is directed toward the infrared detection unit 300' to realize the detection function.
  • the infrared detection unit 300' even if the infrared detection unit 300' is installed on the non-display surface of the mobile phone 3A', its front detection function can be realized.
  • both the first display area 012 and the second display area 011 included in the display area 01 of the display substrate 1A can be displayed, that is, the entire display surface of the mobile phone 3A' can be displayed normally.
  • the non-display area of the infrared detection unit 300' is placed, so that the area of the non-display area (that is, the peripheral area 03) of the mobile phone 3A' is reduced, the area of the display area 01 is increased, and the screen-to-body ratio of the display area 01 is increased.
  • the display substrate 1A provided by the embodiment of the present disclosure can increase the screen-to-body ratio of the display device.
  • the first light-shielding layer 31 included in the display substrate 1A provided by the embodiment of the present disclosure can shield the ambient light from the side of the base substrate 1 away from the display layer 2 and prevent the ambient light from being directed to the first light-shielding layer. 31 is opposed to the display layer 2 (the display layer 2 includes the first sub-pixel 41 and signal wiring, etc.).
  • the ambient light includes an invisible light signal, such as the infrared light signal emitted by the above-mentioned infrared detection unit 300'.
  • the first light shielding layer 31 can prevent the infrared light signal emitted by the above-mentioned infrared detection unit 300 ′ from irradiating the display layer 2, thereby avoiding the adverse effect of the infrared light signal on the display layer 2.
  • At least one first sub-pixel 41 of the plurality of first sub-pixels 41 includes a thin film transistor and a storage capacitor, and the thin film transistor and the storage capacitor constitute a pixel driving circuit, for example.
  • the pixel driving circuit 21 has a 7T1C structure as shown in FIG. 8, and the pixel driving circuit 21 is electrically connected to the light-emitting device 22 to drive the light-emitting device 22 to emit light.
  • the polysilicon channel of the thin film transistor (that is, the area between the source and drain of the thin film transistor in the on state) is more sensitive to energy, when an infrared light signal illuminates the thin film transistor, the polysilicon channel of the thin film transistor is easy to The photocurrent is generated, which easily causes the instability of the current in the pixel driving circuit 21, which causes unstable light emission of the light-emitting device 22, thereby affecting the display quality.
  • the infrared light signal emitted by the above-mentioned infrared detection unit 300' cannot be irradiated to the thin film transistor in the first sub-pixel 41, thereby avoiding the adverse effect of the infrared light signal on the thin film transistor.
  • the first light shielding layer 31 can also block a part of the screen light reflected by the detection object, thereby reducing the screen light passing through the first display area 012, thereby reducing the adverse effect of the screen light on the front optical component 300. For example, the influence of the screen light on the information collection function of the infrared detection unit 300' is reduced.
  • the display substrate 1A further includes: at least one insulating film 20b disposed between the first power line 5 and the first light shielding layer 31, and the at least one insulating film 20b
  • the film 20b is provided with a plurality of via holes P penetrating the at least one insulating film 20b.
  • the first power line 5 is electrically connected to the first light shielding layer 31 through the plurality of via holes P.
  • the plurality of via holes P include at least two types of via holes P having different hole depths h (FIG. 10 uses three types of via holes P as an example for illustration). In this way, the contact yield between the first power line 5 and the first light shielding layer 31 can be improved.
  • FIGS. 10 to 11C is illustrated with a plurality of via holes P including three types of via holes P having different hole depths h.
  • the depth h of each via P in the plurality of vias P is greater than or equal to the first power line 5 and the first power line 5 in the direction perpendicular to the base substrate 1.
  • the distance d1 between the light shielding layers 31 is smaller than the distance d2 between the first power line 5 and the base substrate 1 in the direction perpendicular to the base substrate 1.
  • three types of first via holes P with different hole depths h are produced:
  • the hole depth h of the first type of via P is equal to the distance d1 between the first power line 5 and the first light shielding layer 31 in the direction perpendicular to the base substrate 1. That is, the first type via P exposes the upper surface of the first light shielding layer 31 (that is, the surface of the first light shielding layer 31 away from the base substrate).
  • the hole depth h of the second and third types of first via holes P is greater than the distance d1 between the first power line 5 and the first light shielding layer 31 in the direction perpendicular to the base substrate 1, and less than in the direction perpendicular to the The distance d2 between the first power line 5 and the base substrate 1 in the direction of the base substrate 1; and the hole depth h of the second type via P is smaller than the hole depth h of the third type via P.
  • a via P with the smallest hole depth h does not expose the first light shielding layer 31, and the first power line 5 cannot pass through the via P It is electrically connected to the first light shielding layer 31.
  • the other two types of vias P having a larger hole depth h expose the first light shielding layer 31, and the first power line 5 can be electrically connected to the first light shielding layer 31 through the two types of vias P.
  • a via P with the largest hole depth h may cause etching damage to the first light shielding layer 31, which may cause the first power line 5 and the first light shielding
  • the contact between the layers 31 is poor.
  • the first conductive layer 210 may be electrically connected to the first light shielding layer 31 through the other two types of via holes P having a smaller hole depth h.
  • the display substrate 1A provided by the embodiments of the present disclosure, by making via holes P with different hole depths h, it is possible to effectively avoid the occurrence of etching fluctuations (under-etching or over-etching) during the process of making the via holes P. ) Caused by the poor contact between the first power line 5 and the first light-shielding layer 31, resulting in a waste of materials, and the first light-shielding layer 31 cannot be effectively connected to a stable electrical signal.
  • the contact yield between the first power line 5 and the first light shielding layer 31 is improved, thereby increasing the first power line 5 and the first light shielding layer 31.
  • the reliability of the electrical connection between a power cord 5 and the first light shielding layer 31 is improved.
  • the plurality of vias P includes at least two vias P with different apertures d (three are taken as an example for illustration in FIG. 10), so that the first power line can be improved. 5 The contact yield with the first light-shielding layer 31.
  • the plurality of via holes P include at least two types of via holes P having different hole depths h and different hole diameters d (FIG. 10 uses three as an example for illustration). In this way, the contact yield between the first conductive layer 20 and the light shielding layer 3 can be improved.
  • the arrangement and positions of the multiple vias P have the following situations:
  • the first light-shielding layer 31 is also located in the peripheral region 03, and the plurality of via holes P includes a plurality of first via holes P1 located in the peripheral region 03, and the first light-shielding layer 31 passes The plurality of first via holes P1 are electrically connected to the first power bus 51, so as to realize the electrical connection between the first light shielding layer 31 and the first power line 5.
  • the arrangement of the plurality of first via holes P1 includes but is not limited to the following:
  • the plurality of first via holes P1 includes at least one first via hole group M (in FIG. 13, five first via hole groups M are taken as an example for illustration).
  • Each first via group M includes at least one first via row m (5 first via rows m are taken as an example in FIG. 13 for illustration).
  • the hole depth h of each first via hole P1 in each first via hole row m is different.
  • the larger black dot in FIG. 13 indicates the first via P1 with a larger hole depth h
  • the smaller black dot in FIG. 2 indicates the first via P1 with a smaller hole depth h.
  • the black dot indicates the first via P1 with a larger hole depth h.
  • the first power bus 51 and the first light-shielding layer 31 can be in contact through at least one first via hole group M, which increases the contact area between the first power bus 51 and the first light-shielding layer 31 Therefore, the contact yield between the first power bus 51 and the first light shielding layer 31 is improved.
  • the first via holes P1 in each first via hole group M are arranged in an array.
  • the array arrangement may be arranged in multiple rows and multiple columns, for example, as shown in FIG. 2 with 3 rows and 5 columns. It is assumed that the row direction of the first via holes P1 in each first via hole group M is the first direction D1, and the column direction is the second direction D2. It can be understood that the row direction and the column direction of the arrangement of the first via holes P1 cross each other, that is, the first direction D1 and the second direction D2 cross each other, for example, the first direction D1 and the second direction D2 are perpendicular to each other.
  • the plurality of first via holes P1 includes three types of via holes having different hole depths h, and the number of first via hole rows m in each first via hole group M is multiple, for example, 3. One, four, five, six, seven, etc.
  • each first via hole group M includes but is not limited to the following:
  • each first via hole column m includes three via holes P having different hole depths h, and the three via holes P are arranged along the second direction D2.
  • Each first via row m is arranged along the first direction D1, and the first via holes P1 with the same hole depth h in each first via row m are arranged in a row along the first direction D1.
  • each first via P1 in each first via group M adopts the arrangement as described above, and the number of the first via group M is multiple, for example, 3 , 4, 5, 6, 7, etc.
  • the plurality of first via hole groups M are arranged along the first direction D1.
  • the multiple first via rows m in each first via group M are arranged along the first direction D1
  • the first via holes P1 with the same hole depth h in each first via row m are arranged along the first The direction D1 is arranged in a row.
  • the plurality of first via holes P1 includes at least one first via hole group M (5 first via hole groups M are taken as an example for illustration in FIG. 13), and each first via hole group M includes At least one first via row m (5 first via rows m are taken as an example for illustration in FIG. 13); the aperture d of each first via P1 in each first via row m is different.
  • the first power bus and the first light-shielding layer 31 can be in contact through at least one first via group M, which increases the contact area between the first power bus 51 and the first light-shielding layer 31, Therefore, the contact yield between the first power bus 51 and the first light shielding layer 31 is improved.
  • the number of the first via group M is multiple, for example, 3, 4, 5, 6, 7, etc.
  • the number of the first via row m in each first via group M is multiple, for example, 3, 4, 5, 6, 7, etc.
  • the plurality of first via groups M are arranged along the first direction D1, wherein the plurality of first via rows m in each first via group M are arranged along the first direction D1, and each first via The first via holes P1 with the same diameter d in the hole column m are arranged in a row along the first direction D1.
  • the plurality of vias includes a plurality of first vias P1 disposed in the peripheral area 03, and further includes a plurality of second vias located in the first display area 012.
  • the first light shielding layer 31 is electrically connected to the plurality of first power sub-lines 52 through the plurality of second via holes P2, so as to achieve electrical connection between the first light shielding layer 31 and the first power line 5.
  • a plurality of second via holes P2 are arranged in the first display area 012, and the first light shielding layer 31 is electrically connected to the plurality of first power sub-lines 52 through the plurality of second via holes P2.
  • the first light shielding layer 31 can not only access the first power signal through the first power bus 51 in the peripheral area 03, but also access the first power signal through multiple first power sub-lines 52 in the first display area 012, so as to ensure the first shading
  • the layer 31 can be relatively evenly connected to the first power signal, so that uncontrollable induced charges in the first light shielding layer 31 can be avoided more effectively, and the normal operation of the plurality of first sub-pixels 41 can be ensured.
  • the plurality of second via holes P2 are evenly distributed in the first display area. In this way, in the first display area 012, the plurality of first power sub-lines 52 can pass through the plurality of second via holes P2.
  • the electrical connection with the first light-shielding layer 31 is more uniform, so that it can be ensured that the first light-shielding layer 31 can be more evenly connected to the first power signal.
  • three first sub-pixels 41 are provided at positions between every four openings of the first light-shielding layer 31, and the three first sub-pixels 41 form one pixel 4a, and one pixel The position of 4a corresponds to at least one second via P2.
  • the first light-shielding layer 31 has a plurality of openings 31a arranged in an array, and the plurality of first sub-pixels 41 form a group of three first sub-pixels 41 to form a plurality of arrays.
  • a pixel 4a is provided between every four openings 31a, and the position of each pixel 4a corresponds to a second via hole P2.
  • the plurality of first power sub-lines 52 are grouped into three first power sub-lines 52, the first power sub-lines 52 extend along the second direction D2, and the plurality of arrays
  • the row direction of the arranged pixels 4a is the same as the first direction D1
  • the column direction of the plurality of pixels 4a is the same as the second direction D2.
  • Each group of first power supply sub-lines 52 corresponds to a column of pixels 4a, and each first power supply The sub-line 52 corresponds to a row of first sub-pixels 41.
  • each column of pixels 4a arranged along the second direction D2 corresponds to a first via group M, that is, each group of first power sub-lines 52 corresponds to a first via group M.
  • the plurality of first via groups M can be prevented from being locally concentrated in the peripheral area 03, that is, the plurality of first via groups M can be uniformly distributed in the peripheral area 03 along the first direction D1, so that the first via can be improved.
  • the uniformity of the contact position distribution between the power bus 51 and the first light-shielding layer 31 can further improve the uniformity of the signal received by the first light-shielding layer 31.
  • the plurality of via holes P includes a plurality of second via holes P2 located in the first display area 012, and the first light shielding layer 31 passes through the plurality of second via holes P2 and the plurality of via holes P2.
  • the first power sub-line 52 is electrically connected, so as to realize the electrical connection between the first light shielding layer 31 and the first power line 5.
  • a plurality of second via holes P2 are arranged in the first display area 012, and the first light shielding layer 31 is electrically connected to the plurality of first power sub-lines 52 through the plurality of second via holes P2.
  • the first light shielding layer 31 can be electrically connected to a plurality of first power sub-lines 52 through a plurality of second vias P2, so that the first power signal can be more evenly connected, thereby more effectively avoiding uncontrollable induction of the first light shielding layer 31
  • the charge ensures the normal operation of the multiple first sub-pixels 41.
  • the plurality of second via holes P2 are evenly distributed in the first display area 012, so that in the first display area 012, the plurality of first power sub-lines 52 can pass through the plurality of second via holes P2 is electrically connected to the first light-shielding layer 31 more uniformly, so that it can be ensured that the first light-shielding layer 31 can be more evenly connected to the first power signal.
  • three first sub-pixels 41 are provided at positions between every four openings 31a of the first light-shielding layer 31, and the three first sub-pixels 41 form one pixel 4a, and one The position of the pixel 4a corresponds to at least one second via P2.
  • the first light-shielding layer 31 has a plurality of openings 31a arranged in an array, and the plurality of first sub-pixels 41 form a group of three first sub-pixels 41 to form a plurality of arrays.
  • a pixel 4a is arranged between every four openings, and the position of each pixel 4a corresponds to a second via P2, so as to ensure that a plurality of second vias P2 are evenly distributed in the first display area 012.
  • the first light-shielding layer 31 is also located in the peripheral area 03, and on the basis that the plurality of via holes P includes a plurality of second via holes P2 located in the first display area 012, it also includes a plurality of second via holes P2 located in the peripheral area. 03 multiple first via holes P1, the first light shielding layer 31 is electrically connected to the first power bus 51 through the multiple first via holes P1, thereby achieving electrical connection between the first light shielding layer 31 and the first power line 5 .
  • the arrangement of the plurality of first via holes P1 can refer to the above description, which will not be repeated here.
  • the second display area 011 of the display substrate 1A is described below.
  • the second display area 011 is located on the side of the first display area 012 away from the first power line 5.
  • the display substrate 1A further includes: a second light-shielding layer 32, a plurality of second sub-pixels 42 and a second power supply line 6.
  • a second light-shielding layer 32 a plurality of second sub-pixels 42 and a second power supply line 6.
  • a plurality of second sub-pixels 42 and their corresponding signal traces is integrated as a display layer 2 for illustration.
  • the second light shielding layer 32 is disposed on the side of the base substrate 1, the second light shielding layer 32 is located in the second display area 011, and the second light shielding layer 32 and the first light shielding layer 31 are located in the same layer.
  • the plurality of second sub-pixels 42 are disposed on a side of the second light shielding layer 31 away from the base substrate 1, and the plurality of second sub-pixels 42 are located in the second display area 011.
  • the second power line 6 includes a second power bus 61 and a plurality of second power sub-lines 62. At least a part of the second power bus 61 is located in an area near the second display area 011 in the peripheral area 03, and the plurality of second power sub-lines 62 are located in the second display area 011 and are electrically connected to the second power bus 61
  • the plurality of second power sub-lines 62 are configured to provide second power signals to the plurality of second sub-pixels 42.
  • the second light shielding layer 32 is configured to block the ambient light and prevent the ambient light from passing through the display substrate 1A in the second display area 011.
  • the second light shielding layer 32 is also configured to shield the light emitted by the light emitting device of the display substrate 1A (i.e., screen light), that is, the light emitted by the light emitting device can be directed to a portion of the second light shielding layer 32 away from the base substrate 1. Side, but cannot be directed toward the side of the second light shielding layer 32 close to the base substrate 1.
  • the second light-shielding layer 32 is provided, and the second light-shielding layer 32 and the first light-shielding layer 31 are located in the same layer, which can reduce the thickness difference between the first display area 012 and the second display area 011 of the display substrate 1A. The effect of improving the flatness of the display substrate 1A.
  • the second light shielding layer 32 is electrically connected to the second power line 6.
  • the second power line 6 provides the second power signal to the second light-shielding layer 32, so that the second light-shielding layer 32 is connected to a stable electrical signal, so as to avoid the uncontrollable potential signal of the second light-shielding layer 32 from affecting the display.
  • the normal operation of other structures in the substrate 1A for example, to avoid the influence of the induced charges generated on the second light shielding layer 32 on the plurality of second sub-pixels 42.
  • the display substrate 1A further includes at least one insulating film disposed between the second power line 6 and the second light-shielding layer 32, and the at least one insulating film is provided with a penetrating through the at least one insulating film.
  • the film has a plurality of via holes, and the second power line 6 is electrically connected to the second light-shielding layer 32 through the plurality of via holes.
  • the distribution density of the plurality of second sub-pixels 42 is greater than the distribution density of the plurality of first sub-pixels 41.
  • the pixel distribution density of the first display area 012 is 300 PPI (Pixels Per Inch, pixel density), and the pixel distribution density of the second display area 011 is 400 PPI.
  • the plurality of first sub-pixels 41 form a group of three first sub-pixels 41 to form a plurality of pixels 4a arranged in an array, between every four openings 31a One pixel 4a is provided, and the distribution density of the plurality of first sub-pixels 41 is relatively low.
  • the plurality of second sub-pixels 42 are arranged in an array, and the distribution density of the plurality of second sub-pixels 42 is relatively high. Under the same area, the number of the plurality of first sub-pixels 41 located in the first display area 012 is less than the number of the plurality of second sub-pixels 42 located in the second display area 011.
  • the distribution density of the plurality of second sub-pixels 42 is greater than the distribution density of the plurality of first sub-pixels 41, that is, relative to the second display Area 011, the number of first sub-pixels 41 in the first display area 012 is reduced, so that in the first display area 012, the space occupied by the first sub-pixels 41 is reduced, and the space occupied by the first sub-pixels 41 is reduced.
  • a plurality of openings 31a can leave space for light to pass through, so that the first display area 012 has a higher light transmittance.
  • the above-mentioned display substrate 1A is applied to the display device 3A.
  • the front optical component 300 is arranged on the side of the display substrate 1A away from the display surface, and the front optical component 300 is on the display substrate 1A.
  • the orthographic projection of is located in the first display area 012.
  • the light (ambient light) emitted by the front optical component 300 can pass through the first display area 012 of the display substrate 1A, which has a higher light transmittance, and at the same time, light from outside the display device can also pass through the display substrate 1A.
  • the first display area 012 with higher light transmittance is sensed by the front optical component 300, so that the front optical component 300 can realize the corresponding sensing function.
  • the first power signal transmitted by the first power line 5 is the same as the second power signal transmitted by the second power line 6, or the first power signal transmitted by the first power line 5 is the same as the second power signal.
  • the second power signal transmitted by the power line 6 is different.
  • the first power signal when the first power signal is different from the second power signal, the first power signal is smaller than the second power signal.
  • the first light-shielding layer 31 Since the distribution density of the plurality of second sub-pixels 42 is greater than the distribution density of the plurality of first sub-pixels 41, and the first light-shielding layer 31 has a plurality of openings 31a, compared to the second light-shielding layer 32, the first The area of the light-shielding layer 31 is small, so the first power signal required by the plurality of first sub-pixels 41 and the first light-shielding layer 31 is relatively small, so the magnitude relationship between the first power signal and the second power signal is set to the first The power signal is smaller than the second power signal so as to reasonably distribute the first power signal and the second power signal.
  • the display substrate 1A further includes a first light-shielding layer 31.
  • the first insulating layer 23 and the plurality of first sub-pixels 41 are insulated from each other by the first insulating layer 23, thereby preventing the first light-shielding layer 31 and the plurality of first sub-pixels 41 from each other. Crosstalk occurs in the signals of each sub-pixel.
  • the above-mentioned first insulating layer 23 is disposed between the second light-shielding layer 32 and the plurality of second sub-pixels 42.
  • the first insulating layer 23 is located The entire film layer of the first display area 012 and the second display area 011.
  • the first insulating layer 23 insulates the second light shielding layer 32 and the plurality of first sub-pixels 41 from each other, thereby preventing crosstalk of signals between the second light shielding layer 32 and the plurality of sub-pixels.
  • At least one of the plurality of first sub-pixels 41 includes a thin film transistor and a storage capacitor.
  • the thin film transistor and the storage capacitor form a pixel drive circuit.
  • the first sub-pixel 41 also includes a light-emitting device, which is electrically connected to the pixel drive circuit, and the light-emitting device is driven to emit light through the pixel drive circuit.
  • at least one second sub-pixel 42 of the plurality of second sub-pixels 42 includes a thin film transistor and a storage capacitor.
  • the thin film transistor TFT includes: an active layer 211 located on the side of the first insulating layer 23 away from the base substrate 1, and a first gate insulating layer located on the side of the active layer 211 away from the base substrate 1. 213.
  • the gate electrode 212 located on the side of the first gate insulating layer 213 away from the base substrate 1, the second gate insulating layer 214 located on the side of the gate electrode 212 away from the base substrate 1, and the second gate insulating layer 214 away from the substrate
  • the storage capacitor Cst includes a first electrode plate c1 and a second electrode plate c2.
  • the first electrode plate c1 and the gate electrode 212 are located in the same layer, and the second electrode plate c2 is located between the second gate insulating layer 214 and the interlayer insulating layer 215.
  • the aforementioned at least one insulating film 20b includes at least one of the first insulating layer 23, the first gate insulating layer 213, the second gate insulating layer 214, and the interlayer insulating layer 215.
  • the first insulating layer 23 includes at least one of the first gate insulating layer 213, the second gate insulating layer 214, and the interlayer insulating layer 215.
  • the first power supply sub-line 52 and the source 216 and drain 217 of the thin film transistor TFT are arranged in the same layer, for example, the first power sub-line 52 is electrically connected to the drain 217 of the thin film transistor TFT, so as to provide a first power signal for the first sub-pixel 41.
  • At least one insulating film 20b between the first power supply sub-line 52 and the first light shielding layer 31 includes the first insulating layer 23, the first gate insulating layer 213, the second gate insulating layer 214, and the interlayer insulating layer 215
  • the second via hole P2 penetrates the first insulating layer 23, the first gate insulating layer 213, the second gate insulating layer 214, and the interlayer insulating layer 215 to electrically connect the first power sub-line 52 and the first light shielding layer 31 .
  • At least one of the plurality of first power sub-lines 52 includes a third sub-layer 52a and a fourth sub-layer 52b, and the third sub-layer 52a It is electrically connected to the fourth sub-layer 52b through the fourth via P4.
  • At least one first power sub-line 52 includes two layers, an insulating layer is provided between the third sub-layer 52a and the fourth sub-layer 52b, and the fourth via P4 penetrates the insulating layer to connect the first power
  • the third sub-layer 52a and the fourth sub-layer 52b of the sub-line 52 are electrically connected, so that the third sub-layer 52a and the fourth sub-layer 52b are connected in parallel.
  • the resistance of the first power sub-line 52 can be reduced, thereby reducing
  • the loss of the first power signal during the transmission process is beneficial to the transmission of the first power signal in the first power sub-line 52.
  • the first light shielding layer 31 passes through the second via P2 and is connected to the first The third sub-layer 52 a of the power sub-line 52 is electrically connected, thereby achieving electrical connection with the first power sub-line 52.
  • the first power bus 51 includes a first sublayer and a second sublayer, and the first sublayer and the second sublayer are electrically connected through a third via.
  • the first power bus 51 includes two layers.
  • An insulating layer is provided between the first and second sublayers.
  • the third via penetrates the insulating layer to connect the first and second sublayers of the first power bus 51. Electrically connected, so that the first sub-layer and the second sub-layer are connected in parallel.
  • the light-shielding layer (including the first light-shielding layer 31 and the second light-shielding layer 32), a plurality of first sub-pixels 41, a plurality of second sub-pixels 42 and a plurality of signals in the display substrate 1A are combined below.
  • the wiring layout diagram (layout diagram) specifically introduces the structure of the display substrate 1A.
  • the multiple signal routing lines include a first power sub-line 52, a second power sub-line 62, a data line, a gate line (ie, a scanning signal line), a common electrode line, an initial signal line, and so on.
  • the film layers included in the display substrate 1A are sequentially It is a light-shielding layer (including the first light-shielding layer 31 and the second light-shielding layer 32), the active semiconductor layer 41a (that is, the film layer where the active layer 211 of the thin film transistor TFT is located), and the first conductive layer 81 (that is, the thin film transistor TFT)
  • the active semiconductor layer 41a may be formed by patterning a semiconductor material.
  • the active semiconductor layer 41a can be used to make an active layer of multiple transistors of the pixel driving circuit 21 in the first sub-pixel 41 or the second sub-pixel 42.
  • the pixel driving circuit 21 includes driving transistors T1, The data writing transistor T2, the threshold compensation transistor T3, the first light emission control transistor T4, the second light emission control transistor T5, the first reset transistor T6 and the second reset transistor T7, each active layer may include a source region and a drain region , The channel region between the source region and the drain region.
  • the active layer of each transistor is integrated.
  • the active semiconductor layer 41a can be made of amorphous silicon, polysilicon, oxide semiconductor materials, or the like. It should be noted that the aforementioned source region and drain region may be regions doped with n-type impurities or p-type impurities.
  • the first conductive layer 81 includes a plurality of first signal lines extending along the first direction D1, for example, the plurality of signal lines include reset control signal lines 81a (reset), scanning signal line 81b (gate) and light emission control signal line 81c (EM).
  • the first conductive layer 81 further includes a first plate c1 of the storage capacitor Cst.
  • the second conductive layer 82 includes a plurality of second signal lines extending in the first direction D1.
  • the plurality of signal lines include an initialization signal line 82a (vinit), a voltage signal line 82b (VD), and the like.
  • the second conductive layer 82 further includes a second plate c2 of the storage capacitor Cst.
  • the part of the first signal line and the second signal line between two adjacent pixels 4a is narrowed relative to the part of the pixel 4a where the pixel 4a is located. .
  • Such a design is beneficial to increase the area of the opening 31a and improve the ambient light transmittance of the display substrate 1A provided by the embodiment of the present disclosure.
  • the first signal line 81a and the second signal line 82a extend along the first direction D1, and have the same spacing in the first direction D1.
  • a plurality of first signal lines 81a are parallel to each other, and a plurality of second signal lines
  • the lines 82a are parallel to each other and are not designed to be folded.
  • the number (for example, 4) of each group of first signal lines located in the first display area 012 is greater than that of each group of first signal lines located in the second display area 011.
  • the number (for example, 3) of the second conductive layer 82 in each group of second signal lines in the first display area 012 is greater than that of each group of signal lines in the second display area 011.
  • the number of two signal lines (for example, two). This is because the distribution density of the first sub-pixel 41 is greater than the distribution density of the second sub-pixel 42.
  • the semiconductor layers 41a are connected to each other (see FIG. 5B).
  • the reset control signal line 81a (reset) in a group of first signal lines and the initialization signal line 82a (vinit) in a group of second signal lines can be located in two adjacent rows in the same column.
  • Two second sub-pixels 42 are shared, and in the first display area 012, the first signal line and the second signal line are closed, the distribution density of the first sub-pixels 41 is lower, and the separation distance is longer, and the reset control signal line 81a ( Both reset) and initialization signal line 82a (vinit) cannot be shared by two adjacent first sub-pixels 41 located in the same column, so the number of first signal lines and second signal lines located in the first display area 012 is larger .
  • the third conductive layer 83 includes a third signal line extending along the second direction D2.
  • the third signal line includes a plurality of signal lines located in the first display area 012.
  • a first power sub-line 52 (VDD1), a plurality of second power sub-lines 62 (VDD2) and a second data line 72 (data2) located in the second display area 011 pass through the first display area 012 and the second display area 011 the first data line 71 (data1), where.
  • the first data line 71 (data1) has a corner.
  • the part of the plurality of third signal lines between two adjacent pixels 4a is narrowed relative to the part of the pixel 4a.
  • Such a design is beneficial to increase the area of the opening 31 and improve the ambient light transmittance of the display substrate 1A provided by the embodiment of the present disclosure.
  • a plurality of third signal lines extend along the first direction D1, and the plurality of third signal lines are parallel to each other, and no folding design is made.
  • FIG. 5H is a schematic diagram of the stacked positional relationship of the above-mentioned active semiconductor layer 41a, the first conductive layer 81, the second conductive layer 82, and the third conductive layer 83.
  • FIG. 5H illustrates a structural diagram of a pixel driving circuit in one sub-pixel 42 of the second display area 011 (for example, corresponding to the area G in FIG. 5G), and reference may be made to FIG. 8 at the same time.
  • the second data line 72 (data) is connected to the source region of the data writing transistor T2 in the active semiconductor layer 41a through at least one via K in the insulating layer.
  • the second power supply sub-line 62 (VDD2) is connected to the source region of the corresponding first light emitting control transistor T4 in the active semiconductor layer 41a through at least one via K in the insulating layer.
  • the second power sub-line 62 (VDD2) is connected to the first plate c1 of the storage capacitor Cst in the second conductive layer 82 through at least one via K in the insulating layer.
  • the second power sub-line 62 (VDD2) is also connected to the voltage signal line 82b (VD) in the second conductive layer 82 through at least one via K in the insulating layer.
  • the third conductive layer 83 further includes a first connection portion 83a, a second connection portion 83b, and a third connection portion 83c.
  • One end of the first connection portion 83a is connected to the drain region of the corresponding threshold compensation transistor T3 in the active semiconductor layer 41a through at least one via hole K in the insulating layer, and the other end of the first connection portion 83a is connected through at least one of the insulating layers.
  • a via hole K is connected to the gate of the driving transistor T1 in the first conductive layer 81 (ie, the first plate c1 of the storage capacitor Cst).
  • One end of the second connecting portion 83b is connected to the initialization signal line 82a (vinit) through one via K in the insulating layer, and the other end of the second connecting portion 83b is connected to the active semiconductor layer 41a through at least one via K in the insulating layer.
  • the drain region of the second reset transistor T7 is connected to each other.
  • the third connection portion 83c is connected to the drain region of the second light emission control transistor T5 in the active semiconductor layer 41a through at least one via K in the insulating layer.
  • the present disclosure does not limit the structure of the pixel driving circuit 21 in the first sub-pixel 41 and the second sub-pixel 42.
  • the above are only the transistors and storage capacitors of the pixel driving circuit 21 in the second sub-pixel 42.
  • the connection relationship between the transistors of the pixel driving circuit 21 and the storage capacitor in the first sub-pixel 41 can refer to the above description, but is not limited to this.
  • each first sub-pixel 41 includes a light-emitting device 22.
  • the first light-shielding layer 31 has a plurality of openings arranged in an array. 31a, the plurality of first sub-pixels 41 take three first sub-pixels 41 as a group to form a plurality of pixels 4a arranged in an array. In the case where one pixel 4a is arranged between every four openings 31a, one pixel 4a
  • the light emitting devices 22 in the included three sub-pixels 41 are configured to emit blue light, red light, and green light, respectively.
  • each second sub-pixel 42 includes one light emitting device, and the multiple light emitting devices of the second display area 011 are configured to emit blue light, red light, or green light.
  • the film layer where the first power sub-line 52 and the source and drain of the thin film transistor are located is called the first source. Drain layer (SD1 layer); when the first power sub-line 52 is a double layer (including the third sub-layer and the fourth sub-layer), it is called the third sub-layer of the first power sub-line 52 and the source of the thin film transistor
  • the film layer where the electrode and the drain are located is the first source-drain layer (the SD1 layer)
  • the film layer where the fourth sub-layer of the first power sub-line 52 is located is the second source-drain layer (the SD2 layer).
  • the display substrate 1A further includes a flat layer 24 disposed between the thin film transistor TFT and the light emitting device 22, and a pixel defining layer 25 disposed on the side of the flat layer 24 away from the base substrate 1.
  • the flat layer The layer 24 is disposed on the side of the first source and drain layer away from the base substrate 1, and the flat layer 24 has a via hole penetrating the flat layer 24 to realize the electrical connection between the thin film transistor and the light emitting device 22.
  • a plurality of openings are defined in the pixel defining layer 25, and the plurality of openings are used for disposing a plurality of light-emitting devices 22 to define the size of the light-emitting area.
  • the light emitting device 22 includes an anode 221, a cathode 223, and a light emitting layer 222 disposed between the anode 221 and the cathode 223.
  • the relative positional relationship between the anode 221 and the cathode 223 in the embodiments of the present disclosure includes but is not limited to the following two situations:
  • the cathode 223 is farther away from the base substrate 1 than the anode 221. That is, when the base substrate 1 is placed horizontally, in a direction perpendicular to the base substrate 1 and pointing away from the base substrate 1 from the close to the base substrate 1, the cathode 223 is on the upper layer and the anode 221 is on the lower layer.
  • the source electrode 216 of the thin film transistor TFT is electrically connected to the anode electrode 221 through a via hole penetrating the planarization layer 24.
  • the cathode is closer to the base substrate than the anode. That is, when the base substrate is placed horizontally, in a direction perpendicular to the base substrate 1 and pointing away from the base substrate from the close to the base substrate, the cathode is on the bottom and the anode is on the top.
  • the display substrate 1A further includes: an encapsulation layer 26 disposed on the side of the light emitting device 22 away from the base substrate 1.
  • the encapsulation layer 26 includes: a first inorganic encapsulation The layer 261, the organic encapsulation layer 262, and the second inorganic encapsulation layer 263.
  • the first inorganic encapsulation layer 261 is disposed on the side of the cathode 223 away from the base substrate 1
  • the organic encapsulation layer 262 is disposed on the side of the first inorganic encapsulation layer 261 away from the base substrate 1
  • the second inorganic encapsulation layer 263 is disposed on the organic side.
  • the encapsulation layer 262 is away from the side of the base substrate 1.
  • the top view of the display substrate 1A is simplified, and only the arrangement of the plurality of first sub-pixels 41 and the plurality of second sub-pixels 42 is shown. It can be understood that the arrangement of the plurality of first sub-pixels 41 and the plurality of second sub-pixels 42 in the display substrate 1A shown in FIG. 2 is based on the layout of the pixel driving circuit 21 included in the sub-pixels. Illustratively, the arrangement of the plurality of first sub-pixels 41 and the plurality of second sub-pixels 42 in the display substrate 1A shown in FIG. 12 and FIG. ) The arrangement is shown. Figure 2 can be compared with Figure 12 and Figure 13.
  • each first sub-pixel 41 located in the first display area 012 is larger than that of each second sub-pixel 42 located in the second display area 011. area.
  • the area of each first sub-pixel 41 and the area of each second sub-pixel 42 described herein refer to the area of the light-emitting area of the light-emitting device 22 included in the sub-pixel.
  • the area of the orthographic projection of the pixel driving circuit 21 in the first sub-pixel 41 and the pixel driving circuit 21 in each second sub-pixel 42 on the base substrate 1 is equal.
  • each first sub-pixel 41 located in the first display area 012 is larger than the area of each second sub-pixel 42 located in the second display area 011.
  • the area of each first sub-pixel 41 located in the first display area 012 is larger than the area of each second sub-pixel 42 located in the second display area 011.
  • the area of each first sub-pixel 41 located in the first display area 012 is larger than the area of each second sub-pixel 42 located in the second display area 011.
  • the first display area 012 is more than the above-mentioned distribution density. While providing space for the first sub-pixels 41 and providing space for signal wiring (for example, multiple first power sub-lines 52, multiple first data lines 71, multiple gate lines, etc.), a large amount of These reserved spaces correspond to the multiple openings 31a of the first light-shielding layer 31.
  • These reserved spaces can be used to transmit ambient light (such as infrared light), so that the first display area 012 can not only display images normally, but also transmit ambient light, thereby avoiding opening and installing front optical components on the array substrate 1A. 300 holes for full-screen display.
  • the area of the first sub-pixel 41 located in the first display area 012 is larger than the area of the second sub-pixel 42 located in the second display area 011.
  • the lower luminous intensity caused by the decrease in the pixel distribution density of the first sub-pixel 41 in a display area 012 is compensated, and the brightness difference between the first display area 012 and the second display area 011 is reduced.
  • each sub-pixel may be a rectangle, a rhombus or other polygons. Of course, it may also be other regular patterns, which will not be listed here.
  • each sub-pixel has at least one sub-pixel opening 200b.
  • the second sub-pixel 42 and the first sub-pixel 41 that emit red and blue light have one sub-pixel opening 200b, which emits green light.
  • the second sub-pixel 42 has two sub-pixel openings 200b.
  • the interval d3 between the sub-pixel openings 200b of any two sub-pixels adjacent to each other along the first direction D1 that emit light of the same color is equal.
  • the interval d3 between the sub-pixel openings 200b of any two first sub-pixels 41 adjacent to each other along the first direction D1 that emits blue light B is equal.
  • the interval d3 between the sub-pixel openings 200b of any two second sub-pixels 42 adjacent to each other along the first direction D1 that emits blue light B is equal.
  • the interval d3 between the sub-pixel openings 200b of any two second sub-pixels 42 that are adjacent in the first direction D1 that emits blue light B is,
  • the interval d3 between the sub-pixel openings 200b of the sub-pixel 41 is equal.
  • the light emitting device 22 includes an anode 221, a light emitting layer 222, and a cathode 223.
  • the pixel defining layer 25 is disposed on a side of the anode 221 away from the base substrate 1 and has a sub-pixel opening overlapping with the anode 221.
  • the organic electroluminescent material is formed in the sub-pixel opening of the pixel display substrate 1A to form the light-emitting function layer 222.
  • the second display area 011 and the first display area 012 have a first junction A (dotted line A).
  • each first sub-pixel 41 closest to the first junction A is used to emit the first color light, such as green light.
  • the number of sub-pixel openings 200b of each second sub-pixel 42 closest to the first junction A for emitting the first color light is smaller than that in the second display area 011 , The number of other sub-pixel openings 200b of each second sub-pixel 42 for emitting the first color light (for example, green light). This can help reduce the light color difference near the first junction A.
  • each first sub-pixel 41 closest to the first junction A is used to emit green light.
  • the number of sub-pixel openings 200b of each sub-pixel 200 for emitting green light closest to the first junction A is one.
  • the number of other sub-pixel openings 200b of each second sub-pixel 42 for emitting green light is two. This can help reduce the light color difference near the first junction A.
  • the display device 3A provided by the embodiment of the present disclosure further includes a cover plate 9 on the side of the display substrate 1A away from the base substrate 1.
  • the front optical component 300 is arranged on the side of the display panel 2A away from the display surface 01a (ie the back of the display panel 1A), and the orthographic projection of the front optical component 300 on the display substrate 2A is located in the first display area 012 .
  • the front optical component 300 is arranged on the back of the display substrate 1A, its corresponding receiving surface faces the display surface 01a of the display substrate 1A to realize its front function.
  • the above-mentioned receiving surface means that when the front optical component 300 includes a front camera unit, the receiving surface is the lens of the front camera unit; when the front optical component 300 includes an infrared sensor unit, the receiving surface is the infrared sensor unit. ⁇ sensing surface.
  • the aforementioned front optical component 300 may include a front camera unit, and of course, may also include an infrared detection unit 300'.
  • the display device 3A provided by the embodiment of the present disclosure has the same beneficial effects as the display substrate 1A provided by the embodiment of the present disclosure, and will not be repeated here.
  • the display device 3A may be any device that displays images, whether in motion (for example, video) or fixed (for example, still images), and regardless of text or pictures. More specifically, it is expected that the described embodiments can be implemented in or associated with a variety of electronic devices, including but not limited to mobile phones, wireless devices, and personal data assistants (Portable Android Device, Abbreviated as PAD), handheld or portable computer, GPS (Global Positioning System) receiver/navigator, camera, MP4 (full name MPEG-4 Part 14) video player, camera, game console, watch , Clocks, calculators, TV monitors, flat panel displays, computer monitors, car displays (e.g., odometer displays, etc.), navigators, cockpit controllers and/or displays, camera view displays (e.g., vehicle rearview Camera displays), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (for example, for displays that display an image of a piece of jewelry), etc.
  • GPS Global Positioning System
  • MP4 full name MPEG-4

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Abstract

一种显示基板(1A)，具有显示区(01)和围绕显示区(01)的周边区(03)，显示区(01)包括第一显示区(012)；显示基板(1A)包括：衬底基板(1)、第一遮光层(31)、多个第一子像素(41)和第一电源线(5)；第一遮光层(31)设置于衬底基板(1)一侧，第一遮光层(31)位于第一显示区(012)，第一遮光层(31)具有多个阵列排布的开口(31a)；多个第一子像素(41)设置于第一遮光层(31)远离衬底基板(1)一侧，多个第一子像素(41)位于第一显示区(012)，多个第一子像素(41)在衬底基板(1)的正投影与开口(31a)在衬底基板(1)的正投影不交叠；第一电源线(5)包括第一电源总线(51)和多条第一电源子线(52)；其中，第一遮光层(31)与第一电源线(5)电连接。

Description

显示基板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
在显示装置(如手机、平板电脑、可穿戴显示产品等终端产品)的结构设计中，屏占比，即显示区占整个显示装置的正面的比例，为一个重要设计参数。
随着显示技术的发展，显示装置越来越向着超大屏占比，甚至全屏显示(即显示区的面积与整个显示装置的正面的面积相等或非常接近)的方向发展，因此，如何提高显示装置的屏占比成为本领域技术人员的研究热点。
显示装置中的一些器件，如前置摄像单元、光线传感器、距离传感器、生物传感器等，若要确保其能正常工作，需使器件朝向显示装置的正面设置，例如将前置摄像单元的镜头设置为朝向显示装置的正面、将传感器的传感面设置为朝向显示装置的正面等，以使该器件能够采集到环境中的信息，从而进行相应的操作，例如采集位于显示装置的正面的人或物体的图像、采集位于显示装置的正面的光线等。
发明内容
一方面，提供一种显示基板，具有显示区和围绕所述显示区的周边区，所述显示区包括第一显示区。所述显示基板包括：衬底基板、第一遮光层、多个第一子像素和第一电源线。
第一遮光层设置于所述衬底基板一侧，所述第一遮光层位于所述第一显示区，所述第一遮光层具有多个阵列排布的开口。多个第一子像素设置于所述第一遮光层远离所述衬底基板一侧，所述多个第一子像素位于所述第一显示区，所述多个第一子像素在所述衬底基板的正投影与所述开口在所述衬底基板的正投影不交叠。第一电源线包括第一电源总线和多条第一电源子线；所述第一电源总线的至少一部分位于所述周边区中靠近所述第一显示区一侧的区域；所述多条第一电源子线位于所述第一显示区，且与所述第一电源总线电连接，所述多条第一电源子线被配置为向所述多个第一子像素提供第一电源信号，所述多条第一电源子线在所述衬底基板的正投影与所述开口在所述衬底基板的正投影不交叠。其中，所述第一遮光层与所述第一电源线电连接。
在一些实施例中，显示基板还包括：设置于所述第一电源线和所述第一 遮光层之间的至少一层绝缘薄膜，所述至少一层绝缘薄膜中设有贯通所述至少一层绝缘薄膜的多个过孔。所述第一电源线通过所述多个过孔与所述第一遮光层电连接。
在一些实施例中，所述第一遮光层还位于所述周边区，所述多个过孔包括位于所述周边区的多个第一过孔，所述第一遮光层通过所述多个第一过孔与所述第一电源总线电连接。
在一些实施例中，所述多个第一过孔包括具有不同孔深的至少两种第一过孔。
在一些实施例中，所述多个第一过孔包括至少一个第一过孔组，每个第一过孔组包括至少一个第一过孔列；每个第一过孔列中的各第一过孔的孔深不同。
在一些实施例中，所述第一过孔组的数量为多个；每个第一过孔组所包括的第一过孔列的数量为多个。所述多个第一过孔组沿第一方向排布；所述每个第一过孔组中的多个第一过孔列沿第一方向排布，且各所述第一过孔列中孔深相同的第一过孔沿第一方向排成一排。
在一些实施例中，所述多个过孔还包括位于所述第一显示区的多个第二过孔，所述第一遮光层通过所述多个第二过孔与所述多条第一电源子线电连接。
在一些实施例中，所述多个第二过孔在所述第一显示区均匀分布。
在一些实施例中，在所述第一遮光层的每四个开口之间的位置设置有一个像素，所述一个像素包括三个所述第一子像素，一个所述像素的位置至少对应一个第二过孔。
在一些实施例中，显示基板还包括：位于所述第一遮光层和所述多个子像素之间的第一绝缘层。所述多个第一子像素中的至少一个第一子像素包括薄膜晶体管和存储电容。
所述薄膜晶体管包括：位于所述第一绝缘层上的有源层；位于所述有源层远离所述衬底基板一侧的第一栅绝缘层；位于所述第一栅绝缘层远离所述衬底基板一侧的栅极；位于所述栅极远离所述衬底基板一侧的第二栅绝缘层；位于所述第二栅绝缘层远离所述衬底基板一侧的层间绝缘层和位于所述层间绝缘层远离所述衬底基板一侧的源极和漏极。
所述存储电容包括第一极板和第二极板，所述第一极板和所述栅极位于同一层，所述第二极板位于所述第二栅绝缘层和所述层间绝缘层之间。
在一些实施例中，所述至少一层绝缘薄膜包括所述第一绝缘层、所述第 一栅绝缘层、所述第二栅绝缘层和所述层间绝缘层中的至少一者。
在一些实施例中，所述第一电源总线包括第一子层和第二子层，所述第一子层和所述第二子层通过第三过孔电连接。
在一些实施例中，所述多个第一电源子线中的至少一个第一电源子线包括第三子层和第四子层，所述第三子层和所述第四子层通过第四过孔电连接。
在一些实施例中，所述显示区还包括第二显示区；所述第二显示区位于所述第一显示区远离所述第一电源线的一侧。所述显示基板还包括：多个第二子像素和第二电源线。多个第二子像素位于所述第二显示区。第二电源线，包括第二电源总线和多条第二电源子线；所述第二电源总线的至少一部分位于所述周边区中靠近所述第二显示区一侧的区域，所述多条第二电源子线位于所述第二显示区，且与所述第二电源总线电连接，所述多条第二电源子线被配置为向所述多个第二子像素提供第二电源信号。
在一些实施例中，所述第一电源信号与所述第二电源信号相同，或者，所述第一电源信号与所述第二电源信号不同。
在一些实施例中，在所述第一电源信号与所述第二电源信号不同的情况下，所述第一电源信号小于所述第二电源信号。
在一些实施例中，所述多个第二子像素的分布密度大于所述多个第一子像素的分布密度。
在一些实施例中，显示基板还包括，设置于所述衬底基板一侧的第二遮光层，所述第二遮光层位于所述第二显示区，所述第二遮光层与所述第一遮光层位于同层。所述第二遮光层与所述第二电源线电连接。
另一方面，提供一种显示装置。所述显示装置包括：如上所述的显示基板，和设置在所述显示基板的远离其显示面的一侧的前置光学部件。所述前置光学部件在所述显示基板上的正投影位于所述第一显示区内。
在一些实施例中，所述前置光学部件包括：红外检测单元。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据相关技术提供的两种显示装置的结构图；
图2为根据本公开一些实施例提供的显示基板的结构图；
图3A为根据图2提供的显示基板中截面线CC’得到的剖面图；
图3B为根据图2提供的显示基板中截面线DD’得到的剖面图；
图4为根据本公开一些实施例提供的显示基板的布线图；
图5A～图5G为图2提供的显示基板中区域G的膜层图；
图5H为根据图5G所示的膜层图中的一个子像素的膜层图；
图6A为根据本公开一些实施例提供的显示装置的一种结构图；
图6B为根据本公开一些实施例提供的显示装置的另一种结构图；
图7为根据本公开一些实施例提供的显示装置的工作示意图；
图8为根据本公开一些实施例提供的显示基板中像素驱动电路的电路图；
图9A为根据本公开一些实施例提供的显示基板的另一种剖视图；
图9B为根据本公开一些实施例提供的显示基板的再一种剖视图；
图10为根据本公开一些实施例提供的显示基板中多个过孔的一种剖视图；
图11A为根据本公开一些实施例提供的显示基板中多个过孔的另一种剖视图；
图11B为根据本公开一些实施例提供的显示基板中多个过孔的又一种剖视图；
图11C为根据本公开一些实施例提供的显示基板中多个过孔的再一种剖视图；
图12为根据本公开一些实施例提供的一种子像素排布示意图；
图13为根据本公开一些实施例提供的一种子像素开口排布示意图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)” 或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”和“串接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
“上/上方”、“下/下方”、“行/行方向”以及“列/列方向”等指示的方位或位置关系的术语为基于附图所示的方位或位置关系，仅是为了便于说明本公开的技术方案的简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
例如，在某些情况下，涉及“行方向”的实施例可以在“列方向”的情况下实施等等，相反亦如此。将本公开所述方案进行90°旋转或镜像后亦属本公开要求保护的权利范畴。
在相关技术中，如图1中的(a)部分所示，以显示装置为手机为例，手机的正面(即显示图像的一面)包括：显示区01和位于显示区01外围的非显示区02，非显示区02中的部分区域内设置有器件02a(例如为前置摄像单元、光线传感器、距离传感器、生物传感器中的一种或多种)，但是其余部分区域内并未设置器件02a，这些区域无法进行显示，从而导致屏占比较低。
随着异形切割等技术的出现，相关技术提出了将显示区从传统的矩形转 变为具有内凹(即notch)的矩形，通过将器件设置在内凹外侧的非显示区中，从而提高显示区占整个显示装置的正面的比例。
请继续参阅图1，如图1中的(b)部分所示，仍以显示装置为手机为例，采用异形切割技术在显示面板上“打孔”，即在显示区01的一侧边的部分区域形成内凹，从而使得手机的正面中需要设置上述器件02a的区域为非显示区02，其他区域则均为显示区01，从而在一定程度上提高了显示区01的屏占比。
然而，内凹部分之外的区域仍为非显示区，这些仍占据一定的屏占比，使得显示装置的正面仍存在非显示区02，影响显示装置的屏占比。
本公开实施例一方面提供一种显示基板1A。如图2～图4所示，显示基板1A具有显示区01和围绕显示区01的周边区03，显示区01包括第一显示区012和第二显示区011。
示例性地，如图2所示，第一显示区012设置于靠近显示基板1A的边缘处，且具有与边缘相配合的形状。
请继续参阅图2和图3A、图3B，显示基板1A包括衬底基板1、第一遮光层31、多个第一子像素41和第一电源线5。需要说明的是，在图3A和图3B中，为了便于理解，将设置于第一遮光层31远离衬底基板1一侧的多个第一子像素41和其对应的信号走线(包括第一电源线5)等结构的剖面图案合为一体，作为显示层2进行示意。
第一遮光层31设置于衬底基板1的一侧，第一遮光层31位于第一显示区012，第一遮光层31具有多个阵列排布的开口31a。
多个第一子像素41设置于第一遮光层31远离衬底基板1的一侧，所述多个第一子像素41位于第一显示区012，所述多个第一子像素41在衬底基板的正投影与开口31a在衬底基板的正投影不交叠，也就是说，所述多个第一子像素41在衬底基板1上的正投影在第一遮光层31在衬底基板1上的正投影之内。
请继续参阅图2～图3B，在上述显示基板1A中，第一遮光层31被配置为遮挡环境光，阻止环境光在除第一遮光层31所具有的多个开口31a之外的区域穿透显示基板1A，而在第一遮光层31所具有的多个开口31a处，环境光可以从显示基板1A的一侧射入，穿过显示基板1A，从显示基板1A的另一侧射出。其中，该环境光信号包括不可见光信号，例如红外光信号。例如，环境光的传输路径如图3A中带箭头的虚线所示。此处，显示基板1A的两侧指的是沿垂直于衬底基板1的方向，显示基板1A的相对两侧。
并且，第一遮光层31还被配置为遮挡显示基板1A的发光器件所发出的光线(即屏幕光)，即发光器件所发出的光线可以射向第一遮光层31远离衬底基板1的一侧，但无法射向第一遮光层31靠近衬底基板1的一侧。
如图2所示，第一电源线5包括第一电源总线51和多条第一电源子线52。第一电源总线51的至少一部分位于周边区03中靠近第一显示区012一侧的区域。所述多条第一电源子线52位于第一显示区012，且与第一电源总线51电连接，多条第一电源子线52被配置为向所述多个第一子像素41提供第一电源信号，所述多条第一电源子线52在衬底基板1的正投影与第一遮光层31的开口31a在衬底基板1的正投影不交叠。
其中，第一遮光层31与第一电源线5电连接。这样，第一电源线5向第一遮光层31提供第一电源信号，从而第一遮光层31被接入稳定的电信号，以避免第一遮光层31出现无法控制的电位信号，而影响显示基板1A中其他结构的正常工作。
示例性地，本公开实施例对于第一遮光层31的材料不进行限定，以能够实现遮光功能为准。例如，第一遮光层31的材料可以是黑色树脂或金属等。在第一遮光层31的材料为金属材料的情况下，第一遮光层31上容易产生感应电荷，从而可能会对多个第一子像素41造成影响，例如造成多个第一子像素41的电压不稳定。
因此，在本公开的一些实施例中，在第一遮光层31的材料为金属材料的情况下，将第一遮光层31与第一电源线5电连接，从而将第一遮光层31接入一个恒定电信号，以避免第一遮光层31上产生感应电荷，进而避免第一遮光层31上产生的感应电荷对多个第一子像素41的影响。
本公开实施例提供的显示基板1A可用于制作显示装置3A。如图6A和6B所示，在一些实施例中，本公开的一些实施例还提供了一种显示装置3A，该显示装置3A包括显示基板1A和前置光学部件300。前置光学部件300设置在显示基板1A的远离其显示面的一侧，前置光学部件300在显示基板1A上的正投影位于第一显示区012内。
如图6A和图7所示，以显示装置3A为手机3A＇，且手机3A＇中设置的前置光学部件300为红外检测单元300＇为例进行示意：
由于显示基板1A中，在第一遮光层31所具有的多个开口31a处，环境光可以从显示基板1A的一侧射入，穿过显示基板1A，从显示基板1A的另一侧射出，将红外检测单元300＇设置在手机3A＇的非显示面，无需在显示区01单独设置用于放置红外检测单元300’的区域。如图7所示，在检测模 式(即开启红外检测单元)下，红外检测单元300＇发出的红外光信号可以穿过显示基板1A中第一遮光层31的多个开口31a所对应的区域，进而射向前方(即与手机3A＇的显示面相对的)的被检测对象(例如人)，从而使得该红外检测单元300＇发出的红外光信号经被检测对象反射，然后反射的红外光信号穿过显示基板1A中第一遮光层31的多个开口31a所对应的区域，进而射向红外检测单元300＇，实现检测功能。
也就是说，即使红外检测单元300＇设置于手机3A＇的非显示面，也能实现其前置检测功能。另外，由于显示基板1A的显示区01所包括的第一显示区012和第二显示区011均能进行显示，即手机3A＇的整个显示面均可正常显示，这样一来，无需设置用于放置红外检测单元300＇的不进行显示的区域，使得手机3A＇的非显示区域(即周边区03)的面积减小，显示区01的面积增大，提高了显示区01的屏占比。
由上可知，本公开实施例提供的显示基板1A可以提高显示装置的屏占比。
请参阅图2，本公开实施例提供的显示基板1A所包括的第一遮光层31可以遮挡来自衬底基板1远离显示层2一侧的环境光，阻止环境光其射向该第一遮光层31对正对的显示层2(显示层2包括第一子像素41和信号走线等)。其中，环境光包括不可见光信号，例如上述红外检测单元300＇发出的红外光信号。这样，第一遮光层31可以防止如上述红外检测单元300＇发出的红外光信号照射至显示层2，进而避免红外光信号对显示层2的造成不良影响。
示例性地，所述多个第一子像素41中的至少一个第一子像素41包括薄膜晶体管和存储电容，薄膜晶体管和存储电容组成像素驱动电路，例如。像素驱动电路21为如图8所示的7T1C的结构，像素驱动电路21与发光器件22电连接，驱动发光器件22发光。由于薄膜晶体管的多晶硅沟道(即薄膜晶体管在导通状态下，其源极和漏极之间的区域)对能量比较敏感，当有红外光信号照射薄膜晶体管时，薄膜晶体管的多晶硅沟道容易产生光电流，从而容易引起像素驱动电路21中的电流的不稳定，造成发光器件22发光不稳定，进而影响显示质量。而在第一遮光层31的作用下，上述红外检测单元300＇发出的红外光信号无法照射至第一子像素41中的薄膜晶体管，从而避免红外光信号对薄膜晶体管的不良影响。
此外，第一遮光层31还能遮挡一部分被检测对象反射的屏幕光，从而减少透过第一显示区012的屏幕光，进而减弱屏幕光对前置光学部件300的不良影响。例如，减弱屏幕光对红外检测单元300＇的信息采集功能的影响。
在一些实施例中，如图9A～图10所示，显示基板1A还包括：设置于第一电源线5和第一遮光层31之间的至少一层绝缘薄膜20b，所述至少一层绝缘薄膜20b中设有贯通所述至少一层绝缘薄膜20b的多个过孔P。第一电源线5通过所述多个过孔P与第一遮光层31电连接。
在一些实施例中，如图10～图11C所示，该多个过孔P包括具有不同孔深h的至少两种过孔P(图10以三种过孔P为例进行示意)。这样，可以提高第一电源线5与第一遮光层31之间的接触良率。
需要解释的是，由上述描述可知，第一电源线5与第一遮光层31之间具有多层绝缘薄膜20b，要想实现第一电源线5与第一遮光层31的电连接，需要在多层绝缘薄膜20b中制作至少一个过孔P，其中每个过孔P穿透多层绝缘薄膜20b，该过孔P的孔深h较大，因此在过孔P的制作过程中，容易出现过度刻蚀或者刻蚀不足的问题。
上述实施例，如图10～图11C所示，以多个过孔P包括具有不同孔深h的三种过孔P进行示意。
示例性地，请参阅图10和图11A，多个过孔P中的每个过孔P的孔深h，大于或等于在垂直于衬底基板1的方向上第一电源线5与第一遮光层31之间的距离d1，且小于在垂直于衬底基板1的方向上第一电源线5与衬底基板1之间的距离d2。
这样，如果出现了如图11B所示的过度刻蚀情况，或者出现了如图11C所示的刻蚀不足的情况，至少可以保证第一电源线5穿过其中一种过孔P与第一遮光层31电连接，从而提高了第一电源线5与第一遮光层31之间的接触良率。
例如，如图11A所示，在一些实施例中，制作了具有不同孔深h的三种第一过孔P：
如图11A所示，第一种过孔P的孔深h，等于在垂直于衬底基板1的方向上第一电源线5与第一遮光层31之间的距离d1。即，第一种过孔P暴露出第一遮光层31的上表面(即第一遮光层31远离衬底基板的表面)。第二种和第三种第一过孔P的孔深h，大于在垂直于衬底基板1的方向上第一电源线5与第一遮光层31之间的距离d1，且小于在垂直于衬底基板1的方向上第一电源线5与衬底基板1的距离d2；并且，第二种过孔P的孔深h小于第三种过孔P的孔深h。
请参阅图12，出现刻蚀不足的情况时，此时可能存在具有最小孔深h的一种过孔P没有暴露出第一遮光层31的情况，第一电源线5无法通过该过孔 P与第一遮光层31电连接。具有较大孔深h的另外两种过孔P暴露出了第一遮光层31，第一电源线5能够通过该两种过孔P与第一遮光层31电连接。
请参阅图11，出现过度刻蚀的情况时，此时具有最大孔深h的一种过孔P可能会对第一遮光层31有刻蚀损伤，可能造成第一电源线5与第一遮光层31之间接触不良。第一导电层210可以通过具有较小孔深h的另外两种过孔P与第一遮光层31电连接。
基于此，本公开实施例提供的显示基板1A，通过制作具有不同孔深h的过孔P，可以有效避免在制作过孔P的过程中，由于出现刻蚀波动(刻蚀不足或过度刻蚀)造成的第一电源线5与第一遮光层31之间的接触不良的情况，造成资材的浪费，无法有效地将第一遮光层31接入稳定的电信号。通过在显示基板1A的多个绝缘薄膜20b中设置具有不同孔深h的至少两种过孔P，提高了第一电源线5与第一遮光层31之间的接触良率，进而提高了第一电源线5与第一遮光层31之间电连接的可靠性。
在一些实施例中，如图11A所示，上述多个过孔P包括具有不同孔径d的至少两种过孔P(图10中以三种为例进行示意)，这样可以提高第一电源线5与第一遮光层31之间的接触良率。
在一些实施例中，请参阅图11A，该多个过孔P包括具有不同孔深h和不同孔径d的至少两种过孔P(图10以三种为例进行示意)。这样可以提高第一导电层20与遮光层3之间的接触良率。
在下述实施例中，多个过孔P的设置方式及位置具有如下几种情况：
在一些实施例中，如图2所示，第一遮光层31还位于周边区03，所述多个过孔P包括位于周边区03的多个第一过孔P1，第一遮光层31通过所述多个第一过孔P1与第一电源总线51电连接，从而实现第一遮光层31与第一电源线5的电连接。
在周边区03内，多个第一过孔P1的排布方式包括但不限于下述方式：
如图2所示，多个第一过孔P1包括至少一个第一过孔组M(图13中以5个第一过孔组M为例进行示意)。每个第一过孔组M包括至少一个第一过孔列m(图13中以5个第一过孔列m为例进行示意)。每个第一过孔列m中的各第一过孔P1的孔深h不同。需要说明的是，图13中较大的黑点表示孔深h较大的第一过孔P1，图2中较小的黑点表示孔深h较小的第一过孔P1,较大的黑点表示孔深h较大的第一过孔P1。
这样，在周边区03内，第一电源总线51与第一遮光层31可以通过至少一个第一过孔组M接触，增大了第一电源总线51与第一遮光层31之间的接 触面积，从而提高了第一电源总线51与第一遮光层31之间的接触良率。
如图2所示，在一些实施例中，每个第一过孔组M中各个第一过孔P1呈阵列式排布。
此处，阵列式布置可以是排布成多行和多列，例如，图2中以3行5列进行示意。设定每个第一过孔组M中各个第一过孔P1排列的行方向为第一方向D1，列方向为第二方向D2。可以理解的是，各个第一过孔P1排列的行方向和列方向相互交叉，即第一方向D1与第二方向D2相互交叉，例如第一方向D1与第二方向D2相互垂直。
在一些实施例中，上述多个第一过孔P1包括具有不同孔深h的三种过孔，且每个第一过孔组M中第一过孔列m的数量是多个，例如3个、4个、5个、6个、7个等。
下面以该些实施例中的多个过孔P为例对每个第一过孔组M中各个第一过孔P1的排布方式进行详细说明，即上述多个过孔P包括具有不同孔深h的三种过孔P，且每个第一过孔组M中第一过孔列m的数量是多个。可以理解的是，每个第一过孔组M中各个第一过孔P1的排布方式包括但不限于下述方式：
如图2所示，每个第一过孔列m包括具有不同孔深h的三个过孔P，且这三个过孔P沿第二方向D2排布。各第一过孔列m沿第一方向D1排布，且各第一过孔列m中孔深h相同的第一过孔P1沿第一方向D1排成一排。
在一些示例中，每个第一过孔组M中各个第一过孔P1的排布方式采用如上所述的排布方式，且第一过孔组M的数量为多个，例如，3个、4个、5个、6个、7个等。该多个第一过孔组M沿第一方向D1排布。其中，每个第一过孔组M中的多个第一过孔列m沿第一方向D1排布，且各第一过孔列m中孔深h相同的第一过孔P1沿第一方向D1排成一排。
在一些实施例中，多个第一过孔P1包括至少一个第一过孔组M(图13中以5个第一过孔组M为例进行示意)，每个第一过孔组M包括至少一个第一过孔列m(图13中以5个第一过孔列m为例进行示意)；每个第一过孔列m中的各第一过孔P1的孔径d不同。这样，在周边区03内，第一电源总线与第一遮光层31可以通过至少一个第一过孔组M接触，增大了第一电源总线51与第一遮光层31之间的接触面积，从而提高了第一电源总线51与第一遮光层31之间的接触良率。
示例性的，第一过孔组M的数量为多个，例如，3个、4个、5个、6个、7个等。每个第一过孔组M中第一过孔列m的数量为多个，例如，3个、4 个、5个、6个、7个等。该多个第一过孔组M沿第一方向D1排布，其中，每个第一过孔组M中的多个第一过孔列m沿第一方向D1排布，且各第一过孔列m中孔径d相同的第一过孔P1沿第一方向D1排成一排。
在一些实施例中，如图2所示，所述多个过孔在包括设置于周边区03的多个第一过孔P1的基础上，还包括位于第一显示区012的多个第二过孔P2，第一遮光层31通过所述多个第二过孔P2与所述多条第一电源子线52电连接，从而实现第一遮光层31与第一电源线5的电连接。
将多个第二过孔P2设置在第一显示区012，通过多个第二过孔P2使得第一遮光层31与所述多条第一电源子线52电连接，这样，第一遮光层31不仅能够在周边区03通过第一电源总线51接入第一电源信号，还可以在第一显示区012通过多条第一电源子线52接入第一电源信号，从而可以保证第一遮光层31能够比较均匀地接入第一电源信号，从而能够更有效地避免第一遮光层31出现不可控制的感应电荷，保证多个第一子像素41的正常工作。
在一些示例中，所述多个第二过孔P2在所述第一显示区均匀分布，这样，在第一显示区012，多条第一电源子线52能够通过多个第二过孔P2与第一遮光层31更加均匀地电连接，从而可以保证第一遮光层31能够比较均匀地接入第一电源信号。
在一些实施例中，如图2所示，在第一遮光层31的每四个开口之间的位置设置有三个第一子像素41，三个第一子像素41组成一个像素4a，一个像素4a的位置至少对应一个第二过孔P2。
示例性地，如图2所示，第一遮光层31具有多个阵列排布的开口31a，多个第一子像素41以三个第一子像素41为一组，形成多个阵列排布的像素4a，在每四个开口31a之间设置一个像素4a，每个像素4a的位置对应一个第二过孔P2。
基于上述多个第一子像素41的排布方式，多条第一电源子线52以三条第一电源子线52为一组，第一电源子线52沿第二方向D2延伸，多个阵列排布的像素4a排列的行方向与第一方向D1相同，多个像素4a排列的列方向与第二方向D2相同，每一组第一电源子线52对应一列像素4a，每条第一电源子线52对应一列第一子像素41。
上述显示基板1A中，沿第二方向D2排列的各列像素4a分别对应一个第一过孔组M，即每一组第一电源子线52对应一个第一过孔组M。这样，可以防止多个第一过孔组M在周边区03内局部集中，即，可以使得多个第一过孔组M在周边区03内，沿第一方向D1均匀分布，从而可以提高第一电源总线 51与第一遮光层31之间的接触位置分布的均匀性，进而可以提高第一遮光层31所接收的信号的均一性。
在另一些实施例中，所述多个过孔P包括位于第一显示区012的多个第二过孔P2，第一遮光层31通过所述多个第二过孔P2与所述多条第一电源子线52电连接，从而实现第一遮光层31与第一电源线5的电连接。
将多个第二过孔P2设置在第一显示区012，通过多个第二过孔P2使得第一遮光层31与所述多条第一电源子线52电连接，这样，第一遮光层31能够通过多个第二过孔P2与多条第一电源子线52电连接，从而能够比较均匀地接入第一电源信号，从而能够更有效地避免第一遮光层31出现不可控制的感应电荷，保证多个第一子像素41的正常工作。
在一些示例中，所述多个第二过孔P2在所述第一显示区012均匀分布，这样，在第一显示区012，多条第一电源子线52能够通过多个第二过孔P2与第一遮光层31更加均匀地电连接，从而可以保证第一遮光层31能够比较均匀地接入第一电源信号。
在一些实施例中，如图2所示，在第一遮光层31的每四个开口31a之间的位置设置有三个第一子像素41，三个第一子像素41组成一个像素4a，一个像素4a的位置至少对应一个第二过孔P2。
示例性地，如图2所示，第一遮光层31具有多个阵列排布的开口31a，多个第一子像素41以三个第一子像素41为一组，形成多个阵列排布的像素4a，在每四个开口之间设置一个像素4a，每个像素4a的位置对应一个第二过孔P2，从而可以保证多个第二过孔P2在第一显示区012均匀分布。
在一些实施例中，第一遮光层31还位于周边区03，在所述多个过孔P包括位于第一显示区012的多个第二过孔P2的基础上，还包括设置于周边区03的多个第一过孔P1，第一遮光层31通过所述多个第一过孔P1与第一电源总线51电连接，从而实现第一遮光层31与第一电源线5的电连接。
在周边区03内，多个第一过孔P1的排布方式可参考上面的描述，此处不再赘述。
请再次参考图2～图4，以下介绍显示基板1A的第二显示区011，在一些示例中，第二显示区011位于第一显示区012远离第一电源线5的一侧。
如图图2、3A和3B所示，显示基板1A还包括：第二遮光层32、多个第二子像素42和第二电源线6。需要说明的是，在图3A和3B中，为了便于理解，将设置于第二遮光层32远离衬底基板1一侧的多个第二子像素42和其对应的信号走线(包括第二电源线6)等结构的剖面图案合为一体，作为显示 层2进行示意。
第二遮光层32设置于衬底基板1一侧，第二遮光层32位于第二显示区011，第二遮光层32与第一遮光层31位于同层。
多个第二子像素42设置于第二遮光层31远离衬底基板1的一侧，多个第二子像素42位于第二显示区011。
第二电源线6包括第二电源总线61和多条第二电源子线62。第二电源总线61的至少一部分位于周边03区中靠近第二显示区011一侧的区域，所述多条第二电源子线62位于第二显示区011，且与第二电源总线61电连接，所述多条第二电源子线62被配置为向所述多个第二子像素42提供第二电源信号。
在上述显示基板1A中，第二遮光层32被配置为遮挡环境光，阻止环境光在第二显示区011穿过显示基板1A。并且，第二遮光层32还被配置为遮挡显示基板1A的发光器件所发出的光线(即屏幕光)，即发光器件所发出的光线可以射向第二遮光层32远离衬底基板1的一侧，但无法射向第二遮光层32靠近衬底基板1的一侧。
同时，设置第二遮光层32，且第二遮光层32与第一遮光层31位于同层，能起到降低显示基板1A的第一显示区012和第二显示区011的膜层厚度差，提高显示基板1A的平坦度的作用。
在一些实施例中，第二遮光层32与第二电源线6电连接。这样，第二电源线6向第二遮光层32提供第二电源信号，从而第二遮光层32被接入稳定的电信号，以避免第二遮光层32出现无法控制的电位信号，而影响显示基板1A中其他结构的正常工作，例如避免第二遮光层32上产生的感应电荷对多个第二子像素42的影响。
在一些实施例中，显示基板1A还包括设置于第二电源线6和第二遮光层32之间的至少一层绝缘薄膜，所述至少一层绝缘薄膜中设有贯通所述至少一层绝缘薄膜的多个过孔，第二电源线6通过多个过孔与第二遮光层32电连接。
关于上述多个过孔的具体设置，以及多个第二子像素42的结构可参考前边提到的在显示基板1A的第一显示区012中，多个过孔的具体设置，以及多个第二子像素42的结构的描述，此处不再赘述。
在一些实施例中，如图2所示，所述多个第二子像素42的分布密度大于所述多个第一子像素41的分布密度。示例性的，第一显示区012的像素分布密度为300PPI(Pixels Per Inch，像素密度)，第二显示区011的像素分布密度为400PPI。
如图2所示，在第一显示区012，多个第一子像素41以三个第一子像素41为一组，形成多个阵列排布的像素4a，在每四个开口31a之间设置一个像素4a，多个第一子像素41的分布密度较低。在第二显示区0121，多个第二子像素42呈阵列式排布，多个第二子像素42的分布密度较高。在同等面积下，位于第一显示区012的多个第一子像素41的个数少于位于第二显示区011的多个第二子像素42的个数。
通过这样设置，在显示基板1A的显示区01能够进行显示的前提下，通过多个第二子像素42的分布密度大于所述多个第一子像素41的分布密度，即相对于第二显示区011，减小第一显示区012的第一子像素41的个数，从而在第一显示区012，第一子像素41所占用的空间减小，且通过在第一遮光层31中设置多个开口31a，这样就可以留出空间使得光线可以透过，从而使第一显示区012具有较高的光透过率。
这样，将上述显示基板1A应用于显示装置3A中，如图6B所示，将前置光学部件300设置在显示基板1A的远离其显示面的一侧，前置光学部件300在显示基板1A上的正投影位于第一显示区012内。这样，前置光学部件300所发出的光线(环境光)可以透过显示基板1A的具有较高光透过率的第一显示区012，同时来自显示装置外部的光线也能透过显示基板1A的具有较高光透过率的第一显示区012，被前置光学部件300所感应，从而使得前置光学部件300能够实现相应的感应功能。
在一些实施例中，第一电源线5所传输的第一电源信号与第二电源线6所传输的第二电源信号相同，或者，第一电源线5所传输的第一电源信号与第二电源线6所传输的第二电源信号不同。
示例性地，在第一电源信号与第二电源信号不同的情况下，第一电源信号小于第二电源信号。
由于所述多个第二子像素42的分布密度大于所述多个第一子像素41的分布密度，并且，第一遮光层31具有多个开口31a，相比第二遮光层32，第一遮光层31的面积较小，因此多个第一子像素41以及第一遮光层31所需要的第一电源信号较小，因此将第一电源信号和第二电源信号的大小关系设置为第一电源信号小于第二电源信号，以合理分配第一电源信号和第二电源信号。
可以理解的是，在显示基板1A中，不同导电层之间设置有用于绝缘的绝缘膜层，在一些实施例中，如图9A和9B所示，显示基板1A还包括位于第 一遮光层31和多个第一子像素41之间的第一绝缘层23，通过第一绝缘层23，将第一遮光层31和多个第一子像素41相互绝缘，从而防止第一遮光层31和多个子像素的信号发生串扰。
在显示基板1A还包括第二遮光层32的情况下，上述第一绝缘层23设置于第二遮光层32和多个第二子像素42之间，示例性地，第一绝缘层23为位于第一显示区012和第二显示区011的整层膜层。通过第一绝缘层23，将第二遮光层32和多个第一子像素41相互绝缘，从而防止第二遮光层32和多个子像素的信号发生串扰。
所述多个第一子像素41中的至少一个第一子像素41包括薄膜晶体管和存储电容。该薄膜晶体管和存储电容组成像素驱动电路，第一子像素41还包括发光器件，发光器件与像素驱动电路电连接，通过像素驱动电路驱动发光器件发光。同样，所述多个第二子像素42中的至少一个第二子像素42包括薄膜晶体管和存储电容。
如图9A和9B所示，薄膜晶体管TFT包括：位于第一绝缘层23远离衬底基板1一侧的有源层211、位于有源层211远离衬底基板1一侧的第一栅绝缘层213、位于第一栅绝缘层213远离衬底基板1一侧的栅极212、位于栅极212远离衬底基板1一侧的第二栅绝缘层214、位于第二栅绝缘层214远离衬底基板1一侧的层间绝缘层215、位于层间绝缘层215远离衬底基板1一侧的源极216和漏极217。
存储电容Cst包括第一极板c1和第二极板c2，第一极板c1和栅极212位于同一层，第二极板c2位于第二栅绝缘层214和层间绝缘层215之间。
如图9A和9B所示，前面所提到的所述至少一层绝缘薄膜20b包括第一绝缘层23、第一栅绝缘层213、第二栅绝缘层214和层间绝缘层215中的至少一者。
示例性的，如图9A所示，在显示基板1A的第一显示区012，第一电源子线52与薄膜晶体管TFT的源极216和漏极217同层设置，例如，第一电源子线52与薄膜晶体管TFT的漏极217电连接，从而为第一子像素41提供第一电源信号。在第一电源子线52与第一遮光层31之间的至少一层绝缘薄膜20b包括第一绝缘层23、第一栅绝缘层213、第二栅绝缘层214和层间绝缘层215的情况下，第二过孔P2贯穿第一绝缘层23、第一栅绝缘层213、第二栅绝缘层214和层间绝缘层215，实现将第一电源子线52与第一遮光层31电连接。
在一些实施例中，如图9B所示，所述多个第一电源子线52中的至少一个第一电源子线52包括第三子层52a和第四子层52b，第三子层52a和第四子层52b通过第四过孔P4电连接。
在上述实施例中，至少一个第一电源子线52包括两层，第三子层52a和第四子层52b之间设置有绝缘层，第四过孔P4贯穿该绝缘层，将第一电源子线52的第三子层52a和第四子层52b电连接，从而第三子层52a和第四子层52b并联，通过这样设置，可以减小第一电源子线52的电阻，从而降低第一电源信号在传输过程中的损耗，有利于第一电源子线52中第一电源信号的传输。示例性地，如图9B所示，在至少一个第一电源子线52包括第三子层52a和第四子层52b的情况下，第一遮光层31通过第二过孔P2和与第一电源子线52的第三子层52a电连接，从而实现与第一电源子线52的电连接。
在一些实施例中，第一电源总线51包括第一子层和第二子层，第一子层和第二子层通过第三过孔电连接。第一电源总线51包括两层，第一子层和第二子层之间设置有绝缘层，第三过孔贯穿该绝缘层，将第一电源总线51的第一子层和第二子层电连接，从而第一子层和第二子层并联，通过这样设置，可以减小第一电源总线51的电阻，从而降低第一电源信号在传输过程中的损失，有利于第一电源信号的传输。
如图5A～5G所示，以下结合显示基板1A中遮光层(包括第一遮光层31和第二遮光层32)、多个第一子像素41、多个第二子像素42以及多条信号走线的布局图(layout图)，对显示基板1A的结构进行具体介绍。其中，多条信号走线包括第一电源子线52、第二电源子线62、数据线、栅线(即扫描信号线)、公共电极线、初始信号线等。
如图5A～5F所示，在不考虑绝缘薄膜的前提下，在垂直于衬底基板1且由靠近衬底基板1指向远离衬底基板1的方向上，显示基板1A所包括的膜层依次为遮光层(包括第一遮光层31和第二遮光层32)、有源半导体层41a(即薄膜晶体管TFT的有源层211所在的膜层)、第一导电层81(即薄膜晶体管TFT的栅极212及存储电容Cst的第一极板c1所在的膜层)、第二导电层82(即存储电容Cst的第二极板c2所在的膜层)、连接过孔K、第三导电层83(即薄膜晶体管的源极216和漏极217所在的膜层，也就是第一电源子线52的第三子层52a)，将上述膜层按照顺序依次叠加，即可得到图5G所示的总布局图。
在一些实施例中，有源半导体层41a可采用半导体材料图案化形成。有源半导体层41a可用于制作上述第一子像素41或第二子像素42中的像素驱 动电路21的多个晶体管的有源层，如图8所示，像素驱动电路21包括驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6和第二复位晶体管T7，各有源层可包括源极区域、漏极区域、源极区域和漏极区域之间的沟道区。例如，各晶体管的有源层一体设置。
例如，有源半导体层41a可采用非晶硅、多晶硅、氧化物半导体材料等制作。需要说明的是，上述的源极区域和漏极区域可为掺杂有n型杂质或p型杂质的区域。
在一些实施例中，如图2、图5C和图5D所示，第一导电层81包括多条沿第一方向D1延伸的第一信号线，例如，该多条信号线包括复位控制信号线81a(reset)，扫描信号线81b(gate)和发光控制信号线81c(EM)。在一些示例中，第一导电层81还包括存储电容Cst的第一极板c1。第二导电层82包括多条沿第一方向D1延伸的第二信号线，例如，该多条信号线包括初始化信号线82a(vinit)和电压信号线82b(VD)等。在一些示例中，第二导电层82还包括存储电容Cst的第二极板c2。
在第一显示区012，第一信号线和第二信号线的位于相邻两个像素4a(包括三个第一子像素41)之间的部分，相对于其位于像素4a所在区域的部分收拢。这样设计有利于增大开口31a的面积，提高本公开实施例提供的显示基板1A的环境光透过率。在第二显示区011，第一信号线81a和第二信号线82a沿第一方向D1延伸，且在第一方向D1上间距一致，多条第一信号线81a相互平行，多条第二信号线82a相互平行，不做收拢设计。
需要说明的是，第一导电层81中，位于第一显示区012的每组第一信号线的条数(例如为4条)，大于位于第二显示区011的每组第一信号线的条数(例如为3条)，第二导电层82中，位于第一显示区012的每组第二信号线的条数(例如为3条)，大于位于第二显示区011的每组第二信号线的条数(例如为2条)，这是因为第一子像素41的分布密度大于第二子像素42的分布密度，位于同一列的相邻两个第二子像素42的有源半导体层41a相互连接(可参见图5B)。从而在第二显示区011，一组第一信号线中的复位控制信号线81a(reset)，以及一组第二信号线中的初始化信号线82a(vinit)能够被位于同一列的相邻两个第二子像素42共用，而在第一显示区012，第一信号线和第二信号线有收拢，第一子像素41的分布密度较低，间隔距离较远，复位控制信号线81a(reset)和初始化信号线82a(vinit)均无法被位于同一列的相邻两个第一子像素41共用，因此位于第一显示区012的第一信号 线和第二信号线的条数较多。
在一些实施例中，如图2和图5F所示，第三导电层83包括沿第二方向D2延伸的第三信号线，示例性地，第三信号线包括位于第一显示区012的多条第一电源子线52(VDD1)、位于第二显示区011的多条第二电源子线62(VDD2)和第二数据线72(data2)，贯穿第一显示区012和第二显示区011的第一数据线71(data1)，其中。在第一显示区012和第二显示区011的交界处，第一数据线71(data1)具有拐角。在第一显示区012，多条第三信号线的位于相邻两个像素4a(包括三个第一子像素41)之间的部分，相对于其位于像素4a的部分收拢。这样设计有利于增大开口31的面积，提高本公开实施例提供的显示基板1A的环境光透过率。在第二显示区011，多条第三信号线沿第一方向D1延伸，且多条第三信号线相互平行，不做收拢设计。
如图5H所示，图5H为上述的有源半导体层41a、第一导电层81、第二导电层82和第三导电层83的层叠位置关系的示意图。示例性地，图5H示意出的是位于第二显示区011的一个子像素42中的像素驱动电路的结构图(例如对应图5G中的区域G)，可同时参考图8。
在一些实施例中，第二数据线72(data)通过绝缘层中的至少一个过孔K与有源半导体层41a中的数据写入晶体管T2的源极区域相连。第二电源子线62(VDD2)通过绝缘层中的至少一个过孔K与有源半导体层41a中对应的第一发光控制晶体管T4的源极区域相连。第二电源子线62(VDD2)通过绝缘层中的至少一个过孔K与第二导电层82中的存储电容Cst的第一极板c1相连。第二电源子线62(VDD2)还通过绝缘层中的至少一个过孔K与第二导电层82中的电压信号线82b(VD)相连。
在一些实施例中，如图5H所示，第三导电层83还包括第一连接部83a、第二连接部83b和第三连接部83c。第一连接部83a的一端通过绝缘层中的至少一个过孔K与有源半导体层41a中对应的阈值补偿晶体管T3的漏极区域相连，第一连接部83a的另一端通过绝缘层中的至少一个过孔K与第一导电层81中的驱动晶体管T1的栅极(即存储电容Cst的第一极板c1)相连。第二连接部83b的一端通过绝缘层中的一个过孔K与初始化信号线82a(vinit)相连，第二连接部83b的另一端通过绝缘层中的至少一个过孔K与有源半导体层41a中的第二复位晶体管T7的漏极区域相连。第三连接部83c通过绝缘层中的至少一个过孔K与有源半导体层41a中的第二发光控制晶体管T5的漏极区域相连。
需要说明的是，本公开对第一子像素41和第二子像素42中像素驱动电 路21的结构不做限定，以上仅是第二子像素42中的像素驱动电路21的各晶体管和存储电容的连接关系的一种示例，第一子像素41中的像素驱动电路21的各晶体管和存储电容的连接关系可参考上述描述，但并不限于此。
在一些实施例中，在第一显示区012，每个第一子像素41包括一个发光器件22，示例性地，如图2所示，在第一遮光层31具有多个阵列排布的开口31a，多个第一子像素41以三个第一子像素41为一组，形成多个阵列排布的像素4a，在每四个开口31a之间设置一个像素4a的情况下，一个像素4a所包括的三个子像素41中的发光器件22被配置为分别发出蓝光、红光和绿光。
在第二显示区011，每个第二子像素42包括一个发光器件，第二显示区011的多个发光器件被配置为发出蓝光、红光或绿光。
在一些实施例中，如图9A所示，在第一电源子线52为单层的情况下，称第一电源子线52和薄膜晶体管的源极和漏极所在的膜层为第一源漏层(SD1层)；在第一电源子线52为双层(包括第三子层和第四子层)的情况下，称第一电源子线52的第三子层和薄膜晶体管的源极和漏极所在的膜层为第一源漏层(SD1层)，称第一电源子线52的第四子层所在的膜层为第二源漏层(SD2层)。显示基板1A还包括设置于薄膜晶体管TFT和发光器件22之间的平坦层24，及设置于平坦层24远离衬底基板1一侧的像素界定层25，具体地，如图9A所示，平坦层24设置于第一源漏层远离衬底基板1的一侧，平坦层24中具有贯穿该平坦层24的过孔，以实现薄膜晶体管与发光器件22的电连接。像素界定层25中界定出多个开孔，多个开孔用于设置多个发光器件22，以定义出发光区的大小。
示例性地，发光器件22包括阳极221、阴极223和设置于阳极221和阴极223之间的发光层222。本公开实施例中阳极221与阴极223之间的相对位置关系包括但不限于下述两种情况：
一种是，如图9A和9B所示，阴极223相对于阳极221更远离衬底基板1。即，当衬底基板1水平放置时，在垂直于衬底基板1且由靠近衬底基板1指向远离衬底基板1的方向上，阴极223在上层，阳极221在下层。薄膜晶体管TFT的源极216通过贯穿平坦层24的过孔与阳极221电连接。
另一种是，阴极相对于阳极更靠近衬底基板。即，当衬底基板水平放置时，在垂直于衬底基板1且由靠近衬底基板指向远离衬底基板的方向上，阴极在下，阳极在上。
在一些示例中，如图9A和9B所示，显示基板1A还包括：设置于发光器件22远离衬底基板1的一侧的封装层26，示例性地，封装层26包括：第 一无机封装层261、有机封装层262和第二无机封装层263。其中，第一无机封装层261设置于阴极223远离衬底基板1一侧，有机封装层262设置于第一无机封装层261远离衬底基板1的一侧，第二无机封装层263设置于有机封装层262远离衬底基板1的一侧。
在一些实施例中，请参见图12和图13，将显示基板1A的俯视图进行简化，仅示意出多个第一子像素41和多个第二子像素42的排布。可以这样理解，图2所示的显示基板1A中的多个第一子像素41和多个第二子像素42的排布，使以子像素中所包括的像素驱动电路21的布局为准进行示意，图12和图13所示的显示基板1A中的多个第一子像素41和多个第二子像素42的排布，是以子像素中所包括的发光器件(发光器件的发光区)的排布进行示意。图2和图12、图13可以进行对照。
如图12所示，用于发出相同色光的一些子像素中，位于第一显示区012的每个第一子像素41的面积，大于位于第二显示区011的每个第二子像素42的面积。需要说明的是，此处所述的每个第一子像素41的面积，以及每个第二子像素42的面积指的是子像素中所包括的发光器件22的发光区的面积。而第一子像素41中的像素驱动电路21和每个第二子像素42中的像素驱动电路21在衬底基板1上的正投影的面积是相等的。
例如，用于发出红光的一些子像素中，位于第一显示区012的每个第一子像素41的面积，大于位于第二显示区011的每个第二子像素42的面积。用于发出绿光的一些子像素中，位于第一显示区012的每个第一子像素41的面积，大于位于第二显示区011的每个第二子像素42的面积。用于发出蓝光的一些子像素中，位于第一显示区012的每个第一子像素41的面积，大于位于第二显示区011的每个第二子像素42的面积。
本公开实施例提供的阵列基板1A，由于第一显示区012的第一子像素41的分布密度小于第二显示区011的第二子像素42的分布密度，第一显示区012在为上述多个第一子像素41提供空间，以及为信号走线(例如，多条第一电源子线52和多条第一数据线71，多条栅线等)提供空间的同时，还可预留大量的空间，这些预留的空间与第一遮光层31所具有的多个开口31a相对应。这些预留的空间可用于透过环境光(例如红外光)，使得第一显示区012既可以正常显示图像，又可以透过环境光，从而可避免在阵列基板1A上开设安装前置光学部件300的孔，实现全屏显示。同时，由于用于发出相同色光的一些子像素中，位于第一显示区012的第一子像素41的面积，大于位于第二显示区011的第二子像素42的面积，这样就可对第一显示区012的第一子像 素41的像素分布密度减少而导致的发光强度较低进行补偿，降低第一显示区012和第二显示区011的亮度差异。
在一些实施例中，上述多个子像素中，每个子像素的形状可为矩形、菱形或其它多边形，当然，还可以是其它规则图形，在此不再一一列举。
可以理解的是，如图13所示，每个子像素具有至少一个子像素开口200b，例如发出红光和蓝光的第二子像素42和第一子像素41具有一个子像素开口200b，发出绿光的第二子像素42具有两个子像素开口200b。
在一些实施例中，发出相同色光的沿第一方向D1相邻的任两个子像素的子像素开口200b之间的间隔d3相等。
请参阅图13，以发出蓝光的第一子像素41的子像素开口200b和第二子像素42的子像素开口200b为例，对“发出相同色光的沿第一方向D1相邻的任两个子像素开口之间的间隔d3相等”的含义进行说明，其含义包括三层：
一、发出蓝光B的沿第一方向D1相邻的任两个第一子像素41的子像素开口200b之间的间隔d3相等。
二、发出蓝光B的沿第一方向D1相邻的任两个第二子像素42的子像素开口200b之间的间隔d3相等。
三、发出蓝光B的沿第一方向D1相邻的任两个第二子像素42的子像素开口200b之间的间隔d3，与发出蓝光的沿第一方向D1相邻的任两个第一子像素41的子像素开口200b之间的间隔d3相等。
这样，在将用于发出某一色光(例如蓝色)的有机电致发光材料，形成于像素显示基板1A的像素界定层25以形成发光功能层222时，有机电致发光材料不易形成在错误的子像素开口，从而改善混色问题。
需要解释的是，由上面对发光器件22的描述可知，发光器件22包括阳极221、发光层222以及阴极223。其中，像素界定层25设置于阳极221远离衬底基板1的一侧且具有与阳极221重叠的子像素开口。有机电致发光材料形成于像素显示基板1A的子像素开口以形成发光功能层222。由于，发出相同色光的沿第二方向D2相邻的任两个子像素开口之间的间隔d3相等，在形成发光功能层222时，有机电致发光材料不易形成在错误的像素开口，从而改善混色问题。
请参阅图12和图13，可以理解的是，第二显示区011和第一显示区012具有第一交界处A(虚线A)。
在第一显示区012，最靠近第一交界处A的各第一子像素41，用于发出第一色光，例如绿光。
在第二显示区011，最靠近第一交界处A的用于发出第一色光(例如绿光)的各第二子像素42的子像素开口200b的个数，小于在第二显示区011，其他用于发出第一色光(例如绿光)的每个第二子像素42的子像素开口200b的个数。这样可以有利于减弱第一交界处A附近的光色差异。
例如，如图13所示，在第一显示区012，最靠近第一交界处A的各第一子像素41，用于发出绿光。在第二显示区011，最靠近第一交界处A的用于发出绿光的各子像素200的子像素开口200b的个数为一个。然而，在第二显示区011，其他用于发出绿光的每个第二子像素42的子像素开口200b的个数为2个。这样可以有利于减弱第一交界处A附近的光色差异。
如图6B所示，本公开的实施例所提供一种显示装置3A中，还包括设置显示基板1A的显示层2远离衬底基板1一侧的盖板9。
前置光学部件300设置在显示面板2A的远离其显示面01a的一侧(即显示面板1A的背面)，前置光学部件300在显示基板2A上的正投影位于所述第一显示区012内。
此处需要解释的是，虽然前置光学部件300是设置在显示基板1A的背面，但是其相应的接收面是朝向显示基板1A的显示面01a的，以实现其前置功能。
上述的接收面是指，当前置光学部件300包括前置摄像单元时，接收面即为前置摄像单元的镜头；当前置光学部件300包括红外传感单元时，接收面即为红外传感单元的传感面。
上述前置光学部件300可以包括前置摄像单元，当然，也可以包括红外检测单元300’。
本公开的实施例提供的显示装置3A与本公开的实施例提供的显示基板1A的所能达到的有益效果相同，此处不再赘述。
本公开实施例提供的显示装置3A可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是图画的图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多种电子装置包括但不限于移动电话、无线装置、个人数据助理(Portable Android Device，缩写为PAD)、手持式或便携式计算机、GPS(Global Positioning System，全球定位系统)接收器/导航器、相机、MP4(全称为MPEG-4 Part 14)视频播放器、摄像机、游戏控制台、手表、时钟、计算器、电视监视器、平板显示器、计算机监视器、汽车显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结 构(例如，对于显示一件珠宝的图像的显示器)等。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种显示基板，具有显示区和围绕所述显示区的周边区，所述显示区包括第一显示区；
    所述显示基板包括：
    衬底基板；
    设置于所述衬底基板一侧的第一遮光层，所述第一遮光层位于所述第一显示区，所述第一遮光层具有多个阵列排布的开口；
    设置于所述第一遮光层远离所述衬底基板一侧的多个第一子像素，所述多个第一子像素位于所述第一显示区，所述多个第一子像素在所述衬底基板的正投影与所述开口在所述衬底基板的正投影不交叠；
    第一电源线，包括第一电源总线和多条第一电源子线；所述第一电源总线的至少一部分位于所述周边区中靠近所述第一显示区一侧的区域；所述多条第一电源子线位于所述第一显示区，且与所述第一电源总线电连接，所述多条第一电源子线被配置为向所述多个第一子像素提供第一电源信号，所述多条第一电源子线在所述衬底基板的正投影与所述开口在所述衬底基板的正投影不交叠；
    其中，所述第一遮光层与所述第一电源线电连接。
  2. 根据权利要求1所述的显示基板，还包括：
    设置于所述第一电源线和所述第一遮光层之间的至少一层绝缘薄膜，所述至少一层绝缘薄膜中设有贯通所述至少一层绝缘薄膜的多个过孔；
    所述第一电源线通过所述多个过孔与所述第一遮光层电连接。
  3. 根据权利要求2所述的显示基板，其中，所述第一遮光层还位于所述周边区，所述多个过孔包括位于所述周边区的多个第一过孔，所述第一遮光层通过所述多个第一过孔与所述第一电源总线电连接。
  4. 根据权利要求3所述的显示基板，其中，所述多个第一过孔包括具有不同孔深的至少两种第一过孔。
  5. 根据权利要求4所述的显示基板，其中，所述多个第一过孔包括至少一个第一过孔组，每个第一过孔组包括至少一个第一过孔列；每个第一过孔列中的各第一过孔的孔深不同。
  6. 根据权利要求5所述的显示基板，其中，所述第一过孔组的数量为多个；每个第一过孔组所包括的第一过孔列的数量为多个；
    所述多个第一过孔组沿第一方向排布；
    所述每个第一过孔组中的多个第一过孔列沿第一方向排布，且各所述第一过孔列中孔深相同的第一过孔沿第一方向排成一排。
  7. 根据权利要求3～6任一项所述的显示基板，其中，所述多个过孔还包括位于所述第一显示区的多个第二过孔，所述第一遮光层通过所述多个第二过孔与所述多条第一电源子线电连接。
  8. 根据权利要求7所述的显示基板，其中，所述多个第二过孔在所述第一显示区均匀分布。
  9. 根据权利要求8所述的显示基板，其中，在所述第一遮光层的每四个开口之间的位置设置有三个所述第一子像素，所述三个第一子像素组成一个像素，一个所述像素的位置至少对应一个第二过孔。
  10. 根据权利要求2～9中任一项所述的显示基板，还包括：位于所述第一遮光层和所述多个第一子像素之间的第一绝缘层；
    所述多个第一子像素中的至少一个第一子像素包括薄膜晶体管和存储电容；
    所述薄膜晶体管包括：
    位于所述第一绝缘层远离所述衬底基板一侧的有源层；
    位于所述有源层远离所述衬底基板一侧的第一栅绝缘层；
    位于所述第一栅绝缘层远离所述衬底基板一侧的栅极；
    位于所述栅极远离所述衬底基板一侧的第二栅绝缘层；
    位于所述第二栅绝缘层远离所述衬底基板一侧的层间绝缘层；
    位于所述层间绝缘层远离所述衬底基板一侧的源极和漏极；
    所述存储电容包括第一极板和第二极板，所述第一极板和所述栅极位于同一层，所述第二极板位于所述第二栅绝缘层和所述层间绝缘层之间。
  11. 根据权利要求10所述的显示基板，其中，所述至少一层绝缘薄膜包括所述第一绝缘层、所述第一栅绝缘层、所述第二栅绝缘层和所述层间绝缘层中的至少一者。
  12. 根据权利要求10或11所述的显示基板，其中，所述第一电源总线包括第一子层和第二子层，所述第一子层和所述第二子层通过第三过孔电连接。
  13. 根据权利要求10～12中任一项所述的显示基板，其中，所述多个第一电源子线中的至少一个第一电源子线包括第三子层和第四子层，所述第三子层和所述第四子层通过第四过孔电连接。
  14. 根据权利要求1～13任一项所述的显示基板，其中，所述显示区还包括第二显示区；所述第二显示区位于所述第一显示区远离所述第一电源线的 一侧；
    所述显示基板还包括：
    多个第二子像素，位于所述第二显示区；
    第二电源线，包括第二电源总线和多条第二电源子线；所述第二电源总线的至少一部分位于所述周边区中靠近所述第二显示区一侧的区域，所述多条第二电源子线位于所述第二显示区，且与所述第二电源总线电连接，所述多条第二电源子线被配置为向所述多个第二子像素提供第二电源信号。
  15. 根据权利要求14所述的显示基板，其中，所述多个第二子像素的分布密度大于所述多个第一子像素的分布密度。
  16. 根据权利要求14或15所述的显示基板，其中，所述第一电源信号与所述第二电源信号相同，或者，所述第一电源信号与所述第二电源信号不同。
  17. 根据权利要求16所述的显示基板，其中，在所述第一电源信号与所述第二电源信号不同的情况下，所述第一电源信号小于所述第二电源信号。
  18. 根据权利要求14～17中任一项所述的显示基板，还包括，设置于所述衬底基板一侧的第二遮光层，所述第二遮光层位于所述第二显示区，所述第二遮光层与所述第一遮光层位于同层；
    所述第二遮光层与所述第二电源线电连接。
  19. 一种显示装置，其中，包括：
    如权利要求1～18中任一项所述的显示基板；
    设置在所述显示基板的远离其显示面的一侧的前置光学部件，所述前置光学部件在所述显示基板上的正投影位于所述第一显示区内。
  20. 根据权利要求19所述的显示装置，其中，所述前置光学部件包括：红外检测单元。
PCT/CN2020/089723 2020-05-12 2020-05-12 显示基板及显示装置 Ceased WO2021226817A1 (zh)

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