WO2021232411A1 - 显示基板、显示面板以及显示装置 - Google Patents

显示基板、显示面板以及显示装置 Download PDF

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Publication number
WO2021232411A1
WO2021232411A1 PCT/CN2020/091833 CN2020091833W WO2021232411A1 WO 2021232411 A1 WO2021232411 A1 WO 2021232411A1 CN 2020091833 W CN2020091833 W CN 2020091833W WO 2021232411 A1 WO2021232411 A1 WO 2021232411A1
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WIPO (PCT)
Prior art keywords
line
signal
transistor
display
driving signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/091833
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English (en)
French (fr)
Inventor
张猛
韩林宏
张振华
刘庭良
宋永杰
杨慧娟
姜晓峰
屈忆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to PCT/CN2020/091833 priority Critical patent/WO2021232411A1/zh
Priority to CN202080000808.3A priority patent/CN113973506B/zh
Priority to EP20900747.5A priority patent/EP4002337A4/en
Priority to US17/281,487 priority patent/US11600689B2/en
Publication of WO2021232411A1 publication Critical patent/WO2021232411A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates

Definitions

  • At least one embodiment of the present disclosure relates to a display substrate, a display panel, and a display device.
  • AMOLED Active Matrix Organic Light-Emitting Diode
  • a pixel circuit is provided in the display area
  • a gate driving circuit such as a GOA driving circuit is provided in the frame area to provide driving signals to the pixel circuit.
  • At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, a pixel circuit, and a driving circuit.
  • the base substrate includes a display area and a non-display area, the display area includes display pixels, the non-display area at least partially surrounds the display area;
  • the pixel circuit includes a power supply line, the power supply line is configured to provide the display pixel Power supply voltage;
  • a driving circuit is at least partially located in the non-display area, and includes a driving signal line configured to provide a driving signal to the pixel circuit;
  • the power line includes a narrow line part and the A wide line part connected by a narrow line part, the orthographic projection of the narrow line part on the base substrate and the orthographic projection of the drive signal line on the base substrate at least partially overlap, and the narrow line part
  • the line width of is smaller than the line width of the wide line portion;
  • the display substrate has a first side for display and a second side opposite to the first side, and includes Bending area, the power line
  • the orthographic projection of the first part of the driving signal line on the base substrate and the narrow line portion on the base substrate The orthographic projection of the second part of the driving signal lines at least partially overlaps the orthographic projection of the second portion of the driving signal lines on the base substrate and the orthographic projection of the wide line portion on the base substrate at least partially overlap,
  • the number of the second part of the drive signal lines is less than the number of the first part of the drive signal lines; or, the orthographic projection of the drive signal line on the base substrate and the wide line portion
  • the orthographic projections on the base substrate do not overlap.
  • the driving signal line includes a bent portion on the second side, and the bent portion includes a horizontal portion and a vertical portion that are connected to each other;
  • the extension direction of the part is substantially the same as the extension direction of the power line, and the lateral part and the power line overlap in a direction perpendicular to the base substrate.
  • the display substrate provided by at least one embodiment of the present disclosure further includes: a first power circuit and a second power circuit.
  • the first power supply circuit is located on the second side of the display substrate and is configured to provide the power supply voltage to the power line;
  • the second power supply circuit is located on the second side of the display substrate and is configured to provide all the power to the drive circuit.
  • the driving signal is located on the second side of the display substrate and is configured to provide all the power to the drive circuit.
  • the power line is connected to and drawn from the first power circuit, and the driving signal line is connected to the second power circuit And lead out from the second power circuit; the position where the power line is drawn from the first power circuit is located at a position close to the edge of the display substrate where the drive signal line is drawn from the second power circuit side.
  • the wide line portion includes a first portion and a second portion; the narrow line portion has a first end and a second end in the extending direction of the power cord The first part is connected to the first end of the narrow line part, and the second part is connected to the second end of the narrow line part.
  • the line width of the narrow line portion is less than or equal to half of the line width of the wide line portion.
  • the line width of the power line is greater than the line width of the driving signal line.
  • the line width of the narrow line portion of the power line is greater than the line width of the driving signal line.
  • the display substrate has a first side for display and a second side opposite to the first side; the display substrate includes an edge of the base substrate
  • the power line and the drive signal line extend from the first side through the bending area 4 to the second side; the narrow line portion of the power line is located at the Display the second side of the substrate.
  • the display substrate has a first side for display and a second side opposite to the first side, and the narrow line portion is located on the second side of the display substrate.
  • the non-display area on one side.
  • the power cord includes a first power cord and a second power cord.
  • the first power supply line is configured to provide a first power supply voltage to the display pixel;
  • the second power supply line is configured to provide a second power supply voltage to the display pixel;
  • the second power supply voltage is opposite to the first power supply voltage Polarity; at least one of the first power line and the second power line includes the narrow line portion and the wide line portion.
  • the driving circuit includes a gate driving circuit; the gate driving circuit includes a plurality of cascaded shift registers and trigger signal lines.
  • a plurality of cascaded shift registers includes a first shift register, a second shift register, and an Nth shift register, where N is a positive integer, and each shift register includes a signal input terminal and a signal output terminal
  • the trigger signal line is connected to the signal input end of the first shift register and is configured to provide a trigger signal to the first shift register; the drive signal line includes the trigger signal line.
  • the driving signal includes a scan driving signal;
  • the trigger signal line includes a scan trigger signal line, and the scan trigger signal line is configured to provide the first shift register
  • the trigger signal is scanned to make the shift register output the scan driving signal, and the scan driving signal is supplied to the pixel circuit.
  • the gate driving circuit further includes a gate scan line, and the gate scan line is connected to the signal output terminal of the shift register and is configured to The scan driving signal output by the shift register is provided to the pixel circuit;
  • the pixel circuit includes: a data line, a light emitting device, and a first transistor, a second transistor, and a storage capacitor located in a display pixel.
  • the data line is configured to provide a data signal to the display pixel;
  • the light emitting device includes a first electrode and a second electrode, and the first power line is connected to the first electrode to receive the first power voltage;
  • the gate of the transistor is connected to the gate scan line to receive the scan driving signal, the first electrode of the first transistor is connected to the data line to receive the data signal, and the second electrode of the first transistor is connected to The gate of the second transistor is connected, the first electrode of the second transistor is connected to the second power line to receive the second power voltage, and the second electrode of the second transistor is connected to the first electrode of the light emitting device.
  • the two electrodes are connected to receive the second power supply voltage; the first electrode of the storage capacitor is connected to the gate of the second transistor, and the second electrode of the storage capacitor is connected to the second power line.
  • the drive signal further includes a light emission control drive signal;
  • the trigger signal line further includes a light emission control trigger signal, and the light emission control trigger signal line is configured to transmit to the first
  • the shift register provides a light emission control trigger signal to make the shift register output the light emission control drive signal, and the light emission control drive signal is provided to the pixel circuit.
  • the scan drive signal includes a first scan drive signal and a second scan drive signal
  • the light emission control drive signal includes a first light emission control drive signal and a second light emission control drive signal
  • the driving signal and the reset driving signal are the second light emission control driving signal
  • the driving signal further includes a reset driving signal
  • the gate driving circuit further includes: a first scan line, a second scan line, a first light emission control line, and a second Luminous control line.
  • the first scan line and the second scan line are connected to the signal output terminal of the shift register and are configured to provide the first scan driving signal and the second scan driving signal output from the shift register to the Pixel circuit; a first light-emitting control line and a second light-emitting control line are connected to the signal output end of the shift register and are configured to output the first light-emitting control driving signal and the first light-emitting control drive signal output from the shift register Two light-emitting control driving signals are provided to the pixel circuit; the pixel circuit includes: a data line, a light-emitting device, an initial signal line, and a first transistor, a second transistor, a third transistor, and a fourth transistor located in each pixel. Fifth transistor, sixth transistor, seventh transistor and storage capacitor.
  • the data line is configured to provide a data signal to the display pixel;
  • the light emitting device includes a first electrode and a second electrode, and the first power line is connected to the first electrode to receive the first power voltage; an initial signal line, Configured to provide an initial signal to the display pixel;
  • the gate of the first transistor is connected to a first node;
  • the first electrode of the first transistor is connected to the second node, and the second electrode of the first transistor is connected to The third node is connected;
  • the gate of the second transistor is connected to the first scan line to receive the first scan driving signal, and the first electrode of the second transistor is connected to the data line to receive the Data signal, the second electrode of the second transistor is connected to the second node;
  • the gate of the third transistor is connected to the second scan line to receive the second scan driving signal, the third
  • the first electrode of the transistor is connected to the first node, the second electrode of the third transistor is connected to the third node;
  • the first electrode of the storage capacitor is connected to the first node,
  • the driving signal line further includes the initial signal line, and the initial signal line extends from the non-display area to the display area.
  • the drive signal line further includes a clock signal line
  • the clock signal line is configured to provide a clock control drive signal to each of the shift registers so that the clock signal Provided to the pixel circuit.
  • the driving signal line further includes: a low-level signal line and a high-level signal line.
  • the low-level signal line is configured to provide a first voltage drive signal to each of the shift registers;
  • the high-level signal line is configured to provide a second voltage drive signal to each of the shift registers, and the second voltage is greater than The first voltage.
  • each of the first power supply line and the second power supply line respectively includes a first power supply sub-line and a second power supply sub-line
  • the first power supply sub-line and the second power supply sub-line respectively include the narrow line portion and the wide line portion
  • the driving signal line includes a first signal sub-line and a second signal sub-line
  • the first signal sub-wiring line and the second signal sub-wiring line respectively extend to two opposite sides of the display area
  • the sub-wiring is at least partially overlapped in a direction perpendicular to the base substrate, and the narrow line portion of the second power sub-wiring and the second signal sub-wiring are in a direction perpendicular to the base substrate
  • the upper part overlaps at least partially.
  • the power line enters the display area from the first side of the display area that is close to the first power circuit; or, the power line enters the display area from the The side surface of the display area intersecting the first side of the display area enters the display area.
  • At least one embodiment of the present disclosure provides another display panel, which includes any display substrate provided by the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure provides another display device, and the display device includes any display panel provided in the embodiments of the present disclosure.
  • FIG. 1A is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 1B is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 2A is a partial schematic diagram of FIG. 1A including a first power line, a second power line, and a driving circuit;
  • Fig. 2B is a partial enlarged schematic diagram of Fig. 2A;
  • 2C is a partial schematic diagram of another display substrate provided by an embodiment of the present disclosure.
  • 2D is a schematic cross-sectional view of the display area of the display substrate in FIG. 2A along the line A-A';
  • 3A is a partial enlarged schematic diagram of the driving signal line in FIG. 1A;
  • 3B is a schematic diagram of a clock signal line and multiple shift registers
  • 4A is an equivalent circuit diagram of a pixel circuit of a display substrate provided by an embodiment of the present disclosure
  • 4B is an equivalent circuit diagram of another pixel circuit of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 4C shows the relationship between the data signal Vdata and the data signal reading time T in an ideal state
  • FIG. 4D shows the relationship between the data signal Vdata and the data signal reading time T in the actual state
  • FIG. 5 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, a pixel circuit, and a driving circuit.
  • the base substrate includes a display area and a non-display area, the display area includes display pixels, the non-display area at least partially surrounds the display area;
  • the pixel circuit includes a power supply line, the power supply line is configured to provide the display pixel Power supply voltage;
  • a driving circuit is at least partially located in the non-display area, and includes a driving signal line configured to provide a driving signal to the pixel circuit;
  • the power line includes a narrow line part and the A wide line part connected by a narrow line part, the orthographic projection of the narrow line part on the base substrate and the orthographic projection of the drive signal line on the base substrate at least partially overlap, and the narrow line part
  • the line width of is smaller than the line width of the wide line portion;
  • the display substrate has a first side for display and a second side opposite to the first side, and includes Bending area, the power line
  • FIG. 1A is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure.
  • FIG. 2A is a partial schematic diagram of FIG. 1A including the first power supply line, the second power supply line, and the driving circuit.
  • the second power supply line also includes the narrow line part is taken as an example.
  • the features described below are The features in FIG. 2A, except for the features and effects related to the second power cord, are all applicable to the embodiment shown in FIG. 1B.
  • the display substrate 10 includes: a base substrate 1, a pixel circuit, and a driving circuit.
  • the base substrate 1 includes a display area 11 and a non-display area 12.
  • the display area 11 includes a plurality of display pixels, for example, the plurality of display pixels are arranged in an array; the non-display area 12 surrounds the display area 11. Of course, in other embodiments, the non-display area 12 may also surround a part of the display area 11.
  • the pixel circuit includes a power supply line, for example, the power supply line includes a first power supply line 31 and a second power supply line 32.
  • the first power line 31 is configured to provide a first power voltage to the display pixels
  • the second power line 32 is configured to provide a second power voltage to the display pixels.
  • the second power voltage and the first power voltage have opposite polarities. For example, the polarity of the first power supply voltage is negative, and the polarity of the second power supply voltage is positive.
  • the first power line 31 includes a narrow line portion 312 and a wide line portion 3111/3112 connected to the narrow line portion 312.
  • a part of the driving circuit is located in the non-display area 12, and the driving circuit includes a driving signal line 20 that is configured such that the driving signal is provided to the pixel circuit.
  • the orthographic projection of the narrow line portion 312 of the first power cord 31 on the base substrate 1 and the orthographic projection of the drive signal 20 line on the base substrate 1 at least partially overlap, for example, the orthographic projection of the first power cord 31 Part or all of the orthographic projection of the narrow line portion 312 on the base substrate 1 overlaps with the orthographic projection of the drive signal line 20 on the base substrate 1, and the line width w12 of the narrow line portion 311 of the first power line 31 is smaller than the first power line 31.
  • the wide line portion 3111/3112 of a power line 31 has a line width w11.
  • the display substrate has a first side 101 (ie, the display side) for display and a second side 102 opposite to the first side 101; the display substrate includes a bending area 4 located at the edge of the base substrate 1.
  • the first power line 31, the second power line 32, and the driving signal line 20 extend from the first side across the bending area 4 to the second side 102, that is, the portion below the bending area 4 in FIG. 1A is bent to display The second side of the substrate.
  • the narrow line portion of the first power supply line 31 and the narrow line portion of the second power supply line 32 are located on the second side of the display substrate.
  • the first side 101 and the second side 102 of the display substrate are substantially on the same plane, as shown in FIG. 1A and FIG.
  • the first side 101 is the side of the bending area 4 close to the display area 11
  • the second side 102 is the side of the bending area 4 away from the display area 11
  • the first side 101 and the second side The sides are respectively located on both sides of the bending zone 4 and are substantially opposite to each other in the same plane.
  • the circuit board carrying the narrow line portion and part of the driving circuit is folded to the back of the display side by bending the bending area 4, and the first side 101 and the second side 102 of the display substrate are respectively located
  • line width in the present disclosure refers to the width of the line in a direction perpendicular to the extending direction of the line.
  • the orthographic projection of the wide line portion 3111/3112 of the first power line 31 on the base substrate 1 and the orthographic projection of the drive signal line 20 on the base substrate 1 do not overlap.
  • the wide line portion of the first power line 31 includes a first portion 3111 and a second portion 3112; the narrow line portion 312 of the first power line 31 has a first end in the extending direction of the first power line And the second end, the first part 3111 is connected to the first end of the narrow line part 312, and the second part 3112 is connected to the second end of the narrow line part 312. Therefore, the line width of the portion of the first power line 31 that does not overlap with the driving signal line 20 is made as wide as possible, so as to reduce the resistance of the first power line 31 due to the reduction of the local line width as much as possible. In this way, the signal conduction in the first power line 31 is not affected as much as possible.
  • the line width of the narrow line portion 312 of the first power line 31 is less than or equal to one-half of the line width of the wide line portion of the first power line 31 to achieve a more ideal effect of reducing parasitic capacitance, such as the first part
  • the line width of 3111 is equal to the line width of the second portion 3112.
  • the line width of the first power line 31 is much larger than the line width of the driving signal line 21, for example, the line width of the narrow line portion 312 of the first power line 31 is larger than the line width of the driving signal line 21. That is, for example, the driving signal line 21 includes a plurality of different types of signal lines (the driving signal line 32 in FIG.
  • the first power line 31 is much greater than the line width of each of the plurality of different types of signal lines, and the line width of the narrow line portion 312 of the first power line 31 is greater than that of each of the plurality of different types of signal lines The line width of the signal line.
  • it is necessary not only to reduce the parasitic capacitance on the driving signal line 20 but also not to increase the resistance of the driving signal line 20 as much as possible.
  • the line width of the first power supply line 31 is much larger than the line width of the driving signal line 21, on the one hand, there is little room for reducing the line width; on the other hand, if the line width of the driving signal line 20 is reduced Wide, the effect of reducing the parasitic capacitance is very weak, but will obviously increase the resistance of the driving signal line 20, and still cause poor display effect. Therefore, in the area where the driving signal line 21 and the first power supply line 31 overlap, the line width of the first power supply line 31 is reduced without reducing the line width of the driving signal line 21.
  • the line width of the first power line 31 is greater than the line width of the second power line 32, so that compared to the second power line 32, the line width of the first power line 31 is smaller than that of the second power line 32 in the area overlapping with the driving signal line 20.
  • the reduction range can be greater, so as to achieve a greater effect of reducing parasitic capacitance.
  • the second power line 32 also drives the signal line 20 to intersect, that is, the second power line 32 has an overlap with the drive signal line 20 in the direction perpendicular to the base substrate 1.
  • the second power line 32 includes a narrow line portion 322 and a wide line portion 3211/3212 connected to the narrow line portion 322.
  • the orthographic projection of the narrow line portion 322 of the second power cord 32 on the base substrate 1 and the orthographic projection of the drive signal 20 line on the base substrate 1 at least partially overlap.
  • the narrow line portion 322 of the second power cord 32 is on the base substrate 1.
  • the orthographic projection on the base substrate 1 overlaps with the orthographic projection of the drive signal line 20 on the base substrate 1, and the orthographic projection of the wide line portion 3211/3212 of the second power line 32 on the base substrate 1 is the same as
  • the orthographic projection of the driving signal line 20 on the base substrate 1 does not overlap, and the line width w22 of the narrow line portion 322 of the second power line 32 is smaller than the line width w21 of the wide line portion 3211/3212 of the second power line 32.
  • the first power line is reduced since the line width of the narrow line portion 321 of the second power line 32 overlapping with the driving signal line 20 in the direction perpendicular to the base substrate 1 is reduced.
  • the parasitic capacitance formed between the driving signal line 20 and the second power line 32 is further reduced, thereby further improving the time efficiency of signal conduction on the driving signal line 20 to achieve
  • the designed ideal driving signal can be transmitted to the pixel circuit to further improve the display effect.
  • the second power line 32 may also include a narrow line portion 322 and a wide line portion 3211/3212 connected to the narrow line portion 322, and the first power line 31 overlaps the driving signal line 20
  • the part of the line width does not become narrow, that is, "at least one of the first power line and the second power line includes the narrow line portion and the wide line portion".
  • the first power supply line 31 is a VSS line connected to the pixel circuit
  • the second power supply line 32 is a VDD line connected to the pixel circuit.
  • FIG. 1B is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure.
  • the difference between this embodiment and FIG. 1A is that only the first power line 31 includes the narrow line portion and the wide line portion, which is not limited
  • the second power cord also includes the narrow line portion.
  • Other features are the same as those in the embodiment shown in FIG. 1A and will not be repeated.
  • the pixel circuit of each sub-pixel of the display area 11 of the display substrate includes a thin film transistor (TFT), a light emitting element 180, and a storage capacitor Cst.
  • the thin film transistor includes an active layer 120, a gate electrode 121, and source and drain electrodes 122/123;
  • the storage capacitor Cst includes a first electrode plate CE1 and a second capacitor electrode plate CE2.
  • the light-emitting element 180 includes a cathode 183, an anode 181, and a light-emitting layer 182 between the cathode 183 and the anode 181.
  • the anode 181 is electrically connected to one of the source and drain electrodes 122/123 of the thin film transistor TFT, such as the drain electrode 123.
  • the anode 181 and the drain 123 of the thin film transistor TFT may also be electrically connected through the transfer electrode.
  • the light-emitting element may be, for example, an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), and correspondingly, the light-emitting layer 182 is an organic light-emitting layer or a quantum dot light-emitting layer.
  • the first power line 31 is arranged in the same layer as the gate 121 and the first electrode plate CE1 of the storage capacitor Cst.
  • the structure arranged in the same layer can be formed by a patterning process at one time, thereby simplifying the manufacturing process of the display substrate 20.
  • the first power line 31 and the second plate CE2 of the storage capacitor Cst are arranged in the same layer.
  • each first power line 31 includes a first part provided on the same layer as the gate 121 and the first plate CE1 of the storage capacitor Cst, and a second part provided on the same layer as the second plate CE2 of the storage capacitor Cst,
  • the first part and the second part arranged in different layers are electrically connected through vias, so that the first part and the second part are connected in parallel to reduce the resistance of each first power line 31.
  • No via hole is provided at a position corresponding to the narrow line portion of the first power supply line 31.
  • the display area 11 further includes a first gate insulating layer 151 located between the active layer 120 and the gate 121, a second gate insulating layer 152 located above the gate 121, and an interlayer insulating layer 160.
  • the second gate insulating layer 152 is located between the first electrode plate CE1 and the second capacitor electrode plate CE2, so that the first electrode plate CE1, the second gate insulating layer 152 and the second capacitor electrode plate CE2 constitute a storage capacitor Cst.
  • the interlayer insulating layer 160 covers the second capacitor plate CE2.
  • the display area 11 further includes an insulating layer 113 (for example, a passivation layer) covering the pixel circuit and a first planarization layer 112.
  • the display area 201 further includes a pixel defining layer 170 for defining a plurality of sub-pixels, and spacers (not shown) on the pixel defining layer 170 and other structures. As shown in FIG. 2D, the display area 11 further includes an insulating layer 113 (for example, a passivation layer) covering the pixel circuit and a first planarization layer 112.
  • the display area 201 further includes a pixel defining layer 170 for defining a plurality of sub-pixels, and spacers (not shown) on the pixel defining layer 170 and other structures. As shown in FIG.
  • the insulating layer 113 is located above the source and drain electrodes 122/123 (for example, the passivation layer is formed of silicon oxide, silicon nitride, or silicon oxynitride), and the insulating layer 113 is located above There is a first planarization layer 112, and the anode 181 is electrically connected to the drain 123 through a via hole penetrating the first planarization layer 112 and the insulating layer 113.
  • the display substrate further includes an encapsulation layer 190
  • the encapsulation layer 190 includes a plurality of encapsulation sublayers 191/192/193.
  • the first encapsulation layer 291 and the first encapsulation sublayer 191 in the encapsulation layer 190 are provided on the same layer
  • the second encapsulation layer 292 is provided on the same layer as the second encapsulation sublayer 192 in the encapsulation layer 190
  • the third encapsulation layer 293 is provided on the same layer as the first encapsulation sublayer 191 in the encapsulation layer 190.
  • the third encapsulation sublayer 193 in the encapsulation layer 190 is arranged in the same layer.
  • both the first encapsulation layer 291 and the third encapsulation layer 293 may include inorganic encapsulation materials, such as silicon oxide, silicon nitride, or silicon oxynitride.
  • the second encapsulation layer 292 may include organic materials, for example, resin materials.
  • the multi-layer packaging structure of the display substrate can achieve a better packaging effect to prevent impurities such as water vapor or oxygen from penetrating into the interior of the display substrate.
  • the display substrate further includes a buffer layer 111 on the base substrate 210.
  • the buffer layer 111 serves as a transition layer to prevent harmful substances in the base substrate 1 from intruding into the interior of the display substrate. Entering the display area 11 can increase the adhesion of the film layer in the display substrate on the base substrate 1.
  • the material of the buffer layer 111 may include a single-layer or multi-layer structure formed of insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.
  • Fig. 2B is a partial enlarged schematic diagram of Fig. 2A.
  • the driving signal line in FIG. 2A includes a plurality of signal lines 20 spaced apart from each other.
  • a plurality of driving signal lines 20 extend from the binding area on the second side of the display substrate across the bending area 4 into the non-display area 12 on the first side of the display substrate for display, thereby forming the following as shown in FIG. 3A Of the various signal lines.
  • the plurality of driving signal lines 20 further includes an electrostatic shielding signal line ESD, and the electrostatic shielding signal line ESD is electrically connected to and grounded to at least part of the driving signal lines 20 of the plurality of driving signal lines 20, so as to be configured as Lead away the static electricity between the driving signal lines to prevent the negative effects of static electricity on signal transmission.
  • the multiple drive signal lines 20 also include data selector (MUX) signal lines MUX, which can save the number of wiring.
  • MUX data selector
  • MUX data selector
  • MUX data selector
  • a 1:2 MUX can be used, so that the number of data signal lines can be input before the effective display area. Save half the amount.
  • a 1:6 MUX may also be used, which is not limited in the embodiment of the present disclosure.
  • the driving signal line 20 includes a bent portion 21 on the second side 102, and the bent portion 21 includes a lateral portion 211 and a longitudinal portion 212 connected to each other.
  • the extension direction of the longitudinal portion 212 is substantially the same as the extension direction of the power cord, such as the first power cord 31, and the orthographic projection of the lateral portion 211 on the base substrate 1 is similar to that of the power cord, such as the first power cord 31, on the base substrate 1.
  • the orthographic projections overlap at least partially.
  • the longitudinal portion 212 extends across the bending zone 4 into the first side 101. In this way, reasonable wiring is realized, so that the driving signal line 20 extends from the second side 102 to the first side 101.
  • the display substrate further includes a first power supply circuit 5 and a second power supply circuit 6.
  • the first power supply circuit 5 is located on the second side of the display substrate and is configured to provide a power supply voltage to the power supply line, that is, provide a first power supply voltage to the first power supply line 31 and a second power supply voltage to the second power supply line 32.
  • the second power supply circuit 6 is located on the second side of the display substrate and is configured to provide the above-mentioned driving signal to the driving circuit.
  • the power lines (the first power line 31 and the second power line 32) are connected to and drawn from the first power circuit 5, and the driving signal line 20 is connected to the second power circuit 6. And it is led out from the second power supply circuit 6.
  • the position where the power lines (the first power line 31 and the second power line 32) are drawn from the first power circuit 5 is located on the side close to the edge of the display substrate where the drive signal line 20 is drawn from the second power circuit 6.
  • the portion of the first power line 31 located on the first side 101 surrounds a part of the display area 11, for example, in the upper area of the display area 11, the first power line 31 is closed.
  • the portions of the first power line 31 in the non-display area 12 on the left and right sides of the display area 11 are respectively located on the side of the driving signal line 201 and the driving signal line 202 close to the edge of the display substrate.
  • the driving signal line is closer to the display area 11 to reduce the length of the wire connecting the driving signal line to the display area, thereby improving the transmission efficiency of the driving signal, which is conducive to achieving a better display effect.
  • FIG. 2C is a partial schematic diagram of another display substrate provided by an embodiment of the present disclosure.
  • the embodiment shown in FIG. 2C has the following differences from the embodiment shown in FIG. 2B.
  • the orthographic projection of the first part of the driving signal line 20 on the base substrate 1 and the orthographic projection of the narrow line portion 321 on the base substrate 1 at least partially overlap, and the driving signal line 20
  • the orthographic projection of the second part of the drive signal line 2001 on the base substrate 1 and the orthographic projection of the wide line portion 3111 on the base substrate 1 at least partially overlap (in other embodiments, it may also overlap with the wide line portion 3112
  • the orthographic projection on the base substrate 1 at least partially overlaps, or at least partially overlaps with the orthographic projection of the wide line portion 3111 on the base substrate 1 and the orthographic projection of the wide line portion 3112 on the base substrate 1) ;
  • the number of driving signal lines 2001 in the second part is less than the number of driving signal lines in the first part, so as to reduce the parasitic capacitance on the driving
  • FIG. 3A is a partial enlarged schematic diagram of the driving signal line in FIG. 1A
  • FIG. 3B is a schematic diagram of a clock signal line and multiple shift registers.
  • the driving signal line 20 in FIG. 2A includes a plurality of signal lines spaced apart from each other.
  • the driving circuit includes a gate driving circuit such as a GOA driving circuit; the gate driving circuit includes a plurality of cascaded shift registers and trigger signal lines.
  • a plurality of cascaded shift registers includes a first shift register, a second shift register, and an Nth shift register, where N is a positive integer; each shift register includes a signal input terminal INT and a signal output terminal OUT.
  • the display substrate includes a plurality of display pixels arranged in an array, including a plurality of display pixel rows, and the plurality of display pixel rows correspond to a plurality of cascaded shift registers in a one-to-one correspondence.
  • the trigger signal line is connected to the signal input terminal of the first shift register and is configured to provide a trigger driving signal to the first shift register, and the first shift register outputs a corresponding driving signal from its signal output terminal OUT in response to the trigger signal,
  • the driving signal line includes the trigger signal line.
  • the drive signal output from the signal output terminal OUT of the previous stage shift register is fed to the signal input terminal INT of the next stage shift register as a trigger signal of the next stage shift register.
  • the driving signal includes a scan driving signal;
  • the trigger signal line includes a scan trigger signal line GSTV.
  • the scan trigger signal line GSTV is configured to provide a scan trigger signal to the first shift register to make the first shift register output a scan drive signal, for example, a scan drive signal is output from the signal output terminal OUT of the first shift register, and the scan drive signal is Provided to the pixel circuit.
  • the gate driving circuit further includes a gate scan line, for example, a gate scan line corresponding to each display pixel row.
  • the gate scan line is connected to the signal output terminals OUT of the plurality of shift registers and is configured to provide scan driving signals output from the plurality of shift registers to the pixel circuit.
  • the pixel circuit shown in FIG. 4A is a 2T1C pixel circuit.
  • the pixel circuit includes: a data line, a light emitting device, and a first transistor T1, a second transistor T2, and a storage capacitor C located in each pixel.
  • the data line is configured to provide a data signal to the display pixel, for example, the data signal is a data voltage signal.
  • the light emitting device L includes a first electrode and a second electrode.
  • the first power supply line 31 (VSS) is connected to the first electrode to receive the first power supply voltage; the gate of the first transistor T1 is connected to the gate scan line to receive the scan driving signal , The first electrode of the first transistor T1 is connected to the data line to receive the data signal, the second electrode of the first transistor T1 is connected to the gate of the second transistor T2, and the first electrode of the second transistor T2 is connected to the second power line 32 (VDD) is connected to receive the second power supply voltage, the second electrode of the second transistor T2 is connected to the second electrode of the light emitting device L to receive the second power supply voltage; the first electrode of the storage capacitor C is connected to the gate of the second transistor T2 Connected, the second pole of the storage capacitor C is connected to the second power line 32 (VDD).
  • the first transistor T1 and the second transistor T2 are both N-type transistors.
  • IGZO can be used as the active layer of the thin film transistor to reduce the size of the driving transistor and prevent leakage current.
  • the N-type transistor is turned on in response to a high-level signal.
  • FIG. 4C shows the relationship between the data signal Vdata and the data signal reading time T in an ideal state
  • FIG. 4D shows the relationship between the data signal Vdata and the data signal reading time T in the actual state.
  • the embodiments of the present disclosure reduce the parasitic capacitance on the driving signal lines such as the trace trigger signal line GSTV and the light emission control trigger signal line ESTV, the response time of the data signal Vdata can be reduced, that is, the rise time Tr and the fall time Tf can be reduced. , Making the actual data signal Vdata closer to the ideal state, so as to obtain a better display effect.
  • the second power supply circuit 6 provides the above-mentioned scan trigger signal for the scan trigger signal line, and the scan trigger signal is input to the first stage shift register through the scan trigger signal line, thereby passing the first stage shift
  • the register outputs a scan driving signal, and the scan driving signal is provided to the pixel circuit through the gate scan line.
  • the type of the pixel circuit is not limited to a 2T1C circuit, for example, it may also be any implementable type such as 4T2C, 7T1C, and so on.
  • the drive signal further includes a light emission control drive signal
  • the trigger signal line further includes a light emission control trigger signal line ESTV
  • the light emission control trigger signal line ESTV is configured to provide a light emission control trigger signal to the first shift register to enable
  • the first shift register outputs a light-emission control driving signal, and the light-emission control driving signal is provided to the pixel circuit.
  • a case where the display substrate adopts a 7T1C pixel circuit is taken as an example to illustrate this.
  • FIG. 4B is an equivalent circuit diagram of another pixel circuit of a display substrate provided by an embodiment of the present disclosure, and the pixel circuit shown in FIG. 4B is a 7T1C pixel circuit.
  • the scan driving signal includes a first scan driving signal and a second scan driving signal
  • the light control driving signal includes a first light emitting control driving signal, a second light emitting control driving signal, and a reset driving signal.
  • the gate driving circuit further includes a first scan line GATE1, a second scan line GATE2, a first light emission control line EM1, and a second light emission control line EM2. For each display pixel row, these four signal lines are correspondingly provided.
  • the first scan line GATE1 and the second scan line GATE2 are connected to the signal output terminal OUT of the shift register and are configured to The first scan driving signal and the second scan driving signal output by the shift register are provided to the pixel circuit; the first light-emitting control line EM1 and the second light-emitting control line EM2 are connected to the signal output terminal OUT of the shift register and are configured to The first light emission control driving signal and the second light emission control driving signal output by the shift register are provided to the pixel circuit.
  • the pixel circuit includes: a data line, a light emitting device L1, an initial signal line Vinit, and a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, The sixth transistor T6, the seventh transistor T7 and the storage capacitor C.
  • the data line is configured to provide a data signal Vdata to the display pixel, for example, the data signal Vdata is a data voltage;
  • the light emitting device L1 includes a first electrode and a second electrode, and the first power line 31 (VSS) is connected to the first electrode to receive the first power Voltage;
  • the initial signal line Vinit is configured to provide initial signals to the display pixels.
  • the gate of the first transistor T1 is connected to the first node N1; the first electrode of the first transistor T1 is connected to the second node N2, and the second electrode of the first transistor T1 is connected to the third node N3;
  • the gate is connected to the first scan line GATE1 to receive the first scan driving signal, the first electrode of the second transistor T2 is connected to the data line to receive the data signal Vdata, and the second electrode of the second transistor T2 is connected to the second node N2;
  • the gate of the third transistor T3 is connected to the second scan line GATE2 to receive the second scan driving signal, the first pole of the third transistor T3 is connected to the first node N1 (that is, the gate of the first transistor T1), and the third transistor
  • the second pole of T3 is connected to the third node N3;
  • the first pole of the storage capacitor C is connected to the first node N1 (that is, the gate of the first transistor T1), and the second pole of the storage capacitor C is connected to the second power line 32 ( VDD
  • the first to seventh transistors T1 to T7 are all N-type transistors.
  • IGZO can be used as the active layer of the thin film transistor to reduce the size of the driving transistor and prevent leakage current.
  • the N-type transistor is turned on in response to a high-level signal.
  • the pixel circuit may use a pixel circuit that mixes N-type and P-type transistors.
  • the third transistor T3, the sixth transistor T6, and the seventh transistor T7 use N-type transistors, and the remaining transistors use P-type transistors.
  • the driving signal line further includes an initial signal line Vinit, which extends from the non-display area 12 to the display area 11.
  • the initial signal line Vinit passes through the shift register.
  • the area extends to the display area 11 and is connected to the first electrode of the sixth transistor T6 and the first electrode of the seventh transistor T7 to provide it with an initial signal, that is, to the first electrode of the previous stage before proceeding to the next display stage.
  • the node N1 and the fourth node N4 are reset.
  • the drive signal line further includes a clock signal line
  • the clock signal line is configured to provide a clock control drive signal to each shift register so that the scan drive signal and the light emission control drive signal are provided to the pixels Circuit.
  • the clock signal line includes a first scan clock signal line GCLK1, a second scan clock signal line GCLK2, a first light-emission control clock signal line ECLK1, and a second light-emission control clock signal line ECLK2.
  • the second scan clock signal, the first light emission control clock signal, and the second light emission control clock signal are provided to the shift register, and the shift register outputs the first scan drive signal, the second scan drive signal, the first light emission control drive signal and
  • the second light-emitting control driving signals are provided to the pixel circuit through the first scan line, the second scan line, the first light-emitting control line, and the second light-emitting control line, respectively.
  • a scan drive signal, a second scan drive signal, a first light emission control drive signal, and a second light emission control drive signal are provided to the pixel circuit.
  • the driving signal line further includes a low-level signal line VGL and a high-level signal line VGH.
  • the low-level signal line VGL is connected to each shift register and is configured to provide the first voltage driving signal to each shift register;
  • the high-level signal line VGH is connected to each shift register and is configured to provide each shift register
  • the register provides a second voltage driving signal, and the second voltage is greater than the first voltage to provide a power supply voltage for the operation of each shift register.
  • the second power supply circuit 6 provides a scan trigger signal to the scan trigger signal line, provides a light emission control trigger signal to the light emission control trigger signal line, and provides a first scan clock signal line GCLK1 and a second scan clock signal.
  • the signal line GCLK2, the first light-emission control clock signal line ECLK1 and the second light-emission control clock signal line ECLK2 respectively provide clock control driving signals.
  • the second power supply circuit 6 provides a first voltage drive signal to the low-level signal line VGL and a second voltage drive signal to the high-level signal line VGH. The first voltage drive signal and the second voltage drive signal pass through the low voltage drive signal respectively.
  • the flat signal line VGL and the high-level signal line VGH are provided to the shift register.
  • driving signal lines are not limited to the types listed above, and may also include signal lines with other functions.
  • the types of driving signal lines listed in the above embodiments are only exemplary.
  • the first power supply line 31 includes a first power supply sub-line 3101 and a second power supply sub-line 3102, and the first power supply sub-line 3101 and the second power supply sub-line 3102 respectively include narrow lines.
  • the second power line 32 includes a first power sub-line 3201 and a second power sub-line 3202.
  • the first power sub-line 3201 and the second power sub-line 3202 respectively include a narrow The line portion 322 and the wide line portion 3211/3212.
  • the driving signal line 20 includes a first signal sub-line 201 and a second signal sub-line 202.
  • the first signal sub-line 201 and the second signal sub-line 202 respectively extend to two opposite sides of the display area 11;
  • the narrow line portion of the first power sub-line 3101 of a power line 31 and the narrow line portion of the first power sub-line 3201 of the second power line 32 and the first signal sub-line 201 are perpendicular to the base substrate 1.
  • the direction at least partially overlaps, the narrow line part of the second power sub-line 3102 of the first power line 31 and the narrow line part of the second power sub-line 3202 of the second power line 32 and the second signal sub-line 202 At least partially overlap in the direction perpendicular to the base substrate 1.
  • driving circuits are provided on both sides of the display area 11, and the power supply lines are narrowed in areas where the driving signal lines of the driving circuits on both sides overlap with the power supply lines.
  • the drive circuits on both sides are symmetrical.
  • the driving signal lines on both sides respectively include one or more of the above-mentioned trigger signal line, initial signal line, clock signal line, low-level signal line and high-level signal line.
  • the second signal sub-wiring 202 also includes multiple signal lines.
  • the first power supply line 31 and the second power supply line 32 enter the display area 11 from the first side of the display area 11 close to the first power supply circuit 5; or, in other embodiments, the first power supply The line 31 and the second power line 32 enter the display area 11 from the side surface of the display area 11 intersecting the first side of the display area 11.
  • the narrow line portion 312 of the first power line 31 and the narrow line portion 322 of the second power line 32 are located in the non-display area 12 on the first side of the display substrate. .
  • the display substrate provided by the embodiment of the present disclosure is an organic light emitting diode (OLED) display substrate.
  • OLED organic light emitting diode
  • At least one embodiment of the present disclosure further provides a display panel, which includes any display substrate provided by the embodiments of the present disclosure.
  • Fig. 6 is a schematic diagram of a display panel provided by an embodiment of the present disclosure. As shown in FIG. 6, the display panel 1000 provided by at least one embodiment of the present disclosure includes any display substrate 10 provided by the embodiment of the present disclosure. Other structures of the display panel 1000 can be designed according to specific needs using conventional techniques in the art, which are not limited in the present disclosure.
  • At least one embodiment of the present disclosure further provides a display device, which includes any display panel provided by the embodiments of the present disclosure.
  • the display device may be an organic light emitting diode (OLED) display device.
  • OLED organic light emitting diode
  • it can be a product such as a mobile phone, a tablet computer, a monitor, a notebook computer, and an ATM machine.
  • Other structures of the display device can be designed according to specific needs using conventional techniques in the art.

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)

Abstract

一种显示基板、显示面板以及显示装置。该显示基板包括衬底基板、像素电路和驱动电路。衬底基板包括显示区域和围绕显示区域的非显示区域，显示区域包括显示像素；像素电路包括配置为向显示像素提供电源电压的电源线；驱动电路至少部分位于非显示区域且包括配置为向像素电路提供驱动信号的驱动信号线；电源线包括窄线部和与窄线部连接的宽线部，窄线部在衬底基板上的正投影与驱动信号线在衬底基板上的正投影至少部分重叠，且窄线部的线宽小于宽线部的线宽；显示基板具有用于显示的第一侧和与第一侧相对的第二侧且包括位于衬底基板的边缘处的弯折区，电源线和驱动信号线从第一侧跨经弯折区而延伸至第二侧；电源线的窄线部至少位于该第二侧。

Description

显示基板、显示面板以及显示装置 技术领域
本公开至少一实施例涉及一种显示基板、显示面板以及显示装置。
背景技术
有源矩阵有机发光二极管(AMOLED，Active Matrix Organic Light-Emitting Diode)显示器与传统的液晶显示器(LCD)相比，具有自发光、广色域、高对比度、轻薄等优点，使其广泛应用于手机、平板电脑等领域，另外也广泛应用于智能手表等柔性可穿戴领域。通常在显示区设置有像素电路，在边框区设置有栅驱动电路例如GOA驱动电路以向像素电路提供驱动信号。
发明内容
本公开至少一实施例提供一种显示基板，该显示基板包括衬底基板、像素电路和驱动电路。衬底基板包括显示区域和非显示区域，所述显示区域包括显示像素，所述非显示区域至少部分围绕所述显示区域；像素电路包括电源线，所述电源线配置为向所述显示像素提供电源电压；驱动电路至少部分位于所述非显示区域，且包括驱动信号线，所述驱动信号线配置为使得驱动信号被提供至所述像素电路；所述电源线包括窄线部和与所述窄线部连接的宽线部，所述窄线部在所述衬底基板上的正投影与所述驱动信号线在所述衬底基板上的正投影至少部分重叠，且所述窄线部的线宽小于所述宽线部的线宽；所述显示基板具有用于显示的第一侧和与所述第一侧相对的第二侧，且包括位于所述衬底基板的边缘处的弯折区，所述电源线和所述驱动信号线从所述第一侧跨经所述弯折区从而延伸至所述第二侧；所述电源线的所述窄线部至少位于所述显示基板的第二侧。
例如，在本公开至少一实施例提供的显示基板中，所述驱动信号线中的第一部分驱动信号线在所述衬底基板上的正投影与所述窄线部在所述衬底基 板上的正投影至少部分重叠，所述驱动信号线中的第二部分驱动信号线在所述衬底基板上的正投影与所述宽线部在所述衬底基板上的正投影至少部分重叠，所述第二部分驱动信号线的条数少于与所述第一部分驱动信号线的条数；或者，所述驱动信号线在所述衬底基板上的正投影与所述宽线部在所述衬底基板上的正投影不重叠。
例如，在本公开至少一实施例提供的显示基板中，所述驱动信号线包括位于所述第二侧的弯折部分，所述弯折部分包括彼此连接的横向部分和纵向部分；所述纵向部分的延伸方向与所述电源线的延伸方向基本相同，所述横向部分与所述电源线在垂直于所述衬底基板的方向上交叠。
例如，本公开至少一实施例提供的显示基板还包括：第一电源电路和第二电源电路。第一电源电路位于所述显示基板的第二侧且配置为向所述电源线提供所述电源电压；第二电源电路位于所述显示基板的第二侧且配置为向所述驱动电路提供所述驱动信号。
例如，在本公开至少一实施例提供的显示基板中，所述电源线与所述第一电源电路连接且从所述第一电源电路引出，所述驱动信号线与所述第二电源电路连接且从所述第二电源电路引出；所述电源线从所述第一电源电路引出的位置位于所述驱动信号线从所述第二电源电路引出的位置的靠近所述显示基板的边缘的一侧。
例如，在本公开至少一实施例提供的显示基板中，所述宽线部包括第一部分和第二部分；所述窄线部在所述电源线的延伸方向上具有第一端和第二端，所述第一部分与所述窄线部的所述第一端连接，所述第二部分与所述窄线部的所述第二端连接。
例如，在本公开至少一实施例提供的显示基板中，所述窄线部的线宽小于等于所述宽线部的线宽的二分之一。
例如，在本公开至少一实施例提供的显示基板中，所述电源线的线宽大于所述驱动信号线的线宽。
例如，在本公开至少一实施例提供的显示基板中，所述电源线的窄线部的线宽大于所述驱动信号线的线宽。
例如，在本公开至少一实施例提供的显示基板中，所述显示基板具有用 于显示的第一侧和与第一侧相对的第二侧；所述显示基板包括位于所述衬底基板边缘处的弯折区，所述电源线和所述驱动信号线从所述第一侧跨经所述弯折区4从而延伸至所述第二侧；所述电源线的窄线部位于所述显示基板的第二侧。
例如，在本公开至少一实施例提供的显示基板中，所述显示基板具有用于显示的第一侧和与第一侧相对的第二侧，所述窄线部位于所述显示基板的第一侧的所述非显示区域。
例如，在本公开至少一实施例提供的显示基板中，所述电源线包括第一电源线和第二电源线。第一电源线配置为向所述显示像素提供第一电源电压；第二电源线配置为向所述显示像素提供第二电源电压；所述第二电源电压与所述第一电源电压具有相反的极性；所述第一电源线与第二电源线二者中的至少之一包括所述窄线部和所述宽线部。
例如，在本公开至少一实施例提供的显示基板中，所述驱动电路包括栅极驱动电路；所述栅极驱动电路包括多个级联的移位寄存器和触发信号线。多个级联的移位寄存器包括第一移位寄存器、第二移位寄存器……第N移位寄存器，其中，N为正整数，每个所述移位寄存器包括信号输入端和信号输出端；触发信号线与所述第一移位寄存器的信号输入端连接且配置为向所述第一移位寄存器提供触发信号；所述驱动信号线包括所述触发信号线。
例如，在本公开至少一实施例提供的显示基板中，所述驱动信号包括扫描驱动信号；所述触发信号线包括扫描触发信号线，扫描触发信号线配置为向所述第一移位寄存器提供扫描触发信号以使所述移位寄存器输出所述扫描驱动信号，所述扫描驱动信号被提供给所述像素电路。
例如，在本公开至少一实施例提供的显示基板中，所述栅极驱动电路还包括栅极扫描线，栅极扫描线与所述移位寄存器的信号输出端连接且配置为将从所述移位寄存器输出的所述扫描驱动信号提供给所述像素电路；所述像素电路包括：数据线、发光器件、以及位于显示像素的第一晶体管、第二晶体管和存储电容。数据线配置为向所述显示像素提供数据信号；发光器件包括第一电极和第二电极，所述第一电源线与所述第一电极连接以接收所述第一电源电压；所述第一晶体管的栅极与所述栅极扫描线连接以接收所述扫描 驱动信号，所述第一晶体管的第一极与数据线连接以接收所述数据信号，所述第一晶体管的第二极与所述第二晶体管的栅极连接，所述第二晶体管的第一极与第二电源线连接以接收所述第二电源电压，所述第二晶体管的第二极与所述发光器件的第二电极连接以接收所述第二电源电压；所述存储电容的第一极与所述第二晶体管的栅极连接，所述存储电容的第二极与所述第二电源线连接。
例如，在本公开至少一实施例提供的显示基板中，所述驱动信号还包括发光控制驱动信号；所述触发信号线还包括发光控制触发信号，发光控制触发信号线配置为向所述第一移位寄存器提供发光控制触发信号以使所述移位寄存器输出所述发所述光控制驱动信号，所述发光控制驱动信号被提供给所述像素电路。
例如，在本公开至少一实施例提供的显示基板中，所述扫描驱动信号包括第一扫描驱动信号、和第二扫描驱动信号，发光控制驱动信号包括第一发光控制驱动信号、第二发光控制驱动信号和复位驱动信号第二发光控制驱动信号，所述驱动信号还包括复位驱动信号；所述栅极驱动电路还包括：第一扫描线、第二扫描线、第一发光控制线和第二发光控制线。第一扫描线和第二扫描线与所述移位寄存器的信号输出端连接且配置为将从该移位寄存器输出的所述第一扫描驱动信号和所述第二扫描驱动信号提供给所述像素电路；第一发光控制线和第二发光控制线与所述所述移位寄存器的信号输出端连接且配置为将从该移位寄存器输出的所述第一发光控制驱动信号和所述第二发光控制驱动信号提供给所述像素电路；所述像素电路包括：数据线、发光器件、初始信号线、以及位于每个像素的第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管和存储电容。数据线配置为向所述显示像素提供数据信号；发光器件包括第一电极和第二电极，所述第一电源线与所述第一电极连接以接收所述第一电源电压；初始信号线，配置为向所述显示像素提供初始信号；所述第一晶体管的栅极与第一节点连接；所述第一晶体管的第一极与第二节点连接，所述第一晶体管的第二极与第三节点连接；所述第二晶体管的栅极与所述第一扫描线连接以接收所述第一扫描驱动信号，所述第二晶体管的第一极与所述数据线连接以接收所述数 据信号，所述第二晶体管的第二极与所述第二节点连接；所述第三晶体管的栅极与所述第二扫描线连接以接收所述第二扫描驱动信号，所述第三晶体管的第一极与所述第一节点连接，所述第三晶体管的第二极与所述第三节点连接；所述存储电容的第一极与所述第一节点连接，所述存储电容的第二极与所述第二电源线连接以接收所述第二电源电压；所述第四晶体管的栅极与所述第一发光控制线连接以接收所述第一发光控制驱动信号，所述第四晶体管的第一极与所述第二电源线连接以接收所述第二电源电压，所述第四晶体管的第二极与所述第二节点连接；所述第五晶体管的栅极与所述第二发光控制线连接以接收所述第二发光控制驱动信号，所述第五晶体管的第一极与所述第三节点连接，所述第五晶体管的第二极与所述发光器件的第二电极连接；所述第六晶体管的栅极与所述复位控制端连接以接收所述复位驱动信号，所述第六晶体管的第一极与所述初始信号线连接以接收所述初始信号，所述第六晶体管的第二极与所述发光器件的第二电极连接；所述第七晶体管的栅极与复位控制端连接以接收复位驱动信号，所述第七晶体管的第一极与所述初始信号线连接以接收所述初始信号，所述第七晶体管的第二极与所述第一节点连接。
例如，在本公开至少一实施例提供的显示基板中，所述驱动信号线还包括所述初始信号线，初始信号线从所述非显示区域延伸至所述显示区域。
例如，在本公开至少一实施例提供的显示基板中，所述驱动信号线还包括时钟信号线，所述时钟信号线配置为向每个所述移位寄存器提供时钟控制驱动信号以使时钟信号提供给所述像素电路。
例如，在本公开至少一实施例提供的显示基板中，所述驱动信号线还包括：低电平信号线和高电平信号线。低电平信号线配置为向每个所述移位寄存器提供第一电压驱动信号；高电平信号线配置为向每个所述移位寄存器提供第二电压驱动信号，所述第二电压大于所述第一电压。
例如，在本公开至少一实施例提供的显示基板中，所述第一电源线和所述第二电源线两者中的每个分别包括第一电源子走线和第二电源子走线，所述第一电源子走线和所述第二电源子走线分别包括所述窄线部和所述宽线部；所述驱动信号线包括第一信号子走线和第二信号子走线，所述第一信号 子走线和所述第二信号子走线分别延伸至所述显示区域的彼此相对的两侧；所述第一电源子走线的窄线部与所述第一信号子走线在垂直于所述衬底基板的方向上至少部分交叠，所述第二电源子走线的窄线部与所述第二信号子走线在垂直于所述衬底基板的方向上至少部分交叠。
例如，在本公开至少一实施例提供的显示基板中，所述电源线从所述显示区域的靠近所述第一电源电路的第一侧进入所述显示区域；或者，所述电源线从所述显示区域的与所述显示区域的第一侧相交的侧面进入所述显示区域。
本公开至少一实施例提供还一种显示面板，该显示面板包括本公开实施例提供的任意一种显示基板。
本公开至少一实施例提供还一种显示装置，该显示装置包括本公开实施例提供的任意一种显示面板。
附图说明
为了更清楚地说明本发明实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例，而非对本发明的限制。
图1A为本公开一实施例提供的一种显示基板的结构示意图；
图1B为本公开一实施例提供的另一种显示基板的结构示意图；
图2A为图1A中包括第一电源线、第二电源线和驱动电路的局部示意图；
图2B为图2A的局部放大示意图；
图2C为本公开一实施例提供的另一种显示基板的局部示意图；
图2D为图2A中的显示基板的显示区域沿A-A’线的一种截面示意图；
图3A为图1A中的驱动信号线的局部放大示意图；
图3B为时钟信号线和多个移位寄存器的示意图；
图4A为本公开一实施例提供的显示基板的一种像素电路的等效电路图；
图4B为本公开一实施例提供的显示基板的另一种像素电路的等效电路图；
图4C为理想状态下的数据信号Vdata与数据信号读取时间T的关系；
图4D为实际状态下的数据信号Vdata与数据信号读取时间T的关系；
图5为本公开一实施例提供的另一种显示基板的结构示意图；
图6为本公开一实施例提供的一种显示面板的示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，都属于本发明保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开中的附图并不是严格按实际比例绘制，显示基板中的移位寄存器的个数、显示区中的电源线的条数等不限定为图中所示的数量，各个结构的具体地尺寸和数量可根据实际需要进行确定，本公开中所描述的附图仅是结构示意图。
本公开至少一实施例提供了一种显示基板，该显示基板包括衬底基板、像素电路和驱动电路。衬底基板包括显示区域和非显示区域，所述显示区域包括显示像素，所述非显示区域至少部分围绕所述显示区域；像素电路包括电源线，所述电源线配置为向所述显示像素提供电源电压；驱动电路至少部分位于所述非显示区域，且包括驱动信号线，所述驱动信号线配置为使得驱动信号被提供至所述像素电路；所述电源线包括窄线部和与所述窄线部连接的宽线部，所述窄线部在所述衬底基板上的正投影与所述驱动信号线在所述 衬底基板上的正投影至少部分重叠，且所述窄线部的线宽小于所述宽线部的线宽；所述显示基板具有用于显示的第一侧和与所述第一侧相对的第二侧，且包括位于所述衬底基板的边缘处的弯折区，所述电源线和所述驱动信号线从所述第一侧跨经所述弯折区从而延伸至所述第二侧；所述电源线的所述窄线部至少位于所述显示基板的第二侧。
示例性地，图1A为本公开一实施例提供的一种显示基板的结构示意图。如图1A所示，图2A为图1A中包括第一电源线、第二电源线和驱动电路的局部示意图，此处以包括第二电源线也包括窄线部的情况为例，下面描述的特征图2A中的特征，除了第二电源线相关特征之外的特征及效果均适用于图1B所示的实施例。结合图1A和图2A，显示基板10包括：衬底基板1、像素电路和驱动电路。衬底基板1包括显示区域11和非显示区域12。显示区域11包括多个显示像素，例如多个显示像素呈阵列排列；非显示区域12围绕显示区域11。当然，在其他实施例中，非显示区域12也可以围绕显示区域11的一部分。像素电路包括电源线，例如电源线包括第一电源线31和第二电源线32。第一电源线31配置为向显示像素提供第一电源电压，第二电源线32配置为向显示像素提供第二电源电压，第二电源电压与第一电源电压具有相反的极性。例如第一电源电压的极性为负，第二电源电压的极性为正。例如，在图1A和图2A所示的实施例中，第一电源线31包括窄线部312和与窄线部312连接的宽线部3111/3112。驱动电路的一部分位于非显示区域12，且驱动电路包括驱动信号线20，驱动信号线20配置为使得驱动信号被提供至像素电路。如图2A所示，第一电源线31的窄线部312在衬底基板1上的正投影与驱动信号20线在衬底基板1上的正投影至少部分重叠，例如第一电源线31的窄线部312在衬底基板1上的正投影的一部分或者全部与驱动信号线20在衬底基板1上的正投影重叠，且第一电源线31的窄线部311的线宽w12小于第一电源线31的宽线部3111/3112的线宽w11。在本公开实施例中，由于减小了与驱动信号线20在垂直于衬底基板1的方向上重叠的第一电源线31的窄线部311的线宽，而减小了驱动信号线20与第一电源线31之间形成的寄生电容，从而提高了驱动信号线20上的信号传导的时效，达到使所设计理想的驱动信号能够传送到像素电路，提高显示效果。如图1A所 示，显示基板具有用于显示的第一侧101(即显示侧)和与第一侧101相对的第二侧102；显示基板包括位于衬底基板1边缘处的弯折区4，第一电源线31、第二电源线32和驱动信号线20从第一侧跨经弯折区4从而延伸至第二侧102，即图1A中弯折区4以下的部分弯折到显示基板的第二侧。在这种情况下，第一电源线31的窄线部、第二电源线32的窄线部位于显示基板的第二侧。
例如，在一些实施例中，显示基板的第一侧101与第二侧102基本位于同一平面，如图1A和图2A所示，承载窄线部312和部分驱动电路的电路板未折叠到显示侧的背面，此时，第一侧101是弯折区4的靠近显示区域11的一侧，第二侧102是弯折区4的远离显示区域11的一侧，第一侧101与第二侧分别位于弯折区4的两侧而基本在同一平面内彼此相对。例如，在另一些实施例中，载窄线部和部分驱动电路的电路板通过将弯折区4弯折而折叠到显示侧的背面，显示基板的第一侧101与第二侧102分别位于不同的面，即第一侧101为显示侧，第二侧102为第一侧101的背面，是非显示侧。
需要说明的是，本公开中的“线宽”是指该线的在垂直于该线的延伸方向的方向上的宽度。
或者，第一电源线31的宽线部3111/3112在衬底基板1上的正投影与驱动信号线20在衬底基板1上的正投影不重叠。
例如，如图2A所示，第一电源线31的宽线部包括第一部分3111和第二部分3112；第一电源线31的窄线部312在第一电源线的延伸方向上具有第一端和第二端，第一部分3111与该窄线部312的第一端连接，第二部分3112与该窄线部312的第二端连接。从而，尽可能地使第一电源线31的不与驱动信号线20重叠的部分的线宽较宽，从而尽可能地减小因局部线宽的减小而对第一电源线31的电阻的影响，从而尽可能地不影响信号在第一电源线31中的传导。
例如，第一电源线31的窄线部312的线宽小于等于第一电源线31的宽线部的线宽的二分之一，以达到较为理想的减小寄生电容的效果，例如第一部分3111的线宽与第二部分3112的线宽相等。
例如，第一电源线31的线宽远远大于驱动信号线21的线宽，例如，第 一电源线31的窄线部312的线宽大于驱动信号线21的线宽。即，例如驱动信号线21包括多条不同类型的信号线(图2A中的驱动信号线32为彼此间隔的多条信号线合并在一起的宏观图，放大示意图后续介绍)，第一电源线31的线宽远远大于该多条不同类型的信号线中的每条信号线的线宽，第一电源线31的窄线部312的线宽大于该多条不同类型的信号线中的每条信号线的线宽。为了达到上述提高显示效果的目的，需要不仅减小驱动信号线20上的寄生电容还要尽可能地不增大驱动信号线20的电阻。在上述第一电源线31的线宽远远大于驱动信号线21的线宽情况下，一方面，其线宽减小的余地很小，另一方面，如果减小了驱动信号线20的线宽，减小寄生电容的效果很微弱，反而会明显增大驱动信号线20的电阻，依然会造成显示效果不佳。因此，在驱动信号线21与第一电源线31重叠的区域，减小第一电源线31的线宽而不减小驱动信号线21的线宽。
例如，第一电源线31的线宽大于第二电源线32的线宽，从而，相比于第二电源线32，在与驱动信号线20重叠的区域，第一电源线31的线宽的减小幅度可以更大，从而达到更大的减小寄生电容的效果。
例如，在一些实施例中，如图1A所示，第二电源线32也驱动信号线20相交，即在垂直于衬底基板1的方向上第二电源线32具有与驱动信号线20重叠的部分，且第二电源线32包括窄线部322和与窄线部322连接的宽线部3211/3212。第二电源线32的窄线部322在衬底基板1上的正投影与驱动信号20线在衬底基板1上的正投影至少部分重叠，例如第二电源线32的窄线部322在衬底基板1上的正投影的一部分或者全部与驱动信号线20在衬底基板1上的正投影重叠，且第二电源线32的宽线部3211/3212在衬底基板1上的正投影与驱动信号线20在衬底基板1上的正投影不重叠，且第二电源线32的窄线部322的线宽w22小于第二电源线32的宽线部3211/3212的线宽w21。在本公开实施例中，由于减小了与驱动信号线20在垂直于衬底基板1的方向上重叠的第二电源线32的窄线部321的线宽，而在减小第一电源线31的窄线部的线宽的基础上，进一步减小了驱动信号线20与第二电源线32之间形成的寄生电容，从而进一步提高了驱动信号线20上的信号传导的时效，达到使所设计理想的驱动信号能够传送到像素电路，进一步提高显示效 果。
当然，在其他实施例中，也可以是第二电源线32包括窄线部322和与窄线部322连接的宽线部3211/3212，而第一电源线31的与驱动信号线20重叠的部分的线宽不变窄，即“所述第一电源线与第二电源线二者中的至少之一包括所述窄线部和所述宽线部”。
例如第一电源线31为连接到像素电路的VSS线，第二电源线32为连接到像素电路的VDD线。
图1B为本公开一实施例提供的另一种显示基板的结构示意图，该实施例与图1A的区别在于，仅第一电源线31包括所述窄线部和所述宽线部，不限定第二电源线也包括所述窄线部。其他特征均与图1A所示的实施例中的相同，不再重复。
图2D为图2A中的显示基板的显示区域沿A-A’线的一种截面示意图。如图2D所示，显示基板的显示区域11的每个子像素的像素电路包括薄膜晶体管(TFT)、发光元件180和存储电容Cst。薄膜晶体管包括有源层120、栅极121和源漏极122/123；存储电容Cst包括第一极板CE1和第二电容极板CE2。发光元件180包括阴极183、阳极181以及阴极183和阳极181之间的发光层182，阳极181与薄膜晶体管TFT的源漏极122/123中之一，例如漏极123，电连接。当然，在其他实施例中，阳极181与薄膜晶体管TFT的漏极123也可通过转接电极电连接。例如，该发光元件例如可以为有机发光二极管(OLED)或量子点发光二极管(QLED)，相应地，发光层182为有机发光层或量子点发光层。
例如，第一电源线31与栅极121、存储电容Cst的第一极板CE1同层设置。同层设置的结构可通过一次构图工艺形成，由此可以简化显示基板20的制备工艺。或者，第一电源线31与存储电容Cst的第二极板CE2同层设置。或者，每条第一电源线31包括与栅极121、存储电容Cst的第一极板CE1同层设置的第一部分，以及与存储电容Cst的第二极板CE2同层设置的第二部分，异层设置的该第一部分与该第二部分通过过孔电连接，从而该该第一部分与该第二部分并联，以减小每条第一电源线31的电阻，这种情况下，例如在对应于第一电源线31的窄线部的位置处不设置过孔。
例如，如图2D所示，显示区域11还包括位于有源层120与栅极121之间的第一栅绝缘层151、位于栅极121上方的第二栅绝缘层152以及层间绝缘层160，第二栅绝缘层152位于第一极板CE1和第二电容极板CE2之间，使得第一极板CE1、第二栅绝缘层152和第二电容极板CE2构成存储电容Cst。层间绝缘层160覆盖在第二电容极板CE2上。
例如，如图2D所示，显示区域11还包括覆盖像素电路的绝缘层113(例如钝化层)和第一平坦化层112。显示区域201还包括用于限定多个子像素的像素界定层170以及像素界定层170上的隔垫物(未示出)等结构。如图3A所示，在一些实施例中，绝缘层113位于源漏极122/123上方(例如钝化层，由氧化硅、氮化硅或者氮氧化硅等材料形成)，绝缘层113上方设置有第一平坦化层112，阳极181通过贯穿第一平坦化层112和绝缘层113的过孔与漏极123电连接。
例如，如图2D所示，显示基板还包括封装层190，封装层190包括多个封装子层191/192/193。例如，第一封装层291与封装层190中的第一封装子层191同层设置，第二封装层292与封装层190中的第二封装子层192同层设置，第三封装层293与封装层190中的第三封装子层193同层设置，例如，第一封装层291和第三封装层293均可以包括无机封装材料，例如包括氧化硅、氮化硅或者氮氧化硅等，第二封装层292可以包括有机材料，例如包括树脂材料等。显示基板的多层封装结构可以达到更好的封装效果，以防止水汽或氧气等杂质渗入显示基板内部。
在一些实施例中，如图2D所示，显示基板还包括位于衬底基板210上的缓冲层111，缓冲层111作为过渡层，可以防止衬底基板1中的有害物质侵入显示基板的内部例如进入显示区域11，又可以增加显示基板中的膜层在衬底基板1上的附着力。例如，缓冲层111的材料可以包括氧化硅、氮化硅、氮氧化硅等绝缘材料形成的单层或多层结构。
图2B为图2A的局部放大示意图。如图2B所示，图2A中的驱动信号线包括彼此间隔的多条信号线20。多条驱动信号线20从显示基板的第二侧的绑定区延伸跨过弯折区4进入显示基板的用于显示的第一侧的非显示区域12，从而形成如下所述的图3A中的各条信号线。
例如，如图2B所示，多条驱动信号线20还包括静电屏蔽信号线ESD，静电屏蔽信号线ESD与多条驱动信号线20中的至少部分驱动信号线20电连接且接地，以配置为导走各个驱动信号线之间的静电，以防止静电对信号传输引起的不良影响。例如，多条驱动信号线20还包括数据选择器(MUX)信号线MUX，如此可以节省走线数量，具体可以采用1：2的MUX，这样数据信号线的数量在输入有效显示区之前，可以节省一半的数量。例如也可以采用1：6的MUX，本公开实施例不做限制。
如图2B所示，例如，至少部分驱动信号线20包括位于第二侧102的弯折部分21，弯折部分21包括彼此连接的横向部分211和纵向部分212。纵向部分212的延伸方向与电源线例如第一电源线31的延伸方向基本相同，横向部分211在衬底基板1的上的正投影与电源线例如第一电源线31在衬底基板1上的正投影至少部分重叠。纵向部分212延伸跨过弯折区4进入第一侧101。从而实现合理布线，使得驱动信号线20从第二侧102延伸至第一侧101。
如图1A所示，例如，显示基板还包括第一电源电路5和第二电源电路6。第一电源电路5位于显示基板的第二侧且配置为向电源线提供电源电压，即向第一电源线31提供第一电源电压以及向第二电源线32提供第二电源电压。第二电源电路6位于显示基板的第二侧且配置为向驱动电路提供上述驱动信号。
例如，如图1A所示，电源线(第一电源线31和第二电源线32)与第一电源电路5连接且从第一电源电路5引出，驱动信号线20与第二电源电路6连接且从第二电源电路6引出。电源线(第一电源线31和第二电源线32)从第一电源电路5引出的位置位于驱动信号线20从第二电源电路6引出的位置的靠近显示基板的边缘的一侧。
例如，如图1A所示，第一电源线31的位于第一侧101的部分围绕部分显示区域11，例如在显示区域11的上部区域，第一电源线31是闭合的。例如，图1A中，第一电源线31的位于显示区域11的左右两侧的非显示区域12中的部分，分别位于驱动信号线201和驱动信号线202的靠近显示基板的边缘的一侧，从而驱动信号线更靠近显示区域11，以减小将驱动信号线接入显示区的导线的长度，从而提高驱动信号的传输效率，利于实现较好的显示 效果。
图2C为本公开一实施例提供的另一种显示基板的局部示意图。图2C所示的实施例与图2B所示的实施例具有以下区别。如图2C所示，驱动信号线20中的第一部分驱动信号线在衬底基板1的上的正投影与窄线部321在衬底基板1的上的正投影至少部分重叠，驱动信号线20中的第二部分驱动信号线2001在衬底基板1的上的正投影与宽线部3111在衬底基板1的上的正投影至少部分重叠(在其他实施例中也可以与宽线部3112在衬底基板1的上的正投影至少部分重叠，或者与宽线部3111在衬底基板1的上的正投影和宽线部3112在衬底基板1的上的正投影均至少部分重叠)；第二部分驱动信号线2001的条数少于与第一部分驱动信号线的条数，以尽可能地减小驱动信号线上的寄生电容，达到较好的显示效果。图2C所示的实施例的其他特征及相应技术效果均与图2B所示的实施例的相同，不再重复。
图3A为图1A中的驱动信号线的局部放大示意图，图3B为时钟信号线和多个移位寄存器的示意图。如图3A所示，图2A中的驱动信号线20包括彼此间隔的多条信号线。结合图3A和图3B，驱动电路包括栅极驱动电路例如GOA驱动电路；栅极驱动电路包括多个级联的移位寄存器和触发信号线。多个级联的移位寄存器包括第一移位寄存器、第二移位寄存器……第N移位寄存器，N为正整数；每个移位寄存器包括信号输入端INT和信号输出端OUT。显示基板包括呈阵列排布的多个显示像素，包括多个显示像素行，多个显示像素行与多个级联的移位寄存器一一对应。触发信号线与第一移位寄存器的信号输入端连接且配置为向第一移位寄存器提供触发驱动信号，第一移位寄存器响应于触发信号而从其信号输出端OUT输出相应的驱动信号，以对与第一移位寄存器对应的显示区域(AA)的显示像素行进行扫描，上述驱动信号线包括该触发信号线。如图3B所示，从上一级移位寄存器的信号输出端OUT输出的驱动信号给入到下一级移位寄存器的信号输入端INT以作为下一级移位寄存器的触发信号。
例如，在一些实施例中，如图3A所示，驱动信号包括扫描驱动信号；触发信号线包括扫描触发信号线GSTV。扫描触发信号线GSTV配置为向第一移位寄存器提供扫描触发信号以使第一移位寄存器输出扫描驱动信号，例 如从第一移位寄存器的信号输出端OUT输出扫描驱动信号，扫描驱动信号被提供给像素电路。
图4A为本公开一实施例提供的显示基板的一种像素电路的等效电路图。结合图4A与图3A-3B，例如，栅极驱动电路还包括栅极扫描线，例如包括对应于每个显示像素行的栅极扫描线。对于每个显示像素行对应的栅极扫描线，该栅极扫描线与多个移位寄存器的信号输出端OUT连接且配置为将从多个移位寄存器输出的扫描驱动信号提供给像素电路。例如，图4A所示的像素电路为2T1C像素电路。该像素电路包括：数据线、发光器件、以及位于每个像素的第一晶体管T1、第二晶体管T2和存储电容C。数据线配置为向显示像素提供数据信号，例如所述数据信号为数据电压信号。发光器件L包括第一电极和第二电极，第一电源线31(VSS)与第一电极连接以接收第一电源电压；第一晶体管T1的栅极与栅极扫描线连接以接收扫描驱动信号，第一晶体管T1的第一极与数据线连接以接收数据信号，第一晶体管T1的第二极与第二晶体管T2的栅极连接，第二晶体管T2的第一极与第二电源线32(VDD)连接以接收第二电源电压，第二晶体管T2的第二极与发光器件L的第二电极连接以接收第二电源电压；存储电容C的第一极与第二晶体管T2的栅极连接，存储电容C的第二极与第二电源线32(VDD)连接。例如，第一晶体管T1和第二晶体管T2均为N型晶体管。例如，采用N型晶体管时，其可以采用IGZO作为薄膜晶体管的有源层，以减小驱动晶体管的尺寸以及防止漏电流。例如，N型晶体管响应于高电平信号开启。
由驱动电流公式I＝K*(Vsg-|Vth|) 2＝K*(VDD-Vdata-|Vth|) 2可知，数据电压Vdata直接影响驱动电流，显示亮度与驱动电流成正比，所以显示亮度受到Vdata的影响。图4C为理想状态下的数据信号Vdata与数据信号读取时间T的关系，图4D为实际状态下的数据信号Vdata与数据信号读取时间T的关系。由于本公开实施例减小了驱动信号线例如描触发信号线GSTV和发光控制触发信号线ESTV上的寄生电容，从而能够减小数据信号Vdata的响应时间，即减小上升时间Tr和下降时间Tf，使得实际的数据信号Vdata更加接近理想状态，从而获得更好的显示效果。
例如，对于图4A所示的实施例，第二电源电路6为扫描触发信号线提 供上述扫描触发信号，扫描触发信号经扫描触发信号线输入第一级移位寄存器，从而通过第一级移位寄存器输出扫描驱动信号，扫描驱动信号通过栅极扫描线提供给像素电路。
在本公开的其他实施例中，像素电路的类型不限于是2T1C电路，例如还可以是4T2C、7T1C等任何可以实施的类型。
例如，在一些实施例中，驱动信号还包括发光控制驱动信号；触发信号线还包括发光控制触发信号线ESTV，发光控制触发信号线ESTV配置为向第一移位寄存器提供发光控制触发信号以使第一移位寄存器输出发光控制驱动信号，发光控制驱动信号被提供给像素电路。下面以显示基板采用7T1C像素电路的情况为例对此进说明。
示例性地，图4B为本公开一实施例提供的显示基板的另一种像素电路的等效电路图，图4B所示的像素电路为7T1C像素电路。结合图4B与图3A-3B，所述扫描驱动信号包括第一扫描驱动信号和第二扫描驱动信号，光控制驱动信号包括第一发光控制驱动信号、第二发光控制驱动信号和复位驱动信号。栅极驱动电路还包括第一扫描线GATE1、第二扫描线GATE2、第一发光控制线EM1和第二发光控制线EM2。对于每个显示像素行，均对应设置有这四种信号线，对于每个显示像素行，第一扫描线GATE1和第二扫描线GATE2与移位寄存器的信号输出端OUT连接且配置为将从该移位寄存器输出的第一扫描驱动信号和第二扫描驱动信号提供给像素电路；第一发光控制线EM1和第二发光控制线EM2与移位寄存器的信号输出端OUT连接且配置为将从该移位寄存器输出的第一发光控制驱动信号和第二发光控制驱动信号提供给像素电路。例如，该像素电路包括：数据线、发光器件L1、初始信号线Vinit、以及位于每个像素的第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7和存储电容C。数据线配置为向显示像素提供数据信号Vdata，例如数据信号Vdata为数据电压；发光器件L1包括第一电极和第二电极，第一电源线31(VSS)与第一电极连接以接收第一电源电压；初始信号线Vinit配置为向显示像素提供初始信号。第一晶体管T1的栅极与第一节点N1连接；第一晶体管T1的第一极与第二节N2点连接，第一晶体管T1的第二极与第三节点 N3连接；第二晶体管T2的栅极与第一扫描线GATE1连接以接收第一扫描驱动信号，第二晶体管T2的第一极与数据线连接以接收数据信号Vdata，第二晶体管T2的第二极与第二节点N2连接；第三晶体管T3的栅极与第二扫描线GATE2连接以接收第二扫描驱动信号，第三晶体管T3的第一极与第一节点N1(即第一晶体管T1的栅极)连接，第三晶体管T3的第二极与第三节点N3连接；存储电容C的第一极与第一节点N1(即第一晶体管T1的栅极)连接，存储电容C的第二极与第二电源线32(VDD)连接以接收第二电源电压；第四晶体管T4的栅极与第一发光控制线EM1连接以接收第一发光控制驱动信号，第四晶体管T4的第一极与第二电源线32(VDD)连接以接收第二电源电压，第四晶体管T4的第二极与第二节点N2连接；第五晶体管T5的栅极与第二发光控制线EM2连接以接收第二发光控制驱动信号，第五晶体管T5的第一极与第三节点N3连接，第五晶体管T5的第二极与发光器件L1的第二电极连接；第六晶体管T6的栅极与复位控制端连接以接收复位驱动信号，第六晶体管T6的第一极与初始信号线Vinit连接以接收初始信号，第六晶体管T6的第二极与发光器件L1的第二电极连接；第七晶体管T7的栅极与复位控制端连接以接收复位驱动信号，第七晶体管T7的第一极与初始信号线Vinit连接以接收初始信号，第七晶体管T7的第二极与所述第一节点N1连接。
例如，在图4B所示的实施例中，第一到第七晶体管T1～T7均为N型晶体管。例如，采用N型晶体管时，其可以采用IGZO作为薄膜晶体管的有源层，以减小驱动晶体管的尺寸以及防止漏电流。N型晶体管响应于高电平信号开启。例如在其他实施例中，像素电路可以采用混合N型和P型晶体管的像素电路，例如，第三晶体管T3、第六晶体管T6和第七晶体管T7采用N型晶体管，其余的晶体管采用P型晶体管，由于N型晶体管的漏电流较小，因此可以在该像素电路用于低频率驱动时克服闪屏现象。又由于，像素电路中补偿电路的第三晶体管T3采用漏电流和尺寸较小的N型晶体管，所以该补偿电路的存储电容C可以采用尺寸较小的电容，从而可以增加显示面板的分辨，同时，由于N型晶体管的漏电流较小，所以无需考虑N型晶体管的老化问题。例如，结合图1A、图3A和图4B，所述驱动信号线还包括初始信 号线Vinit，初始信号线Vinit从非显示区域12延伸至显示区域11，例如初始信号线Vinit穿过移位寄存器所在的区域延伸至显示区域11而与第六晶体管T6的第一极和第七晶体管T7的第一极连接，以给其提供初始信号，即在进行下一显示阶段前对上一阶段的第一节点N1和第四节点N4复位。
例如，如图3A-3B所示，所述驱动信号线还包括时钟信号线，时钟信号线配置为向每个移位寄存器提供时钟控制驱动信号以使扫描驱动信号和发光控制驱动信号提供给像素电路。例如，时钟信号线包括第一扫描时钟信号线GCLK1、第二扫描时钟信号线GCLK2、第一发光控制时钟信号线ECLK1和第二发光控制时钟信号线ECLK2，这四者分别将第一扫描时钟信号线、第二扫描时钟信号、第一发光控制时钟信号和第二发光控制时钟信号提供给移位寄存器，移位寄存器输出第一扫描驱动信号、第二扫描驱动信号、第一发光控制驱动信号和第二发光控制驱动信号，这些信号分别通过第一扫描线、第二扫描线、第一发光控制线和第二发光控制线提供给像素电路，即时钟信号线配置为通过移位寄存器分别使第一扫描驱动信号、第二扫描驱动信号、第一发光控制驱动信号和第二发光控制驱动信号提供给像素电路。
例如，如图3A-3B所示，所述驱动信号线还包括低电平信号线VGL和高电平信号线VGH。低电平信号线VGL与每个移位寄存器连接且配置为向每个移位寄存器提供第一电压驱动信号；高电平信号线VGH与每个移位寄存器连接且配置为向每个移位寄存器提供第二电压驱动信号，第二电压大于第一电压，以为每个移位寄存器的工作提供电源电压。
对于图4B所示的实施例，第二电源电路6向扫描触发信号线提供扫描触发信号，向发光控制触发信号线提供发光控制触发信号，以及向第一扫描时钟信号线GCLK1、第二扫描时钟信号线GCLK2、第一发光控制时钟信号线ECLK1和第二发光控制时钟信号线ECLK2分别提供时钟控制驱动信号。并且，第二电源电路6向低电平信号线VGL提供第一电压驱动信号且向高电平信号线VGH提供第二电压驱动信号，第一电压驱动信号和第二电压驱动信号分别通过低电平信号线VGL和高电平信号线VGH提供给移位寄存器。
需要说明的是，驱动信号线不限制为上述列举的种类，也可以包括其他 功能的信号线，上述实施例中列举的驱动信号线的种类只是示例性的。
结合图1A和图2A，例如，第一电源线31包括第一电源子走线3101和第二电源子走线3102，第一电源子走线3101和第二电源子走线3102分别包括窄线部312和宽线部3111/3112；第二电源线32包括第一电源子走线3201和第二电源子走线3202，第一电源子走线3201和第二电源子走线3202分别包括窄线部322和宽线部3211/3212。驱动信号线20包括第一信号子走线201和第二信号子走线202，第一信号子走线201和第二信号子走线202分别延伸至显示区域11的彼此相对的两侧；第一电源线31的第一电源子走线3101的窄线部和第二电源线32的第一电源子走线3201的窄线部与第一信号子走线201在垂直于衬底基板1的方向上至少部分交叠，第一电源线31的第二电源子走线3102的窄线部和第二电源线32的第二电源子走线3202的窄线部与第二信号子走线202在垂直于衬底基板1的方向上至少部分交叠。即在显示区域11的双侧设置驱动电路，在双侧的驱动电路的驱动信号线与电源线重叠的区域，电源线均变窄。例如，两侧的驱动电路是对称的。两侧的驱动信号线分别包括上述触发信号线、初始信号线、时钟信号线、低电平信号线和高电平信号线中的一种或几种。即，第二信号子走线202也包括多条信号线。当然，在其他实施例中，也可以指在显示区域11的一侧设置驱动电路。
例如，如图1A所示，第一电源线31和第二电源线32从显示区域11的靠近第一电源电路5的第一侧进入显示区域11；或者，在其他实施例中，第一电源线31和第二电源线32述显示区域11的与显示区域11的第一侧相交的侧面进入显示区域11。
例如，在另一些实施例中，如图5所示，第一电源线31的窄线部312、第二电源线32的窄线部322位于显示基板的第一侧的所述非显示区域12。
图5所示的显示基板的其他特征及技术效果均与图1A和图2A所示的实施例中的相同，请参考之前的描述，不再赘述。
例如本公开实施例提供的显示基板为有机发光二极管(OLED)显示基板。
例如，本公开至少一实施例还提供一种显示面板，该显示面板包括本公开实施例提供的任意一种显示基板。图6为本公开一实施例提供的一种显示 面板的示意图。如图6所示，本公开至少一实施例提供的显示面板1000包括本公开实施例提供的任意一种显示基板10。显示面板1000的其他结构可根据具体需要采用本领域常规技术进行设计，本公开对此不作限定。
例如，本公开至少一实施例还提供一种显示装置，该显示装置包括本公开实施例提供的任意一种显示面板。
例如该显示装置可以是有机发光二极管(OLED)显示装置。例如可以为手机、平板电脑、显示器、笔记本电脑、ATM机等产品。显示装置的其他结构可根据具体需要采用本领域常规技术进行设计。
以上所述仅是本发明的示例性实施方式，而非用于限制本发明的保护范围，本发明的保护范围由所附的权利要求确定。

Claims (22)

  1. 一种显示基板，包括：
    衬底基板，包括显示区域和非显示区域，其中，所述显示区域包括显示像素，所述非显示区域至少部分围绕所述显示区域；
    像素电路，包括电源线，其中，所述电源线配置为向所述显示像素提供电源电压；以及
    驱动电路，至少部分位于所述非显示区域，且包括驱动信号线，其中，所述驱动信号线配置为使得驱动信号被提供至所述像素电路；
    其中，所述电源线包括窄线部和与所述窄线部连接的宽线部，所述窄线部在所述衬底基板上的正投影与所述驱动信号线在所述衬底基板上的正投影至少部分重叠，且所述窄线部的线宽小于所述宽线部的线宽；
    所述显示基板具有用于显示的第一侧和与所述第一侧相对的第二侧，且包括位于所述衬底基板的边缘处的弯折区，所述电源线和所述驱动信号线从所述第一侧跨经所述弯折区从而延伸至所述第二侧；
    所述电源线的所述窄线部至少位于所述显示基板的第二侧。
  2. 根据权利要求1所述的显示基板，其中，所述驱动信号线中的第一部分驱动信号线在所述衬底基板上的正投影与所述窄线部在所述衬底基板上的正投影至少部分重叠，所述驱动信号线中的第二部分驱动信号线在所述衬底基板上的正投影与所述宽线部在所述衬底基板上的正投影至少部分重叠，所述第二部分驱动信号线的条数少于与所述第一部分驱动信号线的条数；或者，
    所述驱动信号线在所述衬底基板上的正投影与所述宽线部在所述衬底基板上的正投影不重叠。
  3. 根据权利要求1或2所述的显示基板，其中，所述驱动信号线包括位于所述第二侧的弯折部分，所述弯折部分包括彼此连接的横向部分和纵向部分；
    所述纵向部分的延伸方向与所述电源线的延伸方向基本相同，所述横向部分与所述电源线在垂直于所述衬底基板的方向上交叠。
  4. 根据权利要求1-3任一所述的显示基板，还包括：
    第一电源电路，位于所述显示基板的第二侧且配置为向所述电源线提供所述电源电压；以及
    第二电源电路，位于所述显示基板的第二侧且配置为向所述驱动电路提供所述驱动信号。
  5. 根据权利要求4所述的显示基板，其中，所述电源线与所述第一电源电路连接且从所述第一电源电路引出，所述驱动信号线与所述第二电源电路连接且从所述第二电源电路引出；
    所述电源线从所述第一电源电路引出的位置位于所述驱动信号线从所述第二电源电路引出的位置的靠近所述显示基板的边缘的一侧。
  6. 根据权利要求1-5任一所述的显示基板，其中，
    所述宽线部包括第一部分和第二部分；
    所述窄线部在所述电源线的延伸方向上具有第一端和第二端，所述第一部分与所述窄线部的所述第一端连接，所述第二部分与所述窄线部的所述第二端连接。
  7. 根据权利要求1-6任一所述的显示基板，其中，所述窄线部的线宽小于等于所述宽线部的线宽的二分之一。
  8. 根据权利要求1-7任一所述的显示基板，其中，所述电源线的线宽大于所述驱动信号线的线宽。
  9. 根据权利要求8所述的显示基板，其中，所述电源线的窄线部的线宽大于所述驱动信号线的线宽。
  10. 根据权利要求1-9任一所述的显示基板，其中，所述电源线包括：
    第一电源线，配置为向所述显示像素提供第一电源电压；以及
    第二电源线，配置为向所述显示像素提供第二电源电压，其中，所述第二电源电压与所述第一电源电压具有相反的极性；
    所述第一电源线与第二电源线二者中的至少之一包括所述窄线部和所述宽线部。
  11. 根据权利要求10所述的显示基板，其中，
    所述驱动电路包括栅极驱动电路；
    所述栅极驱动电路包括：多个级联的移位寄存器，包括第一移位寄存器、 第二移位寄存器……第N移位寄存器，其中，N为正整数，每个所述移位寄存器包括信号输入端和信号输出端；以及
    触发信号线，与所述第一移位寄存器的信号输入端连接且配置为向所述第一移位寄存器提供触发信号，其中，
    所述驱动信号线包括所述触发信号线。
  12. 根据权利要求11所述的显示基板，其中，
    所述驱动信号包括扫描驱动信号；
    所述触发信号线包括：
    扫描触发信号线，配置为向所述第一移位寄存器提供扫描触发信号以使所述第一移位寄存器输出所述扫描驱动信号，其中，所述扫描驱动信号被提供给所述像素电路。
  13. 根据权利要求12所述的显示基板，其中，
    所述栅极驱动电路还包括：
    栅极扫描线，与所述移位寄存器的信号输出端连接且配置为将从所述移位寄存器输出的所述扫描驱动信号提供给所述像素电路；
    所述像素电路包括：
    数据线，配置为向所述显示像素提供数据信号；
    发光器件，包括第一电极和第二电极，其中，所述第一电源线与所述第一电极连接以接收所述第一电源电压；以及
    位于所述显示像素的第一晶体管、第二晶体管和存储电容，其中，所述第一晶体管的栅极与所述栅极扫描线连接以接收所述扫描驱动信号，所述第一晶体管的第一极与数据线连接以接收所述数据信号，所述第一晶体管的第二极与所述第二晶体管的栅极连接；
    所述第二晶体管的第一极与第二电源线连接以接收所述第二电源电压，所述第二晶体管的第二极与所述发光器件的第二电极连接；
    所述存储电容的第一极与所述第二晶体管的栅极连接，所述存储电容的第二极与所述第二电源线连接。
  14. 根据权利要求12所述的显示基板，其中，
    所述驱动信号还包括发光控制驱动信号；
    所述触发信号线还包括：
    发光控制触发信号线，配置为向所述第一移位寄存器提供发光控制触发信号以使所述移位寄存器输出所述发所述光控制驱动信号，其中，所述发光控制驱动信号被提供给所述像素电路。
  15. 根据权利要求14所述的显示基板，其中，所述扫描驱动信号包括第一扫描驱动信号和第二扫描驱动信号，发光控制驱动信号包括第一发光控制驱动信号、第二发光控制驱动信号，所述驱动信号还包括复位驱动信号；
    所述栅极驱动电路还包括：
    第一扫描线和第二扫描线，与所述移位寄存器的信号输出端连接且配置为将从该移位寄存器输出的所述第一扫描驱动信号和所述第二扫描驱动信号提供给所述像素电路；以及
    第一发光控制线和第二发光控制线，与所述移位寄存器的信号输出端连接且配置为将从该移位寄存器输出的所述第一发光控制驱动信号和所述第二发光控制驱动信号提供给所述像素电路；
    所述像素电路包括：
    数据线，配置为向所述显示像素提供数据信号；
    发光器件，包括第一电极和第二电极，其中，所述第一电源线与所述第一电极连接以接收所述第一电源电压；
    初始信号线，配置为向所述显示像素提供初始信号；以及
    位于每个像素的第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管和存储电容，其中，
    所述第一晶体管的栅极与第一节点连接；所述第一晶体管的第一极与第二节点连接，所述第一晶体管的第二极与第三节点连接；
    所述第二晶体管的栅极与所述第一扫描线连接以接收所述第一扫描驱动信号，所述第二晶体管的第一极与所述数据线连接以接收所述数据信号，所述第二晶体管的第二极与所述第二节点连接；
    所述第三晶体管的栅极与所述第二扫描线连接以接收所述第二扫描驱动信号，所述第三晶体管的第一极与所述第一节点连接，所述第三晶体管的第二极与所述第三节点连接；所述存储电容的第一极与所述第一节点连接，所 述存储电容的第二极与所述第二电源线连接以接收所述第二电源电压；
    所述第四晶体管的栅极与所述第一发光控制线连接以接收所述第一发光控制驱动信号，所述第四晶体管的第一极与所述第二电源线连接以接收所述第二电源电压，所述第四晶体管的第二极与所述第二节点连接；
    所述第五晶体管的栅极与所述第二发光控制线连接以接收所述第二发光控制驱动信号，所述第五晶体管的第一极与所述第三节点连接，所述第五晶体管的第二极与所述发光器件的第二电极连接；
    所述第六晶体管的栅极与复位控制端连接以接收复位驱动信号，所述第六晶体管的第一极与所述初始信号线连接以接收所述初始信号，所述第六晶体管的第二极与所述发光器件的第二电极连接；
    所述第七晶体管的栅极与所述复位控制端连接以接收所述复位驱动信号，所述第七晶体管的第一极与所述初始信号线连接以接收所述初始信号，所述第七晶体管的第二极与所述第一节点连接。
  16. 根据权利要求14或15所述的显示基板，其中，所述驱动信号线还包括时钟信号线，所述时钟信号线配置为向每个所述移位寄存器提供时钟控制驱动信号以使所述扫描驱动信号和所述发光控制驱动信号提供给所述像素电路。
  17. 根据权利要求11-16任一所述的显示基板，其中，所述驱动信号线还包括：
    低电平信号线，与每个所述移位寄存器连接且配置为向每个所述移位寄存器提供第一电压驱动信号；以及
    高电平信号线，与每个所述移位寄存器连接且配置为向每个所述移位寄存器提供第二电压驱动信号，其中，所述第二电压大于所述第一电压。
  18. 根据权利要求1-17任一所述的显示基板，其中，所述窄线部位于所述显示基板的第一侧的所述非显示区域。
  19. 根据权利要求10-18任一所述的显示基板，其中，所述第一电源线和所述第二电源线两者中的每个分别包括第一电源子走线和第二电源子走线，所述第一电源子走线和所述第二电源子走线分别包括所述窄线部和所述宽线部；
    所述驱动信号线包括第一信号子走线和第二信号子走线，所述第一信号子走线和所述第二信号子走线分别延伸至所述显示区域的彼此相对的两侧；
    所述第一电源子走线的窄线部与所述第一信号子走线在垂直于所述衬底基板的方向上至少部分交叠，所述第二电源子走线的窄线部与所述第二信号子走线在垂直于所述衬底基板的方向上至少部分交叠。
  20. 根据权利要求1-19所述的显示基板，其中，所述电源线从所述显示区域的靠近所述第一电源电路的第一侧进入所述显示区域；或者，
    所述电源线从所述显示区域的与所述显示区域的第一侧相交的侧面进入所述显示区域。
  21. 一种显示面板，包括权利要求1-20任一所述的显示基板。
  22. 一种显示装置，包括权利要求21所述的显示面板。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115398641A (zh) * 2022-04-28 2022-11-25 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN115424552A (zh) * 2022-09-23 2022-12-02 京东方科技集团股份有限公司 一种显示基板、显示基板的老化控制方法及显示装置

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116682365B (zh) * 2022-02-23 2026-02-03 京东方科技集团股份有限公司 显示基板及显示装置
CN114708796A (zh) * 2022-03-30 2022-07-05 武汉天马微电子有限公司 显示面板及显示装置
KR102950127B1 (ko) * 2022-06-30 2026-04-10 삼성디스플레이 주식회사 표시 장치 및 그것의 구동 방법
CN115050315B (zh) 2022-06-30 2025-01-28 厦门天马显示科技有限公司 显示面板及显示装置
CN115498001B (zh) * 2022-09-27 2026-04-10 武汉天马微电子有限公司 显示面板和显示装置
CN115798330A (zh) * 2022-11-24 2023-03-14 合肥维信诺科技有限公司 一种显示面板、显示装置和电子设备
CN116013196B (zh) * 2022-12-27 2024-06-18 深圳市华星光电半导体显示技术有限公司 显示面板
CN116234381B (zh) * 2023-01-13 2026-02-10 合肥鑫晟光电科技有限公司 一种显示基板、显示装置以及显示基板的制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10171369A (ja) * 1996-12-16 1998-06-26 Sharp Corp 映像用伝送路及び画像表示装置
CN1779753A (zh) * 2002-06-21 2006-05-31 精工爱普生株式会社 显示器用基板、电光装置、电子仪器
CN101625493A (zh) * 2008-07-08 2010-01-13 三星电子株式会社 阵列基板及具有阵列基板的液晶显示装置
CN202736910U (zh) * 2011-09-27 2013-02-13 株式会社东芝 半导体器件
CN110310572A (zh) * 2019-06-26 2019-10-08 云谷（固安）科技有限公司 一种显示面板及显示装置

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001296556A (ja) * 2001-01-30 2001-10-26 Seiko Epson Corp アクティブマトリクス表示パネル
AU2003241202A1 (en) * 2002-06-10 2003-12-22 Samsung Electronics Co., Ltd. Shift register, liquid crystal display device having the shift register and method of driving scan lines using the same
JP5256710B2 (ja) * 2007-11-28 2013-08-07 ソニー株式会社 Ｅｌ表示パネル
KR102214942B1 (ko) * 2013-12-20 2021-02-09 엘지디스플레이 주식회사 투명 표시 장치 및 투명 유기 발광 표시 장치
KR102086644B1 (ko) * 2013-12-31 2020-03-09 엘지디스플레이 주식회사 플렉서블표시장치 및 이의 제조방법
JP2016142880A (ja) * 2015-01-30 2016-08-08 株式会社ジャパンディスプレイ 表示装置
KR102562898B1 (ko) 2016-03-31 2023-08-04 삼성디스플레이 주식회사 표시 장치
KR102525124B1 (ko) * 2016-04-05 2023-04-26 삼성디스플레이 주식회사 표시 장치
CN108806573B (zh) * 2017-04-27 2021-11-23 乐金显示有限公司 显示装置
US10360854B2 (en) * 2017-06-14 2019-07-23 Lg Display Co., Ltd. Gate driving circuit having a compensating auxiliary load and display device using the same
KR102360094B1 (ko) * 2017-09-15 2022-02-09 삼성디스플레이 주식회사 표시 장치
CN107634086B (zh) * 2017-09-15 2020-03-03 京东方科技集团股份有限公司 一种柔性阵列基板及制备方法、显示装置
JP7118618B2 (ja) * 2017-10-17 2022-08-16 株式会社ジャパンディスプレイ 表示装置
KR102430806B1 (ko) * 2017-12-07 2022-08-09 엘지디스플레이 주식회사 터치 스크린을 구비하는 표시장치
KR102543918B1 (ko) * 2018-06-08 2023-06-15 삼성디스플레이 주식회사 표시 장치
CN109166528B (zh) 2018-09-28 2020-05-19 昆山国显光电有限公司 像素电路及其驱动方法
KR102753465B1 (ko) * 2018-11-30 2025-01-13 삼성디스플레이 주식회사 디스플레이 장치
KR102727644B1 (ko) * 2018-12-27 2024-11-08 삼성디스플레이 주식회사 디스플레이 장치
KR102625726B1 (ko) * 2018-12-31 2024-01-15 엘지디스플레이 주식회사 발광 표시장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10171369A (ja) * 1996-12-16 1998-06-26 Sharp Corp 映像用伝送路及び画像表示装置
CN1779753A (zh) * 2002-06-21 2006-05-31 精工爱普生株式会社 显示器用基板、电光装置、电子仪器
CN101625493A (zh) * 2008-07-08 2010-01-13 三星电子株式会社 阵列基板及具有阵列基板的液晶显示装置
CN202736910U (zh) * 2011-09-27 2013-02-13 株式会社东芝 半导体器件
CN110310572A (zh) * 2019-06-26 2019-10-08 云谷（固安）科技有限公司 一种显示面板及显示装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4002337A4 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115398641A (zh) * 2022-04-28 2022-11-25 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
CN115398641B (zh) * 2022-04-28 2023-10-13 京东方科技集团股份有限公司 显示基板及其制备方法、显示装置
US12610701B2 (en) 2022-04-28 2026-04-21 Chengdu Boe Optoelectronics Technology Co., Ltd. Display substrate, manufacturing method therefor, and display device
CN115424552A (zh) * 2022-09-23 2022-12-02 京东方科技集团股份有限公司 一种显示基板、显示基板的老化控制方法及显示装置

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