WO2021248954A1 - 一种功率半导体模块 - Google Patents

一种功率半导体模块 Download PDF

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Publication number
WO2021248954A1
WO2021248954A1 PCT/CN2021/080899 CN2021080899W WO2021248954A1 WO 2021248954 A1 WO2021248954 A1 WO 2021248954A1 CN 2021080899 W CN2021080899 W CN 2021080899W WO 2021248954 A1 WO2021248954 A1 WO 2021248954A1
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Prior art keywords
copper
chip
material layer
semiconductor module
insulating
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French (fr)
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梁小广
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Wuxi Leapers Semiconductor Co Ltd
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Wuxi Leapers Semiconductor Co Ltd
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Priority to JP2022572635A priority Critical patent/JP7482259B2/ja
Priority to EP21822052.3A priority patent/EP4148778B1/en
Priority to US17/926,623 priority patent/US20230187404A1/en
Publication of WO2021248954A1 publication Critical patent/WO2021248954A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/43—Encapsulations, e.g. protective coatings characterised by their materials comprising oxides, nitrides or carbides, e.g. ceramics or glasses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/20—Conductive package substrates serving as an interconnection, e.g. metal plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/25—Arrangements for cooling characterised by their materials
    • H10W40/255—Arrangements for cooling characterised by their materials having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/20—Conductive package substrates serving as an interconnection, e.g. metal plates
    • H10W70/22—Conductive package substrates serving as an interconnection, e.g. metal plates having an heterogeneous or anisotropic structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
    • H10W76/42—Fillings
    • H10W76/47—Solid or gel fillings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/20—Conductive package substrates serving as an interconnection, e.g. metal plates
    • H10W70/24—Conductive package substrates serving as an interconnection, e.g. metal plates characterised by materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/076—Connecting or disconnecting of strap connectors
    • H10W72/07651—Connecting or disconnecting of strap connectors characterised by changes in properties of the strap connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H10W72/621—Structures or relative sizes of strap connectors
    • H10W72/622—Multilayered strap connectors, e.g. having a coating on a lowermost surface of a core
    • H10W72/623—Multilayered strap connectors, e.g. having a coating on a lowermost surface of a core characterised by the structures of the outermost layers, e.g. multilayered coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H10W72/621—Structures or relative sizes of strap connectors
    • H10W72/624—Strap connectors having multiple distinct cores
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H10W72/651—Materials of strap connectors
    • H10W72/652—Materials of strap connectors comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/886—Die-attach connectors and strap connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/15—Containers comprising an insulating or insulated base
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/761—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors
    • H10W90/764—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the invention relates to the technical field of power semiconductor module packaging, in particular to a power semiconductor module.
  • the power module is mainly composed of a metal bottom plate, a solder layer, DBC (double-sided copper-clad ceramic substrate), AMB (foil brazed copper-clad ceramic substrate), insulating and heat-dissipating resin film or other insulating and heat-dissipating materials, copper frame, shell, and silicone. , As shown in Figure 2 and Figure 3.
  • the strong conductivity of copper can reduce the on-resistance and parasitic inductance.
  • the contact area between the copper frame and the chip is large, and the coefficient of thermal expansion is 16.9x10 -6 /K, which is much lower than that of aluminum (the coefficient of thermal expansion is 23x10 -6 /K) , Closer to the chip (the thermal expansion coefficient is 2x10 -6 /K to 4x10 -6 /K), which can enhance the power cycle life.
  • the copper frame combination method also has a series of shortcomings. First, the copper frame generally uses a special mold and is stamped and manufactured, and the cost is relatively high. Second, in order to reduce the on-resistance, a thicker copper frame must be used.
  • the contact surface of the thicker copper frame with the chip may cause relatively large mechanical stress to the chip when the temperature changes, and the chip may be cracked in severe cases. damage.
  • the position of each chip may be deviated. Once the copper frame is processed, the position of each contact surface cannot be adjusted, which may cause positional deviation during processing. In order to reduce defects, precise chip and frame positioning technology is required.
  • the present invention provides a power semiconductor module to solve the problem of mechanical stress caused to the chip when the thicker copper frame is applied in the power semiconductor module package when the heat and the cold are changed in the prior art.
  • the present invention provides a power semiconductor module, which includes a metal bottom plate, an insulating and heat-dissipating material layer, a chip, a binding plate, silica gel, and a shell.
  • the binding plate includes a copper plate and a copper tape. The copper plate is welded. Connected with copper tape, the binding board is used for circuit connection of each component, the metal bottom plate is connected to the insulating heat dissipation material layer by soldering, the chip is connected to the insulating heat dissipation material layer by soldering, and the chip is connected to the copper tape , The copper tape is connected with the insulating and heat dissipation material layer.
  • the shell and the metal bottom plate are connected by a glue dispensing process.
  • the silica gel is filled in the shell, is anti-corrosion and moisture-proof, protects internal circuits, and isolates internal components with high voltage.
  • the copper plate is connected to the copper strip by laser welding and ultrasonic welding.
  • the chip is connected to the copper strip by welding or sintering, and the copper strip is connected to the insulating and heat-dissipating material layer by welding or sintering.
  • the beneficial effects brought by the present invention 1. Compared with the prior art, in the power semiconductor module of the present invention, when the copper strip in contact with the chip changes in cold and heat, the mechanical stress on the chip is small and does not cause the chip Crack damage, most of the current of the circuit passes through the thicker copper plate, which greatly reduces the on-resistance and also reduces the parasitic inductance; 2. According to the deviation position of the chip, the position of the copper strip can be adjusted to compensate for the position deviation of the chip and reduce it The requirement for positioning technology means simplification of processing technology and at the same time increase the yield rate of product production.
  • Fig. 1 is a schematic diagram of the overall structure of a power semiconductor module according to an embodiment of the present invention
  • Figure 2 is a schematic diagram of the overall structure of a power semiconductor module using a copper frame
  • Figure 3 is a schematic diagram of a power semiconductor module using a copper frame
  • FIG. 4 is a schematic diagram of a part of a power semiconductor module according to an embodiment of the present invention
  • Figure 5 is a first structural diagram of a binding board according to an embodiment of the present invention
  • Figure 6 is a second structural schematic diagram of a binding board according to an embodiment of the present invention.
  • FIG. 7 is a second schematic diagram of a partial structure of a power semiconductor module according to an embodiment of the present invention
  • Fig. 8 is a schematic structural diagram of a power semiconductor module according to a fourth embodiment of the present invention.
  • 1-metal bottom plate 2-insulating and heat-dissipating material layer, 3-chip, 4-binding board, 5-silica gel, 6-shell, 7-copper plate, 8- copper tape.
  • the present invention provides a power semiconductor module, which includes a metal base plate 1, an insulating and heat-dissipating material layer 2, a chip 3, a binding board 4, a silica gel 5, and a casing 6.
  • the binding The board 4 includes a copper plate 7 and a copper strip 8.
  • the copper plate 7 is connected to the copper strip 8 by welding.
  • the binding plate 4 is used for circuit connection of various components.
  • the metal bottom plate 1 is connected to the insulating and heat-dissipating material layer 2 by soldering.
  • the chip 3 is connected to the insulating and heat-dissipating material layer 2 by soldering, the chip 3 is connected to the copper tape 8, and the copper-strip 8 is connected to the insulating heat-dissipating material layer 2.
  • the housing 6 and the metal bottom plate 1 are connected by a glue dispensing process.
  • silica gel 5 is filled in the shell 6 to prevent corrosion and moisture, protect the internal circuit, and isolate the internal components with high voltage.
  • the copper plate 7 is connected to the copper strip 8 by laser welding or ultrasonic welding.
  • the chip 3 is connected to the copper strip 8 by welding or sintering
  • the copper strip 8 is connected to the insulating and heat-dissipating material layer 2 by welding or sintering.
  • the thickness of the copper plate 7 is 1 mm-2 mm, and the thickness of the copper strip 8 is 0.3 mm-0.8 mm.
  • the present invention provides a power semiconductor module, which includes a metal base plate 1, an insulating and heat-dissipating material layer 2, a chip 3, a binding plate 4, a silica gel 5, and a housing 6,
  • the binding plate 4 includes The copper plate 7, the copper strip 8, the copper plate 7 is connected to the copper strip 8 by welding, the binding plate 4 is used for the circuit connection of each component, the metal bottom plate 1 is connected to the insulating and heat-dissipating material layer 2 by soldering, the The chip 3 is connected to the insulating and heat-dissipating material layer 2 by soldering, the chip 3 is connected to the copper tape 8, and the copper-strip 8 is connected to the insulating heat-dissipating material layer 2.
  • the housing 6 and the metal bottom plate 1 are connected by a glue dispensing process.
  • silica gel 5 is filled in the shell 6 to prevent corrosion and moisture, protect the internal circuit, and isolate the internal components with high voltage.
  • the copper plate 7 is connected to the copper strip 8 by laser welding or ultrasonic welding.
  • the chip 3 is connected to the copper strip 8 by welding or sintering
  • the copper strip 8 is connected to the insulating and heat-dissipating material layer 2 by welding or sintering.
  • the thickness of the copper plate 7 is 1 mm-2 mm, and the thickness of the copper strip 8 is 0.5 mm-1 mm.
  • the surface of the copper strip 8 in contact with the chip 3 is ground to eliminate deviations, and the contact area between the copper strip 8 and the chip 3 is enlarged. At the same time, by further reducing the thickness of the copper strip 8 on the contact surface with the chip 3, the mechanical stress when the copper strip 8 is combined with the chip 3 is reduced, and the reliability is further improved.
  • the present invention provides a power semiconductor module, which includes a metal base plate 1, an insulating and heat-dissipating material layer 2, a chip 3, a binding plate 4, a silica gel 5, and a shell 6.
  • the binding plate 4 includes Copper plate 7, copper strip 8, said copper plate 7 is connected to copper strip 8 by welding, said binding plate 4 is used for circuit connection of various components, said metal base plate 1 is connected with insulating and heat-dissipating material layer 2 by soldering, said The chip 3 is connected to the insulating and heat-dissipating material layer 2 by soldering, the chip 3 is connected to the copper tape 8, and the copper-strip 8 is connected to the insulating heat-dissipating material layer 2.
  • the housing 6 and the metal bottom plate 1 are connected by a glue dispensing process.
  • silica gel 5 is filled in the shell 6 to prevent corrosion and moisture, protect the internal circuit, and isolate the internal components with high voltage.
  • the copper plate 7 is connected to the copper strip 8 by laser welding or ultrasonic welding.
  • the chip 3 is connected to the copper strip 8 by welding or sintering
  • the copper strip 8 is connected to the insulating and heat-dissipating material layer 2 by welding or sintering.
  • the thickness of the copper plate 7 is 1 mm-2 mm, and the thickness of the copper strip 8 is 0.3 mm-0.8 mm.
  • the copper plate 7 and the main electrode terminal form an integral structure.
  • the copper plate 7 is a separate structure from the electrode terminals used to connect to an external circuit. Such a structure brings additional resistance and parasitic inductance. In this embodiment, by forming the copper plate 7 and the main electrode terminal into an integrated structure, the resistance and parasitic inductance are further reduced.
  • the present invention provides a power semiconductor module, which includes a metal base plate 1, an insulating and heat-dissipating material layer 2, a chip 3, and a binding board 4.
  • the binding board 4 includes a copper plate 7 and a copper strip 8.
  • the copper plate 7 is connected to the copper strip 8 by welding, the binding plate 4 is used for circuit connection of each component, the metal base plate 1 is connected to the insulating and heat-dissipating material layer 2 by soldering, and the chip 3 is connected to the insulating and heat-dissipating material layer by soldering. 2 is connected, the chip 3 is connected with a copper strip 8, and the copper strip 8 is connected with the insulating and heat-dissipating material layer 2.
  • the copper plate 7 is connected to the copper strip 8 by laser welding or ultrasonic welding.
  • the chip 3 is connected to the copper strip 8 by welding or sintering
  • the copper strip 8 is connected to the insulating and heat-dissipating material layer 2 by welding or sintering.
  • the thickness of the copper plate 7 is 1 mm-2 mm, and the thickness of the copper strip 8 is 0.3 mm-0.8 mm.
  • the packaging form of the semiconductor module adopts the plastic packaging method of resin material. According to the design requirements of the shape and parameters, a special mold is used to pour resin into it, and the chip 3 of the semiconductor module, the insulating and heat dissipation material layer 2, and the binding board 4 are packaged and fixed. That is, 5 and 6 in Figure 1 are replaced by an integrated resin material.
  • This integrated plastic packaging method can eliminate the silicone and shell, simplify the production process, increase production efficiency, and improve product reliability.
  • the copper strip in contact with the chip will bring less mechanical stress to the chip when the temperature changes, and will not cause the chip to break and damage, and most of the current in the circuit will pass more
  • the thick copper plate greatly reduces on-resistance and parasitic inductance;
  • the position deviation of the chip can be compensated by adjusting the position of the copper strip, which reduces the requirements on the positioning process, which means simplifying
  • the processing technology improves the yield rate of product production at the same time.

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)

Abstract

本发明提供一种功率半导体模块，包括金属底板、绝缘散热材料层、芯片、绑定板、硅胶、外壳，所述绑定板包括铜板、铜带，所述铜板通过焊接与铜带连接，所述绑定板用于各部件的电路连接，所述金属底板通过焊锡与绝缘散热材料层连接，所述芯片通过焊锡与绝缘散热材料层连接，所述芯片与铜带连接，所述铜带与绝缘散热材料层连接。通过本发明，以解决现有技术存在的较厚的铜框架应用在功率半导体模块封装中冷热变化时给芯片带来的机械应力的问题。

Description

一种功率半导体模块 技术领域
本发明涉及功率半导体模块封装技术领域，具体地说涉及一种功率半导体模块。
背景技术
在电源、电力电子变换器应用中，功率半导体(IGBT，MOSFET，SiC，GaN等)器件因为被广泛采用，在功率较大的场合下一般使用模块的封装形式。功率模块主要由金属底板、焊接层、DBC(双面覆铜陶瓷基板)、AMB(箔钎焊的覆铜陶瓷基板)、绝缘散热树脂薄膜或者其他绝缘散热材料、铜框架、外壳以及硅胶等组成，如图2、图3。铜的导电能力强可以减小导通电阻和寄生电感，同时铜框架和芯片的接触面积大，并且热膨胀系数为16.9x10 -6/K，远低于铝(热膨胀系数为23x10 -6/K)，更加接近芯片(热膨胀系数为2x10 -6/K到4x10 -6/K),这样可以增强功率循环寿命。铜框架结合的方式也有一系列的缺点，第一，铜框架一般为使用专用模具，冲压制造，成本较高。第二，为了减小导通电阻，必须使用比较厚的铜框架，但是比较厚的铜框架可能与芯片的接触面在冷热变化时给芯片带来比较大的机械应力，严重时引起芯片破裂损坏。第三，多个芯片在连接到DBC或者其他绝缘散热材料的时候，各个芯片所在位置可能产生偏差，而铜框架一经加工就无法调整各个接触面的位置，可能在加工时产生位置偏移，带来不良品，为了减小不良需要精确的芯片和框架的定位工艺。
发明内容
本发明提供一种功率半导体模块，以解决现有技术存在的较厚的铜框架应用在功率半导体模块封装中冷热变化时给芯片带来的机械应力的问题。
为解决上述技术问题，本发明提供一种功率半导体模块，包括金属底板、绝缘散热材料层、芯片、绑定板、硅胶、外壳，所述绑定板包括铜板、铜带，所述铜板通过焊接与铜带连接，所述绑定板用于各部件的电路连接，所述金属底板通过焊锡与绝缘散热材料层连接，所述芯片通过焊锡与绝缘散热材料层连接，所述芯片与铜带连接，所述铜带与绝缘散热材料层连接。
所述外壳与金属底板通过点胶工艺连接。
所述硅胶填充于外壳内，防腐防潮，保护内部电路，对内部各部件进行高压隔离。
所述铜板通过激光焊接、超音波焊接与铜带连接。
所述芯片通过焊接或者烧结与铜带连接，所述铜带通过焊接或者烧结与绝缘散热材料层 连接。
本发明带来的有益效果：一、与现有技术相比，本发明的功率半导体模块里，与芯片接触的铜带在冷热变化时，给芯片带来的机械应力小，不会引起芯片破裂损坏，电路的大部分电流通过较厚的铜板，大大减少导通电阻，也降低了寄生电感；二、可以根据芯片的偏差位置，可以通过调节铜带的位置来补偿芯片的位置偏差，减低了对定位工艺的要求，意味着简化加工工艺，同时提高了产品生产的良率。
附图说明
图1是根据本发明实施例的功率半导体模块的整体结构示意图
图2是使用铜框架的功率半导体模块的整体结构示意图
图3是使用铜框架的功率半导体模块的示意图
图4是根据本发明实施例的功率半导体模块的部分结构示意图一
图5是根据本发明实施例的绑定板的结构示意图一
图6是根据本发明实施例的绑定板的结构示意图二
图7是根据本发明实施例的功率半导体模块的部分结构示意图二
图8是根据本发明实施例四的功率半导体模块的结构示意图
其中，1-金属底板，2-绝缘散热材料层，3-芯片，4-绑定板，5-硅胶，6-外壳，7-铜板，8-铜带。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下结合附图及具体实施例，对本发明作进一步地详细说明。
实施例一
如图1、图4、图5所示，本发明提供一种功率半导体模块，包括金属底板1、绝缘散热材料层2、芯片3、绑定板4、硅胶5、外壳6，所述绑定板4包括铜板7、铜带8，所述铜板7通过焊接与铜带8连接，所述绑定板4用于各部件的电路连接，所述金属底板1通过焊锡与绝缘散热材料层2连接，所述芯片3通过焊锡与绝缘散热材料层2连接，所述芯片3与铜带8连接，所述铜带8与绝缘散热材料层2连接。
进一步来说，所述外壳6与金属底板1通过点胶工艺连接。
进一步来说，所述硅胶5填充于外壳6内，防腐防潮，保护内部电路，对内部各部件进行高压隔离。
进一步来说，所述铜板7通过激光焊接、超音波焊接与铜带8连接。
进一步来说，所述芯片3通过焊接或者烧结与铜带8连接，所述铜带8通过焊接或者烧结与绝缘散热材料层2连接。
所述铜板7的厚度为1mm-2mm，所述铜带8的厚度为0.3mm-0.8mm。
实施例二
如图1、图6所示，本发明提供一种功率半导体模块，包括金属底板1、绝缘散热材料层2、芯片3、绑定板4、硅胶5、外壳6，所述绑定板4包括铜板7、铜带8，所述铜板7通过焊接与铜带8连接，所述绑定板4用于各部件的电路连接，所述金属底板1通过焊锡与绝缘散热材料层2连接，所述芯片3通过焊锡与绝缘散热材料层2连接，所述芯片3与铜带8连接，所述铜带8与绝缘散热材料层2连接。
进一步来说，所述外壳6与金属底板1通过点胶工艺连接。
进一步来说，所述硅胶5填充于外壳6内，防腐防潮，保护内部电路，对内部各部件进行高压隔离。
进一步来说，所述铜板7通过激光焊接、超音波焊接与铜带8连接。
进一步来说，所述芯片3通过焊接或者烧结与铜带8连接，所述铜带8通过焊接或者烧结与绝缘散热材料层2连接。
所述铜板7的厚度为1mm-2mm，所述铜带8的厚度为0.5mm-1mm。
将所述铜带8与芯片3接触的面研磨，消除偏差，加大了铜带8与芯片3接触的面积。同时通过进一步减薄与芯片3接触面的铜带8的厚度，减缓铜带8与芯片3结合时的机械应力，进一步提高可靠性。
实施例三
如图1、图7所示，本发明提供一种功率半导体模块，包括金属底板1、绝缘散热材料层2、芯片3、绑定板4、硅胶5、外壳6，所述绑定板4包括铜板7、铜带8，所述铜板7通过焊接与铜带8连接，所述绑定板4用于各部件的电路连接，所述金属底板1通过焊锡与绝缘散热材料层2连接，所述芯片3通过焊锡与绝缘散热材料层2连接，所述芯片3与铜带8连接，所述铜带8与绝缘散热材料层2连接。
进一步来说，所述外壳6与金属底板1通过点胶工艺连接。
进一步来说，所述硅胶5填充于外壳6内，防腐防潮，保护内部电路，对内部各部件进行高压隔离。
进一步来说，所述铜板7通过激光焊接、超音波焊接与铜带8连接。
进一步来说，所述芯片3通过焊接或者烧结与铜带8连接，所述铜带8通过焊接或者烧 结与绝缘散热材料层2连接。
所述铜板7的厚度为1mm-2mm，所述铜带8的厚度为0.3mm-0.8mm。
将所述铜板7与主电极端子形成一体结构。
图4中，铜板7与用于连接外部电路的电极端子是分开的结构，这样的结构带来了额外的电阻和寄生电感。本实施例中，通过将铜板7与主电极端子形成一体结构，进一步减小电阻和寄生电感。
实施例四
如图8所示，本发明提供一种功率半导体模块，包括金属底板1、绝缘散热材料层2、芯片3、绑定板4，所述绑定板4包括铜板7、铜带8，所述铜板7通过焊接与铜带8连接，所述绑定板4用于各部件的电路连接，所述金属底板1通过焊锡与绝缘散热材料层2连接，所述芯片3通过焊锡与绝缘散热材料层2连接，所述芯片3与铜带8连接，所述铜带8与绝缘散热材料层2连接。
进一步来说，所述铜板7通过激光焊接、超音波焊接与铜带8连接。
进一步来说，所述芯片3通过焊接或者烧结与铜带8连接，所述铜带8通过焊接或者烧结与绝缘散热材料层2连接。
所述铜板7的厚度为1mm-2mm，所述铜带8的厚度为0.3mm-0.8mm。
半导体模块的封装形式采用树脂材料的塑封方式，根据外形及参数设计需要，使用专用的模具，将树脂灌入其中，将半导体模块的芯片3、绝缘散热材料层2、绑定板4封装固定，即图一中的5和6，使用一体化的树脂材料代替，此一体化塑封方法可以省去硅胶和壳体，简化了生产工序，生产效率更高，产品可靠性更好。
综上所述，一、本发明的功率半导体模块里，与芯片接触的铜带在冷热变化时，给芯片带来的机械应力小，不会引起芯片破裂损坏，电路的大部分电流通过较厚的铜板，大大减少导通电阻，也降低了寄生电感；二、可以根据芯片的偏差位置，可以通过调节铜带的位置来补偿芯片的位置偏差，减低了对定位工艺的要求，意味着简化加工工艺，同时提高了产品生产的良率。
以上所述仅为本发明的实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的权利要求范围之内。

Claims (5)

  1. 一种功率半导体模块，包括金属底板(1)、绝缘散热材料层(2)、芯片(3)、绑定板(4)、硅胶(5)、外壳(6)，其特征在于：所述绑定板(4)包括铜板(7)、铜带(8)，所述铜板(7)通过焊接与铜带(8)连接，所述绑定板(4)用于各部件的电路连接，所述金属底板(1)通过焊锡与绝缘散热材料层(2)连接，所述芯片(3)通过焊锡与绝缘散热材料层(2)连接，所述芯片(3)与铜带(8)连接，所述铜带(8)与绝缘散热材料层(2)连接。
  2. 如权利要求1所述的功率半导体模块，其特征在于，所述外壳(6)与金属底板(1)通过点胶工艺连接。
  3. 如权利要求1所述的功率半导体模块，其特征在于，所述硅胶(5)填充于外壳(6)内，防腐防潮，保护内部电路，对内部各部件进行高压隔离。
  4. 如权利要求1所述的功率半导体模块，其特征在于，所述铜板(7)通过激光焊接、超音波焊接与铜带(8)连接。
  5. 如权利要求4所述的功率半导体模块，其特征在于，所述芯片(3)通过焊接或者烧结与铜带(8)连接，所述铜带(8)通过焊接或者烧结与绝缘散热材料层(2)连接。
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* Cited by examiner, † Cited by third party
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CN114724960A (zh) * 2022-04-08 2022-07-08 淄博美林电子有限公司 基于复合铜基板结构功率模块的封装工艺及其复合铜基板结构
DE102022205701A1 (de) 2022-06-03 2023-12-14 Zf Friedrichshafen Ag Leistungselementintegrationsmodul

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JP2023527378A (ja) 2023-06-28
EP4148778B1 (en) 2025-01-01

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