WO2021258457A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2021258457A1
WO2021258457A1 PCT/CN2020/103058 CN2020103058W WO2021258457A1 WO 2021258457 A1 WO2021258457 A1 WO 2021258457A1 CN 2020103058 W CN2020103058 W CN 2020103058W WO 2021258457 A1 WO2021258457 A1 WO 2021258457A1
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WO
WIPO (PCT)
Prior art keywords
layer
display panel
substrate
driving device
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2020/103058
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English (en)
French (fr)
Inventor
赵慧慧
鲜于文旭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to KR1020217015774A priority Critical patent/KR102727791B1/ko
Priority to JP2021542514A priority patent/JP7457717B2/ja
Priority to EP20929681.3A priority patent/EP4170635A4/en
Priority to US17/058,150 priority patent/US11974471B2/en
Publication of WO2021258457A1 publication Critical patent/WO2021258457A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/127—Active-matrix OLED [AMOLED] displays comprising two substrates, e.g. display comprising OLED array and TFT driving circuitry on different substrates
    • H10K59/1275—Electrical connections of the two substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/129—Chiplets
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/127—Active-matrix OLED [AMOLED] displays comprising two substrates, e.g. display comprising OLED array and TFT driving circuitry on different substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • This application relates to the display field, and in particular to a display panel and a display device.
  • the lower frame of the existing mobile phone display panel generally adopts COF (Chip on FPC) or COP (Chip On Pi) technology sets the position of the driver chip, which makes the lower frame spacing of the display panel smaller.
  • COF Chip on FPC
  • COP Chip On Pi
  • the present application provides a display panel and a display device to solve the technical problem that the frame spacing of the existing display panel is too large.
  • the application provides a display panel, which includes a first substrate, a first driving circuit layer on the first substrate, a second substrate on the first driving circuit layer, and a second substrate on the first driving circuit layer.
  • the orthographic projection of the gate driving device and the source driving device in the first driving circuit layer on the first substrate is located in the display area of the display panel.
  • the first driving circuit layer includes the gate driving device located on at least one side of the display panel, and the gate driving device includes at least one gate driving unit, one gate The pole driving unit is electrically connected to at least one scan line of the second driving circuit layer through a first via;
  • the second driving circuit layer includes the source driving device located on at least one side of the display panel, the source driving device includes at least one source driving unit, and one source driving unit passes through a second via hole Electrically connected to at least one data line of the second driving circuit layer;
  • first via hole and the second via hole penetrate the second substrate and part of the second driving circuit layer.
  • the second driving circuit layer includes an active layer on the second substrate, a gate insulating layer on the active layer, and a gate insulating layer on the gate insulating layer.
  • the first via hole penetrates the gate insulating layer and the second substrate
  • the second via hole penetrates the inter-insulating layer, the gate insulating layer, and the second substrate.
  • the first via hole and the second via hole are arranged close to the edge of the display panel.
  • the display panel further includes a first fan-out wiring connecting the gate driving device and the display panel bonding layer, and connecting the source driving device and the display panel bonding layer.
  • the first fan-out trace is electrically connected to the gate driving device through a third via hole, and the second fan-out trace is electrically connected to the source driving device through a fourth via hole;
  • first fan-out wiring and the second fan-out wiring are located in the first substrate.
  • the third via hole and the fourth via hole penetrate the first driving circuit layer and the first substrate.
  • the first driving circuit layer includes a first gate driving device located on the first side of the display panel, and a second gate driving device located on the third side of the display panel , And a first source driving device located on the second side of the display panel;
  • the orthographic projection of the bonding layer of the display panel on the first driving circuit layer is located in the vicinity of the first gate driving device, the second gate driving device, and the first source driving device Into the area.
  • the gate driving device and the source driving device are located in a non-pixel area between adjacent pixel units of the display panel.
  • the first substrate and the second substrate are made of flexible materials, and the thickness of the first substrate and the second substrate is 1 micrometer to 10 micrometers.
  • the display panel further includes a light emitting device layer on the second driving circuit layer and an encapsulation layer on the light emitting device layer.
  • the display device includes a display panel, and a polarizer layer and a cover layer on the display panel.
  • the display panel includes a first substrate and is located on the first substrate.
  • the orthographic projection of the gate driving device and the source driving device in the first driving circuit layer on the first substrate is located in the display area of the display panel.
  • the first driving circuit layer includes the gate driving device located on at least one side of the display panel, and the gate driving device includes at least one gate driving unit, one gate The pole driving unit is electrically connected to at least one scan line of the second driving circuit layer through a first via;
  • the second driving circuit layer includes the source driving device located on at least one side of the display panel, the source driving device includes at least one source driving unit, and one source driving unit passes through a second via hole Electrically connected to at least one data line of the second driving circuit layer;
  • first via hole and the second via hole penetrate the second substrate and part of the second driving circuit layer.
  • the second driving circuit layer includes an active layer on the second substrate, a gate insulating layer on the active layer, and a gate insulating layer on the gate insulating layer.
  • the first via hole penetrates the gate insulating layer and the second substrate
  • the second via hole penetrates the inter-insulating layer, the gate insulating layer, and the second substrate.
  • the first via hole and the second via hole are arranged close to the edge of the display panel.
  • the display panel further includes a first fan-out wiring connecting the gate driving device and the display panel bonding layer, and connecting the source driving device and the display panel bonding layer.
  • the first fan-out trace is electrically connected to the gate driving device through a third via hole, and the second fan-out trace is electrically connected to the source driving device through a fourth via hole;
  • first fan-out wiring and the second fan-out wiring are located in the first substrate.
  • the third via hole and the fourth via hole penetrate the first driving circuit layer and the first substrate.
  • the first driving circuit layer includes a first gate driving device located on the first side of the display panel, and a second gate driving device located on the third side of the display panel , And a first source driving device located on the second side of the display panel;
  • the orthographic projection of the bonding layer of the display panel on the first driving circuit layer is located in the vicinity of the first gate driving device, the second gate driving device, and the first source driving device Into the area.
  • the gate driving device and the source driving device are located in a non-pixel area between adjacent pixel units of the display panel.
  • the first substrate and the second substrate are made of flexible materials, and the thickness of the first substrate and the second substrate is 1 micrometer to 10 micrometers.
  • the display panel further includes a light emitting device layer on the second driving circuit layer and an encapsulation layer on the light emitting device layer.
  • the gate driving device and the source driving device of the display panel are arranged below the array driving layer of the display panel, and the gate driving device and the source driving device are arranged in the first
  • the orthographic projection on a substrate is located in the display area of the display panel, and the original source driving devices and gate driving devices occupying the frame spacing are removed, and the narrow frame design of the display panel is realized.
  • FIG. 1 is a cross-sectional structure diagram of a display panel of this application
  • FIG. 2 is a top view of the structure of the first driving circuit layer of the display panel of the present application.
  • Figure 3 is a schematic diagram of the hierarchical structure of the display panel of this application.
  • FIG. 4 is a schematic diagram of the structure of the binding layer of the display panel of this application.
  • the lower frame of the existing mobile phone display panel generally adopts the COF or COP process to set the position of the driving chip, so that the lower frame spacing of the display panel is smaller.
  • the bending area and the GOA circuits located on both sides of the display panel still occupy a certain distance, and it is impossible to further reduce the frame.
  • the present application provides a display panel 100, which includes a first substrate 1010, a first driving circuit layer 20 located on the first substrate 10, located on the first driving circuit A second substrate 30 on the layer 20, a second driving circuit layer 40 on the second substrate 30, and a pixel electrode layer on the second driving circuit layer 40;
  • the orthographic projection of the gate driving device 21 and the source driving device 22 in the first driving circuit layer 20 on the first substrate 10 is located in the display area of the display panel 100.
  • the gate drive device 21 and the source drive device 22 of the display panel 100 are arranged below the array drive layer of the display panel 100, and the gate drive device 21 and the source drive device
  • the orthographic projection of the device 22 on the first substrate 10 is located in the display area of the display panel 100.
  • the source driving device 22 and the gate driving device 21 that originally occupy the frame spacing are removed, so that the display panel 100 is narrow. Border design.
  • the technical solution of the present application can be applied to the OLED display panel 100 or the LCD display panel 100. Different types of display panels 100 correspond to different structures.
  • the technical solution of the present application will now be described with reference to specific embodiments, taking the OLED display panel 100 as an example .
  • the display panel 100 includes a first substrate 10, a first driving circuit layer 20 on the first substrate 10, and a second substrate 30 on the first driving circuit layer 20. , A second driving circuit layer 40 on the second substrate 30, a light emitting device layer 50 on the second driving circuit layer 40, and an encapsulation layer 60 on the light emitting device layer 50.
  • the first substrate 10 and the second substrate 30 may be one of a rigid substrate or a flexible substrate.
  • the materials of the first substrate 10 and the second substrate 30 may be made of materials such as glass and quartz.
  • the first substrate 10 and the second substrate 30 may be made of materials such as polyimide.
  • the substrate structure can be configured as a flexible substrate, which is not described in detail here.
  • the second driving circuit layer 40 includes a plurality of second thin film transistors 41.
  • the second thin film transistor 41 may be of an etch-stop type, a back-channel etch type, or a top-gate thin film transistor type, which is not specifically limited.
  • the second thin film transistor 41 of the top gate thin film transistor type may include a buffer layer 401 on the second substrate 30, an active layer on the buffer layer 401, and a buffer layer on the active layer.
  • the above-mentioned top-gate thin film transistor is not limited to a single-gate structure, and can also be configured as a double-gate structure, etc., which will be described in detail here.
  • the light-emitting device layer 50 includes an anode layer 51, a light-emitting layer 52, and a cathode layer 53 formed on the second driving circuit layer 40, where the anode layer 51 is the aforementioned pixel electrode layer.
  • the anode layer 51 is formed on the flat layer 404.
  • the anode layer 51 is mainly used to provide holes for absorbing electrons.
  • a top-emission OLED device is taken as an example for description. Therefore, the anode layer 51 may be a non-transparent or transparent metal electrode.
  • the light-emitting layer 52 is formed on the anode layer 51.
  • the light-emitting layer 52 is divided into a plurality of light-emitting units by the pixel definition layer 54.
  • the cathode layer 53 is formed on the light-emitting layer 52.
  • the cathode layer 53 covers the light-emitting layer 52 and the pixel definition layer 54 on the flat layer 404.
  • the materials of the anode layer 51 and the cathode layer 53 can be limited according to the light-emitting type of the display panel 100.
  • the anode layer 51 may be composed of a totally reflective material
  • the cathode layer 53 may be composed of a semi-reflective material.
  • the materials of the cathode layer 53 and the anode layer 51 are exchanged.
  • the light-emitting device layer 50 forms a microcavity effect through the total reflection and half reflection of the anode layer 51 and the cathode layer 53 to improve the luminous efficiency of the light-emitting device layer 50.
  • the devices corresponding to the first driving circuit layer 20 can only be arranged in the display panel 100.
  • the non-transmissive area, while the top-emitting display panel 100 does not have the above limitation. Therefore, compared with the bottom emission type display panel 100, the top emission type display panel 100 has a larger aperture ratio.
  • the encapsulation layer 60 may be a thin film encapsulation layer 60, which may include a first inorganic layer, a first organic layer on the first inorganic layer, and a first organic layer on the first organic layer. Two inorganic layers. The specific structure is the same or similar to the prior art, and will not be repeated here.
  • the first driving circuit layer 20 is located between the first substrate 10 and the second substrate 30.
  • the first driving circuit layer 20 is similar to the second driving circuit layer 40.
  • the first driving circuit layer 20 is also provided with a plurality of first thin film transistors 201.
  • the structure of the first thin film transistor 201 can be referred to The second thin film transistor 41 in the second driving circuit layer 40 will not be repeated here.
  • the combination of a plurality of first thin film transistors 201 in the first driving circuit layer 20 may constitute a corresponding gate driving device 21 or a source driving device 22.
  • the first driving circuit layer 20 includes the gate driving device 21 located on at least one side of the display panel 100, and the gate driving device 21 includes at least one gate driving unit 213 One of the gate driving units 213 is electrically connected to at least one scan line 405 of the second driving circuit layer 40 through the first via 214.
  • the first driving circuit layer 20 may include a first gate driving device 211 located on the first side 701 of the display panel 100, and a first gate drive device 211 located on the third side 703 of the display panel 100.
  • Two gate driving devices 212, the first driving gate device and the second driving gate device are provided with a gate driving unit 213 composed of a plurality of thin film transistors, that is, a GOA unit.
  • One GOA unit can be used for one or Multiple scan lines 405 scan at the same time.
  • the type of the gate driving unit 213 in this embodiment can be 2T1C, 7T1C, etc. in the prior art, and there is no specific limitation here.
  • the first via 214 penetrates the second substrate 30 and part of the second driving circuit layer 40.
  • the first via 214 penetrates the gate insulating layer 402, the buffer layer 401, and the second substrate 30, so that the scan line 405 in the gate layer passes through the first via 214 and the second substrate 30.
  • the gate driving device 21 in the first driving circuit layer 20 is electrically connected.
  • the display panel 100 of this embodiment can be used by the gate driving devices 21 on both sides to input scanning signals into the panel at the same time, or the first gate driving device 211 can be used for For controlling the scan lines 405 of odd rows, the second gate driving device 212 is used to control the scan lines 405 of even rows, etc.
  • the specific scanning method is not described in detail in this application.
  • the second driving circuit layer 40 includes the source driving device 22 located on at least one side of the display panel 100, and the source driving device 22 includes at least one source driving unit 223 One of the source driving units 223 is electrically connected to at least one data line 406 of the second driving circuit layer 40 through the second via 224.
  • first side 701 and the third side 703 may be side frames of the display panel 100 opposite to each other.
  • the display panel 100 further includes a second side 702 and a fourth side 704 disposed opposite to the second side 702.
  • the second side 702 and the fourth side 704 may be an upper frame and The bottom border.
  • the first driving circuit layer 20 may include a first source driving device 221 located on the second side 702 of the display panel 100, and the data line 406 of the display panel 100 runs along the The direction of the first side 701 or the third side 703 extends toward the second side 702 and is electrically connected to the first source driving device 221 through the second via 224.
  • the source driving unit 223 in the first source driving device 221 may be electrically connected to at least one of the data lines 406.
  • the first driving circuit layer 20 may further include a second source driving device 22 located on the fourth side 704 of the display panel 100, part of the data line 406 and the first source
  • the driving device 221 is electrically connected, part of the data line 406 is electrically connected to the second source driving device 22, and the first source driving unit 223 and the second source driving unit 223 do not interfere with each other.
  • the second via 224 penetrates the second substrate 30 and part of the second driving circuit layer 40.
  • the second via hole 224 penetrates the inter insulating layer 403, the gate insulating layer 402, the buffer layer 401, and the second substrate 30, so that the data line 406 located in the source and drain layer
  • the second via 224 is electrically connected to the source driving device 22 in the first driving circuit layer 20.
  • the first via hole 214 and the second via hole 224 may be disposed close to the edge of the display panel 100.
  • the first via 214 and the second via 224 are arranged on the edge of the display panel 100 to avoid the influence of the via on the internal structure of the panel.
  • the display panel 100 may include a display layer 200 located on the first driving circuit layer 20, and a bonding layer 80 located on the side of the first driving circuit layer 20 away from the display layer 200 .
  • the binding layer 80 is located in the first substrate 10 or on a side of the first substrate 10 away from the light emitting device layer 50.
  • the orthographic projection of the bonding layer 80 on the first drive circuit layer 20 is located on the first gate drive device 211, the second gate drive device 212, and the first gate drive device 212. In the area enclosed by a source driving device 221 or/and the second source driving device 22.
  • the display panel 100 further includes a first fan-out wiring 81 connecting the gate driving device 21 and the bonding layer 80 of the display panel 100, and connecting the source driving device 22 and the The second fan-out wiring 82 of the display panel 100 is bound to the layer 80.
  • the first fan-out wiring 81 is electrically connected to the gate driving device 21 through a third via hole 83
  • the second fan-out wiring 82 is electrically connected to the source electrode through a fourth via hole 84.
  • the driving device 22 is electrically connected.
  • the first fan-out wiring 81 and the second fan-out wiring 82 in order to prevent the first fan-out wiring 81 and the second fan-out wiring 82 from being shorted to each signal line in the first driving layer, the first fan-out wiring 81 and the second fan-out wiring The two fan-out wires 82 can be arranged at the same layer as the bonding layer 80.
  • the first fan-out wiring 81 and the second fan-out wiring 82 may be located in the first substrate 10.
  • the third via 83 and the fourth via 84 penetrate the first driving circuit layer 20 and the first substrate 10.
  • the first fan-out trace 81 may extend along the bottom end of the gate driving device 21 close to the second side 702 toward the first terminal area of the bonding layer 80, and is connected to the first terminal area of the bonding layer 80.
  • the second fan-out wiring 82 is insulated.
  • the first fan-out trace 81 may extend from the bottom end of the gate driving device 21 close to the fourth side 704 to the second terminal area of the bonding area.
  • the technical solution of this embodiment can increase the pitch of each signal line in the first fan-out wiring 81 and the second fan-out wiring 82, and reduce the process and accuracy of the first fan-out wiring 81 and the second fan-out wiring 82. And to avoid the technical problems of short signal lines.
  • the bottom frame of the display panel 100 is generally bent to the side of the display panel 100 away from the light-emitting layer 52, and the space on the back of the display panel 100 is used to control the driving IC or
  • the display IC is set to reduce the bottom frame of the display panel 100.
  • the bending structure of the flexible display panel 100 still has a certain bending radius, the spacing of the lower frame of the display panel 100 cannot be eliminated.
  • the binding layer 80 of this embodiment is disposed on the side of the first substrate 10 away from the light-emitting layer 52 of the display panel 100, so that the source driving device 22 and the gate driving device 21 of the display panel 100 can pass through
  • the corresponding via hole is connected to the bonding layer 80, and the corresponding data signal is directly input or output from the bottom of the display panel 100, eliminating the spacing of the bottom frame of the panel, and achieving the spacing of the bottom frame of the display panel 100 as 0.
  • the gate driving device 21 and the source driving device 22 may be located between adjacent pixel units of the display panel 100. Non-pixel area between. Prevent the light emitted by the light-emitting layer 52 or the light source of the backlight module from being blocked by the corresponding gate driving device 21 and the source driving device 22.
  • the thickness of the first substrate 10 and the second substrate 30 is 1 micrometer to 10 micrometers. Since the technical solution of this embodiment requires the preparation of thin film transistors on or in a flexible substrate, a certain thickness basis can ensure the planarization of the panel during the manufacturing process. In addition, the flexible substrate can also increase the bending resistance or stress relief of the panel.
  • the data line 406 or the scan line 405 is electrically connected to the source and drain of each driving device in the first driving circuit layer 20 through corresponding vias, and then passes through the first driving circuit layer.
  • the signal lines in the same layer as the source and drain layers in 20 are transmitted to the bonding layer 80.
  • this application only uses the above connection method as an example for a brief description.
  • the gate layer, active layer and other metal layers in the first thin film transistor 201 can all be used as the transmission film layer of the data signal. It is not limited to the above-mentioned embodiments of this application.
  • the gate drive device 21 and the source drive device 22 of the display panel 100 are arranged below the array drive layer of the display panel 100, and the gate drive device 21 and the source drive device
  • the orthographic projection of the device 22 on the first substrate 10 is located in the display area of the display panel 100.
  • the source driving device 22 and the gate driving device 21 that originally occupy the frame spacing are removed, so that the display panel 100 is narrow.
  • the frame design can make the display panel 100 all display areas.
  • the application also proposes a display device, wherein the display device includes the above-mentioned display panel and a polarizer layer and a cover layer on the display panel.
  • the working principle of the display device in this embodiment is the same as or similar to the working principle of the above-mentioned display panel, and will not be repeated here.
  • the display panel includes a first substrate, a first driving circuit layer on the first substrate, and a second substrate on the first driving circuit layer. , A second driving circuit layer on the second substrate, and a pixel electrode layer on the second driving circuit layer.
  • the gate driving device and the source driving device of the display panel are arranged below the array driving layer of the display panel, and the gate driving device and the source driving device are arranged in the first
  • the orthographic projection on a substrate is located in the display area of the display panel, and the original source driving devices and gate driving devices occupying the frame spacing are removed, and the narrow frame design of the display panel is realized.

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Abstract

本申请提出了一种显示面板及显示装置，该显示面板包括第一衬底、位于该第一衬底上的第一驱动电路层、位于该第一驱动电路层上的第二衬底、位于该第二衬底上的第二驱动电路层、及位于该第二驱动电路层上的像素电极层。

Description

显示面板及显示装置 技术领域
本申请涉及显示领域，特别涉及一种显示面板及显示装置。
 背景技术
随着显示行业技术的发展，用户对显示面板的外观设计要求越来越高，比如窄边框的设计。
现有手机显示面板的下边框一般采用COF（Chip on FPC）或COP（Chip on Pi）的工艺设置驱动芯片的位置，使得显示面板的下边框间距更小。但是弯折区及位于显示面板两侧GOA电路还是占据着一定的间距，无法进一步实现边框的缩小。
因此，亟需一种显示面板以解决上述技术问题。
 技术问题
本申请提供一种显示面板及显示装置，以解决现有显示面板边框间距过大的技术问题。
 技术解决方案
本申请提供了一种显示面板，其包括第一衬底、位于所述第一衬底上的第一驱动电路层、位于所述第一驱动电路层上的第二衬底、位于所述第二衬底上的第二驱动电路层、及位于所述第二驱动电路层上的像素电极层；
其中，所述第一驱动电路层中的栅极驱动器件及源极驱动器件在所述第一衬底上的正投影位于所述显示面板的显示区内。
在本申请的显示面板中，所述第一驱动电路层包括位于所述显示面板至少一侧的所述栅极驱动器件，所述栅极驱动器件包括至少一栅极驱动单元，一所述栅极驱动单元通过第一过孔与至少一条所述第二驱动电路层的扫描线电连接；
所述第二驱动电路层包括位于所述显示面板至少一侧的所述源极驱动器件，所述源极驱动器件包括至少一源极驱动单元，一所述源极驱动单元通过第二过孔与至少一条所述第二驱动电路层的数据线电连接；
其中，所述第一过孔及所述第二过孔贯穿所述第二衬底及部分所述第二驱动电路层。
在本申请的显示面板中，所述第二驱动电路层包括位于所述第二衬底上的有源层、位于所述有源层上的栅绝缘层、位于所述栅绝缘层上的栅极层、位于所述栅极层上的间绝缘层、位于所述间绝缘层上的源漏极层、位于所述源漏极层上的平坦层；
其中，所述第一过孔贯穿所述栅绝缘层及所述第二衬底，所述第二过孔贯穿所述间绝缘层、所述栅绝缘层及所述第二衬底。
在本申请的显示面板中，所述第一过孔及所述第二过孔靠近所述显示面板边缘设置。
在本申请的显示面板中，所述显示面板还包括连接所述栅极驱动器件与所述显示面板绑定层的第一扇出走线、及连接所述源极驱动器件与所述显示面板绑定层的第二扇出走线；
所述第一扇出走线通过第三过孔与所述栅极驱动器件电连接，所述第二扇出走线通过第四过孔与所述源极驱动器件电连接；
其中，所述第一扇出走线与所述第二扇出走线位于所述第一衬底内。
在本申请的显示面板中，所述第三过孔及所述第四过孔贯穿所述第一驱动电路层及所述第一衬底。
在本申请的显示面板中，所述第一驱动电路层包括位于所述显示面板第一侧边的第一栅极驱动器件、及位于所述显示面板第三侧边的第二栅极驱动器件，以及位于所述显示面板第二侧边的第一源极驱动器件；
所述显示面板的绑定层在所述第一驱动电路层上的正投影位于所述第一栅极驱动器件、所述第二栅极驱动器件、及所述第一源极驱动器件所围成的区域内。
在本申请的显示面板中，所述栅极驱动器件及所述源极驱动器件位于所述显示面板相邻像素单元之间的非像素区。
在本申请的显示面板中，所述第一衬底及所述第二衬底的由柔性材料构成，所述第一衬底及所述第二衬底的厚度为1微米~10微米。
在本申请的显示面板中，所述显示面板还包括位于所述第二驱动电路层上的发光器件层及位于所述发光器件层上的封装层。
本申请还提出了一种显示装置，所述显示装置包括显示面板、及位于所述显示面板上的偏光片层及盖板层，所述显示面板包括第一衬底、位于所述第一衬底上的第一驱动电路层、位于所述第一驱动电路层上的第二衬底、位于所述第二衬底上的第二驱动电路层、及位于所述第二驱动电路层上的像素电极层；
其中，所述第一驱动电路层中的栅极驱动器件及源极驱动器件在所述第一衬底上的正投影位于所述显示面板的显示区内。
在本申请的显示装置中，所述第一驱动电路层包括位于所述显示面板至少一侧的所述栅极驱动器件，所述栅极驱动器件包括至少一栅极驱动单元，一所述栅极驱动单元通过第一过孔与至少一条所述第二驱动电路层的扫描线电连接；
所述第二驱动电路层包括位于所述显示面板至少一侧的所述源极驱动器件，所述源极驱动器件包括至少一源极驱动单元，一所述源极驱动单元通过第二过孔与至少一条所述第二驱动电路层的数据线电连接；
其中，所述第一过孔及所述第二过孔贯穿所述第二衬底及部分所述第二驱动电路层。
在本申请的显示装置中，所述第二驱动电路层包括位于所述第二衬底上的有源层、位于所述有源层上的栅绝缘层、位于所述栅绝缘层上的栅极层、位于所述栅极层上的间绝缘层、位于所述间绝缘层上的源漏极层、位于所述源漏极层上的平坦层；
其中，所述第一过孔贯穿所述栅绝缘层及所述第二衬底，所述第二过孔贯穿所述间绝缘层、所述栅绝缘层及所述第二衬底。
在本申请的显示装置中，所述第一过孔及所述第二过孔靠近所述显示面板边缘设置。
在本申请的显示装置中，所述显示面板还包括连接所述栅极驱动器件与所述显示面板绑定层的第一扇出走线、及连接所述源极驱动器件与所述显示面板绑定层的第二扇出走线；
所述第一扇出走线通过第三过孔与所述栅极驱动器件电连接，所述第二扇出走线通过第四过孔与所述源极驱动器件电连接；
其中，所述第一扇出走线与所述第二扇出走线位于所述第一衬底内。
在本申请的显示装置中，所述第三过孔及所述第四过孔贯穿所述第一驱动电路层及所述第一衬底。
在本申请的显示装置中，所述第一驱动电路层包括位于所述显示面板第一侧边的第一栅极驱动器件、及位于所述显示面板第三侧边的第二栅极驱动器件，以及位于所述显示面板第二侧边的第一源极驱动器件；
所述显示面板的绑定层在所述第一驱动电路层上的正投影位于所述第一栅极驱动器件、所述第二栅极驱动器件、及所述第一源极驱动器件所围成的区域内。
在本申请的显示装置中，所述栅极驱动器件及所述源极驱动器件位于所述显示面板相邻像素单元之间的非像素区。
在本申请的显示装置中，所述第一衬底及所述第二衬底的由柔性材料构成，所述第一衬底及所述第二衬底的厚度为1微米~10微米。
在本申请的显示装置中，所述显示面板还包括位于所述第二驱动电路层上的发光器件层及位于所述发光器件层上的封装层。
 有益效果
本申请通过将所述显示面板的栅极驱动器件及源极驱动器件设置在所述显示面板的阵列驱动层的下方、以及使得所述栅极驱动器件及所述源极驱动器件在所述第一衬底上的正投影位于所述显示面板的显示区内，去除原有占据边框间距的源极驱动器件及栅极驱动器件，实现了显示面板窄边框设计。
 附图说明
图1为本申请显示面板的剖面结构图；
图2为本申请显示面板第一驱动电路层的俯视结构图；
图3为本申请显示面板分层结构示意图；
图4为本申请显示面板绑定层的结构示意图。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
现有手机显示面板的下边框一般采用COF或COP的工艺设置驱动芯片的位置，使得显示面板的下边框间距更小。但是弯折区及位于显示面板两侧GOA电路还是占据着一定的间距，无法进一步实现边框的缩小。本申请提出了下列技术方案以解决上述技术问题。
请参阅图1~图4，本申请提供了一种显示面板100，其包括第一衬底1010、位于所述第一衬底10上的第一驱动电路层20、位于所述第一驱动电路层20上的第二衬底30、位于所述第二衬底30上的第二驱动电路层40、及位于所述第二驱动电路层40上的像素电极层；
在本实施例中，所述第一驱动电路层20中的栅极驱动器件21及源极驱动器件22在所述第一衬底10上的正投影位于所述显示面板100的显示区内。
本申请通过将所述显示面板100的栅极驱动器件21及源极驱动器件22设置在所述显示面板100的阵列驱动层的下方、以及使得所述栅极驱动器件21及所述源极驱动器件22在所述第一衬底10上的正投影位于所述显示面板100的显示区内，去除原有占据边框间距的源极驱动器件22及栅极驱动器件21，实现了显示面板100窄边框设计。
本申请的技术方案可以应用于OLED显示面板100或者LCD显示面板100中，不同类型的显示面板100对应不同的结构，现结合具体实施例，以OLED显示面板100为例对本申请的技术方案进行描述。
请参阅图1，所述显示面板100包括第一衬底10、位于所述第一衬底10上的第一驱动电路层20、位于所述第一驱动电路层20上的第二衬底30、位于所述第二衬底30上的第二驱动电路层40、位于所述第二驱动电路层40上的发光器件层50、及位于所述发光器件层50上的封装层60。
在本实施例中，所述第一衬底10及所述第二衬底30可以为刚性衬底或柔性衬底中的一种。当所述第一衬底10及所述第二衬底30为刚性衬底时，所述第一衬底10及所述第二衬底30的材料可以为玻璃、石英等材料制备。当所述第一衬底10及所述第二衬底30为柔性衬底时，所述第一衬底10及所述第二衬底30可以为聚酰亚胺等材料。而在OLED显示面板100中，衬底结构可以设置为柔性衬底，此处不对其作详细介绍。
所述第二驱动电路层40包括多个第二薄膜晶体管41。所述第二薄膜晶体管41可以为蚀刻阻挡型、背沟道蚀刻型或顶栅薄膜晶体管型等结构，具体没有限制。例如顶栅薄膜晶体管型的所述第二薄膜晶体管41可以包括位于所述第二衬底30上的缓冲层401、位于所述缓冲层401上的有源层、位于所述有源层上的栅绝缘层402、位于所述栅绝缘层402上的栅极层、位于所述栅极层上的间绝缘层403、位于所述间绝缘层403上的源漏极层、及位于所述源漏极层上的平坦层404。
在本实施例中，上述顶栅薄膜晶体管不限于单栅极结构，还可以设置为双栅极结构等，此处再详细介绍。
请参阅图1，所述发光器件层50包括形成于所述第二驱动电路层40上的阳极层51、发光层52及阴极层53，此处所述阳极层51为前文的像素电极层。
所述阳极层51形成于所述平坦层404上。所述阳极层51主要用于提供吸收电子的空穴。在本实施例中，以顶发射型OLED器件为例进行说明，因此所述阳极层51可以为非透明或者透明的金属电极。所述发光层52形成于所述阳极层51上。所述发光层52被像素定义层54分割成多个发光单元。
所述阴极层53形成于所述发光层52上。所述阴极层53覆盖所述发光层52及位于所述平坦层404上的像素定义层54。
在本实施例中，根据所述显示面板100的发光类型可以对所述阳极层51及所述阴极层53的材料进行限定。例如，当所述显示面板100为顶发光型显示面板100时，所述阳极层51可以由全反射材料构成，所述阴极层53可以由半反射材料构成。当所述显示面板100为底发光型显示面板100时，所述阴极层53与所述阳极层51的材料互换。
其中，所述发光器件层50通过阳极层51与阴极层53的全反射与半反射以形成微腔效应，以提高所述发光器件层50的发光效率。
由于所述第一驱动电路层20中布置有大量的遮光金属层，因此若所述显示面板100为底发光型时，所述第一驱动电路层20对应的器件只能设置在显示面板100的非透光区，而顶发光型显示面板100则不具有上述限制。因此，与底发光型显示面板100相比，顶发光型显示面板100具有较大的开口率。
请参阅图1，所述封装层60可以为薄膜封装层60，其可以包括第一无机层、位于所述第一无机层上的第一有机层、以及位于所述第一有机层上的第二无机层。具体结构与现有技术相同或相似，此处不再赘述。
请参阅图1，第一驱动电路层20位于所述第一衬底10与所述第二衬底30之间。所述第一驱动电路层20与所述第二驱动电路层40相似，所述第一驱动电路层20同样设置有多个第一薄膜晶体管201，所述第一薄膜晶体管201的结构可以参阅所述第二驱动电路层40中的第二薄膜晶体管41，此处不再赘述。
在本实施例中，所述第一驱动电路层20中的多个第一薄膜晶体管201的组合可以构成相应的栅极驱动器件21或源极驱动器件22。
请参阅图1和图2，所述第一驱动电路层20包括位于所述显示面板100至少一侧的所述栅极驱动器件21，所述栅极驱动器件21包括至少一栅极驱动单元213，一所述栅极驱动单元213通过第一过孔214与至少一条所述第二驱动电路层40的扫描线405电连接。
在本实施例中，所述第一驱动电路层20可以包括位于所述显示面板100第一侧边701的第一栅极驱动器件211、及位于所述显示面板100第三侧边703的第二栅极驱动器件212，所述第一驱动栅极器件及所述第二驱动栅极器件内设置由多个薄膜晶体管构成的栅极驱动单元213，即GOA单元，一个GOA单元可以对一条或多条扫描线405同时扫描。本实施例中的栅极驱动单元213的类型可以为现有技术中2T1C、7T1C等，此处没有具体限制。
在本实施例中，所述第一过孔214贯穿所述第二衬底30及部分所述第二驱动电路层40。所述第一过孔214贯穿所述栅绝缘层402、所述缓冲层401及所述第二衬底30，使得所述栅极层中的扫描线405通过所述第一过孔214与所述第一驱动电路层20中的栅极驱动器件21电连接。
由于面板左右两侧均设置有栅极驱动器件21，因此本实施例的显示面板100可以是由两侧的栅极驱动器件21同时向面板内输入扫描信号，或者第一栅极驱动器件211用于控制奇数行的扫描线405，第二栅极驱动器件212用于控制偶数行的扫描线405等，具体的扫描方式本申请不作详细介绍。
请参阅图1和图2，所述第二驱动电路层40包括位于所述显示面板100至少一侧的所述源极驱动器件22，所述源极驱动器件22包括至少一源极驱动单元223，一所述源极驱动单元223通过第二过孔224与至少一条所述第二驱动电路层40的数据线406电连接。
在本实施例中，所述第一侧边701与所述第三侧边703可以为所述显示面板100相对设置的侧边框。所述显示面板100还包括第二侧边702和与所述第二侧边702相对设置的第四侧边704，所述第二侧边702与所述第四侧边704可以为上边框和底边框。
在本实施例中，所述第一驱动电路层20可以包括位于所述显示面板100所述第二侧边702的第一源极驱动器件221，所述显示面板100的数据线406沿所述第一侧边701或所述第三侧边703的方向向所述第二侧边702的延伸，以及通过所述第二过孔224与所述第一源极驱动器件221电连接。所述第一源极驱动器件221中的源极驱动单元223可以电连接至少一条所述数据线406。
在本实施例中，所述第一驱动电路层20还可以包括位于所述显示面板100第四侧边704的第二源极驱动器件22，部分所述数据线406与所述第一源极驱动器件221电连接，部分所述数据线406与所述第二源极驱动器件22电连接，所述第一源极驱动单元223与所述第二源极驱动单元223彼此之间不干扰。
在本实施例中，所述第二过孔224贯穿所述第二衬底30及部分所述第二驱动电路层40。所述第二过孔224贯穿所述间绝缘层403、所述栅绝缘层402、所述缓冲层401、及所述第二衬底30，使得位于所述源漏极层中的数据线406通过所述第二过孔224与所述第一驱动电路层20中的源极驱动器件22电连接。
请参阅图2，所述第一过孔214及所述第二过孔224可以靠近所述显示面板100边缘设置。将所述第一过孔214及所述第二过孔224设置所述显示面板100的边缘，可以避免过孔对面板内部结构的影响。
请参阅图1和3，所述显示面板100可以包括位于第一驱动电路层20上的显示层200、及位于所述第一驱动电路层20远离所述显示层200一侧的绑定层80。所述绑定层80位于所述第一衬底10内或位于所述第一衬底10远离所述发光器件层50的一侧。
在本实施例中，所述绑定层80在所述第一驱动电路层20上的正投影位于所述第一栅极驱动器件211、所述第二栅极驱动器件212、及所述第一源极驱动器件221或/和所述第二源极驱动器件22所围成的区域内。
请参阅图4，所述显示面板100还包括连接所述栅极驱动器件21与所述显示面板100绑定层80的第一扇出走线81、及连接所述源极驱动器件22与所述显示面板100绑定层80的第二扇出走线82。
在本实施例中，所述第一扇出走线81通过第三过孔83与所述栅极驱动器件21电连接，所述第二扇出走线82通过第四过孔84与所述源极驱动器件22电连接。
在本实施例中，为了避免所述第一扇出走线81及所述第二扇出走线82与第一驱动层中的各信号线短接，所述第一扇出走线81及所述第二扇出走线82可以与所述绑定层80同层设置。
请参阅图1，所述第一扇出走线81与所述第二扇出走线82可以位于所述第一衬底10内。所述第三过孔83及所述第四过孔84贯穿所述第一驱动电路层20及所述第一衬底10。
请参阅图4，所述第一扇出走线81可以沿所述栅极驱动器件21靠近所述第二侧边702的底端向所述绑定层80的第一端子区延伸，以及与所述第二扇出走线82绝缘设置。
在本实施例中，所述第一扇出走线81可以从所述栅极驱动器件21靠近所述第四侧边704的底端向所述绑定区的第二端子区延伸。本实施例的技术方案可以提高第一扇出走线81及所述第二扇出走线82中各信号线的间距，降低第一扇出走线81及第二扇出走线82的工艺及准确度，以及避免信号线出现短线的技术问题。
对于现有的窄边框的柔性显示面板100，一般通过将显示面板100的底边框弯折至显示面板100远离发光层52的一侧，利用显示面板100背面的空间，对面板上的驱动IC或者显示IC进行设置，以减小显示面板100的下边框。但是，由于柔性显示面板100的弯折结构还存在一定的弯折半径，导致显示面板100的下边框的间距无法消除。
本实施例的所述绑定层80设置于所述第一衬底10远离所述显示面板100发光层52的一侧，使得显示面板100的源极驱动器件22及栅极驱动器件21可以通过对应的过孔与所述绑定层80连接，直接从所述显示面板100的底部将对应的数据信号输入或输出，消除了面板下边框的间距，可以实现显示面板100的下边框的间距为0。
在上述实施例中，当所述显示面板100为底发光型或LCD显示面板100时，所述栅极驱动器件21及所述源极驱动器件22可以位于所述显示面板100相邻像素单元之间的非像素区。避免发光层52发出的光线或背光模组发光的光源被对应的所述栅极驱动器件21及所述源极驱动器件22遮挡。
在上述实施例中，所述第一衬底10及所述第二衬底30的厚度为1微米~10微米。由于本实施例的技术方案需要在柔性衬底上或者柔性衬底内进行薄膜晶体管的制备，因此一定的厚度基础才能保证制程过程中面板的平坦化。另外，柔性衬底同样可以增加面板的抗弯曲能力或者应力的释放等有点。
在上述实施例中，所述数据线406或所述扫描线405通过对应的过孔与所述第一驱动电路层20中的各驱动器件的源漏极电连接，再通过第一驱动电路层20中的与源漏极层同层的信号线传输至所述绑定层80中。另外，本申请仅仅以上述连接方式为例进行简单的说明，关于数据信号的传输，所述第一薄膜晶体管201中的栅极层、有源层等金属层均可以作为数据信号的传输膜层，不限定于本申请上述实施例。
本申请通过将所述显示面板100的栅极驱动器件21及源极驱动器件22设置在所述显示面板100的阵列驱动层的下方、以及使得所述栅极驱动器件21及所述源极驱动器件22在所述第一衬底10上的正投影位于所述显示面板100的显示区内，去除原有占据边框间距的源极驱动器件22及栅极驱动器件21，实现了显示面板100窄边框设计，可以使得所述显示面板100全部为显示区。
本申请还提出了一种显示装置，其中，所述显示装置包括上述显示面板及位于所述显示面板上的偏光片层及盖板层。本实施例中的所述显示装置的工作原理与上述显示面板的工作原理相同或相似，此处不再赘述。
本申请提出了一种显示面板及显示装置，该显示面板包括第一衬底、位于所述第一衬底上的第一驱动电路层、位于所述第一驱动电路层上的第二衬底、位于所述第二衬底上的第二驱动电路层、及位于所述第二驱动电路层上的像素电极层。本申请通过将所述显示面板的栅极驱动器件及源极驱动器件设置在所述显示面板的阵列驱动层的下方、以及使得所述栅极驱动器件及所述源极驱动器件在所述第一衬底上的正投影位于所述显示面板的显示区内，去除原有占据边框间距的源极驱动器件及栅极驱动器件，实现了显示面板窄边框设计。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种显示面板，其包括第一衬底、位于所述第一衬底上的第一驱动电路层、位于所述第一驱动电路层上的第二衬底、位于所述第二衬底上的第二驱动电路层、及位于所述第二驱动电路层上的像素电极层；
    其中，所述第一驱动电路层中的栅极驱动器件及源极驱动器件在所述第一衬底上的正投影位于所述显示面板的显示区内。
  2. 根据权利要求1所述的显示面板，其中，所述第一驱动电路层包括位于所述显示面板至少一侧的所述栅极驱动器件，所述栅极驱动器件包括至少一栅极驱动单元，一所述栅极驱动单元通过第一过孔与至少一条所述第二驱动电路层的扫描线电连接；
    所述第二驱动电路层包括位于所述显示面板至少一侧的所述源极驱动器件，所述源极驱动器件包括至少一源极驱动单元，一所述源极驱动单元通过第二过孔与至少一条所述第二驱动电路层的数据线电连接；
    其中，所述第一过孔及所述第二过孔贯穿所述第二衬底及部分所述第二驱动电路层。
  3. 根据权利要求2所述的显示面板，其中，所述第二驱动电路层包括位于所述第二衬底上的有源层、位于所述有源层上的栅绝缘层、位于所述栅绝缘层上的栅极层、位于所述栅极层上的间绝缘层、位于所述间绝缘层上的源漏极层、位于所述源漏极层上的平坦层；
    其中，所述第一过孔贯穿所述栅绝缘层及所述第二衬底，所述第二过孔贯穿所述间绝缘层、所述栅绝缘层及所述第二衬底。
  4. 根据权利要求2所述的显示面板，其中，所述第一过孔及所述第二过孔靠近所述显示面板边缘设置。
  5. 根据权利要求2所述的显示面板，其中，所述显示面板还包括连接所述栅极驱动器件与所述显示面板绑定层的第一扇出走线、及连接所述源极驱动器件与所述显示面板绑定层的第二扇出走线；
    所述第一扇出走线通过第三过孔与所述栅极驱动器件电连接，所述第二扇出走线通过第四过孔与所述源极驱动器件电连接；
    其中，所述第一扇出走线与所述第二扇出走线位于所述第一衬底内。
  6. 根据权利要求5所述的显示面板，其中，所述第三过孔及所述第四过孔贯穿所述第一驱动电路层及所述第一衬底。
  7. 根据权利要求2所述的显示面板，其中，所述第一驱动电路层包括位于所述显示面板第一侧边的第一栅极驱动器件、及位于所述显示面板第三侧边的第二栅极驱动器件，以及位于所述显示面板第二侧边的第一源极驱动器件；
    所述显示面板的绑定层在所述第一驱动电路层上的正投影位于所述第一栅极驱动器件、所述第二栅极驱动器件、及所述第一源极驱动器件所围成的区域内。
  8. 根据权利要求2所述的显示面板，其中，所述栅极驱动器件及所述源极驱动器件位于所述显示面板相邻像素单元之间的非像素区。
  9. 根据权利要求1所述的显示面板，其中，所述第一衬底及所述第二衬底由柔性材料构成，所述第一衬底及所述第二衬底的厚度为1微米~10微米。
  10. 根据权利要求1所述的显示面板，其中，所述显示面板还包括位于所述第二驱动电路层上的发光器件层及位于所述发光器件层上的封装层。
  11. 一种显示装置，所述显示装置包括显示面板、及位于所述显示面板上的偏光片层及盖板层，所述显示面板包括第一衬底、位于所述第一衬底上的第一驱动电路层、位于所述第一驱动电路层上的第二衬底、位于所述第二衬底上的第二驱动电路层、及位于所述第二驱动电路层上的像素电极层；
    其中，所述第一驱动电路层中的栅极驱动器件及源极驱动器件在所述第一衬底上的正投影位于所述显示面板的显示区内。
  12. 根据权利要求11所述的显示装置，其中，
    所述第一驱动电路层包括位于所述显示面板至少一侧的所述栅极驱动器件，所述栅极驱动器件包括至少一栅极驱动单元，一所述栅极驱动单元通过第一过孔与至少一条所述第二驱动电路层的扫描线电连接；
    所述第二驱动电路层包括位于所述显示面板至少一侧的所述源极驱动器件，所述源极驱动器件包括至少一源极驱动单元，一所述源极驱动单元通过第二过孔与至少一条所述第二驱动电路层的数据线电连接；
    其中，所述第一过孔及所述第二过孔贯穿所述第二衬底及部分所述第二驱动电路层。
  13. 根据权利要求12所述的显示装置，其中，
    所述第二驱动电路层包括位于所述第二衬底上的有源层、位于所述有源层上的栅绝缘层、位于所述栅绝缘层上的栅极层、位于所述栅极层上的间绝缘层、位于所述间绝缘层上的源漏极层、位于所述源漏极层上的平坦层；
    其中，所述第一过孔贯穿所述栅绝缘层及所述第二衬底，所述第二过孔贯穿所述间绝缘层、所述栅绝缘层及所述第二衬底。
  14. 根据权利要求12所述的显示装置，其中，所述第一过孔及所述第二过孔靠近所述显示面板边缘设置。
  15. 根据权利要求12所述的显示装置，其中，所述显示面板还包括连接所述栅极驱动器件与所述显示面板绑定层的第一扇出走线、及连接所述源极驱动器件与所述显示面板绑定层的第二扇出走线；
    所述第一扇出走线通过第三过孔与所述栅极驱动器件电连接，所述第二扇出走线通过第四过孔与所述源极驱动器件电连接；
    其中，所述第一扇出走线与所述第二扇出走线位于所述第一衬底内。
  16. 根据权利要求15所述的显示装置，其中，所述第三过孔及所述第四过孔贯穿所述第一驱动电路层及所述第一衬底。
  17. 根据权利要求12所述的显示装置，其中，所述第一驱动电路层包括位于所述显示面板第一侧边的第一栅极驱动器件、及位于所述显示面板第三侧边的第二栅极驱动器件，以及位于所述显示面板第二侧边的第一源极驱动器件；
    所述显示面板的绑定层在所述第一驱动电路层上的正投影位于所述第一栅极驱动器件、所述第二栅极驱动器件、及所述第一源极驱动器件所围成的区域内。
  18. 根据权利要求12所述的显示装置，其中，所述栅极驱动器件及所述源极驱动器件位于所述显示面板相邻像素单元之间的非像素区。
  19. 根据权利要求11所述的显示装置，其中，所述第一衬底及所述第二衬底由柔性材料构成，所述第一衬底及所述第二衬底的厚度为1微米~10微米。
  20. 根据权利要求11所述的显示装置，其中，所述显示面板还包括位于所述第二驱动电路层上的发光器件层及位于所述发光器件层上的封装层。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4239680A1 (en) * 2022-03-03 2023-09-06 Samsung Display Co., Ltd. Display device and tiled display device including the same

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112086049A (zh) * 2020-09-16 2020-12-15 武汉华星光电技术有限公司 显示面板以及电子设备
JP7650654B2 (ja) * 2020-12-22 2025-03-25 日本放送協会 表示装置及びその製造方法
US20230079382A1 (en) * 2021-02-01 2023-03-16 Boe Technology Group Co., Ltd. Driving Backplane, Method for Manufacturing Same and Display Device
CN113257143A (zh) * 2021-03-29 2021-08-13 北海惠科光电技术有限公司 一种显示面板、显示装置和显示面板的制造方法
CN116072010A (zh) * 2021-11-02 2023-05-05 武汉华星光电半导体显示技术有限公司 拼接显示面板和显示装置
CN114122051B (zh) * 2021-11-04 2023-07-25 武汉华星光电半导体显示技术有限公司 显示面板及其制作方法、显示装置
CN114284319B (zh) 2021-12-14 2023-09-26 武汉华星光电半导体显示技术有限公司 显示面板及电子设备
CN114335091A (zh) 2021-12-22 2022-04-12 深圳市华星光电半导体显示技术有限公司 柔性显示面板
CN114428427B (zh) * 2022-01-27 2023-10-03 Tcl华星光电技术有限公司 显示面板及显示装置
CN114725175A (zh) * 2022-04-06 2022-07-08 京东方科技集团股份有限公司 显示面板、拼接屏及显示装置
CN117918042A (zh) * 2022-05-12 2024-04-23 北京小米移动软件有限公司 Oled显示面板、oled显示面板的像素电路及显示设备
JP2023174320A (ja) * 2022-05-27 2023-12-07 キヤノン株式会社 発光装置、発光装置の製造方法、撮像装置、電子機器および移動体
CN115207054B (zh) * 2022-07-05 2024-12-27 武汉华星光电半导体显示技术有限公司 显示面板
KR20240097047A (ko) 2022-12-19 2024-06-27 삼성디스플레이 주식회사 표시 장치
KR20240119947A (ko) 2023-01-30 2024-08-07 삼성디스플레이 주식회사 화소 회로 및 화소 회로를 포함하는 표시 장치의 구동 방법
CN117457697B (zh) * 2023-02-07 2025-09-19 深圳市华星光电半导体显示技术有限公司 显示面板及拼接屏
CN116404011B (zh) * 2023-06-07 2024-05-28 惠科股份有限公司 显示面板和显示装置
CN119905065B (zh) * 2023-10-27 2025-09-30 武汉华星光电半导体显示技术有限公司 显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104867450A (zh) * 2015-06-05 2015-08-26 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN106662783A (zh) * 2014-04-30 2017-05-10 夏普株式会社 有源矩阵基板和具备该有源矩阵基板的显示装置
CN107256870A (zh) * 2017-06-09 2017-10-17 京东方科技集团股份有限公司 一种阵列基板及制作方法、柔性显示面板、显示装置
CN109192751A (zh) * 2017-06-29 2019-01-11 京东方科技集团股份有限公司 一种有机电致发光显示面板、其制作方法及显示装置
CN110211525A (zh) * 2019-05-27 2019-09-06 福建华佳彩有限公司 一种面板设计架构
WO2019220278A1 (ja) * 2018-05-17 2019-11-21 株式会社半導体エネルギー研究所 表示装置、及び電子機器

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5940072Y2 (ja) 1982-11-27 1984-11-12 義雄 川添 洋凧における骨材の連結具
JPWO2010073716A1 (ja) 2008-12-25 2012-06-14 株式会社ブリヂストン 情報表示用パネル
KR101456154B1 (ko) * 2009-08-25 2014-11-04 삼성디스플레이 주식회사 유기 발광 조명 장치
JP5304761B2 (ja) * 2010-09-28 2013-10-02 カシオ計算機株式会社 発光装置及び電子機器
JP5982094B2 (ja) * 2011-03-22 2016-08-31 セイコーエプソン株式会社 電気光学装置、投射型表示装置および電子機器
KR20120130397A (ko) * 2011-05-23 2012-12-03 삼성디스플레이 주식회사 렌즈 모듈 및 이를 갖는 표시 장치
KR102462742B1 (ko) 2013-12-02 2022-11-03 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치 및 그 제조방법
JP2015138612A (ja) * 2014-01-21 2015-07-30 株式会社ジャパンディスプレイ 有機エレクトロルミネセンス表示装置
US10582612B2 (en) * 2014-06-30 2020-03-03 Lg Display Co., Ltd. Flexible display device with reduced bend stress wires and manufacturing method for the same
CN104536229B (zh) * 2015-01-12 2017-02-01 京东方科技集团股份有限公司 一种阵列基板及显示面板
JP6661904B2 (ja) * 2015-07-01 2020-03-11 Jsr株式会社 表示装置、および表示装置の製造方法
US20170213872A1 (en) 2016-01-27 2017-07-27 Semiconductor Energy Laboratory Co., Ltd. Display device
KR20190010052A (ko) * 2017-07-20 2019-01-30 엘지전자 주식회사 디스플레이 디바이스
KR102452251B1 (ko) * 2017-08-04 2022-10-11 삼성디스플레이 주식회사 표시 장치
CN107978622B (zh) * 2017-11-22 2020-08-11 上海天马有机发光显示技术有限公司 一种阵列基板、显示面板和显示装置
KR20250083586A (ko) 2018-05-11 2025-06-10 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치 및 표시 장치의 제작 방법
CN108630144A (zh) * 2018-06-19 2018-10-09 武汉天马微电子有限公司 显示面板和显示装置
TWI686648B (zh) * 2019-01-08 2020-03-01 友達光電股份有限公司 顯示面板
CN109857279B (zh) * 2019-03-19 2022-04-12 厦门天马微电子有限公司 显示面板及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106662783A (zh) * 2014-04-30 2017-05-10 夏普株式会社 有源矩阵基板和具备该有源矩阵基板的显示装置
CN104867450A (zh) * 2015-06-05 2015-08-26 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
CN107256870A (zh) * 2017-06-09 2017-10-17 京东方科技集团股份有限公司 一种阵列基板及制作方法、柔性显示面板、显示装置
CN109192751A (zh) * 2017-06-29 2019-01-11 京东方科技集团股份有限公司 一种有机电致发光显示面板、其制作方法及显示装置
WO2019220278A1 (ja) * 2018-05-17 2019-11-21 株式会社半導体エネルギー研究所 表示装置、及び電子機器
CN110211525A (zh) * 2019-05-27 2019-09-06 福建华佳彩有限公司 一种面板设计架构

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4170635A4 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP4239680A1 (en) * 2022-03-03 2023-09-06 Samsung Display Co., Ltd. Display device and tiled display device including the same
US12354562B2 (en) 2022-03-03 2025-07-08 Samsung Display Co., Ltd. Display device and tiled display device including the same

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