WO2021258771A1 - 一种半导体器件及其制造方法 - Google Patents

一种半导体器件及其制造方法 Download PDF

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WO2021258771A1
WO2021258771A1 PCT/CN2021/078959 CN2021078959W WO2021258771A1 WO 2021258771 A1 WO2021258771 A1 WO 2021258771A1 CN 2021078959 W CN2021078959 W CN 2021078959W WO 2021258771 A1 WO2021258771 A1 WO 2021258771A1
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layer
channel layer
groove
adjustment
channel
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French (fr)
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黎子兰
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Guangdong Zhineng Technology Co Ltd
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Guangdong Zhineng Technology Co Ltd
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Priority to EP21758580.1A priority Critical patent/EP3958329A4/en
Priority to JP2022552997A priority patent/JP7522211B2/ja
Priority to KR1020227019319A priority patent/KR102898623B1/ko
Priority to US17/436,058 priority patent/US12349387B2/en
Publication of WO2021258771A1 publication Critical patent/WO2021258771A1/zh
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    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
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    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/473—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT
    • H10D30/4732—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT using Group III-V semiconductor material
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    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/478—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] the 2D charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
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    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
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    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
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    • H10P14/271—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition
    • H10P14/274—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials characterised by the preparation of substrate for selective deposition using seed materials
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    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
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    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 

Definitions

  • the present disclosure relates to the field of semiconductors, and more specifically, to a semiconductor device capable of adjusting electric field distribution and a manufacturing method thereof.
  • Group III nitride semiconductor is an important new semiconductor material, which mainly includes AlN, GaN, InN and compounds of these materials such as AlGaN, InGaN, AlInGaN, etc. Utilizing the advantages of the III-nitride semiconductors with direct band gap, wide band gap, high breakdown electric field strength, etc., through optimized design of device structure and process, III-nitride semiconductors have great prospects in the fields of power devices and radio frequency devices.
  • High electron mobility and high hole mobility transistors are an important device for the application of group III nitride semiconductors. It is hoped to achieve high performance, high electron mobility and high altitude, such as high withstand voltage, high power, low on-resistance and high reliability. Hole mobility transistor.
  • the present disclosure provides a semiconductor device structure and a manufacturing method thereof.
  • a method of manufacturing a semiconductor device including:
  • a barrier layer is formed on the exposed channel layer, and then a two-dimensional electron gas and immovable background positive charges are formed on the first surface of the channel layer, and/or a barrier layer is formed on the channel layer. Two-dimensional cavity gas and immovable background negative charge are formed on the second surface;
  • a source electrode, a gate electrode, and a drain electrode are formed on the first surface/second surface of the channel layer, and a bottom electrode is formed on the second surface/first surface of the channel layer.
  • step 401 is used instead of step 400.
  • the step 401 includes growing a first channel layer and a first channel layer along the groove with the single seed layer as the core under the restriction of the groove.
  • the adjustment layer and the second channel layer structure are used instead of step 400.
  • step 402 is used instead of step 400.
  • the step 402 includes growing a first channel layer and a second channel layer along the groove with the single seed layer as the core under the restriction of the groove.
  • the adjustment layer and the second channel layer structure are used instead of step 400.
  • step 403 is used instead of step 400.
  • the step 403 includes growing a first channel layer and a first channel layer along the groove with the single seed layer as the core under the restriction of the groove.
  • the adjustment layer, the second adjustment layer and the second channel layer structure are used instead of step 400.
  • the bottom electrode is connected to at least one of the first adjustment layer, the second adjustment layer, the two-dimensional electron gas, and the two-dimensional hole gas.
  • the bottom electrode is formed on the second surface of the channel layer, and the first/second adjustment layer has P-type doping; or the bottom electrode is formed on the first surface of the channel layer , The first/second adjustment layer has N-type doping.
  • the doping concentration in the first adjustment layer is less than 5E18/cm3; the doping concentration in the second adjustment layer is 1E17-5E19/cm3.
  • the source, the gate and the drain are coplanar or not coplanar.
  • the source electrode and the drain electrode are formed directly or indirectly on the channel layer, and the gate electrode is formed directly or indirectly on the barrier layer.
  • a buffer layer is deposited on the seed layer.
  • the seed layer is disposed at a position corresponding to the source electrode, a position corresponding to the drain electrode, or a position corresponding to the gate electrode and the drain electrode.
  • a current blocking layer is also formed on the seed layer.
  • the source region and the drain region are doped with N-type; when the HHMT device is formed, the source region and the drain region are doped with P-type .
  • a dielectric layer is formed on the side surface and the bottom surface of the groove.
  • a semiconductor device including:
  • the substrate has a side surface of a hexagonal symmetrical lattice structure
  • Two-dimensional electron gas and immovable background positive charge formed on the first surface of the channel layer, and/or two-dimensional hole gas and immovable background gas formed on the second surface of the channel layer The background negative charge;
  • the bottom electrode When the bottom electrode is formed on the second surface of the channel layer, it is formed as a HEMT device; when the bottom electrode is formed on the first surface of the channel layer, it is formed as an HHMT device.
  • the channel layer structure is replaced with a first channel layer, a first adjustment layer, and a second channel layer structure.
  • the channel layer structure is replaced with a first channel layer, a second adjustment layer, and a second channel layer structure.
  • the channel layer structure is replaced with a first channel layer, a first adjustment layer, a second adjustment layer, and a second channel layer structure.
  • the bottom electrode is connected to at least one of the first adjustment layer, the second adjustment layer, the two-dimensional electron gas, and the two-dimensional hole gas to adjust the electric field distribution of the device.
  • the bottom electrode is formed on the second surface of the channel layer, and the first/second adjustment layer has P-type doping; or the bottom electrode is formed on the second surface of the channel layer. On one side, the first/second adjustment layer has N-type doping.
  • the doping concentration in the first adjustment layer is less than 5E18/cm3; the doping concentration in the second adjustment layer is 1E17-5E19/cm3.
  • the source, the gate and the drain are coplanar or not coplanar.
  • the seed layer is disposed at a position corresponding to the source electrode, a position corresponding to the drain electrode, or a position corresponding to the gate electrode and the drain electrode.
  • the seed layer is arranged at a position corresponding to the drain, and a current blocking layer is formed on the seed layer.
  • the source and drain regions are also doped with N-type; when the HHMT device is formed, the source and drain regions are also doped with P-type .
  • a dielectric layer is further provided on the sidewall and bottom surface of the groove.
  • a complementary semiconductor device including any one of the aforementioned semiconductor devices.
  • a radio frequency device including any one of the aforementioned semiconductor devices.
  • an electric power device including any one of the aforementioned semiconductor devices.
  • FIGS. 1-15 are schematic diagrams of a semiconductor device structure and a manufacturing method thereof according to an embodiment
  • 20-23 are schematic diagrams of an optional semiconductor device structure and manufacturing method thereof.
  • FIGS 24-28 are schematic diagrams of alternative semiconductor device structures and manufacturing methods thereof.
  • 29-31 are schematic diagrams of alternative semiconductor device structures and manufacturing methods thereof.
  • FIG. 32 is a schematic diagram of an optional semiconductor device structure and manufacturing method thereof.
  • FIG. 33 is a schematic diagram of an optional semiconductor device structure and manufacturing method thereof.
  • FIG. 34 is a schematic diagram of an alternative method of manufacturing a semiconductor device structure.
  • the semiconductor device of the present disclosure is a compound semiconductor device containing a nitride semiconductor material, also referred to as a nitride semiconductor device, wherein the nitride semiconductor device is a group III nitride semiconductor device.
  • the III-nitride semiconductor device includes a transistor using Wurtzite III-nitride semiconductor material.
  • the transistor includes a GaN transistor made of GaN semiconductor material.
  • GaN transistors are normally closed transistors GaN-HEMT and/or GaN-HHMT.
  • the semiconductor device includes a substrate 100.
  • the material of the substrate 100 can be selected according to actual needs. Any substrate material with a hexagonal symmetrical lattice structure on the side surface of the vertical groove on the surface can be used.
  • the material of the substrate 100 may be Si, Al2O3, SiC, GaN, or the like.
  • the Si substrate Since the silicon substrate has the advantages of low price and strong workability, the Si substrate is taken as an example for further description in this disclosure.
  • the single crystal silicon substrate may be a silicon substrate with a (110) or (112) plane.
  • a substrate 100 is provided, and the substrate has a first surface 1001; a first dielectric layer 101 is formed on the first surface 1001 of the substrate 100.
  • the first dielectric layer 101 is formed by thermal oxidation. Or a SiO2 layer formed by vapor deposition.
  • the thickness of the first dielectric layer 101 is about 0.5 microns. It should be noted that the numerical range in the present invention is only an example and not a limitation of the present disclosure.
  • the first dielectric layer 101 has a first surface 1011 parallel to the first surface 1001 of the substrate. Part of the first dielectric layer 101 and the substrate 100 below it are etched to form a plurality of vertical grooves. Specifically, the grooves include first grooves 102 and second grooves 102' arranged at intervals. The structure and size of the groove and the second groove are the same. Exemplarily, the depth of the first groove and the second groove is about 5 microns.
  • the lower part of the first surface 1021 and the second surface 1022 of each groove are respectively constituted by the second surface 1002 and the third surface 1003 exposed by the substrate, wherein the second surface 1002 and the third surface 1003 of the substrate have hexagonal symmetry. Lattice structure, such as Si(111) plane.
  • the second surface and the third surface of the substrate may also be a Al2O3 (0001) face, SiC (0001) face, SiC (0001) plane, GaN (0001) plane, or a GaN (0001 -) plane and the like .
  • the upper part of the first surface 1021 and the second surface 1022 of each groove are respectively constituted by the second surface 1012 and the third surface 1013 of the first dielectric layer 101.
  • a second dielectric layer 103 is formed on the third surface 1023 of each groove.
  • the second dielectric layer 103 may be a silicon dioxide layer formed by oxidation.
  • the thickness It is about 500nm. As shown in FIG.
  • a fourth dielectric layer 105 is formed on the first surface 1021 and the second surface 1022 of each groove.
  • the thickness of the fourth dielectric layer is about 100 nm. Delay, the interaction between the silicon substrate and the Ga-containing precursor is more conducive to improving the selectivity of the external delay. Further, as shown in Figures 8 and 9, remove part of the fourth dielectric layer 105 on the second surface of the first groove and on the first surface of the second groove, and the substrate exposed in the first groove A single seed seed layer 106 is formed on the third surface 1003 of 100 and the second surface 1002 of the substrate 100 exposed in the second groove.
  • the single seed layer is an ALN layer
  • the growth direction of the ALN crystal is the ⁇ 0001> direction
  • the surface thereof is the (0001) plane.
  • the position where the single seed layer is located corresponds to the formation position of the source electrode of the subsequent device. Since the subsequently formed device structure takes the source as the reference point, the semiconductor device structure can show a symmetrical structure, and the voltage of the source region is very low, so it is not sensitive to the crystal quality, so that the crystal quality in the nucleation region is poor. The impact is minimized.
  • a channel layer 201 is selectively grown with the seed layer 106 as the core.
  • the channel layer 201 may be nitride, for example, intrinsic GaN (i-GaN) or unintentionally doped GaN layer. Due to the existence of the groove 102, the channel layer 201 starts to grow from the seed layer along the groove 102, where the growth includes the growth along the first direction of the groove, and also includes the growth in the second direction perpendicular to the groove. During growth, the channel layer 201 may also be grown outside the groove, and the channel layer 201 outside the groove may be removed by planarization or etching techniques.
  • i-GaN intrinsic GaN
  • both sides of the channel layer are etched to remove the first dielectric layer 101 and part of the substrate 100 so that the channel layer 201 protrudes from the fourth surface 1004 of the substrate 100 after the etching.
  • the first side 2013 of the channel layer 201 having the spontaneous polarization effect and the piezoelectric polarization effect and the opposite second surface 2014 having the spontaneous polarization effect and the piezoelectric polarization effect, when the channel layer is GaN,
  • the first surface 2013 (0001) plane, the second plane is 2014 (0001 -) plane.
  • a third dielectric layer 107 is formed on the etched substrate 100 to isolate the exposed silicon substrate.
  • the third dielectric layer may be a silicon dioxide layer.
  • the barrier layer 202 is formed to cover the channel layer 201.
  • the barrier layer can be an AlN layer or an AlGaN layer, and then two-dimensional electron gas 2DEGs are formed on the first surface 2013 and the second surface 2014 of the channel layer. And the two-dimensional hole gas 2DHG, and correspondingly, there are immovable background positive and background negative charges at the interface.
  • the positive background charge attracts the two-dimensional electron gas 2DEG, and the negative background charge attracts the two-dimensional electron gas.
  • the hole gas 2DHG also forms a complementary vertical channel device structure.
  • the source electrode 401, the gate electrode 402, the drain electrode 403, and the bottom electrode 404 are respectively formed on the barrier layer 202 in the direction along the channel length.
  • the source and drain can also be formed on the channel 201 along the direction of the two-dimensional electron gas transport, and the bottom electrode is in electrical contact with the two-dimensional hole gas;
  • the source and drain can also be formed on the channel 201 along the two-dimensional hole gas transport direction, and the bottom electrode is in electrical contact with the two-dimensional electron gas.
  • the bottom electrode can be an independently controlled electrode, and can also be electrically connected to the source electrode or the gate electrode.
  • the bottom electrode can be located between the gate and the drain, between the source and the gate, or under the gate.
  • the channel layer can be grown very flat during lateral epitaxial growth, and the vertical surface of the subsequent semiconductor device including the channel layer can be formed very flat with the help of the groove, so it is easy to achieve A higher aspect ratio. More specifically, when the channel layer 201 is used as a vertical channel, a higher channel density can be achieved per unit area, thereby reducing the resistance of the device and improving the performance of the device.
  • HEMT High Electron Mobility Transistor
  • the current flows from the drain 403 to the source 401 (electrons from the source 401 to the The drain 403 flows in the direction).
  • the setting of the bottom electrode 404 basically has no effect on the flow of current; when the device is turned off, the drain 403 is at a high voltage, and the channel is turned off at this time.
  • the electron gas is depleted due to the existence of the high voltage of the drain 403, and only the background positive charge remains.
  • the 2DHG connected to the bottom electrode is also partially depleted under the action of the electric field, leaving the negative charge of the background, and the negative charge of the background can generate an electric field to cancel out the 2DEG.
  • these negative background charges and the above-mentioned remaining positive charges make the distribution of the electric field more uniform, and achieve the purpose of reducing the strength of the local electric field.
  • HHMT High Hole Mobility Transistor
  • the drain When the device is turned off, the drain is at a high negative pressure. At this time, because the channel is closed, the 2DHG from the gate to the drain is exhausted, leaving only the negative charge in the background. At this time, since the bottom electrode voltage is much higher than the drain electrode voltage, the 2DEG connected to the bottom electrode is also partially depleted under the action of the electric field, leaving the background positive charge. These background positive charges can partially offset the background negative electric field of the 2DHG channel layer, making the electric field more uniform.
  • FIGS. 1-14 in which FIGS. 1, 2, 6, and 10 are cross-sectional views, and FIGS. 3-5, 7-9, and 11-14 are top views.
  • a substrate 100 is provided.
  • the substrate can be a silicon substrate with a (110) or (112) surface.
  • a first dielectric layer 101 is formed on the first surface 1001 of the substrate 100.
  • the first dielectric layer 101 is a SiO2 layer formed by thermal oxidation or vapor deposition.
  • the thickness of the first dielectric layer 101 is about 0.5 microns.
  • Step 2 As shown in FIG. 2, lithography is performed on the first dielectric layer 101 at intervals to expose part of the interior of the first dielectric layer 101, and then the first dielectric layer 101 and the substrate below it are etched at the lithography position 100.
  • Vertical grooves are formed.
  • the grooves include first grooves 102 and second grooves 102' arranged at intervals.
  • the two side surfaces of each groove, that is, the lower part of the first surface 1021 and the second surface 1022 are respectively constituted by the second surface 1002 and the third surface 1003 exposed by the etched substrate.
  • the second surface 1002 and the third surface 1003 of the substrate have a hexagonal symmetrical lattice structure, such as a Si(111) plane.
  • the second surface and the third surface of the substrate may also be a Al2O3 (0001) face, SiC (0001) face, SiC (0001 -)) plane, GaN (0001) plane or a GaN (0001 -) plane and the like.
  • Step 3 As shown in FIG. 3, on the basis of the structure formed in Step 2, a sacrificial layer 104 is formed by coplanar deposition.
  • the sacrificial layer 104 is a silicon nitride layer with a thickness of about 100 nanometers. It is understandable that the choice of the first dielectric layer and the sacrificial layer only needs to have a high etching selection ratio between the two. For example, when the sacrificial layer is etched, the etchant basically does not etch the first dielectric layer. Or its etching is extremely slow.
  • Step 4 As shown in FIG. 4, dry etching is performed to remove the sacrificial layer 104 on the first surface 1011 of the first dielectric layer 101 and the sacrificial layer 104 on the third surface 1023 of the groove 102102', leaving each concave The sacrificial layer 104 on the first surface 1021 and the second surface 1022 of the groove 102 (102').
  • Step 5 As shown in FIG. 5, through an oxidation process, a second dielectric layer 103 (silicon dioxide layer) is formed on the third surface 1023 of each groove. The first surface and the second surface of the groove are sacrificed due to remaining The protection of the layer 104 is not oxidized, and the second dielectric layer can avoid the incompatibility between gallium atoms and the silicon substrate during the subsequent growth of the nitride semiconductor, and avoid the phenomenon of melt-back. At the same time, the second dielectric layer can also effectively block the leakage current between the nitride semiconductor and the silicon substrate, and reduce the parasitic capacitance caused by the silicon substrate.
  • a second dielectric layer 103 silicon dioxide layer
  • Step 6 As shown in FIG. 6, using the etching selection ratio of the sacrificial layer 104 and the second dielectric layer 103 (silicon dioxide layer), the first surface and the second surface of each groove are removed by selective wet etching The sacrificial layer 104.
  • Step 7 As shown in FIG. 7, through an oxidation process, a thinner fourth dielectric layer 105 (silicon dioxide layer) is formed on the first surface and the second surface of each groove 102, so that the fourth dielectric layer
  • the thickness is set differently from the thickness of the first and second dielectric layers, so that when the fourth dielectric layer is subsequently removed, there are still enough thick first and second dielectric layers to protect the substrate.
  • Step 8 As shown in Figure 8, photoresist is applied, and a photolithography pattern is formed between the first groove and the second groove to expose the first dielectric layer between the first groove and the second groove 101. It can be understood that the photolithography pattern can expose all the first dielectric layer 101 between the first groove and the second groove.
  • Step 9 As shown in FIG. 9, remove the exposed fourth dielectric layer 105 on the second surface of the first groove and on the first surface of the second groove, because the thickness of the first dielectric layer is much larger than that of the fourth dielectric layer. The thickness of the dielectric layer. Therefore, in the process of removing part of the fourth dielectric layer, the exposed part of the first dielectric layer is only etched to a small thickness and will not be completely removed. Then the photoresist is removed, so that the first A part of the third surface 1003 of the substrate 100 is exposed in the groove and a part of the second surface 1002 of the substrate 100 is exposed in the second groove.
  • Step 10 As shown in FIG. 9, due to the melt-back effect between the silicon substrate and the gallium, GaN cannot be directly deposited on the silicon substrate. Usually, a seed layer of AlN needs to be deposited first, and then a subsequent nitride semiconductor structure is formed on this basis. Therefore, a single crystal AlN seed layer is respectively formed on the third surface 1003 of the substrate 100 in the exposed first groove and on the second surface 1002 of the substrate 100 in the exposed second groove. 106.
  • the growth direction of single crystal AlN crystal is ⁇ 0001>, and the surface is (0001) plane.
  • the selectivity of AlN is very low, and it is easy to generate polycrystalline or amorphous AlN on the dielectric layer under normal process conditions, which is unfavorable for forming the required structure. Therefore, it is necessary to separately remove AlN on the silicon dioxide layer after the seed layer is formed. Or introduce chlorine-containing gas when growing the AlN seed layer to ensure that it only grows on the silicon substrate and not on the silicon dioxide layer.
  • the seed layer can also be GaN. At this time, it is easier to achieve nucleation only on the exposed substrate surface through process adjustment.
  • Step 11 As shown in FIG. 10, the channel layer 201 is then epitaxially grown with the seed layer 106 as the core side. Due to the existence of the groove 102, the channel layer 201 starts from the seed layer and runs along the starting side of the groove 102 Epitaxial growth, where growth includes growth along the first direction of the groove, and also includes growth in the second direction perpendicular to the groove.
  • the channel layer 201 can also be grown outside the groove, and be planarized or etched. The channel layer 201 outside the groove is removed.
  • the side epitaxy can effectively improve the quality of the nitride semiconductor crystal in the side epitaxial region, thereby improving the electrical performance of the device.
  • Removal of the channel layer outside the groove can make the device in a constrained state during the formation process, which is conducive to the formation of a specific structure and size, helps to form a device with a higher aspect ratio, and provides a growth process In addition to parameter adjustment, it is a means to achieve a higher aspect ratio device. Since the growth of the channel layer in the groove is restricted by the first surface and the second surface of the groove, the growth process of the channel layer avoids being unable to maintain The situation where the growth surface is completely vertical or the growth surface is not on the same plane, as well as the situation where there may be multiple and complicated growth surfaces, facilitates the control of the device and the improvement of the electrical performance. It can be understood that the growth of the channel layer 201 outside the groove may not be removed, and a portion protruding from the groove may be formed.
  • Step 12 As shown in FIG. 11, a photolithography pattern is formed to expose the entire area between the adjacent first groove and the second groove from above, and the first dielectric layer 101 and part of the substrate 100 in the etched area The material is such that the channel layer covering the fourth dielectric layer in the groove 102 protrudes from the fourth surface 1004 of the etched substrate.
  • Step 13 As shown in FIG. 12, a third dielectric layer 107 is formed on the fourth surface 1004 of the etched substrate 100.
  • the third dielectric layer may be a silicon dioxide layer formed by oxidation, and then removed Covering the fourth dielectric layer on the channel layer 201, thereby exposing the first surface 2013 of the channel layer 201 which has the spontaneous polarization effect and the piezoelectric effect, and the opposite spontaneous polarization effect and the piezoelectric effect.
  • Step 14 As shown in FIG. 13, a barrier layer 202 is formed overlying the channel layer 201.
  • the barrier layer may be an AlN layer or an AlGaN layer, and then on the first surface 2013 and the second surface 2014 of the channel layer respectively Two-dimensional electron gas 2DEG and two-dimensional hole gas 2DHG are formed.
  • a buffer layer may also be deposited first.
  • Step 15 As shown in Figure 14, an insulating layer is deposited, the insulating layer is etched by photolithography, and then metal is deposited on it.
  • the first of the channel layer 201 is along the two-dimensional electron gas transmission direction.
  • a source 401 and a drain 403 are respectively formed on the surface, and a gate 402 is formed on the barrier layer 202 along the two-dimensional electron gas transmission direction, wherein the gate is located between the source and the drain.
  • the source electrode, the gate electrode, and the drain electrode are all formed on the barrier layer 202 along the two-dimensional electron gas transmission direction.
  • a bottom electrode 404 is formed at the second surface where the two-dimensional hole gas is located.
  • a source and a drain are respectively formed on the second surface along the two-dimensional hole gas transport direction, and a gate is formed on the barrier layer 202 along the two-dimensional hole gas transport direction. Where the gate is located between the source and the drain.
  • the source, gate, and drain are all formed on the barrier layer 202 along the two-dimensional hole gas transport direction.
  • a bottom electrode 404 is formed on the first surface where the two-dimensional electron gas is located.
  • FIGS. 16-19 are all top views.
  • a first sublayer 2011 of a channel layer, a first adjustment layer 2013, and a second sublayer 2012 of the channel layer are formed in the groove along the direction of the first surface and the second surface of the channel.
  • the first sub-layer 2011 of the channel layer, the first adjustment layer 2013 and the second sub-layer 2012 of the channel layer completely fill the groove and make each layer parallel to the first surface of the channel layer and coplanar.
  • the first adjustment layer may have P-type doping or N-type doping.
  • P-type doping is P-type GaN
  • N-type doping is N-type.
  • the doping concentration is less than 5E18/cm3.
  • P-type doping is selected.
  • HHMT The device is selected for N-type doping. It is understandable that the doping can be graded.
  • the projection of the first adjustment layer on the first surface of the channel layer falls within a range between the gate and the drain, or a range that partially overlaps the projection of the gate in this direction.
  • the doped first adjustment layer is arranged perpendicular or obliquely to the side surface of the channel layer.
  • the adjustment layer here is preferably grown laterally and epitaxially. Compared with the method of ion implantation, it will not cause problems such as ion implantation damage and has good electrical performance.
  • the bottom electrode When the device is in the off state, since the bottom electrode is electrically connected to the first adjustment layer, the situation that the electric potential of the doped layer (electric field adjustment doped layer) between the gate and drain for adjusting the electric field is not stable is avoided. It is understandable that the bottom electrode may not be provided and only the floating electric field adjustment doped layer may be used to reduce the local electric field strength.
  • the bottom electrode is in electrical contact with the two-dimensional charge carrier gas and the first adjustment layer at the same time, so that one type of background charge in the complementary channel is offset by the doping of the first adjustment layer and the other Part of the electric field in various types of two-dimensional charge carriers achieves the purpose of reducing the strength of the local electric field.
  • the manufacturing method for manufacturing the semiconductor device is specifically described below.
  • Step 11' As shown in FIGS. 16-19, after the seed layer 106 is formed, the first sub-layer 2011 of the channel layer is selectively grown with the seed layer 106 as the core. Due to the existence of the groove 102, the first sub-layer 2011 The layer 2011 starts from the seed layer and grows outward along the starting side of the groove 102, wherein the growth includes growth along the first surface or the second surface of the groove in the first direction, and the third surface perpendicular to the groove. Grow. Then, with the first sub-layer 2011 as the core, a doped first adjustment layer 2013 is grown.
  • the growth of the first adjustment layer 2013 also includes growth along the first surface or the second surface of the groove in the first direction, and also includes Growth in the second direction perpendicular to the first or second surface of the groove, and growth perpendicular to the third surface of the groove.
  • the projection of the first adjustment layer 2013 on the first surface of the channel layer falls within the range between the gate and the drain, or partially overlaps the projection of the gate in this direction.
  • the second sublayer 2012 of the channel layer is continued to grow.
  • the second sublayer of the channel layer may also be an intrinsic GaN layer or an unintentionally doped GaN layer.
  • the growth direction of the second sublayer 2012 of the channel layer is the same as the growth direction of the first sublayer or the first adjustment layer.
  • the coplanar structure can make the device in a constrained state during the formation process, is conducive to the formation of a specific structure and size, helps to form a device with a higher aspect ratio, and provides a high level of realization in addition to the adjustment of growth process parameters. Because the growth of the channel layer and the first adjustment layer in the groove is restricted by the first surface and the second surface of the groove, the growth process of the channel layer and the first adjustment layer avoids It keeps the situation that it is completely vertical or the growth surface is not on the same plane, and avoids the possibility of multiple and complicated growth surfaces, which facilitates the control of the device and the improvement of electrical performance.
  • FIGS. 20-23 An optional semiconductor device and its manufacturing method will be described with reference to FIGS. 20-23, and FIGS. 20-23 shown are top views.
  • a first sublayer 2011 of a channel layer, a second adjustment layer 2014, and a second sublayer 2012 of the channel layer are formed in the groove along the direction of the first surface and the second surface of the channel.
  • the first sub-layer, the second adjustment layer 2014 and the second sub-layer 2012 completely fill the grooves and make each layer parallel to the first surface of the channel and coplanar.
  • the second adjustment layer is used to control the threshold voltage.
  • the second adjustment layer has P-type doping or N-type doping.
  • the P-type doping is P-type GaN
  • the N-type doping is N-type GaN.
  • the doping concentration of the second adjustment layer 2014 is 1E17-5E19/cm3, more preferably 1E+18/cm3-5E+19/cm3.
  • the P-type GaN layer can deplete the two-dimensional electron gas on the first side of the channel layer; the N-type GaN layer can deplete the two-dimensional hole gas on the second side of the channel layer, thereby making the device a normally closed state .
  • the specific choice of whether to perform P-type doping or N-type doping depends on the specific type of subsequent devices. For HEMT devices, P-type doping is selected, and for HHMT devices, N-type doping is selected. It is understandable that the doping can be gradual.
  • the projection of the second adjustment layer on the first surface of the channel layer falls within the range of the gate.
  • the doping concentration and size parameters of the second adjustment layer can be set according to the device parameters, as long as it can deplete 95%-100% of the two-dimensional electron gas or two-dimensional hole gas above it, and the two-dimensional charge carrier gas The higher the concentration, the corresponding doping concentration can be increased accordingly.
  • the bottom electrode can be connected to the second adjustment layer and the two-dimensional carrier gas, or only connected to the two-dimensional carrier gas.
  • the bottom electrode is connected to the two-dimensional hole gas.
  • the bottom electrode is connected to the two-dimensional electron gas. The connection mode of the bottom electrode enables the second adjustment layer and the two-dimensional carrier to cooperate or the two-dimensional carrier to act independently, which avoids the situation that the electric field adjusts the doped layer with unstable electric potential.
  • Step 11' As shown in FIGS. 20-23, after the seed layer 106 is formed, the first sub-layer 2011 of the channel layer is selectively grown with the seed layer 106 as the core. Due to the existence of the groove 102, the first sub-layer 2011 is The layer 2011 starts from the seed layer and grows outward along the starting side of the groove 102, wherein the growth includes growth along the first surface or the second surface of the groove in the first direction, and the third surface perpendicular to the groove. Grow. Then take the first sub-layer 2011 as the core to grow a doped second adjustment layer 2014.
  • the growth of the second adjustment layer 2014 also includes growth along the first surface or the second surface of the groove in the first direction, and also includes Growth in the second direction perpendicular to the first or second surface of the groove, and growth perpendicular to the third surface of the groove.
  • the second adjustment layer 2014 is located within the projection range of the gate in the projection direction of the subsequent device.
  • the second sublayer 2012 of the channel layer is continued to grow.
  • the second sublayer of the channel layer may also be an intrinsic GaN layer or an unintentionally doped GaN layer.
  • the growth direction of the second sublayer 2012 of the channel layer is the same as the growth direction of the first sublayer or the second adjustment layer.
  • the coplanar structure can make the device in a constrained state during the formation process, is conducive to the formation of a specific structure and size, helps to form a device with a higher aspect ratio, and provides a high level of realization in addition to the adjustment of growth process parameters. Because the growth of the channel layer and the second adjustment layer in the groove is restricted by the first surface and the second surface of the groove, the growth process of the channel layer and the second adjustment layer avoids It keeps the situation that it is completely vertical or the growth surface is not on the same plane, and avoids the possibility of multiple and complicated growth surfaces, which facilitates the control of the device and the improvement of electrical performance.
  • FIGS. 24-28 are shown as top views.
  • the first sub-layer 2011 of the channel layer, the second adjustment layer 2014, the first adjustment layer 2013 and the channel layer are formed in the groove along the direction of the first surface and the second surface of the channel.
  • the second sublayer 2012 layer, the first sublayer of the channel layer, the second adjustment layer 2014, the first adjustment layer 2013, and the second sublayer of the channel layer completely fill the grooves and make each layer parallel to the channel
  • the first surface is coplanar.
  • the second adjustment layer is used to control the threshold voltage
  • the first adjustment layer is used to adjust the electric field distribution, especially the electric field distribution at the edge of the gate electrode. Understandably, the first adjustment layer and the second adjustment layer have P-type doping or N-type doping.
  • the P-type doping is P-type GaN
  • the N-type doping is N-type doping.
  • the doping concentration of the second adjustment layer 2014 is 1E17-5E19/cm3, more preferably 1E+18/cm3-5E+19/cm3.
  • the P-type GaN layer can deplete the two-dimensional electron gas on the first side of the channel layer; the N-type GaN layer can deplete the two-dimensional hole gas on the second side of the channel layer, thereby making the device a normally closed state .
  • the specific choice of whether to perform P-type doping or N-type doping depends on the specific type of subsequent devices.
  • the doping can be gradual.
  • the projection of the second adjustment layer on the first surface of the channel layer falls within the range of the gate; the projection of the first adjustment layer on the first surface of the channel layer falls within the range between the gate and the drain, or There is a partial overlap range with the projection of the grid in this direction.
  • the doping concentration and size parameters of the second adjustment layer can be set according to the device parameters, as long as it can deplete 95%-100% of the two-dimensional electron gas or two-dimensional hole gas above it, and the two-dimensional charge carrier The higher the gas concentration, the corresponding doping concentration can be increased accordingly.
  • the doping concentration of the first adjustment layer is less than 5E18/cm3.
  • the doped first adjustment layer and the second adjustment layer are arranged perpendicularly or obliquely to the side surface of the channel layer.
  • the external electric field reacts and changes the electric field distribution when the device is turned off. Effectively reduce the local electric field intensity, especially the peak electric field at the gate end close to the drain.
  • the adjustment layer here is preferably grown laterally and epitaxially. Compared with the method of ion implantation, there will be no problems such as ion implantation damage, and it has good electrical performance.
  • the bottom electrode can be electrically connected to the first adjustment layer, the second adjustment layer and the two-dimensional carrier gas.
  • the bottom electrode can be connected to the first adjustment layer and/or the second adjustment layer. It is also possible to connect the first regulating layer and the two-dimensional carrier gas, or to connect the first regulating layer, the second regulating layer and the two-dimensional carrier gas at the same time, through the first regulating layer, the second regulating layer and the two-dimensional carrier gas.
  • the individual or synergistic effects of the various forms of carriers can avoid the unstable potential of the electric field adjustment doped layer.
  • the manufacturing method for manufacturing the semiconductor device is specifically described below.
  • Step 11' As shown in FIGS. 24-28, after the seed layer 106 is formed, the first sub-layer 2011 of the channel layer is selectively grown with the seed layer 106 as the core. Due to the existence of the groove 102, the first sub-layer 2011 is The layer 2011 starts from the seed layer and grows outward along the starting side of the groove 102, wherein the growth includes growth along the first surface or the second surface of the groove in the first direction, and the third surface perpendicular to the groove. Grow. Then take the first sub-layer 2011 as the core to grow a doped second adjustment layer 2014.
  • the growth of the second adjustment layer 2014 also includes growth along the first surface or the second surface of the groove in the first direction, and also includes Growth in the second direction perpendicular to the first or second surface of the groove, and growth perpendicular to the third surface of the groove.
  • the second adjustment layer 2014 is located within the projection range of the gate in the projection direction of the subsequent device. Then take the second adjustment layer 2014 as the core to grow the doped first adjustment layer 2013.
  • the growth of the first adjustment layer 2013 also includes growth along the first surface or the second surface of the groove in the first direction, and also includes Growth in the second direction perpendicular to the first or second surface of the groove, and growth perpendicular to the third surface of the groove.
  • the first adjustment layer 2013 is located in the range from the gate to the drain in the projection direction of the subsequent device, or partially overlaps the projection of the gate. Then, with the first adjustment layer 2013 as the core, the second sub-layer 2012 of the channel layer is continued to grow.
  • the second sub-layer may also be an intrinsic GaN layer or an unintentionally doped GaN layer.
  • the growth direction of the second sublayer 2012 is the same as the growth direction of the first sublayer or the two adjustment layers.
  • the coplanar structure can make the device in a constrained state during the formation process, is conducive to the formation of a specific structure and size, helps to form a device with a higher aspect ratio, and provides a high level of realization in addition to the adjustment of growth process parameters.
  • the growth process of the channel layer and the two adjustment layers in the groove is restricted by the first surface and the second surface of the groove, the growth process of the channel layer and the two adjustment layers avoids It keeps the situation that it is completely vertical or the growth surface is not on the same plane, and avoids the possibility of multiple and complicated growth surfaces, which facilitates the control of the device and the improvement of electrical performance.
  • one side of the channel layer is etched to remove the first dielectric layer 101 and part of the substrate 100, so that the substrate has a first surface and a surface lower than and parallel to The fifth surface of the first surface.
  • the first surface 2013 of the channel layer 201 having the spontaneous polarization effect and the piezoelectric polarization effect is exposed.
  • the channel layer is GaN
  • the first surface 2013 is the (0001) surface.
  • opposite to the first surface 2013 has a spontaneous polarization effect and piezo polarization effects of the second surface of the substrate 2014 and still cover the first dielectric layer, the second surface 2014 of the GaN (0001 -) plane.
  • the channel layer When forming HHMT device, expose the channel layer has a spontaneous polarization effect and piezo polarization effects of the second surface 201 2014, when the channel layer is GaN, the second surface 2014 (0001 -) plane. At this time, the first surface 2013 with spontaneous polarization effect and piezoelectric polarization effect opposite to the second surface 2014 is still covered by the substrate and the first dielectric layer, and the first surface 2013 is the (0001) surface of GaN.
  • a third dielectric layer 107 is formed on the etched substrate 100 to isolate the exposed silicon substrate.
  • the third dielectric layer may be a silicon dioxide layer.
  • a barrier layer 202 is formed on the first surface 2013 or the second surface 2014 of the channel layer 201, the barrier layer is an AlN layer or an AlGaN layer, thereby forming a two-dimensional electron gas on the first surface 2013 of the channel layer 2DEG or two-dimensional hole gas 2DHG is formed on the second surface 2014 of the channel layer.
  • the bottom electrode 404 is connected to the first adjustment layer 2013 or the bottom electrode is connected to the first adjustment layer 2013 and the second adjustment layer 2014, thereby reacting to the external electric field when the device is turned off and changing the electric field distribution, so that the local electric field strength can be effectively reduced.
  • the peak value of the electric field at the gate terminal close to the drain is reduced.
  • the manufacturing method for manufacturing the HEMT semiconductor device will now be exemplarily described with reference to 29-31 in conjunction with the foregoing manufacturing method.
  • step 12' as shown in FIG. 29, a photolithography pattern is formed to expose the area on the first surface 2013 side of the channel layer, and the first dielectric layer 101 and part of the substrate 100 in the area are etched to expose the area of the channel layer 201
  • the fourth dielectric layer on the first side of the spontaneous polarization effect and the piezoelectric polarization effect.
  • the second surface 2014 opposite to the first surface 2013 and having the spontaneous polarization effect and the piezoelectric polarization effect is still surrounded by the fourth dielectric layer, the base material and the first dielectric layer.
  • a third dielectric layer 107' is formed on the etched substrate 100.
  • the third dielectric layer may be a silicon dioxide layer formed by oxidation.
  • the fourth dielectric layer covering the first surface 2013 of the channel layer 201 is removed.
  • a second semiconductor layer 202 is formed by chemical deposition on the first surface 2013 of the channel layer 201.
  • the second semiconductor layer can be an AlN layer or an AlGaN layer, so that it can be formed on the first surface 2013 of the channel layer.
  • Two-dimensional electron gas 2DEG is formed on one side 2013.
  • the method of forming the photolithography pattern can also be changed to expose the entire area between the adjacent first groove and the second groove from above, and the first dielectric layer in this area is etched. 101 and part of the substrate 100, so that the channel layer covering the fourth dielectric layer in the groove 102 protrudes from the fourth surface of the etched substrate, and then only the first surface/second surface of the channel layer The area on the surface side is further etched, and the specific method can refer to the foregoing embodiment, which will not be repeated here.
  • the position of the single-crystal seed layer corresponds to the formation position of the third electrode (drain) of the subsequent device.
  • a current blocking layer may be added to the single seed layer.
  • the current blocking layer may be heavily doped C or Fe element, and the doping concentration of C or Fe may be 1E17-1E20/cm3.
  • the position of the single seed seed layer may also be set in the area between the source electrode and the drain electrode.
  • the above technical problem can be overcome by separating the position of the seed layer from the position of the subsequent drain electrode area by a certain distance.
  • the regions of the corresponding first and second grooves may be exposed by photolithography.
  • the current blocking layer can be formed by performing corresponding doping during epitaxial growth with a single seed seed layer as the core.
  • doping is performed in the source region and the drain region to reduce contact resistance. It is understandable that when forming HEMT devices, the doping type of the source and drain regions is N-type; when forming HHMT devices, the doping type of the source and drain regions is P-type .
  • the barrier layer can be removed to make the source and/or drain physically contact the channel layer, and form an ohmic contact with the two-dimensional electron carrier gas (2DEG).
  • 2DEG two-dimensional electron carrier gas
  • the source (and/or drain) is in physical contact with the channel layer, and the two-dimensional hole carrier
  • the carrier gas (2DHG) forms an ohmic contact
  • this method of direct physical contact with the channel layer is more conducive to reducing the ohmic Contact resistance.
  • the manufacturing method for manufacturing the semiconductor device is exemplarily described in conjunction with the foregoing manufacturing method.
  • the case where the seed layer corresponds to the source region is taken as an example to illustrate the doping of the source region and the drain region.
  • the situation where the seed layer corresponds to the drain region, or the situation where the seed layer is located between the gate and the drain region is similar to the situation where the seed layer corresponds to the source region, and will not be repeated here.
  • FIG. 25 after the seed layer is formed, in the process of growing the channel layer 201 with the seed layer as the core, corresponding P-type or N-type doping is performed in the source region.
  • the intrinsic (undoped) channel layer or the unintentionally doped channel layer is grown before the corresponding doping.
  • the channel layer, and then the growth of the doped source region is grown before the corresponding doping.
  • the intrinsic channel layer or the unintentionally doped channel layer is epitaxially grown to form the channel region. It can be understood that corresponding doping can be selected in the channel region to form the first adjustment layer and/or the second adjustment layer.
  • corresponding P-type or N-type doping may be performed in the drain region.
  • the doping of the drain region and the source region and the doping of the adjustment layer can be performed simultaneously, or the doping of the drain region, the doping of the source region, and the doping of the adjustment layer are performed sequentially. conduct.
  • the device can be formed as a complementary semiconductor device in which HHMT and HEMT coexist.
  • a power supply device includes any one of the above-mentioned semiconductor devices.
  • the power supply device includes a primary circuit, a secondary circuit, a transformer, etc., wherein both the primary circuit and the secondary circuit have switching elements, and the switching element adopts any of the above-mentioned semiconductor devices.
  • a mobile phone includes any one of the above-mentioned semiconductor devices.
  • the mobile phone includes a display screen, a charging unit, etc., wherein the charging unit includes any of the aforementioned semiconductor devices.
  • An amplifier which can be used in power amplifiers in the fields of mobile phone base stations, optical communication systems, and the like.
  • the power amplifier can include any of the above-mentioned semiconductor devices.
  • the semiconductor device can reduce gate leakage current, has a high threshold voltage, high power, and high reliability, and can achieve low on-resistance and constant device performance.
  • the off state can provide a stable threshold voltage, so that the semiconductor device has good switching characteristics.
  • the solution of the present disclosure can also help to achieve one of the following effects: it can effectively reduce the local electric field intensity and improve the overall performance and reliability of the device; the structure and preparation process of the semiconductor device are relatively simple, which can effectively reduce the production cost .
  • the semiconductor device and the manufacturing method thereof provided by the present disclosure have simple process, low cost, energy saving, high aspect ratio, higher channel density per unit area, and high withstand voltage, high power and low power. High performance such as on-resistance.

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Abstract

本公开内容提供一种半导体器件及其制造方法，所述半导体器件包括以一基材，在所述基材上形成的凹槽，受所述凹槽结构限制生长的所述沟道层结构，所述沟道层结构露出所述基材的上表面；覆盖在露出的沟道层结构上的势垒层，在所述沟道层结构的第二面和第一面上分别形成的二维电子气和二维空穴气，以及在所述沟道层结构第一面/第二面上形成的源极、栅极和漏极；在所述沟道层结构第二面/第一面上形成的底电极。所述半导体器件能够减小栅极漏电流，具有高阈值电压、高功率、高可靠性，能够实现低导通电阻和器件的常关状态，能够提供稳定的阈值电压，从而使得半导体器件具有良好的开关特性。以及可以有效地降低局部电场强度，提高器件的整体性能与可靠性；所述半导体器件的结构和制备工艺较为简单，能有效降低生产成本。

Description

一种半导体器件及其制造方法
相关申请的交叉引用
本公开要求于2020年6月23日提交中国专利局的申请号为202010593852.1、名称为“一种半导体器件及其制造方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开内容涉及半导体领域，更具体而言，涉及一种能调节电场分布的半导体器件及其制造方法。
背景技术
III族氮化物半导体是一种重要的新型半导体材料，主要包括AlN、GaN、InN及这些材料的化合物如AlGaN、InGaN、AlInGaN等。利用所述III族氮化物半导体具有直接带隙、宽禁带、高击穿电场强度等优点，通过器件结构与工艺的优化设计，III族氮化物半导体在功率器件和射频器件领域拥有巨大前景。高电子迁移率和高空穴迁移率晶体管是应用III族氮化物半导体的一个重要器件，希望实现高耐受电压、高功率、低导通电阻和高可靠性等高性能的高电子迁移率和高空穴迁移率晶体管。
为了利用III族氮化物半导体材料的高临界击穿电场特性来提高器件的耐压，进行了许多的研究，例如在纵向上增加沟道层的厚度或质量，在横向上进行漂移区长度增加，但上述改进会使器件的面积增加、成本高昂甚至于器件的导通电阻增大、功耗增加以及开关速度随之降低，或者所采用的方案的耐压效果有限。
发明内容
鉴于此，本公开提供一种半导体器件结构及其制造方法。
在下文中将给出关于本公开内容的简要概述，以便提供关于本公开内容某些方面的基本理解。应当理解，此概述并不是关于本公开内容的穷举性概述。它并不是意图确定本公开内容的关键或重要部分，也不是意图限定本公开内容的范围。其目的仅仅是以简化的形式给出某些概念，以此作为稍后论述的更详细描述的前序。
根据本公开内容的一方面，提供一种半导体器件的制造方法，包括：
提供一基材；在所述基材上形成凹槽，所述凹槽的侧表面具有六角对称性的晶格结构；
在所述凹槽中的所述侧表面上形成一单晶种籽层；
在所述凹槽的限制下以所述单晶种籽层为核心沿着所述凹槽生长一沟道层；
刻蚀所述基材，使所述沟道层凸出刻蚀后的基材的上表面；
在所述露出的沟道层上形成势垒层，接着，在所述沟道层的第一面形成二维电子气和不可移动的本底正电荷，和/或在所述沟道层的第二面上形成二维空穴气和不可移动的本底负电荷；
在所述沟道层的第一面/第二面上形成源极、栅极、漏极，在所述沟道层第二面/第一面上形成底电极。
可选地，其中用步骤401替代步骤400，所述步骤401包括在所述凹槽的限制下以所述单晶种籽层为核心沿着所述凹槽生长第一沟道层、第一调节层和第二沟道层结构。
可选地，其中用步骤402替代步骤400，所述步骤402包括在所述凹槽的限制下以所述单晶种籽层为核心沿着所述凹槽生长第一沟道层、第二调节层和第二沟道层结构。
可选地，其中用步骤403替代步骤400，所述步骤403包括在所述凹槽的限制下以所述单晶种籽层为核心沿着所述凹槽生长第一沟道层、第一调节层、第二调节层和第二沟道层结构。
可选地，所述底电极至少与所述第一调节层、第二调节层、所述二维电子气以及二维空穴气中的一者连接。
可选地，底电极形成在所述沟道层的第二面上，所述第一/第二调节层具有P-型掺杂；或者底电极形成在所述沟道层的第一面上，所述第一/第二调节层具有N-型掺杂。
可选地，其中所述第一调节层中的掺杂的浓度小于5E18/cm3；第二调节层中的掺杂的浓度为1E17-5E19/cm3。
可选地，其中所述源极、所述栅极和所述漏极共面或不共面设置。
可选地，其中所述源极、所述漏极在所述沟道层上直接或间接形成，所述栅极在所述势垒层上直接或间接形成。
可选地，其中在生长所述沟道层之前，在所述种籽层上沉积一缓冲层。
可选地，其中所述种籽层设置在与所述源极对应的位置、与所述漏极对应的位置或者在对应于所述栅极与所述漏极之间的位置处。
可选地，其中所述种籽层设置在与所述漏极对应的位置时，还在所述种籽层上形成电流阻挡层。
可选地，其中当形成HEMT器件时，对所述源极区域和漏极区域进行N-型掺杂；当形成HHMT器件时，对所述源极区域和漏极区域进行P-型掺杂。
可选地，其中在所述凹槽的侧表面和底表面上形成介质层。
根据本公开内容的另一方面，提供一种半导体器件，包括：
一基材；
所述基材具有六角对称性晶格结构的一侧表面；
一单晶种籽层；
以所述种籽层为核心生长的一沟道层，所述沟道层凸出所述基材的上表面；
在所述凸出的沟道层上形成的势垒层；
在所述沟道层的第一面上形成的二维电子气和不可移动的本底正电荷，和/或在所述沟道层的第二面上形成的二维空穴气和不可移动的本底负电荷；
在所述沟道层的第一面/第二面上形成源极、栅极、漏极，在所述沟道层的第二面/第一面上形成的底电极；
当在所述沟道层的第二面上形成底电极时，形成为HEMT器件；当在所述沟道层的第一面上形成底电极时，形成为HHMT器件。
可选地，其中用第一沟道层、第一调节层和第二沟道层结构替代所述沟道层结构。
可选地，其中用第一沟道层、第二调节层和第二沟道层结构替代所述沟道层结构。
可选地，其中用第一沟道层、第一调节层、第二调节层和第二沟道层结构替代所述沟道层结构。
可选地，所述底电极至少与所述第一调节层、第二调节层、所述二维电子气以及二维空穴气中的一者连接，以调节所述器件的电场分布。
可选地，所述底电极形成在所述沟道层的第二面，所述第一/第二调节层具有P-型掺杂；或者所述底电极形成在所述沟道层的第一面，所述第一/第二调节层具有N-型掺杂。
可选地，其中所述第一调节层中的掺杂的浓度小于5E18/cm3；第二调节层中的掺杂的浓度为1E17-5E19/cm3。
可选地，其中所述源极、所述栅极和所述漏极共面或不共面设置。
可选地，其中在所述种籽层上还具有一缓冲层。
可选地，其中所述种籽层设置在与所述源极对应的位置、与所述漏极对应的位置或者在对应于所述栅极与所述漏极之间的位置。
可选地，其中所述种籽层设置在与所述漏极对应的位置，在所述种籽层上形成有电流阻挡层。
可选地，其中当形成HEMT器件时，对所述源极和漏极区域还具有N-型掺杂；当形成HHMT器件时，对所述源极和漏极区域还具有P-型掺杂。
可选地，其中在所述凹槽的侧壁和底表面上还具有介质层。
根据本公开内容的另一方面，提供一种互补型半导体器件，包括：前述中任一种半导体器件。
根据本公开内容的另一方面，提供一种射频设备，其包括前述中任一种的半导体器件。
根据本公开内容的另一方面，提供一种电力功率设备，其包括前述中任一种的半导体器件。
附图说明
下面，参照附图说明本公开内容的具体内容，这将有助于更加容易地理解本公开内容的以上和其他目的、特点和优点。应理解，附图只是为了示出本公开内容的原理，在附图中不必依照比例绘制出单元的尺寸和相对位置。在附图中：
图1-15为根据一种实施方式的半导体器件结构及其制造方法的示意图；
图16-19为可选的半导体器件结构及其制造方法的示意图；
图20-23为可选的半导体器件结构及其制造方法的示意图；
图24-28为可选的半导体器件结构及其制造方法的示意图；
图29-31为可选的半导体器件结构及其制造方法的示意图；
图32为可选的半导体器件结构及其制造方法的示意图；
图33为可选的半导体器件结构及其制造方法的示意图；
图34为可选的半导体器件结构的制造方法的示意图。
具体实施方式
在下文中将结合附图对本公开内容的示例性公开内容进行描述。为了清楚和简明起见，在说明书中并未描述实现本公开内容的所有特征。然而，应该了解，在实现本公开内容的过程中可以做出很多能够实施本公开内容的方式，以便实现开发人员的具体目标，并且这些方式可能会随着本公开内容的不同而有所改变。
在此，还需要说明的是，为了避免因不必要的细节而使本公开内容变得复杂，在附图中仅仅示出了与根据本公开内容的方案密切相关的器件结构，而省略了一些细节。
应理解的是，本公开内容并不会由于如下参照附图的描述而只限于所描述的实施形式。本公开内容中，在可行的情况下，不同实施方式之间的特征可替换或组合、或在一个实施方式中可省略一个或多个特征。
在以下具体实施方式中可参照附图，附图示出了本公开内容的一部分并例示了示例性实施方式。此外，应理解的是，在不脱离所请求保护的主题的范围的情况下，可以利用其它实施方式做出结构和/或逻辑改变。还应当指出，方向和位置(例如，上、下、顶部、底部、等等)仅用于帮助对附图中的特征的理解，并非在限制性意义上仅采用以下具体实施方式。
对于在本公开内容的说明书和所附权利要求书中所使用的术语，除非上下文另外明确指示，“一”、“一个”和“所述”也包括复数形式。还将理解的是，如本文中所使用的术语“和/或”指代并包括相关联的列出的项中的一个或多个的任何和所有可能的组合。
具体地，本公开内容的半导体器件为包含氮化物半导体材料的化合物半导体器件，也称为氮化物半导体器件，其中，氮化物半导体器件是III族氮化物半导体器件。进一步的，III族氮化物半导体器件包括使用纤锌矿(Wurtzite)III族氮化物半导体材料的晶体管。更进一步的，晶体管包含GaN半导体材料的GaN晶体管。特别的，GaN晶体管是常闭的晶体管GaN-HEMT和/或GaN-HHMT。
下面，参照图1-图15来描述根据一种实施方式的半导体器件及其制备方法。
如图1-15所示，该半导体器件包括基材100，基材100的材质可以根据实际需要选取，本公开内容并不限制基材100的具体材料，只要基材材料为能够满足形成的垂直其表面的垂直凹槽的侧表面具有六角对称性的晶格结构的基材材料皆可。示例性地，基材100的材料可为Si、Al2O3、SiC、GaN等。
由于硅基材具有价格便宜、可加工性强等优点，所以在本公开中以Si基材为例进行进一步的说明。示例性地，单晶硅基材可以是采用(110)或(112)面的硅基材。如图1所示，提供一基材100，基材具有第一表面1001；在基材100的第一表面1001上形成第一介质层101，示例性地，第一介质层101为通过热氧化或气相沉积形成的SiO2层，示例性地，第一介质层101的厚度约为0.5微米，应注意，本发明中的数值范围等仅作为示例而非对本公开内容的限制。第一介质层101具有平行于基材第一表面1001的第一表面1011。刻蚀部分第一介质层101和其下方的基材100，形成多个垂直的凹槽，具体而言，凹槽包括间隔排列的第一凹槽102和第二凹槽102’，第一凹槽和第二凹槽的结构和尺寸相同。示例性地，第一凹槽和第二凹槽的深度约为5微米。各凹槽的第一表面1021和第二表面1022的下部分别由基材暴 露出的第二表面1002和第三表面1003构成，其中基材的第二表面1002和第三表面1003具有六角对称的晶格结构，例如Si(111)面。可以理解的是，基材的第二表面和第三表面还可以是Al2O3(0001)面、SiC(0001)面、SiC(0001)面、GaN(0001)面、或GaN(0001 -)面等。各凹槽的第一表面1021和第二表面1022的上部分别由第一介质层101的第二表面1012和第三表面1013构成。如图5、6所示，在各凹槽的第三表面1023上形成第二介质层103，示例性地，第二介质层103可以为氧化形成的二氧化硅层，示例性地，其厚度为约500nm。如图7所示，在各凹槽的第一表面1021和第二表面1022上形成第四介质层105，示例性地，第四介质层的厚度为100nm左右，该第四介质层可避免在外延时，硅基材与含Ga的前驱体的相互作用，同时更有利于提高外延时的选择性。进一步的，如图8、9所示，去除第一凹槽的第二表面上的和第二凹槽的第一表面上的部分第四介质层105、在第一凹槽中暴露的基材100的第三表面1003和在第二凹槽中暴露的基材100的第二表面1002上形成单晶种籽层106。示例性地，单晶种籽层是ALN层，ALN晶体的生长方向是<0001>方向，其表面是(0001)面。示例性地，单晶种籽层所在的位置与后续器件的源极的形成位置对应。由于后续形成的器件结构在以源极作为参照点时，半导体器件结构能够呈现出对称的结构，且源极区域的电压很低，因此对晶体质量不敏感，从而将成核区域的晶体质量差的影响降低到最小。然后，如图10所示，以种籽层106为核心选择性生长沟道层201，沟道层201可为氮化物，示例性地，如本征GaN(i-GaN)或非故意掺杂GaN层。由于凹槽102的存在，沟道层201从种籽层开始沿着凹槽102开始生长，其中的生长包括沿着凹槽的第一方向的生长，也包括垂直于凹槽的第二方向的生长，沟道层201还可以在凹槽外生长，并通过平坦化或蚀刻技术去除凹槽外的沟道层201。
如图11所示，对沟道层两侧进行刻蚀，去除第一介质层101以及部分的基材100，使得沟道层201凸出刻蚀后的基材100的第四表面1004。沟道层201的具有自发极化效应和压电极化效应的第一面2013和与其相对的具有自发极化效应和压电极化效应的第二面2014，当沟道层为GaN时，第一面2013为(0001)面，第二面2014为(0001 -)面。如图12所示，在刻蚀后的基材100上形成第三介质层107，以隔离暴露的硅基材。示例性地，如图13所示，第三介质层可以为二氧化硅层。然后以覆盖沟道层201的方式形成势垒层202，势垒层可以是AlN层或AlGaN层，进而在沟道层的第一面2013和第二面2014上分别形成了二维电子气2DEG和二维空穴气2DHG，以及对应的在界面处还存在不可移动的本底正电荷和本底负电荷，其中本底正电荷吸引了二维电子气2DEG，本底负电荷吸引了二维空穴气2DHG，也即形成了一种互补型垂直沟道器件结构。
然后，如图14所示，在沿着沟道长度的方向上在势垒层202上分别形成源极401、栅极402、漏极403和底电极404。可以理解的是，当形成的器件为HEMT时，也可以使源极和漏极沿着二维电子气传输的方向形成在沟道201上，底电极与二维空穴气电接触；当形成的器件为HHMT时，源极和漏极也可以在沿着二维空穴气传输的方向上在沟道201上形成，底电极与二维电子气电接触。底电极可以是独立控制的电极，也可以和源极或者栅极电连接。底电极的位置可以位于栅极和漏极之间，也可以位于源极和栅极之间，也可以位于栅极下方。
由于凹槽的存在，使得沟道层在横向外延生长时可以生长的非常平直，进而后续包括沟道层的半导体器件的垂直表面可以借助于凹槽而形成地非常平直，因此很容易实现了较高的高宽比。更具体的，当沟道层201被用于作为垂直沟道时，可以使得在单位面积上可以实现更高的沟道密度-，从而降低了器件的电阻，提升了器件的性能。
此处以HEMT(高电子迁移率晶体管)为例进行说明，设置了底电极404之后，器件开启时，如图15所示，电流从漏极403向源极401方向流动(电子从源极401到漏极403方向流动)，此时底电极404的设置基本上对电流的流动没有影响；器件关闭时，漏极403处于高电压，此时沟道关闭，栅极402到漏极403的二维电子气由于漏极403高电压的存在从而被耗尽，进而只剩下本底的正电荷。同时由于底电极设置的电压远低于漏极的电压，底电极连接的2DHG在电场作用下也部分耗尽，剩下本底的负电荷，本底负电荷就可以产生一个电场，抵消掉2DEG中的部分电场，这些本底的负电荷与上述剩下的本底正电荷使得电场的分布更均匀，而达到降低局部电场强度的目的。对HHMT(高空穴迁移率晶体管)器件而言，与HEMT器件类似地，器件开启时，电流从漏极向源极(空穴从漏极到源极)方向流动。此时底电极的设置基本上对电流的流动没有影响。器件关闭时，漏极处于高负压，此时由于沟道关闭，从栅 极到漏极的2DHG被耗尽，只剩下本底的负电荷。这时，由于底电极电压远高于漏电极电压，底电极连接的2DEG在电场的作用下也部分耗尽，剩下本底的正电荷。这些本底的正电荷可以部分抵消2DHG沟道层本底负电荷的电场，使得电场的分布更均匀。
现参照图1-14来详细描述用于制造该半导体器件的制造方法，其中所示图1、2、6、10为剖视图，图3-5，7-9，11-14为俯视图。
步骤1：如图1所示，提供一基材100，基材可以是采用(110)或(112)面的硅基材。在基材100的第一表面1001上形成第一介质层101，示例性地，第一介质层101为热氧化或气相沉积形成的SiO2层。示例性地，第一介质层101的厚度约为0.5微米。
步骤2：如图2所示，在第一介质层101上间隔地进行光刻以露出第一介质层101的部分内部，接着在光刻位置刻蚀第一介质层101和其下方的基材100，形成垂直的凹槽，凹槽包括间隔排列的第一凹槽102和第二凹槽102’。各凹槽的两个侧表面即第一表面1021和第二表面1022的下部分别由经刻蚀后的基材暴露出的第二表面1002和第三表面1003构成。基材的第二表面1002和第三表面1003具有六角对称的晶格结构，例如Si(111)面。基材的第二表面和第三表面还可以是Al2O3(0001)面、SiC(0001)面、SiC(0001 -))面、GaN(0001)面或GaN(0001 -)面等。
步骤3：如图3所示，在步骤2形成的结构的基础上，共面沉积形成牺牲层104，示例性地，牺牲层104是氮化硅层，其厚度约为100纳米。可以理解的是，第一介质层和牺牲层的选择，以其二者之间具有高蚀刻选择比即可，例如在刻蚀牺牲层时，刻蚀剂基本上不对第一介质层进行蚀刻，或对其蚀刻极其缓慢。
步骤4：如图4所示，进行干法刻蚀，去除第一介质层101的第一表面1011上的牺牲层104和凹槽102102’的第三表面1023上的牺牲层104，保留各凹槽102(102’)的第一表面1021和第二表面1022上的牺牲层104。
步骤5：如图5所示，通过氧化工艺，在各凹槽的第三表面1023上形成第二介质层103(二氧化硅层)，凹槽的第一表面和第二表面由于保留的牺牲层104的保护没有被氧化，第二介质层可以避免在后续生长氮化物半导体时镓原子与硅基材的不兼容，避免出现回熔(melt-back)现象。同时，该第二介质层还可以有效阻绝氮化物半导体与硅基材之间的漏电流，并降低硅基材所带来的寄生电容。
步骤6：如图6所示，利用牺牲层104和第二介质层103(二氧化硅层)的刻蚀选择比，通过选择性湿法刻蚀去除各凹槽的第一表面和第二表面的牺牲层104。
步骤7：如图7所示，通过氧化工艺，在各凹槽102的第一表面和第二表面上分别形成较薄的第四介质层105(二氧化硅层)，使第四介质层的厚度与第一、第二介质层的厚度设置地不同，以满足在后续去除第四介质层时候，仍然还有足够厚的第一和第二介质层以保护基材。这些介质层可以避免在后续生长氮化物半导体时镓原子与硅基材的不兼容，避免出现回熔(melt-back)现象。
步骤8：如图8所示，涂敷光刻胶，在第一凹槽和第二凹槽之间形成光刻图形以暴露第一凹槽和第二凹槽之间部分的第一介质层101。可以理解的是，光刻图形可以暴露出第一凹槽和第二凹槽之间全部的第一介质层101。
步骤9：如图9所示，去除暴露的第一凹槽的第二表面上的和第二凹槽的第一表面上的第四介质层105，由于第一介质层的厚度远大于第四介质层的厚度，因此，在去除部分第四介质层的过程中，暴露的第一介质层部分仅被蚀刻很少的厚度并不会被完全去除，然后去除光刻胶，从而使得在第一凹槽中暴露出部分基材100的第三表面1003和在第二凹槽中暴露出部分基材100的第二表面1002。
步骤10：如图9所示，由于硅基材与镓之间的回熔(melt-back)效果，硅基材上不能直接沉积GaN。通常需要先沉积AlN的种籽层，再在此基础上形成后续的氮化物半导体结构。因此，在暴露出的第一凹槽中的基材100的第三表面1003上，以及在暴露出的第二凹槽中的基材100的第二表面1002上分别形成单晶AlN种籽层106，单晶AlN晶体的生长方向是<0001>，表面是(0001)面。需要指出的是，AlN的选择性很低，在通常的工艺条件下容易在介质层上也生成多晶或非晶的AlN，这对形成所需的结构是不利的。因此，需要在形成了种籽层后另行去除二氧化硅层上的AlN。或者在生长AlN种籽层时引入含氯气体以保证仅在硅基材上生长而不在二氧化硅层生长。
可以理解的是，如果采用其他基材例如Al2O3，则种籽层也可以是GaN。此时通过工艺调节可以较 容易实现仅在暴露的基材表面成核。
步骤11：如图10所示，然后以种籽层106为核心侧向外延生长沟道层201，由于凹槽的102的存在，沟道层201从种籽层开始沿着凹槽102开始侧向外延生长，其中生长包括沿着凹槽的第一方向的生长，也包括垂直于凹槽的第二方向的生长，沟道层201还可以在凹槽外生长，并通过平坦化或蚀刻技术去除凹槽外的沟道层201。侧向外延可以有效提升侧向外延区域的氮化物半导体晶体质量，进而提升器件的电学性能。去除凹槽外的沟道层，可以使得器件在形成过程中处于受约束的状态，有利于形成特定的结构和尺寸，有助于形成具有较高的高宽比的器件，提供了除生长工艺参数调整外的实现较高的高宽比器件的手段，而由于沟道层在凹槽中的生长受到凹槽的第一表面和第二表面的限制，沟道层的生长过程避免了不能保持完全垂直或者生长面不在同一平面的情况，以及可能出现多个、复杂的生长面的情况，方便实现对器件的控制与电学性能的提升。可以理解的是，沟道层201在凹槽外的生长也可以不必去除，而形成突出凹槽的部分。
步骤12：如图11所示，形成光刻图形，从上面露出相邻第一凹槽和第二凹槽之间的全部区域，刻蚀区域中第一介质层101和部分的基材100的材料，使得凹槽102中的覆盖着第四介质层的沟道层突出于刻蚀后的基材的第四表面1004。
步骤13：如图12所示，在刻蚀后的基材100的第四表面1004上形成第三介质层107，示例性地，第三介质层可以为氧化形成的二氧化硅层，然后去除覆盖着沟道层201的上的第四介质层，从而露出沟道层201的具有自发极化效应和压电效应的第一面2013和与其相对的具有自发极化效应和压电极化效应的第二面2014。
步骤14：如图13所示，在沟道层201上覆盖形成势垒层202，势垒层可以是AlN层或AlGaN层，进而在沟道层的第一面2013和第二面2014上分别形成了二维电子气2DEG和二维空穴气2DHG。
可以理解的是，在生长沟道层之前，还可以先沉积形成缓冲层。
步骤15：如图14所示，沉积绝缘层，对绝缘层进行光刻刻蚀，然后在其上沉积金属，对于HEMT而言，沿着二维电子气传输方向在沟道层201的第一面处分别形成源极401、漏极403以及沿着二维电子气传输方向在势垒层202上形成栅极402，其中栅极位于源极和漏极的中间。可选地，源极、栅极及漏极都形成在沿着二维电子气传输方向的势垒层202上。在二维空穴气所在的第二面处形成底电极404。对于HHMT而言，在沟道层201，沿着二维空穴气传输方向在第二面处分别形成源极、漏极以及沿着二维空穴气传输方向在势垒层202上形成栅极，其中栅极位于源极和漏极的中间。可选地，源极、栅极及漏极都形成在沿着二维空穴气传输方向的势垒层202上。在二维电子气所在的第一面处形成底电极404。
参照图16-19来描述可选的半导体器件及其制造方法，图16-19均为俯视图。
可选地，在凹槽内沿着沟道的第一表面和第二表面的方向形成有沟道层的第一子层2011、第一调节层2013和沟道层的第二子层2012层，沟道层的第一子层2011、第一调节层2013和沟道层的第二子层2012完全填满凹槽且使得各层平行于沟道层的第一表面且共面。可以理解的是，第一调节层中可以具有P-型掺杂，或者具有N-型掺杂，示例性地，P-型掺杂是P-型GaN，N-型掺杂是N-型GaN。示例性地，掺杂浓度小于5E18/cm3，具体选择是进行P-型掺杂还是N-型掺杂视后续器件的具体类型而定，对于HEMT器件则选择进行P-型掺杂，对于HHMT器件则选择进行N-型掺杂，可以理解的是，掺杂可以是渐变的。第一调节层在沟道层的第一面的投影落在栅极和漏极之间的范围内，或与栅极在该方向上的投影有部分重叠的范围。
其中掺杂的第一调节层，其与沟道层的侧表面垂直或倾斜设置，通过设计的掺杂分布，进而在器件关闭时对外加电场反应并改变电场分布，因此可以有效降低局部电场强度，特别是减小靠近漏极的栅极端的电场峰值。这里的调节层优选为侧向外延生长的，其与离子注入的方式相比，不会出现离子注入损伤等问题，具有很好的电学性能
器件关态的时候，由于底电极与第一调节层电连接，从而避免了对电场进行调节的栅漏极之间的掺杂层(电场调节掺杂层)电势不稳定的情况。可以理解的是，也可以不设置底电极而仅仅依靠浮置的电场调节掺杂层来降低局部电场强度。
可以理解的是，底电极同时与二维电荷载流子气及第一调节层电接触，从而通过第一调节层的掺杂 与互补型沟道中的一种类型的本底电荷抵消掉另一种类型的二维电荷载流子中的部分电场的作用，达到降低局部电场强度的目的。
下面具体描述用于制造该半导体器件的制造方法。
步骤11’：如图16-19所示，在形成种籽层106后，以种籽层106为核心选择性生长沟道层的第一子层2011，由于凹槽102的存在，第一子层2011从种籽层开始沿着凹槽102开始侧向外延生长，其中生长包括沿着凹槽的第一表面或第二表面的第一方向的生长，以及垂直于凹槽的第三表面的生长。然后以第一子层2011为核心，生长掺杂的第一调节层2013，第一调节层2013的生长同样包括沿着凹槽的第一表面或第二表面的第一方向的生长，也包括垂直于凹槽的第一表面或第二表面的第二方向的生长，以及垂直于凹槽的第三表面的生长。第一调节层2013在沟道层第一面的投影落在栅极和漏极之间的范围内，或与栅极在该方向上的投影有部分的重叠。
然后，以第一调节层2013为核心，继续生长沟道层的第二子层2012，沟道层的第二子层也可以是本征GaN层或非故意掺杂GaN层。沟道层的第二子层2012的生长方向与第一子层或第一调节层的生长方向相同。最后通过平坦化或蚀刻技术去除垂直于凹槽的第三表面生长且位于凹槽外的第一子层、第一调节层和第二子层的部分，从而使得第一子层、第一调节层和第二子层都位于凹槽内，形成具有共面的结构。共面结构可以使得器件在形成过程中处于受约束的状态，有利于形成特定的结构和尺寸，有助于形成具有较高的高宽比的器件，提供了除生长工艺参数调整外的实现高宽比器件的手段，而由于沟道层和第一调节层在凹槽中的生长受到凹槽的第一表面和第二表面的限制，沟道层和第一调节层的生长过程避免了不能保持完全垂直或者生长面不在同一平面的情况，且避免了可能出现多个、复杂的生长面的情况，方便实现对器件的控制与电学性能的提升。
参照图20-23来描述可选的半导体器件及其制造方法，所示图20-23为俯视图。
可选地，在凹槽内沿着沟道的第一表面和第二表面的方向形成有沟道层的第一子层2011、第二调节层2014和沟道层的第二子层2012层，第一子层、第二调节层2014和第二子层2012完全填满凹槽且使得各层平行于沟道的第一表面且共面。第二调节层用于控制阈值电压。可以理解地，第二调节层中具有P-型掺杂，或者N-型掺杂，示例性地，P-型掺杂是P-型GaN，N-型掺杂是N-型GaN，示例性地，第二调节层2014的掺杂浓度为1E17-5E19/cm3，更优的为1E+18/cm3-5E+19/cm3。P-型GaN层可以耗尽沟道层的第一面的二维电子气；N-型GaN层可以耗尽沟道层的第二面的二维空穴气，进而使器件具有常闭状态。具体选择是进行P-型掺杂还是N-型掺杂视后续器件的具体类型而定，对于HEMT器件则选择进行P-型掺杂，对于HHMT器件则选择进行N-型掺杂。可以理解的是，掺杂可以是渐变的。第二调节层在沟道层的第一面的投影落在栅极的范围内。第二调节层的掺杂浓度、尺寸参数等可以根据器件参数设置，只要能够耗尽其上方95％-100％的二维电子气或二维空穴气即可，二维电荷载流子气的浓度越高，相应的掺杂浓度可以随之提高。
器件关态的时候，底电极可以连接第二调节层和二维载流子气，或者是仅连接二维载流子气，当形成HEMT器件时，底电极与二维空穴气连接，当形成HHMT器件时，底电极与二维电子气连接。底电极的连接方式使得第二调节层和二维载流子协同或二维载流子的单独作用，避免了电场调节掺杂层电势不稳定的情况。
下面具体描述用于制造该半导体器件的制造方法
步骤11’：如图20-23所示，在形成种籽层106后，以种籽层106为核心选择性生长沟道层的第一子层2011，由于凹槽102的存在，第一子层2011从种籽层开始沿着凹槽102开始侧向外延生长，其中生长包括沿着凹槽的第一表面或第二表面的第一方向的生长，以及垂直于凹槽的第三表面的生长。然后以第一子层2011为核心，生长掺杂的第二调节层2014，第二调节层2014的生长同样包括沿着凹槽的第一表面或第二表面的第一方向的生长，也包括垂直于凹槽的第一表面或第二表面的第二方向的生长，以及垂直于凹槽的第三表面的生长。第二调节层2014位于后续器件的投影方向上的栅极的投影范围内。
然后，以第二调节层2014为核心，继续生长沟道层的第二子层2012，沟道层的第二子层也可以是本征GaN层或非故意掺杂GaN层。沟道层的第二子层2012的生长方向与第一子层或第二调节层的生长方向相同。最后通过平坦化或蚀刻技术去除垂直于凹槽的第三表面生长且位于凹槽外的第一子层、第二 调节层和第二子层的部分，从而使得第一子层、第二调节层和第二子层都位于凹槽内，形成具有共面的结构。共面结构可以使得器件在形成过程中处于受约束的状态，有利于形成特定的结构和尺寸，有助于形成具有较高的高宽比的器件，提供了除生长工艺参数调整外的实现高宽比器件的手段，而由于沟道层和第二调节层在凹槽中的生长受到凹槽的第一表面和第二表面的限制，沟道层和第二调节层的生长过程避免了不能保持完全垂直或者生长面不在同一平面的情况，且避免了可能出现多个、复杂的生长面的情况，方便实现对器件的控制与电学性能的提升。
参照图24-28来描述可选的半导体器件及其制造方法，所示图24-28为俯视图。
可选地，在凹槽内沿着沟道的第一表面和第二表面的方向形成有沟道层的第一子层2011、第二调节层2014、第一调节层2013和沟道层的第二子层2012层，沟道层的第一子层、第二调节层2014、第一调节层2013和沟道层的第二子层完全填满凹槽且使得各层平行于沟道的的第一表面且共面。第二调节层用于控制阈值电压，第一调节层用于调节电场分布，特别是栅电极边缘处的电场分布。可以理解地，第一调节层、第二调节层中具有P-型掺杂，或者N-型掺杂，示例性地，P-型掺杂是P-型GaN，N-型掺杂是N-型GaN，示例性地，第二调节层2014的掺杂浓度为1E17-5E19/cm3，更优的为1E+18/cm3-5E+19/cm3。P-型GaN层可以耗尽沟道层的第一面的二维电子气；N-型GaN层可以耗尽沟道层的第二面的二维空穴气，进而使器件具有常闭状态。具体选择是进行P-型掺杂还是N-型掺杂视后续器件的具体类型而定，对于HEMT器件则选择进行P-型掺杂，对于HHMT器件则选择进行N-型掺杂。可以理解的是，掺杂可以是渐变的。第二调节层在沟道层的第一面的投影落在栅极的范围内；第一调节层在沟道层的第一面的投影落在栅极和漏极之间的范围内，或与栅极在该方向上的投影有部分的重叠范围。第二调节层的的掺杂浓度、尺寸参数等可以根据器件参数设置，只要能够耗尽其上方95％-100％的二维电子气或二维空穴气即可，二维电荷载流子气的浓度越高，相应的掺杂浓度可以随之提高。示例性地，第一调节层的掺杂浓度小于5E18/cm3。
其中掺杂的第一调节层和第二调节层，其与沟道层的侧表面垂直或倾斜设置，通过设计的掺杂分布，进而在器件关闭时对外加电场反应并改变电场分布，因此可以有效降低局部电场强度，特别是减小靠近漏极的栅极端的电场峰值。这里的调节层优选为侧向外延生长的，与离子注入的方式相比，不会出现离子注入损伤等问题，具有很好的电学性能
器件关态的时候，底电极可以与第一调节层、第二调节层和二维载流子气进行各种电连接，例如，底电极可以连接第一调节层和/或第二调节层，也可以连接第一调节层和二维载流子气，或者是同时连接第一调节层、第二调节层和二维载流子气等，通过第一调节层、第二调节层与二维载流子的各种形式的单独或协同作用，可以避免电场调节掺杂层电势不稳定的情况。
下面具体描述用于制造该半导体器件的制造方法。
步骤11’：如图24-28所示，在形成种籽层106后，以种籽层106为核心选择性生长沟道层的第一子层2011，由于凹槽102的存在，第一子层2011从种籽层开始沿着凹槽102开始侧向外延生长，其中生长包括沿着凹槽的第一表面或第二表面的第一方向的生长，以及垂直于凹槽的第三表面的生长。然后以第一子层2011为核心，生长掺杂的第二调节层2014，第二调节层2014的生长同样包括沿着凹槽的第一表面或第二表面的第一方向的生长，也包括垂直于凹槽的第一表面或第二表面的第二方向的生长，以及垂直于凹槽的第三表面的生长。第二调节层2014位于后续器件的投影方向上的栅极的投影范围内。然后以第二调节层2014为核心，生长掺杂的第一调节层2013，第一调节层2013的生长同样包括沿着凹槽的第一表面或第二表面的第一方向的生长，也包括垂直于凹槽的第一表面或第二表面的第二方向的生长，以及垂直于凹槽的第三表面的生长。第一调节层2013位于后续器件的投影方向上的栅极到漏极的范围内，或者与栅极的投影有部分重叠。然后以第一调节层2013为核心，继续生长沟道层的第二子层2012，第二子层也可以是本征GaN层或非故意掺杂的GaN层。第二子层2012的生长方向与第一子层或2个调节层的生长方向相同。最后通过平坦化或蚀刻技术去除垂直于凹槽的第三表面生长且位于凹槽外的第一子层、2个调节层和第二子层的部分，从而使得第一子层、2个调节层和第二子层都位于凹槽内，形成具有共面的结构。共面结构可以使得器件在形成过程中处于受约束的状态，有利于形成特定的结构和尺寸，有助于形成具有较高的高宽比的器件，提供了除生长工艺参数调整外的实现高宽比器件的手段， 而由于沟道层和2个调节层在凹槽中的生长受到凹槽的第一表面和第二表面的限制，沟道层和2个调节层的生长过程避免了不能保持完全垂直或者生长面不在同一平面的情况，且避免了可能出现多个、复杂的生长面的情况，方便实现对器件的控制与电学性能的提升。
如附图29-31所示，可选地，对沟道层的一侧进行刻蚀，去除第一介质层101以及部分基材100，使得基材具有第一表面和一低于且平行于第一表面的第五表面。当形成HEMT器件时，暴露沟道层201的具有自发极化效应和压电极化效应的第一面2013，当沟道层为GaN时，第一面2013为(0001)面。此时，与第一面2013相对的具有自发极化效应和压电极化效应的第二面2014仍被基材和第一介质层掩盖，第二面2014为GaN的(0001 -)面。当形成HHMT器件时，暴露沟道层201的具有自发极化效应和压电极化效应的第二面2014，当沟道层为GaN时，第二面2014为(0001 -)面。此时，与第二面2014相对的具有自发极化效应和压电极化效应的第一面2013仍被基材和第一介质层掩盖，第一面2013为GaN的(0001)面。在刻蚀后的基材100上形成一第三介质层107以隔离暴露的硅基材，示例性地，第三介质层可以为二氧化硅层。然后在沟道层201的第一面2013上或第二面2014上形成势垒层202，势垒层是AlN层或AlGaN层，从而在沟道层的第一面2013上形成二维电子气2DEG或者在沟道层的第二面2014上形成二维空穴气2DHG。
从而底电极404与第一调节层2013连接或者底电极与第一调节层2013和第二调节层2014连接，进而在器件关闭时对外加电场反应并改变电场分布，因此可以有效降低局部电场强度，特别是减小靠近漏极的栅极端的电场峰值。
现将参照29-31结合前述的制造方法来示例性描述用于制造该HEMT半导体器件的制造方法。
步骤12’，如图29所示，形成光刻图形，露出沟道层第一面2013侧的区域，刻蚀该区域中第一介质层101和部分基材100，暴露沟道层201的具有自发极化效应和压电极化效应的第一面侧的第四介质层。与第一面2013相对的具有自发极化效应和压电极化效应的第二面2014仍被第四介质层、基材和第一介质层包围。
步骤13’，如图30所示，在刻蚀后的基材100上形成一第三介质层107’，示例性地，第三介质层可以为通过氧化形成的二氧化硅层。在通过该第三介质层隔离暴露的硅基材的情况下，去除覆盖在沟道层201的第一面2013上的第四介质层。
步骤14’，如图31所示，在沟道层201的第一面2013上化学沉积形成第二半导体层202，第二半导体层可以是AlN层或AlGaN层，从而能够在沟道层的第一面2013上形成二维电子气2DEG。
可以理解的是，HHMT半导体器件的制造方法与其类似，在此不再赘述。
可以理解的是，在一些实施方式中，还可以变化形成光刻图形的方式，从上面露出相邻第一凹槽和第二凹槽之间的全部区域，刻蚀该区域中第一介质层101和部分的基材100，使得凹槽102中的覆盖着第四介质层的沟道层突出于刻蚀后的基材的第四表面，然后仅对沟道层的第一面/第二面侧的区域进行进一步的蚀刻，其具体方法可参照前述实施方式，在此不再赘述。
可选地，单晶种籽层所在的位置与后续器件的第三电极(漏极)的形成位置对应，此时，为避免成核区域的晶体质量较差以及漏电流较大等问题，如图32所示，可以在单晶种籽层上加入电流阻挡层，电流阻挡层例如可以是重掺杂的C或Fe元素的，C或Fe的掺杂浓度可以为1E17-1E20/cm3。
可选地，单晶种籽层的位置还可以设置在源电极和漏电极之间的区域。示例性地，可以通过使种籽层所在的位置与后续漏电极区域所在的位置隔开一定的距离来克服上述技术问题。
可选地，对于设置单晶种籽层的区域，可以通过光刻来暴露相应的第一和第二凹槽的区域。
电流阻挡层可以在以单晶种籽层为核心进行外延生长时，通过进行相应的掺杂来形成。
可选地，如图33所示，在源极区域和漏极区域进行掺杂以降低接触电阻。可以理解的是，当形成HEMT器件的时候，源极区域和漏极区域的掺杂类型是N-型；当形成HHMT器件的时候，源极区域和漏极区域的掺杂类型是P-型。
可选地，在HEMT器件中，可去除势垒层使源极和/或漏极与沟道层物理接触，并与二维电子载流 子气(2DEG)形成欧姆接触，由于掺杂后的源极区域和漏极区域的存在，通过工艺和结构的设计，这种直接与沟道层物理接触的方式，更有利于降低欧姆接触电阻。
可选地，在HHMT器件中，由于P-型欧姆接触更加难于形成，因此，当去除势垒层使源极(和/或漏极)与沟道层物理接触，并与二维空穴载流子气(2DHG)形成欧姆接触时，由于掺杂后的源极区域和漏极区域的存在，通过工艺和结构的设计，这种直接与沟道层物理接触的方式，更有利于降低欧姆接触电阻。
结合前述制造方法来示例性描述用于制造该半导体器件的制造方法。
以种籽层与源极区域对应的情况为例来说明源极区域和漏极区域的掺杂。种籽层与漏极区域对应的情况、或者种籽层位于栅极和漏极区域之间的情况与种籽层与源极区域对应的情况类似，在此不再赘述。如图25所示，在形成种籽层后，在以种籽层为核心进行沟道层201的生长过程中，在源极区域进行相应的P-型或N-型掺杂。
可选地，在以种籽层为核心进行沟道层201的生长过程中，在进行相应的掺杂之前，先生长本征的(非掺杂的)沟道层或非故意掺杂的沟道层，而后再进行掺杂的源极区域的生长。
接着，在掺杂的源极区域形成后，再继续进行本征的沟道层或非故意掺杂的沟道层的外延生长形成沟道区域。可以理解的是，在沟道区域可以选择进行相应的掺杂形成第一调节层和/或第二调节层。
然后，可以在后一步的外延生长沟道层的过程中，在漏极区域进行相应的P-型或N-型掺杂。
可以理解的是，可以是其中漏极区域和源极区域的掺杂与调节层的掺杂同时进行，还可以是漏极区域的掺杂、源极区域的掺杂和调节层的掺杂先后进行。
进一步可以理解的是，器件可以形成为HHMT和HEMT同时存在的互补型半导体器件。
一种电源装置，包括上述的半导体器件的任一种。电源装置包括有一次电路、二次电路和变压器等，其中一次电路和二次电路中均具有开关元件，其中，开关元件采用上述的半导体器件的任一种。
一种手机，包括上述的半导体器件的任一种。手机包括显示屏，充电单元等，其中，充电单元包括上述的半导体器件的任一种。
一种放大器，放大器可以用于移动电话基站、光通信系统等领域中的功率放大器，所述功率放大器可以包括上述的半导体器件的任一种。
本公开内容的方案至少能有助于实现如下效果之一：所述半导体器件能够减小栅极漏电流，具有高阈值电压、高功率、高可靠性，能够实现低导通电阻和器件的常关状态，能够提供稳定的阈值电压，从而使得半导体器件具有良好的开关特性。
本公开内容的方案还能有助于实现如下效果之一：可以有效地降低局部电场强度，提高器件的整体性能与可靠性；所述半导体器件的结构和制备工艺较为简单，能有效降低生产成本。
以上结合具体的实施方式对本公开内容进行了描述，但本领域技术人员应该清楚，这些描述都是示例性地，并不是对本公开内容的保护范围的限制。本领域技术人员可以根据本公开内容的精神和原理对本公开内容做出各种变型和修改，这些变型和修改也在本公开内容的范围内。
工业实用性
本公开提供的半导体器件及其制造方法，工艺简单、成本低廉、节能，且具有较高高宽比、可在单位面积上实现更高的沟道密度，具有高耐受电压、高功率和低导通电阻等高性能。

Claims (30)

  1. 一种调节半导体器件分布电场的方法，包括：
    步骤100：提供基材；
    步骤200：在所述基材上形成凹槽，所述凹槽的侧表面具有六角对称性的晶格结构；
    步骤300：在所述凹槽中的所述侧表面上形成一单晶种籽层；
    步骤400：以所述单晶种籽层为核心且受所述凹槽限制沿着所述凹槽生长沟道层；
    步骤500：刻蚀所述基材，使所述沟道层凸出刻蚀后的基材的上表面；
    步骤600：在露出的沟道层上形成势垒层，接着，在所述沟道层的第一面形成二维电子气和不可移动的本底正电荷，和/或在所述沟道层的第二面上形成二维空穴气和不可移动的本底负电荷；
    步骤700：在所述沟道层的第一面/第二面上形成源极、栅极、漏极，在所述沟道层的第二面/第一面上形成底电极。
  2. 如权利要求1所述的方法，用步骤401替代步骤400，所述步骤401包括以所述单晶种籽层为核心且受所述凹槽限制沿着所述凹槽生长第一沟道层、第一调节层和第二沟道层。
  3. 如权利要求1所述的方法，用步骤402替代步骤400，所述步骤402包括以所述单晶种籽层为核心且受所述凹槽限制沿着所述凹槽生长第一沟道层、第二调节层和第二沟道层。
  4. 如权利要求1所述的方法，用步骤403替代步骤400，所述步骤403包括以所述单晶种籽层为核心且受所述凹槽限制沿着所述凹槽生长第一沟道层、第一调节层、第二调节层和第二沟道层。
  5. 如权利要求1-4任一项所述的方法，
    在以所述单晶种籽层为核心且受所述凹槽限制沿着所述凹槽生长沟道层的情况下，所述底电极与所述二维电子气/所述二维空穴气中的一者连接；
    在以所述单晶种籽层为核心且受所述凹槽限制沿着所述凹槽生长第一沟道层、第一调节层和第二沟道层的情况下，所述底电极与所述第一调节层、所述二维电子气/所述二维空穴气连接；
    在以所述单晶种籽层为核心且受所述凹槽限制沿着所述凹槽生长第一沟道层、第二调节层和第二沟道层的情况下，所述底电极与所述第二调节层、所述二维电子气/所述二维空穴气连接；
    在以所述单晶种籽层为核心且受所述凹槽限制沿着所述凹槽生长第一沟道层、第一调节层、第二调节层和第二沟道层的情况下，所述底电极与所述第一调节层、第二调节层、所述二维电子气/所述二维空穴气连接。
  6. 如权利要求5所述的方法，底电极形成在所述沟道层的第二面上，所述第一调节层/第二调节层具有P-型掺杂；或者底电极形成在所述沟道层的第一面上，所述第一调节层/第二调节层具有N-型掺杂。
  7. 如权利要求6所述的方法，所述第一调节层中的掺杂的浓度小于5E18/cm3；第二调节层中的掺杂的浓度为1E17-5E19/cm3。
  8. 如权利要求5所述的方法，所述源极、所述栅极和所述漏极共面或不共面设置。
  9. 如权利要求5所述的方法，所述源极、所述漏极在所述沟道层上直接或间接形成，所述栅极在所述势垒层上直接或间接形成。
  10. 如权利要求1-4中任一个所述的方法，在生长所述沟道层之前，在所述种籽层上沉积一缓冲层。
  11. 如权利要求1-4中任一个所述的方法，所述种籽层设置在与所述源极对应的位置、与所述漏极对应的位置或者在对应于所述栅极与所述漏极之间的位置处。
  12. 如权利要求1-4中任一个所述的方法，所述种籽层设置在与所述漏极对应的位置时，在所述种籽层上还形成电流阻挡层。
  13. 如权利要求1-4中任一个所述的方法，当形成HEMT器件时，对所述源极区域和漏极区域进行N-型掺杂；当形成HHMT器件时，对所述源极区域和漏极区域进行P-型掺杂。
  14. 如权利要求1-4中任一个所述的方法，在所述凹槽的侧表面和底表面上形成介质层。
  15. 一种半导体器件，包括：
    基材，所述基材具有六角对称性晶格结构的侧表面；
    单晶种籽层；
    以所述种籽层为核心生长的沟道层，所述沟道层凸出所述基材的上表面；
    在所述凸出的沟道层上形成的势垒层；
    在所述沟道层的第一面上形成的二维电子气和不可移动的本底正电荷，和/或在所述沟道层的第二面上形成的二维空穴气和不可移动的本底负电荷；
    在所述沟道层的第一面/第二面上形成源极、栅极、漏极，在所述沟道层的第二面/第一面上形成的底电极；
    当在所述沟道层的第二面上形成底电极时，形成为HEMT器件；当在所述沟道层的第一面上形成底电极时，形成为HHMT器件。
  16. 如权利要求15所述的半导体器件，用第一沟道层、第一调节层和第二沟道层替代所述沟道层。
  17. 如权利要求15所述的半导体器件，用第一沟道层、第二调节层和第二沟道层替代所述沟道层。
  18. 如权利要求15所述的半导体器件，用第一沟道层、第一调节层、第二调节层和第二沟道层替代所述沟道层。
  19. 如权利要求15-18中任一项所述的半导体器件，
    在包括以所述种籽层为核心生长的沟道层的情况下，所述底电极与所述二维电子气/所述二维空穴气连接；
    在用第一沟道层、第一调节层和第二沟道层替代所述沟道层的情况下，所述底电极与所述第一调节层、所述二维电子气/所述二维空穴气连接；
    在用第一沟道层、第二调节层和第二沟道层替代所述沟道层的情况下，所述底电极与所述第二调节层、所述二维电子气/所述二维空穴气连接；
    在用第一沟道层、第一调节层、第二调节层和第二沟道层替代所述沟道层的情况下，所述底电极与所述第一调节层、所述第二调节层、所述二维电子气/所述二维空穴气连接，以调节所述器件的电场分布。
  20. 如权利要求19所述的半导体器件，所述底电极形成在所述沟道层的第二面，所述第一调节层/第二调节层具有P-型掺杂；或者所述底电极形成在所述沟道层的第一面，所述第一调节层/第二调节层具有N-型掺杂。
  21. 如权利要求20所述的半导体器件，所述第一调节层中的掺杂的浓度小于5E18/cm3；所述第二调节层中的掺杂的浓度为1E17-5E19/cm3。
  22. 如权利要求19所述的半导体器件，所述源极、所述栅极和所述漏极共面或不共面设置。
  23. 如权利要求15-18中任一个所述的半导体器件，在所述种籽层上还具有一缓冲层。
  24. 如权利要求15-18中任一个所述的半导体器件，所述种籽层设置在与所述源极对应的位置、与所述漏极对应的位置或者在对应于所述栅极与所述漏极之间的位置。
  25. 如权利要求15-18中任一个所述的半导体器件，所述种籽层设置在与所述漏极对应的位置，在所述种籽层上还形成有电流阻挡层。
  26. 如权利要求15-18中任一个所述的半导体器件，当形成HEMT器件时，所述源极和漏极区域还具有N-型掺杂；当形成HHMT器件时，所述源极和漏极区域还具有P-型掺杂。
  27. 如权利要求15-18中任一个所述的半导体器件，在所述基材上形成有凹槽，在所述凹槽的侧壁和底表面上还具有介质层。
  28. 一种互补型半导体器件，包括：如权利要求15-27中任一项所述的半导体器件。
  29. 一种射频设备，其包括权利要求15-28中任一项所述的半导体器件。
  30. 一种电力功率设备，其包括权利要求15-28中任一项所述的半导体器件。
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