WO2022001808A1 - 一种系统以及中断处理方法 - Google Patents

一种系统以及中断处理方法 Download PDF

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Publication number
WO2022001808A1
WO2022001808A1 PCT/CN2021/102011 CN2021102011W WO2022001808A1 WO 2022001808 A1 WO2022001808 A1 WO 2022001808A1 CN 2021102011 W CN2021102011 W CN 2021102011W WO 2022001808 A1 WO2022001808 A1 WO 2022001808A1
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WIPO (PCT)
Prior art keywords
interrupt
virtual
identifier
physical
processor
Prior art date
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Ceased
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PCT/CN2021/102011
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English (en)
French (fr)
Inventor
王海滨
俞增辉
马剑
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Filing date
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Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Priority to KR1020257031783A priority Critical patent/KR20250150147A/ko
Priority to EP24221037.5A priority patent/EP4550140A3/en
Priority to EP21832328.5A priority patent/EP4170492B1/en
Priority to BR112022026693A priority patent/BR112022026693A2/pt
Priority to JP2022580544A priority patent/JP7615474B2/ja
Priority to KR1020237002968A priority patent/KR102865023B1/ko
Publication of WO2022001808A1 publication Critical patent/WO2022001808A1/zh
Priority to US18/146,943 priority patent/US12511152B2/en
Anticipated expiration legal-status Critical
Priority to US19/402,608 priority patent/US20260079742A1/en
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4831—Task transfer initiation or dispatching by interrupt, e.g. masked with variable priority
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45545—Guest-host, i.e. hypervisor is an application program itself, e.g. VirtualBox
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G06F2009/45575—Starting, stopping, suspending or resuming virtual machine instances
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G06F9/45533—Hypervisors; Virtual machine monitors
    • G06F9/45558—Hypervisor-specific management and integration aspects
    • G06F2009/45579—I/O management, e.g. providing access to device drivers or storage

Definitions

  • the present application relates to the field of computers, and in particular, to a system and an interrupt processing method.
  • Virtualization technology achieves "virtualization” and "isolation” of the physical computer hardware by adding a specific software layer to a physical computer, including the host layer and the virtual computer layer.
  • Each software layer includes different operating states, such as user mode and kernel mode.
  • the diversification of software levels and operating states increases the processing links for certain requirements within the physical computer, thereby increasing the processing delay of these requirements.
  • Interrupt processing is a key requirement of computing devices.
  • virtual machine monitor provides users with virtual interrupt controller and virtual interrupt translation service through interrupt virtualization technology.
  • the process of delivering the virtual interrupt to the virtual processor is controlled based on the software of the virtual machine monitor.
  • the VMM can implement the virtual interrupt by writing the virtual interrupt into a register corresponding to the virtual processor.
  • the VMM can write the virtual interrupt into the system register corresponding to the virtual CPU, in order to ensure the timely virtual interrupt Write, the VMM will actively trigger the virtual machine to exit the virtual machine (VM-exit), and write the virtual interrupt to the system register corresponding to the virtual CPU when the virtual machine is re-run (VM-entry).
  • VM-exit virtual machine to exit the virtual machine
  • VM-entry write the virtual interrupt to the system register corresponding to the virtual CPU when the virtual machine is re-run
  • the virtual processor temporarily stops running, thus increasing the virtual interrupt processing delay.
  • the present application provides a computing device, the computing device includes a hardware layer and a host computer running on the hardware layer; wherein, the host computer is used to obtain a virtual interrupt; a virtual device in the virtual machine Virtual interrupts can be enabled, and virtual devices can be virtual devices simulated by software, such as serial ports simulated by software, etc.; the back-end driver (such as QEMU) in the host can capture the virtual machine's behavior of enabling virtual interrupts and trigger virtual interrupts , the virtual interrupt may include a virtual device identifier Device ID and a virtual interrupt vector identifier Vector ID, wherein, when the interrupt resource is initialized, a virtual device identifier Device ID and a virtual interrupt vector identifier Vector ID are allocated to the virtual processor of the virtual machine.
  • Each virtual processor uniquely corresponds to one virtual device identifier Device ID and multiple virtual interrupt vector identifiers Vector ID;
  • the virtual device identifier Device ID in the virtual interrupt can indicate which virtual device is enabled for the virtual interrupt, and the virtual interrupt vector identifier
  • the Vector ID can indicate which virtual interrupt is specifically among the multiple virtual interrupts allocated by the virtual device;
  • the virtual interrupt can be delivered to the VMM, and correspondingly, the VMM in the host machine 200 can obtain the virtual interrupt;
  • the hardware layer is configured to acquire a corresponding virtual interrupt identifier and a virtual processor according to the physical interrupt identifier identifier; wherein the virtual interrupt is configured to interrupt a target virtual processor, the virtual interrupt and the physical interrupt identifier uniquely correspond to the virtual processor identifier, and the virtual processor identifier is used to indicate the target virtual processor a processor; and, passing the virtual interrupt identifier to the target virtual processor.
  • the hardware layer may include a physical interrupt translation service (interrupt translation service, ITS) and a physical interrupt controller (generic interrupt controller, GIC), wherein the physical ITS can obtain a physical interrupt, and the physical interrupt is used to interrupt the virtual CPU, The physical ITS can determine which virtual CPU the physical interrupt corresponds to, and determine the virtual interrupt identifier corresponding to the physical interrupt (which can indicate which virtual interrupt is specific); the physical GIC can send the virtual interrupt identifier to the virtual CPU.
  • ITS interrupt translation service
  • GIC generator
  • the physical ITS may include a register and an arithmetic circuit
  • the register may store the correspondence between the physical interrupt and the virtual interrupt identifier (more specifically, the register stores the base address of the correspondence between the physical interrupt and the virtual interrupt identifier), And the correspondence between the physical interrupt and the virtual processor identifier (more specifically, the register stores the base address of the correspondence between the physical interrupt and the virtual processor identifier), and the arithmetic circuit can obtain the above-mentioned correspondence from the register ( The arithmetic circuit can obtain the above-mentioned base address from the register, and obtain the corresponding relationship between the physical interrupt and the virtual interrupt identifier, and the corresponding relationship between the physical interrupt and the virtual interrupt identifier from the memory based on the base address, and determine that the received Which virtual CPU corresponds to the physical interrupt identifier, and determine the virtual interrupt identifier corresponding to the physical interrupt identifier; GIC can be implemented based on the arithmetic circuit in the chip of the ARM architecture, and the physical GIC
  • the hardware layer transparently transmits the virtual interrupt identifier to the target virtual processor, it does not need to be written into the system register corresponding to the virtual processor, and then the virtual processor obtains the virtual interrupt identifier in the system register when it is put into operation again. It is directly passed to the target virtual processor (specifically, the virtual interrupt identifier can be written to the interface interface corresponding to the virtual processor in the physical memory, and the virtual processor can obtain the virtual interrupt identifier based on the above interface), so the target virtual processing The processor does not need to exit, which reduces the delay caused by the exit of the virtual processor when the software implements virtual interrupt routing.
  • the virtual interrupt uniquely corresponds to the virtual interrupt identifier.
  • the computing device includes a hardware-based physical interrupt translation service ITS and a physical interrupt controller GIC;
  • the physical ITS is used to obtain a corresponding virtual interrupt identifier and a virtual processor identifier according to the physical interrupt identifier;
  • the physical GIC is used to transmit the virtual interrupt identifier to the target virtual processor.
  • the host machine is further configured to: acquire the physical interrupt identifier corresponding to the virtual interrupt according to the virtual interrupt and a preconfigured first mapping relationship; the first mapping relationship represents multiple virtual interrupts and the corresponding relationship between each virtual interrupt and physical interrupt identifiers; exemplarily, the first mapping relationship may include N virtual interrupts and N physical interrupt identifiers, wherein N virtual interrupts and N physical interrupt identifiers exist In a one-to-one correspondence, each virtual interrupt in the N virtual interrupts corresponds to a physical interrupt identifier, and each physical interrupt identifier in the N physical interrupt identifiers corresponds to a virtual interrupt.
  • the hardware layer is further configured to: obtain a virtual interrupt identifier corresponding to the physical interrupt according to the physical interrupt identifier and a preconfigured second mapping relationship; the second mapping relationship represents a plurality of physical interrupt identifiers and each physical interrupt identifier.
  • the first mapping relationship may include N physical interrupt identifiers and N virtual interrupt identifiers, wherein there is a one-to-one correspondence between the N physical interrupt identifiers and the N virtual interrupt identifiers, and each of the N physical interrupt identifiers has a one-to-one correspondence.
  • One physical interrupt identifier corresponds to one virtual interrupt identifier
  • each virtual interrupt identifier in the N virtual interrupt identifiers corresponds to one physical interrupt identifier.
  • the hardware layer is further configured to: obtain the corresponding virtual processor identifier according to the physical interrupt identifier and a preconfigured third mapping relationship; the third mapping relationship represents multiple physical interrupt identifiers and the corresponding relationship between each physical interrupt identifier and the virtual processor identifier.
  • the first mapping relationship may include N physical interrupt identifiers and N virtual processor identifiers, wherein each physical interrupt identifier in the N physical interrupt identifiers corresponds to a virtual processor identifier, and the N virtual processor identifiers Each virtual processor identifier in the identifiers corresponds to one or more physical interrupt identifiers.
  • a new mapping relationship needs to be preconfigured on the VMM side (hereinafter can be referred to as the first mapping relationship), and adaptively configure a new mapping relationship at the hardware layer (hereinafter referred to as the second mapping relationship and the third mapping relationship), the mapping relationship configured on the VMM side and the hardware
  • the mapping relationship of the layer configuration can be mutually configured, so that: the VMM side can convert the acquired virtual interrupt (including the virtual device identifier Device ID and the virtual interrupt vector identifier Vector ID) to the hardware layer side (such as the physical ITS based on the first mapping relationship).
  • identifiable physical interrupt identifier for example, including physical device identifier Device ID and physical interrupt vector identifier Vector ID
  • the hardware layer side can determine the virtual interrupt identifier corresponding to the physical interrupt identifier based on the preconfigured second mapping relationship, and based on The preconfigured third mapping relationship determines the virtual processor identifier corresponding to the physical interrupt identifier, and the virtual processor identifier uniquely corresponds to the target virtual processor.
  • the virtual interrupt identifier determined by the hardware layer based on the pre-configured second mapping relationship should be the virtual interrupt identifier corresponding to the virtual interrupt determined by the VMM in the virtual interrupt transfer implemented by software.
  • the interrupt identifier is consistent, and the virtual processor identifier determined by the hardware layer based on the preconfigured third mapping relationship should be consistent with the virtual processor identifier corresponding to the virtual interrupt determined by the VMM in the implementation of the virtual interrupt delivery through software. .
  • the hardware layer is further configured to: generate a physical interrupt according to the physical interrupt identifier
  • the host can transmit the interrupt generation request carrying the physical interrupt identifier to the physical ITS in the hardware layer, and the physical ITS can generate a corresponding interrupt generation request based on the interrupt generation request carrying the physical interrupt identifier. Physical interruption.
  • the host may write the physical interrupt identifier into a target register located at the hardware layer, so that the target register generates a physical interrupt.
  • the host can write the physical interrupt identifier into a target register located at the hardware layer.
  • the target register has the ability to generate physical interrupts in software, and the physical ITS can obtain physical interrupts from the target register.
  • the virtual interrupt includes a virtual device identifier and a virtual interrupt vector identifier
  • the host machine is further configured to: obtain, according to the virtual interrupt, a physical device identifier corresponding to the virtual device identifier, and a physical interrupt vector identifier corresponding to the virtual interrupt vector identifier; wherein the physical interrupt identifier includes the Physical device identification and the physical interrupt vector identification.
  • the hardware layer is further configured to: acquire interrupt status information corresponding to the physical interrupt identifier, where the interrupt status information is used to indicate whether the virtual interrupt identifier corresponding to the physical interrupt identifier can be is delivered to the virtual processor; specifically, the interrupt status information may include at least one of the following: interrupt pending status, interrupt priority, and interrupt enable status; determine the virtual interrupt based on the interrupt status information An identification can be passed to the virtual processor.
  • the interrupt pending information can indicate that the virtual interrupt is in a pending/active state
  • the interrupt priority state can indicate the priority of the current virtual interrupt among all pending virtual interrupts
  • the interrupt enable state can indicate whether the interrupt is It can be transmitted to the processor. Specifically, if the physical interrupt identifier is in the enabled state, and the priority state and the pending state satisfy the conditions, the virtual interrupt identifier corresponding to the physical interrupt identifier can be transmitted to the virtual processor.
  • the host is also used for:
  • the interrupt status information corresponding to the physical interrupt identifier is obtained from the hardware layer, where the interrupt status information is used to indicate whether the virtual interrupt identifier corresponding to the physical interrupt identifier can be transferred to the a virtual processor; the interrupt status information may include at least one of the following: interrupt pending status, interrupt priority, and interrupt enable status; write the interrupt status information into other computing devices other than the computing device in the hardware layer of the device.
  • the present application provides an interrupt processing method, the method is applied to a host computer, and the host computer runs on a host computer on the hardware layer, and the method includes:
  • the virtual interrupt is configured to interrupt a target virtual processor
  • the virtual interrupt and the physical interrupt identifier uniquely correspond to the virtual processor identifier
  • the virtual processor identifier is used to indicate the target virtual processor the processor, and transmits the virtual interrupt identifier to the target virtual processor.
  • the virtual interrupt uniquely corresponds to the virtual interrupt identifier.
  • obtaining the corresponding physical interrupt identifier according to the virtual interrupt includes:
  • a physical interrupt identifier corresponding to the virtual interrupt is acquired according to the virtual interrupt and a preconfigured first mapping relationship; the first mapping relationship represents a plurality of virtual interrupts and a corresponding relationship between each virtual interrupt and a physical interrupt identifier.
  • the virtual interrupt includes a virtual device identifier and a virtual interrupt vector identifier
  • the obtaining the corresponding physical interrupt identifier according to the virtual interrupt includes:
  • the method further includes:
  • the interrupt status information corresponding to the physical interrupt identifier is obtained from the hardware layer, where the interrupt status information is used to indicate whether the virtual interrupt identifier corresponding to the physical interrupt identifier can be transferred to the A virtual processor; wherein, the interrupt state information may include at least one of the following: interrupt pending state, interrupt priority, and interrupt enable state;
  • the interrupt status information is written into a hardware layer of a computing device other than the computing device.
  • the present application provides an interrupt processing method, the method is applied to a computing device, the computing device includes a hardware layer and a host running on the hardware layer, and the method includes:
  • the hardware layer acquires the corresponding virtual interrupt identifier and the virtual processor identifier according to the physical interrupt identifier; wherein, the physical interrupt identifier is the virtual interrupt acquired by the host machine according to the virtual interrupt and sent to the hardware layer.
  • the physical interrupt identifier corresponding to the interrupt the virtual interrupt is configured as an interrupt target virtual processor, the virtual interrupt and the physical interrupt identifier uniquely correspond to the virtual processor identifier, and the virtual processor identifier is used to indicate the the target virtual processor; and passing the virtual interrupt identifier to the target virtual processor.
  • the virtual interrupt uniquely corresponds to the virtual interrupt identifier.
  • the computing device includes a hardware-based physical interrupt translation service ITS and a physical interrupt controller GIC;
  • the hardware layer obtains the corresponding virtual interrupt identifier and virtual processor identifier according to the physical interrupt identifier, including:
  • the physical ITS obtains, according to the physical interrupt identifier, a corresponding virtual interrupt identifier and a virtual processor identifier;
  • the transmitting the virtual interrupt identifier to the target virtual processor includes:
  • the physical GIC communicates the virtual interrupt identifier to the target virtual processor.
  • the hardware layer acquiring the corresponding virtual interrupt identifier according to the physical interrupt identifier includes: the hardware layer acquiring the corresponding virtual interrupt identifier according to the physical interrupt identifier and a preconfigured second mapping relationship The virtual interrupt identifier corresponding to the physical interrupt; the second mapping relationship represents a plurality of physical interrupt identifiers and the corresponding relationship between each physical interrupt identifier and the virtual interrupt identifier.
  • the method further includes:
  • the third mapping relationship represents a plurality of physical interrupt identifiers and the correspondence between each physical interrupt identifier and the virtual processor identifier relation.
  • the hardware layer obtains the corresponding virtual interrupt identifier and the virtual processor identifier according to the physical interrupt identifier, including: the hardware layer generates a physical interrupt according to the physical interrupt identifier;
  • the method further includes:
  • the hardware layer acquires interrupt status information corresponding to the physical interrupt identifier, where the interrupt status information is used to indicate whether the virtual interrupt identifier corresponding to the physical interrupt identifier can be delivered to the virtual processor; based on the interrupt status The information determines that the virtual interrupt identification can be communicated to the virtual processor.
  • the method further includes: during the virtual machine hot migration process, the host acquires the interrupt status information corresponding to the physical interrupt identifier from the hardware layer, and the interrupt status information uses for indicating whether the virtual interrupt identifier corresponding to the physical interrupt identifier can be delivered to the virtual processor; and writing the interrupt status information into the hardware layer of other computing devices other than the computing device.
  • the present application provides an interrupt processing device, the device comprising:
  • a virtual interrupt processing unit configured to acquire a virtual interrupt; acquire a corresponding physical interrupt identifier according to the virtual interrupt, and transmit the physical interrupt identifier to the hardware layer;
  • a physical interrupt processing unit configured to obtain a corresponding virtual interrupt identifier and a virtual processor identifier according to the physical interrupt identifier; wherein the virtual interrupt is configured as an interrupt target virtual processor, the virtual interrupt and the physical interrupt
  • the identifier uniquely corresponds to the virtual processor identifier, and the virtual processor identifier is used to indicate the target virtual processor; and the virtual interrupt identifier is transmitted to the target virtual processor.
  • the interrupt processing apparatus can be applied to a computing device, and the computing device includes a hardware layer and a host computer running on the hardware layer; the interrupt processing apparatus includes a virtual interrupt processing device deployed in the host computer unit and a physical interrupt processing unit deployed in the hardware layer.
  • the virtual interrupt uniquely corresponds to the virtual interrupt identifier.
  • the computing device includes a hardware-based physical interrupt translation service ITS and a physical interrupt controller GIC;
  • the physical ITS is used to obtain a corresponding virtual interrupt identifier and a virtual processor identifier according to the physical interrupt identifier;
  • the physical GIC is used to transmit the virtual interrupt identifier to the target virtual processor.
  • the virtual interrupt processing unit is further configured to: obtain a physical interrupt identifier corresponding to the virtual interrupt according to the virtual interrupt and a preconfigured first mapping relationship; the first mapping relationship Represents multiple virtual interrupts and the corresponding relationship between each virtual interrupt and the physical interrupt identifier;
  • the physical interrupt processing unit is further configured to: obtain a virtual interrupt identifier corresponding to the physical interrupt according to the physical interrupt identifier and a preconfigured second mapping relationship; the second mapping relationship represents a plurality of physical interrupt identifiers and each physical interrupt identifier. The corresponding relationship between a physical interrupt identifier and a virtual interrupt identifier.
  • the physical interrupt processing unit is further configured to: obtain the corresponding virtual processor identifier according to the physical interrupt identifier and a preconfigured third mapping relationship; the third mapping relationship Indicates multiple physical interrupt identifiers and the corresponding relationship between each physical interrupt identifier and the virtual processor identifier.
  • the physical interrupt processing unit is further configured to: generate a physical interrupt according to the physical interrupt identifier;
  • the virtual interrupt includes a virtual device identifier and a virtual interrupt vector identifier
  • the virtual interrupt processing unit is further configured to: obtain, according to the virtual interrupt, a physical device identifier corresponding to the virtual device identifier, and a physical interrupt vector identifier corresponding to the virtual interrupt vector identifier; wherein the physical interrupt identifier includes the physical device identifier and the physical interrupt vector identifier.
  • the physical interrupt processing unit is further configured to: acquire interrupt status information corresponding to the physical interrupt identifier, where the interrupt status information is used to indicate whether the virtual interrupt identifier corresponding to the physical interrupt identifier is may be communicated to the virtual processor; determining the virtual interrupt identifier may be communicated to the virtual processor based on the interrupt status information.
  • the virtual interrupt processing unit is further configured to:
  • the interrupt status information corresponding to the physical interrupt identifier is obtained from the hardware layer, where the interrupt status information is used to indicate whether the virtual interrupt identifier corresponding to the physical interrupt identifier can be transferred to the A virtual processor; writing the interrupt status information into hardware layers of other computing devices other than the computing device.
  • an embodiment of the present application provides a computing device, where the computing device includes a processor and a memory connected through a bus, and the processor can call code in the memory to implement any one of the second aspect or the third aspect. interrupt handling method.
  • An embodiment of the present application provides a computing device, the computing device includes a hardware layer and a host computer running on the hardware layer; wherein, the host computer is used to obtain a virtual interrupt; according to the virtual interrupt, obtain a corresponding The physical interrupt identifier is transmitted to the hardware layer; the hardware layer is used to obtain the corresponding virtual interrupt identifier and virtual processor identifier according to the physical interrupt identifier; wherein, the virtual interrupt identifier is configured to interrupt the target virtual processor, the virtual interrupt and the physical interrupt identifier uniquely correspond to the virtual processor identifier, and the virtual processor identifier is used to indicate the target virtual processor; A virtual interrupt flag is passed to the target virtual processor.
  • the virtual interrupt acquired by the host is mapped to the physical interrupt of the physical layer, and the virtual interrupt identifier is transmitted to the virtual processor through the physical layer. Since the hardware layer transparently transmits the virtual interrupt identifier to the virtual processor, the virtual processor No exit is required, which reduces the delay caused by the exit of the virtual processor when the software implements virtual interrupt routing.
  • FIG. 1 is a schematic diagram of the architecture of a computing node provided by an embodiment of the present application
  • Figure 2a is a computing device according to an embodiment of the present invention.
  • FIG. 2b is a schematic diagram of interrupt processing according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of interrupt processing according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of interrupt processing according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of interrupt processing according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of interrupt processing according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of interrupt processing according to an embodiment of the present invention.
  • FIG. 8 is a schematic diagram of an interrupt processing apparatus according to an embodiment of the present invention.
  • FIG. 9 is a schematic diagram of a computing device according to an embodiment of the present invention.
  • plural means two or more.
  • the term “and/or” or the character “/” in this application is only an association relationship to describe associated objects, indicating that there can be three relationships, for example, A and/or B, or A/B, which can indicate: There are three cases where A exists alone, A and B exist at the same time, and B exists alone.
  • the computing node 100 may be a computing device in this embodiment of the present application.
  • Virtualization is to virtualize hardware resources (such as processors, storage space in memory, and network resources) in the hardware layer of a computing node and share them for use by multiple virtual computers.
  • a virtual computer is a general term for a running environment virtualized by software in all types of computing devices, and the concept includes virtual machines and containers.
  • the computing node 100 may include a hardware layer, a host layer and a virtualization layer, and the virtualization layer includes two virtual machines.
  • the hardware layer includes hardware such as two processors 110 , a memory 120 , and a physical interrupt management unit 160 .
  • the number of processors 110 and the number of virtual machines may be more or less.
  • Virtual machine One or more virtual computers simulated by software on a physical computer. These virtual machines run in a completely isolated environment and work like real computers.
  • a guest operating system can be installed on the virtual machine, and one or more applications run on the guest operating system.
  • Virtual machines can also access network resources. For applications running in a virtual machine, it is like working on a real computer.
  • Virtual processor under the virtualization technology, a representation of a physical processing unit provided to a virtual computer in a shared or sharded manner, such as a virtual CPU (virtual central processing unit, vCPU).
  • a virtual computer can be served by one or more virtual processors. When there are multiple virtual processors, usually one virtual processor is the master virtual processor, and the others are slave virtual processors.
  • a host operating system 170 and a VMM 180 are deployed in the host, and the VMM 180 is equivalent to a hypervisor or other types of virtual monitoring devices in other virtualization architectures.
  • the VMM 180 can be deployed inside the host operating system 170, or can be deployed separately from the host operating system 170.
  • VMM 180 is responsible for managing one or more virtual machines running on it.
  • a virtual machine includes a virtual hardware layer, a guest operating system 190, and various applications.
  • the virtual hardware layer includes virtual hardware such as virtual memory (not shown in the figure), virtual processor 110-v, and the like.
  • FIG. 1 this embodiment includes two virtual machines, and each virtual machine includes three virtual processors 110-v.
  • the virtual processor 110-v is realized by a combination of software and hardware, and its operation is actually realized by the physical core reading and running the software program. For example, a physical core reads the software program and implements a specific mode of hardware-assisted virtualization of the physical core.
  • the software program is run under the hood to implement a virtual processor 110-v. Therefore, the virtual processor 110-v needs to be scheduled on a certain physical core.
  • the virtual processor 110-v and the physical core may be in a bound relationship, that is, a virtual processor 110-v is fixed to run on a certain physical core and cannot be scheduled to run on other physical cores, then the virtual processor is bound. core; a virtual processor 110-v can be scheduled to run on different physical cores as required, and the virtual processor is a non-core bound.
  • the total number of virtual processors 110-v shown in FIG. 1 is 6, which is greater than the number of physical cores, 4.
  • This scenario is called physical processor over-allocation.
  • physical processor over-allocation there will be multiple virtual processors sharing the same physical core in a time-slicing manner or in other ways.
  • This physical core is called an inclusive core. Of course, in the case of non-over-allocation, inclusive cores may also occur. If a physical core is bound to a virtual processor and is not shared by other virtual processors, the physical core is an exclusive core.
  • a virtual machine is equivalent to an independent computer, so an action performed by a virtual machine can also be considered as a virtual processor performing the action, and the virtual processor is implemented by software, so the virtual processor’s execution action is actually a virtual processor.
  • the running physical processor or physical core performs the action.
  • a virtual machine can contain containers, which are equivalent to applications.
  • the virtualization layer is implemented by a lightweight virtualization technology, such as libOS190.
  • a libOS usually contains an application, the whole libOS is one or more libraries, and the application is linked into a single address space image.
  • the embodiment of the present application generally takes a virtual machine implemented by a traditional virtualization technology as an example, and other types of virtualization architectures may refer to the implementation of the virtual machine.
  • Host As a management layer, it is used to complete the management and allocation of hardware resources; present a virtual hardware platform for virtual machines; realize scheduling and isolation of virtual machines, etc.
  • the host layer includes a host operating system and a virtual monitoring device, such as a virtual machine monitor (VMM) or a hypervisor, wherein the virtual monitoring device can be deployed within the host operating system, or can be Deployed outside the host operating system.
  • the "host layer” may further include a privileged virtual machine (eg, a virtualization architecture Xen).
  • the virtual hardware platform provides various hardware resources, such as virtual processors, virtual memory, virtual disks, and virtual network cards, to each virtual computer running on it. A virtual computer runs on a virtual hardware platform prepared for it by the host layer.
  • the host layer is sometimes simply referred to as the host.
  • the host can also include back-end drivers (such as open source software such as QEMU) to simulate a virtual disk with a cache to the virtual machine, including parsing the cache configuration and cache policy set by the user, such as cache size, cache type and cache priority, etc. , simulates a virtual disk with virtual machine cache that conforms to the user's configuration, provides the simulation of the first physical address required by the front-end driver, and is responsible for management operations involving modifying cache attributes in virtualization management, such as initiating online cache expansion. , capacity reduction and other tasks.
  • the back-end driver can capture the virtual interrupt-enabled behavior of the virtual machine, trigger the corresponding virtual interrupt, and deliver the virtual interrupt to the VMM.
  • the QEMU included in the host shown in FIG. 1 is only an illustration, and in practical applications, the host may also include other types of back-end drivers.
  • the VMM 180 is responsible for scheduling the virtual processors 110-v of each virtual machine VM.
  • a kernel-based virtual machine KVM is a typical VMM.
  • the virtual interrupt management unit 181 is deployed at the host layer.
  • the virtual interrupt management unit 181 may be deployed in the host operating system 170, may also be deployed in the VMM 180, or may be partially deployed in the host operating system 170, and may be partially deployed in the host operating system 170. Deployed within VMM 180.
  • the virtual interrupt management unit 181 may be deployed within the VMM 180, may also be deployed within the host operating system 170 other than the VMM 180, or may be partially deployed within the VMM 180 , partially deployed inside the host operating system 170 other than the VMM 180.
  • the virtual interrupt processing unit 181 may implement the steps related to the host in the interrupt processing method in the embodiment of the present application.
  • Hardware layer The hardware platform on which the virtualized environment runs.
  • the hardware layer may include a variety of hardware, for example, the hardware layer of a physical computer may include a processor and a memory, and may also include an interrupt controller, a network interface card (NIC), an input/output (I/O) ) equipment, etc.
  • NIC network interface card
  • I/O input/output
  • the processor 110 may also be referred to as a physical processor.
  • the physical core represents the smallest processing unit in the processor. As shown in FIG. 1 , in this embodiment, the processor may have two physical cores: core 0 and core 1, and multiple registers. In some other embodiments, the number of cores included in the processor may be more or less, and the number of cores included in each processor may also be different.
  • a processor with multiple physical cores is called a multi-core processor. According to whether the kernel architecture is the same, it can be divided into homogeneous multi-core and heterogeneous multi-core.
  • a virtual processor and a physical core can be in a bound relationship, that is, a virtual processor is fixed to run on a certain physical core and cannot be scheduled to run on other physical cores, then the virtual processor is a bound core; a virtual processor If it can be scheduled to run on different physical cores as required, the virtual processor is a non-core bound.
  • the physical interrupt management unit 160 is responsible for collecting physical interrupt requests (also referred to as physical interrupts), and sending these physical interrupt requests to each processor 110 according to certain rules or to a virtual processor on the processor transparently. It should be noted that the physical interrupt management unit 160 may execute some steps related to the hardware layer of the interrupt processing method in this application.
  • an interrupt refers to an event generated by software or hardware.
  • Interrupts include virtual interrupts and physical interrupts.
  • a physical interrupt is an event generated by hardware.
  • the hardware sends the event to the processor.
  • the processor receives the event, it temporarily stops the execution of the current program and executes the program corresponding to the event.
  • the interrupt request generated by the hardware may be triggered by the hardware itself, or it may be generated by the software triggered by the hardware.
  • Some hardware in the computer (such as network card, sound card, mouse, hard disk, etc.) can complete certain work without the intervention of the processor, but these hardware still need to interrupt the processor periodically to let the processor do some specific tasks for it. Work.
  • the VMM needs to present a virtual interrupt architecture similar to the physical interrupt architecture for the virtual machine.
  • the virtual interrupt also called virtualized interrupt
  • Interrupts can be enabled by front-end drivers in the virtual machine and caught and triggered by back-end drivers in the host (eg QEMU).
  • Interrupt controller It is set between the hardware that triggers the interrupt request and the processor. It is mainly used to collect interrupts generated by each hardware and send them to the processor according to a certain priority or other rules.
  • Interrupt affinity refers to the correspondence between an interrupt and a processing subject (which may be a physical processing subject or a virtual processing subject, such as a physical core) that processes the interrupt request.
  • the interrupt controller may send an interrupt request to one or more physical processing bodies corresponding to the interrupt request according to the interrupt affinity.
  • Figure 2a shows a computing device according to an embodiment of the present invention.
  • the computing device includes a host 200 and a hardware layer 203.
  • the virtual device in the virtual machine can enable virtual interrupts, and the virtual device can be a virtual device simulated by software, such as a serial port simulated by software, etc.; the back-end driver (such as QEMU) in the host can capture the virtual interrupt
  • the virtual interrupt is enabled by the virtual machine, and the virtual interrupt is triggered.
  • the virtual interrupt may include the virtual device ID Device ID and the virtual interrupt vector ID Vector ID.
  • each virtual processor uniquely corresponds to a virtual device ID Device ID and multiple virtual interrupt vector ID Vector IDs; the virtual device ID Device ID in the virtual interrupt can indicate that the virtual interrupt is Which virtual device is enabled, the virtual interrupt vector identifier Vector ID can indicate which virtual interrupt is specifically among the multiple virtual interrupts allocated by the virtual device.
  • the virtual interrupt can be delivered to the VMM, and correspondingly, the VMM in the host 200 can obtain the virtual interrupt.
  • the VMM in the host may acquire a virtual interrupt, acquire a corresponding physical interrupt identifier according to the virtual interrupt, and transmit the physical interrupt identifier to the hardware layer 203.
  • the VMM in the host may acquire a virtual interrupt, acquire a corresponding physical interrupt identifier according to the virtual interrupt, and transmit the physical interrupt identifier to the hardware layer 203.
  • the virtual interrupt in order to transparently transmit the virtual interrupt acquired by the VMM to the corresponding virtual processor through the hardware layer, the virtual interrupt needs to be converted into a physical interrupt that the hardware layer can recognize and process.
  • the hardware layer may include a physical interrupt translation service (interrupt translation service, ITS) and a physical interrupt controller (generic interrupt controller, GIC), where the physical ITS may acquire a physical interrupt, and the physical interrupt is used to interrupt the virtual CPU,
  • the physical ITS can determine which virtual CPU the physical interrupt corresponds to, and determine the virtual interrupt identifier corresponding to the physical interrupt (which can indicate which virtual interrupt is specific); the physical GIC can send the virtual interrupt identifier to the virtual CPU.
  • VMM converts virtual interrupts into physical interrupts that the hardware layer can recognize and process, and can ensure that the virtual processor can receive the correct virtual interrupt identifier:
  • the VMM From the perspective of the virtual interrupt delivery process implemented by software, after the VMM obtains the virtual interrupt (including the virtual device ID Device ID and the virtual interrupt vector ID Vector ID), it can determine the virtual interrupt ID and virtual processing corresponding to the virtual interrupt based on the software ITS.
  • the virtual interrupt identifier here can be different from the above-mentioned virtual device identifier Device ID and virtual interrupt vector identifier Vector ID.
  • the virtual interrupt identifier is vINTID; virtual processor The ID uniquely indicates the target virtual processor.
  • a new mapping relationship needs to be preconfigured on the VMM side (hereinafter can be referred to as the first mapping relationship), and adaptively configure a new mapping relationship at the hardware layer (hereinafter referred to as the second mapping relationship and the third mapping relationship), the mapping relationship configured on the VMM side and the hardware
  • the mapping relationship of the layer configuration can be mutually configured, so that: the VMM side can convert the acquired virtual interrupt (including the virtual device identifier Device ID and the virtual interrupt vector identifier Vector ID) to the hardware layer side (such as the physical ITS based on the first mapping relationship).
  • identifiable physical interrupt identifier for example, including physical device identifier Device ID and physical interrupt vector identifier Vector ID
  • the hardware layer side can determine the virtual interrupt identifier corresponding to the physical interrupt identifier based on the preconfigured second mapping relationship, and based on The preconfigured third mapping relationship determines the virtual processor identifier corresponding to the physical interrupt identifier, and the virtual processor identifier uniquely corresponds to the target virtual processor.
  • the virtual interrupt identifier determined by the hardware layer based on the pre-configured second mapping relationship should be the virtual interrupt identifier corresponding to the virtual interrupt determined by the VMM in the virtual interrupt transfer implemented by software.
  • the interrupt identifier is consistent, and the virtual processor identifier determined by the hardware layer based on the preconfigured third mapping relationship should be consistent with the virtual processor identifier corresponding to the virtual interrupt determined by the VMM in the implementation of the virtual interrupt delivery through software. .
  • VMM can determine B (virtual interrupt identifier) and C (virtual processor identifier) from A (virtual interrupt), and then transparently transmit the virtual interrupt acquired by VMM to the hardware layer through the hardware layer.
  • the VMM can determine D (physical interrupt identifier) from A (virtual interrupt)
  • the physical layer can determine B (virtual interrupt identifier) and C (virtual processor identifier) from D (physical interrupt identifier). identification).
  • an abstraction of a corresponding physical device can be configured for each virtual device in advance.
  • the reason why it is called the abstraction of a physical device is that the physical device may not actually exist.
  • the interrupt resource may include a physical interrupt identifier.
  • the VMM may pre-store the interrupt resource corresponding to each virtual interrupt among the multiple virtual interrupts corresponding to the virtual device. Physical interrupt identifier.
  • the virtual interrupt can include the virtual device identifier Device ID and the virtual interrupt vector identifier Vector ID, then the VMM can obtain the physical device identifier Device ID corresponding to the virtual device identifier Device ID, and the virtual interrupt vector identifier The physical interrupt corresponding to the Vector ID is obtained.
  • Vector ID Vector ID the virtual interrupt vector ID.
  • the VMM may maintain a preconfigured first mapping relationship
  • the first mapping relationship may include a mapping relationship between virtual interrupts and physical interrupt identifiers
  • the VMM may obtain the corresponding virtual interrupt through the first mapping relationship.
  • Physical interrupt identifier More specifically, the first mapping relationship may include two tables (Table 1 and Table 2), wherein Table 1 includes a plurality of virtual device identifiers Device ID, and a pointer corresponding to each virtual device identifier Device ID, and the VMM can pass the pointer.
  • the table 2 can include multiple virtual interrupt vector identifiers Vector ID corresponding to the virtual device identifier Device ID, and the physical interrupt vector identifier Vector corresponding to each virtual interrupt vector identifier Vector ID ID.
  • the VMM can determine the physical interrupt identifier corresponding to the virtual interrupt.
  • the host can transmit the physical interrupt identifier to the hardware layer. Specifically, the host can transmit the physical interrupt identifier to the physical ITS in the hardware layer.
  • the physical ITS in the hardware layer can obtain the corresponding virtual interrupt identifier and virtual processor identifier according to the physical interrupt identifier; wherein, the virtual interrupt identifier is used to uniquely indicate the virtual interrupt, and the virtual processor identifier is used for Indicates the target virtual processor; the physical GIC in the hardware layer can transmit the virtual interrupt identifier to the target virtual processor corresponding to the virtual processor identifier.
  • the hardware layer may further generate a physical interrupt according to the physical interrupt identifier.
  • the host computer may also transmit an interrupt generation request carrying the physical interrupt identifier to the hardware layer, and the hardware layer may generate a physical interrupt according to the interrupt generation request.
  • the host can transmit the interrupt generation request carrying the physical interrupt identifier to the physical ITS in the hardware layer, and the physical ITS can generate a corresponding interrupt generation request based on the interrupt generation request carrying the physical interrupt identifier. Physical interruption.
  • the host may write the physical interrupt identifier into a target register located at the hardware layer, so that the target register generates a physical interrupt.
  • the host can write the physical interrupt identifier into a target register located at the hardware layer.
  • the target register has the ability to generate physical interrupts in software, and the physical ITS can obtain physical interrupts from the target register.
  • the hardware layer may acquire the corresponding virtual interrupt identifier according to the physical interrupt identifier and the preconfigured second mapping relationship.
  • the physical ITS in the hardware layer may maintain a preconfigured mapping relationship, and the mapping relationship may include a mapping relationship between physical interrupt identifiers, virtual interrupt identifiers, and virtual processors.
  • the hardware layer may maintain a second mapping relationship, where the second mapping relationship includes a mapping relationship between a physical interrupt identifier and a virtual interrupt identifier, and the hardware layer may obtain a virtual interrupt identifier corresponding to the physical interrupt identifier through the second mapping relationship.
  • the hardware layer can maintain a third mapping relationship, and the third mapping relationship includes the mapping relationship between the physical interrupt identifier and the virtual processor identifier.
  • the hardware layer can obtain the virtual processor identifier corresponding to the physical interrupt identifier through the third mapping relationship.
  • the processor ID is used to indicate the target virtual processor.
  • the second mapping relationship and the third mapping relationship may be set at the hardware layer during the pre-configuration process, and the hardware layer may determine the physical data obtained from the VMM through the second mapping relationship and the third mapping relationship.
  • the virtual processor corresponding to the interrupt identifier is determined, and the virtual interrupt identifier corresponding to the physical interrupt identifier is determined.
  • the virtual interrupt identifier (eg vINTID) can uniquely indicate the virtual interrupt, and the hardware layer can transmit the virtual interrupt identifier to the target virtual processor.
  • the virtual interrupt is used to interrupt the corresponding target virtual processor.
  • the mapping relationship can cooperate with each other, so that the target virtual processor determined by the final hardware layer is the corresponding target virtual processor used by the virtual interrupt for interrupting.
  • the virtual interrupt identifier obtained by the hardware layer by mapping the physical interrupt identifier needs to uniquely indicate the virtual interrupt.
  • the target The virtual processor is equivalent to receiving the correct virtual interrupt identifier. Compared with the existing way of implementing virtual interrupt routing through VMM software, the above method is consistent from the point of view of the virtual processor.
  • the routing table of the physical ITS (the second mapping relationship and the third mapping relationship in the above embodiment) is defined in the GICv4 specification, and an additional channel is opened for the virtual interrupt at the hardware layer.
  • This channel The virtual interrupt can be transparently transmitted from the hardware layer to the target virtual processor.
  • the hardware layer transparently transmits the virtual interrupt identifier to the target virtual processor, it does not need to be written into the system register corresponding to the virtual processor, and then the virtual processor obtains the virtual interrupt identifier in the system register when it is put into operation again. It is directly passed to the target virtual processor, so the virtual processor does not need to exit, which reduces the delay caused by the exit of the virtual processor when the software implements virtual interrupt routing.
  • the hardware layer is further configured to: acquire interrupt status information corresponding to the physical interrupt identifier, where the interrupt status information is used to indicate whether the virtual interrupt identifier corresponding to the physical interrupt identifier can be transmitted to the The virtual processor; wherein, the interrupt status information may include at least one of the following: interrupt pending information, interrupt priority status, and interrupt enable status; it is determined based on the interrupt status information that the virtual interrupt identifier can be passed to the virtual processor.
  • the interrupt pending information can indicate that the virtual interrupt is in a pending/active state
  • the interrupt priority state can indicate the priority of the current virtual interrupt among all pending virtual interrupts
  • the interrupt enable state can indicate whether the interrupt is It can be transmitted to the processor. Specifically, if the physical interrupt identifier is in the enabled state, and the priority state and the pending state satisfy the conditions, the virtual interrupt identifier corresponding to the physical interrupt identifier can be transmitted to the virtual processor.
  • the physical interrupt controller in the hardware layer may acquire interrupt status information corresponding to the physical interrupt identifier, where the interrupt status information is used to indicate whether the virtual interrupt identifier corresponding to the physical interrupt identifier can be transmitted to
  • the interrupt status information includes at least one of the following: interrupt pending information, interrupt priority status, and interrupt enable status; it is determined based on the interrupt status information that the virtual interrupt identifier can be transmitted to the virtual processor.
  • An embodiment of the present application provides a computing device, the computing device includes a hardware layer and a host computer running on the hardware layer; wherein, the host computer is used to obtain a virtual interrupt; according to the virtual interrupt, obtain a corresponding The physical interrupt identifier is transmitted to the hardware layer; the hardware layer is used to obtain the corresponding virtual interrupt identifier and virtual processor identifier according to the physical interrupt identifier; wherein, the virtual interrupt identifier is configured to interrupt the target virtual processor, the virtual interrupt and the physical interrupt identifier uniquely correspond to the virtual processor identifier, and the virtual processor identifier is used to indicate the target virtual processor; A virtual interrupt flag is passed to the target virtual processor.
  • the virtual interrupt acquired by the host is mapped to the physical interrupt of the physical layer, and the virtual interrupt identifier is transmitted to the virtual processor through the physical layer. Since the hardware layer transparently transmits the virtual interrupt identifier to the virtual processor, the virtual processor No exit is required, which reduces the delay caused by the exit of the virtual processor when the software implements virtual interrupt routing.
  • Figure 3 shows a more specific embodiment, as shown in Figure 3, the VMM may include a shadow map 2021, a shadow device 2022, and the interrupt system may include a shadow interrupt domain 2023, wherein the shadow map 2021 and the shadow device 2022 may An abstraction that provides a "shadow object" for each virtual device of the virtual machine.
  • the front-end driver eg VirtIO driver
  • the shadow map 2021 and the shadow device 2022 are responsible for linking each virtual interrupt of the virtual device to a physical interrupt on the host.
  • VMM can intercept these operations, and configure the interrupt information of the virtual machine (for example, including the information related to the above-mentioned front-end driver enabling virtual interrupts, adjusting virtual interrupt routing related information, Modify the information related to the virtual interrupt configuration, etc.) and synchronize to the corresponding shadow map 2021 and shadow device 2022.
  • the shadow map 2021 may include key information of virtual device registration, such as the device ID of the virtual device, the ID of the virtual interrupt vector, the upper limit of the number of virtual interrupts that the virtual processor can handle, etc., and the virtual routing information of the virtual interrupt of the device , such as the virtual interrupt identifier, the virtual processor corresponding to each virtual interrupt, and so on.
  • the shadow device 2022 can apply for physical interrupt resources such as a physical interrupt identifier on the host for each virtual device.
  • the shadow interrupt field 2023 may pass the physical interrupt identification to the physical ITS of the physical layer.
  • the physical ITS of the hardware layer may include a physical interrupt routing table 2041, and the hardware layer may include a physical interrupt controller 2042, wherein the physical interrupt routing table 2041 may be a preconfigured mapping relationship, the mapping relationship It may include physical interrupt identifiers, virtual interrupt identifiers, and mapping relationships between virtual processors.
  • the hardware layer may maintain a second mapping relationship, and the second mapping relationship may be a part of the above-mentioned physical interrupt routing table 2041.
  • the second mapping relationship includes the mapping relationship between the physical interrupt identifier and the virtual interrupt identifier.
  • the second mapping relationship obtains the virtual interrupt identifier corresponding to the physical interrupt identifier.
  • the hardware layer may maintain a third mapping relationship, and the third mapping relationship may be a part of the above-mentioned physical interrupt routing table 2041.
  • the third mapping relationship may include the mapping relationship between the physical interrupt identifier and the virtual processor, and the hardware layer may pass the third mapping relationship. The relationship obtains the virtual processor corresponding to the physical interrupt identifier.
  • the physical interrupt controller 2042 may obtain the interrupt status information corresponding to the physical interrupt identifier according to the correspondence between the physical interrupt identifier and the interrupt status information, and determine based on the interrupt status information that the virtual interrupt identifier can be transferred to the virtual processing device.
  • FIG. 4 shows more details than FIG. 3.
  • the VMM can write the physical interrupt identification to a target register 2043 located at the hardware layer, so that the target register 2043 generates a physical interrupt.
  • the target register has a physical interrupt that can be generated by software, and the ITS can obtain the physical interrupt from the target register.
  • the VMM and the hardware layer need to be preconfigured.
  • the virtual VirtIO device driver inside the virtual machine is loaded and initialized, and the related operations are intercepted by the VMM to establish a software routing table for virtual interrupts.
  • the virtual VirtIO device driver inside the virtual machine enables the virtual device capability by writing to the peripheral component interconnect (PCI) configuration space, and this write operation is intercepted by the VMM.
  • the VMM can register the key information of the virtual device (the device number of the virtual device, the virtual interrupt vector information, the upper limit of the number of virtual interrupts that the virtual processor can handle, etc.) to the VMM according to the protocol.
  • VMM creates a shadow object for a registered virtual device, creates a shadow device with the help of the registered virtual device information, and applies to occupy the physical host device number and physical interrupt number resources accordingly.
  • the requested physical interrupt number resource is registered in the shadow interrupt domain for management.
  • the VMM can parse the routing information of each virtual interrupt of the virtual device through the registered virtual device, including information such as the target virtual interrupt routing device, the virtual interrupt number, and the target virtual processor.
  • the shadow object parses the virtual interrupt routing relationship, translates and constructs the physical interrupt routing device format, uses the shadow device to correspond to the physical interrupt, and establishes the physical device interrupt routing table corresponding to the physical interrupt of the virtual device through the shadow interrupt domain management.
  • the VMM parses the routing information of each virtual interrupt of the virtual device through the registered virtual device, including information such as the target virtual interrupt routing device, the virtual interrupt number, and the target virtual processor.
  • the configuration of other attributes of virtual interrupts is translated with the help of shadow objects, and managed through the shadow interrupt domain, to configure/modify the shadow device interrupt configuration table.
  • the host machine may also acquire interrupt status information corresponding to the physical interrupt identifier from the hardware layer during the virtual machine hot migration process, where the interrupt status information includes at least one of the following Types: interrupt pending information, interrupt priority state, interrupt enable state; write the interrupt state information into hardware layers of other computing devices other than the computing device.
  • FIG. 5 is an example of a computing device in an embodiment of the application. As shown in FIG.
  • the interrupt status information can be stored in an area 501 accessible to both the hardware layer and the VMM, then the hardware layer
  • the physical interrupt processing unit 204 in can obtain the interrupt status information, and determine whether the virtual interrupt identifier should be transmitted to the corresponding virtual processor based on the interrupt status information, and in the virtual machine hot migration process, the VMM 201 can also be transferred from the hardware
  • the layer acquires interrupt status information corresponding to the physical interrupt identifier, and writes the interrupt status information into hardware layers of other computing devices other than the computing device.
  • the computing device provided by the embodiment of the present application is described below with reference to FIG. 6 .
  • the computing device provided by the embodiment of the present application includes a virtual machine, a host machine, and a hardware layer; wherein, the virtual device in the virtual machine
  • the interrupt can be triggered, and the corresponding front-end driver will enable virtual interrupt.
  • the back-end driver in the host can capture the behavior of the front-end driver to enable virtual interrupt and trigger the virtual interrupt.
  • the IRQFD subsystem can receive the virtual interrupt triggered by the back-end driver.
  • the shadow device module can determine the physical interrupt identifier of the virtual interrupt, and the shadow interrupt domain transfers the physical interrupt identifier to the physical ITS of the hardware layer through the physical ITS driver, and the physical ITS can determine The physical interrupt identifier corresponds to the virtual interrupt identifier and the target virtual processor, and the physical GIC transmits the virtual interrupt identifier to the target virtual processor VCPU.
  • the computing device provided by the embodiment of the present application is described below with reference to FIG. 7 . As shown in FIG.
  • the computing device provided by the embodiment of the present application includes a virtual machine, a host machine, and a hardware layer; wherein, in order to ensure the interruption of software and hardware State consistency, the virtual GIC in the VMM needs to obtain the interrupt status information in the physical GIC, and update the interrupt status information of the corresponding virtual interrupt; specifically, as shown in Figure 7, the back-end driver can trigger the status Synchronization request.
  • the request carries the information related to the virtual interrupt that needs to be synchronized.
  • the shadow map and shadow object can decode the virtual interrupt information of the virtual device, convert it into the corresponding physical interrupt identifier, and send it to the shadow interrupt domain.
  • the interrupt field transmits the physical interrupt identifier to the physical ITS of the physical layer, and the physical GIC can transmit the interrupt status information related to the physical interrupt identifier to the table (such as the pending table) that saves the interrupt status information in the host, and then the state synchronization system can
  • the interrupt status information related to the physical interrupt identification is passed to the virtual GIC, so that the virtual GIC updates the interrupt status information of the virtual interrupt.
  • FIG. 8 is a schematic structural diagram of an interrupt processing apparatus 800 provided by an embodiment of the present application.
  • the computing device includes a hardware layer and a host computer running on the hardware layer; the interrupt processing apparatus includes a The virtual interrupt processing unit 801 in the host and the physical interrupt processing unit 802 deployed in the hardware layer; wherein,
  • the virtual interrupt processing unit 801 is configured to acquire a virtual interrupt; acquire a corresponding physical interrupt identifier according to the virtual interrupt, and transmit the physical interrupt identifier to the hardware layer;
  • the physical interrupt processing unit 802 is configured to obtain a corresponding virtual interrupt identifier and a virtual processor identifier according to the physical interrupt identifier; wherein the virtual interrupt is configured as an interrupt target virtual processor, and the virtual interrupt and the virtual processor The physical interrupt identifier uniquely corresponds to the virtual processor identifier, and the virtual processor identifier is used to indicate the target virtual processor; and,
  • the virtual interrupt identifier is passed to the target virtual processor.
  • the virtual interrupt processing unit 801 may be equivalent to the virtual interrupt management unit 181 shown in FIG. 1 , the virtual interrupt processing unit 202 shown in FIGS. 2 a and 2 b , and the shadow mapping and shadow mapping shown in FIGS. 3 to 7 . Device and shadow interrupt domains.
  • the physical interrupt processing unit 801 may be equivalent to the physical interrupt management unit 160 shown in FIG. 1 , the physical interrupt processing unit 204 shown in FIGS. 2 a and 2 b , and the physical ITS and physical interrupt shown in FIGS. 3 to 7 .
  • Interrupt Controller GIC Interrupt Controller
  • the virtual interrupt uniquely corresponds to the virtual interrupt identifier.
  • the computing device includes a hardware-based physical interrupt translation service ITS and a physical interrupt controller GIC;
  • the physical ITS is used to obtain a corresponding virtual interrupt identifier and a virtual processor identifier according to the physical interrupt identifier;
  • the physical GIC is used to transmit the virtual interrupt identifier to the target virtual processor.
  • the virtual interrupt processing unit 801 is further configured to: obtain a physical interrupt identifier corresponding to the virtual interrupt according to the virtual interrupt and a preconfigured first mapping relationship; the first mapping The relationship represents multiple virtual interrupts and the corresponding relationship between each virtual interrupt and the physical interrupt identifier;
  • the physical interrupt processing unit 802 is further configured to: obtain a virtual interrupt identifier corresponding to the physical interrupt according to the physical interrupt identifier and a preconfigured second mapping relationship; the second mapping relationship represents multiple physical interrupt identifiers and The corresponding relationship between each physical interrupt identifier and the virtual interrupt identifier.
  • the physical interrupt processing unit 802 is further configured to: obtain the corresponding virtual processor identifier according to the physical interrupt identifier and a preconfigured third mapping relationship; the third mapping The relationship represents a plurality of physical interrupt identifiers and the corresponding relationship between each physical interrupt identifier and the virtual processor identifier.
  • the physical interrupt processing unit 802 is further configured to: generate a physical interrupt according to the physical interrupt identifier;
  • the virtual interrupt includes a virtual device identifier and a virtual interrupt vector identifier
  • the virtual interrupt processing unit 801 is further configured to: obtain, according to the virtual interrupt, a physical device identifier corresponding to the virtual device identifier, and a physical interrupt vector identifier corresponding to the virtual interrupt vector identifier; wherein, the physical interrupt identifier Including the physical device identifier and the physical interrupt vector identifier.
  • the physical interrupt processing unit 802 is further configured to: acquire interrupt status information corresponding to the physical interrupt identifier, where the interrupt status information is used to indicate a virtual interrupt identifier corresponding to the physical interrupt identifier Whether it can be transmitted to the virtual processor, the interrupt status information includes at least one of the following: interrupt pending status, interrupt priority, interrupt enable status; determine the virtual interrupt identifier based on the interrupt status information can be passed to the virtual processor.
  • the virtual interrupt processing unit 801 is further configured to:
  • the interrupt status information corresponding to the physical interrupt identifier is obtained from the hardware layer, where the interrupt status information is used to indicate whether the virtual interrupt identifier corresponding to the physical interrupt identifier can be transferred to the a virtual processor; the interrupt status information includes at least one of the following: interrupt pending status, interrupt priority, and interrupt enable status; write the interrupt status information into other computing devices other than the computing device in the hardware layer.
  • the present application also provides a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium contains computer instructions for executing an interrupt processing method, the method is applied in a host computer, the host computer The host is located at a computing device, the computing device includes a hardware layer, and the non-volatile computer-readable storage medium includes first computer instructions for obtaining a virtual interrupt;
  • the non-volatile computer-readable storage medium includes second computer instructions for obtaining a corresponding physical interrupt identifier according to the virtual interrupt, and transmitting the physical interrupt identifier to the hardware layer.
  • the first computer instruction is used to obtain the corresponding physical interrupt identifier according to the virtual interrupt and the preconfigured first mapping relationship.
  • the virtual interrupt includes a virtual device identifier and a virtual interrupt vector identifier
  • the first computer instruction is used to obtain, according to the virtual interrupt, a physical device identifier corresponding to the virtual device identifier, and a physical interrupt vector identifier corresponding to the virtual interrupt vector identifier; wherein, the physical interrupt identifier includes the physical interrupt identifier.
  • Device identification and the physical interrupt vector identification are used to obtain, according to the virtual interrupt, a physical device identifier corresponding to the virtual device identifier, and a physical interrupt vector identifier corresponding to the virtual interrupt vector identifier; wherein, the physical interrupt identifier includes the physical interrupt identifier.
  • the non-volatile computer-readable storage medium further includes third computer instructions for acquiring, from the hardware layer, interrupt status information corresponding to the physical interrupt identifier during a virtual machine live migration process , the interrupt status information includes at least one of the following: pending information, priority information, and enable information; and the interrupt status information is written into hardware layers of other computing devices other than the computing device.
  • the present application also provides a non-volatile computer-readable storage medium, where the non-volatile computer-readable storage medium contains computer instructions, and when the computer instructions are executed by a computer, the interrupt processing method in the above embodiment can be implemented.
  • FIG. 9 is a schematic diagram of a computing device 900 provided by an embodiment of the application.
  • the computing device 900 includes a processor 901 and a memory 902 connected through a bus, and the processor 901 can call
  • the code in the memory 902 implements the interrupt processing method in the above-mentioned embodiment.
  • the disclosed system, apparatus and method may be implemented in other manners.
  • the apparatus embodiments described above are only illustrative.
  • the division of units is only a logical function division.
  • there may be other division methods for example, multiple units or components may be combined or integrated. to another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as an independent product, may be stored in a computer-readable storage medium.
  • the technical solutions of the present application can be embodied in the form of software products in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, and the computer software products are stored in a storage medium , including several instructions for causing a computer device (which may be a personal computer, a server, or other network device, etc.) to execute all or part of the steps of the method described in the embodiment of FIG. 2a of the present application.
  • the aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk and other media that can store program codes .

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Abstract

本申请实施例公开了一种计算设备，应用于计算设备领域。其中，本申请将宿主机获取的虚拟中断映射至物理层的物理中断，并通过物理层将物理中断对应的虚拟中断标识传递至虚拟处理器，由于硬件层向虚拟处理器透传虚拟中断标识时，虚拟处理器不需要退出，降低了由于软件实现虚拟中断路由时由于虚拟处理器退出而导致的时延。

Description

一种系统以及中断处理方法
本申请要求于2020年06月29日提交中国专利局、申请号为202010604993.9、发明名称为“一种系统以及中断处理方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机领域，尤其涉及一种系统以及中断处理方法。
背景技术
虚拟化技术通过将一台物理计算机增加特定的软件层次，包括宿主机层和虚拟计算机层，以实现对该物理计算机硬件的“虚拟”和“隔离”。每个软件层次包括不同的运行状态，例如用户态和内核态。软件层次和运行状态的多样化使得该物理计算机内部针对某些需求的处理环节增加，从而增加了这些需求的处理时延。
中断处理是计算设备的关键需求，现有计算设备的中断处理过程中，虚拟机监控器(virtual machine monitor，VMM)通过中断虚拟化技术为用户提供虚拟的中断控制器和虚拟的中断翻译服务。虚拟中断传递至虚拟处理器的过程是基于虚拟机监控器的软件来控制的，具体的，VMM可以通过将虚拟中断写入虚拟处理器对应的寄存器来实现。然而，现有的实现中，只有在虚拟机的虚拟CPU被调度到重新获得物理CPU的使用权时，VMM才可以将虚拟中断写入到该虚拟CPU对应的系统寄存器中，为了保证虚拟中断的及时写入，VMM会主动触发虚拟机发生虚拟机退出(VM-exit)，并在虚拟机重新运行(VM-entry)时将虚拟中断写入到该虚拟CPU对应的系统寄存器中。在这种情况下，VMM每次进行虚拟中断的写入时都会导致虚拟处理器暂时停止运行，因此，会增加了虚拟中断处理的时延。
发明内容
第一方面，本申请提供了一种计算设备，所述计算设备包括硬件层和运行在所述硬件层上的宿主机；其中，所述宿主机用于获取虚拟中断；虚拟机中的虚拟设备可以使能虚拟中断，虚拟设备可以是软件模拟的虚拟设备，例如软件模拟的串口等等；宿主机中的后端驱动(例如QEMU)可以捕获虚拟机使能虚拟中断的行为，并触发虚拟中断，该虚拟中断可以包括虚拟设备标识Device ID和虚拟中断向量标识Vector ID，其中，在中断资源初始化时，会为虚拟机的虚拟处理器分配虚拟设备标识Device ID和虚拟中断向量标识Vector ID，每个虚拟处理器唯一对应于一个虚拟设备标识Device ID以及多个虚拟中断向量标识Vector ID；虚拟中断中的虚拟设备标识Device ID可以指示该虚拟中断是哪一个虚拟设备使能的，虚拟中断向量标识Vector ID可以指示具体是虚拟设备分配的多个虚拟中断中的哪一个虚拟中断；
后端驱动(例如QEMU)触发虚拟中断之后，可以将虚拟中断传递至VMM，相应的，宿主机200中的VMM可以获取虚拟中断；
根据所述虚拟中断，获取对应的物理中断标识，并将所述物理中断标识传递至所述硬件层；所述硬件层用于根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识；其中，所述虚拟中断被配置为中断目标虚拟处理器，所述虚拟中断和所述物理中断 标识唯一对应于所述虚拟处理器标识，所述虚拟处理器标识用于指示所述目标虚拟处理器；以及，将所述虚拟中断标识传递至所述目标虚拟处理器。
具体的，硬件层可以包括物理中断翻译服务(interrupt translation service，ITS)和物理中断控制器(generic interrupt controller，GIC)，其中，物理ITS可以获取到物理中断，该物理中断用于中断虚拟CPU，物理ITS可以确定该物理中断对应于哪一个虚拟CPU，以及确定该物理中断对应的虚拟中断标识(可以指示具体是哪一个虚拟中断)；物理GIC可以将虚拟中断标识发送至虚拟CPU。其中，物理ITS可以包括寄存器和运算电路，寄存器可以存储有物理中断和虚拟中断标识之间的对应关系(更具体的，寄存器存储有物理中断和虚拟中断标识之间的对应关系的基地址)，以及物理中断和虚拟处理器标识之间的对应关系(更具体的，寄存器存储有物理中断和虚拟处理器标识之间的对应关系的基地址)，运算电路可以从寄存器中获取到上述对应关系(运算电路可以从寄存器中获取到上述基地址，并基于基地址从内存中获取物理中断和虚拟中断标识之间的对应关系、以及物理中断和虚拟中断标识之间的对应关系)，并确定接收到的物理中断标识对应于哪一个虚拟CPU，以及确定该物理中断标识对应的虚拟中断标识；GIC可以基于ARM架构的芯片中的运算电路来实现，物理GIC是一种先进的微控制器总线架构(advanced microcontroller bus architecture，AMBA)和ARM架构兼容的系统片上(SoC)外设。它具有芯片上的AMBA总线接口。
由于硬件层向目标虚拟处理器透传虚拟中断标识时，不需要写入到虚拟处理器对应的系统寄存器中，再由虚拟处理器在重新投入运行时获取系统寄存器中的虚拟中断标识，而是直接传递至目标虚拟处理器(具体的，可以是将虚拟中断标识写到物理存储器中与虚拟处理器相对应的接口interface中，虚拟处理器可以基于上述接口获取虚拟中断标识)，因此目标虚拟处理器不需要退出，降低了由于软件实现虚拟中断路由时由于虚拟处理器退出而导致的时延。
在一种可选的实现中，所述虚拟中断唯一对应于所述虚拟中断标识。
在一种可选的实现中，所述计算设备包括基于硬件层实现的物理中断翻译服务ITS以及物理中断控制器GIC；
所述物理ITS用于根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识；
所述物理GIC用于将所述虚拟中断标识传递至所述目标虚拟处理器。
在一种可选的实现中，所述宿主机还用于：根据所述虚拟中断以及预配置的第一映射关系，获取所述虚拟中断对应的物理中断标识；所述第一映射关系表示多个虚拟中断以及每个虚拟中断与物理中断标识的对应关系；示例性的，第一映射关系可以包括N个虚拟中断以及N个物理中断标识，其中，N个虚拟中断与N个物理中断标识存在一一对应的关系，N个虚拟中断中的每一个虚拟中断对应于一个物理中断标识，N个物理中断标识中的每一个物理中断标识对应于一个虚拟中断。
所述硬件层还用于：根据所述物理中断标识以及预配置的第二映射关系，获取所述物理中断对应的虚拟中断标识；所述第二映射关系表示多个物理中断标识以及每个物理中断 标识与虚拟中断标识的对应关系。示例性的，第一映射关系可以包括N个物理中断标识以及N个虚拟中断标识，其中，N个物理中断标识与N个虚拟中断标识存在一一对应的关系，N个物理中断标识中的每一个物理中断标识对应于一个虚拟中断标识，N个虚拟中断标识中的每一个虚拟中断标识对应于一个物理中断标识。
在一种可选的实现中，所述硬件层还用于：根据所述物理中断标识和预配置的第三映射关系，获取对应的所述虚拟处理器标识；所述第三映射关系表示多个物理中断标识以及每个物理中断标识与虚拟处理器标识的对应关系。示例性的，第一映射关系可以包括N个物理中断标识以及N个虚拟处理器标识，其中，N个物理中断标识中的每个物理中断标识对应于一个虚拟处理器标识，N个虚拟处理器标识中的每一个虚拟处理器标识对应于一个或多个物理中断标识。
为了可以将VMM获取到的虚拟中断通过硬件层透传至对应的虚拟处理器，且保证虚拟处理器可以接收到正确的虚拟中断标识，则需要在VMM侧预配置一个新的映射关系(下文中可以称之为第一映射关系)，以及在硬件层适应性的配置一个新的映射关系(下文中可以称之为第二映射关系和第三映射关系)，上述VMM侧配置的映射关系和硬件层配置的映射关系可以相互配置，以使得：VMM侧可以基于第一映射关系将获取到的虚拟中断(包括虚拟设备标识Device ID以及虚拟中断向量标识Vector ID)转换为硬件层侧(例如物理ITS)可以识别的物理中断标识(例如包括物理设备标识Device ID和物理中断向量标识Vector ID)；且硬件层侧可以基于预配置的第二映射关系，确定物理中断标识对应的虚拟中断标识，以及基于预配置的第三映射关系，确定物理中断标识对应的虚拟处理器标识，该虚拟处理器标识唯一对应于目标虚拟处理器。
为了保证虚拟处理器可以接收到正确的虚拟中断标识，上述硬件层基于预配置的第二映射关系确定出的虚拟中断标识应该与通过软件实现虚拟中断传递中，VMM确定出的虚拟中断对应的虚拟中断标识是一致的，且上述硬件层基于预配置的第三映射关系确定出的虚拟处理器标识应该与通过软件实现虚拟中断传递中，VMM确定出的虚拟中断对应的虚拟处理器标识是一致的。
在一种可选的实现中，所述硬件层还用于：根据所述物理中断标识，生成物理中断；
根据所述物理中断，获取所述虚拟中断标识以及所述虚拟处理器标识。
在一种实现中，宿主机可以将携带有所述物理中断标识的中断生成请求传递至所述硬件层中的物理ITS，物理ITS可以基于携带有所述物理中断标识的中断生成请求生成相应的物理中断。
在另一种可选的实现中，所述宿主机可以将所述物理中断标识写入位于硬件层的目标寄存器，以便所述目标寄存器生成物理中断。
本申请实施例中，宿主机可以将物理中断标识写入位于硬件层的目标寄存器，该目标寄存器具有可以通过软件的方式产生物理中断的能力，物理ITS可以从目标寄存器中获取到物理中断。
在一种可选的实现中，所述虚拟中断包括虚拟设备标识和虚拟中断向量标识；
所述宿主机还用于：根据所述虚拟中断，获取所述虚拟设备标识对应的物理设备标识， 以及所述虚拟中断向量标识对应的物理中断向量标识；其中，所述物理中断标识包括所述物理设备标识和所述物理中断向量标识。
在一种可选的实现中，所述硬件层还用于：获取所述物理中断标识对应的中断状态信息，所述中断状态信息用于指示所述物理中断标识对应的虚拟中断标识是否可被传递至所述虚拟处理器；具体的，所述中断状态信息可以至少包括如下的一种：中断未决pending状态、中断优先级、中断使能状态；基于所述中断状态信息确定所述虚拟中断标识可被传递至所述虚拟处理器。
其中，中断未决pending信息可以指示虚拟中断处于未决pending/活跃active状态、中断优先级状态可以指示当前的虚拟中断在全部待处理虚拟中断中的优先级、中断使能状态可以表示该中断是否可以被传递至处理器，具体的，如果物理中断标识处于使能状态，且优先级状态以及未决pending状态满足条件，则可以将物理中断标识对应的虚拟中断标识传递至所述虚拟处理器。
在一种可选的实现中，所述宿主机还用于：
在虚拟机热迁移过程中，从所述硬件层获取所述物理中断标识对应的中断状态信息，所述中断状态信息用于指示所述物理中断标识对应的虚拟中断标识是否可被传递至所述虚拟处理器；所述中断状态信息可以至少包括如下的一种：中断未决pending状态、中断优先级、中断使能状态；将所述中断状态信息写入除所述计算设备之外的其他计算设备的硬件层中。
第二方面，本申请提供了一种中断处理方法，所述方法应用于宿主机，所述宿主机运行在所述硬件层上的宿主机，所述方法包括：
获取虚拟中断；
根据所述虚拟中断，获取对应的物理中断标识，并将所述物理中断标识传递至所述硬件层，以便所述硬件层根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识；其中，所述虚拟中断被配置为中断目标虚拟处理器，所述虚拟中断和所述物理中断标识唯一对应于所述虚拟处理器标识，所述虚拟处理器标识用于指示所述目标虚拟处理器，并将所述虚拟中断标识传递至所述目标虚拟处理器。
在一种可选的实现中，所述虚拟中断唯一对应于所述虚拟中断标识。
在一种可选的实现中，所述根据所述虚拟中断，获取对应的物理中断标识，包括：
根据所述虚拟中断以及预配置的第一映射关系，获取所述虚拟中断对应的物理中断标识；所述第一映射关系表示多个虚拟中断以及每个虚拟中断与物理中断标识的对应关系。
在一种可选的实现中，所述虚拟中断包括虚拟设备标识和虚拟中断向量标识；
所述根据所述虚拟中断，获取对应的物理中断标识，包括：
根据所述虚拟中断，获取所述虚拟设备标识对应的物理设备标识，以及所述虚拟中断 向量标识对应的物理中断向量标识；其中，所述物理中断标识包括所述物理设备标识和所述物理中断向量标识。
在一种可选的实现中，所述方法还包括：
在虚拟机热迁移过程中，从所述硬件层获取所述物理中断标识对应的中断状态信息，所述中断状态信息用于指示所述物理中断标识对应的虚拟中断标识是否可被传递至所述虚拟处理器；其中，所述中断状态信息可以至少包括如下的一种：中断未决pending状态、中断优先级、中断使能状态；
将所述中断状态信息写入除所述计算设备之外的其他计算设备的硬件层中。
第三方面，本申请提供了一种中断处理方法，所述方法应用于计算设备，所述计算设备包括硬件层和运行在所述硬件层上的宿主机，所述方法包括：
所述硬件层根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识；其中，所述物理中断标识为所述宿主机根据虚拟中断获取并发送至所述硬件层的所述虚拟中断对应的物理中断标识，所述虚拟中断被配置为中断目标虚拟处理器，所述虚拟中断和所述物理中断标识唯一对应于所述虚拟处理器标识，所述虚拟处理器标识用于指示所述目标虚拟处理器；将所述虚拟中断标识传递至所述目标虚拟处理器。
在一种可选的实现中，所述虚拟中断唯一对应于所述虚拟中断标识。
在一种可选的实现中，所述计算设备包括基于硬件层实现的物理中断翻译服务ITS以及物理中断控制器GIC；
所述硬件层根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识，包括：
所述物理ITS根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识；
所述将所述虚拟中断标识传递至所述目标虚拟处理器，包括：
所述物理GIC将所述虚拟中断标识传递至所述目标虚拟处理器。
在一种可选的实现中，所述硬件层根据所述物理中断标识，获取对应的虚拟中断标识，包括：所述硬件层根据所述物理中断标识以及预配置的第二映射关系，获取所述物理中断对应的虚拟中断标识；所述第二映射关系表示多个物理中断标识以及每个物理中断标识与虚拟中断标识的对应关系。
在一种可选的实现中，所述方法还包括：
根据所述物理中断标识和预配置的第三映射关系，获取对应的所述虚拟处理器标识；所述第三映射关系表示多个物理中断标识以及每个物理中断标识与虚拟处理器标识的对应关系。
在一种可选的实现中，所述硬件层根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识，包括：所述硬件层根据所述物理中断标识，生成物理中断；
根据所述物理中断，获取所述虚拟中断标识以及所述虚拟处理器标识。
在一种可选的实现中，所述方法还包括：
所述硬件层获取所述物理中断标识对应的中断状态信息，所述中断状态信息用于指示所述物理中断标识对应的虚拟中断标识是否可被传递至所述虚拟处理器；基于所述中断状态信息确定所述虚拟中断标识可被传递至所述虚拟处理器。
在一种可选的实现中，所述方法还包括：所述宿主机在虚拟机热迁移过程中，从所述硬件层获取所述物理中断标识对应的中断状态信息，所述中断状态信息用于指示所述物理中断标识对应的虚拟中断标识是否可被传递至所述虚拟处理器；将所述中断状态信息写入除所述计算设备之外的其他计算设备的硬件层中。
第四方面，本申请提供了一种中断处理装置，所述装置包括：
虚拟中断处理单元，用于获取虚拟中断；根据所述虚拟中断，获取对应的物理中断标识，并将所述物理中断标识传递至所述硬件层；
物理中断处理单元，用于根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识；其中，所述虚拟中断被配置为中断目标虚拟处理器，所述虚拟中断和所述物理中断标识唯一对应于所述虚拟处理器标识，所述虚拟处理器标识用于指示所述目标虚拟处理器；以及，将所述虚拟中断标识传递至所述目标虚拟处理器。
其中，所述中断处理装置可以应用于计算设备中，所述计算设备包括硬件层和运行在所述硬件层上的宿主机；所述中断处理装置包括部署在所述宿主机中的虚拟中断处理单元以及部署在所述硬件层中的物理中断处理单元。
在一种可选的实现中，所述虚拟中断唯一对应于所述虚拟中断标识。
在一种可选的实现中，所述计算设备包括基于硬件层实现的物理中断翻译服务ITS以及物理中断控制器GIC；
所述物理ITS用于根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识；
所述物理GIC用于将所述虚拟中断标识传递至所述目标虚拟处理器。
在一种可选的实现中，所述虚拟中断处理单元还用于：根据所述虚拟中断以及预配置的第一映射关系，获取所述虚拟中断对应的物理中断标识；所述第一映射关系表示多个虚拟中断以及每个虚拟中断与物理中断标识的对应关系；
所述物理中断处理单元还用于：根据所述物理中断标识以及预配置的第二映射关系，获取所述物理中断对应的虚拟中断标识；所述第二映射关系表示多个物理中断标识以及每个物理中断标识与虚拟中断标识的对应关系。
在一种可选的实现中，所述物理中断处理单元还用于：根据所述物理中断标识和预配置的第三映射关系，获取对应的所述虚拟处理器标识；所述第三映射关系表示多个物理中断标识以及每个物理中断标识与虚拟处理器标识的对应关系。
在一种可选的实现中，所述物理中断处理单元还用于：根据所述物理中断标识，生成物理中断；
根据所述物理中断，获取所述虚拟中断标识以及所述虚拟处理器标识。
在一种可选的实现中，所述虚拟中断包括虚拟设备标识和虚拟中断向量标识；
所述虚拟中断处理单元还用于：根据所述虚拟中断，获取所述虚拟设备标识对应的物理设备标识，以及所述虚拟中断向量标识对应的物理中断向量标识；其中，所述物理中断标识包括所述物理设备标识和所述物理中断向量标识。
在一种可选的实现中，所述物理中断处理单元还用于：获取所述物理中断标识对应的中断状态信息，所述中断状态信息用于指示所述物理中断标识对应的虚拟中断标识是否可被传递至所述虚拟处理器；基于所述中断状态信息确定所述虚拟中断标识可被传递至所述虚拟处理器。
在一种可选的实现中，所述虚拟中断处理单元还用于：
在虚拟机热迁移过程中，从所述硬件层获取所述物理中断标识对应的中断状态信息，所述中断状态信息用于指示所述物理中断标识对应的虚拟中断标识是否可被传递至所述虚拟处理器；将所述中断状态信息写入除所述计算设备之外的其他计算设备的硬件层中。
第五方面，本申请实施例提供了一种计算设备，计算设备包括通过总线连接的处理器以及存储器，处理器可以调用存储器中的代码以实现上述第二方面或第三方面中任一可选的中断处理方法。
本申请实施例提供了一种计算设备，所述计算设备包括硬件层和运行在所述硬件层上的宿主机；其中，所述宿主机用于获取虚拟中断；根据所述虚拟中断，获取对应的物理中断标识，并将所述物理中断标识传递至所述硬件层；所述硬件层用于根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识；其中，所述虚拟中断被配置为中断目标虚拟处理器，所述虚拟中断和所述物理中断标识唯一对应于所述虚拟处理器标识，所述虚拟处理器标识用于指示所述目标虚拟处理器；以及，将所述虚拟中断标识传递至所述目 标虚拟处理器。通过上述方式，将宿主机获取的虚拟中断映射至物理层的物理中断，并通过物理层将虚拟中断标识传递至虚拟处理器，由于硬件层向虚拟处理器透传虚拟中断标识时，虚拟处理器不需要退出，降低了由于软件实现虚拟中断路由时由于虚拟处理器退出而导致的时延。
附图说明
图1为本申请实施例提供的一种计算节点的架构示意；
图2a为根据本发明的实施例的计算设备；
图2b为据本发明的实施例的中断处理示意；
图3为根据本发明的实施例的中断处理示意；
图4为根据本发明的实施例的中断处理示意；
图5为根据本发明的实施例的中断处理示意；
图6为根据本发明的实施例的中断处理示意；
图7为根据本发明的实施例的中断处理示意；
图8为根据本发明的实施例的中断处理装置示意；
图9为根据本发明的实施例的计算设备示意。
具体实施方式
下面结合附图，对本申请的实施例进行描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。本领域普通技术人员可知，随着技术的发展和新场景的出现，本申请实施例提供的技术方案对于类似的技术问题，同样适用。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或模块的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或模块，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或模块。在本申请中出现的对步骤进行的命名或者编号，并不意味着必须按照命名或者编号所指示的时间/逻辑先后顺序执行方法流程中的步骤，已经命名或者编号的流程步骤可以根据要实现的技术目的变更执行次序，只要能达到相同或者相类似的技术效果即可。
另外，在本发明的描述中，除非另有说明，“多个”的含义是两个或两个以上。本申请中的术语“和/或”或字符“/”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，或A/B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。
为了方便理解本发明实施例，首先以图1所示的计算节点100为例介绍本申请所涉及的虚拟化领域内一些基本概念。其中，计算节点100可以为本申请实施例中的计算设备。
虚拟化是将计算节点的硬件层中的硬件资源(例如处理器、存储器中的存储空间以及网络资源)虚拟化后共享给多个虚拟计算机使用。虚拟计算机为所有类型的计算设备中通过软件虚拟出来的运行环境的统称，该概念包括虚拟机、容器。
如图1所示，计算节点100可以包括硬件层、宿主机层和虚拟化层，虚拟化层包含两台虚拟机。硬件层包括两个处理器110、存储器120、物理中断管理单元160等硬件。在其他实施例中，处理器110的个数和虚拟机的个数还可以更多或更少。
虚拟机(virtual machine，VM)：通过软件在一台物理计算机上模拟出的一台或者多台虚拟计算机。这些虚拟机运行在完全隔离的环境中，就像真正的计算机那样进行工作。虚拟机上可以安装客户操作系统(guest operating system,guest OS)，客户操作系统上运行有一个或多个应用。虚拟机还可访问网络资源。对于在虚拟机中运行的应用而言，就像是在真正的计算机中工作。
虚拟处理器(如图1中110-v)：在虚拟化技术下，以共享或者分片方式提供给虚拟计算机使用的物理处理单元的表示，例如虚拟CPU(virtual central processing unit，vCPU)。一台虚拟计算机可以有一个或多个虚拟处理器为其服务，当存在多个虚拟处理器时，通常有一个虚拟处理器为主虚拟处理器,其他为从虚拟处理器。
宿主机内部署有宿主机操作系统170和VMM 180，VMM 180在其他虚拟化架构中相当于hypervisor或其他类型的虚拟监控装置。VMM 180可以部署在宿主机操作系统170内部，也可以和宿主机操作系统170分开部署。VMM 180负责管理在其上运行的一台或多台虚拟机。
虚拟机(VM)包括虚拟硬件层、客户操作系统190以及多种应用。虚拟硬件层包含虚拟存储器(未在图中示出)、虚拟处理器110-v等虚拟硬件。如图1所示，本实施例包含两个虚拟机，每个虚拟机包含三个虚拟处理器110-v。虚拟处理器110-v是软硬件结合实现的，它的运行实际是物理核读取并运行软件程序实现的，例如一个物理核读取软件程序并在该物理核的硬件辅助虚拟化的特定模式下运行该软件程序以实现一个虚拟处理器110-v。也因此，虚拟处理器110-v需要被调度到某一个物理核上。
虚拟处理器110-v和物理核可以是绑定的关系，即一个虚拟处理器110-v固定在某个物理核上运行，不能被调度到其他物理核上运行，则该虚拟处理器为绑核；一个虚拟处理器110-v可以根据需要被调度到不同的物理核上运行，则该虚拟处理器为非绑核。
在图1中示出的虚拟处理器110-v的总个数为6，大于物理核的数量4，这种场景称之为物理处理器超分配。在物理处理器超分配的情况下，会存在多个虚拟处理器以时间分片方式或其他方式共享同一个物理核的情况，这种物理核叫做非独占核。当然非超分配的情况下也可能出现非独占核。一个物理核与一个虚拟处理器绑核且不被其他虚拟处理器共享，则该物理核是独占核。
应理解，虚拟机相当于一台独立的计算机，所以虚拟机执行动作也可以认为是虚拟处理器执行该动作，而虚拟处理器是软件实现的，所以虚拟处理器执行动作实际上是虚拟处理器所运行的物理处理器或物理核执行该动作。在本发明的多个实施例中，为遵循当下场景的技术表达习惯，会有选择地使用以上表述方式。
虚拟机内可以包含容器(container)，容器相当于应用。在其他一些实施例中，虚拟化层由轻量级虚拟化技术实现，例如libOS190。一个libOS内通常包含一个应用，整个libOS是一个或多个库，和该应用链接成一个单地址空间镜像。本申请实施例通常以传统虚拟化技术 实现的虚拟机为例，其他类型的虚拟化架构可参考虚拟机的实现。
宿主机(host)：作为管理层，用以完成硬件资源的管理、分配；为虚拟机呈现虚拟硬件平台；实现虚拟机的调度和隔离等。在一些实现方式下，宿主机层包括宿主机操作系统和虚拟监控装置，例如虚拟机监视器(virtual machine monitor,VMM)或hypervisor，其中虚拟监控装置可部署在宿主机操作系统之内，也可以部署在宿主机操作系统之外。在另一些实现方式下，“宿主机层”还可以包括1个特权虚拟机(例如虚拟化架构Xen)。其中，虚拟硬件平台对其上运行的各个虚拟计算机提供各种硬件资源，如虚拟处理器、虚拟内存、虚拟磁盘、虚拟网卡等。虚拟计算机则运行在宿主机层为其准备的虚拟硬件平台上。本申请中有时将宿主机层简称为宿主机。
宿主机还可以包括后端驱动(例如开源的QEMU等软件)用于向虚拟机模拟带缓存的虚拟磁盘，包括解析用户设置的缓存配置和缓存策略，例如缓存大小、缓存类型和缓存优先级等，为虚拟机模拟一个符合用户配置的带虚拟机缓存的虚拟磁盘，提供前端驱动所需的第一物理地址的模拟，负责虚拟化管理中涉及到修改缓存属性的管理操作，例如发起缓存在线扩容、减容等任务。后端驱动可以捕获虚拟机使能虚拟中断的行为，并触发相应的虚拟中断，将虚拟中断传递给VMM。
应理解，图1中示出的宿主机中包括的QEMU仅为一种示意，实际应用中，宿主机还可以包括其他类型的后端驱动。
VMM 180作为虚拟监控装置，负责调度各个虚拟机VM的虚拟处理器110-v。例如，基于内核的虚拟机(kernel-based virtual machine，KVM)就是一种典型的VMM。
虚拟中断管理单元181部署在宿主机层。当VMM 180部署在宿主机操作系统170之上时，虚拟中断管理单元181可以部署在宿主机操作系统170内，也可以部署在VMM 180内，也可以部分部署在宿主机操作系统170内，部分部署在VMM 180内。当VMM 180部署在宿主机操作系统170内部时，虚拟中断管理单元181可以部署在VMM 180内，也可以部署在除VMM 180之外的宿主机操作系统170内部，也可以部分部署在VMM 180内，部分部署在除VMM 180之外的宿主机操作系统170内部。
其中，虚拟中断处理单元181可以实现本申请实施例中中断处理方法中与宿主机相关的步骤。
硬件层：虚拟化环境运行的硬件平台。其中，硬件层可包括多种硬件，例如某物理计算机的硬件层可包括处理器和存储器，还可以包括中断控制器、网卡(network interface card，NIC)、输入/输出(input/output I/O)设备等。
处理器110，还可称为物理处理器。物理核代表处理器中最小处理单元，如图1所示，本实施例中处理器可具有两个物理核：核0和核1，以及多个寄存器。在其他一些实施例中，处理器包含的核的数量可以更多或更少，各个处理器包含的核的个数也可以不同。具有多个物理核的处理器被称为多核处理器。按照内核架构是否相同，可以分为同构多核与异构多核。虚拟处理器和物理核可以是绑定的关系，即一个虚拟处理器固定在某个物理核上运行，不能被调度到其他物理核上运行，则该虚拟处理器为绑核；一个虚拟处理器可以根据需要被调度到不同的物理核上运行，则该虚拟处理器为非绑核。
物理中断管理单元160负责收集物理中断请求(也可以称之为物理中断)，并根据一定的规则将这些物理中断请求发送给各个处理器110或者透传至处理器上的虚拟处理器。需要说明的是，物理中断管理单元160可以执行本申请中中断处理方法与硬件层相关的部分步骤。
需要说明的是，中断，中断指的是软件或硬件产生的一种事件，中断包括虚拟中断和物理中断；其中，物理中断为硬件产生的一种事件，硬件将该事件发送到处理器，当处理器接收到该事件时，暂时停止当前程序的执行转而执行该事件对应的程序。硬件产生中断请求可能是硬件自己触发的，也可能是软件触发硬件产生的。计算机中的某些硬件(例如网卡、声卡、鼠标、硬盘等)能在没有处理器介入的情况下完成一定的工作，但是这些硬件还是需要定期中断处理器，让处理器为其做一些特定的工作。
在虚拟化环境中，VMM需要为虚拟机展现一个与物理中断架构类似的虚拟中断架构，在这种情况下，与物理中断相对应的是虚拟中断(也可以称之为虚拟化中断)，虚拟中断可以由虚拟机中的前端驱动使能，并由宿主机中的后端驱动(例如QEMU)捕获并触发。
中断控制器：设置在触发中断请求的硬件和处理器之间，主要用于收集各个硬件产生的中断，并按照一定的优先级或其他规则发送给处理器。
中断亲缘性：指的是中断与处理该中断请求的处理主体(可以是物理处理主体或者是虚拟处理主体，例如物理核)的对应关系。中断控制器可根据该中断亲缘性将一个中断请求发送到该中断请求对应的一个或多个物理处理主体上。
图2a示出了根据本发明的实施例的计算设备。如图2a中示出的那样，所述计算设备包括宿主机200和硬件层203。
本申请实施例中，虚拟机中的虚拟设备可以使能虚拟中断，虚拟设备可以是软件模拟的虚拟设备，例如软件模拟的串口等等；宿主机中的后端驱动(例如QEMU)可以捕获虚拟机使能虚拟中断的行为，并触发虚拟中断，该虚拟中断可以包括虚拟设备标识Device ID和虚拟中断向量标识Vector ID，其中，在中断资源初始化时，会为虚拟机的虚拟处理器分配虚拟设备标识Device ID和虚拟中断向量标识Vector ID，每个虚拟处理器唯一对应于一个虚拟设备标识Device ID以及多个虚拟中断向量标识Vector ID；虚拟中断中的虚拟设备标识Device ID可以指示该虚拟中断是哪一个虚拟设备使能的，虚拟中断向量标识Vector ID可以指示具体是虚拟设备分配的多个虚拟中断中的哪一个虚拟中断。
后端驱动(例如QEMU)触发虚拟中断之后，可以将虚拟中断传递至VMM，相应的，宿主机200中的VMM可以获取虚拟中断。
本申请实施例中，宿主机中的VMM可以获取到虚拟中断，并根据所述虚拟中断，获取对应的物理中断标识，并将所述物理中断标识传递至所述硬件层203，具体可以参照示出了更多细节的图2b。
其中，为了可以将VMM获取到的虚拟中断通过硬件层透传至对应的虚拟处理器，需要将虚拟中断转换为硬件层可以识别并处理的物理中断。
具体的，硬件层可以包括物理中断翻译服务(interrupt translation service，ITS)和物理 中断控制器(generic interrupt controller，GIC)，其中，物理ITS可以获取到物理中断，该物理中断用于中断虚拟CPU，物理ITS可以确定该物理中断对应于哪一个虚拟CPU，以及确定该物理中断对应的虚拟中断标识(可以指示具体是哪一个虚拟中断)；物理GIC可以将虚拟中断标识发送至虚拟CPU。
接下来描述，VMM如何将虚拟中断转换为硬件层可以识别并处理的物理中断，且可以保证虚拟处理器可以接收到正确的虚拟中断标识：
从软件实现的虚拟中断传递过程来看，VMM获取到虚拟中断(包括虚拟设备标识Device ID以及虚拟中断向量标识Vector ID)之后，可以基于软件ITS，确定该虚拟中断对应的虚拟中断标识以及虚拟处理器标识；需要说明的是，这里的虚拟中断标识可以不同于上述的虚拟设备标识Device ID以及虚拟中断向量标识Vector ID，以ARM架构标准规定的GICv4为例，虚拟中断标识为vINTID；虚拟处理器标识唯一指示目标虚拟处理器。
为了可以将VMM获取到的虚拟中断通过硬件层透传至对应的虚拟处理器，且保证虚拟处理器可以接收到正确的虚拟中断标识，则需要在VMM侧预配置一个新的映射关系(下文中可以称之为第一映射关系)，以及在硬件层适应性的配置一个新的映射关系(下文中可以称之为第二映射关系和第三映射关系)，上述VMM侧配置的映射关系和硬件层配置的映射关系可以相互配置，以使得：VMM侧可以基于第一映射关系将获取到的虚拟中断(包括虚拟设备标识Device ID以及虚拟中断向量标识Vector ID)转换为硬件层侧(例如物理ITS)可以识别的物理中断标识(例如包括物理设备标识Device ID和物理中断向量标识Vector ID)；且硬件层侧可以基于预配置的第二映射关系，确定物理中断标识对应的虚拟中断标识，以及基于预配置的第三映射关系，确定物理中断标识对应的虚拟处理器标识，该虚拟处理器标识唯一对应于目标虚拟处理器。
为了保证虚拟处理器可以接收到正确的虚拟中断标识，上述硬件层基于预配置的第二映射关系确定出的虚拟中断标识应该与通过软件实现虚拟中断传递中，VMM确定出的虚拟中断对应的虚拟中断标识是一致的，且上述硬件层基于预配置的第三映射关系确定出的虚拟处理器标识应该与通过软件实现虚拟中断传递中，VMM确定出的虚拟中断对应的虚拟处理器标识是一致的。即，通过软件实现虚拟中断传递中，VMM可以由A(虚拟中断)确定出B(虚拟中断标识)和C(虚拟处理器标识)，则在将VMM获取到的虚拟中断通过硬件层透传至对应的虚拟处理器的方案中，VMM可以由A(虚拟中断)确定出D(物理中断标识)，物理层可以由D(物理中断标识)确定出B(虚拟中断标识)和C(虚拟处理器标识)。
更具体的，为了实现上述过程，在VMM侧，可以预先为每个虚拟设备配置一个对应的物理设备的抽象，之所以称之为物理设备的抽象，是因为该物理设备可以并不实际存在，而仅仅在VMM处保存有物理设备所分配的中断资源，该中断资源可以包括物理中断标识，本实施例中，VMM可以预先存储有虚拟设备对应的多个虚拟中断中每个虚拟中断相对应的物理中断标识。示例性的，虚拟中断可以包括虚拟设备标识Device ID和虚拟中断向量标识Vector ID，则VMM可以获取到虚拟设备标识Device ID对应的物理设备标识Device ID，以及虚拟中断向量标识Vector ID对应的物理中断向量标识Vector ID。
在一种实现中，所述VMM可以维护有预配置的第一映射关系，该第一映射关系可以包 括虚拟中断和物理中断标识的映射关系，VMM可以通过第一映射关系获取到虚拟中断对应的物理中断标识。更具体的，第一映射关系可以包括两个表格(表1和表2)，其中表1包括多个虚拟设备标识Device ID，以及每个虚拟设备标识Device ID对应的指针，VMM可以通过该指针查找到该虚拟设备标识Device ID对应的表2，表2中可包括虚拟设备标识Device ID对应的多个虚拟中断向量标识Vector ID，以及每个虚拟中断向量标识Vector ID对应的物理中断向量标识Vector ID。通过上述方式，VMM可以确定虚拟中断对应的物理中断标识。
VMM获取虚拟中断对应的物理中断标识之后，宿主机可以将物理中断标识传递至硬件层。具体的，宿主机可以将物理中断标识传递至硬件层中的物理ITS。
所述硬件层中的物理ITS可以根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识；其中，所述虚拟中断标识用于唯一指示所述虚拟中断，虚拟处理器标识用于指示目标虚拟处理器；所述硬件层中的物理GIC可以将所述虚拟中断标识传递至所述虚拟处理器标识对应的目标虚拟处理器。
在一种可选的实现中，所述硬件层还可以根据所述物理中断标识，生成物理中断。
本申请实施例中，宿主机还可以将携带有所述物理中断标识的中断生成请求传递至所述硬件层，所述硬件层可以根据所述中断生成请求，生成物理中断。
在一种实现中，宿主机可以将携带有所述物理中断标识的中断生成请求传递至所述硬件层中的物理ITS，物理ITS可以基于携带有所述物理中断标识的中断生成请求生成相应的物理中断。
其中，
在另一种可选的实现中，所述宿主机可以将所述物理中断标识写入位于硬件层的目标寄存器，以便所述目标寄存器生成物理中断。
本申请实施例中，宿主机可以将物理中断标识写入位于硬件层的目标寄存器，该目标寄存器具有可以通过软件的方式产生物理中断的能力，物理ITS可以从目标寄存器中获取到物理中断。
本申请实施例中，所述硬件层可以根据所述物理中断标识以及预配置的第二映射关系，获取对应的虚拟中断标识。
在一种实现中，硬件层中的物理ITS可以维护有预配置的映射关系，该映射关系可以包括物理中断标识、虚拟中断标识以及虚拟处理器之间的映射关系。具体的，硬件层可以维护有第二映射关系，该第二映射关系包括物理中断标识和虚拟中断标识的映射关系，硬件层可以通过第二映射关系获取到物理中断标识对应的虚拟中断标识。硬件层可以维护有第三映射关系，该第三映射关系包括物理中断标识和虚拟处理器标识的映射关系，硬件层可以通过第三映射关系获取到物理中断标识对应的虚拟处理器标识，虚拟处理器标识用于指示目标虚拟处理器。
本申请实施例中，可以在预配置的过程中，在硬件层设置上述第二映射关系和第三映射关系，通过第二映射关系和第三映射关系，硬件层可以确定从VMM获取到的物理中断标识对应的虚拟处理器，以及确定物理中断标识对应的虚拟中断标识，该虚拟中断标识(例如vINTID)可以唯一指示虚拟中断，硬件层可以将虚拟中断标识传递到目标虚拟处理器。
其中，虚拟中断用于中断对应的目标虚拟处理器，为了保证中断路由的正确性，VMM维护的从虚拟中断到物理中断标识的映射关系，以及硬件层维护的物理中断标识到目标虚拟处理器的映射关系，可以相互配合，以使得最终硬件层确定的目标虚拟处理器就是虚拟中断用于中断的对应的目标虚拟处理器。且，除了保证路由终点(目标虚拟处理器)的正确性，也需要保证虚拟中断的内容的正确性，则硬件层通过映射物理中断标识得到的虚拟中断标识需要唯一指示虚拟中断，这样的话，目标虚拟处理器相当于接收到了正确的虚拟中断标识。通过上述方式，和现有通过VMM软件实现虚拟中断路由的方式相比，从虚拟处理器的角度来看是一致的。
本申请实施例中，在GICv4的规范中定义了物理ITS的路由表(上述实施例中的第二映射关系和第三映射关系)，在硬件层上为虚拟中断多开了一条通道，该通道可以将虚拟中断由硬件层透传至目标虚拟处理器。由于硬件层向目标虚拟处理器透传虚拟中断标识时，不需要写入到虚拟处理器对应的系统寄存器中，再由虚拟处理器在重新投入运行时获取系统寄存器中的虚拟中断标识，而是直接传递至目标虚拟处理器，因此虚拟处理器不需要退出，降低了由于软件实现虚拟中断路由时由于虚拟处理器退出而导致的时延。
在一种实现中，所述硬件层还用于：获取所述物理中断标识对应的中断状态信息，所述中断状态信息用于指示所述物理中断标识对应的虚拟中断标识是否可被传递至所述虚拟处理器；其中，所述中断状态信息可以至少包括如下的一种：中断未决pending信息、中断优先级状态、中断使能状态；基于所述中断状态信息确定所述虚拟中断标识可被传递至所述虚拟处理器。其中，中断未决pending信息可以指示虚拟中断处于未决pending/活跃active状态、中断优先级状态可以指示当前的虚拟中断在全部待处理虚拟中断中的优先级、中断使能状态可以表示该中断是否可以被传递至处理器，具体的，如果物理中断标识处于使能状态，且优先级状态以及未决pending状态满足条件，则可以将物理中断标识对应的虚拟中断标识传递至所述虚拟处理器。
本申请实施例中，硬件层中的物理中断控制器可以获取所述物理中断标识对应的中断状态信息，所述中断状态信息用于指示所述物理中断标识对应的虚拟中断标识是否可被传递至所述虚拟处理器，所述中断状态信息至少包括如下的一种：中断未决pending信息、中断优先级状态、中断使能状态；基于所述中断状态信息确定所述虚拟中断标识可被传递至所述虚拟处理器。具体的细节可以参照ARM或者其他标准中与物理层中物理终端控制器规定的相关的描述，这里不再赘述。
本申请实施例提供了一种计算设备，所述计算设备包括硬件层和运行在所述硬件层上的宿主机；其中，所述宿主机用于获取虚拟中断；根据所述虚拟中断，获取对应的物理中断标识，并将所述物理中断标识传递至所述硬件层；所述硬件层用于根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识；其中，所述虚拟中断被配置为中断目标虚拟处理器，所述虚拟中断和所述物理中断标识唯一对应于所述虚拟处理器标识，所述虚拟处理器标识用于指示所述目标虚拟处理器；以及，将所述虚拟中断标识传递至所述目标虚拟处理器。通过上述方式，将宿主机获取的虚拟中断映射至物理层的物理中断，并通过物理层将虚拟中断标识传递至虚拟处理器，由于硬件层向虚拟处理器透传虚拟中断标识 时，虚拟处理器不需要退出，降低了由于软件实现虚拟中断路由时由于虚拟处理器退出而导致的时延。
图3展示了一个更具体的实施例，如图3中示出的那样，VMM可以包括影子映射2021、影子设备2022，中断系统可以包括影子中断域2023，其中，影子映射2021和影子设备2022可以为虚拟机的每个虚拟设备提供一个“影子对象”的抽象。虚拟机内部的前端驱动程序(例如VirtIO驱动程序)会为虚拟设备分配若干个虚拟中断，影子映射2021和影子设备2022负责将虚拟设备的每个虚拟中断链接到主机上的一个物理中断。当虚拟机的前端驱动程序使能虚拟中断(即虚拟设备触发中断时)、调整虚拟中断路由(即需要修改虚拟中断和虚拟处理器之间的映射关系)、修改虚拟中断配置(即需要修改虚拟中断和虚拟中断标识之间的映射关系)等，VMM可以截获到这些操作，将虚拟机配置的中断信息(例如包括上述前端驱动程序使能虚拟中断相关的信息、调整虚拟中断路由相关的信息、修改虚拟中断配置相关的信息等)同步到相应的影子映射2021和影子设备2022中。具体的，影子映射2021可以包括虚拟设备注册的关键信息，如虚拟设备的设备标识、虚拟中断向量标识、虚拟处理器可以处理的的虚拟中断数量上限等，以及该设备的虚拟中断的虚拟路由信息，如虚拟中断标识、每个虚拟中断对应的虚拟处理器等。
影子设备2022可以为每个虚拟设备申请主机上的物理中断标识等物理中断资源。
影子中断域2023可以将物理中断标识传递至物理层的物理ITS。
如图3中示出的那样，硬件层的物理ITS可以包括物理中断路由表2041，硬件层可以包括物理中断控制器2042，其中，物理中断路由表2041可以为预配置的映射关系，该映射关系可以包括物理中断标识、虚拟中断标识以及虚拟处理器之间的映射关系。具体的，硬件层可以维护有第二映射关系，该第二映射关系可以为上述物理中断路由表2041的一部分，第二映射关系包括物理中断标识和虚拟中断标识的映射关系，硬件层可以通过第二映射关系获取到物理中断标识对应的虚拟中断标识。硬件层可以维护有第三映射关系，该第三映射关系可以为上述物理中断路由表2041的一部分，第三映射关系可以包括物理中断标识和虚拟处理器的映射关系，硬件层可以通过第三映射关系获取到物理中断标识对应的虚拟处理器。
物理中断控制器2042可以根据物理中断标识与中断状态信息的对应关系获取所述物理中断标识对应的中断状态信息，并基于所述中断状态信息确定所述虚拟中断标识可被传递至所述虚拟处理器。
图4示出了比图3更多的细节，如图4中示出的那样，VMM可以将所述物理中断标识写入位于硬件层的目标寄存器2043，以便所述目标寄存器2043生成物理中断。该目标寄存器具有可以通过软件的方式生产物理中断，ITS可以从目标寄存器中获取到物理中断。
为了实现上述效果，需要预先配置VMM和硬件层，在一种实现中，虚拟机内部虚拟VirtIO设备驱动加载并初始化，相关操作被VMM截获，建立虚拟中断的软件路由表。虚拟机内部虚拟VirtIO设备驱动通过写外设部件互连标准(peripheral component interconnect，PCI)配置空间使能虚拟设备能力，这一写操作被VMM截获。VMM可以将虚拟设备的关键 信息(虚拟设备的设备号、虚拟中断向量信息、虚拟处理器可以处理的虚拟中断数量上限等)按照协议注册到VMM。VMM为注册的虚拟设备创建一个影子对象，借助注册的虚拟设备信息，创建影子设备，对应申请占用物理主机设备号以及物理中断号资源等。其中，申请的物理中断号资源注册至影子中断域进行管理。VMM可以通过注册的虚拟设备，解析虚拟设备每个虚拟中断的路由信息，包括目标虚拟中断路由设备、虚拟中断号、目标虚拟处理器等信息。影子对象解析出虚拟中断路由关系，转译构建物理中断路由设备格式，借助影子设备对应物理中断，经由影子中断域管理，建立相应虚拟设备物理中断的物理设备中断路由表。VMM通过注册的虚拟设备，解析虚拟设备每个虚拟中断的路由信息，包括目标虚拟中断路由设备、虚拟中断号、目标虚拟处理器等信息。虚拟中断其他属性配置(使能/优先级/亲和性等)，借助影子对象进行转译，经由影子中断域管理，配置/修改影子设备中断配置表。
在一种可选的实现中，所述宿主机还可以在虚拟机热迁移过程中，从所述硬件层获取所述物理中断标识对应的中断状态信息，所述中断状态信息至少包括如下的一种：中断未决pending信息、中断优先级状态、中断使能状态；将所述中断状态信息写入除所述计算设备之外的其他计算设备的硬件层中。其中，参照图5，图5为本申请实施例中一种计算设备的实例，如图5中示出的那样，中断状态信息可以存储在硬件层和VMM都可访问的区域501，则硬件层中的物理中断处理单元204可以获取到中断状态信息，并基于中断状态信息确定虚拟中断标识是否应传递至对应的虚拟处理器，且在虚拟机热迁移过程中，VMM 201也可以从所述硬件层获取所述物理中断标识对应的中断状态信息，并将所述中断状态信息写入除所述计算设备之外的其他计算设备的硬件层中。
下面结合图6描述一下本申请实施例提供的计算设备，如图6中示出的那样，本申请实施例提供的计算设备包括虚拟机、宿主机以及硬件层；其中，虚拟机中的虚拟设备可以触发中断，相应的前端驱动会使能虚拟中断，宿主机中的后端驱动可以捕获到前端驱动使能虚拟中断的行为，并触发虚拟中断，IRQFD子系统可以接收后端驱动触发的虚拟中断，并将虚拟中断传递至影子设备模块，影子设备模块可以确定该虚拟中断的物理中断标识，并由影子中断域将该物理中断标识通过物理ITS驱动传递至硬件层的物理ITS，物理ITS可以确定该物理中断标识对应的虚拟中断标识以及目标虚拟处理器，并由物理GIC将虚拟中断标识传递至目标虚拟处理器VCPU。下面结合图7描述一下本申请实施例提供的计算设备，如图7中示出的那样，本申请实施例提供的计算设备包括虚拟机、宿主机以及硬件层；其中，为了保证软硬件的中断状态一致性，VMM中的虚拟GIC需要获取到物理GIC中的中断状态信息，并更新对应的虚拟中断的中断状态信息；具体的，如图7中示出的那样，后端驱动可以触发进行状态同步的请求，请求中携带了需要同步的虚拟中断相关的信息，影子映射和影子对象可以对虚拟设备的虚拟中断信息进行译码，转换成对应的物理中断标识，并交由影子中断域，影子中断域将物理中断标识传递至物理层的物理ITS，物理GIC可以将物理中断标识相关的中断状态信息传递至宿主机中保存中断状态信息的表中(例如pending表)，进而状态同步系统可以将物理中断标识相关的中断状态信息传递至虚 拟GIC，以使得虚拟GIC更新虚拟中断的中断状态信息。
参照图8，图8为本申请实施例提供的一种中断处理装置800的结构示意，所述计算设备包括硬件层和运行在所述硬件层上的宿主机；所述中断处理装置包括部署在所述宿主机中的虚拟中断处理单元801以及部署在所述硬件层中的物理中断处理单元802；其中，
所述虚拟中断处理单元801用于获取虚拟中断；根据所述虚拟中断，获取对应的物理中断标识，并将所述物理中断标识传递至所述硬件层；
所述物理中断处理单元802用于根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识；其中，所述虚拟中断被配置为中断目标虚拟处理器，所述虚拟中断和所述物理中断标识唯一对应于所述虚拟处理器标识，所述虚拟处理器标识用于指示所述目标虚拟处理器；以及，
将所述虚拟中断标识传递至所述目标虚拟处理器。
其中，虚拟中断处理单元801可以相当于图1中示出的虚拟中断管理单元181、以及图2a和图2b中的虚拟中断处理单元202，以及图3至图7中示出的影子映射、影子设备和影子中断域。
其中，物理中断处理单元801可以相当于图1中示出的物理中断管理单元160、以及图2a和图2b中的物理中断处理单元204，以及图3至图7中示出的物理ITS和物理中断控制器GIC。
在一种可选的实现中，所述虚拟中断唯一对应于所述虚拟中断标识。
在一种可选的实现中，所述计算设备包括基于硬件层实现的物理中断翻译服务ITS以及物理中断控制器GIC；
所述物理ITS用于根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识；
所述物理GIC用于将所述虚拟中断标识传递至所述目标虚拟处理器。
在一种可选的实现中，所述虚拟中断处理单元801还用于：根据所述虚拟中断以及预配置的第一映射关系，获取所述虚拟中断对应的物理中断标识；所述第一映射关系表示多个虚拟中断以及每个虚拟中断与物理中断标识的对应关系；
所述物理中断处理单元802还用于：根据所述物理中断标识以及预配置的第二映射关系，获取所述物理中断对应的虚拟中断标识；所述第二映射关系表示多个物理中断标识以及每个物理中断标识与虚拟中断标识的对应关系。
在一种可选的实现中，所述物理中断处理单元802还用于：根据所述物理中断标识和预配置的第三映射关系，获取对应的所述虚拟处理器标识；所述第三映射关系表示多个物理中断标识以及每个物理中断标识与虚拟处理器标识的对应关系。
在一种可选的实现中，所述物理中断处理单元802还用于：根据所述物理中断标识，生成物理中断；
根据所述物理中断，获取所述虚拟中断标识以及所述虚拟处理器标识。
在一种可选的实现中，所述虚拟中断包括虚拟设备标识和虚拟中断向量标识；
所述虚拟中断处理单元801还用于：根据所述虚拟中断，获取所述虚拟设备标识对应的物理设备标识，以及所述虚拟中断向量标识对应的物理中断向量标识；其中，所述物理中断标识包括所述物理设备标识和所述物理中断向量标识。
在一种可选的实现中，所述物理中断处理单元802还用于：获取所述物理中断标识对应的中断状态信息，所述中断状态信息用于指示所述物理中断标识对应的虚拟中断标识是否可被传递至所述虚拟处理器，所述中断状态信息至少包括如下的一种：中断未决pending状态、中断优先级、中断使能状态；基于所述中断状态信息确定所述虚拟中断标识可被传递至所述虚拟处理器。
在一种可选的实现中，所述虚拟中断处理单元801还用于：
在虚拟机热迁移过程中，从所述硬件层获取所述物理中断标识对应的中断状态信息，所述中断状态信息用于指示所述物理中断标识对应的虚拟中断标识是否可被传递至所述虚拟处理器；所述中断状态信息至少包括如下的一种：中断未决pending状态、中断优先级、中断使能状态；将所述中断状态信息写入除所述计算设备之外的其他计算设备的硬件层中。
本申请还提供了一种非易失性计算机可读存储介质，所述非易失性计算机可读存储介质包含计算机指令用于执行中断处理方法，所述方法应用于宿主机中，所述宿主机位于计算设备，所述计算设备包括硬件层，所述非易失性计算机可读存储介质包括第一计算机指令，用于获取虚拟中断；
所述非易失性计算机可读存储介质包括第二计算机指令，用于根据所述虚拟中断，获取对应的物理中断标识，并将所述物理中断标识传递至所述硬件层。
在一种实现中，第一计算机指令，用于根据所述虚拟中断以及预配置的第一映射关系，获取对应的物理中断标识。
在一种实现中，所述虚拟中断包括虚拟设备标识和虚拟中断向量标识；
第一计算机指令，用于根据所述虚拟中断，获取所述虚拟设备标识对应的物理设备标识，以及所述虚拟中断向量标识对应的物理中断向量标识；其中，所述物理中断标识包括所述物理设备标识和所述物理中断向量标识。
在一种实现中，所述非易失性计算机可读存储介质还包括第三计算机指令，用于在虚拟机热迁移过程中，从所述硬件层获取所述物理中断标识对应的中断状态信息，所述中断状态信息至少包括如下的一种：未决pending信息、优先级信息、使能信息；将所述中断状态信息写入除所述计算设备之外的其他计算设备的硬件层中。
本申请还提供了一种非易失性计算机可读存储介质，所述非易失性计算机可读存储介质包含计算机指令，当计算机指令被计算机执行时可以实现上述实施例中的中断处理方法。
参照图9，图9为本申请实施例提供的一种计算设备900的示意，如图9中示出的那样，计算设备900包括通过总线连接的处理器901以及存储器902，处理器901可以调用存储器902中的代码以实现上述实施例中的中断处理方法。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请所提供的几个实施例中，应该理解到，所揭露的系统，装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者其他网络设备等)执行本申请图2a实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(read-only memory，ROM)、随机存取存储器(random access memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (31)

  1. 一种计算设备，其特征在于，所述计算设备包括硬件层和运行在所述硬件层上的宿主机；其中，
    所述宿主机用于获取虚拟中断；
    根据所述虚拟中断，获取对应的物理中断标识，并将所述物理中断标识传递至所述硬件层；
    所述硬件层用于根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识；其中，所述虚拟中断被配置为中断目标虚拟处理器，所述虚拟中断和所述物理中断标识唯一对应于所述虚拟处理器标识，所述虚拟处理器标识用于指示所述目标虚拟处理器；以及，
    将所述虚拟中断标识传递至所述目标虚拟处理器。
  2. 根据权利要求1所述的计算设备，其特征在于，所述虚拟中断唯一对应于所述虚拟中断标识。
  3. 根据权利要求1或2所述的计算设备，其特征在于，所述计算设备包括基于硬件层实现的物理中断翻译服务ITS以及物理中断控制器GIC；
    所述物理ITS用于根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识；
    所述物理GIC用于将所述虚拟中断标识传递至所述目标虚拟处理器。
  4. 根据权利要求1至3任一所述的计算设备，其特征在于，所述宿主机还用于：根据所述虚拟中断以及预配置的第一映射关系，获取所述虚拟中断对应的物理中断标识；所述第一映射关系表示多个虚拟中断以及每个虚拟中断与物理中断标识的对应关系；
    所述硬件层还用于：根据所述物理中断标识以及预配置的第二映射关系，获取所述物理中断对应的虚拟中断标识；所述第二映射关系表示多个物理中断标识以及每个物理中断标识与虚拟中断标识的对应关系。
  5. 根据权利要求1至4任一所述的计算设备，其特征在于，所述硬件层还用于：根据所述物理中断标识和预配置的第三映射关系，获取对应的所述虚拟处理器标识；所述第三映射关系表示多个物理中断标识以及每个物理中断标识与虚拟处理器标识的对应关系。
  6. 根据权利要求1至5任一所述的计算设备，其特征在于，所述硬件层还用于：根据所述物理中断标识，生成物理中断；
    根据所述物理中断，获取所述虚拟中断标识以及所述虚拟处理器标识。
  7. 根据权利要求1至6任一所述的计算设备，其特征在于，所述虚拟中断包括虚拟设 备标识和虚拟中断向量标识；
    所述宿主机还用于：根据所述虚拟中断，获取所述虚拟设备标识对应的物理设备标识，以及所述虚拟中断向量标识对应的物理中断向量标识；其中，所述物理中断标识包括所述物理设备标识和所述物理中断向量标识。
  8. 根据权利要求1至7任一所述的计算设备，其特征在于，所述硬件层还用于：获取所述物理中断标识对应的中断状态信息，所述中断状态信息用于指示所述物理中断标识对应的虚拟中断标识是否可被传递至所述虚拟处理器；基于所述中断状态信息确定所述虚拟中断标识可被传递至所述虚拟处理器。
  9. 根据权利要求1至8任一所述的计算设备，其特征在于，所述宿主机还用于：
    在虚拟机热迁移过程中，从所述硬件层获取所述物理中断标识对应的中断状态信息，所述中断状态信息用于指示所述物理中断标识对应的虚拟中断标识是否可被传递至所述虚拟处理器；将所述中断状态信息写入除所述计算设备之外的其他计算设备的硬件层中。
  10. 一种中断处理方法，其特征在于，所述方法应用于宿主机，所述宿主机运行在所述硬件层上的宿主机，所述方法包括：
    获取虚拟中断；
    根据所述虚拟中断，获取对应的物理中断标识，并将所述物理中断标识传递至所述硬件层，以便所述硬件层根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识；其中，所述虚拟中断被配置为中断目标虚拟处理器，所述虚拟中断和所述物理中断标识唯一对应于所述虚拟处理器标识，所述虚拟处理器标识用于指示所述目标虚拟处理器，并将所述虚拟中断标识传递至所述目标虚拟处理器。
  11. 根据权利要求10所述的方法，其特征在于，所述虚拟中断唯一对应于所述虚拟中断标识。
  12. 根据权利要求11或12所述的方法，其特征在于，所述根据所述虚拟中断，获取对应的物理中断标识，包括：
    根据所述虚拟中断以及预配置的第一映射关系，获取所述虚拟中断对应的物理中断标识；所述第一映射关系表示多个虚拟中断以及每个虚拟中断与物理中断标识的对应关系。
  13. 根据权利要求10至12任一所述的方法，其特征在于，所述虚拟中断包括虚拟设备标识和虚拟中断向量标识；
    所述根据所述虚拟中断，获取对应的物理中断标识，包括：
    根据所述虚拟中断，获取所述虚拟设备标识对应的物理设备标识，以及所述虚拟中断向量标识对应的物理中断向量标识；其中，所述物理中断标识包括所述物理设备标识和所 述物理中断向量标识。
  14. 根据权利要求10至13任一所述的方法，其特征在于，所述方法还包括：
    在虚拟机热迁移过程中，从所述硬件层获取所述物理中断标识对应的中断状态信息，所述中断状态信息用于指示所述物理中断标识对应的虚拟中断标识是否可被传递至所述虚拟处理器；
    将所述中断状态信息写入除所述计算设备之外的其他计算设备的硬件层中。
  15. 一种中断处理方法，其特征在于，所述方法应用于计算设备，所述计算设备包括硬件层和运行在所述硬件层上的宿主机，所述方法包括：
    所述硬件层根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识；其中，所述物理中断标识为所述宿主机根据虚拟中断获取并发送至所述硬件层的所述虚拟中断对应的物理中断标识，所述虚拟中断被配置为中断目标虚拟处理器，所述虚拟中断和所述物理中断标识唯一对应于所述虚拟处理器标识，所述虚拟处理器标识用于指示所述目标虚拟处理器；将所述虚拟中断标识传递至所述目标虚拟处理器。
  16. 根据权利要求15所述的方法，其特征在于，所述虚拟中断唯一对应于所述虚拟中断标识。
  17. 根据权利要求15或16所述的方法，其特征在于，所述计算设备包括基于硬件层实现的物理中断翻译服务ITS以及物理中断控制器GIC；
    所述硬件层根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识，包括：
    所述物理ITS根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识；
    所述将所述虚拟中断标识传递至所述目标虚拟处理器，包括：
    所述物理GIC将所述虚拟中断标识传递至所述目标虚拟处理器。
  18. 根据权利要求15至17任一所述的方法，其特征在于，
    所述硬件层根据所述物理中断标识，获取对应的虚拟中断标识，包括：所述硬件层根据所述物理中断标识以及预配置的第二映射关系，获取所述物理中断对应的虚拟中断标识；所述第二映射关系表示多个物理中断标识以及每个物理中断标识与虚拟中断标识的对应关系。
  19. 根据权利要求15至18任一所述的方法，其特征在于，所述方法还包括：
    根据所述物理中断标识和预配置的第三映射关系，获取对应的所述虚拟处理器标识；所述第三映射关系表示多个物理中断标识以及每个物理中断标识与虚拟处理器标识的对应关系。
  20. 根据权利要求15至19任一所述的方法，其特征在于，所述硬件层根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识，包括：所述硬件层根据所述物理中断标识，生成物理中断；
    根据所述物理中断，获取所述虚拟中断标识以及所述虚拟处理器标识。
  21. 根据权利要求15至20任一所述的方法，其特征在于，所述方法还包括：
    所述硬件层获取所述物理中断标识对应的中断状态信息，所述中断状态信息用于指示所述物理中断标识对应的虚拟中断标识是否可被传递至所述虚拟处理器；基于所述中断状态信息确定所述虚拟中断标识可被传递至所述虚拟处理器。
  22. 一种中断处理装置，其特征在于，所述装置包括：
    虚拟中断处理单元，用于获取虚拟中断；根据所述虚拟中断，获取对应的物理中断标识，并将所述物理中断标识传递至所述硬件层；
    物理中断处理单元，用于根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识；其中，所述虚拟中断被配置为中断目标虚拟处理器，所述虚拟中断和所述物理中断标识唯一对应于所述虚拟处理器标识，所述虚拟处理器标识用于指示所述目标虚拟处理器；以及，
    将所述虚拟中断标识传递至所述目标虚拟处理器。
  23. 根据权利要求22所述的装置，其特征在于，所述虚拟中断唯一对应于所述虚拟中断标识。
  24. 根据权利要求22或23所述的装置，其特征在于，所述计算设备包括基于硬件层实现的物理中断翻译服务ITS以及物理中断控制器GIC；
    所述物理ITS用于根据所述物理中断标识，获取对应的虚拟中断标识以及虚拟处理器标识；
    所述物理GIC用于将所述虚拟中断标识传递至所述目标虚拟处理器。
  25. 根据权利要求22至24任一所述的装置，其特征在于，所述虚拟中断处理单元还用于：根据所述虚拟中断以及预配置的第一映射关系，获取所述虚拟中断对应的物理中断标识；所述第一映射关系表示多个虚拟中断以及每个虚拟中断与物理中断标识的对应关系；
    所述物理中断处理单元还用于：根据所述物理中断标识以及预配置的第二映射关系，获取所述物理中断对应的虚拟中断标识；所述第二映射关系表示多个物理中断标识以及每个物理中断标识与虚拟中断标识的对应关系。
  26. 根据权利要求22至25任一所述的装置，其特征在于，所述物理中断处理单元还用 于：根据所述物理中断标识和预配置的第三映射关系，获取对应的所述虚拟处理器标识；所述第三映射关系表示多个物理中断标识以及每个物理中断标识与虚拟处理器标识的对应关系。
  27. 根据权利要求22至26任一所述的装置，其特征在于，所述物理中断处理单元还用于：根据所述物理中断标识，生成物理中断；
    根据所述物理中断，获取所述虚拟中断标识以及所述虚拟处理器标识。
  28. 根据权利要求22至27任一所述的装置，其特征在于，所述虚拟中断包括虚拟设备标识和虚拟中断向量标识；
    所述虚拟中断处理单元还用于：根据所述虚拟中断，获取所述虚拟设备标识对应的物理设备标识，以及所述虚拟中断向量标识对应的物理中断向量标识；其中，所述物理中断标识包括所述物理设备标识和所述物理中断向量标识。
  29. 根据权利要求22至28任一所述的装置，其特征在于，所述物理中断处理单元还用于：获取所述物理中断标识对应的中断状态信息，所述中断状态信息用于指示所述物理中断标识对应的虚拟中断标识是否可被传递至所述虚拟处理器；基于所述中断状态信息确定所述虚拟中断标识可被传递至所述虚拟处理器。
  30. 根据权利要求22至29任一所述的装置，其特征在于，所述虚拟中断处理单元还用于：
    在虚拟机热迁移过程中，从所述硬件层获取所述物理中断标识对应的中断状态信息，所述中断状态信息用于指示所述物理中断标识对应的虚拟中断标识是否可被传递至所述虚拟处理器；将所述中断状态信息写入除所述计算设备之外的其他计算设备的硬件层中。
  31. 一种计算机可读介质，具有指令，该指令在由处理装置的一个或多个处理器执行时，可操作用于执行根据权利要求10-21中任一项所述的方法。
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