WO2022002000A1 - 一种欠压保护电路和装置 - Google Patents

一种欠压保护电路和装置 Download PDF

Info

Publication number
WO2022002000A1
WO2022002000A1 PCT/CN2021/102906 CN2021102906W WO2022002000A1 WO 2022002000 A1 WO2022002000 A1 WO 2022002000A1 CN 2021102906 W CN2021102906 W CN 2021102906W WO 2022002000 A1 WO2022002000 A1 WO 2022002000A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
pulse
pulse signal
unit
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/102906
Other languages
English (en)
French (fr)
Inventor
王文情
柳婧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BYD Semiconductor Co Ltd
Original Assignee
BYD Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BYD Semiconductor Co Ltd filed Critical BYD Semiconductor Co Ltd
Priority to EP21832884.7A priority Critical patent/EP4175097A4/en
Publication of WO2022002000A1 publication Critical patent/WO2022002000A1/zh
Priority to US18/145,216 priority patent/US12278476B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H3/00—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection
    • H02H3/24—Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition with or without subsequent reconnection ; integrated protection responsive to undervoltage or no-voltage
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H1/00—Details of emergency protective circuit arrangements
    • H02H1/0007—Details of emergency protective circuit arrangements concerning the detecting means
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0081—Power supply means, e.g. to the switch driver
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4902—Pulse width modulation; Pulse position modulation

Definitions

  • the present disclosure relates to the field of undervoltage protection of pulse width modulation, in particular to an undervoltage protection circuit and device.
  • the input end is generally 0V, and the output end is as high as several hundred V or even more than 1000 V. Therefore, it is necessary to isolate the input and output. Since the input and output stages are isolated, the input stage will not be able to directly detect the condition of the output stage supply voltage.
  • a frequency generator needs to be used at the input and output terminals, that is, a clock signal needs to be provided for the transmission and reception of the undervoltage recovery signal, which will lead to the generation of additional circuits; at the same time, the transmission and determination of the input and output signals
  • the frequency needs to correspond, which reduces the response speed of the input terminal to a certain extent.
  • the clock frequency is often made very high, which greatly increases the loss of the chip.
  • the present disclosure aims to solve at least one of the technical problems existing in the prior art.
  • the present disclosure provides an under-voltage protection circuit and device, including: a primary-side input module and a secondary-side output module, the secondary-side output module includes: an under-voltage determination unit configured to compare the voltage of the secondary-side output module with the voltage of the secondary-side output module.
  • the pulse signal generates unit configured to send out a periodic first pulse signal according to the first control signal, and send a second pulse signal according to the second control signal, the pulse width of the second pulse signal is larger than the pulse width of the first pulse signal;
  • the undervoltage determination unit is connected with the pulse signal generating unit;
  • the primary-side input module is configured to determine that the secondary-side output module is in a non-under-voltage state according to the first pulse signal, and determine that the secondary-side output module is in an under-voltage protection state according to the second pulse signal.
  • the primary-side input module is further configured to determine that the secondary-side output module is in an under-voltage protection state without receiving the first pulse signal within a preset time.
  • the pulse signal generating unit includes a periodic narrow pulse generating unit and an edge signal generating unit; the periodic narrow pulse generating unit is configured to issue a periodic pulse signal in a non-undervoltage state; the edge signal The generating unit is configured to send out a pulse signal in an under-voltage protection state; the first input terminal of the periodic narrow pulse generating unit is configured to input the first PWM signal, and the second input terminal of the periodic narrow pulse generating unit is connected to the The output end of the undervoltage determination unit is connected, the output end of the periodic narrow pulse generation unit is connected with the output end of the edge signal generation unit, and the input end of the edge signal generation unit is connected with the undervoltage determination unit output connection.
  • the primary side input module includes: being configured to judge the state of the secondary side output module according to the first pulse signal and the second pulse signal.
  • the secondary side output module further includes a signal sending unit: configured to send the first pulse signal and the second pulse signal to the primary side input module;
  • the primary side input module further It includes: a signal receiving unit configured to receive the first pulse signal and the second pulse signal of the signal sending unit; the output ends of the periodic narrow pulse generating unit and the edge signal generating unit are respectively connected The input end of the signal sending unit, the output end of the signal sending unit is connected with the input end of the signal receiving unit, and the output end of the signal receiving unit is connected with the determining module.
  • the judging module includes a periodic narrow pulse signal judging unit and a signal pulse width judging unit, the periodic narrow pulse signal judging unit is configured to receive the pulses generated by the periodic narrow pulse generating unit;
  • the signal pulse width determination unit is configured to receive and determine the pulse generated by the edge signal generation unit;
  • the first input end of the periodic narrow pulse signal determination unit is connected to the second PWM signal input end, and the periodic
  • the second input terminal of the narrow pulse signal determination unit is connected with the output terminal of the signal receiving unit, and the output terminal of the periodic narrow pulse signal determination unit is connected with the output terminal of the signal pulse width determination unit and the EN signal;
  • the input end of the signal pulse width determination unit is connected with the output end of the signal receiving unit.
  • the sending frequency of the signal sending unit is greater than the receiving frequency of the signal receiving unit.
  • the undervoltage determination unit compares the obtained voltage of the secondary output module with the preset voltage, so as to output the first control signal or the second control signal; the pulse signal generating unit sends out a periodic first pulse signal according to the received first control signal, and sends out a second pulse signal according to the second control signal; the determination module sends out a second pulse signal according to the first pulse signal and the second pulse signal to judge the state of the secondary side output module.
  • judging the state of the secondary-side output module according to the first pulse signal and the second pulse signal according to the judging module includes: judging that the secondary-side output module is not under-voltage according to acquiring the first pulse signal. state; according to the acquisition of the second pulse signal, to determine that the secondary output module is in the under-voltage protection state
  • the present application also provides an undervoltage protection device, including the aforementioned isolator and any undervoltage protection circuit.
  • the solution adopted in this patent does not increase the extra clock circuit and the loss of the primary and secondary side chip modules, and at the same time ensures that the primary side input module does not malfunction, and can more quickly protect the secondary side output module from under-voltage. It responds in real time to the reply, and at the same time improves the accuracy of the acquisition of the undervoltage state of the secondary input module by the primary side input module.
  • FIG. 1 is a diagram of a secondary output module of an embodiment of an undervoltage protection circuit of the present disclosure
  • FIG. 2 is a schematic structural diagram of an embodiment of an undervoltage protection circuit of the present disclosure
  • FIG. 3 is a specific implementation circuit diagram of an edge signal generation module of an embodiment of an undervoltage protection circuit of the present disclosure
  • FIG. 4 is a waveform diagram of an embodiment of an undervoltage protection circuit of the present disclosure.
  • the solution adopted in this patent does not increase the extra clock circuit and the loss of the primary and secondary side chip modules, and at the same time ensures that the primary side input module does not malfunction, and can more quickly protect the secondary side output module from under-voltage. It responds in real time with the reply, and at the same time retains the sending of the first pulse signal in the non-undervoltage state.
  • the undervoltage determination unit is configured to compare the voltage of the secondary output module with the preset voltage, and when the voltage of the secondary output module is greater than or equal to the preset voltage, the undervoltage determination unit outputs the first output voltage.
  • the undervoltage determination unit when the voltage of the secondary output module is less than the preset voltage, the undervoltage determination unit outputs a second control signal; it also includes a pulse signal generating unit: configured to generate a corresponding pulse signal according to the received control signal, when receiving When the first control signal is received, the pulse signal generating unit generates a periodic first pulse signal; and when the second control signal is received, the pulse signal generating unit generates a second pulse signal; the second pulse signal is an aperiodic signal, The secondary-side output module generates a second pulse signal at the moment of undervoltage, and the pulse width of the second pulse signal is larger than the pulse width of the first pulse signal, and further includes: a signal sending unit, configured to send the first pulse signal and the second pulse signal The signal is sent to the main-side input module.
  • the main-side input module receives the first pulse signal, it is determined that the secondary-side output module is not under-voltage state, that is to say, the secondary-side output module is in a state where under-voltage has not occurred temporarily;
  • the module receives the second pulse signal, it determines that the secondary side output module is in the undervoltage protection state, that is to say, the secondary side output module is in the state of undervoltage, and how to solve the problem of the undervoltage on the secondary side of the ultra-high voltage power tube drive circuit? The problem of ensuring that the generated pulse signal can be accurately sampled by the main side.
  • the undervoltage determination unit mainly realizes the determination of the power supply voltage of the secondary output module.
  • the undervoltage determination unit outputs the UV signal as "1". ” level, on the contrary, when the power supply voltage is lower than the set under-voltage protection threshold, that is, in the under-voltage state, the under-voltage determination unit outputs the UV signal as “0” level.
  • the second pulse signal is a wide pulse.
  • the pulse signal generating unit when receiving the second control signal, the pulse signal generating unit generates a second pulse signal; the second pulse signal is different from the periodic first pulse signal, but is an aperiodic signal, that is, the first pulse signal It belongs to a kind of continuous signal.
  • the pulse width time t1 of the first pulse signal is 2us
  • the second pulse signal is only at the moment when the output module of the secondary side is under-voltage, a relatively wide pulse signal is generated.
  • the pulse width time t2 of the second pulse signal is 10us, and the pulse width of the second pulse signal is larger than the pulse width of the first pulse signal, that is to say, t2>t1; the pulse will continue to be sent in the undervoltage state.
  • a relatively wide pulse signal will be sent to the main-side input module at the same time, so that the main-side input module can detect and judge whether the secondary-side output module is under-voltage through the width of the pulse.
  • the primary-side input module is further configured to determine that the secondary-side output module is in an under-voltage protection state without receiving the first pulse signal within a preset time.
  • the primary side input module determines the state of the secondary side output module according to the first pulse signal and the second pulse signal, and the first pulse signal is a continuously sent pulse signal, so the primary side input module continuously receives The first pulse signal transmitted by the secondary side output module, and when undervoltage occurs, the primary side input module cannot receive the first pulse signal output by the secondary side output module, then the secondary side output module is considered to be under voltage protection
  • the under-voltage protection of the side chip has double signal determination: first, it can be determined by the pulse width of the under-voltage control transformer pin.
  • the secondary output module is in Under-voltage and under-voltage protection status; secondly, it can be judged by continuously sampling the pulse of the under-voltage control transformer pin.
  • the secondary side output module is also considered to be the same. is under voltage protection.
  • the pulse signal generating unit includes a periodic narrow pulse generating unit and an edge signal generating unit; the periodic narrow pulse generating unit is configured to emit periodic pulses in a non-undervoltage state The pulse signal; the edge signal generating unit is configured to send a pulse signal in the under-voltage protection state;
  • the first input terminal of the periodic narrow pulse generating unit is configured to input a first PWM signal
  • the second input terminal of the periodic narrow pulse generating unit is connected to the output terminal of the undervoltage determining unit, and the period
  • the output end of the narrow pulse generating unit is connected with the output end of the edge signal generating unit
  • the input end of the edge signal generating unit is connected with the output end of the under-voltage judging unit.
  • the pulse signal generating unit further includes and a first arithmetic unit; the first input end of the periodic narrow pulse generating unit is configured to input the first PWM signal, and the second input end of the module is connected to the undervoltage determination unit.
  • the output terminal is connected to the output terminal, the output terminal of the periodic narrow pulse generation unit is connected to the first input terminal of the first operation unit, the input terminal of the edge signal generation unit is connected to the output terminal of the undervoltage determination unit, and the The output end of the edge signal generating unit is connected with the second input end of the first arithmetic unit, and the output end of the first arithmetic unit is connected with the signal sending unit, that is, the output of the periodic narrow pulse generating unit The terminal is connected to the output terminal of the edge signal generating unit, and then connected to the first arithmetic unit.
  • the pulse signal generation unit is mainly composed of a periodic narrow pulse generation unit, an edge signal generation unit and a first operation unit; the edge signal generation unit is controlled by the undervoltage determination unit , the edge signal generation unit includes a delay subunit, the undervoltage determination unit outputs the UV signal and provides it to the delay subunit in the edge signal generation unit, and the delay subunit generates a UVD signal, wherein the UVD signal is in phase with the input UV signal , and there is a set delay, and the delay time varies according to the UV signal state.
  • the UV signal flips from “0” to “1”, the power supply of the secondary output module is not under-voltage, and the corresponding delay time is t1, which is relatively short (such as 2us); when the UV signal changes from “1” ” is flipped to “0”, it is the power supply under-voltage protection state of the secondary output module, and the corresponding delay time is t2, which is relatively long (for example, 10us); the UV signal and UVD signal undergo some logic processing to obtain the BPUL signal , corresponding to the pulse width generated by the delay sub-unit when the UV signal rises or falls, considering the corresponding relationship between the delay time and the UV signal state, the corresponding BPUL signal pulse width in the non-undervoltage state will be relatively narrow, such as t1 , and the corresponding BPUL signal pulse width in the under-voltage protection state is wider, such as t2; the corresponding pulse waveform is shown in Figure 4.
  • the periodic narrow pulse generation unit is jointly controlled by the input PWM1 signal of the system and the undervoltage judgment signal UV.
  • the UV output signal remains at "0" level.
  • the UVP output keeps "" 0” level, the signal sending unit of the secondary output module does not work;
  • the edge signal generation unit When the power supply voltage of the secondary output module gradually rises above the undervoltage recovery threshold, the moment the UV output signal flips from “0" level to “1” level, the edge signal generation unit will be triggered, and BPUL outputs a For a pulse with a narrower pulse width t1, the UVP signal sends out the same pulse, which is supplied to the signal sending unit, and the signal is transmitted to the main side chip through the isolator for processing;
  • the periodic narrow pulse generation module will use PWM1 as the trigger signal. Periodic narrow pulses are issued, the pulse width time of the first pulse signal is about t1, and then the UVP provides the signal to the signal sending unit, and the signal is transmitted to the main side chip for processing through the isolator;
  • the edge signal generation unit When the secondary-side chip power gradually drops from high voltage to lower than the secondary-side under-voltage protection threshold, the edge signal generation unit will be triggered at the moment when the UV output signal flips from '1' level to '0' level , BPUL gives a pulse of the pulse width time t2 of the second pulse signal with a wider pulse width, and the UVP signal sends out the same pulse signal, and provides it to the signal sending unit, and transmits the signal to the main side chip through the isolator to be processed.
  • the pulse period is controlled by the PWM signal of the secondary side output module chip, so that the sampling frequency of the primary and secondary sides can be well matched without adding additional circuits, so that the undervoltage protection of the primary and secondary side chips has double signal determination.
  • the primary side input module includes: a determination module configured to determine the state of the secondary side output module according to the first pulse signal and the second pulse signal.
  • the primary side input module is composed of a judgment module, a periodic narrow pulse signal judgment unit, an RS flip-flop and a CPU, etc.
  • the signal receiving unit is configured to receive the first pulse signal and The second pulse signal
  • the determination module is configured to determine the state of the secondary output module according to the first pulse signal and the second pulse signal
  • the RS flip-flop is configured to be configured to be configured according to the first pulse signal.
  • the second pulse signal outputs the UV signal to the CPU, and the CPU is configured to perform an undervoltage state operation according to the UV signal output by receiving the first pulse signal, and execute the undervoltage protection state according to the UV signal output by receiving the second pulse signal operate.
  • the secondary side output module further includes a signal sending unit: configured to send the first pulse signal and the second pulse signal to the primary side input module;
  • the primary side input module further comprises: a signal receiving module a unit configured to receive the first pulse signal and the second pulse signal of the signal sending unit; the output ends of the periodic narrow pulse generating unit and the edge signal generating unit are respectively connected to the input ends of the signal sending unit , the output end of the signal sending unit is connected with the input end of the signal receiving unit, and the output end of the signal receiving unit is connected with the determining module.
  • the determination module includes a periodic narrow pulse signal determination unit and a signal pulse width determination unit, and the periodic narrow pulse signal determination unit is configured to receive the pulses generated by the periodic narrow pulse generation unit.
  • the signal pulse width determination unit is configured to receive and determine the pulse generated by the edge signal generation unit; the first input end of the periodic narrow pulse signal determination unit is connected with the second PWM signal input end, and the The second input terminal of the periodic narrow pulse signal determination unit is connected to the output terminal of the signal receiving unit, and the output terminal of the periodic narrow pulse signal determination unit is connected to the output terminal of the signal pulse width determination unit and the EN signal ;
  • the input end of the signal pulse width determination unit is connected with the output end of the signal receiving unit.
  • the determination module further includes a second operation unit, the output terminal of the periodic narrow pulse signal determination unit is connected with the output terminal of the signal pulse width determination unit and the EN signal, and then connected with the second operation unit.
  • the periodic The first input end of the narrow pulse signal determination unit is connected with the second PWM signal input end
  • the second input end of the periodic narrow pulse signal determination unit is connected with the output end of the signal receiving unit
  • the output end of the periodic narrow pulse signal determination unit is connected with the first input end of the second operation unit
  • the input end of the signal pulse width determination unit is connected with the output end of the signal receiving unit
  • the output end of the signal pulse width determination module is connected with the second input end of the second operation unit
  • the EN signal is input to the third input terminal of the second operation unit.
  • the signal pulse width determination unit is mainly configured to realize the width determination of the pulse signal sent by the secondary output module chip received by the signal receiving unit.
  • the pulse width determination threshold is t3
  • the module output signal UVF output is "0"; otherwise, when the pulse width of RX is greater than or equal to t3, the UVF output is "1".
  • the time setting of t3 here mainly refers to the time setting of the pulse width time t1 of the first pulse signal and the pulse width time t2 of the second pulse signal of the secondary side output module chip, assuming that the pulse width t1 sent by the secondary side chip is 2us , t2 is 10us, then t3 is set to be greater than 2us and less than 10us, for example, it can be set to 5us, 6us, 8us, etc.
  • the periodic narrow pulse signal determination unit is controlled by the RX signal output by the signal receiving unit and the system operating signal PWM2.
  • the PWM2 signal is configured to generate an output related to its periodicity.
  • the frequency of the PWM2 signal can be simply divided;
  • the PWM2 signal is divided by four.
  • the output terminal of the second operation unit is connected to the R input terminal of the flip-flop
  • the S input terminal of the flip-flop is connected to the output terminal of the signal receiving unit
  • the output terminal of the flip-flop is connected to the output terminal of the signal receiving unit.
  • the terminal is connected to the CPU, and the transmission frequency of the signal transmission unit is greater than the reception frequency of the signal reception unit.
  • the secondary-side undervoltage protection module does not send a signal, and the output end of the second arithmetic unit unit is connected to the R input end of the flip-flop, so The S input end of the flip-flop is connected with the output end of the signal receiving unit, and the output end of the flip-flop is connected with the CPU; when the output of the signal receiving unit included in the main side input module is "0" level, then the S flip-flop The S input terminal is also at "0" level.
  • the enable signal EN of the main side input module is at "1" level
  • the enable signal EN signal is usually controlled by the power supply, and now it is assumed that during the power-on process
  • the enable signal EN is at “1” level
  • the enable signal EN is at "0” level
  • the secondary output module will continuously output a square wave signal with a pulse width of t1, and the periodic narrow pulse generates the module synchronization signal PWM1.
  • the pulse signal will be provided to the main side input module through the signal receiving unit, and the signal with the output pulse waveform of RX will be provided to the S terminal of the RS flip-flop, so that the RS flip-flop output UV2 will be flipped to 1 "level”.
  • the output signal UVF of the signal pulse width determination unit will remain at "0" level.
  • the signal PWM2 is also used as the system working signal, and the frequencies of the two are approximately equal, so the signal frequency of RX will be much higher than the signal frequency of the PWM2 signal after frequency division, so the output PB2 signal of the periodic narrow pulse signal generator will remain "0" ” level output; that is, the R input terminal of the RS flip-flop will maintain a “0” level input, so its output UV2 will maintain a “1” level, which means that the power supply voltage of the secondary output module is in a normal power supply state.
  • the secondary output module will immediately send out an instantaneous pulse signal with the pulse width and time t2 of the second pulse signal.
  • the main side input module receives the RX signal, and the output signal UVF is inverted to the "1" level through the signal pulse width determination unit, that is, the R end of the RS flip-flop will be “1" level, so the output of the UV2 signal is The output will flip to "0" level, which means that the secondary output module is in the state of under-voltage protection at this time.
  • the RX signal is also provided to the S-side signal of the RS flip-flop, but since the UVF signal is the processed output signal of the RX signal, there will be a certain delay compared with the RX signal, that is to say, the RX signal will be longer than the RX signal.
  • the UVF signal is first flipped to a "0" level signal, so it can also ensure that the UV2 signal is not affected or disturbed by the inversion of the RX signal during the output process.
  • the secondary input module will not send any more pulses to the primary input except that it can receive a pulse signal with a pulse width of t2 sent at the moment when the secondary input module is under voltage. Therefore, the periodic narrow pulse signal determination unit of the main side input module will turn the output signal to "1" level after several cycles of PWM2 signal output, which further ensures the correct output of the UV2 signal.
  • An under-voltage protection method obtaining the secondary-side output module voltage and the preset voltage, and an under-voltage determination unit compares the obtained secondary-side output module voltage with the preset voltage, so as to output the first output control signal or and the second control signal; the pulse signal generating unit sends out a periodic first pulse signal according to the received first control signal, and sends out a second pulse signal according to the second control signal; the determination module according to the The first pulse signal and the second pulse signal determine the state of the secondary-side output module.
  • judging the state of the secondary-side output module according to the first pulse signal and the second pulse signal according to the judging module includes: judging that the secondary-side output module is in a non-undervoltage state according to acquiring the first pulse signal ; According to the acquisition of the second pulse signal, it is judged that the secondary side output module is in an undervoltage protection state.
  • An undervoltage protection device includes an isolator and any one of the aforementioned undervoltage protection circuits.
  • the output abnormal fault signal is fed back to the isolator through a secondary side output module, and the primary side input module transmits the received output feedback abnormality through the isolator.
  • the main side input module is connected to one end of the isolator, and the other end of the isolator is connected to the secondary side output module, forming an undervoltage protection device.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Dc-Dc Converters (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

本公开提供了一种欠压保护电路，包括：次边输出模块，包括：欠压判定单元被配置为比较次边输出模块电压与预设电压的大小，当次边输出模块电压大于或等于预设电压时输出第一控制信号，当次边输出模块电压小于预设电压时输出第二控制信号；脉冲信号发生单元被配置为根据第一控制信号发出周期性第一脉冲信号，以及根据第二控制信号发出第二脉冲信号，第二脉冲信号的脉宽大于第一脉冲信号的脉宽；主边输入模块被配置为根据第一脉冲信号判定次边输出模块为未欠压状态，以及根据第二脉冲信号判定次边输出模块为欠压保护状态。

Description

一种欠压保护电路和装置
本公开要求于2020年06月30日提交中国专利局，申请号为202010610382.5，申请名称为“一种欠压保护电路、装置及方法”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及脉宽调制的欠压保护领域，特别是一种欠压保护电路和装置。
背景技术
在超高压的功率管驱动电路中，由于输入端与输出端的电源域不同，一般输入端为0V，输出端则高达几百V甚至1000多V。因此需要对输入与输出进行隔离处理。由于输入输出级被隔离，输入级将无法直接检测到输出级电源电压的情况。
在现有的方案中，输入输出端需要用到频率发生器，即需要提供时钟信号用于欠压回复信号的发送和接收，这样则会导致额外电路的产生；同时输入输出信号的发送和判定频率需要对应，在一定程度上降低了输入端的响应速度。为了提高输入端的响应速度，往往会把时钟频率做到很高，大大加大了芯片的损耗。
发明内容
本公开内容旨在至少解决现有技术中存在的技术问题之一。
为此，本公开提供一种欠压保护电路和装置，包括：主边输入模块和次边输出模块，所述次边输出模块包括：欠压判定单元：被配置为比较次边输出模块电压与预设电压的大小，当所述次边输出模块电源电压大于或等于预设电压时输出第一控制信号，当所述次边输出模块电压小于预设电压时输出第二控制信号；脉冲信号发生单元：被配置为根据所述第一控制信号发出周期性第一 脉冲信号，以及根据第二控制信号发出第二脉冲信号，第二脉冲信号的脉宽大于第一脉冲信号的脉宽；所述欠压判定单元与所述脉冲信号发生单元连接；
所述主边输入模块被配置为根据第一脉冲信号判定所述次边输出模块为未欠压状态，以及根据所述第二脉冲信号判定所述次边输出模块为欠压保护状态。
可选地，所述主边输入模块还被配置为在预设时间内未接收到所述第一脉冲信号，判断所述次边输出模块为欠压保护状态。
可选地，所述脉冲信号发生单元包括周期性窄脉冲产生单元和边沿信号产生单元；所述周期性窄脉冲产生单元被配置为在未欠压状态发出周期性的脉冲信号；所述边沿信号产生单元被配置为在欠压保护状态发出脉冲信号；所述周期性窄脉冲产生单元的第一输入端被配置为输入第一PWM信号，所述周期性窄脉冲产生单元的第二输入端与所述欠压判定单元的输出端连接，所述周期性窄脉冲产生单元的输出端与所述边沿信号产生单元的输出端连接，所述边沿信号产生单元的输入端与所述欠压判定单元的输出端连接。
可选地，所述主边输入模块包括：被配置为根据所述第一脉冲信号和所述第二脉冲信号判断次边输出模块的状态。
可选地，所述次边输出模块还包括，信号发送单元：被配置为将所述第一脉冲信号和所述第二脉冲信号发送至所述主边输入模块；所述主边输入模块还包括：信号接收单元，被配置为接收所述信号发送单元的所述第一脉冲信号和所述第二脉冲信号；所述周期性窄脉冲产生单元和所述边沿信号产生单元的输出端分别连接所述信号发送单元的输入端，所述信号发送单元的输出端与所述信号接收单元的输入端连接，所述信号接收单元的输出端与所述判定模块连接。
可选地，所述判定模块包括周期性窄脉冲信号判定单元和信号脉冲宽度判定单元，所述周期性窄脉冲信号判定单元，被配置为接收所述周期性窄脉冲产生单元产生的脉冲；所述信号脉冲宽度判定单元，被配置为接收并判断所述边沿信号产生单元产生的脉冲；所述周期性窄脉冲信号判定单元的第一输入端与第二PWM信号输入端连接，所述周期性窄脉冲信号判定单元的第二输入端与所述信号接收单元的输出端连接，所述周期性窄脉冲信号判定单元的输出端 与所述信号脉冲宽度判定单元的输出端和EN信号连接；所述信号脉冲宽度判定单元的输入端与所述信号接收单元的输出端连接。
可选地，所述信号发送单元的发送频率大于所述信号接收单元的接收频率。
可选地，获取所述次边输出模块电压与所述预设电压，欠压判定单元将获取所述次边输出模块电压与所述预设电压比较，以使得输出所述第一控制信号或所述第二控制信号；脉冲信号发生单元根据接收到的所述第一控制信号发出周期性第一脉冲信号，以及根据第二控制信号发出第二脉冲信号；判定模块根据所述第一脉冲信号和所述第二脉冲信号判断次边输出模块的状态。
可选地，根据判定模块根据所述第一脉冲信号和所述第二脉冲信号判断次边输出模块的状态，包括：根据获取所述第一脉冲信号，以判断次边输出模块为未欠压状态；根据获取所述第二脉冲信号，以判断次边输出模块为欠压保护状态
本申请还提供一种欠压保护装置，包括前述隔离器和任一种欠压保护电路。
本专利所采用的方案不增加额外的时钟电路以及不增加主次边芯片模块损耗的同时，确保主边输入模块不会误动作的前提下，能够更加快速的对次边输出模块的欠压保护和回复进行实时的反应，同时提高了主边输入模块对次边输入模块欠压状态采集的准确性。
附图说明
通过结合附图对本公开示例性实施方式进行更详细的描述，本公开的上述以及其它目的、特征和优势将变得更加明显，其中，在本公开示例性实施方式中，相同的参考标号通常代表相同部件。
图1是本公开欠压保护电路实施例的次边输出模块的图；
图2是本公开欠压保护电路实施例的原理结构图；
图3是本公开欠压保护电路实施例的边沿信号产生模块具体实现电路图；
图4是本公开欠压保护电路实施例的波形图。
具体实施方式
下面将参照附图更详细地描述本公开的优选实施方式。虽然附图中显示了本公开的优选实施方式，然而应该理解，可以以各种形式实现本公开而不应被这里阐述的实施方式所限制。相反，提供这些实施方式是为了使本公开更加透彻和完整，并且能够将本公开的范围完整地传达给本领域的技术人员。
为了使本公开所解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本公开进行进一步详细说明，应当理解，此处所描述的具体实施例仅用以解释本公开，并不用于限定本公开。
本专利所采用的方案不增加额外的时钟电路以及不增加主次边芯片模块损耗的同时，确保主边输入模块不会误动作的前提下，能够更加快速的对次边输出模块的欠压保护和回复进行实时的反应，也同时保留了未欠压状态下第一脉冲信号的发送。
如图1所示，其中包括，欠压判定单元被配置为比较次边输出模块电压与预设电压的大小，当次边输出模块电压大于或等于预设电压时，欠压判定单元输出第一控制信号；当次边输出模块电压小于预设电压时，欠压判定单元输出第二控制信号；还包括脉冲信号发生单元：被配置为根据接收到的控制信号去产生相应的脉冲信号，当接收到第一控制信号时，脉冲信号发生单元发生周期性第一脉冲信号；并且当接收到第二控制信号时，脉冲信号发生单元发生第二脉冲信号；第二脉冲信号是非周期性信号，在发生次边输出模块发生欠压的瞬间产生第二脉冲信号，第二脉冲信号的脉宽大于第一脉冲信号的脉宽，还包括：信号发送单元，被配置为将第一脉冲信号和第二脉冲信号发送至主边输入模块，当主边输入模块接收到第一脉冲信号时，判定次边输出模块为未欠压状态，也就是说次边输出模块为暂未发生欠压的状态；当主边输入模块接收到第二脉冲信号时，判定次边输出模块为欠压保护状态，也就是说次边输出模块为已经发生欠压的状态，解决超高压的功率管驱动电路次边发生欠压时如何确保产生脉冲信号可以被主边准确采样到的问题。
如图4所示，其中欠压判定单元主要实现对次边输出模块电源电压的判定，当次边输出模块电压高过设定的欠压回复阈值时，欠压判定单元输出UV 信号为“1”电平，反之当电源电压低过设定的欠压保护阈值时，即欠压状态下，欠压判定单元输出UV信号为“0”电平。
在一实施例中，所述第二脉冲信号为一个宽脉冲。
具体的，当接收到第二控制信号时，脉冲信号发生单元发生第二脉冲信号；第二脉冲信号是不同于周期性第一脉冲信号，而是非周期性信号，也就是说第一脉冲信号是属于一种持续性发出的信号，假设第一脉冲信号的脉冲宽度时间t1为2us，而第二脉冲信号则是仅在次边输出模块发生欠压的瞬间，产生一个比较宽的脉冲信号，假设第二脉冲信号的脉冲宽度时间t2为10us，而第二脉冲信号的脉宽是要大于第一脉冲信号的脉宽的，也就是说t2＞t1；在未欠压状态下会持续发送脉冲之外，在发生欠压保护的瞬间也会同时向主边输入模块发送一个比较宽的脉冲信号，使主边输入模块可以通过脉冲的宽度进行检测判断次边输出模块是否发生欠压。
在一实施例中，所述主边输入模块还被配置为在预设时间内未接收到所述第一脉冲信号，判断所述次边输出模块为欠压保护状态。
具体的，主边输入模块根据第一脉冲信号和第二脉冲信号来判定次边输出模块的状态，而第一脉冲信号是持续性发出的脉冲信号，所以主边输入模块是持续性的接收到次边输出模块传输的第一脉冲信号，而当发生欠压时，主边输入模块无法接收到次边输出模块输出第一脉冲信号，则认为次边输出模块为欠压保护状态，使主次边芯片的欠压保护有双重的信号判定：首先可以通过欠压控制变压器引脚的脉冲宽度判定，当第二脉冲信号宽度>设定的欠压脉冲宽度阈值时，则认为次边输出模块处于欠压欠压保护状态；其次可以通过持续采样欠压控制变压器引脚的脉冲来判定，当超过设定的时间周期内主边输入模块没有采样到第一脉冲信号，则同样认为次边输出模块处于欠压保护状态。
如图2所述，在一实施例中，所述脉冲信号发生单元包括周期性窄脉冲产生单元和边沿信号产生单元；所述周期性窄脉冲产生单元被配置为在未欠压状态发出周期性的脉冲信号；所述边沿信号产生单元被配置为在欠压保护状态发出脉冲信号；
所述周期性窄脉冲产生单元的第一输入端被配置为输入第一PWM信号，所述周期性窄脉冲产生单元的第二输入端与所述欠压判定单元的输出端连接， 所述周期性窄脉冲产生单元的输出端与所述边沿信号产生单元的输出端连接，所述边沿信号产生单元的输入端与所述欠压判定单元的输出端连接。
所述脉冲信号发生单元还包括和第一运算单元；所述周期性窄脉冲产生单元的第一输入端被配置为输入第一PWM信号，所述模块的第二输入端与欠压判定单元的输出端连接，所述周期性窄脉冲产生单元的输出端与第一运算单元的第一输入端连接，所述边沿信号产生单元的输入端与所述欠压判定单元的输出端连接，所述边沿信号产生单元的输出端与所述第一运算单元的第二输入端连接，所述第一运算单元的输出端与所述信号发送单元连接，也就是说，周期性窄脉冲产生单元的输出端与边沿信号产生单元的输出端连接，后连接第一运算单元。
具体的，如图3所示，对于次边输出模块，其脉冲信号发生单元主要周期性窄脉冲产生单元、边沿信号产生单元和第一运算单元共同组成；边沿信号产生单元受欠压判定单元控制，边沿信号产生单元里包括有延时子单元，欠压判定单元输出UV信号提供给边沿信号产生单元里的延时子单元，延时子单元产生UVD信号，其中UVD信号与输入的UV信号同相，且存在一个设定的延时，其延时时间根据UV信号状态不同下输出也不同。
例如，当UV信号从“0”翻转为“1”时，此时为次边输出模块电源未欠压状态，对应的延时时间为t1，比较短(比如2us)；当UV信号从“1”翻转为“0”时，此时为次边输出模块电源欠压保护状态，其对应的延时时间为t2，比较长(比如10us)；UV信号和UVD信号经过一些逻辑处理，得到BPUL信号，对应UV信号上升或者下降时由延时子单元所产生的脉冲宽度，考虑到延时时间与UV信号状态的对应关系，未欠压状态下所对应的BPUL信号脉冲宽度会比较窄，例如t1，而欠压保护状态下所对应的BPUL信号脉冲宽度较宽，例如t2；其对应的脉冲波形示意图见图4。
周期性窄脉冲产生单元受系统的输入PWM1信号以及欠压判定信号UV共同控制，在欠压欠压保护状态下，即UV＝“0”时，周期性窄脉冲产生单元将不会发出有效信号，此时该模块输出信号PPUL＝“0”；在欠压未欠压状态下，此时UV＝“1”，周期性窄脉冲产生模块将受PWM1控制，由PWM1的信号沿触发产生脉冲信号，由于PWM1信号为输入的周期性信号，因此触发产生的 脉冲信号PPUL也是与PWM1同步的周期性信号，周期性窄脉冲产生单元所产生的窄脉冲信号宽度保持一致且比较窄，也就是设定为近似t1的脉冲宽度。
通过以上的模块分析次边输出模块的工作过程如下:
1、当次边输出模块的初始电源低于欠压判定单元的欠压保护阈值时，UV输出信号保持“0”电平，此时BPUL无输出信号，PPUL无输出信号，得到UVP输出保持“0”电平，次边输出模块的信号发送单元不工作；
2、当次边输出模块的电源电压逐渐上升至高于欠压回复阈值时，UV输出信号由“0”电平翻转为“1”电平的瞬间，边沿信号产生单元将被触发，BPUL输出一个较窄脉宽t1的脉冲，UVP信号随之发出相同的脉冲，提供到信号发送单元，并通过隔离器将信号传递到主边芯片进行处理；
3、之后一直到次边输出模块电源下降到低于次边欠压保护阈值之前，UV的输出信号都将保持’1’电平，此时周期性窄脉冲产生模块将以PWM1为触发信号，发出周期性的窄脉冲，第一脉冲信号的脉冲宽度时间约为t1的信号，再由UVP提供给信号发送单元，通过隔离器将信号传递到主边芯片进行处理；
4、当次边芯片电源由高电压逐渐下降到低于次边欠压保护阈值的时候，在UV输出信号由’1’电平翻转为’0’电平瞬间，边沿信号产生单元将被触发，BPUL给出一个较宽脉宽的第二脉冲信号的脉冲宽度时间t2的脉冲，UVP信号随之发出相同脉冲信号，并且将其提供到信号发送单元，通过隔离器将信号传递到主边芯片进行处理。
脉冲周期采用次边输出模块芯片的PWM信号控制，做到不需要额外增加电路的前提下使主次边采样频率能很好的匹配，使主次边芯片的欠压保护有双重的信号判定。
在一实施例中，主边输入模块包括：判定模块，被配置为根据所述第一脉冲信号和所述第二脉冲信号判断次边输出模块的状态。
具体的，主边输入模块则由判定模块、周期性窄脉冲信号判定单元、RS触发器及CPU等共同组成，信号接收单元，是被配置为接收次边输出模块发送模块的第一脉冲信号和第二脉冲信号，判定模块，被配置为根据所述第一脉冲信号和所述第二脉冲信号判断次边输出模块的状态，RS触发器，是被配置 为将被配置为根据第一脉冲信号和第二脉冲信号输出UV信号给CPU，CPU：被配置为根据接收到第一脉冲信号输出的UV信号执行未欠压状态操作，根据接收到第二脉冲信号输出的UV信号执行欠压保护状态操作。
在一实施例中，次边输出模块还包括，信号发送单元：被配置为将所述第一脉冲信号和第二脉冲信号发送至所述主边输入模块；主边输入模块还包括：信号接收单元，被配置为接收信号发送单元的所述第一脉冲信号和第二脉冲信号；所述周期性窄脉冲产生单元和所述边沿信号产生单元的输出端分别连接所述信号发送单元的输入端，所述信号发送单元的输出端与所述信号接收单元的输入端连接，所述信号接收单元的输出端与所述判定模块连接。
在一实施例中，所述判定模块包括周期性窄脉冲信号判定单元和信号脉冲宽度判定单元，所述周期性窄脉冲信号判定单元，被配置为接收所述周期性窄脉冲产生单元产生的脉冲；所述信号脉冲宽度判定单元，被配置为接收并判断所述边沿信号产生单元产生的脉冲；所述周期性窄脉冲信号判定单元的第一输入端与第二PWM信号输入端连接，所述周期性窄脉冲信号判定单元的第二输入端与所述信号接收单元的输出端连接，所述周期性窄脉冲信号判定单元的输出端与所述信号脉冲宽度判定单元的输出端和EN信号连接；所述信号脉冲宽度判定单元的输入端与所述信号接收单元的输出端连接。
判定模块还包括第二运算单元，所述周期性窄脉冲信号判定单元的输出端与所述信号脉冲宽度判定单元的输出端和EN信号连接，后与第二运算单元连接，具体的，周期性窄脉冲信号判定单元的第一输入端与第二PWM信号输入端连接，周期性窄脉冲信号判定单元的第二输入端与信号接收单元的输出端连接，周期性窄脉冲信号判定单元的输出端与第二运算单元的第一输入端连接；信号脉冲宽度判定单元的输入端与信号接收单元的输出端连接，信号脉冲宽度判定模块的输出端与第二运算单元的第二输入端连接；第二运算单元的第三输入端输入EN信号。
如图2所示，其中信号脉冲宽度判定单元主要被配置为实现对信号接收单元所接收到的次边输出模块芯片发送的脉冲信号的宽度判定，此处假设定脉冲宽度判定阈值为t3，当判定信号接收单元所接收到的信号RX的脉冲宽度小于t3，则该模块输出信号UVF输出为“0”；反之当RX的脉冲宽度大于或等于t3， 则UVF输出为“1”。
此处t3的时间设定主要参考次边输出模块芯片的第一脉冲信号的脉冲宽度时间t1和第二脉冲信号的脉冲宽度时间t2的时间设定，假设次边芯片所发送脉冲宽度t1为2us，t2为10us，则t3设定要大于2us且小于10us，比如可以设定为5us、6us、8us等。
周期性窄脉冲信号判定单元受信号接收单元输出RX信号以及系统工作信号PWM2的控制，PWM2信号被配置为产生与其周期性相关的输出，此处可简单的对PWM2信号进行分频；假设此处对PWM2信号采用四分频，在RX保持“0”的前提下，PWM2输入四个周期，则PB2输出将跳变为“1”。而RX信号则实现对周期性窄脉冲信号发生器的复位，一旦RX＝“1”，则内部电路分频器将被复位，即需要重新开始计数，确保输出PB2信号保持“0”。
在一实施例中，第二运算单元单元的输出端与所述触发器的R输入端连接，所述触发器的S输入端与所述信号接收单元的输出端连接，所述触发器的输出端与所述CPU连接，所述信号发送单元的发送频率大于所述信号接收单元的接收频率。
主边输入模块搭配次边输出模块的工作过程如下描述：
1、当初始次边输出芯片电源电压很低的情况下，次边欠压保护模块是没有信号发送出去的，而第二运算单元单元的输出端与所述触发器的R输入端连接，所述触发器的S输入端与信号接收单元的输出端连接，所述触发器的输出端与所述CPU连接；当主边输入模块包含的信号接收单元输出为“0”电平时，那么S触发器的S输入端同样也为“0”电平，此时的主边输入模块由于使能信号EN为“1”电平，(使能信号EN信号通常受电源控制，现在假定上电过程中的使能信号EN为“1”电平的情况下，一旦电源建立则使能信号EN为“0”电平，那么使能信号EN只作为上电初始化，而在后续的分析中，都是假设使能信号EN为“0”电平的情况下)，RS触发器输出信号即次边电源欠压判定输出信号UV2＝“0”电平，则代表次边输出模块处于欠压的状态。
2、一旦次边输出模块芯电源电压上升到高于次边欠压回复阈值时，次边输出模块将持续性的输出脉冲宽度为t1的方波信号，周期性窄脉冲产生模块同步信号PWM1的脉冲信号会经过信号接收单元提供给主边输入模块，并输 出脉冲波形为RX的信号提供给RS触发器的S端，使RS触发器输出UV2翻转至1“电平”。
同时又由于RX信号脉冲宽度是比较窄的脉冲信号，因此信号脉冲宽度判定单元输出信号UVF将会保持“0”电平，同时由于次边发送模块过来的脉冲周期与信号PWM1同步，信号PWM1与信号PWM2同样作为系统工作信号，两者的频率近似相等，因此RX的信号频率将远高于PWM2信号经过分频后的信号频率，因此周期性窄脉冲信号发生器的输出PB2信号将保持“0”电平输出；即此时RS触发器的R输入端将保持“0”电平输入，因此其输出UV2将保持“1”电平，代表次边输出模块电源电压处于正常供电的状态。
3、一旦次边输出模块电源电压下降到低于次边输出模块欠压保护阈值的情况下，则次边输出模块将立刻发出一个第二脉冲信号的脉冲宽度时间为t2的瞬时的脉冲信号，此时主边输入模块接收到RX信号，通过信号脉冲宽度判定单元得到输出信号UVF的翻转至“1”电平，即RS触发器的R端将为“1”电平，因此输出UV2信号的输出将翻转为“0”电平，代表此时次边输出模块正在处于欠压保护的状态。此处RX信号同时也提供给RS触发器的S端信号，但是由于UVF信号是RX信号经过处理后的输出信号，与RX信号相比的话会存在一定的延时，也就是说RX信号会比UVF信号先翻转为“0”电平信号，因此也是可以保证UV2信号在输出的过程中不受RX信号翻转的影响或干扰。
此外，一旦次边输入模块发生欠压保护，在除了可以接收到在次边输入模块欠压瞬间所发出的t2脉宽的脉冲信号以外，次边输入模块将不会再发送脉冲给主边输入模块，因此主边输入模块的周期性窄脉冲信号判定单元会在经过几个周期的PWM2信号输出后，输出信号也会翻转为“1”电平，同样的进一步确保了UV2信号的正确输出。
一种欠压保护方法，获取所述次边输出模块电压与所述预设电压，欠压判定单元将获取所述次边输出模块电压与所述预设电压比较，以使得输出所述第一控制信号或和所述第二控制信号；脉冲信号发生单元根据接收到的所述第一控制信号发出周期性第一脉冲信号，以及根据第二控制信号发出第二脉冲信号；判定模块根据所述第一脉冲信号和所述第二脉冲信号判断次边输出模块的状态。
具体的，根据判定模块根据所述第一脉冲信号和所述第二脉冲信号判断次边输出模块的状态，包括：根据获取所述第一脉冲信号，以判断次边输出模块为未欠压状态；根据获取所述第二脉冲信号，以判断次边输出模块为欠压保护状态。
一种欠压保护装置，包括隔离器和前述任一种欠压保护电路，输出异常故障信号是通过次边输出模块反馈给隔离器，主边输入模块又经过隔离器传输接收到的输出反馈异常故障信号的过程，主边输入模块连接隔离器的一端，隔离器的另一端与次边输出模块连接，构成了一种欠压保护装置。
以上所述仅为本公开的较佳实施例而已，并不用以限制本公开，凡在本公开的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本公开的保护范围之内。
尽管已经示出和描述了本公开的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本公开的原理和精神的情况下可以对这些实施例进行多种变化、修改、替换和变型，本公开的范围由所附权利要求及其等同限定。

Claims (10)

  1. 一种欠压保护电路，包括：主边输入模块和次边输出模块，所述主边输入模块与所述次边输出模块连接，其特征在于，所述次边输出模块包括：
    欠压判定单元：被配置为比较次边输出模块电压与预设电压的大小，当所述次边输出模块电压大于或等于预设电压时输出第一控制信号，当所述次边输出模块电压小于预设电压时输出第二控制信号；
    脉冲信号发生单元：被配置为根据所述第一控制信号发出周期性第一脉冲信号，以及根据第二控制信号发出第二脉冲信号，第二脉冲信号的脉宽大于第一脉冲信号的脉宽；
    所述欠压判定单元与所述脉冲信号发生单元连接；
    所述主边输入模块被配置为根据第一脉冲信号判定所述次边输出模块为未欠压状态，以及根据所述第二脉冲信号判定所述次边输出模块为欠压保护状态。
  2. 如权利要求1所述的欠压保护电路，其特征在于，所述主边输入模块还被配置为在预设时间内未接收到所述第一脉冲信号，判断所述次边输出模块为欠压保护状态。
  3. 如权利要求1或2所述的欠压保护电路，其特征在于，
    所述脉冲信号发生单元包括周期性窄脉冲产生单元和边沿信号产生单元；
    所述周期性窄脉冲产生单元被配置为在未欠压状态发出周期性的脉冲信号；
    所述边沿信号产生单元被配置为在欠压保护状态发出脉冲信号；
    所述周期性窄脉冲产生单元的第一输入端被配置为输入第一PWM信号，所述周期性窄脉冲产生单元的第二输入端与所述欠压判定单元的输出端连接，所述周期性窄脉冲产生单元的输出端与所述边沿信号产生单元的输出端连接，所述边沿信号产生单元的输入端与所述欠压判定单元的输出端连接。
  4. 如权利要求1-3中任一项所述的欠压保护电路，其特征在于，
    所述主边输入模块包括：
    判定模块：被配置为根据所述第一脉冲信号和所述第二脉冲信号判断次边输出模块的状态。
  5. 如权利要求1-4中任一项所述的欠压保护电路，其特征在于，所述次边输出模块还包括，信号发送单元：被配置为将所述第一脉冲信号和所述第二脉冲信号发送至所述主边输入模块；所述主边输入模块还包括：信号接收单元，被配置为接收所述信号发送单元的所述第一脉冲信号和所述第二脉冲信号；所述周期性窄脉冲产生单元和所述边沿信号产生单元的输出端分别连接所述信号发送单元的输入端，所述信号发送单元的输出端与所述信号接收单元的输入端连接，所述信号接收单元的输出端与所述判定模块连接。
  6. 如权利要求1-4中任一项所述的欠压保护电路，其特征在于，所述判定模块包括周期性窄脉冲信号判定单元和信号脉冲宽度判定单元，
    所述周期性窄脉冲信号判定单元，被配置为接收所述周期性窄脉冲产生单元产生的脉冲；
    所述信号脉冲宽度判定单元，被配置为接收并判断所述边沿信号产生单元产生的脉冲；
    所述周期性窄脉冲信号判定单元的第一输入端与第二PWM信号输入端连接，所述周期性窄脉冲信号判定单元的第二输入端与所述信号接收单元的输出端连接，所述周期性窄脉冲信号判定单元的输出端与所述信号脉冲宽度判定单元的输出端和EN信号连接；所述信号脉冲宽度判定单元的输入端与所述信号接收单元的输出端连接。
  7. 如权利要求1-5中任一项所述的欠压保护电路，其特征在于，所述信号发送单元的发送频率大于所述信号接收单元的接收频率。
  8. 一种欠压保护方法，其特征在于，包括权利要求1-7中任一项所述的欠压保护电路，
    获取所述次边输出模块电压与所述预设电压，
    欠压判定单元将获取所述次边输出模块电压与所述预设电压比较，以使得输出所述第一控制信号或所述第二控制信号；
    脉冲信号发生单元根据接收到的所述第一控制信号发出周期性第一脉冲信号，以及根据第二控制信号发出第二脉冲信号；
    判定模块根据所述第一脉冲信号和所述第二脉冲信号判断次边输出模块的状态。
  9. 如权利要求8所述的欠压保护方法，其特征在于，根据判定模块根据所述第一脉冲信号和所述第二脉冲信号判断次边输出模块的状态，包括：
    根据获取所述第一脉冲信号，以判断次边输出模块为未欠压状态；
    根据获取所述第二脉冲信号，以判断次边输出模块为欠压保护状态。
  10. 一种欠压保护装置，其特征在于，包括隔离器和权利要求1-7中任一项所述的欠压保护电路。
PCT/CN2021/102906 2020-06-30 2021-06-29 一种欠压保护电路和装置 Ceased WO2022002000A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP21832884.7A EP4175097A4 (en) 2020-06-30 2021-06-29 CIRCUIT AND UNDERVOLTAGE PROTECTION DEVICE
US18/145,216 US12278476B2 (en) 2020-06-30 2022-12-22 Under voltage protection circuit and device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010610382.5A CN113872148B (zh) 2020-06-30 2020-06-30 一种欠压保护电路、装置及方法
CN202010610382.5 2020-06-30

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US18/145,216 Continuation US12278476B2 (en) 2020-06-30 2022-12-22 Under voltage protection circuit and device

Publications (1)

Publication Number Publication Date
WO2022002000A1 true WO2022002000A1 (zh) 2022-01-06

Family

ID=78980997

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/102906 Ceased WO2022002000A1 (zh) 2020-06-30 2021-06-29 一种欠压保护电路和装置

Country Status (4)

Country Link
US (1) US12278476B2 (zh)
EP (1) EP4175097A4 (zh)
CN (1) CN113872148B (zh)
WO (1) WO2022002000A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116609697A (zh) * 2023-07-07 2023-08-18 无锡芯加集成电路有限公司 一种电源欠压检测方法
CN118868304B (zh) * 2024-07-08 2025-04-22 深圳市驰普科达科技有限公司 户外电源装置及其控制方法、控制装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203457063U (zh) * 2013-09-13 2014-02-26 深圳市金威源科技股份有限公司 一种高频开关电源输出整流电路
CN104052248A (zh) * 2014-06-25 2014-09-17 台达电子企业管理（上海）有限公司 电力变换装置及其保护信号传递方法
US20150381035A1 (en) * 2014-06-30 2015-12-31 Texas Instruments Incorporated Droop reduction circuit for charge pump buck converter
CN105958435A (zh) * 2016-06-24 2016-09-21 中航太克（厦门）电力技术股份有限公司 一种基于fpga的电网过欠压检测电路及方法
CN206601436U (zh) * 2017-01-13 2017-10-31 北京新能源汽车股份有限公司 一种驱动板欠压检测电路

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9421402D0 (en) * 1994-10-21 1994-12-07 Plessey Semiconductors Ltd Power switch driver
US5900683A (en) * 1997-12-23 1999-05-04 Ford Global Technologies, Inc. Isolated gate driver for power switching device and method for carrying out same
JP4585970B2 (ja) 2006-01-05 2010-11-24 Ｏｋｉセミコンダクタ株式会社 パルス幅変調装置
CN100574102C (zh) 2006-08-30 2009-12-23 广州金升阳科技有限公司 Igbt驱动器及其驱动信号的处理方法
TWI360277B (en) * 2007-06-15 2012-03-11 Silicon Touch Tech Inc Power supply protection apparatus and related meth
JP2010124454A (ja) * 2008-10-20 2010-06-03 Rohm Co Ltd パルス発生回路およびパルス幅変調器、遅延回路ならびにそれらを利用したスイッチング電源の制御回路
CN101867295B (zh) * 2010-03-16 2014-07-16 成都芯源系统有限公司 一种电路及控制方法
US9948175B2 (en) * 2010-10-25 2018-04-17 Analog Devices, Inc. Soft-start control system and method for an isolated DC-DC converter with secondary controller
CN103326706B (zh) * 2013-05-27 2015-12-23 上海奔赛电子科技发展有限公司 一种集成电路的滤波电路以及集成电路
CN103546020B (zh) * 2013-10-28 2016-08-31 北京京铁信达铁路设备有限公司 高压igbt驱动及保护电路
EP2996232B1 (en) * 2013-11-22 2019-01-02 Fuji Electric Co., Ltd. Power semiconductor module drive control system and power semiconductor module control circuit
CN104201652B (zh) * 2014-09-10 2017-02-15 广州金升阳科技有限公司 一种电源保护控制方法
TWI533554B (zh) * 2014-11-21 2016-05-11 力林科技股份有限公司 具低電壓保護之電源供應器及其操作方法
US10554456B2 (en) * 2017-08-23 2020-02-04 Semiconductor Components Industries, Llc Circuits and methods for bi-directional data communication over isolation channels
JP7176192B2 (ja) 2018-02-06 2022-11-22 株式会社デンソー スイッチの駆動装置
US10862294B2 (en) * 2018-02-16 2020-12-08 Microchip Technology Incorporated Under-voltage and over-voltage protection using a single comparator
CN109739710B (zh) * 2019-01-04 2022-07-12 华大半导体有限公司 一种欠压检测电路和检测欠压的方法
CN110837044A (zh) 2019-10-14 2020-02-25 中国北方发动机研究所(天津) 混合动力电机驱动频压检测电路
CN111106596A (zh) * 2019-12-13 2020-05-05 珠海格力电器股份有限公司 一种上桥臂igbt驱动电源欠压保护电路、控制方法及电机驱动器
CN110854819B (zh) * 2019-12-13 2022-01-21 陕西亚成微电子股份有限公司 一种集成Xcap电容放电和输入欠压保护的方法和电路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN203457063U (zh) * 2013-09-13 2014-02-26 深圳市金威源科技股份有限公司 一种高频开关电源输出整流电路
CN104052248A (zh) * 2014-06-25 2014-09-17 台达电子企业管理（上海）有限公司 电力变换装置及其保护信号传递方法
US20150381035A1 (en) * 2014-06-30 2015-12-31 Texas Instruments Incorporated Droop reduction circuit for charge pump buck converter
CN105958435A (zh) * 2016-06-24 2016-09-21 中航太克（厦门）电力技术股份有限公司 一种基于fpga的电网过欠压检测电路及方法
CN206601436U (zh) * 2017-01-13 2017-10-31 北京新能源汽车股份有限公司 一种驱动板欠压检测电路

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4175097A4 *

Also Published As

Publication number Publication date
CN113872148A (zh) 2021-12-31
CN113872148B (zh) 2022-12-13
US20230117084A1 (en) 2023-04-20
EP4175097A1 (en) 2023-05-03
US12278476B2 (en) 2025-04-15
EP4175097A4 (en) 2023-12-27

Similar Documents

Publication Publication Date Title
WO2022002000A1 (zh) 一种欠压保护电路和装置
US10547311B2 (en) Reducing glitches that occur when multiplexing of asynchronous clocks using flip-flops and logic gates
US4308472A (en) Clock check circuit
CN108227595B (zh) 激光器脉冲同步控制方法及系统
AU616258B2 (en) Process and arrangement for the monitoring of a clock signal
US8847639B1 (en) Waveform generator
CN112886951A (zh) 一种高精度守时设备的多时钟源无缝切换电路及方法
CN115801503A (zh) 面向跨芯片互连的lvds并行数据自动校准电路及方法
TW201644198A (zh) 積體電路間通訊技術
CN118646614B (zh) 一种lin总线实时防数据传输冲突的方法及电路
EP1972058B1 (en) Serial data communication system and method
CN105048787A (zh) 一种针对多电平级联型高压变频器的光纤集成通信方法
CN108491286B (zh) 一种mcu芯片保护方法
CN101795137A (zh) 一种曼彻斯特码的波形调整方法
CN115833863A (zh) Tr组件保护逻辑电路、控制逻辑和收发控制系统
CN109639457A (zh) 一种jesd204b协议高速发送器单粒子错误率的测试系统及方法
TWI740564B (zh) 跨時鐘域信號傳輸方法、電路以及電子裝置
CN118473376A (zh) 超声波设备及其发射同步方法
US7679404B2 (en) Missing clock pulse detector
CN109857687B (zh) 量测系统及数据传输接口
CN112286841B (zh) 一种数据同步方法及寄存器
CN120768341B (zh) 带测试电路的低功耗异步握手电路
CN118092586B (zh) 星载分布式干涉sar定时信号时间同步的硬件实现方法
CN120768340B (zh) 低功耗异步握手电路和异步电路
CN221575326U (zh) 一种时钟纠错电路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21832884

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

ENP Entry into the national phase

Ref document number: 2021832884

Country of ref document: EP

Effective date: 20230130