WO2022005134A1 - Module d'alimentation - Google Patents

Module d'alimentation Download PDF

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Publication number
WO2022005134A1
WO2022005134A1 PCT/KR2021/008092 KR2021008092W WO2022005134A1 WO 2022005134 A1 WO2022005134 A1 WO 2022005134A1 KR 2021008092 W KR2021008092 W KR 2021008092W WO 2022005134 A1 WO2022005134 A1 WO 2022005134A1
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WO
WIPO (PCT)
Prior art keywords
electrode pattern
ceramic substrate
semiconductor chip
electrode
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/KR2021/008092
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English (en)
Korean (ko)
Inventor
박승곤
조태호
여인태
빈진혁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Amosense Co Ltd
Original Assignee
Amosense Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020200082275A external-priority patent/KR20220004437A/ko
Priority claimed from KR1020200082279A external-priority patent/KR20220004440A/ko
Application filed by Amosense Co Ltd filed Critical Amosense Co Ltd
Publication of WO2022005134A1 publication Critical patent/WO2022005134A1/fr
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/20—Conductive package substrates serving as an interconnection, e.g. metal plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/692—Ceramics or glasses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials

Definitions

  • the present invention relates to a power module, and more particularly, to a power module having improved performance by applying a high output power semiconductor chip.
  • the power module is used to supply high voltage current to drive motors such as hybrid vehicles and electric vehicles.
  • the double-sided cooling power module has a substrate on top and a bottom of a semiconductor chip, respectively, and a heat sink on the outer surface of the substrate.
  • the double-sided cooling power module has an excellent cooling performance compared to a single-sided cooling power module having a heat sink on one side, and thus its use is gradually increasing.
  • Double-sided cooling power modules used in electric vehicles, etc. have power semiconductor chips such as silicon carbide (SiC) and gallium nitride (GaN) mounted between the two substrates. It is important to satisfy both high strength and high heat dissipation characteristics at the same time.
  • SiC silicon carbide
  • GaN gallium nitride
  • An object of the present invention is to provide a power module that has high strength and high heat dissipation characteristics, has excellent bonding characteristics, can reduce a volume by minimizing a current path, and can improve efficiency and performance.
  • Another object of the present invention is to prevent the flow of the semiconductor chip during the bonding (bonding) process of bonding the semiconductor chip to the ceramic substrate and improve the bonding stability to improve the cause of defects caused by the flow of the semiconductor chip and increase the efficiency. is to provide
  • the power module of the present invention has a ceramic substrate, a first electrode pattern formed on the ceramic substrate, and a first electrode pattern formed on the ceramic substrate on the same plane as the first electrode pattern.
  • a semiconductor chip comprising a second electrode pattern spaced apart, a drain electrode disposed to connect the first electrode pattern and the second electrode pattern and joined to the first electrode pattern, and a source electrode joined to the second electrode pattern; and a solder layer bonding the drain electrode to the first electrode pattern and bonding the source electrode to the second electrode pattern.
  • the adhesive layer is made of a non-conductive adhesive.
  • the adhesive layer may be formed of a non-conductive heat dissipation adhesive.
  • the adhesive layer first fixes the semiconductor chip to the ceramic substrate before the melting temperature of the solder layer.
  • the solder mask formed on the first electrode pattern is in contact with one corner of the semiconductor chip, and the solder mask formed on the second electrode pattern is formed at a position in contact with the other corner of the semiconductor chip.
  • the semiconductor chip may further include a semiconductor chip including a source electrode bonded to the pattern, and a solder layer bonding the drain electrode to the second electrode pattern and bonding the source electrode to the third electrode pattern.
  • An adhesive layer disposed between the second electrode pattern and the third electrode pattern and bonding the semiconductor chip to the ceramic substrate may be included.
  • a solder mask formed on the second electrode pattern and the third electrode pattern and guiding a position where the semiconductor chip is bonded to the second electrode pattern and the third electrode pattern may be included.
  • the power module includes a ceramic substrate and a first electrode pattern formed on the ceramic substrate, a second electrode pattern formed on the ceramic substrate and spaced apart on the same plane as the first electrode pattern, the first electrode pattern and the second electrode pattern.
  • a semiconductor chip disposed to connect the two electrode patterns and including a drain electrode joined to the first electrode pattern and a source electrode joined to the second electrode pattern, and the drain electrode is joined to the first electrode pattern and the source electrode is connected to the second electrode
  • the solder mask includes a solder mask formed on the first electrode pattern and a solder mask formed on the second electrode pattern.
  • the solder mask formed on the first electrode pattern is formed at a position in contact with one edge of the semiconductor chip, and the solder mask formed on the second electrode pattern is formed at a position in contact with the other edge of the semiconductor chip.
  • the solder mask may be formed by printing a solder resist in a predetermined area other than the area where the drain electrode and the source electrode are joined in the first electrode pattern and the second electrode pattern.
  • the solder mask has a certain height.
  • the height of the solder mask is relatively low compared to the height of the semiconductor chip.
  • the length of the solder mask corresponds to the length of the drain electrode and the length of the source electrode.
  • a semiconductor chip including a source electrode bonded to the pattern, a solder layer bonding the drain electrode to the second electrode pattern and bonding the source electrode to the third electrode pattern, and the second electrode pattern and the third electrode formed on the ceramic substrate It further includes a solder mask for preventing the position movement of the semiconductor chip during melting of the solder layer for bonding the semiconductor chip to the electrode pattern.
  • the solder mask may be formed by printing a solder resist in a predetermined area other than the area where the drain electrode and the source electrode are joined in the second electrode pattern and the third electrode pattern.
  • the present invention has high strength and high heat dissipation characteristics, has excellent bonding characteristics, can reduce a volume by minimizing a current path, and is optimized for high-speed switching to improve efficiency and performance.
  • the semiconductor chip is mounted in the form of a flip chip on the upper ceramic substrate, wire bonding is omitted so that the inductance value can be as low as possible, thereby improving the heat dissipation performance.
  • the present invention includes an adhesive layer for first fixing the semiconductor chip (G) to the ceramic substrate of the upper ceramic substrate before the melting temperature of the solder layer.
  • heat dissipation efficiency when a non-conductive heat dissipation adhesive excellent for heat transfer is used as a material of the adhesive layer, heat dissipation efficiency can be increased.
  • the present invention forms a solder mask in a certain area out of the position where the drain terminal and the source terminal are joined, so that the solder When the layer is melted, the positional movement of the semiconductor chip can be prevented. Therefore, it is possible to improve the cause of defects such as a short or circuit open due to the flow of the conventional semiconductor chip, and furthermore, it is possible to prevent electrical loss through stable bonding of the semiconductor chip and improve the load to increase the switching efficiency. It works.
  • FIG. 1 is a perspective view of a power module according to an embodiment of the present invention.
  • FIG. 2 is an exploded perspective view of a power module according to an embodiment of the present invention.
  • FIG 3 is a side cross-sectional view of a power module according to an embodiment of the present invention.
  • FIG. 4 is a perspective view showing a housing according to an embodiment of the present invention.
  • FIG. 5 is a perspective view showing a lower ceramic substrate according to an embodiment of the present invention.
  • FIG. 6 is a view showing an upper surface and a lower surface of a lower ceramic substrate according to an embodiment of the present invention.
  • FIG. 7 is a perspective view showing an upper ceramic substrate according to an embodiment of the present invention.
  • FIG. 8 is a view showing an upper surface and a lower surface of an upper ceramic substrate according to an embodiment of the present invention.
  • FIG. 9 is a plan view of a PCB substrate according to an embodiment of the present invention.
  • FIG. 10 is a perspective view illustrating a state in which a connection pin is coupled to an upper ceramic substrate according to an embodiment of the present invention.
  • FIG. 11 is a view for explaining a method of connecting a semiconductor chip to an upper ceramic substrate according to another embodiment of the present invention.
  • FIG. 12 is a view showing a state in which a semiconductor chip is bonded to the upper ceramic substrate of FIG. 11 .
  • FIG. 13 is a cross-sectional view taken along line A-A of FIG. 12 .
  • solder layer 360 adhesive layer
  • bus bar G semiconductor chip (GaN chip)
  • FIG. 1 is a perspective view of a power module according to an embodiment of the present invention
  • FIG. 2 is an exploded perspective view of a power module according to an embodiment of the present invention.
  • the power module 10 is an electronic component in the form of a package formed by accommodating various components constituting the power module in a housing 100 .
  • the power module 10 is formed in such a way that a substrate and elements are disposed in the housing 100 to protect it.
  • the power module 10 may include a plurality of substrates and a plurality of semiconductor chips.
  • the power module 10 according to the embodiment includes a housing 100 , a lower ceramic substrate 200 , an upper ceramic substrate 300 , a PCB substrate 400 , and a heat sink 500 .
  • the housing 100 has an empty space opened vertically in the center, and the first terminal 610 and the second terminal 620 are positioned on both sides.
  • a heat sink 500, a lower ceramic substrate 200, an upper ceramic substrate 300, and a PCB substrate 400 are sequentially stacked at regular intervals in the top and bottom in an empty space in the center, and the first terminals on both sides
  • a support bolt 630 for connecting an external terminal to the 610 and the second terminal 620 is fastened.
  • the first terminal 610 and the second terminal 620 are used as input/output terminals of power.
  • a lower ceramic substrate 200 , an upper ceramic substrate 300 , and a PCB substrate 400 are sequentially accommodated in an empty space in the center of the housing 100 .
  • the heat sink 500 is disposed on the lower surface of the housing 100
  • the lower ceramic substrate 200 is attached to the upper surface of the heat sink 500
  • the upper ceramic substrate 300 is on the upper side of the lower ceramic substrate 200.
  • the PCB substrate 400 is arranged at a predetermined interval on the upper ceramic substrate 300 .
  • the state in which the PCB substrate 400 is disposed in the housing 100 is the guide grooves 401 and 402 formed to be recessed into the edge of the PCB substrate 400 and the guide ribs 101 formed in the housing 100 to correspond to the guide grooves 401 and 402 .
  • the locking jaw 102 may be fixed.
  • a plurality of guide grooves 401 and 402 are formed around the edge of the PCB substrate 400 according to the embodiment, and some of the guide grooves 401 are guided by the guide rib 101 formed on the inner surface of the housing 100 . and the guide groove 402 of the remaining part of them is hung through the locking protrusion 102 formed on the inner surface of the housing 100 .
  • the heat sink 500, the lower ceramic substrate 200, and the upper ceramic substrate 300 are accommodated in the empty space in the center of the housing 100, and the state in which the PCB substrate 400 is disposed on the upper surface is a fastening bolt ( (not shown) may be fixed.
  • a fastening bolt (not shown)
  • fixing the PCB substrate 400 to the housing 100 with a guide groove and a locking jaw structure reduces assembly time and simplifies the assembly process compared to the case of fixing with a fastening bolt.
  • the housing 100 has fastening holes 103 formed at four corners.
  • the fastening hole 103 communicates with the communication hole 501 formed in the heat sink 500 .
  • the fixing bolt 150 is fastened through the fastening hole 103 and the communication hole 501 , and the end of the fixing bolt 150 passing through the fastening hole 103 and the communication hole 501 is the heat sink 500 . It may be fastened to a fixing hole of a fixing jig to be disposed on the lower surface.
  • the bus bar 700 is connected to the first terminal 610 and the second terminal 620 .
  • the bus bar 700 connects the first terminal 610 and the second terminal 620 to the upper ceramic substrate 300 .
  • Three bus bars 700 are provided.
  • One of the bus bars 700 connects the + terminal of the first terminals 610 with the first electrode pattern a of the upper ceramic substrate 300 , and the other connects the - terminal among the first terminals 610 . It is connected to the three electrode pattern (c), and the other one connects the second terminal 620 to the second electrode pattern (b).
  • the first electrode pattern (a), the second electrode pattern (b), and the third electrode pattern (c) will be described later with reference to FIGS. 7 and 10 .
  • FIG 3 is a side cross-sectional view of a power module according to an embodiment of the present invention.
  • the power module 10 has a multilayer structure of a lower ceramic substrate 200 and an upper ceramic substrate 300 , and a semiconductor chip between the lower ceramic substrate 200 and the upper ceramic substrate 300 .
  • the semiconductor chip (G) is any one of GaN (Gallium Nitride) chip, MOSFET (Metal Oxide Semiconductor Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), JFET (Junction Field Effect Transistor), HEMT (High Electric Mobility Transistor) However, preferably, the semiconductor chip (G) uses a GaN chip.
  • the GaN (Gallium Nitride) chip is a semiconductor chip that functions as a high-power (300A) switch and a high-speed ( ⁇ 1MHz) switch.
  • the GaN chip has the advantage of being stronger in heat than the existing silicon-based semiconductor chip and reducing the size of the chip.
  • the lower ceramic substrate 200 and the upper ceramic substrate 300 are formed of a ceramic substrate including a metal layer brazed to at least one surface of the ceramic substrate and the ceramic substrate to increase the heat dissipation efficiency of the heat generated from the semiconductor chip (G). do.
  • the ceramic substrate may be, for example, any one of alumina (Al 2 O 3 ), AlN, SiN, and Si 3 N 4 .
  • the metal layer is formed of an electrode pattern for mounting a semiconductor chip (G) and an electrode pattern for mounting a driving element, respectively, with a metal foil brazed on a ceramic substrate.
  • the metal layer is formed as an electrode pattern in a region where a semiconductor chip or peripheral components are to be mounted.
  • the metal foil may be an aluminum foil or a copper foil as an example.
  • the metal foil is fired at 780° C. to 1100° C. on a ceramic substrate and brazed to the ceramic substrate.
  • Such a ceramic substrate is called an AMB substrate.
  • AMB substrate As an example, a DBC substrate, a TPC substrate, and a DBA substrate may be applied. However, in terms of durability and heat dissipation efficiency, AMB substrates are most suitable. For the above reasons, the lower ceramic substrate 200 and the upper ceramic substrate 300 are AMB substrates as an example.
  • the PCB substrate 400 is disposed on the upper ceramic substrate 300 . That is, the power module 10 has a three-layer structure of a lower ceramic substrate 200 , an upper ceramic substrate 300 , and a PCB substrate 400 .
  • the semiconductor chip (G) for high power control is disposed between the upper ceramic substrate 200 and the lower ceramic substrate 300 to increase heat dissipation efficiency, and the PCB substrate 400 for low power control is disposed on the uppermost part of the semiconductor Prevents damage to the PCB substrate 400 due to heat generated from the chip (G).
  • the lower ceramic substrate 200 , the upper ceramic substrate 300 , and the PCB substrate 400 may be connected or fixed with pins.
  • the heat sink 500 is disposed under the lower ceramic substrate 200 .
  • the heat sink 500 is for dissipating heat generated in the semiconductor chip (G).
  • the heat sink 500 is formed in the shape of a square plate having a predetermined thickness.
  • the heat sink 500 has an area corresponding to the housing 100 and may be formed of copper or aluminum to increase heat dissipation efficiency.
  • FIG. 4 is a perspective view showing a housing according to an embodiment of the present invention.
  • an empty space is formed in the center of the housing 100 , and a first terminal 610 and a second terminal 620 are positioned at both ends.
  • the housing 100 may be formed by an insert injection method such that the first terminal 610 and the second terminal 620 are integrally fixed at both ends.
  • the housing 100 has fastening holes 103 formed at four corners.
  • the fastening hole 103 communicates with the communication hole 501 formed in the heat sink 500 .
  • a support hole 104 is formed in the first terminal 610 and the second terminal 620 .
  • a support bolt 630 for connecting the first terminal 610 and the second terminal 620 to an external terminal such as a motor is fastened to the support hole 104 (see FIG. 10 ).
  • the housing 100 is formed of a heat insulating material.
  • the housing 100 may be formed of a heat insulating material so that heat generated from the semiconductor chip G is not transferred to the PCB substrate 400 above the housing 100 through the housing 100 .
  • the housing 100 may be made of a heat-dissipating plastic material.
  • the housing 100 may be made of a heat-dissipating plastic material so that heat generated from the semiconductor chip G can be radiated to the outside through the housing 100 .
  • the housing 100 may be formed of engineering plastic.
  • Engineering plastics have high heat resistance, excellent strength, chemical resistance, and abrasion resistance, and can be used for a long time at 150°C or higher.
  • the engineering plastic may be made of one of polyamide, polycarbonate, polyester, and modified polyphenylene oxide.
  • the semiconductor chip (G) operates repeatedly as a switch, which causes the housing 100 to be stressed by high temperature and temperature changes. It also has excellent heat dissipation properties.
  • the housing 100 may be manufactured by insert-injecting a terminal made of aluminum or copper to an engineering plastic material.
  • the housing 100 made of an engineering plastic material spreads heat and radiates heat to the outside.
  • the housing 100 may be made of a high heat dissipation engineering plastic that may have higher thermal conductivity than a general engineering plastic material and is lightweight compared to aluminum by filling the resin with a high thermal conductivity filler.
  • the housing 100 may have heat dissipation properties by applying a graphene heat dissipation coating material to the inside and outside of an engineering plastic or high-strength plastic material.
  • FIG. 5 is a perspective view showing a lower ceramic substrate according to an embodiment of the present invention.
  • the lower ceramic substrate 200 is attached to the upper surface of the heat sink 500 .
  • the lower ceramic substrate 200 is disposed between the semiconductor chip G and the heat sink 500 .
  • the lower ceramic substrate 200 transfers heat generated from the semiconductor chip G to the heat sink 500 and insulates between the semiconductor chip G and the heat sink 500 to prevent a short circuit.
  • the lower ceramic substrate 200 may be soldered to the upper surface of the heat sink 500 .
  • the heat sink 500 is formed in an area corresponding to the housing 100 and may be formed of a copper material to increase heat dissipation efficiency.
  • As the solder for soldering joint SnAg, SnAgCu, etc. may be used.
  • FIG. 6 is a view showing an upper surface and a lower surface of a lower ceramic substrate according to an embodiment of the present invention.
  • the lower ceramic substrate 200 includes a ceramic substrate 201 and metal layers 202 and 203 brazed to upper and lower surfaces of the ceramic substrate 201 .
  • the thickness of the ceramic substrate 201 may be 0.68 t
  • the thickness of the metal layers 202 and 203 formed on the upper and lower surfaces of the ceramic substrate 201 may be 0.8 t.
  • the metal layer 202 of the upper surface 200a of the lower ceramic substrate 200 may be an electrode pattern on which a driving element is mounted.
  • the driving device mounted on the lower ceramic substrate 200 may be an NTC temperature sensor 210 .
  • the NTC temperature sensor 210 is mounted on the upper surface of the lower ceramic substrate 200 .
  • the NTC temperature sensor 210 is to provide temperature information in the power module due to the heat of the semiconductor chip G.
  • the metal layer 203 of the lower surface 200b of the lower ceramic substrate 200 may be formed on the entire lower surface of the lower ceramic substrate 200 to facilitate heat transfer to the heat sink 500 .
  • An insulating spacer 220 is bonded to the lower ceramic substrate 200 .
  • the insulating spacer 220 is bonded to the upper surface of the lower ceramic substrate 200 and defines a separation distance between the lower ceramic substrate 200 and the upper ceramic substrate 300 .
  • the insulating spacer 220 defines the separation distance between the lower ceramic substrate 200 and the upper ceramic substrate 300 to increase the heat dissipation efficiency of the heat generated by the semiconductor chip (G) mounted on the lower surface of the upper ceramic substrate 300, Interference between the semiconductor chips G is prevented to prevent an electric shock such as a short circuit.
  • a plurality of insulating spacers 220 are bonded to each other at predetermined intervals around the upper surface edge of the lower ceramic substrate 200 .
  • a gap between the insulating spacers 220 is used as a space to increase heat dissipation efficiency.
  • the insulating spacers 220 are disposed around the edges with respect to the lower ceramic substrate 200 , and for example, eight insulating spacers 220 are disposed at regular intervals.
  • the insulating spacer 220 is integrally bonded to the lower ceramic substrate 200 .
  • the insulating spacer 220 may be applied to check alignment when the upper ceramic substrate 300 is disposed on the lower ceramic substrate 200 .
  • the insulating spacer 220 is formed on the upper ceramic substrate 300 .
  • the insulating spacer 220 supports the lower ceramic substrate 200 and the upper ceramic substrate 300 , thereby contributing to preventing bending of the lower ceramic substrate 200 and the upper ceramic substrate 300 .
  • the insulating spacer 220 may be formed of a ceramic material for insulation between the chip mounted on the lower ceramic substrate 200 and the chip and the component mounted on the upper ceramic substrate 300 .
  • the insulating spacer may be formed of one selected from Al 2 O 3 , ZTA, Si 3 N 4 , and AlN, or an alloy in which two or more thereof are mixed.
  • Al 2 O 3 , ZTA, Si 3 N 4 , and AlN are insulating materials having excellent mechanical strength and heat resistance.
  • the insulating spacer 220 is brazed to the lower ceramic substrate 200 .
  • the substrate may be damaged due to thermal and mechanical shock during soldering or pressurization firing, so that the insulating spacer 220 is bonded by brazing.
  • a brazing bonding layer including an AgCu layer and a Ti layer may be used for the brazing bonding. Heat treatment for brazing can be performed at 780°C to 900°C.
  • the insulating spacer 220 is integrally formed with the metal layer 202 of the lower ceramic substrate 200 .
  • the thickness of the brazing bonding layer is 0.005 mm to 0.08 mm, which is thin enough not to affect the height of the insulating spacer, and the bonding strength is high.
  • An interconnection spacer 230 is installed between the lower ceramic substrate 200 and the upper ceramic substrate 300 .
  • the interconnection spacer 230 may perform electrical connection between electrode patterns in place of connection pins in a substrate having an upper and lower multilayer structure.
  • the interconnection spacer 230 may directly connect between substrates while preventing electrical loss and short circuit, increase bonding strength, and improve electrical characteristics.
  • One end of the interconnection spacer 230 may be bonded to the electrode pattern of the lower ceramic substrate 200 by a brazing bonding method.
  • the other end of the interconnection spacer 230 may be bonded to the electrode pattern of the upper ceramic substrate 300 by a brazing bonding method or a soldering bonding method.
  • the interconnection spacer 230 may be Cu or a Cu+CuMo alloy.
  • FIG. 7 is a perspective view showing an upper ceramic substrate according to an embodiment of the present invention
  • FIG. 8 is a view showing an upper surface and a lower surface of the upper ceramic substrate according to an embodiment of the present invention.
  • the upper ceramic substrate 300 is disposed on the lower ceramic substrate 200 .
  • the upper ceramic substrate 300 is an intermediate substrate having a stacked structure.
  • the upper ceramic substrate 300 has a semiconductor chip (G) mounted on its lower surface, and constitutes a high-side circuit and a low-side circuit for high-speed switching.
  • G semiconductor chip
  • the upper ceramic substrate 300 includes a ceramic substrate 301 and metal layers 302 and 303 brazed to upper and lower surfaces of the ceramic substrate 301 .
  • the thickness of the ceramic substrate is 0.38 t
  • the thickness of the electrode pattern on the upper surface 300a and the lower surface 300b of the ceramic substrate is 0.3 t as an example.
  • the ceramic substrate must have the same pattern thickness on the upper and lower surfaces to prevent distortion during brazing.
  • the electrode pattern formed by the metal layer 302 on the upper surface of the upper ceramic substrate 300 is divided into a first electrode pattern (a), a second electrode pattern (b), and a third electrode pattern (c).
  • the electrode pattern formed by the metal layer 303 on the lower surface of the upper ceramic substrate 300 corresponds to the electrode pattern formed by the metal layer 302 on the upper surface of the upper ceramic substrate 300 .
  • the division of the electrode pattern on the upper surface of the upper ceramic substrate 300 into a first electrode pattern (a), a second electrode pattern (b), and a third electrode pattern (c) is a high-side circuit for high-speed switching. and to separate the low-side circuit.
  • the semiconductor chip G is provided in the form of a flip chip by an adhesive layer such as solder and silver paste on the lower surface 300b of the upper ceramic substrate 300 .
  • an adhesive layer such as solder and silver paste
  • two semiconductor chips G may be connected in parallel for high-speed switching.
  • Two semiconductor chips (G) are disposed at positions connecting the first electrode pattern (a) and the second electrode pattern (b) among the electrode patterns of the upper ceramic substrate 300 , and the other two are the second electrode patterns (b) ) and the third electrode pattern (c) are arranged in parallel at a position connecting it.
  • the capacity of one semiconductor chip G is 150A. Therefore, two semiconductor chips (G) are connected in parallel so that the capacity becomes 300A.
  • the semiconductor chip G is a GaN chip.
  • the purpose of the power module using the semiconductor chip G is high-speed switching.
  • the gate terminal and the source terminal of the semiconductor chip G may be disposed such that the connection pin is connected to the center between the semiconductor chip G and the semiconductor chip G. If the gate terminal and the source terminal do not keep the same distance or the length of the pattern is different, a problem occurs.
  • the gate terminal is a terminal for turning on/off the semiconductor chip G by using a low voltage.
  • the gate terminal may be connected to the PCB board 400 through a connection pin.
  • the Source terminal is a terminal for high current to enter and exit.
  • the semiconductor chip G includes a drain terminal, and the source terminal and the drain terminal are divided into N-type and P-type to change the direction of the current.
  • the source terminal and the drain terminal are responsible for input and output of current through the first electrode pattern (a), the second electrode pattern (b), and the third electrode pattern (c), which are electrode patterns for mounting the semiconductor chip (G).
  • the source terminal and the drain terminal are connected to the first terminal 610 and the second terminal 620 of FIG. 1 in charge of input and output of power.
  • the first terminal 610 shown in FIG. 1 includes a + terminal and a - terminal, and power flowing from the first terminal 610 to the + terminal is the upper part shown in FIG. 8 .
  • the semiconductor chip (G) and the second electrode pattern (b) disposed between the first electrode pattern (a) and the second electrode pattern (b) 2 is output to the terminal 620 .
  • the power supplied to the second terminal 620 shown in FIG. 1 is disposed between the second electrode pattern (b), the second electrode pattern (b) and the third electrode pattern (c) shown in FIG. 8 . It is output to the - terminal of the first terminal 610 through the semiconductor chip G and the third electrode pattern c.
  • a cutting part 310 may be formed in a portion of the upper ceramic substrate 300 corresponding to the NTC temperature sensor 210 .
  • An NTC temperature sensor 210 is mounted on the upper surface of the lower ceramic substrate 200 .
  • the NTC temperature sensor 210 is to provide temperature information in the power module due to the heat of the semiconductor chip G.
  • the thickness of the NTC temperature sensor 210 is thicker than the gap between the lower ceramic substrate 200 and the upper ceramic substrate 300 , interference between the NTC temperature sensor 210 and the upper ceramic substrate 300 occurs.
  • the upper ceramic substrate 300 of the portion that interferes with the NTC temperature sensor 210 is cut to form a cutting portion 310 .
  • a silicone liquid or epoxy for molding may be injected into the space between the upper ceramic substrate 300 and the lower ceramic substrate 200 through the cutting part 310 .
  • silicone liquid or epoxy In order to insulate between the upper ceramic substrate 300 and the lower ceramic substrate 200, silicone liquid or epoxy must be injected.
  • one side of the upper ceramic substrate 300 may be cut to form a cutting part 310, and the cutting part 310 may be formed. is formed at a position corresponding to the NTC temperature sensor 210 to prevent interference between the upper ceramic substrate 300 and the NTC temperature sensor 210 .
  • Silicon liquid or epoxy is used in the space between the lower ceramic substrate 200 and the upper ceramic substrate 300 and the upper ceramic substrate 300 and the PCB substrate 400 for the purpose of protecting the semiconductor chip (G), alleviating vibration, and insulating. You can fill in the space between them.
  • a through hole 320 is formed in the upper ceramic substrate 300 .
  • the through hole 320 connects the semiconductor chip G mounted on the upper ceramic substrate 300 to the driving device mounted on the PCB substrate 400 in the shortest distance in the upper and lower multi-layered substrate structure, and the lower ceramic substrate 200 . This is to connect the NTC temperature sensor 210 mounted to the PCB board 400 to the driving device mounted on the shortest distance.
  • Eight through-holes 320 are formed at a position where the semiconductor chip is installed, and two are installed at a position where the NTC temperature sensor is installed, so that a total of 10 can be formed.
  • a plurality of through-holes 320 may be formed in the portion where the first electrode pattern (a) and the third electrode pattern (c) are formed in the upper ceramic substrate 300 .
  • the plurality of through-holes 320 formed in the first electrode pattern (a) allow the current flowing into the first electrode pattern (a) of the upper surface of the upper ceramic substrate 300 to be formed on the lower surface of the upper ceramic substrate 300 . It moves to the electrode pattern (a) and flows into the semiconductor chip (G). In the plurality of through holes 320 formed in the third electrode pattern c, the current flowing into the semiconductor chip G passes through the third electrode pattern c of the lower surface of the upper ceramic substrate 300 to the upper ceramic substrate 300 . ) to move to the third electrode pattern (c) on the upper surface.
  • the through hole 320 may have a diameter of 0.5 mm to 5.0 mm.
  • a connection pin is installed in the through hole 320 to be connected to the electrode pattern of the PCB substrate, and may be connected to the driving device mounted on the PCB substrate 400 through this.
  • the connection between the electrode patterns through the through-holes 320 and the connection pins installed in the through-holes 320 in the upper and lower multi-layered substrate structure eliminates various output losses through the shortest distance connection, thereby improving the constraints according to the size of the power module. can contribute
  • a plurality of via holes 330 may be formed in the electrode pattern of the upper ceramic substrate 300 .
  • the via hole 330 may be processed by at least 50% of the substrate area.
  • the area of the via hole 330 described above has been described as an example in which at least 50% of the substrate area is applied, but is not limited thereto, and may be processed to 50% or less.
  • 152 via holes may be formed in the first electrode pattern (a)
  • 207 via holes may be formed in the second electrode pattern (b)
  • 154 via holes may be formed in the third electrode pattern (c).
  • the plurality of via holes 330 formed in each electrode pattern are for conducting a large current and distributing a large current.
  • the via hole 330 is filled with a conductive material.
  • the conductive material may be Ag or an Ag alloy.
  • the Ag alloy may be an Ag-Pd paste.
  • the conductive material filled in the via hole 330 electrically connects the electrode pattern on the upper surface and the electrode pattern on the lower surface of the upper ceramic substrate 300 .
  • the via hole 330 may be formed by laser processing. The via hole 330 can be seen in the enlarged view of FIG. 8 .
  • FIG. 9 is a plan view of a PCB substrate according to an embodiment of the present invention.
  • the PCB substrate 400 switches the semiconductor chip G or uses the information sensed by the NTC temperature sensor (reference numeral 210 in FIG. 7 ) to switch the GaN chip (semiconductor chip).
  • the driving element is mounted.
  • the driving device includes a Gate Drive IC.
  • the capacitor 410 is mounted on the PCB substrate 400 .
  • the capacitor 410 includes a semiconductor chip G disposed to connect the first electrode pattern a and the second electrode pattern b of the upper ceramic substrate 300 and the second electrode pattern (G) of the upper ceramic substrate 300 . It is mounted on the upper surface of the PCB substrate 400 at a position corresponding to a position between the semiconductor chip G disposed to connect b) and the third electrode pattern c.
  • the gate drive IC circuit includes a high side gate drive IC and a low side gate drive IC.
  • FIG. 10 is a perspective view illustrating a state in which a connection pin is coupled to an upper ceramic substrate according to an embodiment of the present invention.
  • connection pin 800 is inserted into a through hole (reference numeral 320 in FIG. 7 ) formed at a position adjacent to the semiconductor chip G in the upper ceramic substrate 300 .
  • the connection pin 800 fitted into the through hole 320 formed at a position adjacent to the semiconductor chip G is inserted into the through hole 420 formed at a position corresponding to the PCB substrate (reference numeral 400 in FIG. 9 ) to insert the semiconductor chip G ) may be connected to a gate terminal for mounting the electrode pattern of the PCB substrate 400 .
  • connection pin 800 is inserted into the through hole 320 formed at a position adjacent to the NTC temperature sensor 210 in the upper ceramic substrate 300 .
  • the connection pin 800 fitted into the through hole 320 formed at a position adjacent to the NTC temperature sensor 210 is inserted into the through hole 420 formed at a position corresponding to the PCB substrate 400 to the NTC temperature sensor 210 .
  • the terminal and the electrode pattern of the PCB substrate 400 may be connected.
  • connection pin 800 is fitted into the plurality of through holes 320 formed in a line in the first electrode pattern (a) and the third electrode pattern (c) in the upper ceramic substrate 300 .
  • the connecting pins 800 fitted into the plurality of through holes 320 formed in the first electrode pattern (a) and the third electrode pattern (c) are inserted into the through holes 420 formed at positions corresponding to the PCB substrate 400 .
  • the semiconductor chip G may be connected to the capacitor 410 of the PCB substrate 400 .
  • connection pin 800 connects the semiconductor chip G mounted on the upper ceramic substrate 300 to the driving device mounted on the PCB substrate 400 with the shortest distance, thereby eliminating various output losses and enabling high-speed switching.
  • FIG. 11 is a view for explaining a method of connecting a semiconductor chip to an upper ceramic substrate according to another embodiment of the present invention.
  • FIG. 11 is an enlarged view of a part of FIG. 8 and is different from FIG. 8 in that an adhesive layer and a solder mask are further formed.
  • the semiconductor chip G used in the power module includes a drain electrode, a source electrode, and a gate electrode.
  • the semiconductor chip G is bonded to the upper ceramic substrate 300 by solder bonding. Solder bonding improves load and electrical losses due to resistance on the power delivery path by shortening the power delivery path.
  • a first electrode pattern (a), a second electrode pattern (b), and a third electrode pattern (c) are formed on the upper and lower surfaces of the upper ceramic substrate 300 .
  • the first electrode pattern (a), the second electrode pattern (b), and the third electrode pattern (c) are metal layers 302 and 303 brazed to the upper and lower surfaces of the ceramic substrate 301 .
  • the second electrode pattern (b) is spaced apart from the first electrode pattern (a) on the same plane
  • the third electrode pattern (c) is on the same plane as the second electrode pattern (b). are spaced apart on
  • two semiconductor chips G are bonded to the lower surface of the upper ceramic substrate 300 so as to connect the first electrode pattern a and the second electrode pattern b in parallel, and the second electrode pattern ( The two semiconductor chips G are joined to connect b) and the third electrode pattern c in parallel.
  • Two semiconductor chips G bonded to the upper ceramic substrate 300 to connect the first electrode pattern a and the second electrode pattern b constitute a high side circuit, and the second electrode pattern
  • the semiconductor chip G bonded to the upper ceramic substrate 300 to connect (b) and the third electrode pattern (c) constitutes a low side circuit.
  • a gate terminal and a source terminal are disposed between the first electrode pattern (a) and the second electrode pattern (b).
  • the gate terminal is connected to the gate electrode of the semiconductor chip G
  • the source ) terminal is connected to the source electrode of the semiconductor chip (G).
  • the gate terminal and the source terminal are arranged side by side two by two and are respectively connected to the second electrode patterns (b) on both sides with the same length. This is to increase the reliability of high-speed switching by transmitting a signal at the same speed to the two semiconductor chips G arranged in parallel on both sides.
  • FIG. 12 is a view illustrating a state in which a semiconductor chip is bonded to the upper ceramic substrate of FIG. 11
  • FIG. 13 is a cross-sectional view taken along line A-A of FIG. 12 .
  • the semiconductor chip G is bonded to the lower surface of the upper ceramic substrate 300 to connect the first electrode pattern a and the second electrode pattern b.
  • a drain electrode is soldered to the first electrode pattern (a)
  • a source electrode is soldered to the second electrode pattern (b)
  • a gate electrode is a gate (Gate). ) to the terminals by soldering joints.
  • solder layer 350 bonding the drain electrode to the first electrode pattern (a) and bonding the source electrode to the second electrode pattern (b).
  • the solder layer 350 is made of a conductive adhesive, and for example, SnAg or SnAgCu may be used.
  • the solder layer 350 connects the semiconductor chip G to the first electrode pattern a and the second electrode pattern b in the form of a flip chip.
  • An adhesive layer 360 is disposed between the first electrode pattern (a) and the second electrode pattern (b).
  • the adhesive layer 360 serves to temporarily bond the semiconductor chip G disposed to connect the first electrode pattern a and the second electrode pattern b to the upper ceramic substrate 300 . That is, the adhesive layer 360 temporarily bonds the semiconductor chip G to the ceramic substrate 301 between the first electrode pattern a and the second electrode pattern b.
  • the adhesive layer 360 first fixes the semiconductor chip G to the ceramic substrate 301 of the upper ceramic substrate 300 before the melting temperature of the solder layer 350, and when the solder layer 350 for soldering bonding is melted The position movement of the semiconductor chip G is prevented.
  • the adhesive layer 360 serves as a temporary wall between the solder layer 350 bonding the drain electrode to the first electrode pattern (a) and the solder layer 350 bonding the source electrode to the second electrode pattern (b).
  • the two solder layers 350 overflow and are prevented from being connected to each other during soldering.
  • a short or circuit is opened. (Open) circuit coupling occurs.
  • the adhesive layer 360 has a length corresponding to the horizontal width of the semiconductor chip G or more so that the solder layer 350 is not connected to each other between the first electrode pattern (a) and the second electrode pattern (b). can be formed.
  • the adhesive layer 360 is made of a non-conductive adhesive.
  • the adhesive layer 360 is a non-conductive adhesive for insulation between the solder layer 350 bonding the drain electrode to the first electrode pattern (a) and the solder layer 350 bonding the source electrode to the second electrode pattern (b). is made of
  • the adhesive layer 360 may be formed of a non-conductive heat dissipation adhesive having an excellent effect on heat transfer.
  • the adhesive layer 360 is made of a non-conductive heat dissipation adhesive, it is possible to prevent the flow of the semiconductor chip G during soldering as well as the adhesive layer 360 rapidly transfers heat generated from the semiconductor chip to the upper ceramic substrate 300 . It is possible to increase the heat dissipation efficiency.
  • non-conductive adhesive examples include NCP and epoxy
  • non-conductive heat-dissipating adhesive examples include NCP, epoxy, and the like
  • heat dissipation efficiency is increased by adding thermal conductive fillers such as fine alumina, ceramic powder, carbon, and the like.
  • a solder mask 370 is formed on the first electrode pattern (a) and the second electrode pattern (b).
  • the solder mask 370 guides a position where the semiconductor chip G is joined to be connected to the first electrode pattern a and the second electrode pattern b.
  • the solder mask 370 may be formed by printing a solder resister on the first electrode pattern (a) and the second electrode pattern (b).
  • the solder mask 370 is formed by printing a solder resist on a predetermined area other than the area where the drain electrode and the source electrode are joined.
  • the solder mask 370 may be a thermosetting solder resist that is cured at 100° C. or less.
  • the solder mask 370 formed on the first electrode pattern (a) is in contact with one edge of the semiconductor chip (G) disposed to connect the first electrode pattern (a) and the second electrode pattern (b) and the second electrode pattern
  • the solder mask 370 formed in (b) is positioned so as to be in contact with the other edge of the semiconductor chip (G).
  • the solder mask 370 serves to support both edges of the semiconductor chip G when the solder layer 350 for soldering bonding is melted to prevent the semiconductor chip G from moving.
  • the solder mask 370 preferably has a predetermined height to support both edges of the semiconductor chip G to prevent positional movement. Furthermore, the height of the solder mask 370 is preferably relatively low compared to the height of the semiconductor chip G.
  • the length of the solder mask 370 preferably corresponds to the length of the drain electrode and the length of the source electrode.
  • the solder mask 370 may serve to guide the formation of the solder layer 350 at a position where the drain electrode and the source electrode of the semiconductor chip G are to be joined.
  • the solder mask 370 allows the semiconductor chip G to be stably bonded to the position where the first electrode pattern a and the second electrode pattern b are connected, thereby causing circuit defects such as short circuit or circuit open. In addition to preventing electrical loss, it also improves switching efficiency by improving electrical losses and loads.
  • the solder layer 350 bonds the drain electrode to the first electrode pattern (a) and the source electrode to the second electrode pattern (b).
  • the adhesive layer 360 is disposed between the first electrode pattern (a) and the second electrode pattern (b) to form the semiconductor chip (G) between the first electrode pattern (a) and the second electrode pattern (b). It is fixed to the ceramic substrate 301 which is an insulating material.
  • the adhesive layer 360 first fixes the semiconductor chip G to the ceramic substrate 301 of the upper ceramic substrate 300 before the melting temperature of the solder layer 350, and when the solder layer 350 for soldering bonding is melted The position movement of the semiconductor chip G is prevented.
  • the adhesive layer 360 serves as a temporary wall between the solder layer 350 bonding the drain electrode to the first electrode pattern (a) and the solder layer 350 bonding the source electrode to the second electrode pattern (b). This prevents the two solder layers 350 on both sides from being connected to each other.
  • the solder mask 370 is formed on the first electrode pattern (a) and the second electrode pattern (b), respectively, so that the semiconductor chip (G) is bonded to the first electrode pattern (a) and the second electrode pattern (b). It guides the position and prevents the position movement of the semiconductor chip G by supporting both edges of the semiconductor chip G when the solder layer 350 for soldering bonding is melted.
  • the semiconductor chip G is bonded to the lower surface of the upper ceramic substrate 300 to connect the second electrode pattern b and the third electrode pattern c.
  • a drain electrode is soldered to the second electrode pattern (b)
  • a source electrode is soldered to the third electrode pattern (c)
  • a gate electrode is a gate (Gate). ) to the terminals by soldering joints.
  • an adhesive layer 360 for temporarily bonding the semiconductor chip G to the upper ceramic substrate 300 is disposed between the second electrode pattern b and the third electrode pattern c.
  • a solder mask 370 is formed on the second electrode pattern (b) and the third electrode pattern (c).
  • the adhesive layer 360 disposed between the second electrode pattern (b) and the third electrode pattern (c) and the solder mask 370 formed on the second electrode pattern (b) and the third electrode pattern (c) are The adhesive layer 360 disposed between the first electrode pattern (a) and the second electrode pattern (b), the solder mask 370 formed on the first electrode pattern (a) and the second electrode pattern (b), and the material thereof , configuration and role are the same, so the overlapping description will be omitted.
  • both the adhesive layer 360 and the solder mask 370 are formed on the upper ceramic substrate 300 to prevent flow when the semiconductor chip G is bonded to the upper ceramic substrate 300 as an example.
  • only one of the adhesive layer 360 and the solder mask 370 may be formed.
  • the bonding layer first fixes the semiconductor chip to prevent the position movement of the semiconductor chip, and when the solder layer is melted, the solder mask supports the edge of the semiconductor chip to prevent the solder from moving. Since movement of the semiconductor chip due to flow is prevented, the semiconductor chip can be stably bonded to the upper ceramic substrate.

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

La présente invention se rapporte à un module d'alimentation comprenant : un substrat céramique supérieur (300) ; un premier motif d'électrode (a) formé sur le substrat céramique supérieur (300) ; un second motif d'électrode (b) formé sur le substrat céramique supérieur (300), le second motif d'électrode (b) étant disposé à distance du premier motif d'électrode (a) et sur le même plan que ce dernier ; une puce semi-conductrice (G) disposée de façon à connecter le premier motif d'électrode (a) et le second motif d'électrode (b) et comprenant une électrode drain reliée au premier motif d'électrode (a) et une électrode source reliée au second motif d'électrode (b) ; et une couche de soudure (350) reliant l'électrode drain au premier motif d'électrode (a) et reliant l'électrode source au second motif d'électrode (b). La présente invention présente l'avantage d'empêcher le déplacement de la position de la puce semi-conductrice lorsqu'elle est reliée au substrat céramique supérieur, ce qui permet une liaison stable au substrat céramique supérieur.
PCT/KR2021/008092 2020-07-03 2021-06-28 Module d'alimentation Ceased WO2022005134A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR1020200082275A KR20220004437A (ko) 2020-07-03 2020-07-03 파워모듈
KR1020200082279A KR20220004440A (ko) 2020-07-03 2020-07-03 파워모듈
KR10-2020-0082279 2020-07-03
KR10-2020-0082275 2020-07-03

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WO2022005134A1 true WO2022005134A1 (fr) 2022-01-06

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PCT/KR2021/008092 Ceased WO2022005134A1 (fr) 2020-07-03 2021-06-28 Module d'alimentation

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CZ310213B6 (cs) * 2023-01-31 2024-11-27 Západočeská Univerzita V Plzni Výkonový modul pro polovodičový jistič

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KR100852766B1 (ko) * 2005-12-21 2008-08-18 인터내쇼널 렉티파이어 코포레이션 고 파워 밀도 디바이스를 위한 패키지
WO2014030867A1 (fr) * 2012-08-23 2014-02-27 Cho Hyoyoung Procédé de formation de réserve de soudure de carte à circuit imprimé et carte à circuit imprimé fabriquée par ledit procédé
KR20140142256A (ko) * 2012-03-30 2014-12-11 미쓰비시 마테리알 가부시키가이샤 히트 싱크 장착 파워 모듈용 기판, 냉각기 장착 파워 모듈용 기판 및 파워 모듈
KR20190016007A (ko) * 2017-08-07 2019-02-15 크루셜텍 (주) 커버부를 가진 방수 지문 센서 모듈

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KR20060044927A (ko) * 2004-03-30 2006-05-16 샤프 가부시키가이샤 반도체 장치 및 그 제조 방법 및 상기 반도체 장치를이용한 반도체 모듈 장치, 및 상기 반도체 장치에 이용되는배선 기판
KR100852766B1 (ko) * 2005-12-21 2008-08-18 인터내쇼널 렉티파이어 코포레이션 고 파워 밀도 디바이스를 위한 패키지
KR20140142256A (ko) * 2012-03-30 2014-12-11 미쓰비시 마테리알 가부시키가이샤 히트 싱크 장착 파워 모듈용 기판, 냉각기 장착 파워 모듈용 기판 및 파워 모듈
WO2014030867A1 (fr) * 2012-08-23 2014-02-27 Cho Hyoyoung Procédé de formation de réserve de soudure de carte à circuit imprimé et carte à circuit imprimé fabriquée par ledit procédé
KR20190016007A (ko) * 2017-08-07 2019-02-15 크루셜텍 (주) 커버부를 가진 방수 지문 센서 모듈

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CZ310213B6 (cs) * 2023-01-31 2024-11-27 Západočeská Univerzita V Plzni Výkonový modul pro polovodičový jistič

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